[mirror_ubuntu-artful-kernel.git] / drivers / net / mlx4 / eq.c

/*
 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *	- Redistributions of source code must retain the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer.
 *
 *	- Redistributions in binary form must reproduce the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer in the documentation and/or other materials
 *	  provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>

#include <linux/mlx4/cmd.h>

#include "mlx4.h"
#include "fw.h"

enum {
	MLX4_IRQNAME_SIZE	= 64
};

enum {
	MLX4_NUM_ASYNC_EQE	= 0x100,
	MLX4_NUM_SPARE_EQE	= 0x80,
	MLX4_EQ_ENTRY_SIZE	= 0x20
};

/*
 * Must be packed because start is 64 bits but only aligned to 32 bits.
 */
struct mlx4_eq_context {
	__be32			flags;
	u16			reserved1[3];
	__be16			page_offset;
	u8			log_eq_size;
	u8			reserved2[4];
	u8			eq_period;
	u8			reserved3;
	u8			eq_max_count;
	u8			reserved4[3];
	u8			intr;
	u8			log_page_size;
	u8			reserved5[2];
	u8			mtt_base_addr_h;
	__be32			mtt_base_addr_l;
	u32			reserved6[2];
	__be32			consumer_index;
	__be32			producer_index;
	u32			reserved7[4];
};

#define MLX4_EQ_STATUS_OK	   ( 0 << 28)
#define MLX4_EQ_STATUS_WRITE_FAIL  (10 << 28)
#define MLX4_EQ_OWNER_SW	   ( 0 << 24)
#define MLX4_EQ_OWNER_HW	   ( 1 << 24)
#define MLX4_EQ_FLAG_EC		   ( 1 << 18)
#define MLX4_EQ_FLAG_OI		   ( 1 << 17)
#define MLX4_EQ_STATE_ARMED	   ( 9 <<  8)
#define MLX4_EQ_STATE_FIRED	   (10 <<  8)
#define MLX4_EQ_STATE_ALWAYS_ARMED (11 <<  8)

#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG)	    | \
			       (1ull << MLX4_EVENT_TYPE_COMM_EST)	    | \
			       (1ull << MLX4_EVENT_TYPE_SQ_DRAINED)	    | \
			       (1ull << MLX4_EVENT_TYPE_CQ_ERROR)	    | \
			       (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR)	    | \
			       (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR)    | \
			       (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED)    | \
			       (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
			       (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
			       (1ull << MLX4_EVENT_TYPE_PORT_CHANGE)	    | \
			       (1ull << MLX4_EVENT_TYPE_ECC_DETECT)	    | \
			       (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
			       (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE)    | \
			       (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT)	    | \
			       (1ull << MLX4_EVENT_TYPE_CMD))

struct mlx4_eqe {
	u8			reserved1;
	u8			type;
	u8			reserved2;
	u8			subtype;
	union {
		u32		raw[6];
		struct {
			__be32	cqn;
		} __attribute__((packed)) comp;
		struct {
			u16	reserved1;
			__be16	token;
			u32	reserved2;
			u8	reserved3[3];
			u8	status;
			__be64	out_param;
		} __attribute__((packed)) cmd;
		struct {
			__be32	qpn;
		} __attribute__((packed)) qp;
		struct {
			__be32	srqn;
		} __attribute__((packed)) srq;
		struct {
			__be32	cqn;
			u32	reserved1;
			u8	reserved2[3];
			u8	syndrome;
		} __attribute__((packed)) cq_err;
		struct {
			u32	reserved1[2];
			__be32	port;
		} __attribute__((packed)) port_change;
	}			event;
	u8			reserved3[3];
	u8			owner;
} __attribute__((packed));

static void eq_set_ci(struct mlx4_eq *eq, int req_not)
{
	__raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
					       req_not << 31),
		     eq->doorbell);
	/* We still want ordering, just not swabbing, so add a barrier */
	mb();
}

static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry)
{
	unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
	return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
}

static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq)
{
	struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
	return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
}

static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
{
	struct mlx4_eqe *eqe;
	int cqn;
	int eqes_found = 0;
	int set_ci = 0;
	int port;

	while ((eqe = next_eqe_sw(eq))) {
		/*
		 * Make sure we read EQ entry contents after we've
		 * checked the ownership bit.
		 */
		rmb();

		switch (eqe->type) {
		case MLX4_EVENT_TYPE_COMP:
			cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
			mlx4_cq_completion(dev, cqn);
			break;

		case MLX4_EVENT_TYPE_PATH_MIG:
		case MLX4_EVENT_TYPE_COMM_EST:
		case MLX4_EVENT_TYPE_SQ_DRAINED:
		case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
		case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
		case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
		case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
		case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
			mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
				      eqe->type);
			break;

		case MLX4_EVENT_TYPE_SRQ_LIMIT:
		case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
			mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
				      eqe->type);
			break;

		case MLX4_EVENT_TYPE_CMD:
			mlx4_cmd_event(dev,
				       be16_to_cpu(eqe->event.cmd.token),
				       eqe->event.cmd.status,
				       be64_to_cpu(eqe->event.cmd.out_param));
			break;

		case MLX4_EVENT_TYPE_PORT_CHANGE:
			port = be32_to_cpu(eqe->event.port_change.port) >> 28;
			if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
				mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
						    port);
				mlx4_priv(dev)->sense.do_sense_port[port] = 1;
			} else {
				mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP,
						    port);
				mlx4_priv(dev)->sense.do_sense_port[port] = 0;
			}
			break;

		case MLX4_EVENT_TYPE_CQ_ERROR:
			mlx4_warn(dev, "CQ %s on CQN %06x\n",
				  eqe->event.cq_err.syndrome == 1 ?
				  "overrun" : "access violation",
				  be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
			mlx4_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
				      eqe->type);
			break;

		case MLX4_EVENT_TYPE_EQ_OVERFLOW:
			mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
			break;

		case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
		case MLX4_EVENT_TYPE_ECC_DETECT:
		default:
			mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u\n",
				  eqe->type, eqe->subtype, eq->eqn, eq->cons_index);
			break;
		};

		++eq->cons_index;
		eqes_found = 1;
		++set_ci;

		/*
		 * The HCA will think the queue has overflowed if we
		 * don't tell it we've been processing events.  We
		 * create our EQs with MLX4_NUM_SPARE_EQE extra
		 * entries, so we must update our consumer index at
		 * least that often.
		 */
		if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
			eq_set_ci(eq, 0);
			set_ci = 0;
		}
	}

	eq_set_ci(eq, 1);

	return eqes_found;
}

static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
{
	struct mlx4_dev *dev = dev_ptr;
	struct mlx4_priv *priv = mlx4_priv(dev);
	int work = 0;
	int i;

	writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);

	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
		work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);

	return IRQ_RETVAL(work);
}

static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
{
	struct mlx4_eq  *eq  = eq_ptr;
	struct mlx4_dev *dev = eq->dev;

	mlx4_eq_int(dev, eq);

	/* MSI-X vectors always belong to us */
	return IRQ_HANDLED;
}

static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
			int eq_num)
{
	return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
			0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B);
}

static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int eq_num)
{
	return mlx4_cmd(dev, mailbox->dma, eq_num, 0, MLX4_CMD_SW2HW_EQ,
			MLX4_CMD_TIME_CLASS_A);
}

static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
			 int eq_num)
{
	return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 0, MLX4_CMD_HW2SW_EQ,
			    MLX4_CMD_TIME_CLASS_A);
}

static int mlx4_num_eq_uar(struct mlx4_dev *dev)
{
	/*
	 * Each UAR holds 4 EQ doorbells.  To figure out how many UARs
	 * we need to map, take the difference of highest index and
	 * the lowest index we'll use and add 1.
	 */
	return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 -
		dev->caps.reserved_eqs / 4 + 1;
}

static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	int index;

	index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;

	if (!priv->eq_table.uar_map[index]) {
		priv->eq_table.uar_map[index] =
			ioremap(pci_resource_start(dev->pdev, 2) +
				((eq->eqn / 4) << PAGE_SHIFT),
				PAGE_SIZE);
		if (!priv->eq_table.uar_map[index]) {
			mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
				 eq->eqn);
			return NULL;
		}
	}

	return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
}

static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
			  u8 intr, struct mlx4_eq *eq)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cmd_mailbox *mailbox;
	struct mlx4_eq_context *eq_context;
	int npages;
	u64 *dma_list = NULL;
	dma_addr_t t;
	u64 mtt_addr;
	int err = -ENOMEM;
	int i;

	eq->dev   = dev;
	eq->nent  = roundup_pow_of_two(max(nent, 2));
	npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;

	eq->page_list = kmalloc(npages * sizeof *eq->page_list,
				GFP_KERNEL);
	if (!eq->page_list)
		goto err_out;

	for (i = 0; i < npages; ++i)
		eq->page_list[i].buf = NULL;

	dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
	if (!dma_list)
		goto err_out_free;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		goto err_out_free;
	eq_context = mailbox->buf;

	for (i = 0; i < npages; ++i) {
		eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
							  PAGE_SIZE, &t, GFP_KERNEL);
		if (!eq->page_list[i].buf)
			goto err_out_free_pages;

		dma_list[i] = t;
		eq->page_list[i].map = t;

		memset(eq->page_list[i].buf, 0, PAGE_SIZE);
	}

	eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
	if (eq->eqn == -1)
		goto err_out_free_pages;

	eq->doorbell = mlx4_get_eq_uar(dev, eq);
	if (!eq->doorbell) {
		err = -ENOMEM;
		goto err_out_free_eq;
	}

	err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
	if (err)
		goto err_out_free_eq;

	err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
	if (err)
		goto err_out_free_mtt;

	memset(eq_context, 0, sizeof *eq_context);
	eq_context->flags	  = cpu_to_be32(MLX4_EQ_STATUS_OK   |
						MLX4_EQ_STATE_ARMED);
	eq_context->log_eq_size	  = ilog2(eq->nent);
	eq_context->intr	  = intr;
	eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;

	mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
	eq_context->mtt_base_addr_h = mtt_addr >> 32;
	eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);

	err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
	if (err) {
		mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
		goto err_out_free_mtt;
	}

	kfree(dma_list);
	mlx4_free_cmd_mailbox(dev, mailbox);

	eq->cons_index = 0;

	return err;

err_out_free_mtt:
	mlx4_mtt_cleanup(dev, &eq->mtt);

err_out_free_eq:
	mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);

err_out_free_pages:
	for (i = 0; i < npages; ++i)
		if (eq->page_list[i].buf)
			dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
					  eq->page_list[i].buf,
					  eq->page_list[i].map);

	mlx4_free_cmd_mailbox(dev, mailbox);

err_out_free:
	kfree(eq->page_list);
	kfree(dma_list);

err_out:
	return err;
}

static void mlx4_free_eq(struct mlx4_dev *dev,
			 struct mlx4_eq *eq)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	struct mlx4_cmd_mailbox *mailbox;
	int err;
	int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
	int i;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return;

	err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
	if (err)
		mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);

	if (0) {
		mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
		for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
			if (i % 4 == 0)
				printk("[%02x] ", i * 4);
			printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
			if ((i + 1) % 4 == 0)
				printk("\n");
		}
	}

	mlx4_mtt_cleanup(dev, &eq->mtt);
	for (i = 0; i < npages; ++i)
		pci_free_consistent(dev->pdev, PAGE_SIZE,
				    eq->page_list[i].buf,
				    eq->page_list[i].map);

	kfree(eq->page_list);
	mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
	mlx4_free_cmd_mailbox(dev, mailbox);
}

static void mlx4_free_irqs(struct mlx4_dev *dev)
{
	struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
	int i;

	if (eq_table->have_irq)
		free_irq(dev->pdev->irq, dev);
	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
		if (eq_table->eq[i].have_irq) {
			free_irq(eq_table->eq[i].irq, eq_table->eq + i);
			eq_table->eq[i].have_irq = 0;
		}

	kfree(eq_table->irq_names);
}

static int mlx4_map_clr_int(struct mlx4_dev *dev)
{
	struct mlx4_priv *priv = mlx4_priv(dev);

	priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
				 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
	if (!priv->clr_base) {
		mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
		return -ENOMEM;
	}

	return 0;
}

static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
{
	struct mlx4_priv *priv = mlx4_priv(dev);

	iounmap(priv->clr_base);
}

int mlx4_alloc_eq_table(struct mlx4_dev *dev)
{
	struct mlx4_priv *priv = mlx4_priv(dev);

	priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
				    sizeof *priv->eq_table.eq, GFP_KERNEL);
	if (!priv->eq_table.eq)
		return -ENOMEM;

	return 0;
}

void mlx4_free_eq_table(struct mlx4_dev *dev)
{
	kfree(mlx4_priv(dev)->eq_table.eq);
}

int mlx4_init_eq_table(struct mlx4_dev *dev)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	int err;
	int i;

	priv->eq_table.uar_map = kcalloc(sizeof *priv->eq_table.uar_map,
					 mlx4_num_eq_uar(dev), GFP_KERNEL);
	if (!priv->eq_table.uar_map) {
		err = -ENOMEM;
		goto err_out_free;
	}

	err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
			       dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
	if (err)
		goto err_out_free;

	for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
		priv->eq_table.uar_map[i] = NULL;

	err = mlx4_map_clr_int(dev);
	if (err)
		goto err_out_bitmap;

	priv->eq_table.clr_mask =
		swab32(1 << (priv->eq_table.inta_pin & 31));
	priv->eq_table.clr_int  = priv->clr_base +
		(priv->eq_table.inta_pin < 32 ? 4 : 0);

	priv->eq_table.irq_names =
		kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1),
			GFP_KERNEL);
	if (!priv->eq_table.irq_names) {
		err = -ENOMEM;
		goto err_out_bitmap;
	}

	for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
		err = mlx4_create_eq(dev, dev->caps.num_cqs + MLX4_NUM_SPARE_EQE,
				     (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
				     &priv->eq_table.eq[i]);
		if (err) {
			--i;
			goto err_out_unmap;
		}
	}

	err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
			     (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
			     &priv->eq_table.eq[dev->caps.num_comp_vectors]);
	if (err)
		goto err_out_comp;

	if (dev->flags & MLX4_FLAG_MSI_X) {
		const char *eq_name;

		for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
			if (i < dev->caps.num_comp_vectors) {
				snprintf(priv->eq_table.irq_names +
					 i * MLX4_IRQNAME_SIZE,
					 MLX4_IRQNAME_SIZE,
					 "mlx4-comp-%d@pci:%s", i,
					 pci_name(dev->pdev));
			} else {
				snprintf(priv->eq_table.irq_names +
					 i * MLX4_IRQNAME_SIZE,
					 MLX4_IRQNAME_SIZE,
					 "mlx4-async@pci:%s",
					 pci_name(dev->pdev));
			}

			eq_name = priv->eq_table.irq_names +
				  i * MLX4_IRQNAME_SIZE;
			err = request_irq(priv->eq_table.eq[i].irq,
					  mlx4_msi_x_interrupt, 0, eq_name,
					  priv->eq_table.eq + i);
			if (err)
				goto err_out_async;

			priv->eq_table.eq[i].have_irq = 1;
		}
	} else {
		snprintf(priv->eq_table.irq_names,
			 MLX4_IRQNAME_SIZE,
			 DRV_NAME "@pci:%s",
			 pci_name(dev->pdev));
		err = request_irq(dev->pdev->irq, mlx4_interrupt,
				  IRQF_SHARED, priv->eq_table.irq_names, dev);
		if (err)
			goto err_out_async;

		priv->eq_table.have_irq = 1;
	}

	err = mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
			  priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
	if (err)
		mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
			   priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);

	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
		eq_set_ci(&priv->eq_table.eq[i], 1);

	return 0;

err_out_async:
	mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);

err_out_comp:
	i = dev->caps.num_comp_vectors - 1;

err_out_unmap:
	while (i >= 0) {
		mlx4_free_eq(dev, &priv->eq_table.eq[i]);
		--i;
	}
	mlx4_unmap_clr_int(dev);
	mlx4_free_irqs(dev);

err_out_bitmap:
	mlx4_bitmap_cleanup(&priv->eq_table.bitmap);

err_out_free:
	kfree(priv->eq_table.uar_map);

	return err;
}

void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
{
	struct mlx4_priv *priv = mlx4_priv(dev);
	int i;

	mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 1,
		    priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);

	mlx4_free_irqs(dev);

	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
		mlx4_free_eq(dev, &priv->eq_table.eq[i]);

	mlx4_unmap_clr_int(dev);

	for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
		if (priv->eq_table.uar_map[i])
			iounmap(priv->eq_table.uar_map[i]);

	mlx4_bitmap_cleanup(&priv->eq_table.bitmap);

	kfree(priv->eq_table.uar_map);
}
Commit	Line	Data
225c7b1f	1	/*
51a379d0	2	* Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f RD	3	* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenIB.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*/
	33
225c7b1f	34	#include <linux/interrupt.h>
5a0e3ad6	35	#include <linux/slab.h>
27ac792c	36	#include <linux/mm.h>
9cbe05c7	37	#include <linux/dma-mapping.h>
225c7b1f RD	38
	39	#include <linux/mlx4/cmd.h>
	40
	41	#include "mlx4.h"
	42	#include "fw.h"
	43
f5f5951c AB	44	enum {
	45	MLX4_IRQNAME_SIZE = 64
	46	};
	47
225c7b1f RD	48	enum {
	49	MLX4_NUM_ASYNC_EQE = 0x100,
	50	MLX4_NUM_SPARE_EQE = 0x80,
	51	MLX4_EQ_ENTRY_SIZE = 0x20
	52	};
	53
	54	/*
	55	* Must be packed because start is 64 bits but only aligned to 32 bits.
	56	*/
	57	struct mlx4_eq_context {
	58	__be32 flags;
	59	u16 reserved1[3];
	60	__be16 page_offset;
	61	u8 log_eq_size;
	62	u8 reserved2[4];
	63	u8 eq_period;
	64	u8 reserved3;
	65	u8 eq_max_count;
	66	u8 reserved4[3];
	67	u8 intr;
	68	u8 log_page_size;
	69	u8 reserved5[2];
	70	u8 mtt_base_addr_h;
	71	__be32 mtt_base_addr_l;
	72	u32 reserved6[2];
	73	__be32 consumer_index;
	74	__be32 producer_index;
	75	u32 reserved7[4];
	76	};
	77
	78	#define MLX4_EQ_STATUS_OK ( 0 << 28)
	79	#define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
	80	#define MLX4_EQ_OWNER_SW ( 0 << 24)
	81	#define MLX4_EQ_OWNER_HW ( 1 << 24)
	82	#define MLX4_EQ_FLAG_EC ( 1 << 18)
	83	#define MLX4_EQ_FLAG_OI ( 1 << 17)
	84	#define MLX4_EQ_STATE_ARMED ( 9 << 8)
	85	#define MLX4_EQ_STATE_FIRED (10 << 8)
	86	#define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
	87
	88	#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) \| \
	89	(1ull << MLX4_EVENT_TYPE_COMM_EST) \| \
	90	(1ull << MLX4_EVENT_TYPE_SQ_DRAINED) \| \
	91	(1ull << MLX4_EVENT_TYPE_CQ_ERROR) \| \
	92	(1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) \| \
	93	(1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) \| \
	94	(1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) \| \
	95	(1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) \| \
	96	(1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) \| \
225c7b1f RD	97	(1ull << MLX4_EVENT_TYPE_PORT_CHANGE) \| \
	98	(1ull << MLX4_EVENT_TYPE_ECC_DETECT) \| \
	99	(1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) \| \
	100	(1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) \| \
	101	(1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) \| \
	102	(1ull << MLX4_EVENT_TYPE_CMD))
225c7b1f RD	103
	104	struct mlx4_eqe {
	105	u8 reserved1;
	106	u8 type;
	107	u8 reserved2;
	108	u8 subtype;
	109	union {
	110	u32 raw[6];
	111	struct {
	112	__be32 cqn;
	113	} __attribute__((packed)) comp;
	114	struct {
	115	u16 reserved1;
	116	__be16 token;
	117	u32 reserved2;
	118	u8 reserved3[3];
	119	u8 status;
	120	__be64 out_param;
	121	} __attribute__((packed)) cmd;
	122	struct {
	123	__be32 qpn;
	124	} __attribute__((packed)) qp;
	125	struct {
	126	__be32 srqn;
	127	} __attribute__((packed)) srq;
	128	struct {
	129	__be32 cqn;
	130	u32 reserved1;
	131	u8 reserved2[3];
	132	u8 syndrome;
	133	} __attribute__((packed)) cq_err;
	134	struct {
	135	u32 reserved1[2];
	136	__be32 port;
	137	} __attribute__((packed)) port_change;
	138	} event;
	139	u8 reserved3[3];
	140	u8 owner;
	141	} __attribute__((packed));
	142
	143	static void eq_set_ci(struct mlx4_eq *eq, int req_not)
	144	{
	145	__raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) \|
	146	req_not << 31),
	147	eq->doorbell);
	148	/* We still want ordering, just not swabbing, so add a barrier */
	149	mb();
	150	}
	151
	152	static struct mlx4_eqe get_eqe(struct mlx4_eq eq, u32 entry)
	153	{
	154	unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
	155	return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
	156	}
	157
	158	static struct mlx4_eqe next_eqe_sw(struct mlx4_eq eq)
	159	{
	160	struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
	161	return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
	162	}
	163
	164	static int mlx4_eq_int(struct mlx4_dev dev, struct mlx4_eq eq)
	165	{
	166	struct mlx4_eqe *eqe;
167	int cqn;
168	int eqes_found = 0;
169	int set_ci = 0;
27bf91d6	170	int port;
225c7b1f RD	171
	172	while ((eqe = next_eqe_sw(eq))) {
	173	/*
	174	* Make sure we read EQ entry contents after we've
	175	* checked the ownership bit.
	176	*/
	177	rmb();
	178
	179	switch (eqe->type) {
	180	case MLX4_EVENT_TYPE_COMP:
	181	cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
	182	mlx4_cq_completion(dev, cqn);
	183	break;
	184
	185	case MLX4_EVENT_TYPE_PATH_MIG:
	186	case MLX4_EVENT_TYPE_COMM_EST:
	187	case MLX4_EVENT_TYPE_SQ_DRAINED:
	188	case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
	189	case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
	190	case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
	191	case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
	192	case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
	193	mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
	194	eqe->type);
	195	break;
	196
	197	case MLX4_EVENT_TYPE_SRQ_LIMIT:
	198	case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
	199	mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
	200	eqe->type);
	201	break;
	202
	203	case MLX4_EVENT_TYPE_CMD:
	204	mlx4_cmd_event(dev,
	205	be16_to_cpu(eqe->event.cmd.token),
	206	eqe->event.cmd.status,
	207	be64_to_cpu(eqe->event.cmd.out_param));
	208	break;
	209
	210	case MLX4_EVENT_TYPE_PORT_CHANGE:
27bf91d6 YP	211	port = be32_to_cpu(eqe->event.port_change.port) >> 28;
	212	if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
	213	mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
	214	port);
	215	mlx4_priv(dev)->sense.do_sense_port[port] = 1;
	216	} else {
	217	mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP,
	218	port);
	219	mlx4_priv(dev)->sense.do_sense_port[port] = 0;
	220	}
225c7b1f RD	221	break;
	222
	223	case MLX4_EVENT_TYPE_CQ_ERROR:
	224	mlx4_warn(dev, "CQ %s on CQN %06x\n",
	225	eqe->event.cq_err.syndrome == 1 ?
	226	"overrun" : "access violation",
	227	be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
	228	mlx4_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
	229	eqe->type);
	230	break;
	231
	232	case MLX4_EVENT_TYPE_EQ_OVERFLOW:
	233	mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
	234	break;
	235
	236	case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
	237	case MLX4_EVENT_TYPE_ECC_DETECT:
	238	default:
	239	mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u\n",
	240	eqe->type, eqe->subtype, eq->eqn, eq->cons_index);
	241	break;
	242	};
	243
	244	++eq->cons_index;
	245	eqes_found = 1;
	246	++set_ci;
	247
	248	/*
	249	* The HCA will think the queue has overflowed if we
	250	* don't tell it we've been processing events. We
	251	* create our EQs with MLX4_NUM_SPARE_EQE extra
	252	* entries, so we must update our consumer index at
	253	* least that often.
	254	*/
	255	if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
225c7b1f RD	256	eq_set_ci(eq, 0);
	257	set_ci = 0;
	258	}
	259	}
	260
	261	eq_set_ci(eq, 1);
	262
	263	return eqes_found;
	264	}
	265
	266	static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
	267	{
	268	struct mlx4_dev *dev = dev_ptr;
	269	struct mlx4_priv *priv = mlx4_priv(dev);
	270	int work = 0;
	271	int i;
	272
	273	writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
	274
b8dd786f	275	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
225c7b1f RD	276	work \|= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
	277
	278	return IRQ_RETVAL(work);
	279	}
	280
	281	static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
	282	{
	283	struct mlx4_eq *eq = eq_ptr;
	284	struct mlx4_dev *dev = eq->dev;
	285
	286	mlx4_eq_int(dev, eq);
	287
	288	/* MSI-X vectors always belong to us */
	289	return IRQ_HANDLED;
	290	}
	291
225c7b1f RD	292	static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
	293	int eq_num)
	294	{
	295	return mlx4_cmd(dev, event_mask, (unmap << 31) \| eq_num,
	296	0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B);
	297	}
	298
	299	static int mlx4_SW2HW_EQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	300	int eq_num)
	301	{
	302	return mlx4_cmd(dev, mailbox->dma, eq_num, 0, MLX4_CMD_SW2HW_EQ,
	303	MLX4_CMD_TIME_CLASS_A);
	304	}
	305
	306	static int mlx4_HW2SW_EQ(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox,
	307	int eq_num)
	308	{
	309	return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 0, MLX4_CMD_HW2SW_EQ,
	310	MLX4_CMD_TIME_CLASS_A);
	311	}
	312
b8dd786f YP	313	static int mlx4_num_eq_uar(struct mlx4_dev *dev)
	314	{
	315	/*
	316	* Each UAR holds 4 EQ doorbells. To figure out how many UARs
	317	* we need to map, take the difference of highest index and
	318	* the lowest index we'll use and add 1.
	319	*/
	320	return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 -
	321	dev->caps.reserved_eqs / 4 + 1;
	322	}
	323
3d73c288	324	static void __iomem mlx4_get_eq_uar(struct mlx4_dev dev, struct mlx4_eq *eq)
225c7b1f RD	325	{
	326	struct mlx4_priv *priv = mlx4_priv(dev);
	327	int index;
	328
	329	index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
	330
	331	if (!priv->eq_table.uar_map[index]) {
	332	priv->eq_table.uar_map[index] =
	333	ioremap(pci_resource_start(dev->pdev, 2) +
	334	((eq->eqn / 4) << PAGE_SHIFT),
	335	PAGE_SIZE);
	336	if (!priv->eq_table.uar_map[index]) {
	337	mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
	338	eq->eqn);
	339	return NULL;
	340	}
	341	}
	342
	343	return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
	344	}
	345
3d73c288 RD	346	static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
3d73c288 RD	347	u8 intr, struct mlx4_eq *eq)
225c7b1f RD	348	{
	349	struct mlx4_priv *priv = mlx4_priv(dev);
	350	struct mlx4_cmd_mailbox *mailbox;
	351	struct mlx4_eq_context *eq_context;
	352	int npages;
	353	u64 *dma_list = NULL;
	354	dma_addr_t t;
	355	u64 mtt_addr;
	356	int err = -ENOMEM;
	357	int i;
	358
	359	eq->dev = dev;
	360	eq->nent = roundup_pow_of_two(max(nent, 2));
	361	npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;
	362
	363	eq->page_list = kmalloc(npages * sizeof *eq->page_list,
	364	GFP_KERNEL);
	365	if (!eq->page_list)
	366	goto err_out;
	367
	368	for (i = 0; i < npages; ++i)
	369	eq->page_list[i].buf = NULL;
	370
	371	dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
	372	if (!dma_list)
	373	goto err_out_free;
	374
	375	mailbox = mlx4_alloc_cmd_mailbox(dev);
	376	if (IS_ERR(mailbox))
	377	goto err_out_free;
	378	eq_context = mailbox->buf;
	379
	380	for (i = 0; i < npages; ++i) {
	381	eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
	382	PAGE_SIZE, &t, GFP_KERNEL);
	383	if (!eq->page_list[i].buf)
	384	goto err_out_free_pages;
	385
	386	dma_list[i] = t;
	387	eq->page_list[i].map = t;
	388
	389	memset(eq->page_list[i].buf, 0, PAGE_SIZE);
	390	}
	391
	392	eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
	393	if (eq->eqn == -1)
	394	goto err_out_free_pages;
	395
	396	eq->doorbell = mlx4_get_eq_uar(dev, eq);
	397	if (!eq->doorbell) {
	398	err = -ENOMEM;
	399	goto err_out_free_eq;
	400	}
	401
	402	err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
	403	if (err)
	404	goto err_out_free_eq;
	405
	406	err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
	407	if (err)
	408	goto err_out_free_mtt;
	409
	410	memset(eq_context, 0, sizeof *eq_context);
	411	eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK \|
412	MLX4_EQ_STATE_ARMED);
413	eq_context->log_eq_size = ilog2(eq->nent);
414	eq_context->intr = intr;
415	eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
416
417	mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
418	eq_context->mtt_base_addr_h = mtt_addr >> 32;
419	eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
420
421	err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
422	if (err) {
423	mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
424	goto err_out_free_mtt;
425	}
426
427	kfree(dma_list);
428	mlx4_free_cmd_mailbox(dev, mailbox);
429
430	eq->cons_index = 0;
431
432	return err;
433
434	err_out_free_mtt:
435	mlx4_mtt_cleanup(dev, &eq->mtt);
436
437	err_out_free_eq:
438	mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
439
440	err_out_free_pages:
441	for (i = 0; i < npages; ++i)
442	if (eq->page_list[i].buf)
443	dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
444	eq->page_list[i].buf,
445	eq->page_list[i].map);
446
447	mlx4_free_cmd_mailbox(dev, mailbox);
448
449	err_out_free:
450	kfree(eq->page_list);
451	kfree(dma_list);
452
453	err_out:
454	return err;
455	}
456
457	static void mlx4_free_eq(struct mlx4_dev *dev,
458	struct mlx4_eq *eq)
459	{
460	struct mlx4_priv *priv = mlx4_priv(dev);
461	struct mlx4_cmd_mailbox *mailbox;
462	int err;
463	int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
464	int i;
465
466	mailbox = mlx4_alloc_cmd_mailbox(dev);
467	if (IS_ERR(mailbox))
468	return;
469
470	err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
471	if (err)
472	mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
473
474	if (0) {
475	mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
476	for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
477	if (i % 4 == 0)
478	printk("[%02x] ", i * 4);
479	printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
480	if ((i + 1) % 4 == 0)
481	printk("\n");
482	}
483	}
484
485	mlx4_mtt_cleanup(dev, &eq->mtt);
486	for (i = 0; i < npages; ++i)
487	pci_free_consistent(dev->pdev, PAGE_SIZE,
488	eq->page_list[i].buf,
489	eq->page_list[i].map);
490
491	kfree(eq->page_list);
492	mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
493	mlx4_free_cmd_mailbox(dev, mailbox);
494	}
495
496	static void mlx4_free_irqs(struct mlx4_dev *dev)
497	{
498	struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
499	int i;
500
501	if (eq_table->have_irq)
502	free_irq(dev->pdev->irq, dev);
b8dd786f	503	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
d1fdf24b	504	if (eq_table->eq[i].have_irq) {
225c7b1f	505	free_irq(eq_table->eq[i].irq, eq_table->eq + i);
d1fdf24b RD	506	eq_table->eq[i].have_irq = 0;
d1fdf24b RD	507	}
b8dd786f YP	508
b8dd786f YP	509	kfree(eq_table->irq_names);
225c7b1f RD	510	}
225c7b1f RD	511
3d73c288	512	static int mlx4_map_clr_int(struct mlx4_dev *dev)
225c7b1f RD	513	{
	514	struct mlx4_priv *priv = mlx4_priv(dev);
	515
	516	priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
	517	priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
	518	if (!priv->clr_base) {
	519	mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
	520	return -ENOMEM;
	521	}
	522
	523	return 0;
	524	}
	525
	526	static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
	527	{
	528	struct mlx4_priv *priv = mlx4_priv(dev);
	529
	530	iounmap(priv->clr_base);
	531	}
	532
b8dd786f YP	533	int mlx4_alloc_eq_table(struct mlx4_dev *dev)
	534	{
	535	struct mlx4_priv *priv = mlx4_priv(dev);
	536
	537	priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
	538	sizeof *priv->eq_table.eq, GFP_KERNEL);
	539	if (!priv->eq_table.eq)
	540	return -ENOMEM;
	541
	542	return 0;
	543	}
	544
	545	void mlx4_free_eq_table(struct mlx4_dev *dev)
	546	{
	547	kfree(mlx4_priv(dev)->eq_table.eq);
	548	}
	549
3d73c288	550	int mlx4_init_eq_table(struct mlx4_dev *dev)
225c7b1f RD	551	{
	552	struct mlx4_priv *priv = mlx4_priv(dev);
	553	int err;
	554	int i;
	555
b8dd786f YP	556	priv->eq_table.uar_map = kcalloc(sizeof *priv->eq_table.uar_map,
	557	mlx4_num_eq_uar(dev), GFP_KERNEL);
	558	if (!priv->eq_table.uar_map) {
	559	err = -ENOMEM;
	560	goto err_out_free;
	561	}
	562
225c7b1f	563	err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
93fc9e1b	564	dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
225c7b1f	565	if (err)
b8dd786f	566	goto err_out_free;
225c7b1f	567
b8dd786f	568	for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
225c7b1f RD	569	priv->eq_table.uar_map[i] = NULL;
	570
	571	err = mlx4_map_clr_int(dev);
	572	if (err)
b8dd786f	573	goto err_out_bitmap;
225c7b1f RD	574
	575	priv->eq_table.clr_mask =
	576	swab32(1 << (priv->eq_table.inta_pin & 31));
	577	priv->eq_table.clr_int = priv->clr_base +
	578	(priv->eq_table.inta_pin < 32 ? 4 : 0);
	579
f5f5951c AB	580	priv->eq_table.irq_names =
	581	kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1),
	582	GFP_KERNEL);
b8dd786f YP	583	if (!priv->eq_table.irq_names) {
	584	err = -ENOMEM;
	585	goto err_out_bitmap;
	586	}
	587
	588	for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
	589	err = mlx4_create_eq(dev, dev->caps.num_cqs + MLX4_NUM_SPARE_EQE,
	590	(dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
	591	&priv->eq_table.eq[i]);
a5b19b63 YP	592	if (err) {
a5b19b63 YP	593	--i;
b8dd786f	594	goto err_out_unmap;
a5b19b63	595	}
b8dd786f	596	}
225c7b1f RD	597
225c7b1f RD	598	err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
b8dd786f YP	599	(dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
b8dd786f YP	600	&priv->eq_table.eq[dev->caps.num_comp_vectors]);
225c7b1f RD	601	if (err)
	602	goto err_out_comp;
	603
	604	if (dev->flags & MLX4_FLAG_MSI_X) {
b8dd786f YP	605	const char *eq_name;
	606
	607	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
	608	if (i < dev->caps.num_comp_vectors) {
f5f5951c AB	609	snprintf(priv->eq_table.irq_names +
	610	i * MLX4_IRQNAME_SIZE,
	611	MLX4_IRQNAME_SIZE,
	612	"mlx4-comp-%d@pci:%s", i,
	613	pci_name(dev->pdev));
	614	} else {
	615	snprintf(priv->eq_table.irq_names +
	616	i * MLX4_IRQNAME_SIZE,
	617	MLX4_IRQNAME_SIZE,
	618	"mlx4-async@pci:%s",
	619	pci_name(dev->pdev));
	620	}
225c7b1f	621
f5f5951c AB	622	eq_name = priv->eq_table.irq_names +
f5f5951c AB	623	i * MLX4_IRQNAME_SIZE;
225c7b1f	624	err = request_irq(priv->eq_table.eq[i].irq,
b8dd786f YP	625	mlx4_msi_x_interrupt, 0, eq_name,
b8dd786f YP	626	priv->eq_table.eq + i);
225c7b1f	627	if (err)
ee49bd93	628	goto err_out_async;
225c7b1f RD	629
	630	priv->eq_table.eq[i].have_irq = 1;
	631	}
225c7b1f	632	} else {
f5f5951c AB	633	snprintf(priv->eq_table.irq_names,
	634	MLX4_IRQNAME_SIZE,
	635	DRV_NAME "@pci:%s",
	636	pci_name(dev->pdev));
225c7b1f	637	err = request_irq(dev->pdev->irq, mlx4_interrupt,
f5f5951c	638	IRQF_SHARED, priv->eq_table.irq_names, dev);
225c7b1f RD	639	if (err)
	640	goto err_out_async;
	641
	642	priv->eq_table.have_irq = 1;
	643	}
	644
	645	err = mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
b8dd786f	646	priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
225c7b1f RD	647	if (err)
225c7b1f RD	648	mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
b8dd786f	649	priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
225c7b1f	650
b8dd786f	651	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
225c7b1f RD	652	eq_set_ci(&priv->eq_table.eq[i], 1);
225c7b1f RD	653
225c7b1f RD	654	return 0;
225c7b1f RD	655
225c7b1f	656	err_out_async:
b8dd786f	657	mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
225c7b1f RD	658
225c7b1f RD	659	err_out_comp:
b8dd786f	660	i = dev->caps.num_comp_vectors - 1;
225c7b1f RD	661
225c7b1f RD	662	err_out_unmap:
b8dd786f YP	663	while (i >= 0) {
	664	mlx4_free_eq(dev, &priv->eq_table.eq[i]);
	665	--i;
	666	}
225c7b1f RD	667	mlx4_unmap_clr_int(dev);
	668	mlx4_free_irqs(dev);
	669
b8dd786f	670	err_out_bitmap:
225c7b1f	671	mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
b8dd786f YP	672
	673	err_out_free:
	674	kfree(priv->eq_table.uar_map);
	675
225c7b1f RD	676	return err;
	677	}
	678
	679	void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
	680	{
	681	struct mlx4_priv *priv = mlx4_priv(dev);
	682	int i;
	683
225c7b1f	684	mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 1,
b8dd786f	685	priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
225c7b1f RD	686
	687	mlx4_free_irqs(dev);
	688
b8dd786f	689	for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
225c7b1f	690	mlx4_free_eq(dev, &priv->eq_table.eq[i]);
225c7b1f RD	691
	692	mlx4_unmap_clr_int(dev);
	693
b8dd786f	694	for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
225c7b1f RD	695	if (priv->eq_table.uar_map[i])
	696	iounmap(priv->eq_table.uar_map[i]);
	697
	698	mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
b8dd786f YP	699
b8dd786f YP	700	kfree(priv->eq_table.uar_map);
225c7b1f	701	}