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Merge commit 'v2.6.37-rc7' into x86/security
[mirror_ubuntu-artful-kernel.git] / drivers / net / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/mlx4/cmd.h>
c57e20dc 36#include <linux/cache.h>
225c7b1f
RD		 37
38#include "fw.h"
39#include "icm.h"
40
fe40900f 41enum {
5ae2a7a8
RD		 42 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
43 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
44 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 45};
46
225c7b1f
RD		 47extern void __buggy_use_of_MLX4_GET(void);
48extern void __buggy_use_of_MLX4_PUT(void);
49
51f5f0ee
JM		 50static int enable_qos;
51module_param(enable_qos, bool, 0444);
52MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
53
225c7b1f
RD		 54#define MLX4_GET(dest, source, offset) \
55 do { \
56 void *__p = (char *) (source) + (offset); \
57 switch (sizeof (dest)) { \
58 case 1: (dest) = *(u8 *) __p; break; \
59 case 2: (dest) = be16_to_cpup(__p); break; \
60 case 4: (dest) = be32_to_cpup(__p); break; \
61 case 8: (dest) = be64_to_cpup(__p); break; \
62 default: __buggy_use_of_MLX4_GET(); \
63 } \
64 } while (0)
65
66#define MLX4_PUT(dest, source, offset) \
67 do { \
68 void *__d = ((char *) (dest) + (offset)); \
69 switch (sizeof(source)) { \
70 case 1: *(u8 *) __d = (source); break; \
71 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
72 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
73 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
74 default: __buggy_use_of_MLX4_PUT(); \
75 } \
76 } while (0)
77
78static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
79{
80 static const char *fname[] = {
81 [ 0] = "RC transport",
82 [ 1] = "UC transport",
83 [ 2] = "UD transport",
ea98054f 84 [ 3] = "XRC transport",
225c7b1f
RD		 85 [ 4] = "reliable multicast",
86 [ 5] = "FCoIB support",
87 [ 6] = "SRQ support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
91 [10] = "VMM",
7ff93f8b 92 [12] = "DPDP",
417608c2 93 [15] = "Big LSO headers",
225c7b1f
RD		 94 [16] = "MW support",
95 [17] = "APM support",
96 [18] = "Atomic ops support",
97 [19] = "Raw multicast support",
98 [20] = "Address vector port checking support",
99 [21] = "UD multicast support",
100 [24] = "Demand paging support",
96dfa684
EC		 101 [25] = "Router support",
102 [30] = "IBoE support"
225c7b1f
RD		 103 };
104 int i;
105
106 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 107 for (i = 0; i < ARRAY_SIZE(fname); ++i)
225c7b1f
RD		 108 if (fname[i] && (flags & (1 << i)))
109 mlx4_dbg(dev, " %s\n", fname[i]);
110}
111
2d928651
VS		 112int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
113{
114 struct mlx4_cmd_mailbox *mailbox;
115 u32 *inbox;
116 int err = 0;
117
118#define MOD_STAT_CFG_IN_SIZE 0x100
119
120#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
121#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
122
123 mailbox = mlx4_alloc_cmd_mailbox(dev);
124 if (IS_ERR(mailbox))
125 return PTR_ERR(mailbox);
126 inbox = mailbox->buf;
127
128 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
129
130 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
131 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
132
133 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
134 MLX4_CMD_TIME_CLASS_A);
135
136 mlx4_free_cmd_mailbox(dev, mailbox);
137 return err;
138}
139
225c7b1f
RD		 140int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
141{
142 struct mlx4_cmd_mailbox *mailbox;
143 u32 *outbox;
144 u8 field;
7699517d 145 u32 field32;
225c7b1f
RD		 146 u16 size;
147 u16 stat_rate;
148 int err;
5ae2a7a8 149 int i;
225c7b1f
RD		 150
151#define QUERY_DEV_CAP_OUT_SIZE 0x100
152#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
153#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
154#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
155#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
156#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
157#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
158#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
159#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
160#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
161#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
162#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
163#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
164#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
165#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
166#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
167#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
168#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
169#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
170#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
171#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
172#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 173#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
225c7b1f
RD		 174#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
175#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
176#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
177#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
178#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 179#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 180#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
181#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
182#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
0533943c 183#define QUERY_DEV_CAP_UDP_RSS_OFFSET 0x42
e7c1c2c4 184#define QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET 0x43
225c7b1f
RD		 185#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
186#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
187#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
188#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
189#define QUERY_DEV_CAP_BF_OFFSET 0x4c
190#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
191#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
192#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
193#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
194#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
195#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
196#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
197#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
198#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
199#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
200#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
201#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
202#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
203#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
204#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
205#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
206#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
207#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
208#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
209#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
210#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
211#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 212#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 213#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
214#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
215
216 mailbox = mlx4_alloc_cmd_mailbox(dev);
217 if (IS_ERR(mailbox))
218 return PTR_ERR(mailbox);
219 outbox = mailbox->buf;
220
221 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
222 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 223 if (err)
224 goto out;
225
226 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
227 dev_cap->reserved_qps = 1 << (field & 0xf);
228 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
229 dev_cap->max_qps = 1 << (field & 0x1f);
230 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
231 dev_cap->reserved_srqs = 1 << (field >> 4);
232 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
233 dev_cap->max_srqs = 1 << (field & 0x1f);
234 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
235 dev_cap->max_cq_sz = 1 << field;
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
237 dev_cap->reserved_cqs = 1 << (field & 0xf);
238 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
239 dev_cap->max_cqs = 1 << (field & 0x1f);
240 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
241 dev_cap->max_mpts = 1 << (field & 0x3f);
242 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 243 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 244 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 245 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 246 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
247 dev_cap->reserved_mtts = 1 << (field >> 4);
248 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
249 dev_cap->max_mrw_sz = 1 << field;
250 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
251 dev_cap->reserved_mrws = 1 << (field & 0xf);
252 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
253 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
254 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
255 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
256 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
257 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 258 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
259 field &= 0x1f;
260 if (!field)
261 dev_cap->max_gso_sz = 0;
262 else
263 dev_cap->max_gso_sz = 1 << field;
264
225c7b1f
RD		 265 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
266 dev_cap->max_rdma_global = 1 << (field & 0x3f);
267 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
268 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 269 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 270 dev_cap->num_ports = field & 0xf;
149983af
DB		 271 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
272 dev_cap->max_msg_sz = 1 << (field & 0x1f);
225c7b1f
RD		 273 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
274 dev_cap->stat_rate_support = stat_rate;
0533943c
YP		 275 MLX4_GET(field, outbox, QUERY_DEV_CAP_UDP_RSS_OFFSET);
276 dev_cap->udp_rss = field & 0x1;
e7c1c2c4
YP		 277 MLX4_GET(field, outbox, QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET);
278 dev_cap->loopback_support = field & 0x1;
225c7b1f
RD		 279 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
280 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
281 dev_cap->reserved_uars = field >> 4;
282 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
283 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
284 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
285 dev_cap->min_page_sz = 1 << field;
286
287 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
288 if (field & 0x80) {
289 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
290 dev_cap->bf_reg_size = 1 << (field & 0x1f);
291 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
58d74bb1
EC		 292 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) {
293 mlx4_warn(dev, "firmware bug: log2 # of blue flame regs is invalid (%d), forcing 3\n", field & 0x1f);
294 field = 3;
295 }
225c7b1f
RD		 296 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
297 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
298 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
299 } else {
300 dev_cap->bf_reg_size = 0;
301 mlx4_dbg(dev, "BlueFlame not available\n");
302 }
303
304 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
305 dev_cap->max_sq_sg = field;
306 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
307 dev_cap->max_sq_desc_sz = size;
308
309 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
310 dev_cap->max_qp_per_mcg = 1 << field;
311 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
312 dev_cap->reserved_mgms = field & 0xf;
313 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
314 dev_cap->max_mcgs = 1 << field;
315 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
316 dev_cap->reserved_pds = field >> 4;
317 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
318 dev_cap->max_pds = 1 << (field & 0x3f);
319
320 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
321 dev_cap->rdmarc_entry_sz = size;
322 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
323 dev_cap->qpc_entry_sz = size;
324 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
325 dev_cap->aux_entry_sz = size;
326 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
327 dev_cap->altc_entry_sz = size;
328 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
329 dev_cap->eqc_entry_sz = size;
330 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
331 dev_cap->cqc_entry_sz = size;
332 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
333 dev_cap->srq_entry_sz = size;
334 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
335 dev_cap->cmpt_entry_sz = size;
336 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
337 dev_cap->mtt_entry_sz = size;
338 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
339 dev_cap->dmpt_entry_sz = size;
340
341 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
342 dev_cap->max_srq_sz = 1 << field;
343 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
344 dev_cap->max_qp_sz = 1 << field;
345 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
346 dev_cap->resize_srq = field & 1;
347 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
348 dev_cap->max_rq_sg = field;
349 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
350 dev_cap->max_rq_desc_sz = size;
351
352 MLX4_GET(dev_cap->bmme_flags, outbox,
353 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
354 MLX4_GET(dev_cap->reserved_lkey, outbox,
355 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
356 MLX4_GET(dev_cap->max_icm_sz, outbox,
357 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
358
5ae2a7a8
RD		 359 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
360 for (i = 1; i <= dev_cap->num_ports; ++i) {
361 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
362 dev_cap->max_vl[i] = field >> 4;
363 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 364 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 365 dev_cap->max_port_width[i] = field & 0xf;
366 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
367 dev_cap->max_gids[i] = 1 << (field & 0xf);
368 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
369 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
370 }
371 } else {
7ff93f8b 372#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 373#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 374#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 375#define QUERY_PORT_WIDTH_OFFSET 0x06
376#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 377#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 378#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 379#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 380#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
381#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
382#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 383
384 for (i = 1; i <= dev_cap->num_ports; ++i) {
385 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
386 MLX4_CMD_TIME_CLASS_B);
387 if (err)
388 goto out;
389
7ff93f8b
YP		 390 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
391 dev_cap->supported_port_types[i] = field & 3;
5ae2a7a8 392 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 393 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 394 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
395 dev_cap->max_port_width[i] = field & 0xf;
396 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
397 dev_cap->max_gids[i] = 1 << (field >> 4);
398 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
399 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
400 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 401 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
402 dev_cap->log_max_macs[i] = field & 0xf;
403 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 404 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
405 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 406 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
407 dev_cap->trans_type[i] = field32 >> 24;
408 dev_cap->vendor_oui[i] = field32 & 0xffffff;
409 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
410 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 411 }
412 }
413
95d04f07
RD		 414 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
415 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 416
417 /*
418 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
419 * we can't use any EQs whose doorbell falls on that page,
420 * even if the EQ itself isn't reserved.
421 */
422 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
423 dev_cap->reserved_eqs);
424
425 mlx4_dbg(dev, "Max ICM size %lld MB\n",
426 (unsigned long long) dev_cap->max_icm_sz >> 20);
427 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
428 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
429 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
430 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
431 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
432 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
433 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
434 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
435 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
436 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
437 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
438 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
439 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
440 dev_cap->max_pds, dev_cap->reserved_mgms);
441 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
442 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
443 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 444 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 445 dev_cap->max_port_width[1]);
225c7b1f
RD		 446 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
447 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
448 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
449 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 450 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
225c7b1f
RD		 451
452 dump_dev_cap_flags(dev, dev_cap->flags);
453
454out:
455 mlx4_free_cmd_mailbox(dev, mailbox);
456 return err;
457}
458
459int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
460{
461 struct mlx4_cmd_mailbox *mailbox;
462 struct mlx4_icm_iter iter;
463 __be64 *pages;
464 int lg;
465 int nent = 0;
466 int i;
467 int err = 0;
468 int ts = 0, tc = 0;
469
470 mailbox = mlx4_alloc_cmd_mailbox(dev);
471 if (IS_ERR(mailbox))
472 return PTR_ERR(mailbox);
473 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
474 pages = mailbox->buf;
475
476 for (mlx4_icm_first(icm, &iter);
477 !mlx4_icm_last(&iter);
478 mlx4_icm_next(&iter)) {
479 /*
480 * We have to pass pages that are aligned to their
481 * size, so find the least significant 1 in the
482 * address or size and use that as our log2 size.
483 */
484 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
485 if (lg < MLX4_ICM_PAGE_SHIFT) {
486 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
487 MLX4_ICM_PAGE_SIZE,
488 (unsigned long long) mlx4_icm_addr(&iter),
489 mlx4_icm_size(&iter));
490 err = -EINVAL;
491 goto out;
492 }
493
494 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
495 if (virt != -1) {
496 pages[nent * 2] = cpu_to_be64(virt);
497 virt += 1 << lg;
498 }
499
500 pages[nent * 2 + 1] =
501 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
502 (lg - MLX4_ICM_PAGE_SHIFT));
503 ts += 1 << (lg - 10);
504 ++tc;
505
506 if (++nent == MLX4_MAILBOX_SIZE / 16) {
507 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
508 MLX4_CMD_TIME_CLASS_B);
509 if (err)
510 goto out;
511 nent = 0;
512 }
513 }
514 }
515
516 if (nent)
517 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
518 if (err)
519 goto out;
520
521 switch (op) {
522 case MLX4_CMD_MAP_FA:
523 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
524 break;
525 case MLX4_CMD_MAP_ICM_AUX:
526 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
527 break;
528 case MLX4_CMD_MAP_ICM:
529 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
530 tc, ts, (unsigned long long) virt - (ts << 10));
531 break;
532 }
533
534out:
535 mlx4_free_cmd_mailbox(dev, mailbox);
536 return err;
537}
538
539int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
540{
541 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
542}
543
544int mlx4_UNMAP_FA(struct mlx4_dev *dev)
545{
546 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
547}
548
549
550int mlx4_RUN_FW(struct mlx4_dev *dev)
551{
552 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
553}
554
555int mlx4_QUERY_FW(struct mlx4_dev *dev)
556{
557 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
558 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
559 struct mlx4_cmd_mailbox *mailbox;
560 u32 *outbox;
561 int err = 0;
562 u64 fw_ver;
fe40900f 563 u16 cmd_if_rev;
225c7b1f
RD		 564 u8 lg;
565
566#define QUERY_FW_OUT_SIZE 0x100
567#define QUERY_FW_VER_OFFSET 0x00
fe40900f 568#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 569#define QUERY_FW_MAX_CMD_OFFSET 0x0f
570#define QUERY_FW_ERR_START_OFFSET 0x30
571#define QUERY_FW_ERR_SIZE_OFFSET 0x38
572#define QUERY_FW_ERR_BAR_OFFSET 0x3c
573
574#define QUERY_FW_SIZE_OFFSET 0x00
575#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
576#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
577
578 mailbox = mlx4_alloc_cmd_mailbox(dev);
579 if (IS_ERR(mailbox))
580 return PTR_ERR(mailbox);
581 outbox = mailbox->buf;
582
583 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
584 MLX4_CMD_TIME_CLASS_A);
585 if (err)
586 goto out;
587
588 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
589 /*
3e1db334 590 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 591 * version, so swap here.
592 */
593 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
594 ((fw_ver & 0xffff0000ull) >> 16) |
595 ((fw_ver & 0x0000ffffull) << 16);
596
fe40900f 597 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 598 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
599 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 600 mlx4_err(dev, "Installed FW has unsupported "
601 "command interface revision %d.\n",
602 cmd_if_rev);
603 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
604 (int) (dev->caps.fw_ver >> 32),
605 (int) (dev->caps.fw_ver >> 16) & 0xffff,
606 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 607 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
608 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 609 err = -ENODEV;
610 goto out;
611 }
612
5ae2a7a8
RD		 613 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
614 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
615
225c7b1f
RD		 616 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
617 cmd->max_cmds = 1 << lg;
618
fe40900f 619 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 620 (int) (dev->caps.fw_ver >> 32),
621 (int) (dev->caps.fw_ver >> 16) & 0xffff,
622 (int) dev->caps.fw_ver & 0xffff,
fe40900f 623 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 624
625 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
626 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
627 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
628 fw->catas_bar = (fw->catas_bar >> 6) * 2;
629
630 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
631 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
632
633 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
634 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
635 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
636 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
637
638 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
639
640 /*
641 * Round up number of system pages needed in case
642 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
643 */
644 fw->fw_pages =
645 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
646 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
647
648 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
649 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
650
651out:
652 mlx4_free_cmd_mailbox(dev, mailbox);
653 return err;
654}
655
656static void get_board_id(void *vsd, char *board_id)
657{
658 int i;
659
660#define VSD_OFFSET_SIG1 0x00
661#define VSD_OFFSET_SIG2 0xde
662#define VSD_OFFSET_MLX_BOARD_ID 0xd0
663#define VSD_OFFSET_TS_BOARD_ID 0x20
664
665#define VSD_SIGNATURE_TOPSPIN 0x5ad
666
667 memset(board_id, 0, MLX4_BOARD_ID_LEN);
668
669 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
670 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
671 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
672 } else {
673 /*
674 * The board ID is a string but the firmware byte
675 * swaps each 4-byte word before passing it back to
676 * us. Therefore we need to swab it before printing.
677 */
678 for (i = 0; i < 4; ++i)
679 ((u32 *) board_id)[i] =
680 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
681 }
682}
683
684int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
685{
686 struct mlx4_cmd_mailbox *mailbox;
687 u32 *outbox;
688 int err;
689
690#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 691#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
692#define QUERY_ADAPTER_VSD_OFFSET 0x20
693
694 mailbox = mlx4_alloc_cmd_mailbox(dev);
695 if (IS_ERR(mailbox))
696 return PTR_ERR(mailbox);
697 outbox = mailbox->buf;
698
699 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
700 MLX4_CMD_TIME_CLASS_A);
701 if (err)
702 goto out;
703
225c7b1f
RD		 704 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
705
706 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
707 adapter->board_id);
708
709out:
710 mlx4_free_cmd_mailbox(dev, mailbox);
711 return err;
712}
713
714int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
715{
716 struct mlx4_cmd_mailbox *mailbox;
717 __be32 *inbox;
718 int err;
719
720#define INIT_HCA_IN_SIZE 0x200
721#define INIT_HCA_VERSION_OFFSET 0x000
722#define INIT_HCA_VERSION 2
c57e20dc 723#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 724#define INIT_HCA_FLAGS_OFFSET 0x014
725#define INIT_HCA_QPC_OFFSET 0x020
726#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
727#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
728#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
729#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
730#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
731#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
732#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
733#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
734#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
735#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
736#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
737#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
738#define INIT_HCA_MCAST_OFFSET 0x0c0
739#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
740#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
741#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
742#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
743#define INIT_HCA_TPT_OFFSET 0x0f0
744#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
745#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
746#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
747#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
748#define INIT_HCA_UAR_OFFSET 0x120
749#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
750#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
751
752 mailbox = mlx4_alloc_cmd_mailbox(dev);
753 if (IS_ERR(mailbox))
754 return PTR_ERR(mailbox);
755 inbox = mailbox->buf;
756
757 memset(inbox, 0, INIT_HCA_IN_SIZE);
758
759 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
760
c57e20dc
EC		 761 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
762 (ilog2(cache_line_size()) - 4) << 5;
763
225c7b1f
RD		 764#if defined(__LITTLE_ENDIAN)
765 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
766#elif defined(__BIG_ENDIAN)
767 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
768#else
769#error Host endianness not defined
770#endif
771 /* Check port for UD address vector: */
772 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
773
8ff095ec
EC		 774 /* Enable IPoIB checksumming if we can: */
775 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
776 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
777
51f5f0ee
JM		 778 /* Enable QoS support if module parameter set */
779 if (enable_qos)
780 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
781
225c7b1f
RD		 782 /* QPC/EEC/CQC/EQC/RDMARC attributes */
783
784 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
785 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
786 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
787 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
788 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
789 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
790 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
791 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
792 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
793 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
794 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
795 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
796
797 /* multicast attributes */
798
799 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
800 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
801 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
802 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
803
804 /* TPT attributes */
805
806 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
807 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
808 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
809 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
810
811 /* UAR attributes */
812
813 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
814 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
815
77109cc2 816 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
225c7b1f
RD		 817
818 if (err)
819 mlx4_err(dev, "INIT_HCA returns %d\n", err);
820
821 mlx4_free_cmd_mailbox(dev, mailbox);
822 return err;
823}
824
5ae2a7a8 825int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 826{
827 struct mlx4_cmd_mailbox *mailbox;
828 u32 *inbox;
829 int err;
830 u32 flags;
5ae2a7a8 831 u16 field;
225c7b1f 832
5ae2a7a8 833 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 834#define INIT_PORT_IN_SIZE 256
835#define INIT_PORT_FLAGS_OFFSET 0x00
836#define INIT_PORT_FLAG_SIG (1 << 18)
837#define INIT_PORT_FLAG_NG (1 << 17)
838#define INIT_PORT_FLAG_G0 (1 << 16)
839#define INIT_PORT_VL_SHIFT 4
840#define INIT_PORT_PORT_WIDTH_SHIFT 8
841#define INIT_PORT_MTU_OFFSET 0x04
842#define INIT_PORT_MAX_GID_OFFSET 0x06
843#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
844#define INIT_PORT_GUID0_OFFSET 0x10
845#define INIT_PORT_NODE_GUID_OFFSET 0x18
846#define INIT_PORT_SI_GUID_OFFSET 0x20
847
5ae2a7a8
RD		 848 mailbox = mlx4_alloc_cmd_mailbox(dev);
849 if (IS_ERR(mailbox))
850 return PTR_ERR(mailbox);
851 inbox = mailbox->buf;
225c7b1f 852
5ae2a7a8 853 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 854
5ae2a7a8
RD		 855 flags = 0;
856 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
857 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
858 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 859
b79acb49 860 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 861 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
862 field = dev->caps.gid_table_len[port];
863 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
864 field = dev->caps.pkey_table_len[port];
865 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 866
5ae2a7a8
RD		 867 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
868 MLX4_CMD_TIME_CLASS_A);
225c7b1f 869
5ae2a7a8
RD		 870 mlx4_free_cmd_mailbox(dev, mailbox);
871 } else
872 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
873 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 874
875 return err;
876}
877EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
878
879int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
880{
881 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
882}
883EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
884
885int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
886{
887 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
888}
889
890int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
891{
892 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
893 MLX4_CMD_SET_ICM_SIZE,
894 MLX4_CMD_TIME_CLASS_A);
895 if (ret)
896 return ret;
897
898 /*
899 * Round up number of system pages needed in case
900 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
901 */
902 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
903 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
904
905 return 0;
906}
907
908int mlx4_NOP(struct mlx4_dev *dev)
909{
910 /* Input modifier of 0x1f means "finish as soon as possible." */
911 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
912}
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