[mirror_ubuntu-artful-kernel.git] / drivers / net / mlx4 / icm.c

/*
 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
 * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/init.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/scatterlist.h>

#include <linux/mlx4/cmd.h>

#include "mlx4.h"
#include "icm.h"
#include "fw.h"

/*
 * We allocate in as big chunks as we can, up to a maximum of 256 KB
 * per chunk.
 */
enum {
	MLX4_ICM_ALLOC_SIZE	= 1 << 18,
	MLX4_TABLE_CHUNK_SIZE	= 1 << 18
};

static void mlx4_free_icm_pages(struct mlx4_dev *dev, struct mlx4_icm_chunk *chunk)
{
	int i;

	if (chunk->nsg > 0)
		pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages,
			     PCI_DMA_BIDIRECTIONAL);

	for (i = 0; i < chunk->npages; ++i)
		__free_pages(sg_page(&chunk->mem[i]),
			     get_order(chunk->mem[i].length));
}

static void mlx4_free_icm_coherent(struct mlx4_dev *dev, struct mlx4_icm_chunk *chunk)
{
	int i;

	for (i = 0; i < chunk->npages; ++i)
		dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length,
				  lowmem_page_address(sg_page(&chunk->mem[i])),
				  sg_dma_address(&chunk->mem[i]));
}

void mlx4_free_icm(struct mlx4_dev *dev, struct mlx4_icm *icm, int coherent)
{
	struct mlx4_icm_chunk *chunk, *tmp;

	if (!icm)
		return;

	list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) {
		if (coherent)
			mlx4_free_icm_coherent(dev, chunk);
		else
			mlx4_free_icm_pages(dev, chunk);

		kfree(chunk);
	}

	kfree(icm);
}

static int mlx4_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_mask)
{
	struct page *page;

	page = alloc_pages(gfp_mask, order);
	if (!page)
		return -ENOMEM;

	sg_set_page(mem, page);
	mem->length = PAGE_SIZE << order;
	mem->offset = 0;
	return 0;
}

static int mlx4_alloc_icm_coherent(struct device *dev, struct scatterlist *mem,
				    int order, gfp_t gfp_mask)
{
	void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order,
				       &sg_dma_address(mem), gfp_mask);
	if (!buf)
		return -ENOMEM;

	sg_set_buf(mem, buf, PAGE_SIZE << order);
	BUG_ON(mem->offset);
	sg_dma_len(mem) = PAGE_SIZE << order;
	return 0;
}

struct mlx4_icm *mlx4_alloc_icm(struct mlx4_dev *dev, int npages,
				gfp_t gfp_mask, int coherent)
{
	struct mlx4_icm *icm;
	struct mlx4_icm_chunk *chunk = NULL;
	int cur_order;
	int ret;

	/* We use sg_set_buf for coherent allocs, which assumes low memory */
	BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM));

	icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
	if (!icm)
		return NULL;

	icm->refcount = 0;
	INIT_LIST_HEAD(&icm->chunk_list);

	cur_order = get_order(MLX4_ICM_ALLOC_SIZE);

	while (npages > 0) {
		if (!chunk) {
			chunk = kmalloc(sizeof *chunk,
					gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
			if (!chunk)
				goto fail;

			sg_init_table(chunk->mem, MLX4_ICM_CHUNK_LEN);
			chunk->npages = 0;
			chunk->nsg    = 0;
			list_add_tail(&chunk->list, &icm->chunk_list);
		}

		while (1 << cur_order > npages)
			--cur_order;

		if (coherent)
			ret = mlx4_alloc_icm_coherent(&dev->pdev->dev,
						      &chunk->mem[chunk->npages],
						      cur_order, gfp_mask);
		else
			ret = mlx4_alloc_icm_pages(&chunk->mem[chunk->npages],
						   cur_order, gfp_mask);

		if (!ret) {
			++chunk->npages;

			if (coherent)
				++chunk->nsg;
			else if (chunk->npages == MLX4_ICM_CHUNK_LEN) {
				chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
							chunk->npages,
							PCI_DMA_BIDIRECTIONAL);

				if (chunk->nsg <= 0)
					goto fail;

				chunk = NULL;
			}

			npages -= 1 << cur_order;
		} else {
			--cur_order;
			if (cur_order < 0)
				goto fail;
		}
	}

	if (!coherent && chunk) {
		chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
					chunk->npages,
					PCI_DMA_BIDIRECTIONAL);

		if (chunk->nsg <= 0)
			goto fail;
	}

	return icm;

fail:
	mlx4_free_icm(dev, icm, coherent);
	return NULL;
}

static int mlx4_MAP_ICM(struct mlx4_dev *dev, struct mlx4_icm *icm, u64 virt)
{
	return mlx4_map_cmd(dev, MLX4_CMD_MAP_ICM, icm, virt);
}

int mlx4_UNMAP_ICM(struct mlx4_dev *dev, u64 virt, u32 page_count)
{
	return mlx4_cmd(dev, virt, page_count, 0, MLX4_CMD_UNMAP_ICM,
			MLX4_CMD_TIME_CLASS_B);
}

int mlx4_MAP_ICM_page(struct mlx4_dev *dev, u64 dma_addr, u64 virt)
{
	struct mlx4_cmd_mailbox *mailbox;
	__be64 *inbox;
	int err;

	mailbox = mlx4_alloc_cmd_mailbox(dev);
	if (IS_ERR(mailbox))
		return PTR_ERR(mailbox);
	inbox = mailbox->buf;

	inbox[0] = cpu_to_be64(virt);
	inbox[1] = cpu_to_be64(dma_addr);

	err = mlx4_cmd(dev, mailbox->dma, 1, 0, MLX4_CMD_MAP_ICM,
		       MLX4_CMD_TIME_CLASS_B);

	mlx4_free_cmd_mailbox(dev, mailbox);

	if (!err)
		mlx4_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
			  (unsigned long long) dma_addr, (unsigned long long) virt);

	return err;
}

int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm)
{
	return mlx4_map_cmd(dev, MLX4_CMD_MAP_ICM_AUX, icm, -1);
}

int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev)
{
	return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_ICM_AUX, MLX4_CMD_TIME_CLASS_B);
}

int mlx4_table_get(struct mlx4_dev *dev, struct mlx4_icm_table *table, int obj)
{
	int i = (obj & (table->num_obj - 1)) / (MLX4_TABLE_CHUNK_SIZE / table->obj_size);
	int ret = 0;

	mutex_lock(&table->mutex);

	if (table->icm[i]) {
		++table->icm[i]->refcount;
		goto out;
	}

	table->icm[i] = mlx4_alloc_icm(dev, MLX4_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
				       (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
				       __GFP_NOWARN, table->coherent);
	if (!table->icm[i]) {
		ret = -ENOMEM;
		goto out;
	}

	if (mlx4_MAP_ICM(dev, table->icm[i], table->virt +
			 (u64) i * MLX4_TABLE_CHUNK_SIZE)) {
		mlx4_free_icm(dev, table->icm[i], table->coherent);
		table->icm[i] = NULL;
		ret = -ENOMEM;
		goto out;
	}

	++table->icm[i]->refcount;

out:
	mutex_unlock(&table->mutex);
	return ret;
}

void mlx4_table_put(struct mlx4_dev *dev, struct mlx4_icm_table *table, int obj)
{
	int i;

	i = (obj & (table->num_obj - 1)) / (MLX4_TABLE_CHUNK_SIZE / table->obj_size);

	mutex_lock(&table->mutex);

	if (--table->icm[i]->refcount == 0) {
		mlx4_UNMAP_ICM(dev, table->virt + i * MLX4_TABLE_CHUNK_SIZE,
			       MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
		mlx4_free_icm(dev, table->icm[i], table->coherent);
		table->icm[i] = NULL;
	}

	mutex_unlock(&table->mutex);
}

void *mlx4_table_find(struct mlx4_icm_table *table, int obj, dma_addr_t *dma_handle)
{
	int idx, offset, dma_offset, i;
	struct mlx4_icm_chunk *chunk;
	struct mlx4_icm *icm;
	struct page *page = NULL;

	if (!table->lowmem)
		return NULL;

	mutex_lock(&table->mutex);

	idx = (obj & (table->num_obj - 1)) * table->obj_size;
	icm = table->icm[idx / MLX4_TABLE_CHUNK_SIZE];
	dma_offset = offset = idx % MLX4_TABLE_CHUNK_SIZE;

	if (!icm)
		goto out;

	list_for_each_entry(chunk, &icm->chunk_list, list) {
		for (i = 0; i < chunk->npages; ++i) {
			if (dma_handle && dma_offset >= 0) {
				if (sg_dma_len(&chunk->mem[i]) > dma_offset)
					*dma_handle = sg_dma_address(&chunk->mem[i]) +
						dma_offset;
				dma_offset -= sg_dma_len(&chunk->mem[i]);
			}
			/*
			 * DMA mapping can merge pages but not split them,
			 * so if we found the page, dma_handle has already
			 * been assigned to.
			 */
			if (chunk->mem[i].length > offset) {
				page = sg_page(&chunk->mem[i]);
				goto out;
			}
			offset -= chunk->mem[i].length;
		}
	}

out:
	mutex_unlock(&table->mutex);
	return page ? lowmem_page_address(page) + offset : NULL;
}

int mlx4_table_get_range(struct mlx4_dev *dev, struct mlx4_icm_table *table,
			 int start, int end)
{
	int inc = MLX4_TABLE_CHUNK_SIZE / table->obj_size;
	int i, err;

	for (i = start; i <= end; i += inc) {
		err = mlx4_table_get(dev, table, i);
		if (err)
			goto fail;
	}

	return 0;

fail:
	while (i > start) {
		i -= inc;
		mlx4_table_put(dev, table, i);
	}

	return err;
}

void mlx4_table_put_range(struct mlx4_dev *dev, struct mlx4_icm_table *table,
			  int start, int end)
{
	int i;

	for (i = start; i <= end; i += MLX4_TABLE_CHUNK_SIZE / table->obj_size)
		mlx4_table_put(dev, table, i);
}

int mlx4_init_icm_table(struct mlx4_dev *dev, struct mlx4_icm_table *table,
			u64 virt, int obj_size,	int nobj, int reserved,
			int use_lowmem, int use_coherent)
{
	int obj_per_chunk;
	int num_icm;
	unsigned chunk_size;
	int i;

	obj_per_chunk = MLX4_TABLE_CHUNK_SIZE / obj_size;
	num_icm = (nobj + obj_per_chunk - 1) / obj_per_chunk;

	table->icm      = kcalloc(num_icm, sizeof *table->icm, GFP_KERNEL);
	if (!table->icm)
		return -ENOMEM;
	table->virt     = virt;
	table->num_icm  = num_icm;
	table->num_obj  = nobj;
	table->obj_size = obj_size;
	table->lowmem   = use_lowmem;
	table->coherent = use_coherent;
	mutex_init(&table->mutex);

	for (i = 0; i * MLX4_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) {
		chunk_size = MLX4_TABLE_CHUNK_SIZE;
		if ((i + 1) * MLX4_TABLE_CHUNK_SIZE > nobj * obj_size)
			chunk_size = PAGE_ALIGN(nobj * obj_size - i * MLX4_TABLE_CHUNK_SIZE);

		table->icm[i] = mlx4_alloc_icm(dev, chunk_size >> PAGE_SHIFT,
					       (use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
					       __GFP_NOWARN, use_coherent);
		if (!table->icm[i])
			goto err;
		if (mlx4_MAP_ICM(dev, table->icm[i], virt + i * MLX4_TABLE_CHUNK_SIZE)) {
			mlx4_free_icm(dev, table->icm[i], use_coherent);
			table->icm[i] = NULL;
			goto err;
		}

		/*
		 * Add a reference to this ICM chunk so that it never
		 * gets freed (since it contains reserved firmware objects).
		 */
		++table->icm[i]->refcount;
	}

	return 0;

err:
	for (i = 0; i < num_icm; ++i)
		if (table->icm[i]) {
			mlx4_UNMAP_ICM(dev, virt + i * MLX4_TABLE_CHUNK_SIZE,
				       MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
			mlx4_free_icm(dev, table->icm[i], use_coherent);
		}

	return -ENOMEM;
}

void mlx4_cleanup_icm_table(struct mlx4_dev *dev, struct mlx4_icm_table *table)
{
	int i;

	for (i = 0; i < table->num_icm; ++i)
		if (table->icm[i]) {
			mlx4_UNMAP_ICM(dev, table->virt + i * MLX4_TABLE_CHUNK_SIZE,
				       MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
			mlx4_free_icm(dev, table->icm[i], table->coherent);
		}

	kfree(table->icm);
}
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
	3	* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the
	9	* OpenIB.org BSD license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or
	12	* without modification, are permitted provided that the following
	13	* conditions are met:
	14	*
	15	* - Redistributions of source code must retain the above
	16	* copyright notice, this list of conditions and the following
	17	* disclaimer.
	18	*
	19	* - Redistributions in binary form must reproduce the above
	20	* copyright notice, this list of conditions and the following
	21	* disclaimer in the documentation and/or other materials
	22	* provided with the distribution.
	23	*
	24	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	25	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	26	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	27	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	28	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	29	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	30	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	31	* SOFTWARE.
	32	*/
	33
	34	#include <linux/init.h>
	35	#include <linux/errno.h>
9cbe05c7	36	#include <linux/mm.h>
5b0bf5e2	37	#include <linux/scatterlist.h>
225c7b1f RD	38
	39	#include <linux/mlx4/cmd.h>
	40
	41	#include "mlx4.h"
	42	#include "icm.h"
	43	#include "fw.h"
	44
	45	/*
	46	* We allocate in as big chunks as we can, up to a maximum of 256 KB
	47	* per chunk.
	48	*/
	49	enum {
	50	MLX4_ICM_ALLOC_SIZE = 1 << 18,
	51	MLX4_TABLE_CHUNK_SIZE = 1 << 18
	52	};
	53
5b0bf5e2	54	static void mlx4_free_icm_pages(struct mlx4_dev dev, struct mlx4_icm_chunk chunk)
225c7b1f	55	{
225c7b1f RD	56	int i;
225c7b1f RD	57
5b0bf5e2 JM	58	if (chunk->nsg > 0)
	59	pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages,
	60	PCI_DMA_BIDIRECTIONAL);
	61
	62	for (i = 0; i < chunk->npages; ++i)
45711f1a	63	__free_pages(sg_page(&chunk->mem[i]),
5b0bf5e2 JM	64	get_order(chunk->mem[i].length));
5b0bf5e2 JM	65	}
225c7b1f	66
5b0bf5e2 JM	67	static void mlx4_free_icm_coherent(struct mlx4_dev dev, struct mlx4_icm_chunk chunk)
	68	{
	69	int i;
	70
	71	for (i = 0; i < chunk->npages; ++i)
	72	dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length,
45711f1a	73	lowmem_page_address(sg_page(&chunk->mem[i])),
5b0bf5e2 JM	74	sg_dma_address(&chunk->mem[i]));
	75	}
	76
	77	void mlx4_free_icm(struct mlx4_dev dev, struct mlx4_icm icm, int coherent)
	78	{
	79	struct mlx4_icm_chunk chunk, tmp;
	80
	81	if (!icm)
	82	return;
	83
	84	list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) {
	85	if (coherent)
	86	mlx4_free_icm_coherent(dev, chunk);
	87	else
	88	mlx4_free_icm_pages(dev, chunk);
225c7b1f RD	89
	90	kfree(chunk);
	91	}
	92
	93	kfree(icm);
	94	}
	95
5b0bf5e2 JM	96	static int mlx4_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_mask)
5b0bf5e2 JM	97	{
45711f1a JA	98	struct page *page;
	99
	100	page = alloc_pages(gfp_mask, order);
	101	if (!page)
5b0bf5e2 JM	102	return -ENOMEM;
5b0bf5e2 JM	103
45711f1a	104	sg_set_page(mem, page);
5b0bf5e2 JM	105	mem->length = PAGE_SIZE << order;
	106	mem->offset = 0;
	107	return 0;
	108	}
	109
	110	static int mlx4_alloc_icm_coherent(struct device dev, struct scatterlist mem,
	111	int order, gfp_t gfp_mask)
	112	{
	113	void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order,
	114	&sg_dma_address(mem), gfp_mask);
	115	if (!buf)
	116	return -ENOMEM;
	117
	118	sg_set_buf(mem, buf, PAGE_SIZE << order);
	119	BUG_ON(mem->offset);
	120	sg_dma_len(mem) = PAGE_SIZE << order;
	121	return 0;
	122	}
	123
225c7b1f	124	struct mlx4_icm mlx4_alloc_icm(struct mlx4_dev dev, int npages,
5b0bf5e2	125	gfp_t gfp_mask, int coherent)
225c7b1f RD	126	{
	127	struct mlx4_icm *icm;
	128	struct mlx4_icm_chunk *chunk = NULL;
	129	int cur_order;
5b0bf5e2 JM	130	int ret;
	131
	132	/* We use sg_set_buf for coherent allocs, which assumes low memory */
	133	BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM));
225c7b1f RD	134
	135	icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM \| __GFP_NOWARN));
	136	if (!icm)
5b0bf5e2	137	return NULL;
225c7b1f RD	138
	139	icm->refcount = 0;
	140	INIT_LIST_HEAD(&icm->chunk_list);
	141
	142	cur_order = get_order(MLX4_ICM_ALLOC_SIZE);
	143
	144	while (npages > 0) {
	145	if (!chunk) {
	146	chunk = kmalloc(sizeof *chunk,
	147	gfp_mask & ~(__GFP_HIGHMEM \| __GFP_NOWARN));
	148	if (!chunk)
	149	goto fail;
	150
45711f1a	151	sg_init_table(chunk->mem, MLX4_ICM_CHUNK_LEN);
225c7b1f RD	152	chunk->npages = 0;
	153	chunk->nsg = 0;
	154	list_add_tail(&chunk->list, &icm->chunk_list);
	155	}
	156
	157	while (1 << cur_order > npages)
	158	--cur_order;
	159
5b0bf5e2 JM	160	if (coherent)
	161	ret = mlx4_alloc_icm_coherent(&dev->pdev->dev,
	162	&chunk->mem[chunk->npages],
	163	cur_order, gfp_mask);
	164	else
	165	ret = mlx4_alloc_icm_pages(&chunk->mem[chunk->npages],
	166	cur_order, gfp_mask);
	167
	168	if (!ret) {
	169	++chunk->npages;
225c7b1f	170
5b0bf5e2 JM	171	if (coherent)
	172	++chunk->nsg;
	173	else if (chunk->npages == MLX4_ICM_CHUNK_LEN) {
225c7b1f RD	174	chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
	175	chunk->npages,
	176	PCI_DMA_BIDIRECTIONAL);
	177
	178	if (chunk->nsg <= 0)
	179	goto fail;
	180
	181	chunk = NULL;
	182	}
	183
	184	npages -= 1 << cur_order;
	185	} else {
	186	--cur_order;
	187	if (cur_order < 0)
	188	goto fail;
	189	}
	190	}
	191
5b0bf5e2	192	if (!coherent && chunk) {
225c7b1f RD	193	chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
	194	chunk->npages,
	195	PCI_DMA_BIDIRECTIONAL);
	196
	197	if (chunk->nsg <= 0)
	198	goto fail;
	199	}
	200
	201	return icm;
	202
	203	fail:
5b0bf5e2	204	mlx4_free_icm(dev, icm, coherent);
225c7b1f RD	205	return NULL;
	206	}
	207
	208	static int mlx4_MAP_ICM(struct mlx4_dev dev, struct mlx4_icm icm, u64 virt)
	209	{
	210	return mlx4_map_cmd(dev, MLX4_CMD_MAP_ICM, icm, virt);
	211	}
	212
	213	int mlx4_UNMAP_ICM(struct mlx4_dev *dev, u64 virt, u32 page_count)
	214	{
	215	return mlx4_cmd(dev, virt, page_count, 0, MLX4_CMD_UNMAP_ICM,
	216	MLX4_CMD_TIME_CLASS_B);
	217	}
	218
	219	int mlx4_MAP_ICM_page(struct mlx4_dev *dev, u64 dma_addr, u64 virt)
	220	{
	221	struct mlx4_cmd_mailbox *mailbox;
	222	__be64 *inbox;
	223	int err;
	224
	225	mailbox = mlx4_alloc_cmd_mailbox(dev);
	226	if (IS_ERR(mailbox))
	227	return PTR_ERR(mailbox);
	228	inbox = mailbox->buf;
	229
	230	inbox[0] = cpu_to_be64(virt);
	231	inbox[1] = cpu_to_be64(dma_addr);
	232
	233	err = mlx4_cmd(dev, mailbox->dma, 1, 0, MLX4_CMD_MAP_ICM,
	234	MLX4_CMD_TIME_CLASS_B);
	235
	236	mlx4_free_cmd_mailbox(dev, mailbox);
	237
	238	if (!err)
	239	mlx4_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
	240	(unsigned long long) dma_addr, (unsigned long long) virt);
	241
	242	return err;
	243	}
	244
	245	int mlx4_MAP_ICM_AUX(struct mlx4_dev dev, struct mlx4_icm icm)
	246	{
	247	return mlx4_map_cmd(dev, MLX4_CMD_MAP_ICM_AUX, icm, -1);
	248	}
	249
	250	int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev)
	251	{
	252	return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_ICM_AUX, MLX4_CMD_TIME_CLASS_B);
	253	}
	254
	255	int mlx4_table_get(struct mlx4_dev dev, struct mlx4_icm_table table, int obj)
	256	{
	257	int i = (obj & (table->num_obj - 1)) / (MLX4_TABLE_CHUNK_SIZE / table->obj_size);
	258	int ret = 0;
	259
	260	mutex_lock(&table->mutex);
	261
	262	if (table->icm[i]) {
	263	++table->icm[i]->refcount;
	264	goto out;
	265	}
	266
	267	table->icm[i] = mlx4_alloc_icm(dev, MLX4_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
	268	(table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) \|
5b0bf5e2	269	__GFP_NOWARN, table->coherent);
225c7b1f RD	270	if (!table->icm[i]) {
	271	ret = -ENOMEM;
	272	goto out;
	273	}
	274
	275	if (mlx4_MAP_ICM(dev, table->icm[i], table->virt +
	276	(u64) i * MLX4_TABLE_CHUNK_SIZE)) {
5b0bf5e2	277	mlx4_free_icm(dev, table->icm[i], table->coherent);
225c7b1f RD	278	table->icm[i] = NULL;
	279	ret = -ENOMEM;
	280	goto out;
	281	}
	282
	283	++table->icm[i]->refcount;
	284
	285	out:
	286	mutex_unlock(&table->mutex);
	287	return ret;
	288	}
	289
	290	void mlx4_table_put(struct mlx4_dev dev, struct mlx4_icm_table table, int obj)
	291	{
	292	int i;
	293
	294	i = (obj & (table->num_obj - 1)) / (MLX4_TABLE_CHUNK_SIZE / table->obj_size);
	295
	296	mutex_lock(&table->mutex);
	297
	298	if (--table->icm[i]->refcount == 0) {
	299	mlx4_UNMAP_ICM(dev, table->virt + i * MLX4_TABLE_CHUNK_SIZE,
	300	MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
5b0bf5e2	301	mlx4_free_icm(dev, table->icm[i], table->coherent);
225c7b1f RD	302	table->icm[i] = NULL;
	303	}
	304
	305	mutex_unlock(&table->mutex);
	306	}
	307
d7bb58fb	308	void mlx4_table_find(struct mlx4_icm_table table, int obj, dma_addr_t *dma_handle)
225c7b1f	309	{
d7bb58fb	310	int idx, offset, dma_offset, i;
225c7b1f RD	311	struct mlx4_icm_chunk *chunk;
	312	struct mlx4_icm *icm;
	313	struct page *page = NULL;
	314
	315	if (!table->lowmem)
	316	return NULL;
	317
	318	mutex_lock(&table->mutex);
	319
d7bb58fb JM	320	idx = (obj & (table->num_obj - 1)) * table->obj_size;
	321	icm = table->icm[idx / MLX4_TABLE_CHUNK_SIZE];
	322	dma_offset = offset = idx % MLX4_TABLE_CHUNK_SIZE;
225c7b1f RD	323
	324	if (!icm)
	325	goto out;
	326
	327	list_for_each_entry(chunk, &icm->chunk_list, list) {
	328	for (i = 0; i < chunk->npages; ++i) {
d7bb58fb JM	329	if (dma_handle && dma_offset >= 0) {
	330	if (sg_dma_len(&chunk->mem[i]) > dma_offset)
	331	*dma_handle = sg_dma_address(&chunk->mem[i]) +
	332	dma_offset;
	333	dma_offset -= sg_dma_len(&chunk->mem[i]);
	334	}
	335	/*
	336	* DMA mapping can merge pages but not split them,
	337	* so if we found the page, dma_handle has already
	338	* been assigned to.
	339	*/
225c7b1f	340	if (chunk->mem[i].length > offset) {
45711f1a	341	page = sg_page(&chunk->mem[i]);
225c7b1f RD	342	goto out;
	343	}
	344	offset -= chunk->mem[i].length;
	345	}
	346	}
	347
	348	out:
	349	mutex_unlock(&table->mutex);
	350	return page ? lowmem_page_address(page) + offset : NULL;
	351	}
	352
	353	int mlx4_table_get_range(struct mlx4_dev dev, struct mlx4_icm_table table,
	354	int start, int end)
	355	{
	356	int inc = MLX4_TABLE_CHUNK_SIZE / table->obj_size;
	357	int i, err;
	358
	359	for (i = start; i <= end; i += inc) {
	360	err = mlx4_table_get(dev, table, i);
	361	if (err)
	362	goto fail;
	363	}
	364
	365	return 0;
	366
	367	fail:
	368	while (i > start) {
	369	i -= inc;
	370	mlx4_table_put(dev, table, i);
	371	}
	372
	373	return err;
	374	}
	375
	376	void mlx4_table_put_range(struct mlx4_dev dev, struct mlx4_icm_table table,
	377	int start, int end)
	378	{
	379	int i;
	380
	381	for (i = start; i <= end; i += MLX4_TABLE_CHUNK_SIZE / table->obj_size)
	382	mlx4_table_put(dev, table, i);
	383	}
	384
	385	int mlx4_init_icm_table(struct mlx4_dev dev, struct mlx4_icm_table table,
	386	u64 virt, int obj_size, int nobj, int reserved,
5b0bf5e2	387	int use_lowmem, int use_coherent)
225c7b1f RD	388	{
	389	int obj_per_chunk;
	390	int num_icm;
	391	unsigned chunk_size;
	392	int i;
	393
	394	obj_per_chunk = MLX4_TABLE_CHUNK_SIZE / obj_size;
	395	num_icm = (nobj + obj_per_chunk - 1) / obj_per_chunk;
	396
	397	table->icm = kcalloc(num_icm, sizeof *table->icm, GFP_KERNEL);
	398	if (!table->icm)
	399	return -ENOMEM;
	400	table->virt = virt;
	401	table->num_icm = num_icm;
	402	table->num_obj = nobj;
	403	table->obj_size = obj_size;
	404	table->lowmem = use_lowmem;
5b0bf5e2	405	table->coherent = use_coherent;
225c7b1f RD	406	mutex_init(&table->mutex);
	407
	408	for (i = 0; i * MLX4_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) {
	409	chunk_size = MLX4_TABLE_CHUNK_SIZE;
	410	if ((i + 1) * MLX4_TABLE_CHUNK_SIZE > nobj * obj_size)
	411	chunk_size = PAGE_ALIGN(nobj * obj_size - i * MLX4_TABLE_CHUNK_SIZE);
	412
	413	table->icm[i] = mlx4_alloc_icm(dev, chunk_size >> PAGE_SHIFT,
	414	(use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) \|
5b0bf5e2	415	__GFP_NOWARN, use_coherent);
225c7b1f RD	416	if (!table->icm[i])
	417	goto err;
	418	if (mlx4_MAP_ICM(dev, table->icm[i], virt + i * MLX4_TABLE_CHUNK_SIZE)) {
5b0bf5e2	419	mlx4_free_icm(dev, table->icm[i], use_coherent);
225c7b1f RD	420	table->icm[i] = NULL;
	421	goto err;
	422	}
	423
	424	/*
	425	* Add a reference to this ICM chunk so that it never
	426	* gets freed (since it contains reserved firmware objects).
	427	*/
	428	++table->icm[i]->refcount;
	429	}
	430
	431	return 0;
	432
	433	err:
	434	for (i = 0; i < num_icm; ++i)
	435	if (table->icm[i]) {
	436	mlx4_UNMAP_ICM(dev, virt + i * MLX4_TABLE_CHUNK_SIZE,
	437	MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
5b0bf5e2	438	mlx4_free_icm(dev, table->icm[i], use_coherent);
225c7b1f RD	439	}
	440
	441	return -ENOMEM;
	442	}
	443
	444	void mlx4_cleanup_icm_table(struct mlx4_dev dev, struct mlx4_icm_table table)
	445	{
	446	int i;
	447
	448	for (i = 0; i < table->num_icm; ++i)
	449	if (table->icm[i]) {
	450	mlx4_UNMAP_ICM(dev, table->virt + i * MLX4_TABLE_CHUNK_SIZE,
	451	MLX4_TABLE_CHUNK_SIZE / MLX4_ICM_PAGE_SIZE);
5b0bf5e2	452	mlx4_free_icm(dev, table->icm[i], table->coherent);
225c7b1f RD	453	}
	454
	455	kfree(table->icm);
	456	}