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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. | |
51a379d0 | 4 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
5 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/errno.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | ||
42 | #include <linux/mlx4/device.h> | |
43 | #include <linux/mlx4/doorbell.h> | |
44 | ||
45 | #include "mlx4.h" | |
46 | #include "fw.h" | |
47 | #include "icm.h" | |
48 | ||
49 | MODULE_AUTHOR("Roland Dreier"); | |
50 | MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); | |
51 | MODULE_LICENSE("Dual BSD/GPL"); | |
52 | MODULE_VERSION(DRV_VERSION); | |
53 | ||
54 | #ifdef CONFIG_MLX4_DEBUG | |
55 | ||
56 | int mlx4_debug_level = 0; | |
57 | module_param_named(debug_level, mlx4_debug_level, int, 0644); | |
58 | MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); | |
59 | ||
60 | #endif /* CONFIG_MLX4_DEBUG */ | |
61 | ||
62 | #ifdef CONFIG_PCI_MSI | |
63 | ||
08fb1055 | 64 | static int msi_x = 1; |
225c7b1f RD |
65 | module_param(msi_x, int, 0444); |
66 | MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); | |
67 | ||
68 | #else /* CONFIG_PCI_MSI */ | |
69 | ||
70 | #define msi_x (0) | |
71 | ||
72 | #endif /* CONFIG_PCI_MSI */ | |
73 | ||
f33afc26 | 74 | static char mlx4_version[] __devinitdata = |
225c7b1f RD |
75 | DRV_NAME ": Mellanox ConnectX core driver v" |
76 | DRV_VERSION " (" DRV_RELDATE ")\n"; | |
77 | ||
78 | static struct mlx4_profile default_profile = { | |
9b1f3851 | 79 | .num_qp = 1 << 17, |
225c7b1f | 80 | .num_srq = 1 << 16, |
c9f2ba5e | 81 | .rdmarc_per_qp = 1 << 4, |
225c7b1f RD |
82 | .num_cq = 1 << 16, |
83 | .num_mcg = 1 << 13, | |
84 | .num_mpt = 1 << 17, | |
85 | .num_mtt = 1 << 20, | |
86 | }; | |
87 | ||
93fc9e1b YP |
88 | static int log_num_mac = 2; |
89 | module_param_named(log_num_mac, log_num_mac, int, 0444); | |
90 | MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); | |
91 | ||
92 | static int log_num_vlan; | |
93 | module_param_named(log_num_vlan, log_num_vlan, int, 0444); | |
94 | MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); | |
95 | ||
96 | static int use_prio; | |
97 | module_param_named(use_prio, use_prio, bool, 0444); | |
98 | MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports " | |
99 | "(0/1, default 0)"); | |
100 | ||
7ff93f8b YP |
101 | static int mlx4_check_port_params(struct mlx4_dev *dev, |
102 | enum mlx4_port_type *port_type) | |
103 | { | |
104 | int i; | |
105 | ||
106 | for (i = 0; i < dev->caps.num_ports - 1; i++) { | |
107 | if (port_type[i] != port_type[i+1] && | |
108 | !(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { | |
109 | mlx4_err(dev, "Only same port types supported " | |
110 | "on this HCA, aborting.\n"); | |
111 | return -EINVAL; | |
112 | } | |
113 | } | |
114 | if ((port_type[0] == MLX4_PORT_TYPE_ETH) && | |
115 | (port_type[1] == MLX4_PORT_TYPE_IB)) { | |
116 | mlx4_err(dev, "eth-ib configuration is not supported.\n"); | |
117 | return -EINVAL; | |
118 | } | |
119 | ||
120 | for (i = 0; i < dev->caps.num_ports; i++) { | |
121 | if (!(port_type[i] & dev->caps.supported_type[i+1])) { | |
122 | mlx4_err(dev, "Requested port type for port %d is not " | |
123 | "supported on this HCA\n", i + 1); | |
124 | return -EINVAL; | |
125 | } | |
126 | } | |
127 | return 0; | |
128 | } | |
129 | ||
130 | static void mlx4_set_port_mask(struct mlx4_dev *dev) | |
131 | { | |
132 | int i; | |
133 | ||
134 | dev->caps.port_mask = 0; | |
135 | for (i = 1; i <= dev->caps.num_ports; ++i) | |
136 | if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB) | |
137 | dev->caps.port_mask |= 1 << (i - 1); | |
138 | } | |
3d73c288 | 139 | static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
225c7b1f RD |
140 | { |
141 | int err; | |
5ae2a7a8 | 142 | int i; |
225c7b1f RD |
143 | |
144 | err = mlx4_QUERY_DEV_CAP(dev, dev_cap); | |
145 | if (err) { | |
146 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
147 | return err; | |
148 | } | |
149 | ||
150 | if (dev_cap->min_page_sz > PAGE_SIZE) { | |
151 | mlx4_err(dev, "HCA minimum page size of %d bigger than " | |
152 | "kernel PAGE_SIZE of %ld, aborting.\n", | |
153 | dev_cap->min_page_sz, PAGE_SIZE); | |
154 | return -ENODEV; | |
155 | } | |
156 | if (dev_cap->num_ports > MLX4_MAX_PORTS) { | |
157 | mlx4_err(dev, "HCA has %d ports, but we only support %d, " | |
158 | "aborting.\n", | |
159 | dev_cap->num_ports, MLX4_MAX_PORTS); | |
160 | return -ENODEV; | |
161 | } | |
162 | ||
163 | if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { | |
164 | mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than " | |
165 | "PCI resource 2 size of 0x%llx, aborting.\n", | |
166 | dev_cap->uar_size, | |
167 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
168 | return -ENODEV; | |
169 | } | |
170 | ||
171 | dev->caps.num_ports = dev_cap->num_ports; | |
5ae2a7a8 RD |
172 | for (i = 1; i <= dev->caps.num_ports; ++i) { |
173 | dev->caps.vl_cap[i] = dev_cap->max_vl[i]; | |
b79acb49 | 174 | dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; |
5ae2a7a8 RD |
175 | dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; |
176 | dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; | |
177 | dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; | |
b79acb49 YP |
178 | dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; |
179 | dev->caps.def_mac[i] = dev_cap->def_mac[i]; | |
7ff93f8b | 180 | dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; |
5ae2a7a8 RD |
181 | } |
182 | ||
225c7b1f | 183 | dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; |
225c7b1f RD |
184 | dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; |
185 | dev->caps.bf_reg_size = dev_cap->bf_reg_size; | |
186 | dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; | |
187 | dev->caps.max_sq_sg = dev_cap->max_sq_sg; | |
188 | dev->caps.max_rq_sg = dev_cap->max_rq_sg; | |
189 | dev->caps.max_wqes = dev_cap->max_qp_sz; | |
190 | dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; | |
225c7b1f RD |
191 | dev->caps.max_srq_wqes = dev_cap->max_srq_sz; |
192 | dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; | |
193 | dev->caps.reserved_srqs = dev_cap->reserved_srqs; | |
194 | dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; | |
195 | dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; | |
196 | dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM; | |
197 | /* | |
198 | * Subtract 1 from the limit because we need to allocate a | |
199 | * spare CQE so the HCA HW can tell the difference between an | |
200 | * empty CQ and a full CQ. | |
201 | */ | |
202 | dev->caps.max_cqes = dev_cap->max_cq_sz - 1; | |
203 | dev->caps.reserved_cqs = dev_cap->reserved_cqs; | |
204 | dev->caps.reserved_eqs = dev_cap->reserved_eqs; | |
121964ec RD |
205 | dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts, |
206 | MLX4_MTT_ENTRY_PER_SEG); | |
225c7b1f RD |
207 | dev->caps.reserved_mrws = dev_cap->reserved_mrws; |
208 | dev->caps.reserved_uars = dev_cap->reserved_uars; | |
209 | dev->caps.reserved_pds = dev_cap->reserved_pds; | |
225c7b1f | 210 | dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz; |
149983af | 211 | dev->caps.max_msg_sz = dev_cap->max_msg_sz; |
225c7b1f RD |
212 | dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); |
213 | dev->caps.flags = dev_cap->flags; | |
95d04f07 RD |
214 | dev->caps.bmme_flags = dev_cap->bmme_flags; |
215 | dev->caps.reserved_lkey = dev_cap->reserved_lkey; | |
225c7b1f | 216 | dev->caps.stat_rate_support = dev_cap->stat_rate_support; |
b832be1e | 217 | dev->caps.max_gso_sz = dev_cap->max_gso_sz; |
225c7b1f | 218 | |
93fc9e1b YP |
219 | dev->caps.log_num_macs = log_num_mac; |
220 | dev->caps.log_num_vlans = log_num_vlan; | |
221 | dev->caps.log_num_prios = use_prio ? 3 : 0; | |
222 | ||
223 | for (i = 1; i <= dev->caps.num_ports; ++i) { | |
7ff93f8b YP |
224 | if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH) |
225 | dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; | |
226 | else | |
227 | dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; | |
228 | ||
93fc9e1b YP |
229 | if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { |
230 | dev->caps.log_num_macs = dev_cap->log_max_macs[i]; | |
231 | mlx4_warn(dev, "Requested number of MACs is too much " | |
232 | "for port %d, reducing to %d.\n", | |
233 | i, 1 << dev->caps.log_num_macs); | |
234 | } | |
235 | if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { | |
236 | dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; | |
237 | mlx4_warn(dev, "Requested number of VLANs is too much " | |
238 | "for port %d, reducing to %d.\n", | |
239 | i, 1 << dev->caps.log_num_vlans); | |
240 | } | |
241 | } | |
242 | ||
7ff93f8b YP |
243 | mlx4_set_port_mask(dev); |
244 | ||
93fc9e1b YP |
245 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; |
246 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = | |
247 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = | |
248 | (1 << dev->caps.log_num_macs) * | |
249 | (1 << dev->caps.log_num_vlans) * | |
250 | (1 << dev->caps.log_num_prios) * | |
251 | dev->caps.num_ports; | |
252 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; | |
253 | ||
254 | dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + | |
255 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + | |
256 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + | |
257 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; | |
258 | ||
225c7b1f RD |
259 | return 0; |
260 | } | |
261 | ||
7ff93f8b YP |
262 | /* |
263 | * Change the port configuration of the device. | |
264 | * Every user of this function must hold the port mutex. | |
265 | */ | |
266 | static int mlx4_change_port_types(struct mlx4_dev *dev, | |
267 | enum mlx4_port_type *port_types) | |
268 | { | |
269 | int err = 0; | |
270 | int change = 0; | |
271 | int port; | |
272 | ||
273 | for (port = 0; port < dev->caps.num_ports; port++) { | |
274 | if (port_types[port] != dev->caps.port_type[port + 1]) { | |
275 | change = 1; | |
276 | dev->caps.port_type[port + 1] = port_types[port]; | |
277 | } | |
278 | } | |
279 | if (change) { | |
280 | mlx4_unregister_device(dev); | |
281 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
282 | mlx4_CLOSE_PORT(dev, port); | |
283 | err = mlx4_SET_PORT(dev, port); | |
284 | if (err) { | |
285 | mlx4_err(dev, "Failed to set port %d, " | |
286 | "aborting\n", port); | |
287 | goto out; | |
288 | } | |
289 | } | |
290 | mlx4_set_port_mask(dev); | |
291 | err = mlx4_register_device(dev); | |
292 | } | |
293 | ||
294 | out: | |
295 | return err; | |
296 | } | |
297 | ||
298 | static ssize_t show_port_type(struct device *dev, | |
299 | struct device_attribute *attr, | |
300 | char *buf) | |
301 | { | |
302 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
303 | port_attr); | |
304 | struct mlx4_dev *mdev = info->dev; | |
305 | ||
306 | return sprintf(buf, "%s\n", | |
307 | mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB ? | |
308 | "ib" : "eth"); | |
309 | } | |
310 | ||
311 | static ssize_t set_port_type(struct device *dev, | |
312 | struct device_attribute *attr, | |
313 | const char *buf, size_t count) | |
314 | { | |
315 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
316 | port_attr); | |
317 | struct mlx4_dev *mdev = info->dev; | |
318 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
319 | enum mlx4_port_type types[MLX4_MAX_PORTS]; | |
320 | int i; | |
321 | int err = 0; | |
322 | ||
323 | if (!strcmp(buf, "ib\n")) | |
324 | info->tmp_type = MLX4_PORT_TYPE_IB; | |
325 | else if (!strcmp(buf, "eth\n")) | |
326 | info->tmp_type = MLX4_PORT_TYPE_ETH; | |
327 | else { | |
328 | mlx4_err(mdev, "%s is not supported port type\n", buf); | |
329 | return -EINVAL; | |
330 | } | |
331 | ||
332 | mutex_lock(&priv->port_mutex); | |
333 | for (i = 0; i < mdev->caps.num_ports; i++) | |
334 | types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : | |
335 | mdev->caps.port_type[i+1]; | |
336 | ||
337 | err = mlx4_check_port_params(mdev, types); | |
338 | if (err) | |
339 | goto out; | |
340 | ||
341 | for (i = 1; i <= mdev->caps.num_ports; i++) | |
342 | priv->port[i].tmp_type = 0; | |
343 | ||
344 | err = mlx4_change_port_types(mdev, types); | |
345 | ||
346 | out: | |
347 | mutex_unlock(&priv->port_mutex); | |
348 | return err ? err : count; | |
349 | } | |
350 | ||
e8f9b2ed | 351 | static int mlx4_load_fw(struct mlx4_dev *dev) |
225c7b1f RD |
352 | { |
353 | struct mlx4_priv *priv = mlx4_priv(dev); | |
354 | int err; | |
355 | ||
356 | priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, | |
5b0bf5e2 | 357 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f RD |
358 | if (!priv->fw.fw_icm) { |
359 | mlx4_err(dev, "Couldn't allocate FW area, aborting.\n"); | |
360 | return -ENOMEM; | |
361 | } | |
362 | ||
363 | err = mlx4_MAP_FA(dev, priv->fw.fw_icm); | |
364 | if (err) { | |
365 | mlx4_err(dev, "MAP_FA command failed, aborting.\n"); | |
366 | goto err_free; | |
367 | } | |
368 | ||
369 | err = mlx4_RUN_FW(dev); | |
370 | if (err) { | |
371 | mlx4_err(dev, "RUN_FW command failed, aborting.\n"); | |
372 | goto err_unmap_fa; | |
373 | } | |
374 | ||
375 | return 0; | |
376 | ||
377 | err_unmap_fa: | |
378 | mlx4_UNMAP_FA(dev); | |
379 | ||
380 | err_free: | |
5b0bf5e2 | 381 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); |
225c7b1f RD |
382 | return err; |
383 | } | |
384 | ||
e8f9b2ed RD |
385 | static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, |
386 | int cmpt_entry_sz) | |
225c7b1f RD |
387 | { |
388 | struct mlx4_priv *priv = mlx4_priv(dev); | |
389 | int err; | |
390 | ||
391 | err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, | |
392 | cmpt_base + | |
393 | ((u64) (MLX4_CMPT_TYPE_QP * | |
394 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
395 | cmpt_entry_sz, dev->caps.num_qps, | |
93fc9e1b YP |
396 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
397 | 0, 0); | |
225c7b1f RD |
398 | if (err) |
399 | goto err; | |
400 | ||
401 | err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, | |
402 | cmpt_base + | |
403 | ((u64) (MLX4_CMPT_TYPE_SRQ * | |
404 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
405 | cmpt_entry_sz, dev->caps.num_srqs, | |
5b0bf5e2 | 406 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f RD |
407 | if (err) |
408 | goto err_qp; | |
409 | ||
410 | err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, | |
411 | cmpt_base + | |
412 | ((u64) (MLX4_CMPT_TYPE_CQ * | |
413 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
414 | cmpt_entry_sz, dev->caps.num_cqs, | |
5b0bf5e2 | 415 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f RD |
416 | if (err) |
417 | goto err_srq; | |
418 | ||
419 | err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, | |
420 | cmpt_base + | |
421 | ((u64) (MLX4_CMPT_TYPE_EQ * | |
422 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
423 | cmpt_entry_sz, | |
b8dd786f | 424 | dev->caps.num_eqs, dev->caps.num_eqs, 0, 0); |
225c7b1f RD |
425 | if (err) |
426 | goto err_cq; | |
427 | ||
428 | return 0; | |
429 | ||
430 | err_cq: | |
431 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
432 | ||
433 | err_srq: | |
434 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
435 | ||
436 | err_qp: | |
437 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
438 | ||
439 | err: | |
440 | return err; | |
441 | } | |
442 | ||
3d73c288 RD |
443 | static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, |
444 | struct mlx4_init_hca_param *init_hca, u64 icm_size) | |
225c7b1f RD |
445 | { |
446 | struct mlx4_priv *priv = mlx4_priv(dev); | |
447 | u64 aux_pages; | |
448 | int err; | |
449 | ||
450 | err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); | |
451 | if (err) { | |
452 | mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n"); | |
453 | return err; | |
454 | } | |
455 | ||
456 | mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n", | |
457 | (unsigned long long) icm_size >> 10, | |
458 | (unsigned long long) aux_pages << 2); | |
459 | ||
460 | priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, | |
5b0bf5e2 | 461 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f RD |
462 | if (!priv->fw.aux_icm) { |
463 | mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n"); | |
464 | return -ENOMEM; | |
465 | } | |
466 | ||
467 | err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); | |
468 | if (err) { | |
469 | mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n"); | |
470 | goto err_free_aux; | |
471 | } | |
472 | ||
473 | err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); | |
474 | if (err) { | |
475 | mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n"); | |
476 | goto err_unmap_aux; | |
477 | } | |
478 | ||
479 | err = mlx4_map_eq_icm(dev, init_hca->eqc_base); | |
480 | if (err) { | |
481 | mlx4_err(dev, "Failed to map EQ context memory, aborting.\n"); | |
482 | goto err_unmap_cmpt; | |
483 | } | |
484 | ||
d7bb58fb JM |
485 | /* |
486 | * Reserved MTT entries must be aligned up to a cacheline | |
487 | * boundary, since the FW will write to them, while the driver | |
488 | * writes to all other MTT entries. (The variable | |
489 | * dev->caps.mtt_entry_sz below is really the MTT segment | |
490 | * size, not the raw entry size) | |
491 | */ | |
492 | dev->caps.reserved_mtts = | |
493 | ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, | |
494 | dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; | |
495 | ||
225c7b1f RD |
496 | err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, |
497 | init_hca->mtt_base, | |
498 | dev->caps.mtt_entry_sz, | |
499 | dev->caps.num_mtt_segs, | |
5b0bf5e2 | 500 | dev->caps.reserved_mtts, 1, 0); |
225c7b1f RD |
501 | if (err) { |
502 | mlx4_err(dev, "Failed to map MTT context memory, aborting.\n"); | |
503 | goto err_unmap_eq; | |
504 | } | |
505 | ||
506 | err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, | |
507 | init_hca->dmpt_base, | |
508 | dev_cap->dmpt_entry_sz, | |
509 | dev->caps.num_mpts, | |
5b0bf5e2 | 510 | dev->caps.reserved_mrws, 1, 1); |
225c7b1f RD |
511 | if (err) { |
512 | mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n"); | |
513 | goto err_unmap_mtt; | |
514 | } | |
515 | ||
516 | err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, | |
517 | init_hca->qpc_base, | |
518 | dev_cap->qpc_entry_sz, | |
519 | dev->caps.num_qps, | |
93fc9e1b YP |
520 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
521 | 0, 0); | |
225c7b1f RD |
522 | if (err) { |
523 | mlx4_err(dev, "Failed to map QP context memory, aborting.\n"); | |
524 | goto err_unmap_dmpt; | |
525 | } | |
526 | ||
527 | err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, | |
528 | init_hca->auxc_base, | |
529 | dev_cap->aux_entry_sz, | |
530 | dev->caps.num_qps, | |
93fc9e1b YP |
531 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
532 | 0, 0); | |
225c7b1f RD |
533 | if (err) { |
534 | mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n"); | |
535 | goto err_unmap_qp; | |
536 | } | |
537 | ||
538 | err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, | |
539 | init_hca->altc_base, | |
540 | dev_cap->altc_entry_sz, | |
541 | dev->caps.num_qps, | |
93fc9e1b YP |
542 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
543 | 0, 0); | |
225c7b1f RD |
544 | if (err) { |
545 | mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n"); | |
546 | goto err_unmap_auxc; | |
547 | } | |
548 | ||
549 | err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, | |
550 | init_hca->rdmarc_base, | |
551 | dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, | |
552 | dev->caps.num_qps, | |
93fc9e1b YP |
553 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
554 | 0, 0); | |
225c7b1f RD |
555 | if (err) { |
556 | mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); | |
557 | goto err_unmap_altc; | |
558 | } | |
559 | ||
560 | err = mlx4_init_icm_table(dev, &priv->cq_table.table, | |
561 | init_hca->cqc_base, | |
562 | dev_cap->cqc_entry_sz, | |
563 | dev->caps.num_cqs, | |
5b0bf5e2 | 564 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f RD |
565 | if (err) { |
566 | mlx4_err(dev, "Failed to map CQ context memory, aborting.\n"); | |
567 | goto err_unmap_rdmarc; | |
568 | } | |
569 | ||
570 | err = mlx4_init_icm_table(dev, &priv->srq_table.table, | |
571 | init_hca->srqc_base, | |
572 | dev_cap->srq_entry_sz, | |
573 | dev->caps.num_srqs, | |
5b0bf5e2 | 574 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f RD |
575 | if (err) { |
576 | mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n"); | |
577 | goto err_unmap_cq; | |
578 | } | |
579 | ||
580 | /* | |
581 | * It's not strictly required, but for simplicity just map the | |
582 | * whole multicast group table now. The table isn't very big | |
583 | * and it's a lot easier than trying to track ref counts. | |
584 | */ | |
585 | err = mlx4_init_icm_table(dev, &priv->mcg_table.table, | |
586 | init_hca->mc_base, MLX4_MGM_ENTRY_SIZE, | |
587 | dev->caps.num_mgms + dev->caps.num_amgms, | |
588 | dev->caps.num_mgms + dev->caps.num_amgms, | |
5b0bf5e2 | 589 | 0, 0); |
225c7b1f RD |
590 | if (err) { |
591 | mlx4_err(dev, "Failed to map MCG context memory, aborting.\n"); | |
592 | goto err_unmap_srq; | |
593 | } | |
594 | ||
595 | return 0; | |
596 | ||
597 | err_unmap_srq: | |
598 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
599 | ||
600 | err_unmap_cq: | |
601 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
602 | ||
603 | err_unmap_rdmarc: | |
604 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
605 | ||
606 | err_unmap_altc: | |
607 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
608 | ||
609 | err_unmap_auxc: | |
610 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
611 | ||
612 | err_unmap_qp: | |
613 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
614 | ||
615 | err_unmap_dmpt: | |
616 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
617 | ||
618 | err_unmap_mtt: | |
619 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
620 | ||
621 | err_unmap_eq: | |
622 | mlx4_unmap_eq_icm(dev); | |
623 | ||
624 | err_unmap_cmpt: | |
625 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); | |
626 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
627 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
628 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
629 | ||
630 | err_unmap_aux: | |
631 | mlx4_UNMAP_ICM_AUX(dev); | |
632 | ||
633 | err_free_aux: | |
5b0bf5e2 | 634 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
635 | |
636 | return err; | |
637 | } | |
638 | ||
639 | static void mlx4_free_icms(struct mlx4_dev *dev) | |
640 | { | |
641 | struct mlx4_priv *priv = mlx4_priv(dev); | |
642 | ||
643 | mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); | |
644 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
645 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
646 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
647 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
648 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
649 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
650 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
651 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
652 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); | |
653 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
654 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
655 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
656 | mlx4_unmap_eq_icm(dev); | |
657 | ||
658 | mlx4_UNMAP_ICM_AUX(dev); | |
5b0bf5e2 | 659 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
660 | } |
661 | ||
662 | static void mlx4_close_hca(struct mlx4_dev *dev) | |
663 | { | |
664 | mlx4_CLOSE_HCA(dev, 0); | |
665 | mlx4_free_icms(dev); | |
666 | mlx4_UNMAP_FA(dev); | |
5b0bf5e2 | 667 | mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); |
225c7b1f RD |
668 | } |
669 | ||
3d73c288 | 670 | static int mlx4_init_hca(struct mlx4_dev *dev) |
225c7b1f RD |
671 | { |
672 | struct mlx4_priv *priv = mlx4_priv(dev); | |
673 | struct mlx4_adapter adapter; | |
674 | struct mlx4_dev_cap dev_cap; | |
2d928651 | 675 | struct mlx4_mod_stat_cfg mlx4_cfg; |
225c7b1f RD |
676 | struct mlx4_profile profile; |
677 | struct mlx4_init_hca_param init_hca; | |
678 | u64 icm_size; | |
679 | int err; | |
680 | ||
681 | err = mlx4_QUERY_FW(dev); | |
682 | if (err) { | |
683 | mlx4_err(dev, "QUERY_FW command failed, aborting.\n"); | |
684 | return err; | |
685 | } | |
686 | ||
687 | err = mlx4_load_fw(dev); | |
688 | if (err) { | |
689 | mlx4_err(dev, "Failed to start FW, aborting.\n"); | |
690 | return err; | |
691 | } | |
692 | ||
2d928651 VS |
693 | mlx4_cfg.log_pg_sz_m = 1; |
694 | mlx4_cfg.log_pg_sz = 0; | |
695 | err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); | |
696 | if (err) | |
697 | mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); | |
698 | ||
225c7b1f RD |
699 | err = mlx4_dev_cap(dev, &dev_cap); |
700 | if (err) { | |
701 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
702 | goto err_stop_fw; | |
703 | } | |
704 | ||
705 | profile = default_profile; | |
706 | ||
707 | icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca); | |
708 | if ((long long) icm_size < 0) { | |
709 | err = icm_size; | |
710 | goto err_stop_fw; | |
711 | } | |
712 | ||
713 | init_hca.log_uar_sz = ilog2(dev->caps.num_uars); | |
714 | ||
715 | err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); | |
716 | if (err) | |
717 | goto err_stop_fw; | |
718 | ||
719 | err = mlx4_INIT_HCA(dev, &init_hca); | |
720 | if (err) { | |
721 | mlx4_err(dev, "INIT_HCA command failed, aborting.\n"); | |
722 | goto err_free_icm; | |
723 | } | |
724 | ||
725 | err = mlx4_QUERY_ADAPTER(dev, &adapter); | |
726 | if (err) { | |
727 | mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n"); | |
728 | goto err_close; | |
729 | } | |
730 | ||
731 | priv->eq_table.inta_pin = adapter.inta_pin; | |
cd9281d8 | 732 | memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); |
225c7b1f RD |
733 | |
734 | return 0; | |
735 | ||
736 | err_close: | |
737 | mlx4_close_hca(dev); | |
738 | ||
739 | err_free_icm: | |
740 | mlx4_free_icms(dev); | |
741 | ||
742 | err_stop_fw: | |
743 | mlx4_UNMAP_FA(dev); | |
5b0bf5e2 | 744 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); |
225c7b1f RD |
745 | |
746 | return err; | |
747 | } | |
748 | ||
3d73c288 | 749 | static int mlx4_setup_hca(struct mlx4_dev *dev) |
225c7b1f RD |
750 | { |
751 | struct mlx4_priv *priv = mlx4_priv(dev); | |
752 | int err; | |
7ff93f8b | 753 | int port; |
9a5aa622 | 754 | __be32 ib_port_default_caps; |
225c7b1f | 755 | |
225c7b1f RD |
756 | err = mlx4_init_uar_table(dev); |
757 | if (err) { | |
758 | mlx4_err(dev, "Failed to initialize " | |
759 | "user access region table, aborting.\n"); | |
760 | return err; | |
761 | } | |
762 | ||
763 | err = mlx4_uar_alloc(dev, &priv->driver_uar); | |
764 | if (err) { | |
765 | mlx4_err(dev, "Failed to allocate driver access region, " | |
766 | "aborting.\n"); | |
767 | goto err_uar_table_free; | |
768 | } | |
769 | ||
770 | priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); | |
771 | if (!priv->kar) { | |
772 | mlx4_err(dev, "Couldn't map kernel access region, " | |
773 | "aborting.\n"); | |
774 | err = -ENOMEM; | |
775 | goto err_uar_free; | |
776 | } | |
777 | ||
778 | err = mlx4_init_pd_table(dev); | |
779 | if (err) { | |
780 | mlx4_err(dev, "Failed to initialize " | |
781 | "protection domain table, aborting.\n"); | |
782 | goto err_kar_unmap; | |
783 | } | |
784 | ||
785 | err = mlx4_init_mr_table(dev); | |
786 | if (err) { | |
787 | mlx4_err(dev, "Failed to initialize " | |
788 | "memory region table, aborting.\n"); | |
789 | goto err_pd_table_free; | |
790 | } | |
791 | ||
225c7b1f RD |
792 | err = mlx4_init_eq_table(dev); |
793 | if (err) { | |
794 | mlx4_err(dev, "Failed to initialize " | |
795 | "event queue table, aborting.\n"); | |
ee49bd93 | 796 | goto err_mr_table_free; |
225c7b1f RD |
797 | } |
798 | ||
799 | err = mlx4_cmd_use_events(dev); | |
800 | if (err) { | |
801 | mlx4_err(dev, "Failed to switch to event-driven " | |
802 | "firmware commands, aborting.\n"); | |
803 | goto err_eq_table_free; | |
804 | } | |
805 | ||
806 | err = mlx4_NOP(dev); | |
807 | if (err) { | |
08fb1055 MT |
808 | if (dev->flags & MLX4_FLAG_MSI_X) { |
809 | mlx4_warn(dev, "NOP command failed to generate MSI-X " | |
810 | "interrupt IRQ %d).\n", | |
b8dd786f | 811 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
08fb1055 MT |
812 | mlx4_warn(dev, "Trying again without MSI-X.\n"); |
813 | } else { | |
814 | mlx4_err(dev, "NOP command failed to generate interrupt " | |
815 | "(IRQ %d), aborting.\n", | |
b8dd786f | 816 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
225c7b1f | 817 | mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); |
08fb1055 | 818 | } |
225c7b1f RD |
819 | |
820 | goto err_cmd_poll; | |
821 | } | |
822 | ||
823 | mlx4_dbg(dev, "NOP command IRQ test passed\n"); | |
824 | ||
825 | err = mlx4_init_cq_table(dev); | |
826 | if (err) { | |
827 | mlx4_err(dev, "Failed to initialize " | |
828 | "completion queue table, aborting.\n"); | |
829 | goto err_cmd_poll; | |
830 | } | |
831 | ||
832 | err = mlx4_init_srq_table(dev); | |
833 | if (err) { | |
834 | mlx4_err(dev, "Failed to initialize " | |
835 | "shared receive queue table, aborting.\n"); | |
836 | goto err_cq_table_free; | |
837 | } | |
838 | ||
839 | err = mlx4_init_qp_table(dev); | |
840 | if (err) { | |
841 | mlx4_err(dev, "Failed to initialize " | |
842 | "queue pair table, aborting.\n"); | |
843 | goto err_srq_table_free; | |
844 | } | |
845 | ||
846 | err = mlx4_init_mcg_table(dev); | |
847 | if (err) { | |
848 | mlx4_err(dev, "Failed to initialize " | |
849 | "multicast group table, aborting.\n"); | |
850 | goto err_qp_table_free; | |
851 | } | |
852 | ||
7ff93f8b | 853 | for (port = 1; port <= dev->caps.num_ports; port++) { |
9a5aa622 JM |
854 | ib_port_default_caps = 0; |
855 | err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps); | |
856 | if (err) | |
857 | mlx4_warn(dev, "failed to get port %d default " | |
858 | "ib capabilities (%d). Continuing with " | |
859 | "caps = 0\n", port, err); | |
860 | dev->caps.ib_port_def_cap[port] = ib_port_default_caps; | |
7ff93f8b YP |
861 | err = mlx4_SET_PORT(dev, port); |
862 | if (err) { | |
863 | mlx4_err(dev, "Failed to set port %d, aborting\n", | |
864 | port); | |
865 | goto err_mcg_table_free; | |
866 | } | |
867 | } | |
868 | ||
225c7b1f RD |
869 | return 0; |
870 | ||
7ff93f8b YP |
871 | err_mcg_table_free: |
872 | mlx4_cleanup_mcg_table(dev); | |
873 | ||
225c7b1f RD |
874 | err_qp_table_free: |
875 | mlx4_cleanup_qp_table(dev); | |
876 | ||
877 | err_srq_table_free: | |
878 | mlx4_cleanup_srq_table(dev); | |
879 | ||
880 | err_cq_table_free: | |
881 | mlx4_cleanup_cq_table(dev); | |
882 | ||
883 | err_cmd_poll: | |
884 | mlx4_cmd_use_polling(dev); | |
885 | ||
886 | err_eq_table_free: | |
887 | mlx4_cleanup_eq_table(dev); | |
888 | ||
ee49bd93 | 889 | err_mr_table_free: |
225c7b1f RD |
890 | mlx4_cleanup_mr_table(dev); |
891 | ||
892 | err_pd_table_free: | |
893 | mlx4_cleanup_pd_table(dev); | |
894 | ||
895 | err_kar_unmap: | |
896 | iounmap(priv->kar); | |
897 | ||
898 | err_uar_free: | |
899 | mlx4_uar_free(dev, &priv->driver_uar); | |
900 | ||
901 | err_uar_table_free: | |
902 | mlx4_cleanup_uar_table(dev); | |
903 | return err; | |
904 | } | |
905 | ||
e8f9b2ed | 906 | static void mlx4_enable_msi_x(struct mlx4_dev *dev) |
225c7b1f RD |
907 | { |
908 | struct mlx4_priv *priv = mlx4_priv(dev); | |
b8dd786f YP |
909 | struct msix_entry *entries; |
910 | int nreq; | |
225c7b1f RD |
911 | int err; |
912 | int i; | |
913 | ||
914 | if (msi_x) { | |
70cb9253 RD |
915 | nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, |
916 | num_possible_cpus() + 1); | |
b8dd786f YP |
917 | entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); |
918 | if (!entries) | |
919 | goto no_msi; | |
920 | ||
921 | for (i = 0; i < nreq; ++i) | |
225c7b1f RD |
922 | entries[i].entry = i; |
923 | ||
b8dd786f YP |
924 | retry: |
925 | err = pci_enable_msix(dev->pdev, entries, nreq); | |
225c7b1f | 926 | if (err) { |
b8dd786f YP |
927 | /* Try again if at least 2 vectors are available */ |
928 | if (err > 1) { | |
929 | mlx4_info(dev, "Requested %d vectors, " | |
930 | "but only %d MSI-X vectors available, " | |
931 | "trying again\n", nreq, err); | |
932 | nreq = err; | |
933 | goto retry; | |
934 | } | |
935 | ||
225c7b1f RD |
936 | goto no_msi; |
937 | } | |
938 | ||
b8dd786f YP |
939 | dev->caps.num_comp_vectors = nreq - 1; |
940 | for (i = 0; i < nreq; ++i) | |
225c7b1f RD |
941 | priv->eq_table.eq[i].irq = entries[i].vector; |
942 | ||
943 | dev->flags |= MLX4_FLAG_MSI_X; | |
b8dd786f YP |
944 | |
945 | kfree(entries); | |
225c7b1f RD |
946 | return; |
947 | } | |
948 | ||
949 | no_msi: | |
b8dd786f YP |
950 | dev->caps.num_comp_vectors = 1; |
951 | ||
952 | for (i = 0; i < 2; ++i) | |
225c7b1f RD |
953 | priv->eq_table.eq[i].irq = dev->pdev->irq; |
954 | } | |
955 | ||
7ff93f8b | 956 | static int mlx4_init_port_info(struct mlx4_dev *dev, int port) |
2a2336f8 YP |
957 | { |
958 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
7ff93f8b | 959 | int err = 0; |
2a2336f8 YP |
960 | |
961 | info->dev = dev; | |
962 | info->port = port; | |
963 | mlx4_init_mac_table(dev, &info->mac_table); | |
964 | mlx4_init_vlan_table(dev, &info->vlan_table); | |
7ff93f8b YP |
965 | |
966 | sprintf(info->dev_name, "mlx4_port%d", port); | |
967 | info->port_attr.attr.name = info->dev_name; | |
968 | info->port_attr.attr.mode = S_IRUGO | S_IWUSR; | |
969 | info->port_attr.show = show_port_type; | |
970 | info->port_attr.store = set_port_type; | |
971 | ||
972 | err = device_create_file(&dev->pdev->dev, &info->port_attr); | |
973 | if (err) { | |
974 | mlx4_err(dev, "Failed to create file for port %d\n", port); | |
975 | info->port = -1; | |
976 | } | |
977 | ||
978 | return err; | |
979 | } | |
980 | ||
981 | static void mlx4_cleanup_port_info(struct mlx4_port_info *info) | |
982 | { | |
983 | if (info->port < 0) | |
984 | return; | |
985 | ||
986 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
2a2336f8 YP |
987 | } |
988 | ||
3d73c288 | 989 | static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
225c7b1f | 990 | { |
225c7b1f RD |
991 | struct mlx4_priv *priv; |
992 | struct mlx4_dev *dev; | |
993 | int err; | |
2a2336f8 | 994 | int port; |
225c7b1f | 995 | |
225c7b1f RD |
996 | printk(KERN_INFO PFX "Initializing %s\n", |
997 | pci_name(pdev)); | |
998 | ||
999 | err = pci_enable_device(pdev); | |
1000 | if (err) { | |
1001 | dev_err(&pdev->dev, "Cannot enable PCI device, " | |
1002 | "aborting.\n"); | |
1003 | return err; | |
1004 | } | |
1005 | ||
1006 | /* | |
4ff08a76 | 1007 | * Check for BARs. We expect 0: 1MB |
225c7b1f RD |
1008 | */ |
1009 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || | |
1010 | pci_resource_len(pdev, 0) != 1 << 20) { | |
1011 | dev_err(&pdev->dev, "Missing DCS, aborting.\n"); | |
1012 | err = -ENODEV; | |
1013 | goto err_disable_pdev; | |
1014 | } | |
1015 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
1016 | dev_err(&pdev->dev, "Missing UAR, aborting.\n"); | |
1017 | err = -ENODEV; | |
1018 | goto err_disable_pdev; | |
1019 | } | |
1020 | ||
1021 | err = pci_request_region(pdev, 0, DRV_NAME); | |
1022 | if (err) { | |
1023 | dev_err(&pdev->dev, "Cannot request control region, aborting.\n"); | |
1024 | goto err_disable_pdev; | |
1025 | } | |
1026 | ||
1027 | err = pci_request_region(pdev, 2, DRV_NAME); | |
1028 | if (err) { | |
1029 | dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n"); | |
1030 | goto err_release_bar0; | |
1031 | } | |
1032 | ||
1033 | pci_set_master(pdev); | |
1034 | ||
1035 | err = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
1036 | if (err) { | |
1037 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); | |
1038 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1039 | if (err) { | |
1040 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); | |
1041 | goto err_release_bar2; | |
1042 | } | |
1043 | } | |
1044 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1045 | if (err) { | |
1046 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " | |
1047 | "consistent PCI DMA mask.\n"); | |
1048 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1049 | if (err) { | |
1050 | dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " | |
1051 | "aborting.\n"); | |
1052 | goto err_release_bar2; | |
1053 | } | |
1054 | } | |
1055 | ||
1056 | priv = kzalloc(sizeof *priv, GFP_KERNEL); | |
1057 | if (!priv) { | |
1058 | dev_err(&pdev->dev, "Device struct alloc failed, " | |
1059 | "aborting.\n"); | |
1060 | err = -ENOMEM; | |
1061 | goto err_release_bar2; | |
1062 | } | |
1063 | ||
1064 | dev = &priv->dev; | |
1065 | dev->pdev = pdev; | |
b581401e RD |
1066 | INIT_LIST_HEAD(&priv->ctx_list); |
1067 | spin_lock_init(&priv->ctx_lock); | |
225c7b1f | 1068 | |
7ff93f8b YP |
1069 | mutex_init(&priv->port_mutex); |
1070 | ||
6296883c YP |
1071 | INIT_LIST_HEAD(&priv->pgdir_list); |
1072 | mutex_init(&priv->pgdir_mutex); | |
1073 | ||
225c7b1f RD |
1074 | /* |
1075 | * Now reset the HCA before we touch the PCI capabilities or | |
1076 | * attempt a firmware command, since a boot ROM may have left | |
1077 | * the HCA in an undefined state. | |
1078 | */ | |
1079 | err = mlx4_reset(dev); | |
1080 | if (err) { | |
1081 | mlx4_err(dev, "Failed to reset HCA, aborting.\n"); | |
1082 | goto err_free_dev; | |
1083 | } | |
1084 | ||
225c7b1f RD |
1085 | if (mlx4_cmd_init(dev)) { |
1086 | mlx4_err(dev, "Failed to init command interface, aborting.\n"); | |
1087 | goto err_free_dev; | |
1088 | } | |
1089 | ||
1090 | err = mlx4_init_hca(dev); | |
1091 | if (err) | |
1092 | goto err_cmd; | |
1093 | ||
b8dd786f YP |
1094 | err = mlx4_alloc_eq_table(dev); |
1095 | if (err) | |
1096 | goto err_close; | |
1097 | ||
08fb1055 MT |
1098 | mlx4_enable_msi_x(dev); |
1099 | ||
225c7b1f | 1100 | err = mlx4_setup_hca(dev); |
08fb1055 MT |
1101 | if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) { |
1102 | dev->flags &= ~MLX4_FLAG_MSI_X; | |
1103 | pci_disable_msix(pdev); | |
1104 | err = mlx4_setup_hca(dev); | |
1105 | } | |
1106 | ||
225c7b1f | 1107 | if (err) |
b8dd786f | 1108 | goto err_free_eq; |
225c7b1f | 1109 | |
7ff93f8b YP |
1110 | for (port = 1; port <= dev->caps.num_ports; port++) { |
1111 | err = mlx4_init_port_info(dev, port); | |
1112 | if (err) | |
1113 | goto err_port; | |
1114 | } | |
2a2336f8 | 1115 | |
225c7b1f RD |
1116 | err = mlx4_register_device(dev); |
1117 | if (err) | |
7ff93f8b | 1118 | goto err_port; |
225c7b1f RD |
1119 | |
1120 | pci_set_drvdata(pdev, dev); | |
1121 | ||
1122 | return 0; | |
1123 | ||
7ff93f8b YP |
1124 | err_port: |
1125 | for (port = 1; port <= dev->caps.num_ports; port++) | |
1126 | mlx4_cleanup_port_info(&priv->port[port]); | |
1127 | ||
225c7b1f RD |
1128 | mlx4_cleanup_mcg_table(dev); |
1129 | mlx4_cleanup_qp_table(dev); | |
1130 | mlx4_cleanup_srq_table(dev); | |
1131 | mlx4_cleanup_cq_table(dev); | |
1132 | mlx4_cmd_use_polling(dev); | |
1133 | mlx4_cleanup_eq_table(dev); | |
225c7b1f RD |
1134 | mlx4_cleanup_mr_table(dev); |
1135 | mlx4_cleanup_pd_table(dev); | |
1136 | mlx4_cleanup_uar_table(dev); | |
1137 | ||
b8dd786f YP |
1138 | err_free_eq: |
1139 | mlx4_free_eq_table(dev); | |
1140 | ||
225c7b1f | 1141 | err_close: |
08fb1055 MT |
1142 | if (dev->flags & MLX4_FLAG_MSI_X) |
1143 | pci_disable_msix(pdev); | |
1144 | ||
225c7b1f RD |
1145 | mlx4_close_hca(dev); |
1146 | ||
1147 | err_cmd: | |
1148 | mlx4_cmd_cleanup(dev); | |
1149 | ||
1150 | err_free_dev: | |
225c7b1f RD |
1151 | kfree(priv); |
1152 | ||
1153 | err_release_bar2: | |
1154 | pci_release_region(pdev, 2); | |
1155 | ||
1156 | err_release_bar0: | |
1157 | pci_release_region(pdev, 0); | |
1158 | ||
1159 | err_disable_pdev: | |
1160 | pci_disable_device(pdev); | |
1161 | pci_set_drvdata(pdev, NULL); | |
1162 | return err; | |
1163 | } | |
1164 | ||
3d73c288 RD |
1165 | static int __devinit mlx4_init_one(struct pci_dev *pdev, |
1166 | const struct pci_device_id *id) | |
1167 | { | |
1168 | static int mlx4_version_printed; | |
1169 | ||
1170 | if (!mlx4_version_printed) { | |
1171 | printk(KERN_INFO "%s", mlx4_version); | |
1172 | ++mlx4_version_printed; | |
1173 | } | |
1174 | ||
b027cacd | 1175 | return __mlx4_init_one(pdev, id); |
3d73c288 RD |
1176 | } |
1177 | ||
1178 | static void mlx4_remove_one(struct pci_dev *pdev) | |
225c7b1f RD |
1179 | { |
1180 | struct mlx4_dev *dev = pci_get_drvdata(pdev); | |
1181 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1182 | int p; | |
1183 | ||
1184 | if (dev) { | |
1185 | mlx4_unregister_device(dev); | |
1186 | ||
7ff93f8b YP |
1187 | for (p = 1; p <= dev->caps.num_ports; p++) { |
1188 | mlx4_cleanup_port_info(&priv->port[p]); | |
225c7b1f | 1189 | mlx4_CLOSE_PORT(dev, p); |
7ff93f8b | 1190 | } |
225c7b1f RD |
1191 | |
1192 | mlx4_cleanup_mcg_table(dev); | |
1193 | mlx4_cleanup_qp_table(dev); | |
1194 | mlx4_cleanup_srq_table(dev); | |
1195 | mlx4_cleanup_cq_table(dev); | |
1196 | mlx4_cmd_use_polling(dev); | |
1197 | mlx4_cleanup_eq_table(dev); | |
225c7b1f RD |
1198 | mlx4_cleanup_mr_table(dev); |
1199 | mlx4_cleanup_pd_table(dev); | |
1200 | ||
1201 | iounmap(priv->kar); | |
1202 | mlx4_uar_free(dev, &priv->driver_uar); | |
1203 | mlx4_cleanup_uar_table(dev); | |
b8dd786f | 1204 | mlx4_free_eq_table(dev); |
225c7b1f RD |
1205 | mlx4_close_hca(dev); |
1206 | mlx4_cmd_cleanup(dev); | |
1207 | ||
1208 | if (dev->flags & MLX4_FLAG_MSI_X) | |
1209 | pci_disable_msix(pdev); | |
1210 | ||
1211 | kfree(priv); | |
1212 | pci_release_region(pdev, 2); | |
1213 | pci_release_region(pdev, 0); | |
1214 | pci_disable_device(pdev); | |
1215 | pci_set_drvdata(pdev, NULL); | |
1216 | } | |
1217 | } | |
1218 | ||
ee49bd93 JM |
1219 | int mlx4_restart_one(struct pci_dev *pdev) |
1220 | { | |
1221 | mlx4_remove_one(pdev); | |
3d73c288 | 1222 | return __mlx4_init_one(pdev, NULL); |
ee49bd93 JM |
1223 | } |
1224 | ||
225c7b1f RD |
1225 | static struct pci_device_id mlx4_pci_table[] = { |
1226 | { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */ | |
1227 | { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */ | |
1228 | { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */ | |
786f238e JM |
1229 | { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */ |
1230 | { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */ | |
57893d1c YP |
1231 | { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */ |
1232 | { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ | |
225c7b1f RD |
1233 | { 0, } |
1234 | }; | |
1235 | ||
1236 | MODULE_DEVICE_TABLE(pci, mlx4_pci_table); | |
1237 | ||
1238 | static struct pci_driver mlx4_driver = { | |
1239 | .name = DRV_NAME, | |
1240 | .id_table = mlx4_pci_table, | |
1241 | .probe = mlx4_init_one, | |
1242 | .remove = __devexit_p(mlx4_remove_one) | |
1243 | }; | |
1244 | ||
7ff93f8b YP |
1245 | static int __init mlx4_verify_params(void) |
1246 | { | |
1247 | if ((log_num_mac < 0) || (log_num_mac > 7)) { | |
1248 | printk(KERN_WARNING "mlx4_core: bad num_mac: %d\n", log_num_mac); | |
1249 | return -1; | |
1250 | } | |
1251 | ||
1252 | if ((log_num_vlan < 0) || (log_num_vlan > 7)) { | |
1253 | printk(KERN_WARNING "mlx4_core: bad num_vlan: %d\n", log_num_vlan); | |
1254 | return -1; | |
1255 | } | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
225c7b1f RD |
1260 | static int __init mlx4_init(void) |
1261 | { | |
1262 | int ret; | |
1263 | ||
7ff93f8b YP |
1264 | if (mlx4_verify_params()) |
1265 | return -EINVAL; | |
1266 | ||
ee49bd93 JM |
1267 | ret = mlx4_catas_init(); |
1268 | if (ret) | |
1269 | return ret; | |
1270 | ||
225c7b1f RD |
1271 | ret = pci_register_driver(&mlx4_driver); |
1272 | return ret < 0 ? ret : 0; | |
1273 | } | |
1274 | ||
1275 | static void __exit mlx4_cleanup(void) | |
1276 | { | |
1277 | pci_unregister_driver(&mlx4_driver); | |
ee49bd93 | 1278 | mlx4_catas_cleanup(); |
225c7b1f RD |
1279 | } |
1280 | ||
1281 | module_init(mlx4_init); | |
1282 | module_exit(mlx4_cleanup); |