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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. | |
4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. | |
51a379d0 | 5 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
6 | * Copyright (c) 2004 Voltaire, Inc. All rights reserved. |
7 | * | |
8 | * This software is available to you under a choice of one of two | |
9 | * licenses. You may choose to be licensed under the terms of the GNU | |
10 | * General Public License (GPL) Version 2, available from the file | |
11 | * COPYING in the main directory of this source tree, or the | |
12 | * OpenIB.org BSD license below: | |
13 | * | |
14 | * Redistribution and use in source and binary forms, with or | |
15 | * without modification, are permitted provided that the following | |
16 | * conditions are met: | |
17 | * | |
18 | * - Redistributions of source code must retain the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer. | |
21 | * | |
22 | * - Redistributions in binary form must reproduce the above | |
23 | * copyright notice, this list of conditions and the following | |
24 | * disclaimer in the documentation and/or other materials | |
25 | * provided with the distribution. | |
26 | * | |
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
28 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
29 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
30 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
31 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
32 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
33 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
34 | * SOFTWARE. | |
35 | */ | |
36 | ||
37 | #ifndef MLX4_H | |
38 | #define MLX4_H | |
39 | ||
525f5f44 | 40 | #include <linux/mutex.h> |
225c7b1f | 41 | #include <linux/radix-tree.h> |
ee49bd93 | 42 | #include <linux/timer.h> |
225c7b1f RD |
43 | |
44 | #include <linux/mlx4/device.h> | |
37608eea | 45 | #include <linux/mlx4/driver.h> |
225c7b1f RD |
46 | #include <linux/mlx4/doorbell.h> |
47 | ||
48 | #define DRV_NAME "mlx4_core" | |
49 | #define PFX DRV_NAME ": " | |
50 | #define DRV_VERSION "0.01" | |
51 | #define DRV_RELDATE "May 1, 2007" | |
52 | ||
53 | enum { | |
54 | MLX4_HCR_BASE = 0x80680, | |
55 | MLX4_HCR_SIZE = 0x0001c, | |
56 | MLX4_CLR_INT_SIZE = 0x00008 | |
57 | }; | |
58 | ||
225c7b1f | 59 | enum { |
e57ac0c2 | 60 | MLX4_MGM_ENTRY_SIZE = 0x100, |
225c7b1f RD |
61 | MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2), |
62 | MLX4_MTT_ENTRY_PER_SEG = 8 | |
63 | }; | |
64 | ||
65 | enum { | |
66 | MLX4_EQ_ASYNC, | |
67 | MLX4_EQ_COMP, | |
225c7b1f RD |
68 | MLX4_NUM_EQ |
69 | }; | |
70 | ||
71 | enum { | |
72 | MLX4_NUM_PDS = 1 << 15 | |
73 | }; | |
74 | ||
75 | enum { | |
76 | MLX4_CMPT_TYPE_QP = 0, | |
77 | MLX4_CMPT_TYPE_SRQ = 1, | |
78 | MLX4_CMPT_TYPE_CQ = 2, | |
79 | MLX4_CMPT_TYPE_EQ = 3, | |
80 | MLX4_CMPT_NUM_TYPE | |
81 | }; | |
82 | ||
83 | enum { | |
84 | MLX4_CMPT_SHIFT = 24, | |
85 | MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT | |
86 | }; | |
87 | ||
88 | #ifdef CONFIG_MLX4_DEBUG | |
89 | extern int mlx4_debug_level; | |
90 | ||
91 | #define mlx4_dbg(mdev, format, arg...) \ | |
92 | do { \ | |
93 | if (mlx4_debug_level) \ | |
94 | dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \ | |
95 | } while (0) | |
96 | ||
97 | #else /* CONFIG_MLX4_DEBUG */ | |
98 | ||
99 | #define mlx4_dbg(mdev, format, arg...) do { (void) mdev; } while (0) | |
100 | ||
101 | #endif /* CONFIG_MLX4_DEBUG */ | |
102 | ||
103 | #define mlx4_err(mdev, format, arg...) \ | |
104 | dev_err(&mdev->pdev->dev, format, ## arg) | |
105 | #define mlx4_info(mdev, format, arg...) \ | |
106 | dev_info(&mdev->pdev->dev, format, ## arg) | |
107 | #define mlx4_warn(mdev, format, arg...) \ | |
108 | dev_warn(&mdev->pdev->dev, format, ## arg) | |
109 | ||
110 | struct mlx4_bitmap { | |
111 | u32 last; | |
112 | u32 top; | |
113 | u32 max; | |
93fc9e1b | 114 | u32 reserved_top; |
225c7b1f RD |
115 | u32 mask; |
116 | spinlock_t lock; | |
117 | unsigned long *table; | |
118 | }; | |
119 | ||
120 | struct mlx4_buddy { | |
121 | unsigned long **bits; | |
e4044cfc | 122 | unsigned int *num_free; |
225c7b1f RD |
123 | int max_order; |
124 | spinlock_t lock; | |
125 | }; | |
126 | ||
127 | struct mlx4_icm; | |
128 | ||
129 | struct mlx4_icm_table { | |
130 | u64 virt; | |
131 | int num_icm; | |
132 | int num_obj; | |
133 | int obj_size; | |
134 | int lowmem; | |
5b0bf5e2 | 135 | int coherent; |
225c7b1f RD |
136 | struct mutex mutex; |
137 | struct mlx4_icm **icm; | |
138 | }; | |
139 | ||
140 | struct mlx4_eq { | |
141 | struct mlx4_dev *dev; | |
142 | void __iomem *doorbell; | |
143 | int eqn; | |
144 | u32 cons_index; | |
145 | u16 irq; | |
146 | u16 have_irq; | |
147 | int nent; | |
148 | struct mlx4_buf_list *page_list; | |
149 | struct mlx4_mtt mtt; | |
150 | }; | |
151 | ||
152 | struct mlx4_profile { | |
153 | int num_qp; | |
154 | int rdmarc_per_qp; | |
155 | int num_srq; | |
156 | int num_cq; | |
157 | int num_mcg; | |
158 | int num_mpt; | |
159 | int num_mtt; | |
160 | }; | |
161 | ||
162 | struct mlx4_fw { | |
163 | u64 clr_int_base; | |
164 | u64 catas_offset; | |
165 | struct mlx4_icm *fw_icm; | |
166 | struct mlx4_icm *aux_icm; | |
167 | u32 catas_size; | |
168 | u16 fw_pages; | |
169 | u8 clr_int_bar; | |
170 | u8 catas_bar; | |
171 | }; | |
172 | ||
173 | struct mlx4_cmd { | |
174 | struct pci_pool *pool; | |
175 | void __iomem *hcr; | |
176 | struct mutex hcr_mutex; | |
177 | struct semaphore poll_sem; | |
178 | struct semaphore event_sem; | |
179 | int max_cmds; | |
180 | spinlock_t context_lock; | |
181 | int free_head; | |
182 | struct mlx4_cmd_context *context; | |
183 | u16 token_mask; | |
184 | u8 use_events; | |
185 | u8 toggle; | |
186 | }; | |
187 | ||
188 | struct mlx4_uar_table { | |
189 | struct mlx4_bitmap bitmap; | |
190 | }; | |
191 | ||
192 | struct mlx4_mr_table { | |
193 | struct mlx4_bitmap mpt_bitmap; | |
194 | struct mlx4_buddy mtt_buddy; | |
195 | u64 mtt_base; | |
196 | u64 mpt_base; | |
197 | struct mlx4_icm_table mtt_table; | |
198 | struct mlx4_icm_table dmpt_table; | |
199 | }; | |
200 | ||
201 | struct mlx4_cq_table { | |
202 | struct mlx4_bitmap bitmap; | |
203 | spinlock_t lock; | |
204 | struct radix_tree_root tree; | |
205 | struct mlx4_icm_table table; | |
206 | struct mlx4_icm_table cmpt_table; | |
207 | }; | |
208 | ||
209 | struct mlx4_eq_table { | |
210 | struct mlx4_bitmap bitmap; | |
211 | void __iomem *clr_int; | |
212 | void __iomem *uar_map[(MLX4_NUM_EQ + 6) / 4]; | |
213 | u32 clr_mask; | |
214 | struct mlx4_eq eq[MLX4_NUM_EQ]; | |
215 | u64 icm_virt; | |
216 | struct page *icm_page; | |
217 | dma_addr_t icm_dma; | |
218 | struct mlx4_icm_table cmpt_table; | |
219 | int have_irq; | |
220 | u8 inta_pin; | |
221 | }; | |
222 | ||
223 | struct mlx4_srq_table { | |
224 | struct mlx4_bitmap bitmap; | |
225 | spinlock_t lock; | |
226 | struct radix_tree_root tree; | |
227 | struct mlx4_icm_table table; | |
228 | struct mlx4_icm_table cmpt_table; | |
229 | }; | |
230 | ||
231 | struct mlx4_qp_table { | |
232 | struct mlx4_bitmap bitmap; | |
233 | u32 rdmarc_base; | |
234 | int rdmarc_shift; | |
235 | spinlock_t lock; | |
236 | struct mlx4_icm_table qp_table; | |
237 | struct mlx4_icm_table auxc_table; | |
238 | struct mlx4_icm_table altc_table; | |
239 | struct mlx4_icm_table rdmarc_table; | |
240 | struct mlx4_icm_table cmpt_table; | |
241 | }; | |
242 | ||
243 | struct mlx4_mcg_table { | |
244 | struct mutex mutex; | |
245 | struct mlx4_bitmap bitmap; | |
246 | struct mlx4_icm_table table; | |
247 | }; | |
248 | ||
249 | struct mlx4_catas_err { | |
250 | u32 __iomem *map; | |
ee49bd93 JM |
251 | struct timer_list timer; |
252 | struct list_head list; | |
225c7b1f RD |
253 | }; |
254 | ||
2a2336f8 YP |
255 | #define MLX4_MAX_MAC_NUM 128 |
256 | #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) | |
257 | ||
258 | struct mlx4_mac_table { | |
259 | __be64 entries[MLX4_MAX_MAC_NUM]; | |
260 | int refs[MLX4_MAX_MAC_NUM]; | |
261 | struct mutex mutex; | |
262 | int total; | |
263 | int max; | |
264 | }; | |
265 | ||
266 | #define MLX4_MAX_VLAN_NUM 128 | |
267 | #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) | |
268 | ||
269 | struct mlx4_vlan_table { | |
270 | __be32 entries[MLX4_MAX_VLAN_NUM]; | |
271 | int refs[MLX4_MAX_VLAN_NUM]; | |
272 | struct mutex mutex; | |
273 | int total; | |
274 | int max; | |
275 | }; | |
276 | ||
277 | struct mlx4_port_info { | |
278 | struct mlx4_dev *dev; | |
279 | int port; | |
7ff93f8b YP |
280 | char dev_name[16]; |
281 | struct device_attribute port_attr; | |
282 | enum mlx4_port_type tmp_type; | |
2a2336f8 YP |
283 | struct mlx4_mac_table mac_table; |
284 | struct mlx4_vlan_table vlan_table; | |
285 | }; | |
286 | ||
225c7b1f RD |
287 | struct mlx4_priv { |
288 | struct mlx4_dev dev; | |
289 | ||
290 | struct list_head dev_list; | |
291 | struct list_head ctx_list; | |
292 | spinlock_t ctx_lock; | |
293 | ||
6296883c YP |
294 | struct list_head pgdir_list; |
295 | struct mutex pgdir_mutex; | |
296 | ||
225c7b1f RD |
297 | struct mlx4_fw fw; |
298 | struct mlx4_cmd cmd; | |
299 | ||
300 | struct mlx4_bitmap pd_bitmap; | |
301 | struct mlx4_uar_table uar_table; | |
302 | struct mlx4_mr_table mr_table; | |
303 | struct mlx4_cq_table cq_table; | |
304 | struct mlx4_eq_table eq_table; | |
305 | struct mlx4_srq_table srq_table; | |
306 | struct mlx4_qp_table qp_table; | |
307 | struct mlx4_mcg_table mcg_table; | |
308 | ||
309 | struct mlx4_catas_err catas_err; | |
310 | ||
311 | void __iomem *clr_base; | |
312 | ||
313 | struct mlx4_uar driver_uar; | |
314 | void __iomem *kar; | |
2a2336f8 | 315 | struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; |
7ff93f8b | 316 | struct mutex port_mutex; |
225c7b1f RD |
317 | }; |
318 | ||
319 | static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) | |
320 | { | |
321 | return container_of(dev, struct mlx4_priv, dev); | |
322 | } | |
323 | ||
324 | u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); | |
325 | void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj); | |
a3cdcbfa YP |
326 | u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); |
327 | void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt); | |
93fc9e1b YP |
328 | int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, |
329 | u32 reserved_bot, u32 resetrved_top); | |
225c7b1f RD |
330 | void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); |
331 | ||
332 | int mlx4_reset(struct mlx4_dev *dev); | |
333 | ||
334 | int mlx4_init_pd_table(struct mlx4_dev *dev); | |
335 | int mlx4_init_uar_table(struct mlx4_dev *dev); | |
336 | int mlx4_init_mr_table(struct mlx4_dev *dev); | |
337 | int mlx4_init_eq_table(struct mlx4_dev *dev); | |
338 | int mlx4_init_cq_table(struct mlx4_dev *dev); | |
339 | int mlx4_init_qp_table(struct mlx4_dev *dev); | |
340 | int mlx4_init_srq_table(struct mlx4_dev *dev); | |
341 | int mlx4_init_mcg_table(struct mlx4_dev *dev); | |
342 | ||
343 | void mlx4_cleanup_pd_table(struct mlx4_dev *dev); | |
344 | void mlx4_cleanup_uar_table(struct mlx4_dev *dev); | |
345 | void mlx4_cleanup_mr_table(struct mlx4_dev *dev); | |
346 | void mlx4_cleanup_eq_table(struct mlx4_dev *dev); | |
347 | void mlx4_cleanup_cq_table(struct mlx4_dev *dev); | |
348 | void mlx4_cleanup_qp_table(struct mlx4_dev *dev); | |
349 | void mlx4_cleanup_srq_table(struct mlx4_dev *dev); | |
350 | void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); | |
351 | ||
ee49bd93 JM |
352 | void mlx4_start_catas_poll(struct mlx4_dev *dev); |
353 | void mlx4_stop_catas_poll(struct mlx4_dev *dev); | |
354 | int mlx4_catas_init(void); | |
355 | void mlx4_catas_cleanup(void); | |
356 | int mlx4_restart_one(struct pci_dev *pdev); | |
225c7b1f RD |
357 | int mlx4_register_device(struct mlx4_dev *dev); |
358 | void mlx4_unregister_device(struct mlx4_dev *dev); | |
37608eea | 359 | void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port); |
225c7b1f RD |
360 | |
361 | struct mlx4_dev_cap; | |
362 | struct mlx4_init_hca_param; | |
363 | ||
364 | u64 mlx4_make_profile(struct mlx4_dev *dev, | |
365 | struct mlx4_profile *request, | |
366 | struct mlx4_dev_cap *dev_cap, | |
367 | struct mlx4_init_hca_param *init_hca); | |
368 | ||
369 | int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt); | |
370 | void mlx4_unmap_eq_icm(struct mlx4_dev *dev); | |
371 | ||
372 | int mlx4_cmd_init(struct mlx4_dev *dev); | |
373 | void mlx4_cmd_cleanup(struct mlx4_dev *dev); | |
374 | void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); | |
375 | int mlx4_cmd_use_events(struct mlx4_dev *dev); | |
376 | void mlx4_cmd_use_polling(struct mlx4_dev *dev); | |
377 | ||
378 | void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); | |
379 | void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); | |
380 | ||
381 | void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); | |
382 | ||
383 | void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); | |
384 | ||
385 | void mlx4_handle_catas_err(struct mlx4_dev *dev); | |
386 | ||
2a2336f8 YP |
387 | void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); |
388 | void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); | |
389 | ||
7ff93f8b YP |
390 | int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port); |
391 | ||
225c7b1f | 392 | #endif /* MLX4_H */ |