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1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
c3efab8e | 41 | #include <linux/ip.h> |
1da177e4 LT |
42 | #include <linux/tcp.h> |
43 | #include <linux/udp.h> | |
44 | #include <linux/etherdevice.h> | |
1da177e4 LT |
45 | #include <linux/delay.h> |
46 | #include <linux/ethtool.h> | |
d052d1be | 47 | #include <linux/platform_device.h> |
fbd6a754 LB |
48 | #include <linux/module.h> |
49 | #include <linux/kernel.h> | |
50 | #include <linux/spinlock.h> | |
51 | #include <linux/workqueue.h> | |
ed94493f | 52 | #include <linux/phy.h> |
fbd6a754 | 53 | #include <linux/mv643xx_eth.h> |
10a9948d LB |
54 | #include <linux/io.h> |
55 | #include <linux/types.h> | |
eaf5d590 | 56 | #include <linux/inet_lro.h> |
5a0e3ad6 | 57 | #include <linux/slab.h> |
1da177e4 | 58 | #include <asm/system.h> |
fbd6a754 | 59 | |
e5371493 | 60 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
042af53c | 61 | static char mv643xx_eth_driver_version[] = "1.4"; |
c9df406f | 62 | |
fbd6a754 | 63 | |
fbd6a754 LB |
64 | /* |
65 | * Registers shared between all ports. | |
66 | */ | |
3cb4667c LB |
67 | #define PHY_ADDR 0x0000 |
68 | #define SMI_REG 0x0004 | |
45c5d3bc LB |
69 | #define SMI_BUSY 0x10000000 |
70 | #define SMI_READ_VALID 0x08000000 | |
71 | #define SMI_OPCODE_READ 0x04000000 | |
72 | #define SMI_OPCODE_WRITE 0x00000000 | |
73 | #define ERR_INT_CAUSE 0x0080 | |
74 | #define ERR_INT_SMI_DONE 0x00000010 | |
75 | #define ERR_INT_MASK 0x0084 | |
3cb4667c LB |
76 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) |
77 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
78 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
79 | #define WINDOW_BAR_ENABLE 0x0290 | |
80 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
81 | |
82 | /* | |
37a6084f LB |
83 | * Main per-port registers. These live at offset 0x0400 for |
84 | * port #0, 0x0800 for port #1, and 0x0c00 for port #2. | |
fbd6a754 | 85 | */ |
37a6084f | 86 | #define PORT_CONFIG 0x0000 |
d9a073ea | 87 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
37a6084f LB |
88 | #define PORT_CONFIG_EXT 0x0004 |
89 | #define MAC_ADDR_LOW 0x0014 | |
90 | #define MAC_ADDR_HIGH 0x0018 | |
91 | #define SDMA_CONFIG 0x001c | |
becfad97 LB |
92 | #define TX_BURST_SIZE_16_64BIT 0x01000000 |
93 | #define TX_BURST_SIZE_4_64BIT 0x00800000 | |
94 | #define BLM_TX_NO_SWAP 0x00000020 | |
95 | #define BLM_RX_NO_SWAP 0x00000010 | |
96 | #define RX_BURST_SIZE_16_64BIT 0x00000008 | |
97 | #define RX_BURST_SIZE_4_64BIT 0x00000004 | |
37a6084f | 98 | #define PORT_SERIAL_CONTROL 0x003c |
becfad97 LB |
99 | #define SET_MII_SPEED_TO_100 0x01000000 |
100 | #define SET_GMII_SPEED_TO_1000 0x00800000 | |
101 | #define SET_FULL_DUPLEX_MODE 0x00200000 | |
102 | #define MAX_RX_PACKET_9700BYTE 0x000a0000 | |
103 | #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 | |
104 | #define DO_NOT_FORCE_LINK_FAIL 0x00000400 | |
105 | #define SERIAL_PORT_CONTROL_RESERVED 0x00000200 | |
106 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 | |
107 | #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 | |
108 | #define FORCE_LINK_PASS 0x00000002 | |
109 | #define SERIAL_PORT_ENABLE 0x00000001 | |
37a6084f | 110 | #define PORT_STATUS 0x0044 |
a2a41689 | 111 | #define TX_FIFO_EMPTY 0x00000400 |
ae9ae064 | 112 | #define TX_IN_PROGRESS 0x00000080 |
2f7eb47a LB |
113 | #define PORT_SPEED_MASK 0x00000030 |
114 | #define PORT_SPEED_1000 0x00000010 | |
115 | #define PORT_SPEED_100 0x00000020 | |
116 | #define PORT_SPEED_10 0x00000000 | |
117 | #define FLOW_CONTROL_ENABLED 0x00000008 | |
118 | #define FULL_DUPLEX 0x00000004 | |
81600eea | 119 | #define LINK_UP 0x00000002 |
37a6084f LB |
120 | #define TXQ_COMMAND 0x0048 |
121 | #define TXQ_FIX_PRIO_CONF 0x004c | |
122 | #define TX_BW_RATE 0x0050 | |
123 | #define TX_BW_MTU 0x0058 | |
124 | #define TX_BW_BURST 0x005c | |
125 | #define INT_CAUSE 0x0060 | |
226bb6b7 | 126 | #define INT_TX_END 0x07f80000 |
e0ca8410 | 127 | #define INT_TX_END_0 0x00080000 |
befefe21 | 128 | #define INT_RX 0x000003fc |
e0ca8410 | 129 | #define INT_RX_0 0x00000004 |
073a345c | 130 | #define INT_EXT 0x00000002 |
37a6084f | 131 | #define INT_CAUSE_EXT 0x0064 |
befefe21 LB |
132 | #define INT_EXT_LINK_PHY 0x00110000 |
133 | #define INT_EXT_TX 0x000000ff | |
37a6084f LB |
134 | #define INT_MASK 0x0068 |
135 | #define INT_MASK_EXT 0x006c | |
136 | #define TX_FIFO_URGENT_THRESHOLD 0x0074 | |
137 | #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc | |
138 | #define TX_BW_RATE_MOVED 0x00e0 | |
139 | #define TX_BW_MTU_MOVED 0x00e8 | |
140 | #define TX_BW_BURST_MOVED 0x00ec | |
141 | #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) | |
142 | #define RXQ_COMMAND 0x0280 | |
143 | #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) | |
144 | #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) | |
145 | #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) | |
146 | #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) | |
147 | ||
148 | /* | |
149 | * Misc per-port registers. | |
150 | */ | |
3cb4667c LB |
151 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) |
152 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
153 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
154 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 155 | |
2679a550 LB |
156 | |
157 | /* | |
becfad97 | 158 | * SDMA configuration register default value. |
2679a550 | 159 | */ |
fbd6a754 LB |
160 | #if defined(__BIG_ENDIAN) |
161 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
162 | (RX_BURST_SIZE_4_64BIT | \ |
163 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
164 | #elif defined(__LITTLE_ENDIAN) |
165 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
166 | (RX_BURST_SIZE_4_64BIT | \ |
167 | BLM_RX_NO_SWAP | \ | |
168 | BLM_TX_NO_SWAP | \ | |
169 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
170 | #else |
171 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
172 | #endif | |
173 | ||
2beff77b LB |
174 | |
175 | /* | |
becfad97 | 176 | * Misc definitions. |
2beff77b | 177 | */ |
becfad97 LB |
178 | #define DEFAULT_RX_QUEUE_SIZE 128 |
179 | #define DEFAULT_TX_QUEUE_SIZE 256 | |
7fd96ce4 | 180 | #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) |
fbd6a754 | 181 | |
fbd6a754 | 182 | |
7ca72a3b LB |
183 | /* |
184 | * RX/TX descriptors. | |
fbd6a754 LB |
185 | */ |
186 | #if defined(__BIG_ENDIAN) | |
cc9754b3 | 187 | struct rx_desc { |
fbd6a754 LB |
188 | u16 byte_cnt; /* Descriptor buffer byte count */ |
189 | u16 buf_size; /* Buffer size */ | |
190 | u32 cmd_sts; /* Descriptor command status */ | |
191 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
192 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
193 | }; | |
194 | ||
cc9754b3 | 195 | struct tx_desc { |
fbd6a754 LB |
196 | u16 byte_cnt; /* buffer byte count */ |
197 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
198 | u32 cmd_sts; /* Command/status field */ | |
199 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
200 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
201 | }; | |
202 | #elif defined(__LITTLE_ENDIAN) | |
cc9754b3 | 203 | struct rx_desc { |
fbd6a754 LB |
204 | u32 cmd_sts; /* Descriptor command status */ |
205 | u16 buf_size; /* Buffer size */ | |
206 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
207 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
208 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
209 | }; | |
210 | ||
cc9754b3 | 211 | struct tx_desc { |
fbd6a754 LB |
212 | u32 cmd_sts; /* Command/status field */ |
213 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
214 | u16 byte_cnt; /* buffer byte count */ | |
215 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
216 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
217 | }; | |
218 | #else | |
219 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
220 | #endif | |
221 | ||
7ca72a3b | 222 | /* RX & TX descriptor command */ |
cc9754b3 | 223 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
7ca72a3b LB |
224 | |
225 | /* RX & TX descriptor status */ | |
cc9754b3 | 226 | #define ERROR_SUMMARY 0x00000001 |
7ca72a3b LB |
227 | |
228 | /* RX descriptor status */ | |
cc9754b3 LB |
229 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
230 | #define RX_ENABLE_INTERRUPT 0x20000000 | |
231 | #define RX_FIRST_DESC 0x08000000 | |
232 | #define RX_LAST_DESC 0x04000000 | |
eaf5d590 LB |
233 | #define RX_IP_HDR_OK 0x02000000 |
234 | #define RX_PKT_IS_IPV4 0x01000000 | |
235 | #define RX_PKT_IS_ETHERNETV2 0x00800000 | |
236 | #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 | |
237 | #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 | |
238 | #define RX_PKT_IS_VLAN_TAGGED 0x00080000 | |
7ca72a3b LB |
239 | |
240 | /* TX descriptor command */ | |
cc9754b3 LB |
241 | #define TX_ENABLE_INTERRUPT 0x00800000 |
242 | #define GEN_CRC 0x00400000 | |
243 | #define TX_FIRST_DESC 0x00200000 | |
244 | #define TX_LAST_DESC 0x00100000 | |
245 | #define ZERO_PADDING 0x00080000 | |
246 | #define GEN_IP_V4_CHECKSUM 0x00040000 | |
247 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 | |
248 | #define UDP_FRAME 0x00010000 | |
e32b6617 LB |
249 | #define MAC_HDR_EXTRA_4_BYTES 0x00008000 |
250 | #define MAC_HDR_EXTRA_8_BYTES 0x00000200 | |
7ca72a3b | 251 | |
cc9754b3 | 252 | #define TX_IHL_SHIFT 11 |
7ca72a3b LB |
253 | |
254 | ||
c9df406f | 255 | /* global *******************************************************************/ |
e5371493 | 256 | struct mv643xx_eth_shared_private { |
fc32b0e2 LB |
257 | /* |
258 | * Ethernet controller base address. | |
259 | */ | |
cc9754b3 | 260 | void __iomem *base; |
c9df406f | 261 | |
fc0eb9f2 LB |
262 | /* |
263 | * Points at the right SMI instance to use. | |
264 | */ | |
265 | struct mv643xx_eth_shared_private *smi; | |
266 | ||
fc32b0e2 | 267 | /* |
ed94493f | 268 | * Provides access to local SMI interface. |
fc32b0e2 | 269 | */ |
298cf9be | 270 | struct mii_bus *smi_bus; |
c9df406f | 271 | |
45c5d3bc LB |
272 | /* |
273 | * If we have access to the error interrupt pin (which is | |
274 | * somewhat misnamed as it not only reflects internal errors | |
275 | * but also reflects SMI completion), use that to wait for | |
276 | * SMI access completion instead of polling the SMI busy bit. | |
277 | */ | |
278 | int err_interrupt; | |
279 | wait_queue_head_t smi_busy_wait; | |
280 | ||
fc32b0e2 LB |
281 | /* |
282 | * Per-port MBUS window access register value. | |
283 | */ | |
c9df406f LB |
284 | u32 win_protect; |
285 | ||
fc32b0e2 LB |
286 | /* |
287 | * Hardware-specific parameters. | |
288 | */ | |
c9df406f | 289 | unsigned int t_clk; |
773fc3ee | 290 | int extended_rx_coal_limit; |
457b1d5a | 291 | int tx_bw_control; |
9b2c2ff7 | 292 | int tx_csum_limit; |
c9df406f LB |
293 | }; |
294 | ||
457b1d5a LB |
295 | #define TX_BW_CONTROL_ABSENT 0 |
296 | #define TX_BW_CONTROL_OLD_LAYOUT 1 | |
297 | #define TX_BW_CONTROL_NEW_LAYOUT 2 | |
298 | ||
e7d2f4db LB |
299 | static int mv643xx_eth_open(struct net_device *dev); |
300 | static int mv643xx_eth_stop(struct net_device *dev); | |
301 | ||
c9df406f LB |
302 | |
303 | /* per-port *****************************************************************/ | |
e5371493 | 304 | struct mib_counters { |
fbd6a754 LB |
305 | u64 good_octets_received; |
306 | u32 bad_octets_received; | |
307 | u32 internal_mac_transmit_err; | |
308 | u32 good_frames_received; | |
309 | u32 bad_frames_received; | |
310 | u32 broadcast_frames_received; | |
311 | u32 multicast_frames_received; | |
312 | u32 frames_64_octets; | |
313 | u32 frames_65_to_127_octets; | |
314 | u32 frames_128_to_255_octets; | |
315 | u32 frames_256_to_511_octets; | |
316 | u32 frames_512_to_1023_octets; | |
317 | u32 frames_1024_to_max_octets; | |
318 | u64 good_octets_sent; | |
319 | u32 good_frames_sent; | |
320 | u32 excessive_collision; | |
321 | u32 multicast_frames_sent; | |
322 | u32 broadcast_frames_sent; | |
323 | u32 unrec_mac_control_received; | |
324 | u32 fc_sent; | |
325 | u32 good_fc_received; | |
326 | u32 bad_fc_received; | |
327 | u32 undersize_received; | |
328 | u32 fragments_received; | |
329 | u32 oversize_received; | |
330 | u32 jabber_received; | |
331 | u32 mac_receive_error; | |
332 | u32 bad_crc_event; | |
333 | u32 collision; | |
334 | u32 late_collision; | |
335 | }; | |
336 | ||
eaf5d590 LB |
337 | struct lro_counters { |
338 | u32 lro_aggregated; | |
339 | u32 lro_flushed; | |
340 | u32 lro_no_desc; | |
341 | }; | |
342 | ||
8a578111 | 343 | struct rx_queue { |
64da80a2 LB |
344 | int index; |
345 | ||
8a578111 LB |
346 | int rx_ring_size; |
347 | ||
348 | int rx_desc_count; | |
349 | int rx_curr_desc; | |
350 | int rx_used_desc; | |
351 | ||
352 | struct rx_desc *rx_desc_area; | |
353 | dma_addr_t rx_desc_dma; | |
354 | int rx_desc_area_size; | |
355 | struct sk_buff **rx_skb; | |
eaf5d590 | 356 | |
eaf5d590 LB |
357 | struct net_lro_mgr lro_mgr; |
358 | struct net_lro_desc lro_arr[8]; | |
8a578111 LB |
359 | }; |
360 | ||
13d64285 | 361 | struct tx_queue { |
3d6b35bc LB |
362 | int index; |
363 | ||
13d64285 | 364 | int tx_ring_size; |
fbd6a754 | 365 | |
13d64285 LB |
366 | int tx_desc_count; |
367 | int tx_curr_desc; | |
368 | int tx_used_desc; | |
fbd6a754 | 369 | |
5daffe94 | 370 | struct tx_desc *tx_desc_area; |
fbd6a754 LB |
371 | dma_addr_t tx_desc_dma; |
372 | int tx_desc_area_size; | |
99ab08e0 LB |
373 | |
374 | struct sk_buff_head tx_skb; | |
8fd89211 LB |
375 | |
376 | unsigned long tx_packets; | |
377 | unsigned long tx_bytes; | |
378 | unsigned long tx_dropped; | |
13d64285 LB |
379 | }; |
380 | ||
381 | struct mv643xx_eth_private { | |
382 | struct mv643xx_eth_shared_private *shared; | |
37a6084f | 383 | void __iomem *base; |
fc32b0e2 | 384 | int port_num; |
13d64285 | 385 | |
fc32b0e2 | 386 | struct net_device *dev; |
fbd6a754 | 387 | |
ed94493f | 388 | struct phy_device *phy; |
fbd6a754 | 389 | |
4ff3495a LB |
390 | struct timer_list mib_counters_timer; |
391 | spinlock_t mib_counters_lock; | |
fc32b0e2 | 392 | struct mib_counters mib_counters; |
4ff3495a | 393 | |
eaf5d590 LB |
394 | struct lro_counters lro_counters; |
395 | ||
fc32b0e2 | 396 | struct work_struct tx_timeout_task; |
8a578111 | 397 | |
1fa38c58 | 398 | struct napi_struct napi; |
e0ca8410 | 399 | u32 int_mask; |
1319ebad | 400 | u8 oom; |
1fa38c58 LB |
401 | u8 work_link; |
402 | u8 work_tx; | |
403 | u8 work_tx_end; | |
404 | u8 work_rx; | |
405 | u8 work_rx_refill; | |
1fa38c58 | 406 | |
2bcb4b0f LB |
407 | int skb_size; |
408 | struct sk_buff_head rx_recycle; | |
409 | ||
8a578111 LB |
410 | /* |
411 | * RX state. | |
412 | */ | |
e7d2f4db | 413 | int rx_ring_size; |
8a578111 LB |
414 | unsigned long rx_desc_sram_addr; |
415 | int rx_desc_sram_size; | |
f7981c1c | 416 | int rxq_count; |
2257e05c | 417 | struct timer_list rx_oom; |
64da80a2 | 418 | struct rx_queue rxq[8]; |
13d64285 LB |
419 | |
420 | /* | |
421 | * TX state. | |
422 | */ | |
e7d2f4db | 423 | int tx_ring_size; |
13d64285 LB |
424 | unsigned long tx_desc_sram_addr; |
425 | int tx_desc_sram_size; | |
f7981c1c | 426 | int txq_count; |
3d6b35bc | 427 | struct tx_queue txq[8]; |
fbd6a754 | 428 | }; |
1da177e4 | 429 | |
fbd6a754 | 430 | |
c9df406f | 431 | /* port register accessors **************************************************/ |
e5371493 | 432 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 433 | { |
cc9754b3 | 434 | return readl(mp->shared->base + offset); |
c9df406f | 435 | } |
fbd6a754 | 436 | |
37a6084f LB |
437 | static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) |
438 | { | |
439 | return readl(mp->base + offset); | |
440 | } | |
441 | ||
e5371493 | 442 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
c9df406f | 443 | { |
cc9754b3 | 444 | writel(data, mp->shared->base + offset); |
c9df406f | 445 | } |
fbd6a754 | 446 | |
37a6084f LB |
447 | static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) |
448 | { | |
449 | writel(data, mp->base + offset); | |
450 | } | |
451 | ||
fbd6a754 | 452 | |
c9df406f | 453 | /* rxq/txq helper functions *************************************************/ |
8a578111 | 454 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
c9df406f | 455 | { |
64da80a2 | 456 | return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); |
c9df406f | 457 | } |
fbd6a754 | 458 | |
13d64285 LB |
459 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
460 | { | |
3d6b35bc | 461 | return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); |
13d64285 LB |
462 | } |
463 | ||
8a578111 | 464 | static void rxq_enable(struct rx_queue *rxq) |
c9df406f | 465 | { |
8a578111 | 466 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
37a6084f | 467 | wrlp(mp, RXQ_COMMAND, 1 << rxq->index); |
8a578111 | 468 | } |
1da177e4 | 469 | |
8a578111 LB |
470 | static void rxq_disable(struct rx_queue *rxq) |
471 | { | |
472 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); | |
64da80a2 | 473 | u8 mask = 1 << rxq->index; |
1da177e4 | 474 | |
37a6084f LB |
475 | wrlp(mp, RXQ_COMMAND, mask << 8); |
476 | while (rdlp(mp, RXQ_COMMAND) & mask) | |
8a578111 | 477 | udelay(10); |
c9df406f LB |
478 | } |
479 | ||
6b368f68 LB |
480 | static void txq_reset_hw_ptr(struct tx_queue *txq) |
481 | { | |
482 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
6b368f68 LB |
483 | u32 addr; |
484 | ||
485 | addr = (u32)txq->tx_desc_dma; | |
486 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); | |
37a6084f | 487 | wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); |
6b368f68 LB |
488 | } |
489 | ||
13d64285 | 490 | static void txq_enable(struct tx_queue *txq) |
1da177e4 | 491 | { |
13d64285 | 492 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
37a6084f | 493 | wrlp(mp, TXQ_COMMAND, 1 << txq->index); |
1da177e4 LT |
494 | } |
495 | ||
13d64285 | 496 | static void txq_disable(struct tx_queue *txq) |
1da177e4 | 497 | { |
13d64285 | 498 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 499 | u8 mask = 1 << txq->index; |
c9df406f | 500 | |
37a6084f LB |
501 | wrlp(mp, TXQ_COMMAND, mask << 8); |
502 | while (rdlp(mp, TXQ_COMMAND) & mask) | |
13d64285 LB |
503 | udelay(10); |
504 | } | |
505 | ||
1fa38c58 | 506 | static void txq_maybe_wake(struct tx_queue *txq) |
13d64285 LB |
507 | { |
508 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
e5ef1de1 | 509 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
3d6b35bc | 510 | |
8fd89211 LB |
511 | if (netif_tx_queue_stopped(nq)) { |
512 | __netif_tx_lock(nq, smp_processor_id()); | |
513 | if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1) | |
514 | netif_tx_wake_queue(nq); | |
515 | __netif_tx_unlock(nq); | |
516 | } | |
1da177e4 LT |
517 | } |
518 | ||
c9df406f | 519 | |
1fa38c58 | 520 | /* rx napi ******************************************************************/ |
eaf5d590 LB |
521 | static int |
522 | mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph, | |
523 | u64 *hdr_flags, void *priv) | |
524 | { | |
525 | unsigned long cmd_sts = (unsigned long)priv; | |
526 | ||
527 | /* | |
528 | * Make sure that this packet is Ethernet II, is not VLAN | |
529 | * tagged, is IPv4, has a valid IP header, and is TCP. | |
530 | */ | |
531 | if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | | |
532 | RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK | | |
533 | RX_PKT_IS_VLAN_TAGGED)) != | |
534 | (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | | |
535 | RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4)) | |
536 | return -1; | |
537 | ||
538 | skb_reset_network_header(skb); | |
539 | skb_set_transport_header(skb, ip_hdrlen(skb)); | |
540 | *iphdr = ip_hdr(skb); | |
541 | *tcph = tcp_hdr(skb); | |
542 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
543 | ||
544 | return 0; | |
545 | } | |
eaf5d590 | 546 | |
8a578111 | 547 | static int rxq_process(struct rx_queue *rxq, int budget) |
1da177e4 | 548 | { |
8a578111 LB |
549 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
550 | struct net_device_stats *stats = &mp->dev->stats; | |
eaf5d590 | 551 | int lro_flush_needed; |
8a578111 | 552 | int rx; |
1da177e4 | 553 | |
eaf5d590 | 554 | lro_flush_needed = 0; |
8a578111 | 555 | rx = 0; |
9e1f3772 | 556 | while (rx < budget && rxq->rx_desc_count) { |
fc32b0e2 | 557 | struct rx_desc *rx_desc; |
96587661 | 558 | unsigned int cmd_sts; |
fc32b0e2 | 559 | struct sk_buff *skb; |
6b8f90c2 | 560 | u16 byte_cnt; |
ff561eef | 561 | |
8a578111 | 562 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
1da177e4 | 563 | |
96587661 | 564 | cmd_sts = rx_desc->cmd_sts; |
2257e05c | 565 | if (cmd_sts & BUFFER_OWNED_BY_DMA) |
96587661 | 566 | break; |
96587661 | 567 | rmb(); |
1da177e4 | 568 | |
8a578111 LB |
569 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
570 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; | |
ff561eef | 571 | |
9da78745 LB |
572 | rxq->rx_curr_desc++; |
573 | if (rxq->rx_curr_desc == rxq->rx_ring_size) | |
574 | rxq->rx_curr_desc = 0; | |
ff561eef | 575 | |
eb0519b5 | 576 | dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, |
abe78717 | 577 | rx_desc->buf_size, DMA_FROM_DEVICE); |
8a578111 LB |
578 | rxq->rx_desc_count--; |
579 | rx++; | |
b1dd9ca1 | 580 | |
1fa38c58 LB |
581 | mp->work_rx_refill |= 1 << rxq->index; |
582 | ||
6b8f90c2 LB |
583 | byte_cnt = rx_desc->byte_cnt; |
584 | ||
468d09f8 DF |
585 | /* |
586 | * Update statistics. | |
fc32b0e2 LB |
587 | * |
588 | * Note that the descriptor byte count includes 2 dummy | |
589 | * bytes automatically inserted by the hardware at the | |
590 | * start of the packet (which we don't count), and a 4 | |
591 | * byte CRC at the end of the packet (which we do count). | |
468d09f8 | 592 | */ |
1da177e4 | 593 | stats->rx_packets++; |
6b8f90c2 | 594 | stats->rx_bytes += byte_cnt - 2; |
96587661 | 595 | |
1da177e4 | 596 | /* |
fc32b0e2 LB |
597 | * In case we received a packet without first / last bits |
598 | * on, or the error summary bit is set, the packet needs | |
599 | * to be dropped. | |
1da177e4 | 600 | */ |
f61e5547 LB |
601 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) |
602 | != (RX_FIRST_DESC | RX_LAST_DESC)) | |
603 | goto err; | |
604 | ||
605 | /* | |
606 | * The -4 is for the CRC in the trailer of the | |
607 | * received packet | |
608 | */ | |
609 | skb_put(skb, byte_cnt - 2 - 4); | |
610 | ||
611 | if (cmd_sts & LAYER_4_CHECKSUM_OK) | |
612 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
613 | skb->protocol = eth_type_trans(skb, mp->dev); | |
eaf5d590 | 614 | |
eaf5d590 LB |
615 | if (skb->dev->features & NETIF_F_LRO && |
616 | skb->ip_summed == CHECKSUM_UNNECESSARY) { | |
617 | lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts); | |
618 | lro_flush_needed = 1; | |
619 | } else | |
eaf5d590 | 620 | netif_receive_skb(skb); |
f61e5547 LB |
621 | |
622 | continue; | |
623 | ||
624 | err: | |
625 | stats->rx_dropped++; | |
626 | ||
627 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != | |
628 | (RX_FIRST_DESC | RX_LAST_DESC)) { | |
629 | if (net_ratelimit()) | |
630 | dev_printk(KERN_ERR, &mp->dev->dev, | |
631 | "received packet spanning " | |
632 | "multiple descriptors\n"); | |
1da177e4 | 633 | } |
f61e5547 LB |
634 | |
635 | if (cmd_sts & ERROR_SUMMARY) | |
636 | stats->rx_errors++; | |
637 | ||
638 | dev_kfree_skb(skb); | |
1da177e4 | 639 | } |
fc32b0e2 | 640 | |
eaf5d590 LB |
641 | if (lro_flush_needed) |
642 | lro_flush_all(&rxq->lro_mgr); | |
eaf5d590 | 643 | |
1fa38c58 LB |
644 | if (rx < budget) |
645 | mp->work_rx &= ~(1 << rxq->index); | |
646 | ||
8a578111 | 647 | return rx; |
1da177e4 LT |
648 | } |
649 | ||
1fa38c58 | 650 | static int rxq_refill(struct rx_queue *rxq, int budget) |
d0412d96 | 651 | { |
1fa38c58 | 652 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1fa38c58 | 653 | int refilled; |
8a578111 | 654 | |
1fa38c58 LB |
655 | refilled = 0; |
656 | while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { | |
657 | struct sk_buff *skb; | |
1fa38c58 | 658 | int rx; |
53771522 | 659 | struct rx_desc *rx_desc; |
530e557a | 660 | int size; |
d0412d96 | 661 | |
2bcb4b0f LB |
662 | skb = __skb_dequeue(&mp->rx_recycle); |
663 | if (skb == NULL) | |
7fd96ce4 | 664 | skb = dev_alloc_skb(mp->skb_size); |
2bcb4b0f | 665 | |
1fa38c58 | 666 | if (skb == NULL) { |
1319ebad | 667 | mp->oom = 1; |
1fa38c58 LB |
668 | goto oom; |
669 | } | |
d0412d96 | 670 | |
7fd96ce4 LB |
671 | if (SKB_DMA_REALIGN) |
672 | skb_reserve(skb, SKB_DMA_REALIGN); | |
2257e05c | 673 | |
1fa38c58 LB |
674 | refilled++; |
675 | rxq->rx_desc_count++; | |
c9df406f | 676 | |
1fa38c58 LB |
677 | rx = rxq->rx_used_desc++; |
678 | if (rxq->rx_used_desc == rxq->rx_ring_size) | |
679 | rxq->rx_used_desc = 0; | |
2257e05c | 680 | |
53771522 LB |
681 | rx_desc = rxq->rx_desc_area + rx; |
682 | ||
530e557a | 683 | size = skb->end - skb->data; |
eb0519b5 | 684 | rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, |
530e557a | 685 | skb->data, size, |
eb0519b5 | 686 | DMA_FROM_DEVICE); |
530e557a | 687 | rx_desc->buf_size = size; |
1fa38c58 LB |
688 | rxq->rx_skb[rx] = skb; |
689 | wmb(); | |
53771522 | 690 | rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; |
1fa38c58 | 691 | wmb(); |
2257e05c | 692 | |
1fa38c58 LB |
693 | /* |
694 | * The hardware automatically prepends 2 bytes of | |
695 | * dummy data to each received packet, so that the | |
696 | * IP header ends up 16-byte aligned. | |
697 | */ | |
698 | skb_reserve(skb, 2); | |
699 | } | |
700 | ||
701 | if (refilled < budget) | |
702 | mp->work_rx_refill &= ~(1 << rxq->index); | |
703 | ||
704 | oom: | |
705 | return refilled; | |
d0412d96 JC |
706 | } |
707 | ||
c9df406f LB |
708 | |
709 | /* tx ***********************************************************************/ | |
c9df406f | 710 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 711 | { |
13d64285 | 712 | int frag; |
1da177e4 | 713 | |
c9df406f | 714 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
13d64285 LB |
715 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
716 | if (fragp->size <= 8 && fragp->page_offset & 7) | |
c9df406f | 717 | return 1; |
1da177e4 | 718 | } |
13d64285 | 719 | |
c9df406f LB |
720 | return 0; |
721 | } | |
7303fde8 | 722 | |
13d64285 | 723 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
c9df406f | 724 | { |
eb0519b5 | 725 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 726 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 727 | int frag; |
1da177e4 | 728 | |
13d64285 LB |
729 | for (frag = 0; frag < nr_frags; frag++) { |
730 | skb_frag_t *this_frag; | |
731 | int tx_index; | |
732 | struct tx_desc *desc; | |
733 | ||
734 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
66823b92 LB |
735 | tx_index = txq->tx_curr_desc++; |
736 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
737 | txq->tx_curr_desc = 0; | |
13d64285 LB |
738 | desc = &txq->tx_desc_area[tx_index]; |
739 | ||
740 | /* | |
741 | * The last fragment will generate an interrupt | |
742 | * which will free the skb on TX completion. | |
743 | */ | |
744 | if (frag == nr_frags - 1) { | |
745 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | | |
746 | ZERO_PADDING | TX_LAST_DESC | | |
747 | TX_ENABLE_INTERRUPT; | |
13d64285 LB |
748 | } else { |
749 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; | |
13d64285 LB |
750 | } |
751 | ||
c9df406f LB |
752 | desc->l4i_chk = 0; |
753 | desc->byte_cnt = this_frag->size; | |
eb0519b5 GP |
754 | desc->buf_ptr = dma_map_page(mp->dev->dev.parent, |
755 | this_frag->page, | |
756 | this_frag->page_offset, | |
757 | this_frag->size, DMA_TO_DEVICE); | |
c9df406f | 758 | } |
1da177e4 LT |
759 | } |
760 | ||
c9df406f LB |
761 | static inline __be16 sum16_as_be(__sum16 sum) |
762 | { | |
763 | return (__force __be16)sum; | |
764 | } | |
1da177e4 | 765 | |
4df89bd5 | 766 | static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) |
1da177e4 | 767 | { |
8fa89bf5 | 768 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 769 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 770 | int tx_index; |
cc9754b3 | 771 | struct tx_desc *desc; |
c9df406f | 772 | u32 cmd_sts; |
4df89bd5 | 773 | u16 l4i_chk; |
c9df406f | 774 | int length; |
1da177e4 | 775 | |
cc9754b3 | 776 | cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
4df89bd5 | 777 | l4i_chk = 0; |
c9df406f LB |
778 | |
779 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
9b2c2ff7 | 780 | int hdr_len; |
4df89bd5 | 781 | int tag_bytes; |
e32b6617 LB |
782 | |
783 | BUG_ON(skb->protocol != htons(ETH_P_IP) && | |
784 | skb->protocol != htons(ETH_P_8021Q)); | |
c9df406f | 785 | |
9b2c2ff7 SB |
786 | hdr_len = (void *)ip_hdr(skb) - (void *)skb->data; |
787 | tag_bytes = hdr_len - ETH_HLEN; | |
788 | if (skb->len - hdr_len > mp->shared->tx_csum_limit || | |
789 | unlikely(tag_bytes & ~12)) { | |
4df89bd5 LB |
790 | if (skb_checksum_help(skb) == 0) |
791 | goto no_csum; | |
792 | kfree_skb(skb); | |
793 | return 1; | |
794 | } | |
c9df406f | 795 | |
4df89bd5 | 796 | if (tag_bytes & 4) |
e32b6617 | 797 | cmd_sts |= MAC_HDR_EXTRA_4_BYTES; |
4df89bd5 | 798 | if (tag_bytes & 8) |
e32b6617 | 799 | cmd_sts |= MAC_HDR_EXTRA_8_BYTES; |
4df89bd5 LB |
800 | |
801 | cmd_sts |= GEN_TCP_UDP_CHECKSUM | | |
802 | GEN_IP_V4_CHECKSUM | | |
803 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; | |
e32b6617 | 804 | |
c9df406f LB |
805 | switch (ip_hdr(skb)->protocol) { |
806 | case IPPROTO_UDP: | |
cc9754b3 | 807 | cmd_sts |= UDP_FRAME; |
4df89bd5 | 808 | l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
c9df406f LB |
809 | break; |
810 | case IPPROTO_TCP: | |
4df89bd5 | 811 | l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); |
c9df406f LB |
812 | break; |
813 | default: | |
814 | BUG(); | |
815 | } | |
816 | } else { | |
4df89bd5 | 817 | no_csum: |
c9df406f | 818 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
cc9754b3 | 819 | cmd_sts |= 5 << TX_IHL_SHIFT; |
c9df406f LB |
820 | } |
821 | ||
66823b92 LB |
822 | tx_index = txq->tx_curr_desc++; |
823 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
824 | txq->tx_curr_desc = 0; | |
4df89bd5 LB |
825 | desc = &txq->tx_desc_area[tx_index]; |
826 | ||
827 | if (nr_frags) { | |
828 | txq_submit_frag_skb(txq, skb); | |
829 | length = skb_headlen(skb); | |
830 | } else { | |
831 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; | |
832 | length = skb->len; | |
833 | } | |
834 | ||
835 | desc->l4i_chk = l4i_chk; | |
836 | desc->byte_cnt = length; | |
eb0519b5 GP |
837 | desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, |
838 | length, DMA_TO_DEVICE); | |
4df89bd5 | 839 | |
99ab08e0 LB |
840 | __skb_queue_tail(&txq->tx_skb, skb); |
841 | ||
c9df406f LB |
842 | /* ensure all other descriptors are written before first cmd_sts */ |
843 | wmb(); | |
844 | desc->cmd_sts = cmd_sts; | |
845 | ||
1fa38c58 LB |
846 | /* clear TX_END status */ |
847 | mp->work_tx_end &= ~(1 << txq->index); | |
8fa89bf5 | 848 | |
c9df406f LB |
849 | /* ensure all descriptors are written before poking hardware */ |
850 | wmb(); | |
13d64285 | 851 | txq_enable(txq); |
c9df406f | 852 | |
13d64285 | 853 | txq->tx_desc_count += nr_frags + 1; |
4df89bd5 LB |
854 | |
855 | return 0; | |
1da177e4 | 856 | } |
1da177e4 | 857 | |
0ccfe64d | 858 | static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 859 | { |
e5371493 | 860 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
e5ef1de1 | 861 | int queue; |
13d64285 | 862 | struct tx_queue *txq; |
e5ef1de1 | 863 | struct netdev_queue *nq; |
afdb57a2 | 864 | |
8fd89211 LB |
865 | queue = skb_get_queue_mapping(skb); |
866 | txq = mp->txq + queue; | |
867 | nq = netdev_get_tx_queue(dev, queue); | |
868 | ||
c9df406f | 869 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
8fd89211 | 870 | txq->tx_dropped++; |
fc32b0e2 LB |
871 | dev_printk(KERN_DEBUG, &dev->dev, |
872 | "failed to linearize skb with tiny " | |
873 | "unaligned fragment\n"); | |
c9df406f LB |
874 | return NETDEV_TX_BUSY; |
875 | } | |
876 | ||
17cd0a59 | 877 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { |
e5ef1de1 LB |
878 | if (net_ratelimit()) |
879 | dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n"); | |
3d6b35bc LB |
880 | kfree_skb(skb); |
881 | return NETDEV_TX_OK; | |
c9df406f LB |
882 | } |
883 | ||
4df89bd5 LB |
884 | if (!txq_submit_skb(txq, skb)) { |
885 | int entries_left; | |
886 | ||
887 | txq->tx_bytes += skb->len; | |
888 | txq->tx_packets++; | |
c9df406f | 889 | |
4df89bd5 LB |
890 | entries_left = txq->tx_ring_size - txq->tx_desc_count; |
891 | if (entries_left < MAX_SKB_FRAGS + 1) | |
892 | netif_tx_stop_queue(nq); | |
893 | } | |
c9df406f | 894 | |
c9df406f | 895 | return NETDEV_TX_OK; |
1da177e4 LT |
896 | } |
897 | ||
c9df406f | 898 | |
1fa38c58 LB |
899 | /* tx napi ******************************************************************/ |
900 | static void txq_kick(struct tx_queue *txq) | |
901 | { | |
902 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 903 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
904 | u32 hw_desc_ptr; |
905 | u32 expected_ptr; | |
906 | ||
8fd89211 | 907 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 | 908 | |
37a6084f | 909 | if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) |
1fa38c58 LB |
910 | goto out; |
911 | ||
37a6084f | 912 | hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); |
1fa38c58 LB |
913 | expected_ptr = (u32)txq->tx_desc_dma + |
914 | txq->tx_curr_desc * sizeof(struct tx_desc); | |
915 | ||
916 | if (hw_desc_ptr != expected_ptr) | |
917 | txq_enable(txq); | |
918 | ||
919 | out: | |
8fd89211 | 920 | __netif_tx_unlock(nq); |
1fa38c58 LB |
921 | |
922 | mp->work_tx_end &= ~(1 << txq->index); | |
923 | } | |
924 | ||
925 | static int txq_reclaim(struct tx_queue *txq, int budget, int force) | |
926 | { | |
927 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 928 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
929 | int reclaimed; |
930 | ||
8fd89211 | 931 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 LB |
932 | |
933 | reclaimed = 0; | |
934 | while (reclaimed < budget && txq->tx_desc_count > 0) { | |
935 | int tx_index; | |
936 | struct tx_desc *desc; | |
937 | u32 cmd_sts; | |
938 | struct sk_buff *skb; | |
1fa38c58 LB |
939 | |
940 | tx_index = txq->tx_used_desc; | |
941 | desc = &txq->tx_desc_area[tx_index]; | |
942 | cmd_sts = desc->cmd_sts; | |
943 | ||
944 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { | |
945 | if (!force) | |
946 | break; | |
947 | desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; | |
948 | } | |
949 | ||
950 | txq->tx_used_desc = tx_index + 1; | |
951 | if (txq->tx_used_desc == txq->tx_ring_size) | |
952 | txq->tx_used_desc = 0; | |
953 | ||
954 | reclaimed++; | |
955 | txq->tx_desc_count--; | |
956 | ||
99ab08e0 LB |
957 | skb = NULL; |
958 | if (cmd_sts & TX_LAST_DESC) | |
959 | skb = __skb_dequeue(&txq->tx_skb); | |
1fa38c58 LB |
960 | |
961 | if (cmd_sts & ERROR_SUMMARY) { | |
962 | dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); | |
963 | mp->dev->stats.tx_errors++; | |
964 | } | |
965 | ||
a418950c | 966 | if (cmd_sts & TX_FIRST_DESC) { |
eb0519b5 | 967 | dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr, |
a418950c LB |
968 | desc->byte_cnt, DMA_TO_DEVICE); |
969 | } else { | |
eb0519b5 | 970 | dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr, |
a418950c LB |
971 | desc->byte_cnt, DMA_TO_DEVICE); |
972 | } | |
1fa38c58 | 973 | |
2bcb4b0f LB |
974 | if (skb != NULL) { |
975 | if (skb_queue_len(&mp->rx_recycle) < | |
e7d2f4db | 976 | mp->rx_ring_size && |
7fd96ce4 | 977 | skb_recycle_check(skb, mp->skb_size)) |
2bcb4b0f LB |
978 | __skb_queue_head(&mp->rx_recycle, skb); |
979 | else | |
980 | dev_kfree_skb(skb); | |
981 | } | |
1fa38c58 LB |
982 | } |
983 | ||
8fd89211 LB |
984 | __netif_tx_unlock(nq); |
985 | ||
1fa38c58 LB |
986 | if (reclaimed < budget) |
987 | mp->work_tx &= ~(1 << txq->index); | |
988 | ||
1fa38c58 LB |
989 | return reclaimed; |
990 | } | |
991 | ||
992 | ||
89df5fdc LB |
993 | /* tx rate control **********************************************************/ |
994 | /* | |
995 | * Set total maximum TX rate (shared by all TX queues for this port) | |
996 | * to 'rate' bits per second, with a maximum burst of 'burst' bytes. | |
997 | */ | |
998 | static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) | |
999 | { | |
1000 | int token_rate; | |
1001 | int mtu; | |
1002 | int bucket_size; | |
1003 | ||
1004 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
1005 | if (token_rate > 1023) | |
1006 | token_rate = 1023; | |
1007 | ||
1008 | mtu = (mp->dev->mtu + 255) >> 8; | |
1009 | if (mtu > 63) | |
1010 | mtu = 63; | |
1011 | ||
1012 | bucket_size = (burst + 255) >> 8; | |
1013 | if (bucket_size > 65535) | |
1014 | bucket_size = 65535; | |
1015 | ||
457b1d5a LB |
1016 | switch (mp->shared->tx_bw_control) { |
1017 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f LB |
1018 | wrlp(mp, TX_BW_RATE, token_rate); |
1019 | wrlp(mp, TX_BW_MTU, mtu); | |
1020 | wrlp(mp, TX_BW_BURST, bucket_size); | |
457b1d5a LB |
1021 | break; |
1022 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f LB |
1023 | wrlp(mp, TX_BW_RATE_MOVED, token_rate); |
1024 | wrlp(mp, TX_BW_MTU_MOVED, mtu); | |
1025 | wrlp(mp, TX_BW_BURST_MOVED, bucket_size); | |
457b1d5a | 1026 | break; |
1e881592 | 1027 | } |
89df5fdc LB |
1028 | } |
1029 | ||
1030 | static void txq_set_rate(struct tx_queue *txq, int rate, int burst) | |
1031 | { | |
1032 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1033 | int token_rate; | |
1034 | int bucket_size; | |
1035 | ||
1036 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
1037 | if (token_rate > 1023) | |
1038 | token_rate = 1023; | |
1039 | ||
1040 | bucket_size = (burst + 255) >> 8; | |
1041 | if (bucket_size > 65535) | |
1042 | bucket_size = 65535; | |
1043 | ||
37a6084f LB |
1044 | wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); |
1045 | wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); | |
89df5fdc LB |
1046 | } |
1047 | ||
1048 | static void txq_set_fixed_prio_mode(struct tx_queue *txq) | |
1049 | { | |
1050 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1051 | int off; | |
1052 | u32 val; | |
1053 | ||
1054 | /* | |
1055 | * Turn on fixed priority mode. | |
1056 | */ | |
457b1d5a LB |
1057 | off = 0; |
1058 | switch (mp->shared->tx_bw_control) { | |
1059 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f | 1060 | off = TXQ_FIX_PRIO_CONF; |
457b1d5a LB |
1061 | break; |
1062 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f | 1063 | off = TXQ_FIX_PRIO_CONF_MOVED; |
457b1d5a LB |
1064 | break; |
1065 | } | |
89df5fdc | 1066 | |
457b1d5a | 1067 | if (off) { |
37a6084f | 1068 | val = rdlp(mp, off); |
457b1d5a | 1069 | val |= 1 << txq->index; |
37a6084f | 1070 | wrlp(mp, off, val); |
457b1d5a | 1071 | } |
89df5fdc LB |
1072 | } |
1073 | ||
89df5fdc | 1074 | |
c9df406f | 1075 | /* mii management interface *************************************************/ |
45c5d3bc LB |
1076 | static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id) |
1077 | { | |
1078 | struct mv643xx_eth_shared_private *msp = dev_id; | |
1079 | ||
1080 | if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) { | |
1081 | writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE); | |
1082 | wake_up(&msp->smi_busy_wait); | |
1083 | return IRQ_HANDLED; | |
1084 | } | |
1085 | ||
1086 | return IRQ_NONE; | |
1087 | } | |
c9df406f | 1088 | |
45c5d3bc | 1089 | static int smi_is_done(struct mv643xx_eth_shared_private *msp) |
1da177e4 | 1090 | { |
45c5d3bc LB |
1091 | return !(readl(msp->base + SMI_REG) & SMI_BUSY); |
1092 | } | |
1da177e4 | 1093 | |
45c5d3bc LB |
1094 | static int smi_wait_ready(struct mv643xx_eth_shared_private *msp) |
1095 | { | |
1096 | if (msp->err_interrupt == NO_IRQ) { | |
1097 | int i; | |
c9df406f | 1098 | |
45c5d3bc LB |
1099 | for (i = 0; !smi_is_done(msp); i++) { |
1100 | if (i == 10) | |
1101 | return -ETIMEDOUT; | |
1102 | msleep(10); | |
c9df406f | 1103 | } |
45c5d3bc LB |
1104 | |
1105 | return 0; | |
1106 | } | |
1107 | ||
ee04448d LB |
1108 | if (!smi_is_done(msp)) { |
1109 | wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), | |
1110 | msecs_to_jiffies(100)); | |
1111 | if (!smi_is_done(msp)) | |
1112 | return -ETIMEDOUT; | |
1113 | } | |
45c5d3bc LB |
1114 | |
1115 | return 0; | |
1116 | } | |
1117 | ||
ed94493f | 1118 | static int smi_bus_read(struct mii_bus *bus, int addr, int reg) |
45c5d3bc | 1119 | { |
ed94493f | 1120 | struct mv643xx_eth_shared_private *msp = bus->priv; |
45c5d3bc LB |
1121 | void __iomem *smi_reg = msp->base + SMI_REG; |
1122 | int ret; | |
1123 | ||
45c5d3bc | 1124 | if (smi_wait_ready(msp)) { |
10a9948d | 1125 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f | 1126 | return -ETIMEDOUT; |
1da177e4 LT |
1127 | } |
1128 | ||
fc32b0e2 | 1129 | writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); |
1da177e4 | 1130 | |
45c5d3bc | 1131 | if (smi_wait_ready(msp)) { |
10a9948d | 1132 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f | 1133 | return -ETIMEDOUT; |
45c5d3bc LB |
1134 | } |
1135 | ||
1136 | ret = readl(smi_reg); | |
1137 | if (!(ret & SMI_READ_VALID)) { | |
10a9948d | 1138 | printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n"); |
ed94493f | 1139 | return -ENODEV; |
c9df406f LB |
1140 | } |
1141 | ||
ed94493f | 1142 | return ret & 0xffff; |
1da177e4 LT |
1143 | } |
1144 | ||
ed94493f | 1145 | static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val) |
1da177e4 | 1146 | { |
ed94493f | 1147 | struct mv643xx_eth_shared_private *msp = bus->priv; |
45c5d3bc | 1148 | void __iomem *smi_reg = msp->base + SMI_REG; |
1da177e4 | 1149 | |
45c5d3bc | 1150 | if (smi_wait_ready(msp)) { |
10a9948d | 1151 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
45c5d3bc | 1152 | return -ETIMEDOUT; |
1da177e4 LT |
1153 | } |
1154 | ||
fc32b0e2 | 1155 | writel(SMI_OPCODE_WRITE | (reg << 21) | |
ed94493f | 1156 | (addr << 16) | (val & 0xffff), smi_reg); |
45c5d3bc | 1157 | |
ed94493f | 1158 | if (smi_wait_ready(msp)) { |
10a9948d | 1159 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f LB |
1160 | return -ETIMEDOUT; |
1161 | } | |
45c5d3bc LB |
1162 | |
1163 | return 0; | |
c9df406f | 1164 | } |
1da177e4 | 1165 | |
c9df406f | 1166 | |
8fd89211 LB |
1167 | /* statistics ***************************************************************/ |
1168 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) | |
1169 | { | |
1170 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1171 | struct net_device_stats *stats = &dev->stats; | |
1172 | unsigned long tx_packets = 0; | |
1173 | unsigned long tx_bytes = 0; | |
1174 | unsigned long tx_dropped = 0; | |
1175 | int i; | |
1176 | ||
1177 | for (i = 0; i < mp->txq_count; i++) { | |
1178 | struct tx_queue *txq = mp->txq + i; | |
1179 | ||
1180 | tx_packets += txq->tx_packets; | |
1181 | tx_bytes += txq->tx_bytes; | |
1182 | tx_dropped += txq->tx_dropped; | |
1183 | } | |
1184 | ||
1185 | stats->tx_packets = tx_packets; | |
1186 | stats->tx_bytes = tx_bytes; | |
1187 | stats->tx_dropped = tx_dropped; | |
1188 | ||
1189 | return stats; | |
1190 | } | |
1191 | ||
eaf5d590 LB |
1192 | static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp) |
1193 | { | |
1194 | u32 lro_aggregated = 0; | |
1195 | u32 lro_flushed = 0; | |
1196 | u32 lro_no_desc = 0; | |
1197 | int i; | |
1198 | ||
eaf5d590 LB |
1199 | for (i = 0; i < mp->rxq_count; i++) { |
1200 | struct rx_queue *rxq = mp->rxq + i; | |
1201 | ||
1202 | lro_aggregated += rxq->lro_mgr.stats.aggregated; | |
1203 | lro_flushed += rxq->lro_mgr.stats.flushed; | |
1204 | lro_no_desc += rxq->lro_mgr.stats.no_desc; | |
1205 | } | |
eaf5d590 LB |
1206 | |
1207 | mp->lro_counters.lro_aggregated = lro_aggregated; | |
1208 | mp->lro_counters.lro_flushed = lro_flushed; | |
1209 | mp->lro_counters.lro_no_desc = lro_no_desc; | |
1210 | } | |
1211 | ||
fc32b0e2 | 1212 | static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 1213 | { |
fc32b0e2 | 1214 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
1da177e4 LT |
1215 | } |
1216 | ||
fc32b0e2 | 1217 | static void mib_counters_clear(struct mv643xx_eth_private *mp) |
d0412d96 | 1218 | { |
fc32b0e2 LB |
1219 | int i; |
1220 | ||
1221 | for (i = 0; i < 0x80; i += 4) | |
1222 | mib_read(mp, i); | |
c9df406f | 1223 | } |
d0412d96 | 1224 | |
fc32b0e2 | 1225 | static void mib_counters_update(struct mv643xx_eth_private *mp) |
c9df406f | 1226 | { |
e5371493 | 1227 | struct mib_counters *p = &mp->mib_counters; |
4b8e3655 | 1228 | |
57e8f26a | 1229 | spin_lock_bh(&mp->mib_counters_lock); |
fc32b0e2 | 1230 | p->good_octets_received += mib_read(mp, 0x00); |
fc32b0e2 LB |
1231 | p->bad_octets_received += mib_read(mp, 0x08); |
1232 | p->internal_mac_transmit_err += mib_read(mp, 0x0c); | |
1233 | p->good_frames_received += mib_read(mp, 0x10); | |
1234 | p->bad_frames_received += mib_read(mp, 0x14); | |
1235 | p->broadcast_frames_received += mib_read(mp, 0x18); | |
1236 | p->multicast_frames_received += mib_read(mp, 0x1c); | |
1237 | p->frames_64_octets += mib_read(mp, 0x20); | |
1238 | p->frames_65_to_127_octets += mib_read(mp, 0x24); | |
1239 | p->frames_128_to_255_octets += mib_read(mp, 0x28); | |
1240 | p->frames_256_to_511_octets += mib_read(mp, 0x2c); | |
1241 | p->frames_512_to_1023_octets += mib_read(mp, 0x30); | |
1242 | p->frames_1024_to_max_octets += mib_read(mp, 0x34); | |
1243 | p->good_octets_sent += mib_read(mp, 0x38); | |
fc32b0e2 LB |
1244 | p->good_frames_sent += mib_read(mp, 0x40); |
1245 | p->excessive_collision += mib_read(mp, 0x44); | |
1246 | p->multicast_frames_sent += mib_read(mp, 0x48); | |
1247 | p->broadcast_frames_sent += mib_read(mp, 0x4c); | |
1248 | p->unrec_mac_control_received += mib_read(mp, 0x50); | |
1249 | p->fc_sent += mib_read(mp, 0x54); | |
1250 | p->good_fc_received += mib_read(mp, 0x58); | |
1251 | p->bad_fc_received += mib_read(mp, 0x5c); | |
1252 | p->undersize_received += mib_read(mp, 0x60); | |
1253 | p->fragments_received += mib_read(mp, 0x64); | |
1254 | p->oversize_received += mib_read(mp, 0x68); | |
1255 | p->jabber_received += mib_read(mp, 0x6c); | |
1256 | p->mac_receive_error += mib_read(mp, 0x70); | |
1257 | p->bad_crc_event += mib_read(mp, 0x74); | |
1258 | p->collision += mib_read(mp, 0x78); | |
1259 | p->late_collision += mib_read(mp, 0x7c); | |
57e8f26a | 1260 | spin_unlock_bh(&mp->mib_counters_lock); |
4ff3495a LB |
1261 | |
1262 | mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); | |
1263 | } | |
1264 | ||
1265 | static void mib_counters_timer_wrapper(unsigned long _mp) | |
1266 | { | |
1267 | struct mv643xx_eth_private *mp = (void *)_mp; | |
1268 | ||
1269 | mib_counters_update(mp); | |
d0412d96 JC |
1270 | } |
1271 | ||
c9df406f | 1272 | |
3e508034 LB |
1273 | /* interrupt coalescing *****************************************************/ |
1274 | /* | |
1275 | * Hardware coalescing parameters are set in units of 64 t_clk | |
1276 | * cycles. I.e.: | |
1277 | * | |
1278 | * coal_delay_in_usec = 64000000 * register_value / t_clk_rate | |
1279 | * | |
1280 | * register_value = coal_delay_in_usec * t_clk_rate / 64000000 | |
1281 | * | |
1282 | * In the ->set*() methods, we round the computed register value | |
1283 | * to the nearest integer. | |
1284 | */ | |
1285 | static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) | |
1286 | { | |
1287 | u32 val = rdlp(mp, SDMA_CONFIG); | |
1288 | u64 temp; | |
1289 | ||
1290 | if (mp->shared->extended_rx_coal_limit) | |
1291 | temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); | |
1292 | else | |
1293 | temp = (val & 0x003fff00) >> 8; | |
1294 | ||
1295 | temp *= 64000000; | |
1296 | do_div(temp, mp->shared->t_clk); | |
1297 | ||
1298 | return (unsigned int)temp; | |
1299 | } | |
1300 | ||
1301 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1302 | { | |
1303 | u64 temp; | |
1304 | u32 val; | |
1305 | ||
1306 | temp = (u64)usec * mp->shared->t_clk; | |
1307 | temp += 31999999; | |
1308 | do_div(temp, 64000000); | |
1309 | ||
1310 | val = rdlp(mp, SDMA_CONFIG); | |
1311 | if (mp->shared->extended_rx_coal_limit) { | |
1312 | if (temp > 0xffff) | |
1313 | temp = 0xffff; | |
1314 | val &= ~0x023fff80; | |
1315 | val |= (temp & 0x8000) << 10; | |
1316 | val |= (temp & 0x7fff) << 7; | |
1317 | } else { | |
1318 | if (temp > 0x3fff) | |
1319 | temp = 0x3fff; | |
1320 | val &= ~0x003fff00; | |
1321 | val |= (temp & 0x3fff) << 8; | |
1322 | } | |
1323 | wrlp(mp, SDMA_CONFIG, val); | |
1324 | } | |
1325 | ||
1326 | static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) | |
1327 | { | |
1328 | u64 temp; | |
1329 | ||
1330 | temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; | |
1331 | temp *= 64000000; | |
1332 | do_div(temp, mp->shared->t_clk); | |
1333 | ||
1334 | return (unsigned int)temp; | |
1335 | } | |
1336 | ||
1337 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1338 | { | |
1339 | u64 temp; | |
1340 | ||
1341 | temp = (u64)usec * mp->shared->t_clk; | |
1342 | temp += 31999999; | |
1343 | do_div(temp, 64000000); | |
1344 | ||
1345 | if (temp > 0x3fff) | |
1346 | temp = 0x3fff; | |
1347 | ||
1348 | wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); | |
1349 | } | |
1350 | ||
1351 | ||
c9df406f | 1352 | /* ethtool ******************************************************************/ |
e5371493 | 1353 | struct mv643xx_eth_stats { |
c9df406f LB |
1354 | char stat_string[ETH_GSTRING_LEN]; |
1355 | int sizeof_stat; | |
16820054 LB |
1356 | int netdev_off; |
1357 | int mp_off; | |
c9df406f LB |
1358 | }; |
1359 | ||
16820054 LB |
1360 | #define SSTAT(m) \ |
1361 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ | |
1362 | offsetof(struct net_device, stats.m), -1 } | |
1363 | ||
1364 | #define MIBSTAT(m) \ | |
1365 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ | |
1366 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } | |
1367 | ||
eaf5d590 LB |
1368 | #define LROSTAT(m) \ |
1369 | { #m, FIELD_SIZEOF(struct lro_counters, m), \ | |
1370 | -1, offsetof(struct mv643xx_eth_private, lro_counters.m) } | |
1371 | ||
16820054 LB |
1372 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { |
1373 | SSTAT(rx_packets), | |
1374 | SSTAT(tx_packets), | |
1375 | SSTAT(rx_bytes), | |
1376 | SSTAT(tx_bytes), | |
1377 | SSTAT(rx_errors), | |
1378 | SSTAT(tx_errors), | |
1379 | SSTAT(rx_dropped), | |
1380 | SSTAT(tx_dropped), | |
1381 | MIBSTAT(good_octets_received), | |
1382 | MIBSTAT(bad_octets_received), | |
1383 | MIBSTAT(internal_mac_transmit_err), | |
1384 | MIBSTAT(good_frames_received), | |
1385 | MIBSTAT(bad_frames_received), | |
1386 | MIBSTAT(broadcast_frames_received), | |
1387 | MIBSTAT(multicast_frames_received), | |
1388 | MIBSTAT(frames_64_octets), | |
1389 | MIBSTAT(frames_65_to_127_octets), | |
1390 | MIBSTAT(frames_128_to_255_octets), | |
1391 | MIBSTAT(frames_256_to_511_octets), | |
1392 | MIBSTAT(frames_512_to_1023_octets), | |
1393 | MIBSTAT(frames_1024_to_max_octets), | |
1394 | MIBSTAT(good_octets_sent), | |
1395 | MIBSTAT(good_frames_sent), | |
1396 | MIBSTAT(excessive_collision), | |
1397 | MIBSTAT(multicast_frames_sent), | |
1398 | MIBSTAT(broadcast_frames_sent), | |
1399 | MIBSTAT(unrec_mac_control_received), | |
1400 | MIBSTAT(fc_sent), | |
1401 | MIBSTAT(good_fc_received), | |
1402 | MIBSTAT(bad_fc_received), | |
1403 | MIBSTAT(undersize_received), | |
1404 | MIBSTAT(fragments_received), | |
1405 | MIBSTAT(oversize_received), | |
1406 | MIBSTAT(jabber_received), | |
1407 | MIBSTAT(mac_receive_error), | |
1408 | MIBSTAT(bad_crc_event), | |
1409 | MIBSTAT(collision), | |
1410 | MIBSTAT(late_collision), | |
eaf5d590 LB |
1411 | LROSTAT(lro_aggregated), |
1412 | LROSTAT(lro_flushed), | |
1413 | LROSTAT(lro_no_desc), | |
c9df406f LB |
1414 | }; |
1415 | ||
10a9948d | 1416 | static int |
6bdf576e LB |
1417 | mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, |
1418 | struct ethtool_cmd *cmd) | |
d0412d96 | 1419 | { |
d0412d96 JC |
1420 | int err; |
1421 | ||
ed94493f LB |
1422 | err = phy_read_status(mp->phy); |
1423 | if (err == 0) | |
1424 | err = phy_ethtool_gset(mp->phy, cmd); | |
d0412d96 | 1425 | |
fc32b0e2 LB |
1426 | /* |
1427 | * The MAC does not support 1000baseT_Half. | |
1428 | */ | |
d0412d96 JC |
1429 | cmd->supported &= ~SUPPORTED_1000baseT_Half; |
1430 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1431 | ||
1432 | return err; | |
1433 | } | |
1434 | ||
10a9948d | 1435 | static int |
6bdf576e | 1436 | mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, |
10a9948d | 1437 | struct ethtool_cmd *cmd) |
bedfe324 | 1438 | { |
81600eea LB |
1439 | u32 port_status; |
1440 | ||
37a6084f | 1441 | port_status = rdlp(mp, PORT_STATUS); |
81600eea | 1442 | |
bedfe324 LB |
1443 | cmd->supported = SUPPORTED_MII; |
1444 | cmd->advertising = ADVERTISED_MII; | |
81600eea LB |
1445 | switch (port_status & PORT_SPEED_MASK) { |
1446 | case PORT_SPEED_10: | |
1447 | cmd->speed = SPEED_10; | |
1448 | break; | |
1449 | case PORT_SPEED_100: | |
1450 | cmd->speed = SPEED_100; | |
1451 | break; | |
1452 | case PORT_SPEED_1000: | |
1453 | cmd->speed = SPEED_1000; | |
1454 | break; | |
1455 | default: | |
1456 | cmd->speed = -1; | |
1457 | break; | |
1458 | } | |
1459 | cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; | |
bedfe324 LB |
1460 | cmd->port = PORT_MII; |
1461 | cmd->phy_address = 0; | |
1462 | cmd->transceiver = XCVR_INTERNAL; | |
1463 | cmd->autoneg = AUTONEG_DISABLE; | |
1464 | cmd->maxtxpkt = 1; | |
1465 | cmd->maxrxpkt = 1; | |
1466 | ||
1467 | return 0; | |
1468 | } | |
1469 | ||
6bdf576e LB |
1470 | static int |
1471 | mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1472 | { | |
1473 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1474 | ||
1475 | if (mp->phy != NULL) | |
1476 | return mv643xx_eth_get_settings_phy(mp, cmd); | |
1477 | else | |
1478 | return mv643xx_eth_get_settings_phyless(mp, cmd); | |
1479 | } | |
1480 | ||
10a9948d LB |
1481 | static int |
1482 | mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1da177e4 | 1483 | { |
e5371493 | 1484 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
ab4384a6 | 1485 | |
6bdf576e LB |
1486 | if (mp->phy == NULL) |
1487 | return -EINVAL; | |
1488 | ||
fc32b0e2 LB |
1489 | /* |
1490 | * The MAC does not support 1000baseT_Half. | |
1491 | */ | |
1492 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1493 | ||
ed94493f | 1494 | return phy_ethtool_sset(mp->phy, cmd); |
c9df406f | 1495 | } |
1da177e4 | 1496 | |
fc32b0e2 LB |
1497 | static void mv643xx_eth_get_drvinfo(struct net_device *dev, |
1498 | struct ethtool_drvinfo *drvinfo) | |
c9df406f | 1499 | { |
e5371493 LB |
1500 | strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); |
1501 | strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); | |
c9df406f | 1502 | strncpy(drvinfo->fw_version, "N/A", 32); |
fc32b0e2 | 1503 | strncpy(drvinfo->bus_info, "platform", 32); |
16820054 | 1504 | drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); |
c9df406f | 1505 | } |
1da177e4 | 1506 | |
fc32b0e2 | 1507 | static int mv643xx_eth_nway_reset(struct net_device *dev) |
c9df406f | 1508 | { |
e5371493 | 1509 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1510 | |
6bdf576e LB |
1511 | if (mp->phy == NULL) |
1512 | return -EINVAL; | |
1da177e4 | 1513 | |
6bdf576e | 1514 | return genphy_restart_aneg(mp->phy); |
bedfe324 LB |
1515 | } |
1516 | ||
3e508034 LB |
1517 | static int |
1518 | mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1519 | { | |
1520 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1521 | ||
1522 | ec->rx_coalesce_usecs = get_rx_coal(mp); | |
1523 | ec->tx_coalesce_usecs = get_tx_coal(mp); | |
1524 | ||
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | static int | |
1529 | mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1530 | { | |
1531 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1532 | ||
1533 | set_rx_coal(mp, ec->rx_coalesce_usecs); | |
1534 | set_tx_coal(mp, ec->tx_coalesce_usecs); | |
1535 | ||
1536 | return 0; | |
1537 | } | |
1538 | ||
e7d2f4db LB |
1539 | static void |
1540 | mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1541 | { | |
1542 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1543 | ||
1544 | er->rx_max_pending = 4096; | |
1545 | er->tx_max_pending = 4096; | |
1546 | er->rx_mini_max_pending = 0; | |
1547 | er->rx_jumbo_max_pending = 0; | |
1548 | ||
1549 | er->rx_pending = mp->rx_ring_size; | |
1550 | er->tx_pending = mp->tx_ring_size; | |
1551 | er->rx_mini_pending = 0; | |
1552 | er->rx_jumbo_pending = 0; | |
1553 | } | |
1554 | ||
1555 | static int | |
1556 | mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1557 | { | |
1558 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1559 | ||
1560 | if (er->rx_mini_pending || er->rx_jumbo_pending) | |
1561 | return -EINVAL; | |
1562 | ||
1563 | mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; | |
1564 | mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096; | |
1565 | ||
1566 | if (netif_running(dev)) { | |
1567 | mv643xx_eth_stop(dev); | |
1568 | if (mv643xx_eth_open(dev)) { | |
1569 | dev_printk(KERN_ERR, &dev->dev, | |
1570 | "fatal error on re-opening device after " | |
1571 | "ring param change\n"); | |
1572 | return -ENOMEM; | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | ||
d888b373 LB |
1579 | static u32 |
1580 | mv643xx_eth_get_rx_csum(struct net_device *dev) | |
1581 | { | |
1582 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1583 | ||
1584 | return !!(rdlp(mp, PORT_CONFIG) & 0x02000000); | |
1585 | } | |
1586 | ||
1587 | static int | |
1588 | mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum) | |
1589 | { | |
1590 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1591 | ||
1592 | wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); | |
1593 | ||
1594 | return 0; | |
1595 | } | |
1596 | ||
fc32b0e2 LB |
1597 | static void mv643xx_eth_get_strings(struct net_device *dev, |
1598 | uint32_t stringset, uint8_t *data) | |
c9df406f LB |
1599 | { |
1600 | int i; | |
1da177e4 | 1601 | |
fc32b0e2 LB |
1602 | if (stringset == ETH_SS_STATS) { |
1603 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { | |
c9df406f | 1604 | memcpy(data + i * ETH_GSTRING_LEN, |
16820054 | 1605 | mv643xx_eth_stats[i].stat_string, |
e5371493 | 1606 | ETH_GSTRING_LEN); |
c9df406f | 1607 | } |
c9df406f LB |
1608 | } |
1609 | } | |
1da177e4 | 1610 | |
fc32b0e2 LB |
1611 | static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, |
1612 | struct ethtool_stats *stats, | |
1613 | uint64_t *data) | |
c9df406f | 1614 | { |
b9873841 | 1615 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 1616 | int i; |
1da177e4 | 1617 | |
8fd89211 | 1618 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 1619 | mib_counters_update(mp); |
eaf5d590 | 1620 | mv643xx_eth_grab_lro_stats(mp); |
1da177e4 | 1621 | |
16820054 LB |
1622 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
1623 | const struct mv643xx_eth_stats *stat; | |
1624 | void *p; | |
1625 | ||
1626 | stat = mv643xx_eth_stats + i; | |
1627 | ||
1628 | if (stat->netdev_off >= 0) | |
1629 | p = ((void *)mp->dev) + stat->netdev_off; | |
1630 | else | |
1631 | p = ((void *)mp) + stat->mp_off; | |
1632 | ||
1633 | data[i] = (stat->sizeof_stat == 8) ? | |
1634 | *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1635 | } |
c9df406f | 1636 | } |
1da177e4 | 1637 | |
1437ce39 BH |
1638 | static int mv643xx_eth_set_flags(struct net_device *dev, u32 data) |
1639 | { | |
1640 | return ethtool_op_set_flags(dev, data, ETH_FLAG_LRO); | |
1641 | } | |
1642 | ||
fc32b0e2 | 1643 | static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) |
c9df406f | 1644 | { |
fc32b0e2 | 1645 | if (sset == ETH_SS_STATS) |
16820054 | 1646 | return ARRAY_SIZE(mv643xx_eth_stats); |
fc32b0e2 LB |
1647 | |
1648 | return -EOPNOTSUPP; | |
c9df406f | 1649 | } |
1da177e4 | 1650 | |
e5371493 | 1651 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
fc32b0e2 LB |
1652 | .get_settings = mv643xx_eth_get_settings, |
1653 | .set_settings = mv643xx_eth_set_settings, | |
1654 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1655 | .nway_reset = mv643xx_eth_nway_reset, | |
ed4ba4b5 | 1656 | .get_link = ethtool_op_get_link, |
3e508034 LB |
1657 | .get_coalesce = mv643xx_eth_get_coalesce, |
1658 | .set_coalesce = mv643xx_eth_set_coalesce, | |
e7d2f4db LB |
1659 | .get_ringparam = mv643xx_eth_get_ringparam, |
1660 | .set_ringparam = mv643xx_eth_set_ringparam, | |
d888b373 LB |
1661 | .get_rx_csum = mv643xx_eth_get_rx_csum, |
1662 | .set_rx_csum = mv643xx_eth_set_rx_csum, | |
b8df184f | 1663 | .set_tx_csum = ethtool_op_set_tx_csum, |
c9df406f | 1664 | .set_sg = ethtool_op_set_sg, |
fc32b0e2 LB |
1665 | .get_strings = mv643xx_eth_get_strings, |
1666 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
eaf5d590 | 1667 | .get_flags = ethtool_op_get_flags, |
1437ce39 | 1668 | .set_flags = mv643xx_eth_set_flags, |
e5371493 | 1669 | .get_sset_count = mv643xx_eth_get_sset_count, |
c9df406f | 1670 | }; |
1da177e4 | 1671 | |
bea3348e | 1672 | |
c9df406f | 1673 | /* address handling *********************************************************/ |
5daffe94 | 1674 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1675 | { |
66e63ffb LB |
1676 | unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); |
1677 | unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); | |
1da177e4 | 1678 | |
5daffe94 LB |
1679 | addr[0] = (mac_h >> 24) & 0xff; |
1680 | addr[1] = (mac_h >> 16) & 0xff; | |
1681 | addr[2] = (mac_h >> 8) & 0xff; | |
1682 | addr[3] = mac_h & 0xff; | |
1683 | addr[4] = (mac_l >> 8) & 0xff; | |
1684 | addr[5] = mac_l & 0xff; | |
c9df406f | 1685 | } |
1da177e4 | 1686 | |
66e63ffb | 1687 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1688 | { |
66e63ffb LB |
1689 | wrlp(mp, MAC_ADDR_HIGH, |
1690 | (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); | |
1691 | wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); | |
c9df406f | 1692 | } |
d0412d96 | 1693 | |
66e63ffb | 1694 | static u32 uc_addr_filter_mask(struct net_device *dev) |
c9df406f | 1695 | { |
ccffad25 | 1696 | struct netdev_hw_addr *ha; |
66e63ffb | 1697 | u32 nibbles; |
1da177e4 | 1698 | |
66e63ffb LB |
1699 | if (dev->flags & IFF_PROMISC) |
1700 | return 0; | |
1da177e4 | 1701 | |
66e63ffb | 1702 | nibbles = 1 << (dev->dev_addr[5] & 0x0f); |
32e7bfc4 | 1703 | netdev_for_each_uc_addr(ha, dev) { |
ccffad25 | 1704 | if (memcmp(dev->dev_addr, ha->addr, 5)) |
66e63ffb | 1705 | return 0; |
ccffad25 | 1706 | if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0) |
66e63ffb | 1707 | return 0; |
ff561eef | 1708 | |
ccffad25 | 1709 | nibbles |= 1 << (ha->addr[5] & 0x0f); |
66e63ffb | 1710 | } |
1da177e4 | 1711 | |
66e63ffb | 1712 | return nibbles; |
1da177e4 LT |
1713 | } |
1714 | ||
66e63ffb | 1715 | static void mv643xx_eth_program_unicast_filter(struct net_device *dev) |
1da177e4 | 1716 | { |
e5371493 | 1717 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1718 | u32 port_config; |
1719 | u32 nibbles; | |
1720 | int i; | |
1da177e4 | 1721 | |
cc9754b3 | 1722 | uc_addr_set(mp, dev->dev_addr); |
1da177e4 | 1723 | |
6877f54e PS |
1724 | port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE; |
1725 | ||
66e63ffb LB |
1726 | nibbles = uc_addr_filter_mask(dev); |
1727 | if (!nibbles) { | |
1728 | port_config |= UNICAST_PROMISCUOUS_MODE; | |
6877f54e | 1729 | nibbles = 0xffff; |
66e63ffb LB |
1730 | } |
1731 | ||
1732 | for (i = 0; i < 16; i += 4) { | |
1733 | int off = UNICAST_TABLE(mp->port_num) + i; | |
1734 | u32 v; | |
1735 | ||
1736 | v = 0; | |
1737 | if (nibbles & 1) | |
1738 | v |= 0x00000001; | |
1739 | if (nibbles & 2) | |
1740 | v |= 0x00000100; | |
1741 | if (nibbles & 4) | |
1742 | v |= 0x00010000; | |
1743 | if (nibbles & 8) | |
1744 | v |= 0x01000000; | |
1745 | nibbles >>= 4; | |
1746 | ||
1747 | wrl(mp, off, v); | |
1748 | } | |
1749 | ||
66e63ffb | 1750 | wrlp(mp, PORT_CONFIG, port_config); |
1da177e4 LT |
1751 | } |
1752 | ||
69876569 LB |
1753 | static int addr_crc(unsigned char *addr) |
1754 | { | |
1755 | int crc = 0; | |
1756 | int i; | |
1757 | ||
1758 | for (i = 0; i < 6; i++) { | |
1759 | int j; | |
1760 | ||
1761 | crc = (crc ^ addr[i]) << 8; | |
1762 | for (j = 7; j >= 0; j--) { | |
1763 | if (crc & (0x100 << j)) | |
1764 | crc ^= 0x107 << j; | |
1765 | } | |
1766 | } | |
1767 | ||
1768 | return crc; | |
1769 | } | |
1770 | ||
66e63ffb | 1771 | static void mv643xx_eth_program_multicast_filter(struct net_device *dev) |
1da177e4 | 1772 | { |
fc32b0e2 | 1773 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1774 | u32 *mc_spec; |
1775 | u32 *mc_other; | |
22bedad3 | 1776 | struct netdev_hw_addr *ha; |
fc32b0e2 | 1777 | int i; |
c8aaea25 | 1778 | |
fc32b0e2 | 1779 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { |
66e63ffb LB |
1780 | int port_num; |
1781 | u32 accept; | |
c8aaea25 | 1782 | |
66e63ffb LB |
1783 | oom: |
1784 | port_num = mp->port_num; | |
1785 | accept = 0x01010101; | |
fc32b0e2 LB |
1786 | for (i = 0; i < 0x100; i += 4) { |
1787 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); | |
1788 | wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); | |
c9df406f LB |
1789 | } |
1790 | return; | |
1791 | } | |
c8aaea25 | 1792 | |
82a5bd6a | 1793 | mc_spec = kmalloc(0x200, GFP_ATOMIC); |
66e63ffb LB |
1794 | if (mc_spec == NULL) |
1795 | goto oom; | |
1796 | mc_other = mc_spec + (0x100 >> 2); | |
1797 | ||
1798 | memset(mc_spec, 0, 0x100); | |
1799 | memset(mc_other, 0, 0x100); | |
1da177e4 | 1800 | |
22bedad3 JP |
1801 | netdev_for_each_mc_addr(ha, dev) { |
1802 | u8 *a = ha->addr; | |
66e63ffb LB |
1803 | u32 *table; |
1804 | int entry; | |
1da177e4 | 1805 | |
fc32b0e2 | 1806 | if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { |
66e63ffb LB |
1807 | table = mc_spec; |
1808 | entry = a[5]; | |
fc32b0e2 | 1809 | } else { |
66e63ffb LB |
1810 | table = mc_other; |
1811 | entry = addr_crc(a); | |
fc32b0e2 | 1812 | } |
66e63ffb | 1813 | |
2b448334 | 1814 | table[entry >> 2] |= 1 << (8 * (entry & 3)); |
fc32b0e2 | 1815 | } |
66e63ffb LB |
1816 | |
1817 | for (i = 0; i < 0x100; i += 4) { | |
1818 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]); | |
1819 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]); | |
1820 | } | |
1821 | ||
1822 | kfree(mc_spec); | |
1823 | } | |
1824 | ||
1825 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
1826 | { | |
1827 | mv643xx_eth_program_unicast_filter(dev); | |
1828 | mv643xx_eth_program_multicast_filter(dev); | |
1829 | } | |
1830 | ||
1831 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
1832 | { | |
1833 | struct sockaddr *sa = addr; | |
1834 | ||
a29ec08a DK |
1835 | if (!is_valid_ether_addr(sa->sa_data)) |
1836 | return -EINVAL; | |
1837 | ||
66e63ffb LB |
1838 | memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); |
1839 | ||
1840 | netif_addr_lock_bh(dev); | |
1841 | mv643xx_eth_program_unicast_filter(dev); | |
1842 | netif_addr_unlock_bh(dev); | |
1843 | ||
1844 | return 0; | |
c9df406f | 1845 | } |
c8aaea25 | 1846 | |
c8aaea25 | 1847 | |
c9df406f | 1848 | /* rx/tx queue initialisation ***********************************************/ |
64da80a2 | 1849 | static int rxq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1850 | { |
64da80a2 | 1851 | struct rx_queue *rxq = mp->rxq + index; |
8a578111 LB |
1852 | struct rx_desc *rx_desc; |
1853 | int size; | |
c9df406f LB |
1854 | int i; |
1855 | ||
64da80a2 LB |
1856 | rxq->index = index; |
1857 | ||
e7d2f4db | 1858 | rxq->rx_ring_size = mp->rx_ring_size; |
8a578111 LB |
1859 | |
1860 | rxq->rx_desc_count = 0; | |
1861 | rxq->rx_curr_desc = 0; | |
1862 | rxq->rx_used_desc = 0; | |
1863 | ||
1864 | size = rxq->rx_ring_size * sizeof(struct rx_desc); | |
1865 | ||
f7981c1c | 1866 | if (index == 0 && size <= mp->rx_desc_sram_size) { |
8a578111 LB |
1867 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, |
1868 | mp->rx_desc_sram_size); | |
1869 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; | |
1870 | } else { | |
eb0519b5 GP |
1871 | rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, |
1872 | size, &rxq->rx_desc_dma, | |
1873 | GFP_KERNEL); | |
f7ea3337 PJ |
1874 | } |
1875 | ||
8a578111 LB |
1876 | if (rxq->rx_desc_area == NULL) { |
1877 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1878 | "can't allocate rx ring (%d bytes)\n", size); | |
1879 | goto out; | |
1880 | } | |
1881 | memset(rxq->rx_desc_area, 0, size); | |
1da177e4 | 1882 | |
8a578111 LB |
1883 | rxq->rx_desc_area_size = size; |
1884 | rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), | |
1885 | GFP_KERNEL); | |
1886 | if (rxq->rx_skb == NULL) { | |
1887 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1888 | "can't allocate rx skb ring\n"); | |
1889 | goto out_free; | |
1890 | } | |
1891 | ||
1892 | rx_desc = (struct rx_desc *)rxq->rx_desc_area; | |
1893 | for (i = 0; i < rxq->rx_ring_size; i++) { | |
9da78745 LB |
1894 | int nexti; |
1895 | ||
1896 | nexti = i + 1; | |
1897 | if (nexti == rxq->rx_ring_size) | |
1898 | nexti = 0; | |
1899 | ||
8a578111 LB |
1900 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + |
1901 | nexti * sizeof(struct rx_desc); | |
1902 | } | |
1903 | ||
eaf5d590 LB |
1904 | rxq->lro_mgr.dev = mp->dev; |
1905 | memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats)); | |
1906 | rxq->lro_mgr.features = LRO_F_NAPI; | |
1907 | rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1908 | rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
1909 | rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr); | |
1910 | rxq->lro_mgr.max_aggr = 32; | |
1911 | rxq->lro_mgr.frag_align_pad = 0; | |
1912 | rxq->lro_mgr.lro_arr = rxq->lro_arr; | |
1913 | rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header; | |
1914 | ||
1915 | memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr)); | |
eaf5d590 | 1916 | |
8a578111 LB |
1917 | return 0; |
1918 | ||
1919 | ||
1920 | out_free: | |
f7981c1c | 1921 | if (index == 0 && size <= mp->rx_desc_sram_size) |
8a578111 LB |
1922 | iounmap(rxq->rx_desc_area); |
1923 | else | |
eb0519b5 | 1924 | dma_free_coherent(mp->dev->dev.parent, size, |
8a578111 LB |
1925 | rxq->rx_desc_area, |
1926 | rxq->rx_desc_dma); | |
1927 | ||
1928 | out: | |
1929 | return -ENOMEM; | |
c9df406f | 1930 | } |
c8aaea25 | 1931 | |
8a578111 | 1932 | static void rxq_deinit(struct rx_queue *rxq) |
c9df406f | 1933 | { |
8a578111 LB |
1934 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1935 | int i; | |
1936 | ||
1937 | rxq_disable(rxq); | |
c8aaea25 | 1938 | |
8a578111 LB |
1939 | for (i = 0; i < rxq->rx_ring_size; i++) { |
1940 | if (rxq->rx_skb[i]) { | |
1941 | dev_kfree_skb(rxq->rx_skb[i]); | |
1942 | rxq->rx_desc_count--; | |
1da177e4 | 1943 | } |
c8aaea25 | 1944 | } |
1da177e4 | 1945 | |
8a578111 LB |
1946 | if (rxq->rx_desc_count) { |
1947 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1948 | "error freeing rx ring -- %d skbs stuck\n", | |
1949 | rxq->rx_desc_count); | |
1950 | } | |
1951 | ||
f7981c1c | 1952 | if (rxq->index == 0 && |
64da80a2 | 1953 | rxq->rx_desc_area_size <= mp->rx_desc_sram_size) |
8a578111 | 1954 | iounmap(rxq->rx_desc_area); |
c9df406f | 1955 | else |
eb0519b5 | 1956 | dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, |
8a578111 LB |
1957 | rxq->rx_desc_area, rxq->rx_desc_dma); |
1958 | ||
1959 | kfree(rxq->rx_skb); | |
c9df406f | 1960 | } |
1da177e4 | 1961 | |
3d6b35bc | 1962 | static int txq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1963 | { |
3d6b35bc | 1964 | struct tx_queue *txq = mp->txq + index; |
13d64285 LB |
1965 | struct tx_desc *tx_desc; |
1966 | int size; | |
c9df406f | 1967 | int i; |
1da177e4 | 1968 | |
3d6b35bc LB |
1969 | txq->index = index; |
1970 | ||
e7d2f4db | 1971 | txq->tx_ring_size = mp->tx_ring_size; |
13d64285 LB |
1972 | |
1973 | txq->tx_desc_count = 0; | |
1974 | txq->tx_curr_desc = 0; | |
1975 | txq->tx_used_desc = 0; | |
1976 | ||
1977 | size = txq->tx_ring_size * sizeof(struct tx_desc); | |
1978 | ||
f7981c1c | 1979 | if (index == 0 && size <= mp->tx_desc_sram_size) { |
13d64285 LB |
1980 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, |
1981 | mp->tx_desc_sram_size); | |
1982 | txq->tx_desc_dma = mp->tx_desc_sram_addr; | |
1983 | } else { | |
eb0519b5 GP |
1984 | txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, |
1985 | size, &txq->tx_desc_dma, | |
1986 | GFP_KERNEL); | |
13d64285 LB |
1987 | } |
1988 | ||
1989 | if (txq->tx_desc_area == NULL) { | |
1990 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1991 | "can't allocate tx ring (%d bytes)\n", size); | |
99ab08e0 | 1992 | return -ENOMEM; |
c9df406f | 1993 | } |
13d64285 LB |
1994 | memset(txq->tx_desc_area, 0, size); |
1995 | ||
1996 | txq->tx_desc_area_size = size; | |
13d64285 LB |
1997 | |
1998 | tx_desc = (struct tx_desc *)txq->tx_desc_area; | |
1999 | for (i = 0; i < txq->tx_ring_size; i++) { | |
6b368f68 | 2000 | struct tx_desc *txd = tx_desc + i; |
9da78745 LB |
2001 | int nexti; |
2002 | ||
2003 | nexti = i + 1; | |
2004 | if (nexti == txq->tx_ring_size) | |
2005 | nexti = 0; | |
6b368f68 LB |
2006 | |
2007 | txd->cmd_sts = 0; | |
2008 | txd->next_desc_ptr = txq->tx_desc_dma + | |
13d64285 LB |
2009 | nexti * sizeof(struct tx_desc); |
2010 | } | |
2011 | ||
99ab08e0 | 2012 | skb_queue_head_init(&txq->tx_skb); |
c9df406f | 2013 | |
99ab08e0 | 2014 | return 0; |
c8aaea25 | 2015 | } |
1da177e4 | 2016 | |
13d64285 | 2017 | static void txq_deinit(struct tx_queue *txq) |
c9df406f | 2018 | { |
13d64285 | 2019 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
fa3959f4 | 2020 | |
13d64285 | 2021 | txq_disable(txq); |
1fa38c58 | 2022 | txq_reclaim(txq, txq->tx_ring_size, 1); |
1da177e4 | 2023 | |
13d64285 | 2024 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
1da177e4 | 2025 | |
f7981c1c | 2026 | if (txq->index == 0 && |
3d6b35bc | 2027 | txq->tx_desc_area_size <= mp->tx_desc_sram_size) |
13d64285 | 2028 | iounmap(txq->tx_desc_area); |
c9df406f | 2029 | else |
eb0519b5 | 2030 | dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, |
13d64285 | 2031 | txq->tx_desc_area, txq->tx_desc_dma); |
c9df406f | 2032 | } |
1da177e4 | 2033 | |
1da177e4 | 2034 | |
c9df406f | 2035 | /* netdev ops and related ***************************************************/ |
1fa38c58 LB |
2036 | static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) |
2037 | { | |
2038 | u32 int_cause; | |
2039 | u32 int_cause_ext; | |
2040 | ||
e0ca8410 | 2041 | int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask; |
1fa38c58 LB |
2042 | if (int_cause == 0) |
2043 | return 0; | |
2044 | ||
2045 | int_cause_ext = 0; | |
e0ca8410 SB |
2046 | if (int_cause & INT_EXT) { |
2047 | int_cause &= ~INT_EXT; | |
37a6084f | 2048 | int_cause_ext = rdlp(mp, INT_CAUSE_EXT); |
e0ca8410 | 2049 | } |
1fa38c58 | 2050 | |
1fa38c58 | 2051 | if (int_cause) { |
37a6084f | 2052 | wrlp(mp, INT_CAUSE, ~int_cause); |
1fa38c58 | 2053 | mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & |
37a6084f | 2054 | ~(rdlp(mp, TXQ_COMMAND) & 0xff); |
1fa38c58 LB |
2055 | mp->work_rx |= (int_cause & INT_RX) >> 2; |
2056 | } | |
2057 | ||
2058 | int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; | |
2059 | if (int_cause_ext) { | |
37a6084f | 2060 | wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); |
1fa38c58 LB |
2061 | if (int_cause_ext & INT_EXT_LINK_PHY) |
2062 | mp->work_link = 1; | |
2063 | mp->work_tx |= int_cause_ext & INT_EXT_TX; | |
2064 | } | |
2065 | ||
2066 | return 1; | |
2067 | } | |
2068 | ||
2069 | static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) | |
2070 | { | |
2071 | struct net_device *dev = (struct net_device *)dev_id; | |
2072 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
2073 | ||
2074 | if (unlikely(!mv643xx_eth_collect_events(mp))) | |
2075 | return IRQ_NONE; | |
2076 | ||
37a6084f | 2077 | wrlp(mp, INT_MASK, 0); |
1fa38c58 LB |
2078 | napi_schedule(&mp->napi); |
2079 | ||
2080 | return IRQ_HANDLED; | |
2081 | } | |
2082 | ||
2f7eb47a LB |
2083 | static void handle_link_event(struct mv643xx_eth_private *mp) |
2084 | { | |
2085 | struct net_device *dev = mp->dev; | |
2086 | u32 port_status; | |
2087 | int speed; | |
2088 | int duplex; | |
2089 | int fc; | |
2090 | ||
37a6084f | 2091 | port_status = rdlp(mp, PORT_STATUS); |
2f7eb47a LB |
2092 | if (!(port_status & LINK_UP)) { |
2093 | if (netif_carrier_ok(dev)) { | |
2094 | int i; | |
2095 | ||
2096 | printk(KERN_INFO "%s: link down\n", dev->name); | |
2097 | ||
2098 | netif_carrier_off(dev); | |
2f7eb47a | 2099 | |
f7981c1c | 2100 | for (i = 0; i < mp->txq_count; i++) { |
2f7eb47a LB |
2101 | struct tx_queue *txq = mp->txq + i; |
2102 | ||
1fa38c58 | 2103 | txq_reclaim(txq, txq->tx_ring_size, 1); |
f7981c1c | 2104 | txq_reset_hw_ptr(txq); |
2f7eb47a LB |
2105 | } |
2106 | } | |
2107 | return; | |
2108 | } | |
2109 | ||
2110 | switch (port_status & PORT_SPEED_MASK) { | |
2111 | case PORT_SPEED_10: | |
2112 | speed = 10; | |
2113 | break; | |
2114 | case PORT_SPEED_100: | |
2115 | speed = 100; | |
2116 | break; | |
2117 | case PORT_SPEED_1000: | |
2118 | speed = 1000; | |
2119 | break; | |
2120 | default: | |
2121 | speed = -1; | |
2122 | break; | |
2123 | } | |
2124 | duplex = (port_status & FULL_DUPLEX) ? 1 : 0; | |
2125 | fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; | |
2126 | ||
2127 | printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " | |
2128 | "flow control %sabled\n", dev->name, | |
2129 | speed, duplex ? "full" : "half", | |
2130 | fc ? "en" : "dis"); | |
2131 | ||
4fdeca3f | 2132 | if (!netif_carrier_ok(dev)) |
2f7eb47a | 2133 | netif_carrier_on(dev); |
2f7eb47a LB |
2134 | } |
2135 | ||
1fa38c58 | 2136 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
c9df406f | 2137 | { |
1fa38c58 LB |
2138 | struct mv643xx_eth_private *mp; |
2139 | int work_done; | |
ce4e2e45 | 2140 | |
1fa38c58 | 2141 | mp = container_of(napi, struct mv643xx_eth_private, napi); |
fc32b0e2 | 2142 | |
1319ebad LB |
2143 | if (unlikely(mp->oom)) { |
2144 | mp->oom = 0; | |
2145 | del_timer(&mp->rx_oom); | |
2146 | } | |
1da177e4 | 2147 | |
1fa38c58 LB |
2148 | work_done = 0; |
2149 | while (work_done < budget) { | |
2150 | u8 queue_mask; | |
2151 | int queue; | |
2152 | int work_tbd; | |
2153 | ||
2154 | if (mp->work_link) { | |
2155 | mp->work_link = 0; | |
2156 | handle_link_event(mp); | |
26ef1f17 | 2157 | work_done++; |
1fa38c58 LB |
2158 | continue; |
2159 | } | |
1da177e4 | 2160 | |
1319ebad LB |
2161 | queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; |
2162 | if (likely(!mp->oom)) | |
2163 | queue_mask |= mp->work_rx_refill; | |
2164 | ||
1fa38c58 LB |
2165 | if (!queue_mask) { |
2166 | if (mv643xx_eth_collect_events(mp)) | |
2167 | continue; | |
2168 | break; | |
2169 | } | |
1da177e4 | 2170 | |
1fa38c58 LB |
2171 | queue = fls(queue_mask) - 1; |
2172 | queue_mask = 1 << queue; | |
2173 | ||
2174 | work_tbd = budget - work_done; | |
2175 | if (work_tbd > 16) | |
2176 | work_tbd = 16; | |
2177 | ||
2178 | if (mp->work_tx_end & queue_mask) { | |
2179 | txq_kick(mp->txq + queue); | |
2180 | } else if (mp->work_tx & queue_mask) { | |
2181 | work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); | |
2182 | txq_maybe_wake(mp->txq + queue); | |
2183 | } else if (mp->work_rx & queue_mask) { | |
2184 | work_done += rxq_process(mp->rxq + queue, work_tbd); | |
1319ebad | 2185 | } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { |
1fa38c58 LB |
2186 | work_done += rxq_refill(mp->rxq + queue, work_tbd); |
2187 | } else { | |
2188 | BUG(); | |
2189 | } | |
84dd619e | 2190 | } |
fc32b0e2 | 2191 | |
1fa38c58 | 2192 | if (work_done < budget) { |
1319ebad | 2193 | if (mp->oom) |
1fa38c58 LB |
2194 | mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); |
2195 | napi_complete(napi); | |
e0ca8410 | 2196 | wrlp(mp, INT_MASK, mp->int_mask); |
226bb6b7 | 2197 | } |
3d6b35bc | 2198 | |
1fa38c58 LB |
2199 | return work_done; |
2200 | } | |
8fa89bf5 | 2201 | |
1fa38c58 LB |
2202 | static inline void oom_timer_wrapper(unsigned long data) |
2203 | { | |
2204 | struct mv643xx_eth_private *mp = (void *)data; | |
1da177e4 | 2205 | |
1fa38c58 | 2206 | napi_schedule(&mp->napi); |
1da177e4 LT |
2207 | } |
2208 | ||
e5371493 | 2209 | static void phy_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2210 | { |
45c5d3bc LB |
2211 | int data; |
2212 | ||
ed94493f | 2213 | data = phy_read(mp->phy, MII_BMCR); |
45c5d3bc LB |
2214 | if (data < 0) |
2215 | return; | |
1da177e4 | 2216 | |
7f106c1d | 2217 | data |= BMCR_RESET; |
ed94493f | 2218 | if (phy_write(mp->phy, MII_BMCR, data) < 0) |
45c5d3bc | 2219 | return; |
1da177e4 | 2220 | |
c9df406f | 2221 | do { |
ed94493f | 2222 | data = phy_read(mp->phy, MII_BMCR); |
45c5d3bc | 2223 | } while (data >= 0 && data & BMCR_RESET); |
1da177e4 LT |
2224 | } |
2225 | ||
fc32b0e2 | 2226 | static void port_start(struct mv643xx_eth_private *mp) |
1da177e4 | 2227 | { |
d0412d96 | 2228 | u32 pscr; |
8a578111 | 2229 | int i; |
1da177e4 | 2230 | |
bedfe324 LB |
2231 | /* |
2232 | * Perform PHY reset, if there is a PHY. | |
2233 | */ | |
ed94493f | 2234 | if (mp->phy != NULL) { |
bedfe324 LB |
2235 | struct ethtool_cmd cmd; |
2236 | ||
2237 | mv643xx_eth_get_settings(mp->dev, &cmd); | |
2238 | phy_reset(mp); | |
2239 | mv643xx_eth_set_settings(mp->dev, &cmd); | |
2240 | } | |
1da177e4 | 2241 | |
81600eea LB |
2242 | /* |
2243 | * Configure basic link parameters. | |
2244 | */ | |
37a6084f | 2245 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2246 | |
2247 | pscr |= SERIAL_PORT_ENABLE; | |
37a6084f | 2248 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2249 | |
2250 | pscr |= DO_NOT_FORCE_LINK_FAIL; | |
ed94493f | 2251 | if (mp->phy == NULL) |
81600eea | 2252 | pscr |= FORCE_LINK_PASS; |
37a6084f | 2253 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea | 2254 | |
13d64285 LB |
2255 | /* |
2256 | * Configure TX path and queues. | |
2257 | */ | |
89df5fdc | 2258 | tx_set_rate(mp, 1000000000, 16777216); |
f7981c1c | 2259 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc | 2260 | struct tx_queue *txq = mp->txq + i; |
13d64285 | 2261 | |
6b368f68 | 2262 | txq_reset_hw_ptr(txq); |
89df5fdc LB |
2263 | txq_set_rate(txq, 1000000000, 16777216); |
2264 | txq_set_fixed_prio_mode(txq); | |
13d64285 LB |
2265 | } |
2266 | ||
d9a073ea LB |
2267 | /* |
2268 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
170e7108 LB |
2269 | * frames to RX queue #0, and include the pseudo-header when |
2270 | * calculating receive checksums. | |
d9a073ea | 2271 | */ |
37a6084f | 2272 | wrlp(mp, PORT_CONFIG, 0x02000000); |
01999873 | 2273 | |
376489a2 LB |
2274 | /* |
2275 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
2276 | */ | |
37a6084f | 2277 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); |
01999873 | 2278 | |
5a893922 LB |
2279 | /* |
2280 | * Add configured unicast addresses to address filter table. | |
2281 | */ | |
2282 | mv643xx_eth_program_unicast_filter(mp->dev); | |
2283 | ||
8a578111 | 2284 | /* |
64da80a2 | 2285 | * Enable the receive queues. |
8a578111 | 2286 | */ |
f7981c1c | 2287 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 | 2288 | struct rx_queue *rxq = mp->rxq + i; |
8a578111 | 2289 | u32 addr; |
1da177e4 | 2290 | |
8a578111 LB |
2291 | addr = (u32)rxq->rx_desc_dma; |
2292 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); | |
37a6084f | 2293 | wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); |
1da177e4 | 2294 | |
8a578111 LB |
2295 | rxq_enable(rxq); |
2296 | } | |
1da177e4 LT |
2297 | } |
2298 | ||
2bcb4b0f LB |
2299 | static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) |
2300 | { | |
2301 | int skb_size; | |
2302 | ||
2303 | /* | |
2304 | * Reserve 2+14 bytes for an ethernet header (the hardware | |
2305 | * automatically prepends 2 bytes of dummy data to each | |
2306 | * received packet), 16 bytes for up to four VLAN tags, and | |
2307 | * 4 bytes for the trailing FCS -- 36 bytes total. | |
2308 | */ | |
2309 | skb_size = mp->dev->mtu + 36; | |
2310 | ||
2311 | /* | |
2312 | * Make sure that the skb size is a multiple of 8 bytes, as | |
2313 | * the lower three bits of the receive descriptor's buffer | |
2314 | * size field are ignored by the hardware. | |
2315 | */ | |
2316 | mp->skb_size = (skb_size + 7) & ~7; | |
7fd96ce4 LB |
2317 | |
2318 | /* | |
2319 | * If NET_SKB_PAD is smaller than a cache line, | |
2320 | * netdev_alloc_skb() will cause skb->data to be misaligned | |
2321 | * to a cache line boundary. If this is the case, include | |
2322 | * some extra space to allow re-aligning the data area. | |
2323 | */ | |
2324 | mp->skb_size += SKB_DMA_REALIGN; | |
2bcb4b0f LB |
2325 | } |
2326 | ||
c9df406f | 2327 | static int mv643xx_eth_open(struct net_device *dev) |
16e03018 | 2328 | { |
e5371493 | 2329 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2330 | int err; |
64da80a2 | 2331 | int i; |
16e03018 | 2332 | |
37a6084f LB |
2333 | wrlp(mp, INT_CAUSE, 0); |
2334 | wrlp(mp, INT_CAUSE_EXT, 0); | |
2335 | rdlp(mp, INT_CAUSE_EXT); | |
c9df406f | 2336 | |
fc32b0e2 | 2337 | err = request_irq(dev->irq, mv643xx_eth_irq, |
2a1867a7 | 2338 | IRQF_SHARED, dev->name, dev); |
c9df406f | 2339 | if (err) { |
fc32b0e2 | 2340 | dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); |
c9df406f | 2341 | return -EAGAIN; |
16e03018 DF |
2342 | } |
2343 | ||
2bcb4b0f LB |
2344 | mv643xx_eth_recalc_skb_size(mp); |
2345 | ||
2257e05c LB |
2346 | napi_enable(&mp->napi); |
2347 | ||
2bcb4b0f LB |
2348 | skb_queue_head_init(&mp->rx_recycle); |
2349 | ||
e0ca8410 SB |
2350 | mp->int_mask = INT_EXT; |
2351 | ||
f7981c1c | 2352 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 LB |
2353 | err = rxq_init(mp, i); |
2354 | if (err) { | |
2355 | while (--i >= 0) | |
f7981c1c | 2356 | rxq_deinit(mp->rxq + i); |
64da80a2 LB |
2357 | goto out; |
2358 | } | |
2359 | ||
1fa38c58 | 2360 | rxq_refill(mp->rxq + i, INT_MAX); |
e0ca8410 | 2361 | mp->int_mask |= INT_RX_0 << i; |
2257e05c LB |
2362 | } |
2363 | ||
1319ebad | 2364 | if (mp->oom) { |
2257e05c LB |
2365 | mp->rx_oom.expires = jiffies + (HZ / 10); |
2366 | add_timer(&mp->rx_oom); | |
64da80a2 | 2367 | } |
8a578111 | 2368 | |
f7981c1c | 2369 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc LB |
2370 | err = txq_init(mp, i); |
2371 | if (err) { | |
2372 | while (--i >= 0) | |
f7981c1c | 2373 | txq_deinit(mp->txq + i); |
3d6b35bc LB |
2374 | goto out_free; |
2375 | } | |
e0ca8410 | 2376 | mp->int_mask |= INT_TX_END_0 << i; |
3d6b35bc | 2377 | } |
16e03018 | 2378 | |
fc32b0e2 | 2379 | port_start(mp); |
16e03018 | 2380 | |
37a6084f | 2381 | wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); |
e0ca8410 | 2382 | wrlp(mp, INT_MASK, mp->int_mask); |
16e03018 | 2383 | |
c9df406f LB |
2384 | return 0; |
2385 | ||
13d64285 | 2386 | |
fc32b0e2 | 2387 | out_free: |
f7981c1c LB |
2388 | for (i = 0; i < mp->rxq_count; i++) |
2389 | rxq_deinit(mp->rxq + i); | |
fc32b0e2 | 2390 | out: |
c9df406f LB |
2391 | free_irq(dev->irq, dev); |
2392 | ||
2393 | return err; | |
16e03018 DF |
2394 | } |
2395 | ||
e5371493 | 2396 | static void port_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2397 | { |
fc32b0e2 | 2398 | unsigned int data; |
64da80a2 | 2399 | int i; |
1da177e4 | 2400 | |
f7981c1c LB |
2401 | for (i = 0; i < mp->rxq_count; i++) |
2402 | rxq_disable(mp->rxq + i); | |
2403 | for (i = 0; i < mp->txq_count; i++) | |
2404 | txq_disable(mp->txq + i); | |
ae9ae064 LB |
2405 | |
2406 | while (1) { | |
37a6084f | 2407 | u32 ps = rdlp(mp, PORT_STATUS); |
ae9ae064 LB |
2408 | |
2409 | if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) | |
2410 | break; | |
13d64285 | 2411 | udelay(10); |
ae9ae064 | 2412 | } |
1da177e4 | 2413 | |
c9df406f | 2414 | /* Reset the Enable bit in the Configuration Register */ |
37a6084f | 2415 | data = rdlp(mp, PORT_SERIAL_CONTROL); |
fc32b0e2 LB |
2416 | data &= ~(SERIAL_PORT_ENABLE | |
2417 | DO_NOT_FORCE_LINK_FAIL | | |
2418 | FORCE_LINK_PASS); | |
37a6084f | 2419 | wrlp(mp, PORT_SERIAL_CONTROL, data); |
1da177e4 LT |
2420 | } |
2421 | ||
c9df406f | 2422 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 | 2423 | { |
e5371493 | 2424 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
64da80a2 | 2425 | int i; |
1da177e4 | 2426 | |
fe65e704 | 2427 | wrlp(mp, INT_MASK_EXT, 0x00000000); |
37a6084f LB |
2428 | wrlp(mp, INT_MASK, 0x00000000); |
2429 | rdlp(mp, INT_MASK); | |
1da177e4 | 2430 | |
c9df406f | 2431 | napi_disable(&mp->napi); |
78fff83b | 2432 | |
2257e05c LB |
2433 | del_timer_sync(&mp->rx_oom); |
2434 | ||
c9df406f | 2435 | netif_carrier_off(dev); |
1da177e4 | 2436 | |
fc32b0e2 LB |
2437 | free_irq(dev->irq, dev); |
2438 | ||
cc9754b3 | 2439 | port_reset(mp); |
8fd89211 | 2440 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 2441 | mib_counters_update(mp); |
57e8f26a | 2442 | del_timer_sync(&mp->mib_counters_timer); |
1da177e4 | 2443 | |
2bcb4b0f LB |
2444 | skb_queue_purge(&mp->rx_recycle); |
2445 | ||
f7981c1c LB |
2446 | for (i = 0; i < mp->rxq_count; i++) |
2447 | rxq_deinit(mp->rxq + i); | |
2448 | for (i = 0; i < mp->txq_count; i++) | |
2449 | txq_deinit(mp->txq + i); | |
1da177e4 | 2450 | |
c9df406f | 2451 | return 0; |
1da177e4 LT |
2452 | } |
2453 | ||
fc32b0e2 | 2454 | static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2455 | { |
e5371493 | 2456 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2457 | |
ed94493f | 2458 | if (mp->phy != NULL) |
28b04113 | 2459 | return phy_mii_ioctl(mp->phy, ifr, cmd); |
bedfe324 LB |
2460 | |
2461 | return -EOPNOTSUPP; | |
1da177e4 LT |
2462 | } |
2463 | ||
c9df406f | 2464 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2465 | { |
89df5fdc LB |
2466 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
2467 | ||
fc32b0e2 | 2468 | if (new_mtu < 64 || new_mtu > 9500) |
c9df406f | 2469 | return -EINVAL; |
1da177e4 | 2470 | |
c9df406f | 2471 | dev->mtu = new_mtu; |
2bcb4b0f | 2472 | mv643xx_eth_recalc_skb_size(mp); |
89df5fdc LB |
2473 | tx_set_rate(mp, 1000000000, 16777216); |
2474 | ||
c9df406f LB |
2475 | if (!netif_running(dev)) |
2476 | return 0; | |
1da177e4 | 2477 | |
c9df406f LB |
2478 | /* |
2479 | * Stop and then re-open the interface. This will allocate RX | |
2480 | * skbs of the new MTU. | |
2481 | * There is a possible danger that the open will not succeed, | |
fc32b0e2 | 2482 | * due to memory being full. |
c9df406f LB |
2483 | */ |
2484 | mv643xx_eth_stop(dev); | |
2485 | if (mv643xx_eth_open(dev)) { | |
fc32b0e2 LB |
2486 | dev_printk(KERN_ERR, &dev->dev, |
2487 | "fatal error on re-opening device after " | |
2488 | "MTU change\n"); | |
c9df406f LB |
2489 | } |
2490 | ||
2491 | return 0; | |
1da177e4 LT |
2492 | } |
2493 | ||
fc32b0e2 | 2494 | static void tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2495 | { |
fc32b0e2 | 2496 | struct mv643xx_eth_private *mp; |
1da177e4 | 2497 | |
fc32b0e2 LB |
2498 | mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); |
2499 | if (netif_running(mp->dev)) { | |
e5ef1de1 | 2500 | netif_tx_stop_all_queues(mp->dev); |
fc32b0e2 LB |
2501 | port_reset(mp); |
2502 | port_start(mp); | |
e5ef1de1 | 2503 | netif_tx_wake_all_queues(mp->dev); |
fc32b0e2 | 2504 | } |
c9df406f LB |
2505 | } |
2506 | ||
c9df406f | 2507 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2508 | { |
e5371493 | 2509 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2510 | |
fc32b0e2 | 2511 | dev_printk(KERN_INFO, &dev->dev, "tx timeout\n"); |
d0412d96 | 2512 | |
c9df406f | 2513 | schedule_work(&mp->tx_timeout_task); |
1da177e4 LT |
2514 | } |
2515 | ||
c9df406f | 2516 | #ifdef CONFIG_NET_POLL_CONTROLLER |
fc32b0e2 | 2517 | static void mv643xx_eth_netpoll(struct net_device *dev) |
9f8dd319 | 2518 | { |
fc32b0e2 | 2519 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2520 | |
37a6084f LB |
2521 | wrlp(mp, INT_MASK, 0x00000000); |
2522 | rdlp(mp, INT_MASK); | |
c9df406f | 2523 | |
fc32b0e2 | 2524 | mv643xx_eth_irq(dev->irq, dev); |
c9df406f | 2525 | |
e0ca8410 | 2526 | wrlp(mp, INT_MASK, mp->int_mask); |
9f8dd319 | 2527 | } |
c9df406f | 2528 | #endif |
9f8dd319 | 2529 | |
9f8dd319 | 2530 | |
c9df406f | 2531 | /* platform glue ************************************************************/ |
e5371493 LB |
2532 | static void |
2533 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, | |
2534 | struct mbus_dram_target_info *dram) | |
c9df406f | 2535 | { |
cc9754b3 | 2536 | void __iomem *base = msp->base; |
c9df406f LB |
2537 | u32 win_enable; |
2538 | u32 win_protect; | |
2539 | int i; | |
9f8dd319 | 2540 | |
c9df406f LB |
2541 | for (i = 0; i < 6; i++) { |
2542 | writel(0, base + WINDOW_BASE(i)); | |
2543 | writel(0, base + WINDOW_SIZE(i)); | |
2544 | if (i < 4) | |
2545 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2546 | } |
2547 | ||
c9df406f LB |
2548 | win_enable = 0x3f; |
2549 | win_protect = 0; | |
2550 | ||
2551 | for (i = 0; i < dram->num_cs; i++) { | |
2552 | struct mbus_dram_window *cs = dram->cs + i; | |
2553 | ||
2554 | writel((cs->base & 0xffff0000) | | |
2555 | (cs->mbus_attr << 8) | | |
2556 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2557 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2558 | ||
2559 | win_enable &= ~(1 << i); | |
2560 | win_protect |= 3 << (2 * i); | |
2561 | } | |
2562 | ||
2563 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2564 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2565 | } |
2566 | ||
773fc3ee LB |
2567 | static void infer_hw_params(struct mv643xx_eth_shared_private *msp) |
2568 | { | |
2569 | /* | |
2570 | * Check whether we have a 14-bit coal limit field in bits | |
2571 | * [21:8], or a 16-bit coal limit in bits [25,21:7] of the | |
2572 | * SDMA config register. | |
2573 | */ | |
37a6084f LB |
2574 | writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); |
2575 | if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) | |
773fc3ee LB |
2576 | msp->extended_rx_coal_limit = 1; |
2577 | else | |
2578 | msp->extended_rx_coal_limit = 0; | |
1e881592 LB |
2579 | |
2580 | /* | |
457b1d5a LB |
2581 | * Check whether the MAC supports TX rate control, and if |
2582 | * yes, whether its associated registers are in the old or | |
2583 | * the new place. | |
1e881592 | 2584 | */ |
37a6084f LB |
2585 | writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); |
2586 | if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { | |
457b1d5a LB |
2587 | msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; |
2588 | } else { | |
37a6084f LB |
2589 | writel(7, msp->base + 0x0400 + TX_BW_RATE); |
2590 | if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) | |
457b1d5a LB |
2591 | msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; |
2592 | else | |
2593 | msp->tx_bw_control = TX_BW_CONTROL_ABSENT; | |
2594 | } | |
773fc3ee LB |
2595 | } |
2596 | ||
c9df406f | 2597 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2598 | { |
10a9948d | 2599 | static int mv643xx_eth_version_printed; |
c9df406f | 2600 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
e5371493 | 2601 | struct mv643xx_eth_shared_private *msp; |
c9df406f LB |
2602 | struct resource *res; |
2603 | int ret; | |
9f8dd319 | 2604 | |
e5371493 | 2605 | if (!mv643xx_eth_version_printed++) |
7dde154d LB |
2606 | printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet " |
2607 | "driver version %s\n", mv643xx_eth_driver_version); | |
9f8dd319 | 2608 | |
c9df406f LB |
2609 | ret = -EINVAL; |
2610 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2611 | if (res == NULL) | |
2612 | goto out; | |
9f8dd319 | 2613 | |
c9df406f | 2614 | ret = -ENOMEM; |
beae22e6 | 2615 | msp = kzalloc(sizeof(*msp), GFP_KERNEL); |
c9df406f LB |
2616 | if (msp == NULL) |
2617 | goto out; | |
c9df406f | 2618 | |
cc9754b3 LB |
2619 | msp->base = ioremap(res->start, res->end - res->start + 1); |
2620 | if (msp->base == NULL) | |
c9df406f LB |
2621 | goto out_free; |
2622 | ||
ed94493f LB |
2623 | /* |
2624 | * Set up and register SMI bus. | |
2625 | */ | |
2626 | if (pd == NULL || pd->shared_smi == NULL) { | |
298cf9be LB |
2627 | msp->smi_bus = mdiobus_alloc(); |
2628 | if (msp->smi_bus == NULL) | |
ed94493f | 2629 | goto out_unmap; |
298cf9be LB |
2630 | |
2631 | msp->smi_bus->priv = msp; | |
2632 | msp->smi_bus->name = "mv643xx_eth smi"; | |
2633 | msp->smi_bus->read = smi_bus_read; | |
2634 | msp->smi_bus->write = smi_bus_write, | |
2635 | snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); | |
2636 | msp->smi_bus->parent = &pdev->dev; | |
2637 | msp->smi_bus->phy_mask = 0xffffffff; | |
2638 | if (mdiobus_register(msp->smi_bus) < 0) | |
2639 | goto out_free_mii_bus; | |
ed94493f LB |
2640 | msp->smi = msp; |
2641 | } else { | |
fc0eb9f2 | 2642 | msp->smi = platform_get_drvdata(pd->shared_smi); |
ed94493f | 2643 | } |
c9df406f | 2644 | |
45c5d3bc LB |
2645 | msp->err_interrupt = NO_IRQ; |
2646 | init_waitqueue_head(&msp->smi_busy_wait); | |
2647 | ||
2648 | /* | |
2649 | * Check whether the error interrupt is hooked up. | |
2650 | */ | |
2651 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
2652 | if (res != NULL) { | |
2653 | int err; | |
2654 | ||
2655 | err = request_irq(res->start, mv643xx_eth_err_irq, | |
2656 | IRQF_SHARED, "mv643xx_eth", msp); | |
2657 | if (!err) { | |
2658 | writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK); | |
2659 | msp->err_interrupt = res->start; | |
2660 | } | |
2661 | } | |
2662 | ||
c9df406f LB |
2663 | /* |
2664 | * (Re-)program MBUS remapping windows if we are asked to. | |
2665 | */ | |
2666 | if (pd != NULL && pd->dram != NULL) | |
2667 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2668 | ||
fc32b0e2 LB |
2669 | /* |
2670 | * Detect hardware parameters. | |
2671 | */ | |
2672 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
50a749c1 DC |
2673 | msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ? |
2674 | pd->tx_csum_limit : 9 * 1024; | |
773fc3ee | 2675 | infer_hw_params(msp); |
fc32b0e2 LB |
2676 | |
2677 | platform_set_drvdata(pdev, msp); | |
2678 | ||
c9df406f LB |
2679 | return 0; |
2680 | ||
298cf9be LB |
2681 | out_free_mii_bus: |
2682 | mdiobus_free(msp->smi_bus); | |
ed94493f LB |
2683 | out_unmap: |
2684 | iounmap(msp->base); | |
c9df406f LB |
2685 | out_free: |
2686 | kfree(msp); | |
2687 | out: | |
2688 | return ret; | |
2689 | } | |
2690 | ||
2691 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2692 | { | |
e5371493 | 2693 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
ed94493f | 2694 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
c9df406f | 2695 | |
298cf9be | 2696 | if (pd == NULL || pd->shared_smi == NULL) { |
298cf9be | 2697 | mdiobus_unregister(msp->smi_bus); |
bcb3336c | 2698 | mdiobus_free(msp->smi_bus); |
298cf9be | 2699 | } |
45c5d3bc LB |
2700 | if (msp->err_interrupt != NO_IRQ) |
2701 | free_irq(msp->err_interrupt, msp); | |
cc9754b3 | 2702 | iounmap(msp->base); |
c9df406f LB |
2703 | kfree(msp); |
2704 | ||
2705 | return 0; | |
9f8dd319 DF |
2706 | } |
2707 | ||
c9df406f | 2708 | static struct platform_driver mv643xx_eth_shared_driver = { |
fc32b0e2 LB |
2709 | .probe = mv643xx_eth_shared_probe, |
2710 | .remove = mv643xx_eth_shared_remove, | |
c9df406f | 2711 | .driver = { |
fc32b0e2 | 2712 | .name = MV643XX_ETH_SHARED_NAME, |
c9df406f LB |
2713 | .owner = THIS_MODULE, |
2714 | }, | |
2715 | }; | |
2716 | ||
e5371493 | 2717 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
1da177e4 | 2718 | { |
c9df406f | 2719 | int addr_shift = 5 * mp->port_num; |
fc32b0e2 | 2720 | u32 data; |
1da177e4 | 2721 | |
fc32b0e2 LB |
2722 | data = rdl(mp, PHY_ADDR); |
2723 | data &= ~(0x1f << addr_shift); | |
2724 | data |= (phy_addr & 0x1f) << addr_shift; | |
2725 | wrl(mp, PHY_ADDR, data); | |
1da177e4 LT |
2726 | } |
2727 | ||
e5371493 | 2728 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
1da177e4 | 2729 | { |
fc32b0e2 LB |
2730 | unsigned int data; |
2731 | ||
2732 | data = rdl(mp, PHY_ADDR); | |
2733 | ||
2734 | return (data >> (5 * mp->port_num)) & 0x1f; | |
2735 | } | |
2736 | ||
2737 | static void set_params(struct mv643xx_eth_private *mp, | |
2738 | struct mv643xx_eth_platform_data *pd) | |
2739 | { | |
2740 | struct net_device *dev = mp->dev; | |
2741 | ||
2742 | if (is_valid_ether_addr(pd->mac_addr)) | |
2743 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2744 | else | |
2745 | uc_addr_get(mp, dev->dev_addr); | |
2746 | ||
e7d2f4db | 2747 | mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
fc32b0e2 | 2748 | if (pd->rx_queue_size) |
e7d2f4db | 2749 | mp->rx_ring_size = pd->rx_queue_size; |
fc32b0e2 LB |
2750 | mp->rx_desc_sram_addr = pd->rx_sram_addr; |
2751 | mp->rx_desc_sram_size = pd->rx_sram_size; | |
1da177e4 | 2752 | |
f7981c1c | 2753 | mp->rxq_count = pd->rx_queue_count ? : 1; |
64da80a2 | 2754 | |
e7d2f4db | 2755 | mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
fc32b0e2 | 2756 | if (pd->tx_queue_size) |
e7d2f4db | 2757 | mp->tx_ring_size = pd->tx_queue_size; |
fc32b0e2 LB |
2758 | mp->tx_desc_sram_addr = pd->tx_sram_addr; |
2759 | mp->tx_desc_sram_size = pd->tx_sram_size; | |
3d6b35bc | 2760 | |
f7981c1c | 2761 | mp->txq_count = pd->tx_queue_count ? : 1; |
1da177e4 LT |
2762 | } |
2763 | ||
ed94493f LB |
2764 | static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, |
2765 | int phy_addr) | |
1da177e4 | 2766 | { |
298cf9be | 2767 | struct mii_bus *bus = mp->shared->smi->smi_bus; |
ed94493f LB |
2768 | struct phy_device *phydev; |
2769 | int start; | |
2770 | int num; | |
2771 | int i; | |
45c5d3bc | 2772 | |
ed94493f LB |
2773 | if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { |
2774 | start = phy_addr_get(mp) & 0x1f; | |
2775 | num = 32; | |
2776 | } else { | |
2777 | start = phy_addr & 0x1f; | |
2778 | num = 1; | |
2779 | } | |
45c5d3bc | 2780 | |
ed94493f LB |
2781 | phydev = NULL; |
2782 | for (i = 0; i < num; i++) { | |
2783 | int addr = (start + i) & 0x1f; | |
fc32b0e2 | 2784 | |
ed94493f LB |
2785 | if (bus->phy_map[addr] == NULL) |
2786 | mdiobus_scan(bus, addr); | |
1da177e4 | 2787 | |
ed94493f LB |
2788 | if (phydev == NULL) { |
2789 | phydev = bus->phy_map[addr]; | |
2790 | if (phydev != NULL) | |
2791 | phy_addr_set(mp, addr); | |
2792 | } | |
2793 | } | |
1da177e4 | 2794 | |
ed94493f | 2795 | return phydev; |
1da177e4 LT |
2796 | } |
2797 | ||
ed94493f | 2798 | static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) |
c28a4f89 | 2799 | { |
ed94493f | 2800 | struct phy_device *phy = mp->phy; |
c28a4f89 | 2801 | |
fc32b0e2 LB |
2802 | phy_reset(mp); |
2803 | ||
db1d7bf7 | 2804 | phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII); |
ed94493f LB |
2805 | |
2806 | if (speed == 0) { | |
2807 | phy->autoneg = AUTONEG_ENABLE; | |
2808 | phy->speed = 0; | |
2809 | phy->duplex = 0; | |
2810 | phy->advertising = phy->supported | ADVERTISED_Autoneg; | |
c9df406f | 2811 | } else { |
ed94493f LB |
2812 | phy->autoneg = AUTONEG_DISABLE; |
2813 | phy->advertising = 0; | |
2814 | phy->speed = speed; | |
2815 | phy->duplex = duplex; | |
c9df406f | 2816 | } |
ed94493f | 2817 | phy_start_aneg(phy); |
c28a4f89 JC |
2818 | } |
2819 | ||
81600eea LB |
2820 | static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) |
2821 | { | |
2822 | u32 pscr; | |
2823 | ||
37a6084f | 2824 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2825 | if (pscr & SERIAL_PORT_ENABLE) { |
2826 | pscr &= ~SERIAL_PORT_ENABLE; | |
37a6084f | 2827 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2828 | } |
2829 | ||
2830 | pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; | |
ed94493f | 2831 | if (mp->phy == NULL) { |
81600eea LB |
2832 | pscr |= DISABLE_AUTO_NEG_SPEED_GMII; |
2833 | if (speed == SPEED_1000) | |
2834 | pscr |= SET_GMII_SPEED_TO_1000; | |
2835 | else if (speed == SPEED_100) | |
2836 | pscr |= SET_MII_SPEED_TO_100; | |
2837 | ||
2838 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; | |
2839 | ||
2840 | pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; | |
2841 | if (duplex == DUPLEX_FULL) | |
2842 | pscr |= SET_FULL_DUPLEX_MODE; | |
2843 | } | |
2844 | ||
37a6084f | 2845 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2846 | } |
2847 | ||
ea8a8642 LB |
2848 | static const struct net_device_ops mv643xx_eth_netdev_ops = { |
2849 | .ndo_open = mv643xx_eth_open, | |
2850 | .ndo_stop = mv643xx_eth_stop, | |
2851 | .ndo_start_xmit = mv643xx_eth_xmit, | |
2852 | .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, | |
2853 | .ndo_set_mac_address = mv643xx_eth_set_mac_address, | |
1d4bd947 | 2854 | .ndo_validate_addr = eth_validate_addr, |
ea8a8642 LB |
2855 | .ndo_do_ioctl = mv643xx_eth_ioctl, |
2856 | .ndo_change_mtu = mv643xx_eth_change_mtu, | |
2857 | .ndo_tx_timeout = mv643xx_eth_tx_timeout, | |
2858 | .ndo_get_stats = mv643xx_eth_get_stats, | |
2859 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2860 | .ndo_poll_controller = mv643xx_eth_netpoll, | |
2861 | #endif | |
2862 | }; | |
2863 | ||
c9df406f | 2864 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2865 | { |
c9df406f | 2866 | struct mv643xx_eth_platform_data *pd; |
e5371493 | 2867 | struct mv643xx_eth_private *mp; |
c9df406f | 2868 | struct net_device *dev; |
c9df406f | 2869 | struct resource *res; |
fc32b0e2 | 2870 | int err; |
1da177e4 | 2871 | |
c9df406f LB |
2872 | pd = pdev->dev.platform_data; |
2873 | if (pd == NULL) { | |
fc32b0e2 LB |
2874 | dev_printk(KERN_ERR, &pdev->dev, |
2875 | "no mv643xx_eth_platform_data\n"); | |
c9df406f LB |
2876 | return -ENODEV; |
2877 | } | |
1da177e4 | 2878 | |
c9df406f | 2879 | if (pd->shared == NULL) { |
fc32b0e2 LB |
2880 | dev_printk(KERN_ERR, &pdev->dev, |
2881 | "no mv643xx_eth_platform_data->shared\n"); | |
c9df406f LB |
2882 | return -ENODEV; |
2883 | } | |
8f518703 | 2884 | |
e5ef1de1 | 2885 | dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); |
c9df406f LB |
2886 | if (!dev) |
2887 | return -ENOMEM; | |
1da177e4 | 2888 | |
c9df406f | 2889 | mp = netdev_priv(dev); |
fc32b0e2 LB |
2890 | platform_set_drvdata(pdev, mp); |
2891 | ||
2892 | mp->shared = platform_get_drvdata(pd->shared); | |
37a6084f | 2893 | mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); |
fc32b0e2 LB |
2894 | mp->port_num = pd->port_number; |
2895 | ||
c9df406f | 2896 | mp->dev = dev; |
78fff83b | 2897 | |
fc32b0e2 | 2898 | set_params(mp, pd); |
206d6b32 BH |
2899 | netif_set_real_num_tx_queues(dev, mp->txq_count); |
2900 | netif_set_real_num_rx_queues(dev, mp->rxq_count); | |
fc32b0e2 | 2901 | |
ed94493f LB |
2902 | if (pd->phy_addr != MV643XX_ETH_PHY_NONE) |
2903 | mp->phy = phy_scan(mp, pd->phy_addr); | |
bedfe324 | 2904 | |
6bdf576e | 2905 | if (mp->phy != NULL) |
ed94493f | 2906 | phy_init(mp, pd->speed, pd->duplex); |
6bdf576e LB |
2907 | |
2908 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); | |
ed94493f | 2909 | |
81600eea | 2910 | init_pscr(mp, pd->speed, pd->duplex); |
fc32b0e2 | 2911 | |
4ff3495a LB |
2912 | |
2913 | mib_counters_clear(mp); | |
2914 | ||
2915 | init_timer(&mp->mib_counters_timer); | |
2916 | mp->mib_counters_timer.data = (unsigned long)mp; | |
2917 | mp->mib_counters_timer.function = mib_counters_timer_wrapper; | |
2918 | mp->mib_counters_timer.expires = jiffies + 30 * HZ; | |
2919 | add_timer(&mp->mib_counters_timer); | |
2920 | ||
2921 | spin_lock_init(&mp->mib_counters_lock); | |
2922 | ||
2923 | INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); | |
2924 | ||
2257e05c LB |
2925 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128); |
2926 | ||
2927 | init_timer(&mp->rx_oom); | |
2928 | mp->rx_oom.data = (unsigned long)mp; | |
2929 | mp->rx_oom.function = oom_timer_wrapper; | |
2930 | ||
fc32b0e2 | 2931 | |
c9df406f LB |
2932 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2933 | BUG_ON(!res); | |
2934 | dev->irq = res->start; | |
1da177e4 | 2935 | |
ea8a8642 LB |
2936 | dev->netdev_ops = &mv643xx_eth_netdev_ops; |
2937 | ||
c9df406f LB |
2938 | dev->watchdog_timeo = 2 * HZ; |
2939 | dev->base_addr = 0; | |
1da177e4 | 2940 | |
c9df406f | 2941 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
e32b6617 | 2942 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 | 2943 | |
fc32b0e2 | 2944 | SET_NETDEV_DEV(dev, &pdev->dev); |
8f518703 | 2945 | |
c9df406f | 2946 | if (mp->shared->win_protect) |
fc32b0e2 | 2947 | wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); |
1da177e4 | 2948 | |
a5fe3616 LB |
2949 | netif_carrier_off(dev); |
2950 | ||
b5e86db4 LB |
2951 | wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); |
2952 | ||
4fb0a54a | 2953 | set_rx_coal(mp, 250); |
a5fe3616 LB |
2954 | set_tx_coal(mp, 0); |
2955 | ||
c9df406f LB |
2956 | err = register_netdev(dev); |
2957 | if (err) | |
2958 | goto out; | |
1da177e4 | 2959 | |
e174961c JB |
2960 | dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n", |
2961 | mp->port_num, dev->dev_addr); | |
1da177e4 | 2962 | |
13d64285 | 2963 | if (mp->tx_desc_sram_size > 0) |
fc32b0e2 | 2964 | dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n"); |
1da177e4 | 2965 | |
c9df406f | 2966 | return 0; |
1da177e4 | 2967 | |
c9df406f LB |
2968 | out: |
2969 | free_netdev(dev); | |
1da177e4 | 2970 | |
c9df406f | 2971 | return err; |
1da177e4 LT |
2972 | } |
2973 | ||
c9df406f | 2974 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2975 | { |
fc32b0e2 | 2976 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
1da177e4 | 2977 | |
fc32b0e2 | 2978 | unregister_netdev(mp->dev); |
ed94493f LB |
2979 | if (mp->phy != NULL) |
2980 | phy_detach(mp->phy); | |
23f333a2 | 2981 | cancel_work_sync(&mp->tx_timeout_task); |
fc32b0e2 | 2982 | free_netdev(mp->dev); |
c9df406f | 2983 | |
c9df406f | 2984 | platform_set_drvdata(pdev, NULL); |
fc32b0e2 | 2985 | |
c9df406f | 2986 | return 0; |
1da177e4 LT |
2987 | } |
2988 | ||
c9df406f | 2989 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2990 | { |
fc32b0e2 | 2991 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
d0412d96 | 2992 | |
c9df406f | 2993 | /* Mask all interrupts on ethernet port */ |
37a6084f LB |
2994 | wrlp(mp, INT_MASK, 0); |
2995 | rdlp(mp, INT_MASK); | |
c9df406f | 2996 | |
fc32b0e2 LB |
2997 | if (netif_running(mp->dev)) |
2998 | port_reset(mp); | |
d0412d96 JC |
2999 | } |
3000 | ||
c9df406f | 3001 | static struct platform_driver mv643xx_eth_driver = { |
fc32b0e2 LB |
3002 | .probe = mv643xx_eth_probe, |
3003 | .remove = mv643xx_eth_remove, | |
3004 | .shutdown = mv643xx_eth_shutdown, | |
c9df406f | 3005 | .driver = { |
fc32b0e2 | 3006 | .name = MV643XX_ETH_NAME, |
c9df406f LB |
3007 | .owner = THIS_MODULE, |
3008 | }, | |
3009 | }; | |
3010 | ||
e5371493 | 3011 | static int __init mv643xx_eth_init_module(void) |
d0412d96 | 3012 | { |
c9df406f | 3013 | int rc; |
d0412d96 | 3014 | |
c9df406f LB |
3015 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
3016 | if (!rc) { | |
3017 | rc = platform_driver_register(&mv643xx_eth_driver); | |
3018 | if (rc) | |
3019 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
3020 | } | |
fc32b0e2 | 3021 | |
c9df406f | 3022 | return rc; |
d0412d96 | 3023 | } |
fc32b0e2 | 3024 | module_init(mv643xx_eth_init_module); |
d0412d96 | 3025 | |
e5371493 | 3026 | static void __exit mv643xx_eth_cleanup_module(void) |
d0412d96 | 3027 | { |
c9df406f LB |
3028 | platform_driver_unregister(&mv643xx_eth_driver); |
3029 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 | 3030 | } |
e5371493 | 3031 | module_exit(mv643xx_eth_cleanup_module); |
1da177e4 | 3032 | |
45675bc6 LB |
3033 | MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " |
3034 | "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); | |
c9df406f | 3035 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
fc32b0e2 | 3036 | MODULE_LICENSE("GPL"); |
c9df406f | 3037 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |
fc32b0e2 | 3038 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |