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1da177e4 LT |
1 | /* |
2 | * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports | |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> | |
4 | * | |
5 | * Based on the 64360 driver from: | |
6 | * Copyright (C) 2002 rabeeh@galileo.co.il | |
7 | * | |
8 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 9 | * written by Manish Lachwani |
1da177e4 LT |
10 | * |
11 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
12 | * | |
c8aaea25 | 13 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
14 | * Dale Farnsworth <dale@farnsworth.org> |
15 | * | |
16 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
17 | * <sjhill@realitydiluted.com> | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version 2 | |
22 | * of the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
32 | */ | |
33 | #include <linux/init.h> | |
34 | #include <linux/dma-mapping.h> | |
b6298c22 AV |
35 | #include <linux/in.h> |
36 | #include <linux/ip.h> | |
1da177e4 LT |
37 | #include <linux/tcp.h> |
38 | #include <linux/udp.h> | |
39 | #include <linux/etherdevice.h> | |
40 | ||
41 | #include <linux/bitops.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/ethtool.h> | |
d052d1be RK |
44 | #include <linux/platform_device.h> |
45 | ||
1da177e4 LT |
46 | #include <asm/io.h> |
47 | #include <asm/types.h> | |
48 | #include <asm/pgtable.h> | |
49 | #include <asm/system.h> | |
50 | #include <asm/delay.h> | |
51 | #include "mv643xx_eth.h" | |
52 | ||
1da177e4 | 53 | /* Static function declarations */ |
1da177e4 LT |
54 | static void eth_port_uc_addr_get(struct net_device *dev, |
55 | unsigned char *MacAddr); | |
16e03018 | 56 | static void eth_port_set_multicast_list(struct net_device *); |
9f8dd319 | 57 | static void mv643xx_eth_port_enable_tx(unsigned int port_num, |
12a87c64 | 58 | unsigned int queues); |
9f8dd319 | 59 | static void mv643xx_eth_port_enable_rx(unsigned int port_num, |
12a87c64 | 60 | unsigned int queues); |
9f8dd319 DF |
61 | static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num); |
62 | static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num); | |
ab4384a6 DF |
63 | static int mv643xx_eth_open(struct net_device *); |
64 | static int mv643xx_eth_stop(struct net_device *); | |
1da177e4 LT |
65 | static int mv643xx_eth_change_mtu(struct net_device *, int); |
66 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *); | |
67 | static void eth_port_init_mac_tables(unsigned int eth_port_num); | |
68 | #ifdef MV643XX_NAPI | |
69 | static int mv643xx_poll(struct net_device *dev, int *budget); | |
70 | #endif | |
c28a4f89 | 71 | static int ethernet_phy_get(unsigned int eth_port_num); |
1da177e4 LT |
72 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); |
73 | static int ethernet_phy_detect(unsigned int eth_port_num); | |
c28a4f89 JC |
74 | static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location); |
75 | static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val); | |
d0412d96 | 76 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); |
7282d491 | 77 | static const struct ethtool_ops mv643xx_ethtool_ops; |
1da177e4 LT |
78 | |
79 | static char mv643xx_driver_name[] = "mv643xx_eth"; | |
80 | static char mv643xx_driver_version[] = "1.0"; | |
81 | ||
82 | static void __iomem *mv643xx_eth_shared_base; | |
83 | ||
84 | /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */ | |
a9f6a0dd | 85 | static DEFINE_SPINLOCK(mv643xx_eth_phy_lock); |
1da177e4 LT |
86 | |
87 | static inline u32 mv_read(int offset) | |
88 | { | |
dc074a8a | 89 | void __iomem *reg_base; |
1da177e4 LT |
90 | |
91 | reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS; | |
92 | ||
93 | return readl(reg_base + offset); | |
94 | } | |
95 | ||
96 | static inline void mv_write(int offset, u32 data) | |
97 | { | |
dc074a8a | 98 | void __iomem *reg_base; |
1da177e4 LT |
99 | |
100 | reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS; | |
101 | writel(data, reg_base + offset); | |
102 | } | |
103 | ||
104 | /* | |
105 | * Changes MTU (maximum transfer unit) of the gigabit ethenret port | |
106 | * | |
107 | * Input : pointer to ethernet interface network device structure | |
108 | * new mtu size | |
109 | * Output : 0 upon success, -EINVAL upon failure | |
110 | */ | |
111 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) | |
112 | { | |
8f518703 | 113 | if ((new_mtu > 9500) || (new_mtu < 64)) |
1da177e4 | 114 | return -EINVAL; |
1da177e4 LT |
115 | |
116 | dev->mtu = new_mtu; | |
117 | /* | |
118 | * Stop then re-open the interface. This will allocate RX skb's with | |
119 | * the new MTU. | |
120 | * There is a possible danger that the open will not successed, due | |
121 | * to memory is full, which might fail the open function. | |
122 | */ | |
123 | if (netif_running(dev)) { | |
ab4384a6 DF |
124 | mv643xx_eth_stop(dev); |
125 | if (mv643xx_eth_open(dev)) | |
1da177e4 LT |
126 | printk(KERN_ERR |
127 | "%s: Fatal error on opening device\n", | |
128 | dev->name); | |
129 | } | |
130 | ||
1da177e4 LT |
131 | return 0; |
132 | } | |
133 | ||
134 | /* | |
f78fb474 | 135 | * mv643xx_eth_rx_refill_descs |
1da177e4 LT |
136 | * |
137 | * Fills / refills RX queue on a certain gigabit ethernet port | |
138 | * | |
139 | * Input : pointer to ethernet interface network device structure | |
140 | * Output : N/A | |
141 | */ | |
f78fb474 | 142 | static void mv643xx_eth_rx_refill_descs(struct net_device *dev) |
1da177e4 | 143 | { |
1da177e4 LT |
144 | struct mv643xx_private *mp = netdev_priv(dev); |
145 | struct pkt_info pkt_info; | |
146 | struct sk_buff *skb; | |
b44cd572 | 147 | int unaligned; |
1da177e4 | 148 | |
f78fb474 | 149 | while (mp->rx_desc_count < mp->rx_ring_size) { |
908b637f | 150 | skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment()); |
1da177e4 LT |
151 | if (!skb) |
152 | break; | |
f98e36f1 | 153 | mp->rx_desc_count++; |
908b637f | 154 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
b44cd572 | 155 | if (unaligned) |
908b637f | 156 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
1da177e4 | 157 | pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; |
7303fde8 DF |
158 | pkt_info.byte_cnt = ETH_RX_SKB_SIZE; |
159 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, | |
160 | ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); | |
1da177e4 LT |
161 | pkt_info.return_info = skb; |
162 | if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { | |
163 | printk(KERN_ERR | |
164 | "%s: Error allocating RX Ring\n", dev->name); | |
165 | break; | |
166 | } | |
7303fde8 | 167 | skb_reserve(skb, ETH_HW_IP_ALIGN); |
1da177e4 | 168 | } |
1da177e4 LT |
169 | /* |
170 | * If RX ring is empty of SKB, set a timer to try allocating | |
f78fb474 | 171 | * again at a later time. |
1da177e4 | 172 | */ |
f78fb474 | 173 | if (mp->rx_desc_count == 0) { |
1da177e4 | 174 | printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); |
f78fb474 | 175 | mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */ |
1da177e4 | 176 | add_timer(&mp->timeout); |
1da177e4 | 177 | } |
1da177e4 LT |
178 | } |
179 | ||
180 | /* | |
f78fb474 | 181 | * mv643xx_eth_rx_refill_descs_timer_wrapper |
1da177e4 LT |
182 | * |
183 | * Timer routine to wake up RX queue filling task. This function is | |
184 | * used only in case the RX queue is empty, and all alloc_skb has | |
185 | * failed (due to out of memory event). | |
186 | * | |
187 | * Input : pointer to ethernet interface network device structure | |
188 | * Output : N/A | |
189 | */ | |
f78fb474 | 190 | static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data) |
1da177e4 | 191 | { |
f78fb474 | 192 | mv643xx_eth_rx_refill_descs((struct net_device *)data); |
1da177e4 LT |
193 | } |
194 | ||
195 | /* | |
196 | * mv643xx_eth_update_mac_address | |
197 | * | |
198 | * Update the MAC address of the port in the address table | |
199 | * | |
200 | * Input : pointer to ethernet interface network device structure | |
201 | * Output : N/A | |
202 | */ | |
203 | static void mv643xx_eth_update_mac_address(struct net_device *dev) | |
204 | { | |
205 | struct mv643xx_private *mp = netdev_priv(dev); | |
206 | unsigned int port_num = mp->port_num; | |
207 | ||
208 | eth_port_init_mac_tables(port_num); | |
ed9b5d45 | 209 | eth_port_uc_addr_set(port_num, dev->dev_addr); |
1da177e4 LT |
210 | } |
211 | ||
212 | /* | |
213 | * mv643xx_eth_set_rx_mode | |
214 | * | |
215 | * Change from promiscuos to regular rx mode | |
216 | * | |
217 | * Input : pointer to ethernet interface network device structure | |
218 | * Output : N/A | |
219 | */ | |
220 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
221 | { | |
222 | struct mv643xx_private *mp = netdev_priv(dev); | |
01999873 | 223 | u32 config_reg; |
1da177e4 | 224 | |
01999873 | 225 | config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num)); |
1da177e4 | 226 | if (dev->flags & IFF_PROMISC) |
01999873 | 227 | config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; |
1da177e4 | 228 | else |
01999873 DF |
229 | config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE; |
230 | mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg); | |
16e03018 DF |
231 | |
232 | eth_port_set_multicast_list(dev); | |
1da177e4 LT |
233 | } |
234 | ||
235 | /* | |
236 | * mv643xx_eth_set_mac_address | |
237 | * | |
238 | * Change the interface's mac address. | |
239 | * No special hardware thing should be done because interface is always | |
240 | * put in promiscuous mode. | |
241 | * | |
242 | * Input : pointer to ethernet interface network device structure and | |
243 | * a pointer to the designated entry to be added to the cache. | |
244 | * Output : zero upon success, negative upon failure | |
245 | */ | |
246 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
247 | { | |
248 | int i; | |
249 | ||
250 | for (i = 0; i < 6; i++) | |
251 | /* +2 is for the offset of the HW addr type */ | |
252 | dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; | |
253 | mv643xx_eth_update_mac_address(dev); | |
254 | return 0; | |
255 | } | |
256 | ||
257 | /* | |
258 | * mv643xx_eth_tx_timeout | |
259 | * | |
260 | * Called upon a timeout on transmitting a packet | |
261 | * | |
262 | * Input : pointer to ethernet interface network device structure. | |
263 | * Output : N/A | |
264 | */ | |
265 | static void mv643xx_eth_tx_timeout(struct net_device *dev) | |
266 | { | |
267 | struct mv643xx_private *mp = netdev_priv(dev); | |
268 | ||
269 | printk(KERN_INFO "%s: TX timeout ", dev->name); | |
270 | ||
271 | /* Do the reset outside of interrupt context */ | |
272 | schedule_work(&mp->tx_timeout_task); | |
273 | } | |
274 | ||
275 | /* | |
276 | * mv643xx_eth_tx_timeout_task | |
277 | * | |
278 | * Actual routine to reset the adapter when a timeout on Tx has occurred | |
279 | */ | |
91c7c568 | 280 | static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 281 | { |
91c7c568 AV |
282 | struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, |
283 | tx_timeout_task); | |
284 | struct net_device *dev = mp->mii.dev; /* yuck */ | |
1da177e4 | 285 | |
94843566 DF |
286 | if (!netif_running(dev)) |
287 | return; | |
288 | ||
289 | netif_stop_queue(dev); | |
290 | ||
1da177e4 | 291 | eth_port_reset(mp->port_num); |
ed9b5d45 | 292 | eth_port_start(dev); |
94843566 DF |
293 | |
294 | if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
295 | netif_wake_queue(dev); | |
1da177e4 LT |
296 | } |
297 | ||
ff561eef DF |
298 | /** |
299 | * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors | |
1da177e4 | 300 | * |
ff561eef | 301 | * If force is non-zero, frees uncompleted descriptors as well |
1da177e4 | 302 | */ |
ff561eef | 303 | int mv643xx_eth_free_tx_descs(struct net_device *dev, int force) |
1da177e4 LT |
304 | { |
305 | struct mv643xx_private *mp = netdev_priv(dev); | |
ff561eef DF |
306 | struct eth_tx_desc *desc; |
307 | u32 cmd_sts; | |
308 | struct sk_buff *skb; | |
309 | unsigned long flags; | |
310 | int tx_index; | |
311 | dma_addr_t addr; | |
312 | int count; | |
313 | int released = 0; | |
1da177e4 | 314 | |
ff561eef DF |
315 | while (mp->tx_desc_count > 0) { |
316 | spin_lock_irqsave(&mp->lock, flags); | |
d344bff9 DF |
317 | |
318 | /* tx_desc_count might have changed before acquiring the lock */ | |
319 | if (mp->tx_desc_count <= 0) { | |
320 | spin_unlock_irqrestore(&mp->lock, flags); | |
321 | return released; | |
322 | } | |
323 | ||
ff561eef DF |
324 | tx_index = mp->tx_used_desc_q; |
325 | desc = &mp->p_tx_desc_area[tx_index]; | |
326 | cmd_sts = desc->cmd_sts; | |
327 | ||
328 | if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { | |
329 | spin_unlock_irqrestore(&mp->lock, flags); | |
330 | return released; | |
331 | } | |
332 | ||
333 | mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; | |
334 | mp->tx_desc_count--; | |
335 | ||
336 | addr = desc->buf_ptr; | |
337 | count = desc->byte_cnt; | |
338 | skb = mp->tx_skb[tx_index]; | |
339 | if (skb) | |
340 | mp->tx_skb[tx_index] = NULL; | |
341 | ||
7303fde8 | 342 | if (cmd_sts & ETH_ERROR_SUMMARY) { |
1da177e4 | 343 | printk("%s: Error in TX\n", dev->name); |
ff561eef | 344 | mp->stats.tx_errors++; |
1da177e4 LT |
345 | } |
346 | ||
d344bff9 DF |
347 | spin_unlock_irqrestore(&mp->lock, flags); |
348 | ||
ff561eef DF |
349 | if (cmd_sts & ETH_TX_FIRST_DESC) |
350 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); | |
cb415d30 | 351 | else |
ff561eef | 352 | dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); |
1da177e4 | 353 | |
ff561eef DF |
354 | if (skb) |
355 | dev_kfree_skb_irq(skb); | |
356 | ||
357 | released = 1; | |
1da177e4 LT |
358 | } |
359 | ||
1da177e4 LT |
360 | return released; |
361 | } | |
362 | ||
ff561eef DF |
363 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) |
364 | { | |
365 | struct mv643xx_private *mp = netdev_priv(dev); | |
366 | ||
367 | if (mv643xx_eth_free_tx_descs(dev, 0) && | |
368 | mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
369 | netif_wake_queue(dev); | |
370 | } | |
371 | ||
372 | static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) | |
373 | { | |
374 | mv643xx_eth_free_tx_descs(dev, 1); | |
375 | } | |
376 | ||
1da177e4 LT |
377 | /* |
378 | * mv643xx_eth_receive | |
379 | * | |
380 | * This function is forward packets that are received from the port's | |
381 | * queues toward kernel core or FastRoute them to another interface. | |
382 | * | |
383 | * Input : dev - a pointer to the required interface | |
384 | * max - maximum number to receive (0 means unlimted) | |
385 | * | |
386 | * Output : number of served packets | |
387 | */ | |
1da177e4 | 388 | static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) |
1da177e4 LT |
389 | { |
390 | struct mv643xx_private *mp = netdev_priv(dev); | |
391 | struct net_device_stats *stats = &mp->stats; | |
392 | unsigned int received_packets = 0; | |
393 | struct sk_buff *skb; | |
394 | struct pkt_info pkt_info; | |
395 | ||
b1dd9ca1 | 396 | while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { |
54caf44d | 397 | dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, |
71d28725 | 398 | DMA_FROM_DEVICE); |
f98e36f1 | 399 | mp->rx_desc_count--; |
1da177e4 | 400 | received_packets++; |
b1dd9ca1 | 401 | |
468d09f8 DF |
402 | /* |
403 | * Update statistics. | |
404 | * Note byte count includes 4 byte CRC count | |
405 | */ | |
1da177e4 LT |
406 | stats->rx_packets++; |
407 | stats->rx_bytes += pkt_info.byte_cnt; | |
408 | skb = pkt_info.return_info; | |
409 | /* | |
410 | * In case received a packet without first / last bits on OR | |
411 | * the error summary bit is on, the packets needs to be dropeed. | |
412 | */ | |
413 | if (((pkt_info.cmd_sts | |
414 | & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != | |
415 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) | |
416 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { | |
417 | stats->rx_dropped++; | |
418 | if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | | |
419 | ETH_RX_LAST_DESC)) != | |
420 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { | |
421 | if (net_ratelimit()) | |
422 | printk(KERN_ERR | |
423 | "%s: Received packet spread " | |
424 | "on multiple descriptors\n", | |
425 | dev->name); | |
426 | } | |
427 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) | |
428 | stats->rx_errors++; | |
429 | ||
430 | dev_kfree_skb_irq(skb); | |
431 | } else { | |
432 | /* | |
433 | * The -4 is for the CRC in the trailer of the | |
434 | * received packet | |
435 | */ | |
436 | skb_put(skb, pkt_info.byte_cnt - 4); | |
1da177e4 LT |
437 | |
438 | if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { | |
439 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
440 | skb->csum = htons( | |
441 | (pkt_info.cmd_sts & 0x0007fff8) >> 3); | |
442 | } | |
443 | skb->protocol = eth_type_trans(skb, dev); | |
444 | #ifdef MV643XX_NAPI | |
445 | netif_receive_skb(skb); | |
446 | #else | |
447 | netif_rx(skb); | |
448 | #endif | |
449 | } | |
12ad74f8 | 450 | dev->last_rx = jiffies; |
1da177e4 | 451 | } |
f78fb474 | 452 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
1da177e4 LT |
453 | |
454 | return received_packets; | |
455 | } | |
456 | ||
d0412d96 JC |
457 | /* Set the mv643xx port configuration register for the speed/duplex mode. */ |
458 | static void mv643xx_eth_update_pscr(struct net_device *dev, | |
459 | struct ethtool_cmd *ecmd) | |
460 | { | |
461 | struct mv643xx_private *mp = netdev_priv(dev); | |
462 | int port_num = mp->port_num; | |
463 | u32 o_pscr, n_pscr; | |
12a87c64 | 464 | unsigned int queues; |
d0412d96 JC |
465 | |
466 | o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); | |
467 | n_pscr = o_pscr; | |
468 | ||
469 | /* clear speed, duplex and rx buffer size fields */ | |
470 | n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 | | |
471 | MV643XX_ETH_SET_GMII_SPEED_TO_1000 | | |
472 | MV643XX_ETH_SET_FULL_DUPLEX_MODE | | |
473 | MV643XX_ETH_MAX_RX_PACKET_MASK); | |
474 | ||
475 | if (ecmd->duplex == DUPLEX_FULL) | |
476 | n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE; | |
477 | ||
478 | if (ecmd->speed == SPEED_1000) | |
479 | n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 | | |
480 | MV643XX_ETH_MAX_RX_PACKET_9700BYTE; | |
481 | else { | |
482 | if (ecmd->speed == SPEED_100) | |
483 | n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100; | |
484 | n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE; | |
485 | } | |
486 | ||
487 | if (n_pscr != o_pscr) { | |
488 | if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0) | |
489 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
490 | n_pscr); | |
491 | else { | |
12a87c64 | 492 | queues = mv643xx_eth_port_disable_tx(port_num); |
d0412d96 JC |
493 | |
494 | o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE; | |
495 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
496 | o_pscr); | |
497 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
498 | n_pscr); | |
499 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), | |
500 | n_pscr); | |
12a87c64 DF |
501 | if (queues) |
502 | mv643xx_eth_port_enable_tx(port_num, queues); | |
d0412d96 JC |
503 | } |
504 | } | |
505 | } | |
506 | ||
1da177e4 LT |
507 | /* |
508 | * mv643xx_eth_int_handler | |
509 | * | |
510 | * Main interrupt handler for the gigbit ethernet ports | |
511 | * | |
512 | * Input : irq - irq number (not used) | |
513 | * dev_id - a pointer to the required interface's data structure | |
514 | * regs - not used | |
515 | * Output : N/A | |
516 | */ | |
517 | ||
7d12e780 | 518 | static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) |
1da177e4 LT |
519 | { |
520 | struct net_device *dev = (struct net_device *)dev_id; | |
521 | struct mv643xx_private *mp = netdev_priv(dev); | |
522 | u32 eth_int_cause, eth_int_cause_ext = 0; | |
523 | unsigned int port_num = mp->port_num; | |
524 | ||
525 | /* Read interrupt cause registers */ | |
526 | eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) & | |
7303fde8 | 527 | ETH_INT_UNMASK_ALL; |
468d09f8 | 528 | if (eth_int_cause & ETH_INT_CAUSE_EXT) { |
1da177e4 LT |
529 | eth_int_cause_ext = mv_read( |
530 | MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) & | |
7303fde8 | 531 | ETH_INT_UNMASK_ALL_EXT; |
468d09f8 DF |
532 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), |
533 | ~eth_int_cause_ext); | |
1da177e4 | 534 | } |
7303fde8 | 535 | |
1da177e4 | 536 | /* PHY status changed */ |
468d09f8 | 537 | if (eth_int_cause_ext & ETH_INT_CAUSE_PHY) { |
d0412d96 JC |
538 | struct ethtool_cmd cmd; |
539 | ||
c28a4f89 | 540 | if (mii_link_ok(&mp->mii)) { |
d0412d96 JC |
541 | mii_ethtool_gset(&mp->mii, &cmd); |
542 | mv643xx_eth_update_pscr(dev, &cmd); | |
ff561eef DF |
543 | mv643xx_eth_port_enable_tx(port_num, |
544 | ETH_TX_QUEUES_ENABLED); | |
c28a4f89 JC |
545 | if (!netif_carrier_ok(dev)) { |
546 | netif_carrier_on(dev); | |
ff561eef DF |
547 | if (mp->tx_ring_size - mp->tx_desc_count >= |
548 | MAX_DESCS_PER_SKB) | |
d0412d96 | 549 | netif_wake_queue(dev); |
c28a4f89 JC |
550 | } |
551 | } else if (netif_carrier_ok(dev)) { | |
1da177e4 | 552 | netif_stop_queue(dev); |
c28a4f89 | 553 | netif_carrier_off(dev); |
1da177e4 LT |
554 | } |
555 | } | |
556 | ||
468d09f8 DF |
557 | #ifdef MV643XX_NAPI |
558 | if (eth_int_cause & ETH_INT_CAUSE_RX) { | |
559 | /* schedule the NAPI poll routine to maintain port */ | |
560 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), | |
561 | ETH_INT_MASK_ALL); | |
562 | /* wait for previous write to complete */ | |
563 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
564 | ||
565 | netif_rx_schedule(dev); | |
566 | } | |
567 | #else | |
568 | if (eth_int_cause & ETH_INT_CAUSE_RX) | |
569 | mv643xx_eth_receive_queue(dev, INT_MAX); | |
5c537408 | 570 | #endif |
468d09f8 DF |
571 | if (eth_int_cause_ext & ETH_INT_CAUSE_TX) |
572 | mv643xx_eth_free_completed_tx_descs(dev); | |
468d09f8 | 573 | |
1da177e4 LT |
574 | /* |
575 | * If no real interrupt occured, exit. | |
576 | * This can happen when using gigE interrupt coalescing mechanism. | |
577 | */ | |
578 | if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) | |
579 | return IRQ_NONE; | |
580 | ||
581 | return IRQ_HANDLED; | |
582 | } | |
583 | ||
584 | #ifdef MV643XX_COAL | |
585 | ||
586 | /* | |
587 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path | |
588 | * | |
589 | * DESCRIPTION: | |
590 | * This routine sets the RX coalescing interrupt mechanism parameter. | |
591 | * This parameter is a timeout counter, that counts in 64 t_clk | |
592 | * chunks ; that when timeout event occurs a maskable interrupt | |
593 | * occurs. | |
594 | * The parameter is calculated using the tClk of the MV-643xx chip | |
595 | * , and the required delay of the interrupt in usec. | |
596 | * | |
597 | * INPUT: | |
598 | * unsigned int eth_port_num Ethernet port number | |
599 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units | |
600 | * unsigned int delay Delay in usec | |
601 | * | |
602 | * OUTPUT: | |
603 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
604 | * | |
605 | * RETURN: | |
606 | * The interrupt coalescing value set in the gigE port. | |
607 | * | |
608 | */ | |
609 | static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num, | |
610 | unsigned int t_clk, unsigned int delay) | |
611 | { | |
612 | unsigned int coal = ((t_clk / 1000000) * delay) / 64; | |
613 | ||
614 | /* Set RX Coalescing mechanism */ | |
615 | mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num), | |
616 | ((coal & 0x3fff) << 8) | | |
617 | (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num)) | |
618 | & 0xffc000ff)); | |
619 | ||
620 | return coal; | |
621 | } | |
622 | #endif | |
623 | ||
624 | /* | |
625 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path | |
626 | * | |
627 | * DESCRIPTION: | |
628 | * This routine sets the TX coalescing interrupt mechanism parameter. | |
629 | * This parameter is a timeout counter, that counts in 64 t_clk | |
630 | * chunks ; that when timeout event occurs a maskable interrupt | |
631 | * occurs. | |
632 | * The parameter is calculated using the t_cLK frequency of the | |
633 | * MV-643xx chip and the required delay in the interrupt in uSec | |
634 | * | |
635 | * INPUT: | |
636 | * unsigned int eth_port_num Ethernet port number | |
637 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units | |
638 | * unsigned int delay Delay in uSeconds | |
639 | * | |
640 | * OUTPUT: | |
641 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
642 | * | |
643 | * RETURN: | |
644 | * The interrupt coalescing value set in the gigE port. | |
645 | * | |
646 | */ | |
647 | static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num, | |
648 | unsigned int t_clk, unsigned int delay) | |
649 | { | |
650 | unsigned int coal; | |
651 | coal = ((t_clk / 1000000) * delay) / 64; | |
652 | /* Set TX Coalescing mechanism */ | |
653 | mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), | |
654 | coal << 4); | |
655 | return coal; | |
656 | } | |
657 | ||
1da177e4 LT |
658 | /* |
659 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. | |
660 | * | |
661 | * DESCRIPTION: | |
662 | * This function prepares a Rx chained list of descriptors and packet | |
663 | * buffers in a form of a ring. The routine must be called after port | |
664 | * initialization routine and before port start routine. | |
665 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
666 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
667 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
668 | * with physical addresses. | |
669 | * | |
670 | * INPUT: | |
671 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
672 | * | |
673 | * OUTPUT: | |
674 | * The routine updates the Ethernet port control struct with information | |
675 | * regarding the Rx descriptors and buffers. | |
676 | * | |
677 | * RETURN: | |
678 | * None. | |
679 | */ | |
680 | static void ether_init_rx_desc_ring(struct mv643xx_private *mp) | |
681 | { | |
682 | volatile struct eth_rx_desc *p_rx_desc; | |
683 | int rx_desc_num = mp->rx_ring_size; | |
684 | int i; | |
685 | ||
686 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ | |
687 | p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; | |
688 | for (i = 0; i < rx_desc_num; i++) { | |
689 | p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + | |
690 | ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); | |
691 | } | |
692 | ||
693 | /* Save Rx desc pointer to driver struct. */ | |
694 | mp->rx_curr_desc_q = 0; | |
695 | mp->rx_used_desc_q = 0; | |
696 | ||
697 | mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); | |
1da177e4 LT |
698 | } |
699 | ||
700 | /* | |
701 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. | |
702 | * | |
703 | * DESCRIPTION: | |
704 | * This function prepares a Tx chained list of descriptors and packet | |
705 | * buffers in a form of a ring. The routine must be called after port | |
706 | * initialization routine and before port start routine. | |
707 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
708 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
709 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
710 | * with physical addresses. | |
711 | * | |
712 | * INPUT: | |
713 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
714 | * | |
715 | * OUTPUT: | |
716 | * The routine updates the Ethernet port control struct with information | |
717 | * regarding the Tx descriptors and buffers. | |
718 | * | |
719 | * RETURN: | |
720 | * None. | |
721 | */ | |
722 | static void ether_init_tx_desc_ring(struct mv643xx_private *mp) | |
723 | { | |
724 | int tx_desc_num = mp->tx_ring_size; | |
725 | struct eth_tx_desc *p_tx_desc; | |
726 | int i; | |
727 | ||
728 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ | |
729 | p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; | |
730 | for (i = 0; i < tx_desc_num; i++) { | |
731 | p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + | |
732 | ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); | |
733 | } | |
734 | ||
735 | mp->tx_curr_desc_q = 0; | |
736 | mp->tx_used_desc_q = 0; | |
1da177e4 LT |
737 | |
738 | mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); | |
1da177e4 LT |
739 | } |
740 | ||
d0412d96 JC |
741 | static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
742 | { | |
743 | struct mv643xx_private *mp = netdev_priv(dev); | |
744 | int err; | |
745 | ||
746 | spin_lock_irq(&mp->lock); | |
747 | err = mii_ethtool_sset(&mp->mii, cmd); | |
748 | spin_unlock_irq(&mp->lock); | |
749 | ||
750 | return err; | |
751 | } | |
752 | ||
753 | static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
754 | { | |
755 | struct mv643xx_private *mp = netdev_priv(dev); | |
756 | int err; | |
757 | ||
758 | spin_lock_irq(&mp->lock); | |
759 | err = mii_ethtool_gset(&mp->mii, cmd); | |
760 | spin_unlock_irq(&mp->lock); | |
761 | ||
762 | /* The PHY may support 1000baseT_Half, but the mv643xx does not */ | |
763 | cmd->supported &= ~SUPPORTED_1000baseT_Half; | |
764 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
765 | ||
766 | return err; | |
767 | } | |
768 | ||
ab4384a6 DF |
769 | /* |
770 | * mv643xx_eth_open | |
771 | * | |
772 | * This function is called when openning the network device. The function | |
773 | * should initialize all the hardware, initialize cyclic Rx/Tx | |
774 | * descriptors chain and buffers and allocate an IRQ to the network | |
775 | * device. | |
776 | * | |
777 | * Input : a pointer to the network device structure | |
778 | * | |
779 | * Output : zero of success , nonzero if fails. | |
780 | */ | |
781 | ||
782 | static int mv643xx_eth_open(struct net_device *dev) | |
1da177e4 LT |
783 | { |
784 | struct mv643xx_private *mp = netdev_priv(dev); | |
785 | unsigned int port_num = mp->port_num; | |
786 | unsigned int size; | |
ab4384a6 DF |
787 | int err; |
788 | ||
85cf572c DF |
789 | /* Clear any pending ethernet port interrupts */ |
790 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); | |
791 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
792 | /* wait for previous write to complete */ | |
793 | mv_read (MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)); | |
794 | ||
ab4384a6 | 795 | err = request_irq(dev->irq, mv643xx_eth_int_handler, |
1fb9df5d | 796 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); |
ab4384a6 DF |
797 | if (err) { |
798 | printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n", | |
799 | port_num); | |
800 | return -EAGAIN; | |
801 | } | |
1da177e4 | 802 | |
1da177e4 LT |
803 | eth_port_init(mp); |
804 | ||
1da177e4 | 805 | memset(&mp->timeout, 0, sizeof(struct timer_list)); |
f78fb474 | 806 | mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; |
1da177e4 LT |
807 | mp->timeout.data = (unsigned long)dev; |
808 | ||
1da177e4 LT |
809 | /* Allocate RX and TX skb rings */ |
810 | mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, | |
811 | GFP_KERNEL); | |
812 | if (!mp->rx_skb) { | |
813 | printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); | |
ab4384a6 DF |
814 | err = -ENOMEM; |
815 | goto out_free_irq; | |
1da177e4 LT |
816 | } |
817 | mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, | |
818 | GFP_KERNEL); | |
819 | if (!mp->tx_skb) { | |
820 | printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); | |
ab4384a6 DF |
821 | err = -ENOMEM; |
822 | goto out_free_rx_skb; | |
1da177e4 LT |
823 | } |
824 | ||
825 | /* Allocate TX ring */ | |
f98e36f1 | 826 | mp->tx_desc_count = 0; |
1da177e4 LT |
827 | size = mp->tx_ring_size * sizeof(struct eth_tx_desc); |
828 | mp->tx_desc_area_size = size; | |
829 | ||
830 | if (mp->tx_sram_size) { | |
831 | mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, | |
832 | mp->tx_sram_size); | |
833 | mp->tx_desc_dma = mp->tx_sram_addr; | |
834 | } else | |
835 | mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, | |
836 | &mp->tx_desc_dma, | |
837 | GFP_KERNEL); | |
838 | ||
839 | if (!mp->p_tx_desc_area) { | |
840 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | |
841 | dev->name, size); | |
ab4384a6 DF |
842 | err = -ENOMEM; |
843 | goto out_free_tx_skb; | |
1da177e4 LT |
844 | } |
845 | BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ | |
846 | memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); | |
847 | ||
848 | ether_init_tx_desc_ring(mp); | |
849 | ||
850 | /* Allocate RX ring */ | |
f98e36f1 | 851 | mp->rx_desc_count = 0; |
1da177e4 LT |
852 | size = mp->rx_ring_size * sizeof(struct eth_rx_desc); |
853 | mp->rx_desc_area_size = size; | |
854 | ||
855 | if (mp->rx_sram_size) { | |
856 | mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, | |
857 | mp->rx_sram_size); | |
858 | mp->rx_desc_dma = mp->rx_sram_addr; | |
859 | } else | |
860 | mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, | |
861 | &mp->rx_desc_dma, | |
862 | GFP_KERNEL); | |
863 | ||
864 | if (!mp->p_rx_desc_area) { | |
865 | printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", | |
866 | dev->name, size); | |
867 | printk(KERN_ERR "%s: Freeing previously allocated TX queues...", | |
868 | dev->name); | |
869 | if (mp->rx_sram_size) | |
dd09b1de | 870 | iounmap(mp->p_tx_desc_area); |
1da177e4 LT |
871 | else |
872 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
873 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
ab4384a6 DF |
874 | err = -ENOMEM; |
875 | goto out_free_tx_skb; | |
1da177e4 LT |
876 | } |
877 | memset((void *)mp->p_rx_desc_area, 0, size); | |
878 | ||
879 | ether_init_rx_desc_ring(mp); | |
880 | ||
f78fb474 | 881 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
1da177e4 | 882 | |
ed9b5d45 | 883 | eth_port_start(dev); |
1da177e4 LT |
884 | |
885 | /* Interrupt Coalescing */ | |
886 | ||
887 | #ifdef MV643XX_COAL | |
888 | mp->rx_int_coal = | |
889 | eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL); | |
890 | #endif | |
891 | ||
892 | mp->tx_int_coal = | |
893 | eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL); | |
894 | ||
8f518703 DF |
895 | /* Unmask phy and link status changes interrupts */ |
896 | mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), | |
7303fde8 | 897 | ETH_INT_UNMASK_ALL_EXT); |
1da177e4 | 898 | |
8f518703 | 899 | /* Unmask RX buffer and TX end interrupt */ |
7303fde8 | 900 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); |
d0412d96 | 901 | |
1da177e4 | 902 | return 0; |
ab4384a6 DF |
903 | |
904 | out_free_tx_skb: | |
905 | kfree(mp->tx_skb); | |
906 | out_free_rx_skb: | |
907 | kfree(mp->rx_skb); | |
908 | out_free_irq: | |
909 | free_irq(dev->irq, dev); | |
910 | ||
911 | return err; | |
1da177e4 LT |
912 | } |
913 | ||
914 | static void mv643xx_eth_free_tx_rings(struct net_device *dev) | |
915 | { | |
916 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 LT |
917 | |
918 | /* Stop Tx Queues */ | |
ff561eef | 919 | mv643xx_eth_port_disable_tx(mp->port_num); |
1da177e4 | 920 | |
ff561eef DF |
921 | /* Free outstanding skb's on TX ring */ |
922 | mv643xx_eth_free_all_tx_descs(dev); | |
923 | ||
924 | BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); | |
1da177e4 LT |
925 | |
926 | /* Free TX ring */ | |
927 | if (mp->tx_sram_size) | |
928 | iounmap(mp->p_tx_desc_area); | |
929 | else | |
930 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
931 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
932 | } | |
933 | ||
934 | static void mv643xx_eth_free_rx_rings(struct net_device *dev) | |
935 | { | |
936 | struct mv643xx_private *mp = netdev_priv(dev); | |
937 | unsigned int port_num = mp->port_num; | |
938 | int curr; | |
939 | ||
940 | /* Stop RX Queues */ | |
9f8dd319 | 941 | mv643xx_eth_port_disable_rx(port_num); |
1da177e4 LT |
942 | |
943 | /* Free preallocated skb's on RX rings */ | |
f98e36f1 | 944 | for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { |
1da177e4 LT |
945 | if (mp->rx_skb[curr]) { |
946 | dev_kfree_skb(mp->rx_skb[curr]); | |
f98e36f1 | 947 | mp->rx_desc_count--; |
1da177e4 LT |
948 | } |
949 | } | |
950 | ||
f98e36f1 | 951 | if (mp->rx_desc_count) |
1da177e4 LT |
952 | printk(KERN_ERR |
953 | "%s: Error in freeing Rx Ring. %d skb's still" | |
954 | " stuck in RX Ring - ignoring them\n", dev->name, | |
f98e36f1 | 955 | mp->rx_desc_count); |
1da177e4 LT |
956 | /* Free RX ring */ |
957 | if (mp->rx_sram_size) | |
958 | iounmap(mp->p_rx_desc_area); | |
959 | else | |
960 | dma_free_coherent(NULL, mp->rx_desc_area_size, | |
961 | mp->p_rx_desc_area, mp->rx_desc_dma); | |
962 | } | |
963 | ||
964 | /* | |
965 | * mv643xx_eth_stop | |
966 | * | |
967 | * This function is used when closing the network device. | |
968 | * It updates the hardware, | |
969 | * release all memory that holds buffers and descriptors and release the IRQ. | |
970 | * Input : a pointer to the device structure | |
971 | * Output : zero if success , nonzero if fails | |
972 | */ | |
973 | ||
ab4384a6 | 974 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 LT |
975 | { |
976 | struct mv643xx_private *mp = netdev_priv(dev); | |
977 | unsigned int port_num = mp->port_num; | |
978 | ||
c2e5b352 | 979 | /* Mask all interrupts on ethernet port */ |
7303fde8 | 980 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); |
c2e5b352 | 981 | /* wait for previous write to complete */ |
8f518703 DF |
982 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); |
983 | ||
984 | #ifdef MV643XX_NAPI | |
985 | netif_poll_disable(dev); | |
986 | #endif | |
1da177e4 LT |
987 | netif_carrier_off(dev); |
988 | netif_stop_queue(dev); | |
989 | ||
1da177e4 LT |
990 | eth_port_reset(mp->port_num); |
991 | ||
8f518703 DF |
992 | mv643xx_eth_free_tx_rings(dev); |
993 | mv643xx_eth_free_rx_rings(dev); | |
1da177e4 | 994 | |
8f518703 DF |
995 | #ifdef MV643XX_NAPI |
996 | netif_poll_enable(dev); | |
997 | #endif | |
1da177e4 | 998 | |
1da177e4 | 999 | free_irq(dev->irq, dev); |
1da177e4 LT |
1000 | |
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | #ifdef MV643XX_NAPI | |
1da177e4 LT |
1005 | /* |
1006 | * mv643xx_poll | |
1007 | * | |
1008 | * This function is used in case of NAPI | |
1009 | */ | |
1010 | static int mv643xx_poll(struct net_device *dev, int *budget) | |
1011 | { | |
1012 | struct mv643xx_private *mp = netdev_priv(dev); | |
1013 | int done = 1, orig_budget, work_done; | |
1014 | unsigned int port_num = mp->port_num; | |
1da177e4 LT |
1015 | |
1016 | #ifdef MV643XX_TX_FAST_REFILL | |
1017 | if (++mp->tx_clean_threshold > 5) { | |
ff561eef | 1018 | mv643xx_eth_free_completed_tx_descs(dev); |
1da177e4 | 1019 | mp->tx_clean_threshold = 0; |
1da177e4 LT |
1020 | } |
1021 | #endif | |
1022 | ||
1023 | if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num))) | |
1024 | != (u32) mp->rx_used_desc_q) { | |
1025 | orig_budget = *budget; | |
1026 | if (orig_budget > dev->quota) | |
1027 | orig_budget = dev->quota; | |
1028 | work_done = mv643xx_eth_receive_queue(dev, orig_budget); | |
1da177e4 LT |
1029 | *budget -= work_done; |
1030 | dev->quota -= work_done; | |
1031 | if (work_done >= orig_budget) | |
1032 | done = 0; | |
1033 | } | |
1034 | ||
1035 | if (done) { | |
8f518703 | 1036 | netif_rx_complete(dev); |
1da177e4 LT |
1037 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0); |
1038 | mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0); | |
1039 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), | |
7303fde8 | 1040 | ETH_INT_UNMASK_ALL); |
1da177e4 LT |
1041 | } |
1042 | ||
1043 | return done ? 0 : 1; | |
1044 | } | |
1045 | #endif | |
1046 | ||
c8aaea25 DF |
1047 | /** |
1048 | * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments | |
1049 | * | |
1050 | * Hardware can't handle unaligned fragments smaller than 9 bytes. | |
f7ea3337 PJ |
1051 | * This helper function detects that case. |
1052 | */ | |
1053 | ||
1054 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) | |
1055 | { | |
b4de9051 DF |
1056 | unsigned int frag; |
1057 | skb_frag_t *fragp; | |
f7ea3337 | 1058 | |
b4de9051 DF |
1059 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
1060 | fragp = &skb_shinfo(skb)->frags[frag]; | |
1061 | if (fragp->size <= 8 && fragp->page_offset & 0x7) | |
1062 | return 1; | |
1063 | } | |
1064 | return 0; | |
f7ea3337 PJ |
1065 | } |
1066 | ||
c8aaea25 DF |
1067 | /** |
1068 | * eth_alloc_tx_desc_index - return the index of the next available tx desc | |
1069 | */ | |
1070 | static int eth_alloc_tx_desc_index(struct mv643xx_private *mp) | |
1071 | { | |
1072 | int tx_desc_curr; | |
1073 | ||
c8aaea25 | 1074 | BUG_ON(mp->tx_desc_count >= mp->tx_ring_size); |
c8aaea25 | 1075 | |
ff561eef | 1076 | tx_desc_curr = mp->tx_curr_desc_q; |
c8aaea25 DF |
1077 | mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; |
1078 | ||
1079 | BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); | |
1080 | ||
1081 | return tx_desc_curr; | |
1082 | } | |
1083 | ||
1084 | /** | |
1085 | * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. | |
1da177e4 | 1086 | * |
c8aaea25 DF |
1087 | * Ensure the data for each fragment to be transmitted is mapped properly, |
1088 | * then fill in descriptors in the tx hw queue. | |
1da177e4 | 1089 | */ |
c8aaea25 DF |
1090 | static void eth_tx_fill_frag_descs(struct mv643xx_private *mp, |
1091 | struct sk_buff *skb) | |
1da177e4 | 1092 | { |
c8aaea25 DF |
1093 | int frag; |
1094 | int tx_index; | |
1095 | struct eth_tx_desc *desc; | |
1da177e4 | 1096 | |
c8aaea25 DF |
1097 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
1098 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
1099 | ||
1100 | tx_index = eth_alloc_tx_desc_index(mp); | |
1101 | desc = &mp->p_tx_desc_area[tx_index]; | |
1102 | ||
1103 | desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA; | |
1104 | /* Last Frag enables interrupt and frees the skb */ | |
1105 | if (frag == (skb_shinfo(skb)->nr_frags - 1)) { | |
1106 | desc->cmd_sts |= ETH_ZERO_PADDING | | |
1107 | ETH_TX_LAST_DESC | | |
1108 | ETH_TX_ENABLE_INTERRUPT; | |
1109 | mp->tx_skb[tx_index] = skb; | |
1110 | } else | |
05980775 | 1111 | mp->tx_skb[tx_index] = NULL; |
c8aaea25 DF |
1112 | |
1113 | desc = &mp->p_tx_desc_area[tx_index]; | |
1114 | desc->l4i_chk = 0; | |
1115 | desc->byte_cnt = this_frag->size; | |
1116 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
1117 | this_frag->page_offset, | |
1118 | this_frag->size, | |
1119 | DMA_TO_DEVICE); | |
1da177e4 | 1120 | } |
c8aaea25 | 1121 | } |
1da177e4 | 1122 | |
c8aaea25 DF |
1123 | /** |
1124 | * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw | |
1125 | * | |
1126 | * Ensure the data for an skb to be transmitted is mapped properly, | |
1127 | * then fill in descriptors in the tx hw queue and start the hardware. | |
1128 | */ | |
ff561eef DF |
1129 | static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp, |
1130 | struct sk_buff *skb) | |
c8aaea25 DF |
1131 | { |
1132 | int tx_index; | |
1133 | struct eth_tx_desc *desc; | |
1134 | u32 cmd_sts; | |
1135 | int length; | |
ff561eef | 1136 | int nr_frags = skb_shinfo(skb)->nr_frags; |
1da177e4 | 1137 | |
c8aaea25 | 1138 | cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; |
1da177e4 | 1139 | |
c8aaea25 DF |
1140 | tx_index = eth_alloc_tx_desc_index(mp); |
1141 | desc = &mp->p_tx_desc_area[tx_index]; | |
1142 | ||
ff561eef | 1143 | if (nr_frags) { |
c8aaea25 DF |
1144 | eth_tx_fill_frag_descs(mp, skb); |
1145 | ||
1146 | length = skb_headlen(skb); | |
05980775 | 1147 | mp->tx_skb[tx_index] = NULL; |
c8aaea25 DF |
1148 | } else { |
1149 | cmd_sts |= ETH_ZERO_PADDING | | |
1150 | ETH_TX_LAST_DESC | | |
1151 | ETH_TX_ENABLE_INTERRUPT; | |
1152 | length = skb->len; | |
1153 | mp->tx_skb[tx_index] = skb; | |
f7ea3337 PJ |
1154 | } |
1155 | ||
c8aaea25 DF |
1156 | desc->byte_cnt = length; |
1157 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
1da177e4 | 1158 | |
84fa7933 | 1159 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
c8aaea25 DF |
1160 | BUG_ON(skb->protocol != ETH_P_IP); |
1161 | ||
1162 | cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | | |
1163 | ETH_GEN_IP_V_4_CHECKSUM | | |
eddc9ec5 | 1164 | ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; |
c8aaea25 | 1165 | |
eddc9ec5 | 1166 | switch (ip_hdr(skb)->protocol) { |
c8aaea25 DF |
1167 | case IPPROTO_UDP: |
1168 | cmd_sts |= ETH_UDP_FRAME; | |
4bedb452 | 1169 | desc->l4i_chk = udp_hdr(skb)->check; |
c8aaea25 DF |
1170 | break; |
1171 | case IPPROTO_TCP: | |
aa8223c7 | 1172 | desc->l4i_chk = tcp_hdr(skb)->check; |
c8aaea25 DF |
1173 | break; |
1174 | default: | |
1175 | BUG(); | |
1da177e4 | 1176 | } |
1da177e4 | 1177 | } else { |
c8aaea25 DF |
1178 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
1179 | cmd_sts |= 5 << ETH_TX_IHL_SHIFT; | |
1180 | desc->l4i_chk = 0; | |
1181 | } | |
1da177e4 | 1182 | |
c8aaea25 DF |
1183 | /* ensure all other descriptors are written before first cmd_sts */ |
1184 | wmb(); | |
1185 | desc->cmd_sts = cmd_sts; | |
1da177e4 | 1186 | |
c8aaea25 DF |
1187 | /* ensure all descriptors are written before poking hardware */ |
1188 | wmb(); | |
ff561eef | 1189 | mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED); |
1da177e4 | 1190 | |
ff561eef | 1191 | mp->tx_desc_count += nr_frags + 1; |
c8aaea25 | 1192 | } |
1da177e4 | 1193 | |
c8aaea25 DF |
1194 | /** |
1195 | * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission | |
1196 | * | |
1197 | */ | |
1198 | static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1199 | { | |
1200 | struct mv643xx_private *mp = netdev_priv(dev); | |
1201 | struct net_device_stats *stats = &mp->stats; | |
1202 | unsigned long flags; | |
1da177e4 | 1203 | |
c8aaea25 DF |
1204 | BUG_ON(netif_queue_stopped(dev)); |
1205 | BUG_ON(skb == NULL); | |
94843566 DF |
1206 | |
1207 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { | |
1208 | printk(KERN_ERR "%s: transmit with queue full\n", dev->name); | |
1209 | netif_stop_queue(dev); | |
1210 | return 1; | |
1211 | } | |
1da177e4 | 1212 | |
c8aaea25 | 1213 | if (has_tiny_unaligned_frags(skb)) { |
364c6bad | 1214 | if (__skb_linearize(skb)) { |
c8aaea25 DF |
1215 | stats->tx_dropped++; |
1216 | printk(KERN_DEBUG "%s: failed to linearize tiny " | |
1217 | "unaligned fragment\n", dev->name); | |
1218 | return 1; | |
1da177e4 LT |
1219 | } |
1220 | } | |
f7ea3337 | 1221 | |
c8aaea25 | 1222 | spin_lock_irqsave(&mp->lock, flags); |
1da177e4 | 1223 | |
ff561eef DF |
1224 | eth_tx_submit_descs_for_skb(mp, skb); |
1225 | stats->tx_bytes = skb->len; | |
1da177e4 LT |
1226 | stats->tx_packets++; |
1227 | dev->trans_start = jiffies; | |
1228 | ||
c8aaea25 DF |
1229 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) |
1230 | netif_stop_queue(dev); | |
1231 | ||
1da177e4 LT |
1232 | spin_unlock_irqrestore(&mp->lock, flags); |
1233 | ||
1234 | return 0; /* success */ | |
1235 | } | |
1236 | ||
1237 | /* | |
1238 | * mv643xx_eth_get_stats | |
1239 | * | |
1240 | * Returns a pointer to the interface statistics. | |
1241 | * | |
1242 | * Input : dev - a pointer to the required interface | |
1243 | * | |
1244 | * Output : a pointer to the interface's statistics | |
1245 | */ | |
1246 | ||
1247 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) | |
1248 | { | |
1249 | struct mv643xx_private *mp = netdev_priv(dev); | |
1250 | ||
1251 | return &mp->stats; | |
1252 | } | |
1253 | ||
63c9e549 | 1254 | #ifdef CONFIG_NET_POLL_CONTROLLER |
63c9e549 DF |
1255 | static void mv643xx_netpoll(struct net_device *netdev) |
1256 | { | |
1257 | struct mv643xx_private *mp = netdev_priv(netdev); | |
c2e5b352 DF |
1258 | int port_num = mp->port_num; |
1259 | ||
7303fde8 | 1260 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL); |
c2e5b352 DF |
1261 | /* wait for previous write to complete */ |
1262 | mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
63c9e549 | 1263 | |
9da3b1ad | 1264 | mv643xx_eth_int_handler(netdev->irq, netdev); |
c2e5b352 | 1265 | |
7303fde8 | 1266 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL); |
63c9e549 DF |
1267 | } |
1268 | #endif | |
1269 | ||
d0412d96 JC |
1270 | static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, |
1271 | int speed, int duplex, | |
1272 | struct ethtool_cmd *cmd) | |
1273 | { | |
1274 | struct mv643xx_private *mp = netdev_priv(dev); | |
1275 | ||
1276 | memset(cmd, 0, sizeof(*cmd)); | |
1277 | ||
1278 | cmd->port = PORT_MII; | |
1279 | cmd->transceiver = XCVR_INTERNAL; | |
1280 | cmd->phy_address = phy_address; | |
1281 | ||
1282 | if (speed == 0) { | |
1283 | cmd->autoneg = AUTONEG_ENABLE; | |
1284 | /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */ | |
1285 | cmd->speed = SPEED_100; | |
1286 | cmd->advertising = ADVERTISED_10baseT_Half | | |
1287 | ADVERTISED_10baseT_Full | | |
1288 | ADVERTISED_100baseT_Half | | |
1289 | ADVERTISED_100baseT_Full; | |
1290 | if (mp->mii.supports_gmii) | |
1291 | cmd->advertising |= ADVERTISED_1000baseT_Full; | |
1292 | } else { | |
1293 | cmd->autoneg = AUTONEG_DISABLE; | |
1294 | cmd->speed = speed; | |
1295 | cmd->duplex = duplex; | |
1296 | } | |
1297 | } | |
1298 | ||
1da177e4 LT |
1299 | /*/ |
1300 | * mv643xx_eth_probe | |
1301 | * | |
1302 | * First function called after registering the network device. | |
1303 | * It's purpose is to initialize the device as an ethernet device, | |
1304 | * fill the ethernet device structure with pointers * to functions, | |
1305 | * and set the MAC address of the interface | |
1306 | * | |
1307 | * Input : struct device * | |
1308 | * Output : -ENOMEM if failed , 0 if success | |
1309 | */ | |
3ae5eaec | 1310 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 1311 | { |
1da177e4 | 1312 | struct mv643xx_eth_platform_data *pd; |
84dd619e | 1313 | int port_num; |
1da177e4 LT |
1314 | struct mv643xx_private *mp; |
1315 | struct net_device *dev; | |
1316 | u8 *p; | |
1317 | struct resource *res; | |
1318 | int err; | |
d0412d96 | 1319 | struct ethtool_cmd cmd; |
01999873 DF |
1320 | int duplex = DUPLEX_HALF; |
1321 | int speed = 0; /* default to auto-negotiation */ | |
1da177e4 | 1322 | |
84dd619e DF |
1323 | pd = pdev->dev.platform_data; |
1324 | if (pd == NULL) { | |
1325 | printk(KERN_ERR "No mv643xx_eth_platform_data\n"); | |
1326 | return -ENODEV; | |
1327 | } | |
1328 | ||
1da177e4 LT |
1329 | dev = alloc_etherdev(sizeof(struct mv643xx_private)); |
1330 | if (!dev) | |
1331 | return -ENOMEM; | |
1332 | ||
3ae5eaec | 1333 | platform_set_drvdata(pdev, dev); |
1da177e4 LT |
1334 | |
1335 | mp = netdev_priv(dev); | |
1336 | ||
1337 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1338 | BUG_ON(!res); | |
1339 | dev->irq = res->start; | |
1340 | ||
1da177e4 LT |
1341 | dev->open = mv643xx_eth_open; |
1342 | dev->stop = mv643xx_eth_stop; | |
1343 | dev->hard_start_xmit = mv643xx_eth_start_xmit; | |
1344 | dev->get_stats = mv643xx_eth_get_stats; | |
1345 | dev->set_mac_address = mv643xx_eth_set_mac_address; | |
1346 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; | |
1347 | ||
1348 | /* No need to Tx Timeout */ | |
1349 | dev->tx_timeout = mv643xx_eth_tx_timeout; | |
1350 | #ifdef MV643XX_NAPI | |
1351 | dev->poll = mv643xx_poll; | |
1352 | dev->weight = 64; | |
1353 | #endif | |
1354 | ||
63c9e549 DF |
1355 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1356 | dev->poll_controller = mv643xx_netpoll; | |
1357 | #endif | |
1358 | ||
1da177e4 LT |
1359 | dev->watchdog_timeo = 2 * HZ; |
1360 | dev->tx_queue_len = mp->tx_ring_size; | |
1361 | dev->base_addr = 0; | |
1362 | dev->change_mtu = mv643xx_eth_change_mtu; | |
d0412d96 | 1363 | dev->do_ioctl = mv643xx_eth_do_ioctl; |
1da177e4 LT |
1364 | SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); |
1365 | ||
1366 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
1367 | #ifdef MAX_SKB_FRAGS | |
1368 | /* | |
1369 | * Zero copy can only work if we use Discovery II memory. Else, we will | |
1370 | * have to map the buffers to ISA memory which is only 16 MB | |
1371 | */ | |
63890576 | 1372 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 LT |
1373 | #endif |
1374 | #endif | |
1375 | ||
1376 | /* Configure the timeout task */ | |
91c7c568 | 1377 | INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task); |
1da177e4 LT |
1378 | |
1379 | spin_lock_init(&mp->lock); | |
1380 | ||
fadac406 | 1381 | port_num = mp->port_num = pd->port_number; |
84dd619e | 1382 | |
1da177e4 LT |
1383 | /* set default config values */ |
1384 | eth_port_uc_addr_get(dev, dev->dev_addr); | |
1da177e4 LT |
1385 | mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE; |
1386 | mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; | |
1387 | ||
84dd619e DF |
1388 | if (is_valid_ether_addr(pd->mac_addr)) |
1389 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
1da177e4 | 1390 | |
84dd619e DF |
1391 | if (pd->phy_addr || pd->force_phy_addr) |
1392 | ethernet_phy_set(port_num, pd->phy_addr); | |
1da177e4 | 1393 | |
84dd619e DF |
1394 | if (pd->rx_queue_size) |
1395 | mp->rx_ring_size = pd->rx_queue_size; | |
1da177e4 | 1396 | |
84dd619e DF |
1397 | if (pd->tx_queue_size) |
1398 | mp->tx_ring_size = pd->tx_queue_size; | |
1da177e4 | 1399 | |
84dd619e DF |
1400 | if (pd->tx_sram_size) { |
1401 | mp->tx_sram_size = pd->tx_sram_size; | |
1402 | mp->tx_sram_addr = pd->tx_sram_addr; | |
1403 | } | |
01999873 | 1404 | |
84dd619e DF |
1405 | if (pd->rx_sram_size) { |
1406 | mp->rx_sram_size = pd->rx_sram_size; | |
1407 | mp->rx_sram_addr = pd->rx_sram_addr; | |
1da177e4 LT |
1408 | } |
1409 | ||
84dd619e DF |
1410 | duplex = pd->duplex; |
1411 | speed = pd->speed; | |
1412 | ||
c28a4f89 JC |
1413 | /* Hook up MII support for ethtool */ |
1414 | mp->mii.dev = dev; | |
1415 | mp->mii.mdio_read = mv643xx_mdio_read; | |
1416 | mp->mii.mdio_write = mv643xx_mdio_write; | |
1417 | mp->mii.phy_id = ethernet_phy_get(port_num); | |
1418 | mp->mii.phy_id_mask = 0x3f; | |
1419 | mp->mii.reg_num_mask = 0x1f; | |
1420 | ||
1da177e4 LT |
1421 | err = ethernet_phy_detect(port_num); |
1422 | if (err) { | |
1423 | pr_debug("MV643xx ethernet port %d: " | |
1424 | "No PHY detected at addr %d\n", | |
1425 | port_num, ethernet_phy_get(port_num)); | |
d0412d96 | 1426 | goto out; |
1da177e4 LT |
1427 | } |
1428 | ||
01999873 | 1429 | ethernet_phy_reset(port_num); |
c28a4f89 | 1430 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); |
d0412d96 JC |
1431 | mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); |
1432 | mv643xx_eth_update_pscr(dev, &cmd); | |
1433 | mv643xx_set_settings(dev, &cmd); | |
c28a4f89 | 1434 | |
b0b8dab2 OH |
1435 | SET_MODULE_OWNER(dev); |
1436 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1da177e4 LT |
1437 | err = register_netdev(dev); |
1438 | if (err) | |
1439 | goto out; | |
1440 | ||
1441 | p = dev->dev_addr; | |
1442 | printk(KERN_NOTICE | |
1443 | "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", | |
1444 | dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]); | |
1445 | ||
1446 | if (dev->features & NETIF_F_SG) | |
1447 | printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); | |
1448 | ||
1449 | if (dev->features & NETIF_F_IP_CSUM) | |
1450 | printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", | |
1451 | dev->name); | |
1452 | ||
1453 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
1454 | printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); | |
1455 | #endif | |
1456 | ||
1457 | #ifdef MV643XX_COAL | |
1458 | printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", | |
1459 | dev->name); | |
1460 | #endif | |
1461 | ||
1462 | #ifdef MV643XX_NAPI | |
1463 | printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); | |
1464 | #endif | |
1465 | ||
b1529871 ND |
1466 | if (mp->tx_sram_size > 0) |
1467 | printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); | |
1468 | ||
1da177e4 LT |
1469 | return 0; |
1470 | ||
1471 | out: | |
1472 | free_netdev(dev); | |
1473 | ||
1474 | return err; | |
1475 | } | |
1476 | ||
3ae5eaec | 1477 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 1478 | { |
3ae5eaec | 1479 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 LT |
1480 | |
1481 | unregister_netdev(dev); | |
1482 | flush_scheduled_work(); | |
1483 | ||
1484 | free_netdev(dev); | |
3ae5eaec | 1485 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
1486 | return 0; |
1487 | } | |
1488 | ||
3ae5eaec | 1489 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
1da177e4 | 1490 | { |
1da177e4 LT |
1491 | struct resource *res; |
1492 | ||
1493 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); | |
1494 | ||
1495 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1496 | if (res == NULL) | |
1497 | return -ENODEV; | |
1498 | ||
1499 | mv643xx_eth_shared_base = ioremap(res->start, | |
1500 | MV643XX_ETH_SHARED_REGS_SIZE); | |
1501 | if (mv643xx_eth_shared_base == NULL) | |
1502 | return -ENOMEM; | |
1503 | ||
1504 | return 0; | |
1505 | ||
1506 | } | |
1507 | ||
3ae5eaec | 1508 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) |
1da177e4 LT |
1509 | { |
1510 | iounmap(mv643xx_eth_shared_base); | |
1511 | mv643xx_eth_shared_base = NULL; | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
d57ab6fd DF |
1516 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
1517 | { | |
1518 | struct net_device *dev = platform_get_drvdata(pdev); | |
1519 | struct mv643xx_private *mp = netdev_priv(dev); | |
1520 | unsigned int port_num = mp->port_num; | |
1521 | ||
1522 | /* Mask all interrupts on ethernet port */ | |
1523 | mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0); | |
1524 | mv_read (MV643XX_ETH_INTERRUPT_MASK_REG(port_num)); | |
1525 | ||
1526 | eth_port_reset(port_num); | |
1527 | } | |
1528 | ||
3ae5eaec | 1529 | static struct platform_driver mv643xx_eth_driver = { |
1da177e4 LT |
1530 | .probe = mv643xx_eth_probe, |
1531 | .remove = mv643xx_eth_remove, | |
d57ab6fd | 1532 | .shutdown = mv643xx_eth_shutdown, |
3ae5eaec RK |
1533 | .driver = { |
1534 | .name = MV643XX_ETH_NAME, | |
1535 | }, | |
1da177e4 LT |
1536 | }; |
1537 | ||
3ae5eaec | 1538 | static struct platform_driver mv643xx_eth_shared_driver = { |
1da177e4 LT |
1539 | .probe = mv643xx_eth_shared_probe, |
1540 | .remove = mv643xx_eth_shared_remove, | |
3ae5eaec RK |
1541 | .driver = { |
1542 | .name = MV643XX_ETH_SHARED_NAME, | |
1543 | }, | |
1da177e4 LT |
1544 | }; |
1545 | ||
1546 | /* | |
1547 | * mv643xx_init_module | |
1548 | * | |
1549 | * Registers the network drivers into the Linux kernel | |
1550 | * | |
1551 | * Input : N/A | |
1552 | * | |
1553 | * Output : N/A | |
1554 | */ | |
1555 | static int __init mv643xx_init_module(void) | |
1556 | { | |
1557 | int rc; | |
1558 | ||
3ae5eaec | 1559 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
1da177e4 | 1560 | if (!rc) { |
3ae5eaec | 1561 | rc = platform_driver_register(&mv643xx_eth_driver); |
1da177e4 | 1562 | if (rc) |
3ae5eaec | 1563 | platform_driver_unregister(&mv643xx_eth_shared_driver); |
1da177e4 LT |
1564 | } |
1565 | return rc; | |
1566 | } | |
1567 | ||
1568 | /* | |
1569 | * mv643xx_cleanup_module | |
1570 | * | |
1571 | * Registers the network drivers into the Linux kernel | |
1572 | * | |
1573 | * Input : N/A | |
1574 | * | |
1575 | * Output : N/A | |
1576 | */ | |
1577 | static void __exit mv643xx_cleanup_module(void) | |
1578 | { | |
3ae5eaec RK |
1579 | platform_driver_unregister(&mv643xx_eth_driver); |
1580 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
1da177e4 LT |
1581 | } |
1582 | ||
1583 | module_init(mv643xx_init_module); | |
1584 | module_exit(mv643xx_cleanup_module); | |
1585 | ||
1586 | MODULE_LICENSE("GPL"); | |
1587 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | |
1588 | " and Dale Farnsworth"); | |
1589 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | |
1590 | ||
1591 | /* | |
1592 | * The second part is the low level driver of the gigE ethernet ports. | |
1593 | */ | |
1594 | ||
1595 | /* | |
1596 | * Marvell's Gigabit Ethernet controller low level driver | |
1597 | * | |
1598 | * DESCRIPTION: | |
1599 | * This file introduce low level API to Marvell's Gigabit Ethernet | |
1600 | * controller. This Gigabit Ethernet Controller driver API controls | |
1601 | * 1) Operations (i.e. port init, start, reset etc'). | |
1602 | * 2) Data flow (i.e. port send, receive etc'). | |
1603 | * Each Gigabit Ethernet port is controlled via | |
1604 | * struct mv643xx_private. | |
1605 | * This struct includes user configuration information as well as | |
1606 | * driver internal data needed for its operations. | |
1607 | * | |
1608 | * Supported Features: | |
1609 | * - This low level driver is OS independent. Allocating memory for | |
1610 | * the descriptor rings and buffers are not within the scope of | |
1611 | * this driver. | |
1612 | * - The user is free from Rx/Tx queue managing. | |
1613 | * - This low level driver introduce functionality API that enable | |
1614 | * the to operate Marvell's Gigabit Ethernet Controller in a | |
1615 | * convenient way. | |
1616 | * - Simple Gigabit Ethernet port operation API. | |
1617 | * - Simple Gigabit Ethernet port data flow API. | |
1618 | * - Data flow and operation API support per queue functionality. | |
1619 | * - Support cached descriptors for better performance. | |
1620 | * - Enable access to all four DRAM banks and internal SRAM memory | |
1621 | * spaces. | |
1622 | * - PHY access and control API. | |
1623 | * - Port control register configuration API. | |
1624 | * - Full control over Unicast and Multicast MAC configurations. | |
1625 | * | |
1626 | * Operation flow: | |
1627 | * | |
1628 | * Initialization phase | |
1629 | * This phase complete the initialization of the the | |
1630 | * mv643xx_private struct. | |
1631 | * User information regarding port configuration has to be set | |
1632 | * prior to calling the port initialization routine. | |
1633 | * | |
1634 | * In this phase any port Tx/Rx activity is halted, MIB counters | |
1635 | * are cleared, PHY address is set according to user parameter and | |
1636 | * access to DRAM and internal SRAM memory spaces. | |
1637 | * | |
1638 | * Driver ring initialization | |
1639 | * Allocating memory for the descriptor rings and buffers is not | |
1640 | * within the scope of this driver. Thus, the user is required to | |
1641 | * allocate memory for the descriptors ring and buffers. Those | |
1642 | * memory parameters are used by the Rx and Tx ring initialization | |
1643 | * routines in order to curve the descriptor linked list in a form | |
1644 | * of a ring. | |
1645 | * Note: Pay special attention to alignment issues when using | |
1646 | * cached descriptors/buffers. In this phase the driver store | |
1647 | * information in the mv643xx_private struct regarding each queue | |
1648 | * ring. | |
1649 | * | |
1650 | * Driver start | |
1651 | * This phase prepares the Ethernet port for Rx and Tx activity. | |
1652 | * It uses the information stored in the mv643xx_private struct to | |
1653 | * initialize the various port registers. | |
1654 | * | |
1655 | * Data flow: | |
1656 | * All packet references to/from the driver are done using | |
1657 | * struct pkt_info. | |
1658 | * This struct is a unified struct used with Rx and Tx operations. | |
1659 | * This way the user is not required to be familiar with neither | |
1660 | * Tx nor Rx descriptors structures. | |
1661 | * The driver's descriptors rings are management by indexes. | |
1662 | * Those indexes controls the ring resources and used to indicate | |
1663 | * a SW resource error: | |
1664 | * 'current' | |
1665 | * This index points to the current available resource for use. For | |
1666 | * example in Rx process this index will point to the descriptor | |
1667 | * that will be passed to the user upon calling the receive | |
1668 | * routine. In Tx process, this index will point to the descriptor | |
1669 | * that will be assigned with the user packet info and transmitted. | |
1670 | * 'used' | |
1671 | * This index points to the descriptor that need to restore its | |
1672 | * resources. For example in Rx process, using the Rx buffer return | |
1673 | * API will attach the buffer returned in packet info to the | |
1674 | * descriptor pointed by 'used'. In Tx process, using the Tx | |
1675 | * descriptor return will merely return the user packet info with | |
1676 | * the command status of the transmitted buffer pointed by the | |
1677 | * 'used' index. Nevertheless, it is essential to use this routine | |
1678 | * to update the 'used' index. | |
1679 | * 'first' | |
1680 | * This index supports Tx Scatter-Gather. It points to the first | |
1681 | * descriptor of a packet assembled of multiple buffers. For | |
1682 | * example when in middle of Such packet we have a Tx resource | |
1683 | * error the 'curr' index get the value of 'first' to indicate | |
1684 | * that the ring returned to its state before trying to transmit | |
1685 | * this packet. | |
1686 | * | |
1687 | * Receive operation: | |
1688 | * The eth_port_receive API set the packet information struct, | |
1689 | * passed by the caller, with received information from the | |
1690 | * 'current' SDMA descriptor. | |
1691 | * It is the user responsibility to return this resource back | |
1692 | * to the Rx descriptor ring to enable the reuse of this source. | |
1693 | * Return Rx resource is done using the eth_rx_return_buff API. | |
1694 | * | |
1da177e4 LT |
1695 | * Prior to calling the initialization routine eth_port_init() the user |
1696 | * must set the following fields under mv643xx_private struct: | |
1697 | * port_num User Ethernet port number. | |
1da177e4 LT |
1698 | * port_config User port configuration value. |
1699 | * port_config_extend User port config extend value. | |
1700 | * port_sdma_config User port SDMA config value. | |
1701 | * port_serial_control User port serial control value. | |
1702 | * | |
1703 | * This driver data flow is done using the struct pkt_info which | |
1704 | * is a unified struct for Rx and Tx operations: | |
1705 | * | |
1706 | * byte_cnt Tx/Rx descriptor buffer byte count. | |
1707 | * l4i_chk CPU provided TCP Checksum. For Tx operation | |
1708 | * only. | |
1709 | * cmd_sts Tx/Rx descriptor command status. | |
1710 | * buf_ptr Tx/Rx descriptor buffer pointer. | |
1711 | * return_info Tx/Rx user resource return information. | |
1712 | */ | |
1713 | ||
1da177e4 LT |
1714 | /* PHY routines */ |
1715 | static int ethernet_phy_get(unsigned int eth_port_num); | |
1716 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr); | |
1717 | ||
1718 | /* Ethernet Port routines */ | |
cf4086c7 | 1719 | static void eth_port_set_filter_table_entry(int table, unsigned char entry); |
1da177e4 LT |
1720 | |
1721 | /* | |
1722 | * eth_port_init - Initialize the Ethernet port driver | |
1723 | * | |
1724 | * DESCRIPTION: | |
1725 | * This function prepares the ethernet port to start its activity: | |
1726 | * 1) Completes the ethernet port driver struct initialization toward port | |
1727 | * start routine. | |
1728 | * 2) Resets the device to a quiescent state in case of warm reboot. | |
1729 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. | |
1730 | * 4) Clean MAC tables. The reset status of those tables is unknown. | |
1731 | * 5) Set PHY address. | |
1732 | * Note: Call this routine prior to eth_port_start routine and after | |
1733 | * setting user values in the user fields of Ethernet port control | |
1734 | * struct. | |
1735 | * | |
1736 | * INPUT: | |
1737 | * struct mv643xx_private *mp Ethernet port control struct | |
1738 | * | |
1739 | * OUTPUT: | |
1740 | * See description. | |
1741 | * | |
1742 | * RETURN: | |
1743 | * None. | |
1744 | */ | |
1745 | static void eth_port_init(struct mv643xx_private *mp) | |
1746 | { | |
1da177e4 | 1747 | mp->rx_resource_err = 0; |
1da177e4 LT |
1748 | |
1749 | eth_port_reset(mp->port_num); | |
1750 | ||
1751 | eth_port_init_mac_tables(mp->port_num); | |
1da177e4 LT |
1752 | } |
1753 | ||
1754 | /* | |
1755 | * eth_port_start - Start the Ethernet port activity. | |
1756 | * | |
1757 | * DESCRIPTION: | |
1758 | * This routine prepares the Ethernet port for Rx and Tx activity: | |
1759 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that | |
1760 | * has been initialized a descriptor's ring (using | |
1761 | * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) | |
1762 | * 2. Initialize and enable the Ethernet configuration port by writing to | |
1763 | * the port's configuration and command registers. | |
1764 | * 3. Initialize and enable the SDMA by writing to the SDMA's | |
1765 | * configuration and command registers. After completing these steps, | |
1766 | * the ethernet port SDMA can starts to perform Rx and Tx activities. | |
1767 | * | |
1768 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior | |
1769 | * to calling this function (use ether_init_tx_desc_ring for Tx queues | |
1770 | * and ether_init_rx_desc_ring for Rx queues). | |
1771 | * | |
1772 | * INPUT: | |
ed9b5d45 | 1773 | * dev - a pointer to the required interface |
1da177e4 LT |
1774 | * |
1775 | * OUTPUT: | |
1776 | * Ethernet port is ready to receive and transmit. | |
1777 | * | |
1778 | * RETURN: | |
1779 | * None. | |
1780 | */ | |
ed9b5d45 | 1781 | static void eth_port_start(struct net_device *dev) |
1da177e4 | 1782 | { |
ed9b5d45 | 1783 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 LT |
1784 | unsigned int port_num = mp->port_num; |
1785 | int tx_curr_desc, rx_curr_desc; | |
d0412d96 JC |
1786 | u32 pscr; |
1787 | struct ethtool_cmd ethtool_cmd; | |
1da177e4 LT |
1788 | |
1789 | /* Assignment of Tx CTRP of given queue */ | |
1790 | tx_curr_desc = mp->tx_curr_desc_q; | |
1791 | mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num), | |
1792 | (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); | |
1793 | ||
1794 | /* Assignment of Rx CRDP of given queue */ | |
1795 | rx_curr_desc = mp->rx_curr_desc_q; | |
1796 | mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num), | |
1797 | (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); | |
1798 | ||
1799 | /* Add the assigned Ethernet address to the port's address table */ | |
ed9b5d45 | 1800 | eth_port_uc_addr_set(port_num, dev->dev_addr); |
1da177e4 LT |
1801 | |
1802 | /* Assign port configuration and command. */ | |
01999873 DF |
1803 | mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), |
1804 | MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE); | |
1805 | ||
1806 | mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num), | |
1807 | MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE); | |
1da177e4 | 1808 | |
d0412d96 | 1809 | pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); |
01999873 DF |
1810 | |
1811 | pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS); | |
d0412d96 | 1812 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); |
1da177e4 | 1813 | |
d0412d96 JC |
1814 | pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | |
1815 | MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII | | |
1816 | MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX | | |
1817 | MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | | |
1818 | MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED; | |
1da177e4 | 1819 | |
d0412d96 | 1820 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); |
1da177e4 | 1821 | |
d0412d96 JC |
1822 | pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE; |
1823 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr); | |
1da177e4 LT |
1824 | |
1825 | /* Assign port SDMA configuration */ | |
01999873 DF |
1826 | mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num), |
1827 | MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE); | |
1da177e4 LT |
1828 | |
1829 | /* Enable port Rx. */ | |
ff561eef | 1830 | mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED); |
8f543718 DF |
1831 | |
1832 | /* Disable port bandwidth limits by clearing MTU register */ | |
1833 | mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0); | |
d0412d96 JC |
1834 | |
1835 | /* save phy settings across reset */ | |
1836 | mv643xx_get_settings(dev, ðtool_cmd); | |
1837 | ethernet_phy_reset(mp->port_num); | |
1838 | mv643xx_set_settings(dev, ðtool_cmd); | |
1da177e4 LT |
1839 | } |
1840 | ||
1841 | /* | |
1842 | * eth_port_uc_addr_set - This function Set the port Unicast address. | |
1843 | * | |
1844 | * DESCRIPTION: | |
1845 | * This function Set the port Ethernet MAC address. | |
1846 | * | |
1847 | * INPUT: | |
1848 | * unsigned int eth_port_num Port number. | |
1849 | * char * p_addr Address to be set | |
1850 | * | |
1851 | * OUTPUT: | |
cf4086c7 DF |
1852 | * Set MAC address low and high registers. also calls |
1853 | * eth_port_set_filter_table_entry() to set the unicast | |
1854 | * table with the proper information. | |
1da177e4 LT |
1855 | * |
1856 | * RETURN: | |
1857 | * N/A. | |
1858 | * | |
1859 | */ | |
1860 | static void eth_port_uc_addr_set(unsigned int eth_port_num, | |
1861 | unsigned char *p_addr) | |
1862 | { | |
1863 | unsigned int mac_h; | |
1864 | unsigned int mac_l; | |
cf4086c7 | 1865 | int table; |
1da177e4 LT |
1866 | |
1867 | mac_l = (p_addr[4] << 8) | (p_addr[5]); | |
1868 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | | |
1869 | (p_addr[3] << 0); | |
1870 | ||
1871 | mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l); | |
1872 | mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h); | |
1873 | ||
1874 | /* Accept frames of this address */ | |
cf4086c7 DF |
1875 | table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num); |
1876 | eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f); | |
1da177e4 LT |
1877 | } |
1878 | ||
1879 | /* | |
1880 | * eth_port_uc_addr_get - This function retrieves the port Unicast address | |
1881 | * (MAC address) from the ethernet hw registers. | |
1882 | * | |
1883 | * DESCRIPTION: | |
1884 | * This function retrieves the port Ethernet MAC address. | |
1885 | * | |
1886 | * INPUT: | |
1887 | * unsigned int eth_port_num Port number. | |
1888 | * char *MacAddr pointer where the MAC address is stored | |
1889 | * | |
1890 | * OUTPUT: | |
1891 | * Copy the MAC address to the location pointed to by MacAddr | |
1892 | * | |
1893 | * RETURN: | |
1894 | * N/A. | |
1895 | * | |
1896 | */ | |
1897 | static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr) | |
1898 | { | |
1899 | struct mv643xx_private *mp = netdev_priv(dev); | |
1900 | unsigned int mac_h; | |
1901 | unsigned int mac_l; | |
1902 | ||
1903 | mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num)); | |
1904 | mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num)); | |
1905 | ||
1906 | p_addr[0] = (mac_h >> 24) & 0xff; | |
1907 | p_addr[1] = (mac_h >> 16) & 0xff; | |
1908 | p_addr[2] = (mac_h >> 8) & 0xff; | |
1909 | p_addr[3] = mac_h & 0xff; | |
1910 | p_addr[4] = (mac_l >> 8) & 0xff; | |
1911 | p_addr[5] = mac_l & 0xff; | |
1912 | } | |
1913 | ||
16e03018 DF |
1914 | /* |
1915 | * The entries in each table are indexed by a hash of a packet's MAC | |
1916 | * address. One bit in each entry determines whether the packet is | |
1917 | * accepted. There are 4 entries (each 8 bits wide) in each register | |
1918 | * of the table. The bits in each entry are defined as follows: | |
1919 | * 0 Accept=1, Drop=0 | |
1920 | * 3-1 Queue (ETH_Q0=0) | |
1921 | * 7-4 Reserved = 0; | |
1922 | */ | |
1923 | static void eth_port_set_filter_table_entry(int table, unsigned char entry) | |
1924 | { | |
1925 | unsigned int table_reg; | |
1926 | unsigned int tbl_offset; | |
1927 | unsigned int reg_offset; | |
1928 | ||
1929 | tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ | |
1930 | reg_offset = entry % 4; /* Entry offset within the register */ | |
1931 | ||
1932 | /* Set "accepts frame bit" at specified table entry */ | |
1933 | table_reg = mv_read(table + tbl_offset); | |
1934 | table_reg |= 0x01 << (8 * reg_offset); | |
1935 | mv_write(table + tbl_offset, table_reg); | |
1936 | } | |
1937 | ||
1938 | /* | |
1939 | * eth_port_mc_addr - Multicast address settings. | |
1940 | * | |
1941 | * The MV device supports multicast using two tables: | |
1942 | * 1) Special Multicast Table for MAC addresses of the form | |
1943 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). | |
1944 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1945 | * Table entries in the DA-Filter table. | |
1946 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit | |
1947 | * is used as an index to the Other Multicast Table entries in the | |
1948 | * DA-Filter table. This function calculates the CRC-8bit value. | |
1949 | * In either case, eth_port_set_filter_table_entry() is then called | |
1950 | * to set to set the actual table entry. | |
1951 | */ | |
1952 | static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr) | |
1953 | { | |
1954 | unsigned int mac_h; | |
1955 | unsigned int mac_l; | |
1956 | unsigned char crc_result = 0; | |
1957 | int table; | |
1958 | int mac_array[48]; | |
1959 | int crc[8]; | |
1960 | int i; | |
1961 | ||
1962 | if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && | |
1963 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { | |
1964 | table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE | |
1965 | (eth_port_num); | |
1966 | eth_port_set_filter_table_entry(table, p_addr[5]); | |
1967 | return; | |
1968 | } | |
1969 | ||
1970 | /* Calculate CRC-8 out of the given address */ | |
1971 | mac_h = (p_addr[0] << 8) | (p_addr[1]); | |
1972 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | | |
1973 | (p_addr[4] << 8) | (p_addr[5] << 0); | |
1974 | ||
1975 | for (i = 0; i < 32; i++) | |
1976 | mac_array[i] = (mac_l >> i) & 0x1; | |
1977 | for (i = 32; i < 48; i++) | |
1978 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; | |
1979 | ||
1980 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ | |
1981 | mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ | |
1982 | mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ | |
1983 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ | |
1984 | mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; | |
1985 | ||
1986 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ | |
1987 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ | |
1988 | mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ | |
1989 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ | |
1990 | mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ | |
1991 | mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ | |
1992 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; | |
1993 | ||
1994 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ | |
1995 | mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ | |
1996 | mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ | |
1997 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ | |
1998 | mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ | |
1999 | mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; | |
2000 | ||
2001 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ | |
2002 | mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ | |
2003 | mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ | |
2004 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ | |
2005 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ | |
2006 | mac_array[3] ^ mac_array[2] ^ mac_array[1]; | |
2007 | ||
2008 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ | |
2009 | mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ | |
2010 | mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ | |
2011 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ | |
2012 | mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ | |
2013 | mac_array[3] ^ mac_array[2]; | |
2014 | ||
2015 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ | |
2016 | mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ | |
2017 | mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ | |
2018 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ | |
2019 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ | |
2020 | mac_array[4] ^ mac_array[3]; | |
2021 | ||
2022 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ | |
2023 | mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ | |
2024 | mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ | |
2025 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ | |
2026 | mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ | |
2027 | mac_array[4]; | |
2028 | ||
2029 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ | |
2030 | mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ | |
2031 | mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ | |
2032 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ | |
2033 | mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; | |
2034 | ||
2035 | for (i = 0; i < 8; i++) | |
2036 | crc_result = crc_result | (crc[i] << i); | |
2037 | ||
2038 | table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num); | |
2039 | eth_port_set_filter_table_entry(table, crc_result); | |
2040 | } | |
2041 | ||
2042 | /* | |
2043 | * Set the entire multicast list based on dev->mc_list. | |
2044 | */ | |
2045 | static void eth_port_set_multicast_list(struct net_device *dev) | |
2046 | { | |
2047 | ||
2048 | struct dev_mc_list *mc_list; | |
2049 | int i; | |
2050 | int table_index; | |
2051 | struct mv643xx_private *mp = netdev_priv(dev); | |
2052 | unsigned int eth_port_num = mp->port_num; | |
2053 | ||
2054 | /* If the device is in promiscuous mode or in all multicast mode, | |
2055 | * we will fully populate both multicast tables with accept. | |
2056 | * This is guaranteed to yield a match on all multicast addresses... | |
2057 | */ | |
2058 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { | |
2059 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
b4de9051 DF |
2060 | /* Set all entries in DA filter special multicast |
2061 | * table (Ex_dFSMT) | |
2062 | * Set for ETH_Q0 for now | |
2063 | * Bits | |
2064 | * 0 Accept=1, Drop=0 | |
2065 | * 3-1 Queue ETH_Q0=0 | |
2066 | * 7-4 Reserved = 0; | |
2067 | */ | |
2068 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); | |
2069 | ||
2070 | /* Set all entries in DA filter other multicast | |
2071 | * table (Ex_dFOMT) | |
2072 | * Set for ETH_Q0 for now | |
2073 | * Bits | |
2074 | * 0 Accept=1, Drop=0 | |
2075 | * 3-1 Queue ETH_Q0=0 | |
2076 | * 7-4 Reserved = 0; | |
2077 | */ | |
2078 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101); | |
2079 | } | |
16e03018 DF |
2080 | return; |
2081 | } | |
2082 | ||
2083 | /* We will clear out multicast tables every time we get the list. | |
2084 | * Then add the entire new list... | |
2085 | */ | |
2086 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2087 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
2088 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE | |
2089 | (eth_port_num) + table_index, 0); | |
2090 | ||
2091 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
2092 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE | |
2093 | (eth_port_num) + table_index, 0); | |
2094 | } | |
2095 | ||
2096 | /* Get pointer to net_device multicast list and add each one... */ | |
2097 | for (i = 0, mc_list = dev->mc_list; | |
2098 | (i < 256) && (mc_list != NULL) && (i < dev->mc_count); | |
2099 | i++, mc_list = mc_list->next) | |
2100 | if (mc_list->dmi_addrlen == 6) | |
2101 | eth_port_mc_addr(eth_port_num, mc_list->dmi_addr); | |
2102 | } | |
2103 | ||
1da177e4 LT |
2104 | /* |
2105 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables | |
2106 | * | |
2107 | * DESCRIPTION: | |
2108 | * Go through all the DA filter tables (Unicast, Special Multicast & | |
2109 | * Other Multicast) and set each entry to 0. | |
2110 | * | |
2111 | * INPUT: | |
2112 | * unsigned int eth_port_num Ethernet Port number. | |
2113 | * | |
2114 | * OUTPUT: | |
2115 | * Multicast and Unicast packets are rejected. | |
2116 | * | |
2117 | * RETURN: | |
2118 | * None. | |
2119 | */ | |
2120 | static void eth_port_init_mac_tables(unsigned int eth_port_num) | |
2121 | { | |
2122 | int table_index; | |
2123 | ||
2124 | /* Clear DA filter unicast table (Ex_dFUT) */ | |
2125 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
cf4086c7 DF |
2126 | mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE |
2127 | (eth_port_num) + table_index, 0); | |
1da177e4 LT |
2128 | |
2129 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2130 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
16e03018 DF |
2131 | mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE |
2132 | (eth_port_num) + table_index, 0); | |
1da177e4 | 2133 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
16e03018 DF |
2134 | mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE |
2135 | (eth_port_num) + table_index, 0); | |
1da177e4 LT |
2136 | } |
2137 | } | |
2138 | ||
2139 | /* | |
2140 | * eth_clear_mib_counters - Clear all MIB counters | |
2141 | * | |
2142 | * DESCRIPTION: | |
2143 | * This function clears all MIB counters of a specific ethernet port. | |
2144 | * A read from the MIB counter will reset the counter. | |
2145 | * | |
2146 | * INPUT: | |
2147 | * unsigned int eth_port_num Ethernet Port number. | |
2148 | * | |
2149 | * OUTPUT: | |
2150 | * After reading all MIB counters, the counters resets. | |
2151 | * | |
2152 | * RETURN: | |
2153 | * MIB counter value. | |
2154 | * | |
2155 | */ | |
2156 | static void eth_clear_mib_counters(unsigned int eth_port_num) | |
2157 | { | |
2158 | int i; | |
2159 | ||
2160 | /* Perform dummy reads from MIB counters */ | |
2161 | for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; | |
2162 | i += 4) | |
2163 | mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i); | |
2164 | } | |
2165 | ||
2166 | static inline u32 read_mib(struct mv643xx_private *mp, int offset) | |
2167 | { | |
2168 | return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset); | |
2169 | } | |
2170 | ||
2171 | static void eth_update_mib_counters(struct mv643xx_private *mp) | |
2172 | { | |
2173 | struct mv643xx_mib_counters *p = &mp->mib_counters; | |
2174 | int offset; | |
2175 | ||
2176 | p->good_octets_received += | |
2177 | read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); | |
2178 | p->good_octets_received += | |
2179 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32; | |
2180 | ||
2181 | for (offset = ETH_MIB_BAD_OCTETS_RECEIVED; | |
2182 | offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS; | |
2183 | offset += 4) | |
70fbf327 | 2184 | *(u32 *)((char *)p + offset) += read_mib(mp, offset); |
1da177e4 LT |
2185 | |
2186 | p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW); | |
2187 | p->good_octets_sent += | |
2188 | (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32; | |
2189 | ||
2190 | for (offset = ETH_MIB_GOOD_FRAMES_SENT; | |
2191 | offset <= ETH_MIB_LATE_COLLISION; | |
2192 | offset += 4) | |
70fbf327 | 2193 | *(u32 *)((char *)p + offset) += read_mib(mp, offset); |
1da177e4 LT |
2194 | } |
2195 | ||
2196 | /* | |
2197 | * ethernet_phy_detect - Detect whether a phy is present | |
2198 | * | |
2199 | * DESCRIPTION: | |
2200 | * This function tests whether there is a PHY present on | |
2201 | * the specified port. | |
2202 | * | |
2203 | * INPUT: | |
2204 | * unsigned int eth_port_num Ethernet Port number. | |
2205 | * | |
2206 | * OUTPUT: | |
2207 | * None | |
2208 | * | |
2209 | * RETURN: | |
2210 | * 0 on success | |
2211 | * -ENODEV on failure | |
2212 | * | |
2213 | */ | |
2214 | static int ethernet_phy_detect(unsigned int port_num) | |
2215 | { | |
2216 | unsigned int phy_reg_data0; | |
2217 | int auto_neg; | |
2218 | ||
2219 | eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); | |
2220 | auto_neg = phy_reg_data0 & 0x1000; | |
2221 | phy_reg_data0 ^= 0x1000; /* invert auto_neg */ | |
2222 | eth_port_write_smi_reg(port_num, 0, phy_reg_data0); | |
2223 | ||
2224 | eth_port_read_smi_reg(port_num, 0, &phy_reg_data0); | |
2225 | if ((phy_reg_data0 & 0x1000) == auto_neg) | |
2226 | return -ENODEV; /* change didn't take */ | |
2227 | ||
2228 | phy_reg_data0 ^= 0x1000; | |
2229 | eth_port_write_smi_reg(port_num, 0, phy_reg_data0); | |
2230 | return 0; | |
2231 | } | |
2232 | ||
2233 | /* | |
2234 | * ethernet_phy_get - Get the ethernet port PHY address. | |
2235 | * | |
2236 | * DESCRIPTION: | |
2237 | * This routine returns the given ethernet port PHY address. | |
2238 | * | |
2239 | * INPUT: | |
2240 | * unsigned int eth_port_num Ethernet Port number. | |
2241 | * | |
2242 | * OUTPUT: | |
2243 | * None. | |
2244 | * | |
2245 | * RETURN: | |
2246 | * PHY address. | |
2247 | * | |
2248 | */ | |
2249 | static int ethernet_phy_get(unsigned int eth_port_num) | |
2250 | { | |
2251 | unsigned int reg_data; | |
2252 | ||
2253 | reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); | |
2254 | ||
2255 | return ((reg_data >> (5 * eth_port_num)) & 0x1f); | |
2256 | } | |
2257 | ||
2258 | /* | |
2259 | * ethernet_phy_set - Set the ethernet port PHY address. | |
2260 | * | |
2261 | * DESCRIPTION: | |
2262 | * This routine sets the given ethernet port PHY address. | |
2263 | * | |
2264 | * INPUT: | |
2265 | * unsigned int eth_port_num Ethernet Port number. | |
2266 | * int phy_addr PHY address. | |
2267 | * | |
2268 | * OUTPUT: | |
2269 | * None. | |
2270 | * | |
2271 | * RETURN: | |
2272 | * None. | |
2273 | * | |
2274 | */ | |
2275 | static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr) | |
2276 | { | |
2277 | u32 reg_data; | |
2278 | int addr_shift = 5 * eth_port_num; | |
2279 | ||
2280 | reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG); | |
2281 | reg_data &= ~(0x1f << addr_shift); | |
2282 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
2283 | mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data); | |
2284 | } | |
2285 | ||
2286 | /* | |
2287 | * ethernet_phy_reset - Reset Ethernet port PHY. | |
2288 | * | |
2289 | * DESCRIPTION: | |
2290 | * This routine utilizes the SMI interface to reset the ethernet port PHY. | |
2291 | * | |
2292 | * INPUT: | |
2293 | * unsigned int eth_port_num Ethernet Port number. | |
2294 | * | |
2295 | * OUTPUT: | |
2296 | * The PHY is reset. | |
2297 | * | |
2298 | * RETURN: | |
2299 | * None. | |
2300 | * | |
2301 | */ | |
2302 | static void ethernet_phy_reset(unsigned int eth_port_num) | |
2303 | { | |
2304 | unsigned int phy_reg_data; | |
2305 | ||
2306 | /* Reset the PHY */ | |
2307 | eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data); | |
2308 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ | |
2309 | eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data); | |
d0412d96 JC |
2310 | |
2311 | /* wait for PHY to come out of reset */ | |
2312 | do { | |
2313 | udelay(1); | |
2314 | eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data); | |
2315 | } while (phy_reg_data & 0x8000); | |
1da177e4 LT |
2316 | } |
2317 | ||
9f8dd319 | 2318 | static void mv643xx_eth_port_enable_tx(unsigned int port_num, |
12a87c64 | 2319 | unsigned int queues) |
9f8dd319 | 2320 | { |
12a87c64 | 2321 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues); |
9f8dd319 DF |
2322 | } |
2323 | ||
2324 | static void mv643xx_eth_port_enable_rx(unsigned int port_num, | |
12a87c64 | 2325 | unsigned int queues) |
9f8dd319 | 2326 | { |
12a87c64 | 2327 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues); |
9f8dd319 DF |
2328 | } |
2329 | ||
2330 | static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num) | |
2331 | { | |
12a87c64 | 2332 | u32 queues; |
9f8dd319 DF |
2333 | |
2334 | /* Stop Tx port activity. Check port Tx activity. */ | |
12a87c64 | 2335 | queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)) |
9f8dd319 | 2336 | & 0xFF; |
12a87c64 DF |
2337 | if (queues) { |
2338 | /* Issue stop command for active queues only */ | |
9f8dd319 | 2339 | mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), |
12a87c64 | 2340 | (queues << 8)); |
9f8dd319 DF |
2341 | |
2342 | /* Wait for all Tx activity to terminate. */ | |
2343 | /* Check port cause register that all Tx queues are stopped */ | |
2344 | while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num)) | |
2345 | & 0xFF) | |
2346 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2347 | ||
2348 | /* Wait for Tx FIFO to empty */ | |
2349 | while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) & | |
2350 | ETH_PORT_TX_FIFO_EMPTY) | |
2351 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2352 | } | |
2353 | ||
12a87c64 | 2354 | return queues; |
9f8dd319 DF |
2355 | } |
2356 | ||
2357 | static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num) | |
2358 | { | |
12a87c64 | 2359 | u32 queues; |
9f8dd319 DF |
2360 | |
2361 | /* Stop Rx port activity. Check port Rx activity. */ | |
12a87c64 | 2362 | queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)) |
e38fd1a0 | 2363 | & 0xFF; |
12a87c64 DF |
2364 | if (queues) { |
2365 | /* Issue stop command for active queues only */ | |
9f8dd319 | 2366 | mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), |
12a87c64 | 2367 | (queues << 8)); |
9f8dd319 DF |
2368 | |
2369 | /* Wait for all Rx activity to terminate. */ | |
2370 | /* Check port cause register that all Rx queues are stopped */ | |
2371 | while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num)) | |
2372 | & 0xFF) | |
2373 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2374 | } | |
2375 | ||
12a87c64 | 2376 | return queues; |
9f8dd319 DF |
2377 | } |
2378 | ||
1da177e4 LT |
2379 | /* |
2380 | * eth_port_reset - Reset Ethernet port | |
2381 | * | |
2382 | * DESCRIPTION: | |
2383 | * This routine resets the chip by aborting any SDMA engine activity and | |
2384 | * clearing the MIB counters. The Receiver and the Transmit unit are in | |
2385 | * idle state after this command is performed and the port is disabled. | |
2386 | * | |
2387 | * INPUT: | |
2388 | * unsigned int eth_port_num Ethernet Port number. | |
2389 | * | |
2390 | * OUTPUT: | |
2391 | * Channel activity is halted. | |
2392 | * | |
2393 | * RETURN: | |
2394 | * None. | |
2395 | * | |
2396 | */ | |
2397 | static void eth_port_reset(unsigned int port_num) | |
2398 | { | |
2399 | unsigned int reg_data; | |
2400 | ||
9f8dd319 DF |
2401 | mv643xx_eth_port_disable_tx(port_num); |
2402 | mv643xx_eth_port_disable_rx(port_num); | |
1da177e4 LT |
2403 | |
2404 | /* Clear all MIB counters */ | |
2405 | eth_clear_mib_counters(port_num); | |
2406 | ||
2407 | /* Reset the Enable bit in the Configuration Register */ | |
2408 | reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)); | |
d0412d96 JC |
2409 | reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | |
2410 | MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | | |
2411 | MV643XX_ETH_FORCE_LINK_PASS); | |
1da177e4 LT |
2412 | mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data); |
2413 | } | |
2414 | ||
1da177e4 | 2415 | |
1da177e4 LT |
2416 | /* |
2417 | * eth_port_read_smi_reg - Read PHY registers | |
2418 | * | |
2419 | * DESCRIPTION: | |
2420 | * This routine utilize the SMI interface to interact with the PHY in | |
2421 | * order to perform PHY register read. | |
2422 | * | |
2423 | * INPUT: | |
2424 | * unsigned int port_num Ethernet Port number. | |
2425 | * unsigned int phy_reg PHY register address offset. | |
2426 | * unsigned int *value Register value buffer. | |
2427 | * | |
2428 | * OUTPUT: | |
2429 | * Write the value of a specified PHY register into given buffer. | |
2430 | * | |
2431 | * RETURN: | |
2432 | * false if the PHY is busy or read data is not in valid state. | |
2433 | * true otherwise. | |
2434 | * | |
2435 | */ | |
2436 | static void eth_port_read_smi_reg(unsigned int port_num, | |
2437 | unsigned int phy_reg, unsigned int *value) | |
2438 | { | |
2439 | int phy_addr = ethernet_phy_get(port_num); | |
2440 | unsigned long flags; | |
2441 | int i; | |
2442 | ||
2443 | /* the SMI register is a shared resource */ | |
2444 | spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); | |
2445 | ||
2446 | /* wait for the SMI register to become available */ | |
2447 | for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { | |
2448 | if (i == PHY_WAIT_ITERATIONS) { | |
2449 | printk("mv643xx PHY busy timeout, port %d\n", port_num); | |
2450 | goto out; | |
2451 | } | |
2452 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2453 | } | |
2454 | ||
2455 | mv_write(MV643XX_ETH_SMI_REG, | |
2456 | (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ); | |
2457 | ||
2458 | /* now wait for the data to be valid */ | |
2459 | for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) { | |
2460 | if (i == PHY_WAIT_ITERATIONS) { | |
2461 | printk("mv643xx PHY read timeout, port %d\n", port_num); | |
2462 | goto out; | |
2463 | } | |
2464 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2465 | } | |
2466 | ||
2467 | *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff; | |
2468 | out: | |
2469 | spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); | |
2470 | } | |
2471 | ||
2472 | /* | |
2473 | * eth_port_write_smi_reg - Write to PHY registers | |
2474 | * | |
2475 | * DESCRIPTION: | |
2476 | * This routine utilize the SMI interface to interact with the PHY in | |
2477 | * order to perform writes to PHY registers. | |
2478 | * | |
2479 | * INPUT: | |
2480 | * unsigned int eth_port_num Ethernet Port number. | |
2481 | * unsigned int phy_reg PHY register address offset. | |
2482 | * unsigned int value Register value. | |
2483 | * | |
2484 | * OUTPUT: | |
2485 | * Write the given value to the specified PHY register. | |
2486 | * | |
2487 | * RETURN: | |
2488 | * false if the PHY is busy. | |
2489 | * true otherwise. | |
2490 | * | |
2491 | */ | |
2492 | static void eth_port_write_smi_reg(unsigned int eth_port_num, | |
2493 | unsigned int phy_reg, unsigned int value) | |
2494 | { | |
2495 | int phy_addr; | |
2496 | int i; | |
2497 | unsigned long flags; | |
2498 | ||
2499 | phy_addr = ethernet_phy_get(eth_port_num); | |
2500 | ||
2501 | /* the SMI register is a shared resource */ | |
2502 | spin_lock_irqsave(&mv643xx_eth_phy_lock, flags); | |
2503 | ||
2504 | /* wait for the SMI register to become available */ | |
2505 | for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) { | |
2506 | if (i == PHY_WAIT_ITERATIONS) { | |
2507 | printk("mv643xx PHY busy timeout, port %d\n", | |
2508 | eth_port_num); | |
2509 | goto out; | |
2510 | } | |
2511 | udelay(PHY_WAIT_MICRO_SECONDS); | |
2512 | } | |
2513 | ||
2514 | mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) | | |
2515 | ETH_SMI_OPCODE_WRITE | (value & 0xffff)); | |
2516 | out: | |
2517 | spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags); | |
2518 | } | |
2519 | ||
c28a4f89 JC |
2520 | /* |
2521 | * Wrappers for MII support library. | |
2522 | */ | |
2523 | static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) | |
2524 | { | |
2525 | int val; | |
2526 | struct mv643xx_private *mp = netdev_priv(dev); | |
2527 | ||
2528 | eth_port_read_smi_reg(mp->port_num, location, &val); | |
2529 | return val; | |
2530 | } | |
2531 | ||
2532 | static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) | |
2533 | { | |
2534 | struct mv643xx_private *mp = netdev_priv(dev); | |
2535 | eth_port_write_smi_reg(mp->port_num, location, val); | |
2536 | } | |
2537 | ||
1da177e4 LT |
2538 | /* |
2539 | * eth_port_receive - Get received information from Rx ring. | |
2540 | * | |
2541 | * DESCRIPTION: | |
2542 | * This routine returns the received data to the caller. There is no | |
2543 | * data copying during routine operation. All information is returned | |
2544 | * using pointer to packet information struct passed from the caller. | |
2545 | * If the routine exhausts Rx ring resources then the resource error flag | |
2546 | * is set. | |
2547 | * | |
2548 | * INPUT: | |
2549 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2550 | * struct pkt_info *p_pkt_info User packet buffer. | |
2551 | * | |
2552 | * OUTPUT: | |
2553 | * Rx ring current and used indexes are updated. | |
2554 | * | |
2555 | * RETURN: | |
2556 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
2557 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. | |
2558 | * ETH_END_OF_JOB if there is no received data. | |
2559 | * ETH_OK otherwise. | |
2560 | */ | |
2561 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, | |
2562 | struct pkt_info *p_pkt_info) | |
2563 | { | |
2564 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; | |
2565 | volatile struct eth_rx_desc *p_rx_desc; | |
2566 | unsigned int command_status; | |
8f518703 | 2567 | unsigned long flags; |
1da177e4 LT |
2568 | |
2569 | /* Do not process Rx ring in case of Rx ring resource error */ | |
2570 | if (mp->rx_resource_err) | |
2571 | return ETH_QUEUE_FULL; | |
2572 | ||
8f518703 DF |
2573 | spin_lock_irqsave(&mp->lock, flags); |
2574 | ||
1da177e4 LT |
2575 | /* Get the Rx Desc ring 'curr and 'used' indexes */ |
2576 | rx_curr_desc = mp->rx_curr_desc_q; | |
2577 | rx_used_desc = mp->rx_used_desc_q; | |
2578 | ||
2579 | p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; | |
2580 | ||
2581 | /* The following parameters are used to save readings from memory */ | |
2582 | command_status = p_rx_desc->cmd_sts; | |
2583 | rmb(); | |
2584 | ||
2585 | /* Nothing to receive... */ | |
8f518703 DF |
2586 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { |
2587 | spin_unlock_irqrestore(&mp->lock, flags); | |
1da177e4 | 2588 | return ETH_END_OF_JOB; |
8f518703 | 2589 | } |
1da177e4 LT |
2590 | |
2591 | p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET; | |
2592 | p_pkt_info->cmd_sts = command_status; | |
2593 | p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET; | |
2594 | p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; | |
2595 | p_pkt_info->l4i_chk = p_rx_desc->buf_size; | |
2596 | ||
b4de9051 DF |
2597 | /* |
2598 | * Clean the return info field to indicate that the | |
2599 | * packet has been moved to the upper layers | |
2600 | */ | |
1da177e4 LT |
2601 | mp->rx_skb[rx_curr_desc] = NULL; |
2602 | ||
2603 | /* Update current index in data structure */ | |
2604 | rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; | |
2605 | mp->rx_curr_desc_q = rx_next_curr_desc; | |
2606 | ||
2607 | /* Rx descriptors exhausted. Set the Rx ring resource error flag */ | |
2608 | if (rx_next_curr_desc == rx_used_desc) | |
2609 | mp->rx_resource_err = 1; | |
2610 | ||
8f518703 DF |
2611 | spin_unlock_irqrestore(&mp->lock, flags); |
2612 | ||
1da177e4 LT |
2613 | return ETH_OK; |
2614 | } | |
2615 | ||
2616 | /* | |
2617 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. | |
2618 | * | |
2619 | * DESCRIPTION: | |
2620 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the | |
2621 | * next 'used' descriptor and attached the returned buffer to it. | |
2622 | * In case the Rx ring was in "resource error" condition, where there are | |
2623 | * no available Rx resources, the function resets the resource error flag. | |
2624 | * | |
2625 | * INPUT: | |
2626 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
2627 | * struct pkt_info *p_pkt_info Information on returned buffer. | |
2628 | * | |
2629 | * OUTPUT: | |
2630 | * New available Rx resource in Rx descriptor ring. | |
2631 | * | |
2632 | * RETURN: | |
2633 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
2634 | * ETH_OK otherwise. | |
2635 | */ | |
2636 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, | |
2637 | struct pkt_info *p_pkt_info) | |
2638 | { | |
2639 | int used_rx_desc; /* Where to return Rx resource */ | |
2640 | volatile struct eth_rx_desc *p_used_rx_desc; | |
8f518703 DF |
2641 | unsigned long flags; |
2642 | ||
2643 | spin_lock_irqsave(&mp->lock, flags); | |
1da177e4 LT |
2644 | |
2645 | /* Get 'used' Rx descriptor */ | |
2646 | used_rx_desc = mp->rx_used_desc_q; | |
2647 | p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; | |
2648 | ||
2649 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; | |
2650 | p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; | |
2651 | mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; | |
2652 | ||
2653 | /* Flush the write pipe */ | |
2654 | ||
2655 | /* Return the descriptor to DMA ownership */ | |
2656 | wmb(); | |
2657 | p_used_rx_desc->cmd_sts = | |
2658 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
2659 | wmb(); | |
2660 | ||
2661 | /* Move the used descriptor pointer to the next descriptor */ | |
2662 | mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; | |
2663 | ||
2664 | /* Any Rx return cancels the Rx resource error status */ | |
2665 | mp->rx_resource_err = 0; | |
2666 | ||
8f518703 DF |
2667 | spin_unlock_irqrestore(&mp->lock, flags); |
2668 | ||
1da177e4 LT |
2669 | return ETH_OK; |
2670 | } | |
2671 | ||
2672 | /************* Begin ethtool support *************************/ | |
2673 | ||
2674 | struct mv643xx_stats { | |
2675 | char stat_string[ETH_GSTRING_LEN]; | |
2676 | int sizeof_stat; | |
2677 | int stat_offset; | |
2678 | }; | |
2679 | ||
2680 | #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \ | |
b4de9051 | 2681 | offsetof(struct mv643xx_private, m) |
1da177e4 LT |
2682 | |
2683 | static const struct mv643xx_stats mv643xx_gstrings_stats[] = { | |
2684 | { "rx_packets", MV643XX_STAT(stats.rx_packets) }, | |
2685 | { "tx_packets", MV643XX_STAT(stats.tx_packets) }, | |
2686 | { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, | |
2687 | { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, | |
2688 | { "rx_errors", MV643XX_STAT(stats.rx_errors) }, | |
2689 | { "tx_errors", MV643XX_STAT(stats.tx_errors) }, | |
2690 | { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, | |
2691 | { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, | |
2692 | { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, | |
2693 | { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, | |
2694 | { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, | |
2695 | { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, | |
2696 | { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, | |
2697 | { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, | |
2698 | { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, | |
2699 | { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, | |
2700 | { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, | |
2701 | { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, | |
2702 | { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, | |
2703 | { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, | |
2704 | { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, | |
2705 | { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, | |
2706 | { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, | |
2707 | { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, | |
2708 | { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, | |
2709 | { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, | |
2710 | { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, | |
2711 | { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, | |
2712 | { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, | |
2713 | { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, | |
2714 | { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, | |
2715 | { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, | |
2716 | { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, | |
2717 | { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, | |
2718 | { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, | |
2719 | { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, | |
2720 | { "collision", MV643XX_STAT(mib_counters.collision) }, | |
2721 | { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, | |
2722 | }; | |
2723 | ||
2724 | #define MV643XX_STATS_LEN \ | |
2725 | sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats) | |
2726 | ||
b4de9051 DF |
2727 | static void mv643xx_get_drvinfo(struct net_device *netdev, |
2728 | struct ethtool_drvinfo *drvinfo) | |
1da177e4 LT |
2729 | { |
2730 | strncpy(drvinfo->driver, mv643xx_driver_name, 32); | |
2731 | strncpy(drvinfo->version, mv643xx_driver_version, 32); | |
2732 | strncpy(drvinfo->fw_version, "N/A", 32); | |
2733 | strncpy(drvinfo->bus_info, "mv643xx", 32); | |
2734 | drvinfo->n_stats = MV643XX_STATS_LEN; | |
2735 | } | |
2736 | ||
b4de9051 | 2737 | static int mv643xx_get_stats_count(struct net_device *netdev) |
1da177e4 LT |
2738 | { |
2739 | return MV643XX_STATS_LEN; | |
2740 | } | |
2741 | ||
b4de9051 DF |
2742 | static void mv643xx_get_ethtool_stats(struct net_device *netdev, |
2743 | struct ethtool_stats *stats, uint64_t *data) | |
1da177e4 LT |
2744 | { |
2745 | struct mv643xx_private *mp = netdev->priv; | |
2746 | int i; | |
2747 | ||
2748 | eth_update_mib_counters(mp); | |
2749 | ||
b4de9051 | 2750 | for (i = 0; i < MV643XX_STATS_LEN; i++) { |
6aa20a22 | 2751 | char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; |
b4de9051 | 2752 | data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == |
1da177e4 LT |
2753 | sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; |
2754 | } | |
2755 | } | |
2756 | ||
b4de9051 DF |
2757 | static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, |
2758 | uint8_t *data) | |
1da177e4 LT |
2759 | { |
2760 | int i; | |
2761 | ||
2762 | switch(stringset) { | |
2763 | case ETH_SS_STATS: | |
2764 | for (i=0; i < MV643XX_STATS_LEN; i++) { | |
b4de9051 DF |
2765 | memcpy(data + i * ETH_GSTRING_LEN, |
2766 | mv643xx_gstrings_stats[i].stat_string, | |
2767 | ETH_GSTRING_LEN); | |
1da177e4 LT |
2768 | } |
2769 | break; | |
2770 | } | |
2771 | } | |
2772 | ||
d0412d96 JC |
2773 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
2774 | { | |
2775 | struct mv643xx_private *mp = netdev_priv(dev); | |
2776 | ||
2777 | return mii_link_ok(&mp->mii); | |
2778 | } | |
2779 | ||
2780 | static int mv643xx_eth_nway_restart(struct net_device *dev) | |
2781 | { | |
2782 | struct mv643xx_private *mp = netdev_priv(dev); | |
2783 | ||
2784 | return mii_nway_restart(&mp->mii); | |
2785 | } | |
2786 | ||
2787 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2788 | { | |
2789 | struct mv643xx_private *mp = netdev_priv(dev); | |
2790 | ||
2791 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); | |
2792 | } | |
2793 | ||
7282d491 | 2794 | static const struct ethtool_ops mv643xx_ethtool_ops = { |
1da177e4 | 2795 | .get_settings = mv643xx_get_settings, |
d0412d96 | 2796 | .set_settings = mv643xx_set_settings, |
1da177e4 | 2797 | .get_drvinfo = mv643xx_get_drvinfo, |
d0412d96 | 2798 | .get_link = mv643xx_eth_get_link, |
1da177e4 LT |
2799 | .get_sg = ethtool_op_get_sg, |
2800 | .set_sg = ethtool_op_set_sg, | |
1da177e4 LT |
2801 | .get_stats_count = mv643xx_get_stats_count, |
2802 | .get_ethtool_stats = mv643xx_get_ethtool_stats, | |
d0412d96 JC |
2803 | .get_strings = mv643xx_get_strings, |
2804 | .get_stats_count = mv643xx_get_stats_count, | |
2805 | .get_ethtool_stats = mv643xx_get_ethtool_stats, | |
2806 | .nway_reset = mv643xx_eth_nway_restart, | |
1da177e4 LT |
2807 | }; |
2808 | ||
2809 | /************* End ethtool support *************************/ |