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drivers/net: Kill now superfluous ->last_rx stores.
[mirror_ubuntu-jammy-kernel.git] / drivers / net / mv643xx_eth.c
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1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
1da177e4
LT		 54#include <asm/io.h>
55#include <asm/types.h>
1da177e4 56#include <asm/system.h>
fbd6a754 57
e5371493 58static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 59static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 60
fbd6a754 61
fbd6a754
LB		 62/*
63 * Registers shared between all ports.
64 */
3cb4667c
LB		 65#define PHY_ADDR 0x0000
66#define SMI_REG 0x0004
45c5d3bc
LB		 67#define SMI_BUSY 0x10000000
68#define SMI_READ_VALID 0x08000000
69#define SMI_OPCODE_READ 0x04000000
70#define SMI_OPCODE_WRITE 0x00000000
71#define ERR_INT_CAUSE 0x0080
72#define ERR_INT_SMI_DONE 0x00000010
73#define ERR_INT_MASK 0x0084
3cb4667c
LB		 74#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77#define WINDOW_BAR_ENABLE 0x0290
78#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 79
80/*
81 * Per-port registers.
82 */
3cb4667c 83#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 84#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 85#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
86#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
87#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
88#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
89#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
90#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 91#define TX_FIFO_EMPTY 0x00000400
ae9ae064 92#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 93#define PORT_SPEED_MASK 0x00000030
94#define PORT_SPEED_1000 0x00000010
95#define PORT_SPEED_100 0x00000020
96#define PORT_SPEED_10 0x00000000
97#define FLOW_CONTROL_ENABLED 0x00000008
98#define FULL_DUPLEX 0x00000004
81600eea 99#define LINK_UP 0x00000002
3cb4667c 100#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 101#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
102#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 103#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 104#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 105#define INT_CAUSE(p) (0x0460 + ((p) << 10))
226bb6b7 106#define INT_TX_END 0x07f80000
befefe21 107#define INT_RX 0x000003fc
073a345c 108#define INT_EXT 0x00000002
3cb4667c 109#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
befefe21
LB		 110#define INT_EXT_LINK_PHY 0x00110000
111#define INT_EXT_TX 0x000000ff
3cb4667c
LB		 112#define INT_MASK(p) (0x0468 + ((p) << 10))
113#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
114#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 115#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
116#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
117#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
118#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 119#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 120#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 121#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
122#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
123#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
124#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 125#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
126#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
127#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
128#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 129
2679a550
LB		 130
131/*
132 * SDMA configuration register.
133 */
cd4ccf76 134#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 135#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 136#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 137#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 138
139#if defined(__BIG_ENDIAN)
140#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 141 RX_BURST_SIZE_16_64BIT | \
142 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 143#elif defined(__LITTLE_ENDIAN)
144#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 145 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 146 BLM_RX_NO_SWAP | \
147 BLM_TX_NO_SWAP | \
cd4ccf76 148 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 149#else
150#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
151#endif
152
2beff77b
LB		 153
154/*
155 * Port serial control register.
156 */
157#define SET_MII_SPEED_TO_100 (1 << 24)
158#define SET_GMII_SPEED_TO_1000 (1 << 23)
159#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 160#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 161#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
162#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
163#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
164#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
165#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
166#define FORCE_LINK_PASS (1 << 1)
167#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 168
2b4a624d
LB		 169#define DEFAULT_RX_QUEUE_SIZE 128
170#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 171
fbd6a754 172
7ca72a3b
LB		 173/*
174 * RX/TX descriptors.
fbd6a754
LB		 175 */
176#if defined(__BIG_ENDIAN)
cc9754b3 177struct rx_desc {
fbd6a754
LB		 178 u16 byte_cnt; /* Descriptor buffer byte count */
179 u16 buf_size; /* Buffer size */
180 u32 cmd_sts; /* Descriptor command status */
181 u32 next_desc_ptr; /* Next descriptor pointer */
182 u32 buf_ptr; /* Descriptor buffer pointer */
183};
184
cc9754b3 185struct tx_desc {
fbd6a754
LB		 186 u16 byte_cnt; /* buffer byte count */
187 u16 l4i_chk; /* CPU provided TCP checksum */
188 u32 cmd_sts; /* Command/status field */
189 u32 next_desc_ptr; /* Pointer to next descriptor */
190 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191};
192#elif defined(__LITTLE_ENDIAN)
cc9754b3 193struct rx_desc {
fbd6a754
LB		 194 u32 cmd_sts; /* Descriptor command status */
195 u16 buf_size; /* Buffer size */
196 u16 byte_cnt; /* Descriptor buffer byte count */
197 u32 buf_ptr; /* Descriptor buffer pointer */
198 u32 next_desc_ptr; /* Next descriptor pointer */
199};
200
cc9754b3 201struct tx_desc {
fbd6a754
LB		 202 u32 cmd_sts; /* Command/status field */
203 u16 l4i_chk; /* CPU provided TCP checksum */
204 u16 byte_cnt; /* buffer byte count */
205 u32 buf_ptr; /* pointer to buffer for this descriptor*/
206 u32 next_desc_ptr; /* Pointer to next descriptor */
207};
208#else
209#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
210#endif
211
7ca72a3b 212/* RX & TX descriptor command */
cc9754b3 213#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 214
215/* RX & TX descriptor status */
cc9754b3 216#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 217
218/* RX descriptor status */
cc9754b3
LB		 219#define LAYER_4_CHECKSUM_OK 0x40000000
220#define RX_ENABLE_INTERRUPT 0x20000000
221#define RX_FIRST_DESC 0x08000000
222#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 223
224/* TX descriptor command */
cc9754b3
LB		 225#define TX_ENABLE_INTERRUPT 0x00800000
226#define GEN_CRC 0x00400000
227#define TX_FIRST_DESC 0x00200000
228#define TX_LAST_DESC 0x00100000
229#define ZERO_PADDING 0x00080000
230#define GEN_IP_V4_CHECKSUM 0x00040000
231#define GEN_TCP_UDP_CHECKSUM 0x00020000
232#define UDP_FRAME 0x00010000
e32b6617
LB		 233#define MAC_HDR_EXTRA_4_BYTES 0x00008000
234#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 235
cc9754b3 236#define TX_IHL_SHIFT 11
7ca72a3b
LB		 237
238
c9df406f 239/* global *******************************************************************/
e5371493 240struct mv643xx_eth_shared_private {
fc32b0e2
LB		 241 /*
242 * Ethernet controller base address.
243 */
cc9754b3 244 void __iomem *base;
c9df406f 245
fc0eb9f2
LB		 246 /*
247 * Points at the right SMI instance to use.
248 */
249 struct mv643xx_eth_shared_private *smi;
250
fc32b0e2 251 /*
ed94493f 252 * Provides access to local SMI interface.
fc32b0e2 253 */
298cf9be 254 struct mii_bus *smi_bus;
c9df406f 255
45c5d3bc
LB		 256 /*
257 * If we have access to the error interrupt pin (which is
258 * somewhat misnamed as it not only reflects internal errors
259 * but also reflects SMI completion), use that to wait for
260 * SMI access completion instead of polling the SMI busy bit.
261 */
262 int err_interrupt;
263 wait_queue_head_t smi_busy_wait;
264
fc32b0e2
LB		 265 /*
266 * Per-port MBUS window access register value.
267 */
c9df406f
LB		 268 u32 win_protect;
269
fc32b0e2
LB		 270 /*
271 * Hardware-specific parameters.
272 */
c9df406f 273 unsigned int t_clk;
773fc3ee 274 int extended_rx_coal_limit;
457b1d5a 275 int tx_bw_control;
c9df406f
LB		 276};
277
457b1d5a
LB		 278#define TX_BW_CONTROL_ABSENT 0
279#define TX_BW_CONTROL_OLD_LAYOUT 1
280#define TX_BW_CONTROL_NEW_LAYOUT 2
281
c9df406f
LB		 282
283/* per-port *****************************************************************/
e5371493 284struct mib_counters {
fbd6a754
LB		 285 u64 good_octets_received;
286 u32 bad_octets_received;
287 u32 internal_mac_transmit_err;
288 u32 good_frames_received;
289 u32 bad_frames_received;
290 u32 broadcast_frames_received;
291 u32 multicast_frames_received;
292 u32 frames_64_octets;
293 u32 frames_65_to_127_octets;
294 u32 frames_128_to_255_octets;
295 u32 frames_256_to_511_octets;
296 u32 frames_512_to_1023_octets;
297 u32 frames_1024_to_max_octets;
298 u64 good_octets_sent;
299 u32 good_frames_sent;
300 u32 excessive_collision;
301 u32 multicast_frames_sent;
302 u32 broadcast_frames_sent;
303 u32 unrec_mac_control_received;
304 u32 fc_sent;
305 u32 good_fc_received;
306 u32 bad_fc_received;
307 u32 undersize_received;
308 u32 fragments_received;
309 u32 oversize_received;
310 u32 jabber_received;
311 u32 mac_receive_error;
312 u32 bad_crc_event;
313 u32 collision;
314 u32 late_collision;
315};
316
8a578111 317struct rx_queue {
64da80a2
LB		 318 int index;
319
8a578111
LB		 320 int rx_ring_size;
321
322 int rx_desc_count;
323 int rx_curr_desc;
324 int rx_used_desc;
325
326 struct rx_desc *rx_desc_area;
327 dma_addr_t rx_desc_dma;
328 int rx_desc_area_size;
329 struct sk_buff **rx_skb;
8a578111
LB		 330};
331
13d64285 332struct tx_queue {
3d6b35bc
LB		 333 int index;
334
13d64285 335 int tx_ring_size;
fbd6a754 336
13d64285
LB		 337 int tx_desc_count;
338 int tx_curr_desc;
339 int tx_used_desc;
fbd6a754 340
5daffe94 341 struct tx_desc *tx_desc_area;
fbd6a754
LB		 342 dma_addr_t tx_desc_dma;
343 int tx_desc_area_size;
99ab08e0
LB		 344
345 struct sk_buff_head tx_skb;
8fd89211
LB		 346
347 unsigned long tx_packets;
348 unsigned long tx_bytes;
349 unsigned long tx_dropped;
13d64285
LB		 350};
351
352struct mv643xx_eth_private {
353 struct mv643xx_eth_shared_private *shared;
fc32b0e2 354 int port_num;
13d64285 355
fc32b0e2 356 struct net_device *dev;
fbd6a754 357
ed94493f 358 struct phy_device *phy;
fbd6a754 359
4ff3495a
LB		 360 struct timer_list mib_counters_timer;
361 spinlock_t mib_counters_lock;
fc32b0e2 362 struct mib_counters mib_counters;
4ff3495a 363
fc32b0e2 364 struct work_struct tx_timeout_task;
8a578111 365
1fa38c58
LB		 366 struct napi_struct napi;
367 u8 work_link;
368 u8 work_tx;
369 u8 work_tx_end;
370 u8 work_rx;
371 u8 work_rx_refill;
372 u8 work_rx_oom;
373
2bcb4b0f
LB		 374 int skb_size;
375 struct sk_buff_head rx_recycle;
376
8a578111
LB		 377 /*
378 * RX state.
379 */
380 int default_rx_ring_size;
381 unsigned long rx_desc_sram_addr;
382 int rx_desc_sram_size;
f7981c1c 383 int rxq_count;
2257e05c 384 struct timer_list rx_oom;
64da80a2 385 struct rx_queue rxq[8];
13d64285
LB		 386
387 /*
388 * TX state.
389 */
390 int default_tx_ring_size;
391 unsigned long tx_desc_sram_addr;
392 int tx_desc_sram_size;
f7981c1c 393 int txq_count;
3d6b35bc 394 struct tx_queue txq[8];
fbd6a754 395};
1da177e4 396
fbd6a754 397
c9df406f 398/* port register accessors **************************************************/
e5371493 399static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 400{
cc9754b3 401 return readl(mp->shared->base + offset);
c9df406f 402}
fbd6a754 403
e5371493 404static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 405{
cc9754b3 406 writel(data, mp->shared->base + offset);
c9df406f 407}
fbd6a754 408
fbd6a754 409
c9df406f 410/* rxq/txq helper functions *************************************************/
8a578111 411static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 412{
64da80a2 413 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 414}
fbd6a754 415
13d64285
LB		 416static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
417{
3d6b35bc 418 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 419}
420
8a578111 421static void rxq_enable(struct rx_queue *rxq)
c9df406f 422{
8a578111 423 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 424 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 425}
1da177e4 426
8a578111
LB		 427static void rxq_disable(struct rx_queue *rxq)
428{
429 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 430 u8 mask = 1 << rxq->index;
1da177e4 431
8a578111
LB		 432 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
433 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
434 udelay(10);
c9df406f
LB		 435}
436
6b368f68
LB		 437static void txq_reset_hw_ptr(struct tx_queue *txq)
438{
439 struct mv643xx_eth_private *mp = txq_to_mp(txq);
440 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
441 u32 addr;
442
443 addr = (u32)txq->tx_desc_dma;
444 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
445 wrl(mp, off, addr);
446}
447
13d64285 448static void txq_enable(struct tx_queue *txq)
1da177e4 449{
13d64285 450 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 451 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 452}
453
13d64285 454static void txq_disable(struct tx_queue *txq)
1da177e4 455{
13d64285 456 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 457 u8 mask = 1 << txq->index;
c9df406f 458
13d64285
LB		 459 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
460 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
461 udelay(10);
462}
463
1fa38c58 464static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 465{
466 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 467 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 468
8fd89211
LB		 469 if (netif_tx_queue_stopped(nq)) {
470 __netif_tx_lock(nq, smp_processor_id());
471 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
472 netif_tx_wake_queue(nq);
473 __netif_tx_unlock(nq);
474 }
1da177e4
LT		 475}
476
c9df406f 477
1fa38c58 478/* rx napi ******************************************************************/
8a578111 479static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 480{
8a578111
LB		 481 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
482 struct net_device_stats *stats = &mp->dev->stats;
483 int rx;
1da177e4 484
8a578111 485 rx = 0;
9e1f3772 486 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 487 struct rx_desc *rx_desc;
96587661 488 unsigned int cmd_sts;
fc32b0e2 489 struct sk_buff *skb;
6b8f90c2 490 u16 byte_cnt;
ff561eef 491
8a578111 492 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 493
96587661 494 cmd_sts = rx_desc->cmd_sts;
2257e05c 495 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 496 break;
96587661 497 rmb();
1da177e4 498
8a578111
LB		 499 skb = rxq->rx_skb[rxq->rx_curr_desc];
500 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 501
9da78745
LB		 502 rxq->rx_curr_desc++;
503 if (rxq->rx_curr_desc == rxq->rx_ring_size)
504 rxq->rx_curr_desc = 0;
ff561eef 505
3a499481 506 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 507 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 508 rxq->rx_desc_count--;
509 rx++;
b1dd9ca1 510
1fa38c58
LB		 511 mp->work_rx_refill |= 1 << rxq->index;
512
6b8f90c2
LB		 513 byte_cnt = rx_desc->byte_cnt;
514
468d09f8
DF		 515 /*
516 * Update statistics.
fc32b0e2
LB		 517 *
518 * Note that the descriptor byte count includes 2 dummy
519 * bytes automatically inserted by the hardware at the
520 * start of the packet (which we don't count), and a 4
521 * byte CRC at the end of the packet (which we do count).
468d09f8 522 */
1da177e4 523 stats->rx_packets++;
6b8f90c2 524 stats->rx_bytes += byte_cnt - 2;
96587661 525
1da177e4 526 /*
fc32b0e2
LB		 527 * In case we received a packet without first / last bits
528 * on, or the error summary bit is set, the packet needs
529 * to be dropped.
1da177e4 530 */
96587661 531 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 532 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 533 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 534 stats->rx_dropped++;
fc32b0e2 535
96587661 536 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 537 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 538 if (net_ratelimit())
fc32b0e2
LB		 539 dev_printk(KERN_ERR, &mp->dev->dev,
540 "received packet spanning "
541 "multiple descriptors\n");
1da177e4 542 }
fc32b0e2 543
96587661 544 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 545 stats->rx_errors++;
546
78fff83b 547 dev_kfree_skb(skb);
1da177e4
LT		 548 } else {
549 /*
550 * The -4 is for the CRC in the trailer of the
551 * received packet
552 */
6b8f90c2 553 skb_put(skb, byte_cnt - 2 - 4);
1da177e4 554
170e7108 555 if (cmd_sts & LAYER_4_CHECKSUM_OK)
1da177e4 556 skb->ip_summed = CHECKSUM_UNNECESSARY;
8a578111 557 skb->protocol = eth_type_trans(skb, mp->dev);
1da177e4 558 netif_receive_skb(skb);
1da177e4
LT		 559 }
560 }
fc32b0e2 561
1fa38c58
LB		 562 if (rx < budget)
563 mp->work_rx &= ~(1 << rxq->index);
564
8a578111 565 return rx;
1da177e4
LT		 566}
567
1fa38c58 568static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 569{
1fa38c58 570 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 571 int refilled;
8a578111 572
1fa38c58
LB		 573 refilled = 0;
574 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
575 struct sk_buff *skb;
576 int unaligned;
577 int rx;
d0412d96 578
2bcb4b0f
LB		 579 skb = __skb_dequeue(&mp->rx_recycle);
580 if (skb == NULL)
581 skb = dev_alloc_skb(mp->skb_size +
582 dma_get_cache_alignment() - 1);
583
1fa38c58
LB		 584 if (skb == NULL) {
585 mp->work_rx_oom |= 1 << rxq->index;
586 goto oom;
587 }
d0412d96 588
1fa38c58
LB		 589 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
590 if (unaligned)
591 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 592
1fa38c58
LB		 593 refilled++;
594 rxq->rx_desc_count++;
c9df406f 595
1fa38c58
LB		 596 rx = rxq->rx_used_desc++;
597 if (rxq->rx_used_desc == rxq->rx_ring_size)
598 rxq->rx_used_desc = 0;
2257e05c 599
1fa38c58 600 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
2bcb4b0f
LB		 601 mp->skb_size, DMA_FROM_DEVICE);
602 rxq->rx_desc_area[rx].buf_size = mp->skb_size;
1fa38c58
LB		 603 rxq->rx_skb[rx] = skb;
604 wmb();
605 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
606 RX_ENABLE_INTERRUPT;
607 wmb();
2257e05c 608
1fa38c58
LB		 609 /*
610 * The hardware automatically prepends 2 bytes of
611 * dummy data to each received packet, so that the
612 * IP header ends up 16-byte aligned.
613 */
614 skb_reserve(skb, 2);
615 }
616
617 if (refilled < budget)
618 mp->work_rx_refill &= ~(1 << rxq->index);
619
620oom:
621 return refilled;
d0412d96
JC		 622}
623
c9df406f
LB		 624
625/* tx ***********************************************************************/
c9df406f 626static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 627{
13d64285 628 int frag;
1da177e4 629
c9df406f 630 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 631 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
632 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 633 return 1;
1da177e4 634 }
13d64285 635
c9df406f
LB		 636 return 0;
637}
7303fde8 638
13d64285 639static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 640{
641 int tx_desc_curr;
d0412d96 642
13d64285 643 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 644
9da78745
LB		 645 tx_desc_curr = txq->tx_curr_desc++;
646 if (txq->tx_curr_desc == txq->tx_ring_size)
647 txq->tx_curr_desc = 0;
e4d00fa9 648
13d64285 649 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 650
c9df406f
LB		 651 return tx_desc_curr;
652}
468d09f8 653
13d64285 654static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 655{
13d64285 656 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 657 int frag;
1da177e4 658
13d64285
LB		 659 for (frag = 0; frag < nr_frags; frag++) {
660 skb_frag_t *this_frag;
661 int tx_index;
662 struct tx_desc *desc;
663
664 this_frag = &skb_shinfo(skb)->frags[frag];
665 tx_index = txq_alloc_desc_index(txq);
666 desc = &txq->tx_desc_area[tx_index];
667
668 /*
669 * The last fragment will generate an interrupt
670 * which will free the skb on TX completion.
671 */
672 if (frag == nr_frags - 1) {
673 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
674 ZERO_PADDING | TX_LAST_DESC |
675 TX_ENABLE_INTERRUPT;
13d64285
LB		 676 } else {
677 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 678 }
679
c9df406f
LB		 680 desc->l4i_chk = 0;
681 desc->byte_cnt = this_frag->size;
682 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
683 this_frag->page_offset,
684 this_frag->size,
685 DMA_TO_DEVICE);
686 }
1da177e4
LT		 687}
688
c9df406f
LB		 689static inline __be16 sum16_as_be(__sum16 sum)
690{
691 return (__force __be16)sum;
692}
1da177e4 693
4df89bd5 694static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 695{
8fa89bf5 696 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 697 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 698 int tx_index;
cc9754b3 699 struct tx_desc *desc;
c9df406f 700 u32 cmd_sts;
4df89bd5 701 u16 l4i_chk;
c9df406f 702 int length;
1da177e4 703
cc9754b3 704 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 705 l4i_chk = 0;
c9df406f
LB		 706
707 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 708 int tag_bytes;
e32b6617
LB		 709
710 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
711 skb->protocol != htons(ETH_P_8021Q));
c9df406f 712
4df89bd5
LB		 713 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
714 if (unlikely(tag_bytes & ~12)) {
715 if (skb_checksum_help(skb) == 0)
716 goto no_csum;
717 kfree_skb(skb);
718 return 1;
719 }
c9df406f 720
4df89bd5 721 if (tag_bytes & 4)
e32b6617 722 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 723 if (tag_bytes & 8)
e32b6617 724 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 725
726 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
727 GEN_IP_V4_CHECKSUM |
728 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 729
c9df406f
LB		 730 switch (ip_hdr(skb)->protocol) {
731 case IPPROTO_UDP:
cc9754b3 732 cmd_sts |= UDP_FRAME;
4df89bd5 733 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 734 break;
735 case IPPROTO_TCP:
4df89bd5 736 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 737 break;
738 default:
739 BUG();
740 }
741 } else {
4df89bd5 742no_csum:
c9df406f 743 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 744 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 745 }
746
4df89bd5
LB		 747 tx_index = txq_alloc_desc_index(txq);
748 desc = &txq->tx_desc_area[tx_index];
749
750 if (nr_frags) {
751 txq_submit_frag_skb(txq, skb);
752 length = skb_headlen(skb);
753 } else {
754 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
755 length = skb->len;
756 }
757
758 desc->l4i_chk = l4i_chk;
759 desc->byte_cnt = length;
760 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
761
99ab08e0
LB		 762 __skb_queue_tail(&txq->tx_skb, skb);
763
c9df406f
LB		 764 /* ensure all other descriptors are written before first cmd_sts */
765 wmb();
766 desc->cmd_sts = cmd_sts;
767
1fa38c58
LB		 768 /* clear TX_END status */
769 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 770
c9df406f
LB		 771 /* ensure all descriptors are written before poking hardware */
772 wmb();
13d64285 773 txq_enable(txq);
c9df406f 774
13d64285 775 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 776
777 return 0;
1da177e4 778}
1da177e4 779
fc32b0e2 780static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 781{
e5371493 782 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 783 int queue;
13d64285 784 struct tx_queue *txq;
e5ef1de1 785 struct netdev_queue *nq;
afdb57a2 786
8fd89211
LB		 787 queue = skb_get_queue_mapping(skb);
788 txq = mp->txq + queue;
789 nq = netdev_get_tx_queue(dev, queue);
790
c9df406f 791 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 792 txq->tx_dropped++;
fc32b0e2
LB		 793 dev_printk(KERN_DEBUG, &dev->dev,
794 "failed to linearize skb with tiny "
795 "unaligned fragment\n");
c9df406f
LB		 796 return NETDEV_TX_BUSY;
797 }
798
17cd0a59 799 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 800 if (net_ratelimit())
801 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 802 kfree_skb(skb);
803 return NETDEV_TX_OK;
c9df406f
LB		 804 }
805
4df89bd5
LB		 806 if (!txq_submit_skb(txq, skb)) {
807 int entries_left;
808
809 txq->tx_bytes += skb->len;
810 txq->tx_packets++;
811 dev->trans_start = jiffies;
c9df406f 812
4df89bd5
LB		 813 entries_left = txq->tx_ring_size - txq->tx_desc_count;
814 if (entries_left < MAX_SKB_FRAGS + 1)
815 netif_tx_stop_queue(nq);
816 }
c9df406f 817
c9df406f 818 return NETDEV_TX_OK;
1da177e4
LT		 819}
820
c9df406f 821
1fa38c58
LB		 822/* tx napi ******************************************************************/
823static void txq_kick(struct tx_queue *txq)
824{
825 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 826 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 827 u32 hw_desc_ptr;
828 u32 expected_ptr;
829
8fd89211 830 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 831
832 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
833 goto out;
834
835 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
836 expected_ptr = (u32)txq->tx_desc_dma +
837 txq->tx_curr_desc * sizeof(struct tx_desc);
838
839 if (hw_desc_ptr != expected_ptr)
840 txq_enable(txq);
841
842out:
8fd89211 843 __netif_tx_unlock(nq);
1fa38c58
LB		 844
845 mp->work_tx_end &= ~(1 << txq->index);
846}
847
848static int txq_reclaim(struct tx_queue *txq, int budget, int force)
849{
850 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 851 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 852 int reclaimed;
853
8fd89211 854 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 855
856 reclaimed = 0;
857 while (reclaimed < budget && txq->tx_desc_count > 0) {
858 int tx_index;
859 struct tx_desc *desc;
860 u32 cmd_sts;
861 struct sk_buff *skb;
1fa38c58
LB		 862
863 tx_index = txq->tx_used_desc;
864 desc = &txq->tx_desc_area[tx_index];
865 cmd_sts = desc->cmd_sts;
866
867 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
868 if (!force)
869 break;
870 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
871 }
872
873 txq->tx_used_desc = tx_index + 1;
874 if (txq->tx_used_desc == txq->tx_ring_size)
875 txq->tx_used_desc = 0;
876
877 reclaimed++;
878 txq->tx_desc_count--;
879
99ab08e0
LB		 880 skb = NULL;
881 if (cmd_sts & TX_LAST_DESC)
882 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 883
884 if (cmd_sts & ERROR_SUMMARY) {
885 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
886 mp->dev->stats.tx_errors++;
887 }
888
a418950c
LB		 889 if (cmd_sts & TX_FIRST_DESC) {
890 dma_unmap_single(NULL, desc->buf_ptr,
891 desc->byte_cnt, DMA_TO_DEVICE);
892 } else {
893 dma_unmap_page(NULL, desc->buf_ptr,
894 desc->byte_cnt, DMA_TO_DEVICE);
895 }
1fa38c58 896
2bcb4b0f
LB		 897 if (skb != NULL) {
898 if (skb_queue_len(&mp->rx_recycle) <
899 mp->default_rx_ring_size &&
900 skb_recycle_check(skb, mp->skb_size))
901 __skb_queue_head(&mp->rx_recycle, skb);
902 else
903 dev_kfree_skb(skb);
904 }
1fa38c58
LB		 905 }
906
8fd89211
LB		 907 __netif_tx_unlock(nq);
908
1fa38c58
LB		 909 if (reclaimed < budget)
910 mp->work_tx &= ~(1 << txq->index);
911
1fa38c58
LB		 912 return reclaimed;
913}
914
915
89df5fdc
LB		 916/* tx rate control **********************************************************/
917/*
918 * Set total maximum TX rate (shared by all TX queues for this port)
919 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
920 */
921static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
922{
923 int token_rate;
924 int mtu;
925 int bucket_size;
926
927 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
928 if (token_rate > 1023)
929 token_rate = 1023;
930
931 mtu = (mp->dev->mtu + 255) >> 8;
932 if (mtu > 63)
933 mtu = 63;
934
935 bucket_size = (burst + 255) >> 8;
936 if (bucket_size > 65535)
937 bucket_size = 65535;
938
457b1d5a
LB		 939 switch (mp->shared->tx_bw_control) {
940 case TX_BW_CONTROL_OLD_LAYOUT:
1e881592
LB		 941 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
942 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
943 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
457b1d5a
LB		 944 break;
945 case TX_BW_CONTROL_NEW_LAYOUT:
946 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
947 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
948 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
949 break;
1e881592 950 }
89df5fdc
LB		 951}
952
953static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
954{
955 struct mv643xx_eth_private *mp = txq_to_mp(txq);
956 int token_rate;
957 int bucket_size;
958
959 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
960 if (token_rate > 1023)
961 token_rate = 1023;
962
963 bucket_size = (burst + 255) >> 8;
964 if (bucket_size > 65535)
965 bucket_size = 65535;
966
3d6b35bc
LB		 967 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
968 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 969 (bucket_size << 10) | token_rate);
970}
971
972static void txq_set_fixed_prio_mode(struct tx_queue *txq)
973{
974 struct mv643xx_eth_private *mp = txq_to_mp(txq);
975 int off;
976 u32 val;
977
978 /*
979 * Turn on fixed priority mode.
980 */
457b1d5a
LB		 981 off = 0;
982 switch (mp->shared->tx_bw_control) {
983 case TX_BW_CONTROL_OLD_LAYOUT:
1e881592 984 off = TXQ_FIX_PRIO_CONF(mp->port_num);
457b1d5a
LB		 985 break;
986 case TX_BW_CONTROL_NEW_LAYOUT:
987 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
988 break;
989 }
89df5fdc 990
457b1d5a
LB		 991 if (off) {
992 val = rdl(mp, off);
993 val |= 1 << txq->index;
994 wrl(mp, off, val);
995 }
89df5fdc
LB		 996}
997
998static void txq_set_wrr(struct tx_queue *txq, int weight)
999{
1000 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1001 int off;
1002 u32 val;
1003
1004 /*
1005 * Turn off fixed priority mode.
1006 */
457b1d5a
LB		 1007 off = 0;
1008 switch (mp->shared->tx_bw_control) {
1009 case TX_BW_CONTROL_OLD_LAYOUT:
1e881592 1010 off = TXQ_FIX_PRIO_CONF(mp->port_num);
457b1d5a
LB		 1011 break;
1012 case TX_BW_CONTROL_NEW_LAYOUT:
1013 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1014 break;
1015 }
89df5fdc 1016
457b1d5a
LB		 1017 if (off) {
1018 val = rdl(mp, off);
1019 val &= ~(1 << txq->index);
1020 wrl(mp, off, val);
89df5fdc 1021
457b1d5a
LB		 1022 /*
1023 * Configure WRR weight for this queue.
1024 */
1025 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc 1026
457b1d5a
LB		 1027 val = rdl(mp, off);
1028 val = (val & ~0xff) | (weight & 0xff);
1029 wrl(mp, off, val);
1030 }
89df5fdc
LB		 1031}
1032
1033
c9df406f 1034/* mii management interface *************************************************/
45c5d3bc
LB		 1035static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1036{
1037 struct mv643xx_eth_shared_private *msp = dev_id;
1038
1039 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1040 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1041 wake_up(&msp->smi_busy_wait);
1042 return IRQ_HANDLED;
1043 }
1044
1045 return IRQ_NONE;
1046}
c9df406f 1047
45c5d3bc 1048static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1049{
45c5d3bc
LB		 1050 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1051}
1da177e4 1052
45c5d3bc
LB		 1053static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1054{
1055 if (msp->err_interrupt == NO_IRQ) {
1056 int i;
c9df406f 1057
45c5d3bc
LB		 1058 for (i = 0; !smi_is_done(msp); i++) {
1059 if (i == 10)
1060 return -ETIMEDOUT;
1061 msleep(10);
c9df406f 1062 }
45c5d3bc
LB		 1063
1064 return 0;
1065 }
1066
1067 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1068 msecs_to_jiffies(100)))
1069 return -ETIMEDOUT;
1070
1071 return 0;
1072}
1073
ed94493f 1074static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1075{
ed94493f 1076 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1077 void __iomem *smi_reg = msp->base + SMI_REG;
1078 int ret;
1079
45c5d3bc 1080 if (smi_wait_ready(msp)) {
ed94493f
LB		 1081 printk("mv643xx_eth: SMI bus busy timeout\n");
1082 return -ETIMEDOUT;
1da177e4
LT		 1083 }
1084
fc32b0e2 1085 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1086
45c5d3bc 1087 if (smi_wait_ready(msp)) {
ed94493f
LB		 1088 printk("mv643xx_eth: SMI bus busy timeout\n");
1089 return -ETIMEDOUT;
45c5d3bc
LB		 1090 }
1091
1092 ret = readl(smi_reg);
1093 if (!(ret & SMI_READ_VALID)) {
ed94493f
LB		 1094 printk("mv643xx_eth: SMI bus read not valid\n");
1095 return -ENODEV;
c9df406f
LB		 1096 }
1097
ed94493f 1098 return ret & 0xffff;
1da177e4
LT		 1099}
1100
ed94493f 1101static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1102{
ed94493f 1103 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1104 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1105
45c5d3bc 1106 if (smi_wait_ready(msp)) {
ed94493f 1107 printk("mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1108 return -ETIMEDOUT;
1da177e4
LT		 1109 }
1110
fc32b0e2 1111 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1112 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1113
ed94493f
LB		 1114 if (smi_wait_ready(msp)) {
1115 printk("mv643xx_eth: SMI bus busy timeout\n");
1116 return -ETIMEDOUT;
1117 }
45c5d3bc
LB		 1118
1119 return 0;
c9df406f 1120}
1da177e4 1121
c9df406f 1122
8fd89211
LB		 1123/* statistics ***************************************************************/
1124static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1125{
1126 struct mv643xx_eth_private *mp = netdev_priv(dev);
1127 struct net_device_stats *stats = &dev->stats;
1128 unsigned long tx_packets = 0;
1129 unsigned long tx_bytes = 0;
1130 unsigned long tx_dropped = 0;
1131 int i;
1132
1133 for (i = 0; i < mp->txq_count; i++) {
1134 struct tx_queue *txq = mp->txq + i;
1135
1136 tx_packets += txq->tx_packets;
1137 tx_bytes += txq->tx_bytes;
1138 tx_dropped += txq->tx_dropped;
1139 }
1140
1141 stats->tx_packets = tx_packets;
1142 stats->tx_bytes = tx_bytes;
1143 stats->tx_dropped = tx_dropped;
1144
1145 return stats;
1146}
1147
fc32b0e2 1148static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1149{
fc32b0e2 1150 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1151}
1152
fc32b0e2 1153static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1154{
fc32b0e2
LB		 1155 int i;
1156
1157 for (i = 0; i < 0x80; i += 4)
1158 mib_read(mp, i);
c9df406f 1159}
d0412d96 1160
fc32b0e2 1161static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1162{
e5371493 1163 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1164
4ff3495a 1165 spin_lock(&mp->mib_counters_lock);
fc32b0e2
LB		 1166 p->good_octets_received += mib_read(mp, 0x00);
1167 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1168 p->bad_octets_received += mib_read(mp, 0x08);
1169 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1170 p->good_frames_received += mib_read(mp, 0x10);
1171 p->bad_frames_received += mib_read(mp, 0x14);
1172 p->broadcast_frames_received += mib_read(mp, 0x18);
1173 p->multicast_frames_received += mib_read(mp, 0x1c);
1174 p->frames_64_octets += mib_read(mp, 0x20);
1175 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1176 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1177 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1178 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1179 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1180 p->good_octets_sent += mib_read(mp, 0x38);
1181 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1182 p->good_frames_sent += mib_read(mp, 0x40);
1183 p->excessive_collision += mib_read(mp, 0x44);
1184 p->multicast_frames_sent += mib_read(mp, 0x48);
1185 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1186 p->unrec_mac_control_received += mib_read(mp, 0x50);
1187 p->fc_sent += mib_read(mp, 0x54);
1188 p->good_fc_received += mib_read(mp, 0x58);
1189 p->bad_fc_received += mib_read(mp, 0x5c);
1190 p->undersize_received += mib_read(mp, 0x60);
1191 p->fragments_received += mib_read(mp, 0x64);
1192 p->oversize_received += mib_read(mp, 0x68);
1193 p->jabber_received += mib_read(mp, 0x6c);
1194 p->mac_receive_error += mib_read(mp, 0x70);
1195 p->bad_crc_event += mib_read(mp, 0x74);
1196 p->collision += mib_read(mp, 0x78);
1197 p->late_collision += mib_read(mp, 0x7c);
4ff3495a
LB		 1198 spin_unlock(&mp->mib_counters_lock);
1199
1200 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1201}
1202
1203static void mib_counters_timer_wrapper(unsigned long _mp)
1204{
1205 struct mv643xx_eth_private *mp = (void *)_mp;
1206
1207 mib_counters_update(mp);
d0412d96
JC		 1208}
1209
c9df406f
LB		 1210
1211/* ethtool ******************************************************************/
e5371493 1212struct mv643xx_eth_stats {
c9df406f
LB		 1213 char stat_string[ETH_GSTRING_LEN];
1214 int sizeof_stat;
16820054
LB		 1215 int netdev_off;
1216 int mp_off;
c9df406f
LB		 1217};
1218
16820054
LB		 1219#define SSTAT(m) \
1220 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1221 offsetof(struct net_device, stats.m), -1 }
1222
1223#define MIBSTAT(m) \
1224 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1225 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1226
1227static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1228 SSTAT(rx_packets),
1229 SSTAT(tx_packets),
1230 SSTAT(rx_bytes),
1231 SSTAT(tx_bytes),
1232 SSTAT(rx_errors),
1233 SSTAT(tx_errors),
1234 SSTAT(rx_dropped),
1235 SSTAT(tx_dropped),
1236 MIBSTAT(good_octets_received),
1237 MIBSTAT(bad_octets_received),
1238 MIBSTAT(internal_mac_transmit_err),
1239 MIBSTAT(good_frames_received),
1240 MIBSTAT(bad_frames_received),
1241 MIBSTAT(broadcast_frames_received),
1242 MIBSTAT(multicast_frames_received),
1243 MIBSTAT(frames_64_octets),
1244 MIBSTAT(frames_65_to_127_octets),
1245 MIBSTAT(frames_128_to_255_octets),
1246 MIBSTAT(frames_256_to_511_octets),
1247 MIBSTAT(frames_512_to_1023_octets),
1248 MIBSTAT(frames_1024_to_max_octets),
1249 MIBSTAT(good_octets_sent),
1250 MIBSTAT(good_frames_sent),
1251 MIBSTAT(excessive_collision),
1252 MIBSTAT(multicast_frames_sent),
1253 MIBSTAT(broadcast_frames_sent),
1254 MIBSTAT(unrec_mac_control_received),
1255 MIBSTAT(fc_sent),
1256 MIBSTAT(good_fc_received),
1257 MIBSTAT(bad_fc_received),
1258 MIBSTAT(undersize_received),
1259 MIBSTAT(fragments_received),
1260 MIBSTAT(oversize_received),
1261 MIBSTAT(jabber_received),
1262 MIBSTAT(mac_receive_error),
1263 MIBSTAT(bad_crc_event),
1264 MIBSTAT(collision),
1265 MIBSTAT(late_collision),
c9df406f
LB		 1266};
1267
e5371493 1268static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1269{
e5371493 1270 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1271 int err;
1272
ed94493f
LB		 1273 err = phy_read_status(mp->phy);
1274 if (err == 0)
1275 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1276
fc32b0e2
LB		 1277 /*
1278 * The MAC does not support 1000baseT_Half.
1279 */
d0412d96
JC		 1280 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1281 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1282
1283 return err;
1284}
1285
bedfe324
LB		 1286static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1287{
81600eea
LB		 1288 struct mv643xx_eth_private *mp = netdev_priv(dev);
1289 u32 port_status;
1290
1291 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1292
bedfe324
LB		 1293 cmd->supported = SUPPORTED_MII;
1294 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1295 switch (port_status & PORT_SPEED_MASK) {
1296 case PORT_SPEED_10:
1297 cmd->speed = SPEED_10;
1298 break;
1299 case PORT_SPEED_100:
1300 cmd->speed = SPEED_100;
1301 break;
1302 case PORT_SPEED_1000:
1303 cmd->speed = SPEED_1000;
1304 break;
1305 default:
1306 cmd->speed = -1;
1307 break;
1308 }
1309 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1310 cmd->port = PORT_MII;
1311 cmd->phy_address = 0;
1312 cmd->transceiver = XCVR_INTERNAL;
1313 cmd->autoneg = AUTONEG_DISABLE;
1314 cmd->maxtxpkt = 1;
1315 cmd->maxrxpkt = 1;
1316
1317 return 0;
1318}
1319
e5371493 1320static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1321{
e5371493 1322 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1323
fc32b0e2
LB		 1324 /*
1325 * The MAC does not support 1000baseT_Half.
1326 */
1327 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1328
ed94493f 1329 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1330}
1da177e4 1331
bedfe324
LB		 1332static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1333{
1334 return -EINVAL;
1335}
1336
fc32b0e2
LB		 1337static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1338 struct ethtool_drvinfo *drvinfo)
c9df406f 1339{
e5371493
LB		 1340 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1341 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1342 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1343 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1344 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1345}
1da177e4 1346
fc32b0e2 1347static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1348{
e5371493 1349 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1350
ed94493f 1351 return genphy_restart_aneg(mp->phy);
c9df406f 1352}
1da177e4 1353
bedfe324
LB		 1354static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1355{
1356 return -EINVAL;
1357}
1358
c9df406f
LB		 1359static u32 mv643xx_eth_get_link(struct net_device *dev)
1360{
ed94493f 1361 return !!netif_carrier_ok(dev);
bedfe324
LB		 1362}
1363
fc32b0e2
LB		 1364static void mv643xx_eth_get_strings(struct net_device *dev,
1365 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1366{
1367 int i;
1da177e4 1368
fc32b0e2
LB		 1369 if (stringset == ETH_SS_STATS) {
1370 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1371 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1372 mv643xx_eth_stats[i].stat_string,
e5371493 1373 ETH_GSTRING_LEN);
c9df406f 1374 }
c9df406f
LB		 1375 }
1376}
1da177e4 1377
fc32b0e2
LB		 1378static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1379 struct ethtool_stats *stats,
1380 uint64_t *data)
c9df406f 1381{
b9873841 1382 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1383 int i;
1da177e4 1384
8fd89211 1385 mv643xx_eth_get_stats(dev);
fc32b0e2 1386 mib_counters_update(mp);
1da177e4 1387
16820054
LB		 1388 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1389 const struct mv643xx_eth_stats *stat;
1390 void *p;
1391
1392 stat = mv643xx_eth_stats + i;
1393
1394 if (stat->netdev_off >= 0)
1395 p = ((void *)mp->dev) + stat->netdev_off;
1396 else
1397 p = ((void *)mp) + stat->mp_off;
1398
1399 data[i] = (stat->sizeof_stat == 8) ?
1400 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1401 }
c9df406f 1402}
1da177e4 1403
fc32b0e2 1404static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1405{
fc32b0e2 1406 if (sset == ETH_SS_STATS)
16820054 1407 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1408
1409 return -EOPNOTSUPP;
c9df406f 1410}
1da177e4 1411
e5371493 1412static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1413 .get_settings = mv643xx_eth_get_settings,
1414 .set_settings = mv643xx_eth_set_settings,
1415 .get_drvinfo = mv643xx_eth_get_drvinfo,
1416 .nway_reset = mv643xx_eth_nway_reset,
1417 .get_link = mv643xx_eth_get_link,
c9df406f 1418 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1419 .get_strings = mv643xx_eth_get_strings,
1420 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1421 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1422};
1da177e4 1423
bedfe324
LB		 1424static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1425 .get_settings = mv643xx_eth_get_settings_phyless,
1426 .set_settings = mv643xx_eth_set_settings_phyless,
1427 .get_drvinfo = mv643xx_eth_get_drvinfo,
1428 .nway_reset = mv643xx_eth_nway_reset_phyless,
ed94493f 1429 .get_link = mv643xx_eth_get_link,
bedfe324
LB		 1430 .set_sg = ethtool_op_set_sg,
1431 .get_strings = mv643xx_eth_get_strings,
1432 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1433 .get_sset_count = mv643xx_eth_get_sset_count,
1434};
1435
bea3348e 1436
c9df406f 1437/* address handling *********************************************************/
5daffe94 1438static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1439{
c9df406f
LB		 1440 unsigned int mac_h;
1441 unsigned int mac_l;
1da177e4 1442
fc32b0e2
LB		 1443 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1444 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1445
5daffe94
LB		 1446 addr[0] = (mac_h >> 24) & 0xff;
1447 addr[1] = (mac_h >> 16) & 0xff;
1448 addr[2] = (mac_h >> 8) & 0xff;
1449 addr[3] = mac_h & 0xff;
1450 addr[4] = (mac_l >> 8) & 0xff;
1451 addr[5] = mac_l & 0xff;
c9df406f 1452}
1da177e4 1453
e5371493 1454static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1455{
fc32b0e2 1456 int i;
1da177e4 1457
fc32b0e2
LB		 1458 for (i = 0; i < 0x100; i += 4) {
1459 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1460 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1461 }
fc32b0e2
LB		 1462
1463 for (i = 0; i < 0x10; i += 4)
1464 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1465}
d0412d96 1466
e5371493 1467static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1468 int table, unsigned char entry)
c9df406f
LB		 1469{
1470 unsigned int table_reg;
ab4384a6 1471
c9df406f 1472 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1473 table_reg = rdl(mp, table + (entry & 0xfc));
1474 table_reg |= 0x01 << (8 * (entry & 3));
1475 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1476}
1477
5daffe94 1478static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1479{
c9df406f
LB		 1480 unsigned int mac_h;
1481 unsigned int mac_l;
1482 int table;
1da177e4 1483
fc32b0e2
LB		 1484 mac_l = (addr[4] << 8) | addr[5];
1485 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1486
fc32b0e2
LB		 1487 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1488 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1489
fc32b0e2 1490 table = UNICAST_TABLE(mp->port_num);
5daffe94 1491 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1492}
1493
fc32b0e2 1494static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1495{
e5371493 1496 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1497
fc32b0e2
LB		 1498 /* +2 is for the offset of the HW addr type */
1499 memcpy(dev->dev_addr, addr + 2, 6);
1500
cc9754b3
LB		 1501 init_mac_tables(mp);
1502 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1503
1504 return 0;
1505}
1506
69876569
LB		 1507static int addr_crc(unsigned char *addr)
1508{
1509 int crc = 0;
1510 int i;
1511
1512 for (i = 0; i < 6; i++) {
1513 int j;
1514
1515 crc = (crc ^ addr[i]) << 8;
1516 for (j = 7; j >= 0; j--) {
1517 if (crc & (0x100 << j))
1518 crc ^= 0x107 << j;
1519 }
1520 }
1521
1522 return crc;
1523}
1524
fc32b0e2 1525static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1526{
fc32b0e2
LB		 1527 struct mv643xx_eth_private *mp = netdev_priv(dev);
1528 u32 port_config;
1529 struct dev_addr_list *addr;
1530 int i;
c8aaea25 1531
fc32b0e2
LB		 1532 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1533 if (dev->flags & IFF_PROMISC)
1534 port_config |= UNICAST_PROMISCUOUS_MODE;
1535 else
1536 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1537 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1538
fc32b0e2
LB		 1539 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1540 int port_num = mp->port_num;
1541 u32 accept = 0x01010101;
c8aaea25 1542
fc32b0e2
LB		 1543 for (i = 0; i < 0x100; i += 4) {
1544 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1545 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1546 }
1547 return;
1548 }
c8aaea25 1549
fc32b0e2
LB		 1550 for (i = 0; i < 0x100; i += 4) {
1551 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1552 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1553 }
1554
fc32b0e2
LB		 1555 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1556 u8 *a = addr->da_addr;
1557 int table;
324ff2c1 1558
fc32b0e2
LB		 1559 if (addr->da_addrlen != 6)
1560 continue;
1da177e4 1561
fc32b0e2
LB		 1562 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1563 table = SPECIAL_MCAST_TABLE(mp->port_num);
1564 set_filter_table_entry(mp, table, a[5]);
1565 } else {
1566 int crc = addr_crc(a);
1da177e4 1567
fc32b0e2
LB		 1568 table = OTHER_MCAST_TABLE(mp->port_num);
1569 set_filter_table_entry(mp, table, crc);
1570 }
1571 }
c9df406f 1572}
c8aaea25 1573
c8aaea25 1574
c9df406f 1575/* rx/tx queue initialisation ***********************************************/
64da80a2 1576static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1577{
64da80a2 1578 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1579 struct rx_desc *rx_desc;
1580 int size;
c9df406f
LB		 1581 int i;
1582
64da80a2
LB		 1583 rxq->index = index;
1584
8a578111
LB		 1585 rxq->rx_ring_size = mp->default_rx_ring_size;
1586
1587 rxq->rx_desc_count = 0;
1588 rxq->rx_curr_desc = 0;
1589 rxq->rx_used_desc = 0;
1590
1591 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1592
f7981c1c 1593 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1594 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1595 mp->rx_desc_sram_size);
1596 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1597 } else {
1598 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1599 &rxq->rx_desc_dma,
1600 GFP_KERNEL);
f7ea3337
PJ		 1601 }
1602
8a578111
LB		 1603 if (rxq->rx_desc_area == NULL) {
1604 dev_printk(KERN_ERR, &mp->dev->dev,
1605 "can't allocate rx ring (%d bytes)\n", size);
1606 goto out;
1607 }
1608 memset(rxq->rx_desc_area, 0, size);
1da177e4 1609
8a578111
LB		 1610 rxq->rx_desc_area_size = size;
1611 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1612 GFP_KERNEL);
1613 if (rxq->rx_skb == NULL) {
1614 dev_printk(KERN_ERR, &mp->dev->dev,
1615 "can't allocate rx skb ring\n");
1616 goto out_free;
1617 }
1618
1619 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1620 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1621 int nexti;
1622
1623 nexti = i + 1;
1624 if (nexti == rxq->rx_ring_size)
1625 nexti = 0;
1626
8a578111
LB		 1627 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1628 nexti * sizeof(struct rx_desc);
1629 }
1630
8a578111
LB		 1631 return 0;
1632
1633
1634out_free:
f7981c1c 1635 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1636 iounmap(rxq->rx_desc_area);
1637 else
1638 dma_free_coherent(NULL, size,
1639 rxq->rx_desc_area,
1640 rxq->rx_desc_dma);
1641
1642out:
1643 return -ENOMEM;
c9df406f 1644}
c8aaea25 1645
8a578111 1646static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1647{
8a578111
LB		 1648 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1649 int i;
1650
1651 rxq_disable(rxq);
c8aaea25 1652
8a578111
LB		 1653 for (i = 0; i < rxq->rx_ring_size; i++) {
1654 if (rxq->rx_skb[i]) {
1655 dev_kfree_skb(rxq->rx_skb[i]);
1656 rxq->rx_desc_count--;
1da177e4 1657 }
c8aaea25 1658 }
1da177e4 1659
8a578111
LB		 1660 if (rxq->rx_desc_count) {
1661 dev_printk(KERN_ERR, &mp->dev->dev,
1662 "error freeing rx ring -- %d skbs stuck\n",
1663 rxq->rx_desc_count);
1664 }
1665
f7981c1c 1666 if (rxq->index == 0 &&
64da80a2 1667 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1668 iounmap(rxq->rx_desc_area);
c9df406f 1669 else
8a578111
LB		 1670 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1671 rxq->rx_desc_area, rxq->rx_desc_dma);
1672
1673 kfree(rxq->rx_skb);
c9df406f 1674}
1da177e4 1675
3d6b35bc 1676static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1677{
3d6b35bc 1678 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1679 struct tx_desc *tx_desc;
1680 int size;
c9df406f 1681 int i;
1da177e4 1682
3d6b35bc
LB		 1683 txq->index = index;
1684
13d64285
LB		 1685 txq->tx_ring_size = mp->default_tx_ring_size;
1686
1687 txq->tx_desc_count = 0;
1688 txq->tx_curr_desc = 0;
1689 txq->tx_used_desc = 0;
1690
1691 size = txq->tx_ring_size * sizeof(struct tx_desc);
1692
f7981c1c 1693 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1694 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1695 mp->tx_desc_sram_size);
1696 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1697 } else {
1698 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1699 &txq->tx_desc_dma,
1700 GFP_KERNEL);
1701 }
1702
1703 if (txq->tx_desc_area == NULL) {
1704 dev_printk(KERN_ERR, &mp->dev->dev,
1705 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1706 return -ENOMEM;
c9df406f 1707 }
13d64285
LB		 1708 memset(txq->tx_desc_area, 0, size);
1709
1710 txq->tx_desc_area_size = size;
13d64285
LB		 1711
1712 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1713 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1714 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1715 int nexti;
1716
1717 nexti = i + 1;
1718 if (nexti == txq->tx_ring_size)
1719 nexti = 0;
6b368f68
LB		 1720
1721 txd->cmd_sts = 0;
1722 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1723 nexti * sizeof(struct tx_desc);
1724 }
1725
99ab08e0 1726 skb_queue_head_init(&txq->tx_skb);
c9df406f 1727
99ab08e0 1728 return 0;
c8aaea25 1729}
1da177e4 1730
13d64285 1731static void txq_deinit(struct tx_queue *txq)
c9df406f 1732{
13d64285 1733 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1734
13d64285 1735 txq_disable(txq);
1fa38c58 1736 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1737
13d64285 1738 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1739
f7981c1c 1740 if (txq->index == 0 &&
3d6b35bc 1741 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1742 iounmap(txq->tx_desc_area);
c9df406f 1743 else
13d64285
LB		 1744 dma_free_coherent(NULL, txq->tx_desc_area_size,
1745 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1746}
1da177e4 1747
1da177e4 1748
c9df406f 1749/* netdev ops and related ***************************************************/
1fa38c58
LB		 1750static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1751{
1752 u32 int_cause;
1753 u32 int_cause_ext;
1754
1755 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1756 (INT_TX_END | INT_RX | INT_EXT);
1757 if (int_cause == 0)
1758 return 0;
1759
1760 int_cause_ext = 0;
1761 if (int_cause & INT_EXT)
1762 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1763
1764 int_cause &= INT_TX_END | INT_RX;
1765 if (int_cause) {
1766 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1767 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1768 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1769 mp->work_rx |= (int_cause & INT_RX) >> 2;
1770 }
1771
1772 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1773 if (int_cause_ext) {
1774 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1775 if (int_cause_ext & INT_EXT_LINK_PHY)
1776 mp->work_link = 1;
1777 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1778 }
1779
1780 return 1;
1781}
1782
1783static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1784{
1785 struct net_device *dev = (struct net_device *)dev_id;
1786 struct mv643xx_eth_private *mp = netdev_priv(dev);
1787
1788 if (unlikely(!mv643xx_eth_collect_events(mp)))
1789 return IRQ_NONE;
1790
1791 wrl(mp, INT_MASK(mp->port_num), 0);
1792 napi_schedule(&mp->napi);
1793
1794 return IRQ_HANDLED;
1795}
1796
2f7eb47a
LB		 1797static void handle_link_event(struct mv643xx_eth_private *mp)
1798{
1799 struct net_device *dev = mp->dev;
1800 u32 port_status;
1801 int speed;
1802 int duplex;
1803 int fc;
1804
1805 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1806 if (!(port_status & LINK_UP)) {
1807 if (netif_carrier_ok(dev)) {
1808 int i;
1809
1810 printk(KERN_INFO "%s: link down\n", dev->name);
1811
1812 netif_carrier_off(dev);
2f7eb47a 1813
f7981c1c 1814 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1815 struct tx_queue *txq = mp->txq + i;
1816
1fa38c58 1817 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1818 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1819 }
1820 }
1821 return;
1822 }
1823
1824 switch (port_status & PORT_SPEED_MASK) {
1825 case PORT_SPEED_10:
1826 speed = 10;
1827 break;
1828 case PORT_SPEED_100:
1829 speed = 100;
1830 break;
1831 case PORT_SPEED_1000:
1832 speed = 1000;
1833 break;
1834 default:
1835 speed = -1;
1836 break;
1837 }
1838 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1839 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1840
1841 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1842 "flow control %sabled\n", dev->name,
1843 speed, duplex ? "full" : "half",
1844 fc ? "en" : "dis");
1845
4fdeca3f 1846 if (!netif_carrier_ok(dev))
2f7eb47a 1847 netif_carrier_on(dev);
2f7eb47a
LB		 1848}
1849
1fa38c58 1850static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1851{
1fa38c58
LB		 1852 struct mv643xx_eth_private *mp;
1853 int work_done;
ce4e2e45 1854
1fa38c58 1855 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1856
1fa38c58
LB		 1857 mp->work_rx_refill |= mp->work_rx_oom;
1858 mp->work_rx_oom = 0;
1da177e4 1859
1fa38c58
LB		 1860 work_done = 0;
1861 while (work_done < budget) {
1862 u8 queue_mask;
1863 int queue;
1864 int work_tbd;
1865
1866 if (mp->work_link) {
1867 mp->work_link = 0;
1868 handle_link_event(mp);
1869 continue;
1870 }
1da177e4 1871
1fa38c58
LB		 1872 queue_mask = mp->work_tx | mp->work_tx_end |
1873 mp->work_rx | mp->work_rx_refill;
1874 if (!queue_mask) {
1875 if (mv643xx_eth_collect_events(mp))
1876 continue;
1877 break;
1878 }
1da177e4 1879
1fa38c58
LB		 1880 queue = fls(queue_mask) - 1;
1881 queue_mask = 1 << queue;
1882
1883 work_tbd = budget - work_done;
1884 if (work_tbd > 16)
1885 work_tbd = 16;
1886
1887 if (mp->work_tx_end & queue_mask) {
1888 txq_kick(mp->txq + queue);
1889 } else if (mp->work_tx & queue_mask) {
1890 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1891 txq_maybe_wake(mp->txq + queue);
1892 } else if (mp->work_rx & queue_mask) {
1893 work_done += rxq_process(mp->rxq + queue, work_tbd);
1894 } else if (mp->work_rx_refill & queue_mask) {
1895 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1896 } else {
1897 BUG();
1898 }
84dd619e 1899 }
fc32b0e2 1900
1fa38c58
LB		 1901 if (work_done < budget) {
1902 if (mp->work_rx_oom)
1903 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1904 napi_complete(napi);
1905 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1906 }
3d6b35bc 1907
1fa38c58
LB		 1908 return work_done;
1909}
8fa89bf5 1910
1fa38c58
LB		 1911static inline void oom_timer_wrapper(unsigned long data)
1912{
1913 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1914
1fa38c58 1915 napi_schedule(&mp->napi);
1da177e4
LT		 1916}
1917
e5371493 1918static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1919{
45c5d3bc
LB		 1920 int data;
1921
ed94493f 1922 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 1923 if (data < 0)
1924 return;
1da177e4 1925
7f106c1d 1926 data |= BMCR_RESET;
ed94493f 1927 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 1928 return;
1da177e4 1929
c9df406f 1930 do {
ed94493f 1931 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 1932 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1933}
1934
fc32b0e2 1935static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1936{
d0412d96 1937 u32 pscr;
8a578111 1938 int i;
1da177e4 1939
bedfe324
LB		 1940 /*
1941 * Perform PHY reset, if there is a PHY.
1942 */
ed94493f 1943 if (mp->phy != NULL) {
bedfe324
LB		 1944 struct ethtool_cmd cmd;
1945
1946 mv643xx_eth_get_settings(mp->dev, &cmd);
1947 phy_reset(mp);
1948 mv643xx_eth_set_settings(mp->dev, &cmd);
1949 }
1da177e4 1950
81600eea
LB		 1951 /*
1952 * Configure basic link parameters.
1953 */
1954 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1955
1956 pscr |= SERIAL_PORT_ENABLE;
1957 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1958
1959 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 1960 if (mp->phy == NULL)
81600eea
LB		 1961 pscr |= FORCE_LINK_PASS;
1962 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1963
1964 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1965
13d64285
LB		 1966 /*
1967 * Configure TX path and queues.
1968 */
89df5fdc 1969 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 1970 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 1971 struct tx_queue *txq = mp->txq + i;
13d64285 1972
6b368f68 1973 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1974 txq_set_rate(txq, 1000000000, 16777216);
1975 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1976 }
1977
fc32b0e2
LB		 1978 /*
1979 * Add configured unicast address to address filter table.
1980 */
1981 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1982
d9a073ea
LB		 1983 /*
1984 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 1985 * frames to RX queue #0, and include the pseudo-header when
1986 * calculating receive checksums.
d9a073ea 1987 */
170e7108 1988 wrl(mp, PORT_CONFIG(mp->port_num), 0x02000000);
01999873 1989
376489a2
LB		 1990 /*
1991 * Treat BPDUs as normal multicasts, and disable partition mode.
1992 */
8a578111 1993 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1994
8a578111 1995 /*
64da80a2 1996 * Enable the receive queues.
8a578111 1997 */
f7981c1c 1998 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 1999 struct rx_queue *rxq = mp->rxq + i;
2000 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 2001 u32 addr;
1da177e4 2002
8a578111
LB		 2003 addr = (u32)rxq->rx_desc_dma;
2004 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2005 wrl(mp, off, addr);
1da177e4 2006
8a578111
LB		 2007 rxq_enable(rxq);
2008 }
1da177e4
LT		 2009}
2010
ffd86bbe 2011static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2012{
c9df406f 2013 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2014 u32 val;
1da177e4 2015
773fc3ee
LB		 2016 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2017 if (mp->shared->extended_rx_coal_limit) {
2018 if (coal > 0xffff)
2019 coal = 0xffff;
2020 val &= ~0x023fff80;
2021 val |= (coal & 0x8000) << 10;
2022 val |= (coal & 0x7fff) << 7;
2023 } else {
2024 if (coal > 0x3fff)
2025 coal = 0x3fff;
2026 val &= ~0x003fff00;
2027 val |= (coal & 0x3fff) << 8;
2028 }
2029 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 2030}
2031
ffd86bbe 2032static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2033{
c9df406f 2034 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2035
fc32b0e2
LB		 2036 if (coal > 0x3fff)
2037 coal = 0x3fff;
2038 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 2039}
2040
2bcb4b0f
LB		 2041static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2042{
2043 int skb_size;
2044
2045 /*
2046 * Reserve 2+14 bytes for an ethernet header (the hardware
2047 * automatically prepends 2 bytes of dummy data to each
2048 * received packet), 16 bytes for up to four VLAN tags, and
2049 * 4 bytes for the trailing FCS -- 36 bytes total.
2050 */
2051 skb_size = mp->dev->mtu + 36;
2052
2053 /*
2054 * Make sure that the skb size is a multiple of 8 bytes, as
2055 * the lower three bits of the receive descriptor's buffer
2056 * size field are ignored by the hardware.
2057 */
2058 mp->skb_size = (skb_size + 7) & ~7;
2059}
2060
c9df406f 2061static int mv643xx_eth_open(struct net_device *dev)
16e03018 2062{
e5371493 2063 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2064 int err;
64da80a2 2065 int i;
16e03018 2066
fc32b0e2
LB		 2067 wrl(mp, INT_CAUSE(mp->port_num), 0);
2068 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2069 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 2070
fc32b0e2 2071 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2072 IRQF_SHARED, dev->name, dev);
c9df406f 2073 if (err) {
fc32b0e2 2074 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2075 return -EAGAIN;
16e03018
DF		 2076 }
2077
fc32b0e2 2078 init_mac_tables(mp);
16e03018 2079
2bcb4b0f
LB		 2080 mv643xx_eth_recalc_skb_size(mp);
2081
2257e05c
LB		 2082 napi_enable(&mp->napi);
2083
2bcb4b0f
LB		 2084 skb_queue_head_init(&mp->rx_recycle);
2085
f7981c1c 2086 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2087 err = rxq_init(mp, i);
2088 if (err) {
2089 while (--i >= 0)
f7981c1c 2090 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2091 goto out;
2092 }
2093
1fa38c58 2094 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2095 }
2096
1fa38c58 2097 if (mp->work_rx_oom) {
2257e05c
LB		 2098 mp->rx_oom.expires = jiffies + (HZ / 10);
2099 add_timer(&mp->rx_oom);
64da80a2 2100 }
8a578111 2101
f7981c1c 2102 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2103 err = txq_init(mp, i);
2104 if (err) {
2105 while (--i >= 0)
f7981c1c 2106 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2107 goto out_free;
2108 }
2109 }
16e03018 2110
2f7eb47a 2111 netif_carrier_off(dev);
2f7eb47a 2112
fc32b0e2 2113 port_start(mp);
16e03018 2114
ffd86bbe
LB		 2115 set_rx_coal(mp, 0);
2116 set_tx_coal(mp, 0);
16e03018 2117
befefe21 2118 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
226bb6b7 2119 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2120
c9df406f
LB		 2121 return 0;
2122
13d64285 2123
fc32b0e2 2124out_free:
f7981c1c
LB		 2125 for (i = 0; i < mp->rxq_count; i++)
2126 rxq_deinit(mp->rxq + i);
fc32b0e2 2127out:
c9df406f
LB		 2128 free_irq(dev->irq, dev);
2129
2130 return err;
16e03018
DF		 2131}
2132
e5371493 2133static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2134{
fc32b0e2 2135 unsigned int data;
64da80a2 2136 int i;
1da177e4 2137
f7981c1c
LB		 2138 for (i = 0; i < mp->rxq_count; i++)
2139 rxq_disable(mp->rxq + i);
2140 for (i = 0; i < mp->txq_count; i++)
2141 txq_disable(mp->txq + i);
ae9ae064
LB		 2142
2143 while (1) {
2144 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2145
2146 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2147 break;
13d64285 2148 udelay(10);
ae9ae064 2149 }
1da177e4 2150
c9df406f 2151 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2152 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2153 data &= ~(SERIAL_PORT_ENABLE |
2154 DO_NOT_FORCE_LINK_FAIL |
2155 FORCE_LINK_PASS);
2156 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2157}
2158
c9df406f 2159static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2160{
e5371493 2161 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2162 int i;
1da177e4 2163
fc32b0e2
LB		 2164 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2165 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2166
4ff3495a
LB		 2167 del_timer_sync(&mp->mib_counters_timer);
2168
c9df406f 2169 napi_disable(&mp->napi);
78fff83b 2170
2257e05c
LB		 2171 del_timer_sync(&mp->rx_oom);
2172
c9df406f 2173 netif_carrier_off(dev);
1da177e4 2174
fc32b0e2
LB		 2175 free_irq(dev->irq, dev);
2176
cc9754b3 2177 port_reset(mp);
8fd89211 2178 mv643xx_eth_get_stats(dev);
fc32b0e2 2179 mib_counters_update(mp);
1da177e4 2180
2bcb4b0f
LB		 2181 skb_queue_purge(&mp->rx_recycle);
2182
f7981c1c
LB		 2183 for (i = 0; i < mp->rxq_count; i++)
2184 rxq_deinit(mp->rxq + i);
2185 for (i = 0; i < mp->txq_count; i++)
2186 txq_deinit(mp->txq + i);
1da177e4 2187
c9df406f 2188 return 0;
1da177e4
LT		 2189}
2190
fc32b0e2 2191static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2192{
e5371493 2193 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2194
ed94493f
LB		 2195 if (mp->phy != NULL)
2196 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2197
2198 return -EOPNOTSUPP;
1da177e4
LT		 2199}
2200
c9df406f 2201static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2202{
89df5fdc
LB		 2203 struct mv643xx_eth_private *mp = netdev_priv(dev);
2204
fc32b0e2 2205 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2206 return -EINVAL;
1da177e4 2207
c9df406f 2208 dev->mtu = new_mtu;
2bcb4b0f 2209 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2210 tx_set_rate(mp, 1000000000, 16777216);
2211
c9df406f
LB		 2212 if (!netif_running(dev))
2213 return 0;
1da177e4 2214
c9df406f
LB		 2215 /*
2216 * Stop and then re-open the interface. This will allocate RX
2217 * skbs of the new MTU.
2218 * There is a possible danger that the open will not succeed,
fc32b0e2 2219 * due to memory being full.
c9df406f
LB		 2220 */
2221 mv643xx_eth_stop(dev);
2222 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2223 dev_printk(KERN_ERR, &dev->dev,
2224 "fatal error on re-opening device after "
2225 "MTU change\n");
c9df406f
LB		 2226 }
2227
2228 return 0;
1da177e4
LT		 2229}
2230
fc32b0e2 2231static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2232{
fc32b0e2 2233 struct mv643xx_eth_private *mp;
1da177e4 2234
fc32b0e2
LB		 2235 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2236 if (netif_running(mp->dev)) {
e5ef1de1 2237 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2238 port_reset(mp);
2239 port_start(mp);
e5ef1de1 2240 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2241 }
c9df406f
LB		 2242}
2243
c9df406f 2244static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2245{
e5371493 2246 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2247
fc32b0e2 2248 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2249
c9df406f 2250 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2251}
2252
c9df406f 2253#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2254static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2255{
fc32b0e2 2256 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2257
fc32b0e2
LB		 2258 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2259 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2260
fc32b0e2 2261 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2262
f2ca60f2 2263 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2264}
c9df406f 2265#endif
9f8dd319 2266
9f8dd319 2267
c9df406f 2268/* platform glue ************************************************************/
e5371493
LB		 2269static void
2270mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2271 struct mbus_dram_target_info *dram)
c9df406f 2272{
cc9754b3 2273 void __iomem *base = msp->base;
c9df406f
LB		 2274 u32 win_enable;
2275 u32 win_protect;
2276 int i;
9f8dd319 2277
c9df406f
LB		 2278 for (i = 0; i < 6; i++) {
2279 writel(0, base + WINDOW_BASE(i));
2280 writel(0, base + WINDOW_SIZE(i));
2281 if (i < 4)
2282 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2283 }
2284
c9df406f
LB		 2285 win_enable = 0x3f;
2286 win_protect = 0;
2287
2288 for (i = 0; i < dram->num_cs; i++) {
2289 struct mbus_dram_window *cs = dram->cs + i;
2290
2291 writel((cs->base & 0xffff0000) |
2292 (cs->mbus_attr << 8) |
2293 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2294 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2295
2296 win_enable &= ~(1 << i);
2297 win_protect |= 3 << (2 * i);
2298 }
2299
2300 writel(win_enable, base + WINDOW_BAR_ENABLE);
2301 msp->win_protect = win_protect;
9f8dd319
DF		 2302}
2303
773fc3ee
LB		 2304static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2305{
2306 /*
2307 * Check whether we have a 14-bit coal limit field in bits
2308 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2309 * SDMA config register.
2310 */
2311 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2312 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2313 msp->extended_rx_coal_limit = 1;
2314 else
2315 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2316
2317 /*
457b1d5a
LB		 2318 * Check whether the MAC supports TX rate control, and if
2319 * yes, whether its associated registers are in the old or
2320 * the new place.
1e881592
LB		 2321 */
2322 writel(1, msp->base + TX_BW_MTU_MOVED(0));
457b1d5a
LB		 2323 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) {
2324 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2325 } else {
2326 writel(7, msp->base + TX_BW_RATE(0));
2327 if (readl(msp->base + TX_BW_RATE(0)) & 7)
2328 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2329 else
2330 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2331 }
773fc3ee
LB		 2332}
2333
c9df406f 2334static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2335{
e5371493 2336 static int mv643xx_eth_version_printed = 0;
c9df406f 2337 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2338 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2339 struct resource *res;
2340 int ret;
9f8dd319 2341
e5371493 2342 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2343 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2344 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2345
c9df406f
LB		 2346 ret = -EINVAL;
2347 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2348 if (res == NULL)
2349 goto out;
9f8dd319 2350
c9df406f
LB		 2351 ret = -ENOMEM;
2352 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2353 if (msp == NULL)
2354 goto out;
2355 memset(msp, 0, sizeof(*msp));
2356
cc9754b3
LB		 2357 msp->base = ioremap(res->start, res->end - res->start + 1);
2358 if (msp->base == NULL)
c9df406f
LB		 2359 goto out_free;
2360
ed94493f
LB		 2361 /*
2362 * Set up and register SMI bus.
2363 */
2364 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2365 msp->smi_bus = mdiobus_alloc();
2366 if (msp->smi_bus == NULL)
ed94493f 2367 goto out_unmap;
298cf9be
LB		 2368
2369 msp->smi_bus->priv = msp;
2370 msp->smi_bus->name = "mv643xx_eth smi";
2371 msp->smi_bus->read = smi_bus_read;
2372 msp->smi_bus->write = smi_bus_write,
2373 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2374 msp->smi_bus->parent = &pdev->dev;
2375 msp->smi_bus->phy_mask = 0xffffffff;
2376 if (mdiobus_register(msp->smi_bus) < 0)
2377 goto out_free_mii_bus;
ed94493f
LB		 2378 msp->smi = msp;
2379 } else {
fc0eb9f2 2380 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2381 }
c9df406f 2382
45c5d3bc
LB		 2383 msp->err_interrupt = NO_IRQ;
2384 init_waitqueue_head(&msp->smi_busy_wait);
2385
2386 /*
2387 * Check whether the error interrupt is hooked up.
2388 */
2389 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2390 if (res != NULL) {
2391 int err;
2392
2393 err = request_irq(res->start, mv643xx_eth_err_irq,
2394 IRQF_SHARED, "mv643xx_eth", msp);
2395 if (!err) {
2396 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2397 msp->err_interrupt = res->start;
2398 }
2399 }
2400
c9df406f
LB		 2401 /*
2402 * (Re-)program MBUS remapping windows if we are asked to.
2403 */
2404 if (pd != NULL && pd->dram != NULL)
2405 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2406
fc32b0e2
LB		 2407 /*
2408 * Detect hardware parameters.
2409 */
2410 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2411 infer_hw_params(msp);
fc32b0e2
LB		 2412
2413 platform_set_drvdata(pdev, msp);
2414
c9df406f
LB		 2415 return 0;
2416
298cf9be
LB		 2417out_free_mii_bus:
2418 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2419out_unmap:
2420 iounmap(msp->base);
c9df406f
LB		 2421out_free:
2422 kfree(msp);
2423out:
2424 return ret;
2425}
2426
2427static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2428{
e5371493 2429 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2430 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2431
298cf9be
LB		 2432 if (pd == NULL || pd->shared_smi == NULL) {
2433 mdiobus_free(msp->smi_bus);
2434 mdiobus_unregister(msp->smi_bus);
2435 }
45c5d3bc
LB		 2436 if (msp->err_interrupt != NO_IRQ)
2437 free_irq(msp->err_interrupt, msp);
cc9754b3 2438 iounmap(msp->base);
c9df406f
LB		 2439 kfree(msp);
2440
2441 return 0;
9f8dd319
DF		 2442}
2443
c9df406f 2444static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2445 .probe = mv643xx_eth_shared_probe,
2446 .remove = mv643xx_eth_shared_remove,
c9df406f 2447 .driver = {
fc32b0e2 2448 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2449 .owner = THIS_MODULE,
2450 },
2451};
2452
e5371493 2453static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2454{
c9df406f 2455 int addr_shift = 5 * mp->port_num;
fc32b0e2 2456 u32 data;
1da177e4 2457
fc32b0e2
LB		 2458 data = rdl(mp, PHY_ADDR);
2459 data &= ~(0x1f << addr_shift);
2460 data |= (phy_addr & 0x1f) << addr_shift;
2461 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2462}
2463
e5371493 2464static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2465{
fc32b0e2
LB		 2466 unsigned int data;
2467
2468 data = rdl(mp, PHY_ADDR);
2469
2470 return (data >> (5 * mp->port_num)) & 0x1f;
2471}
2472
2473static void set_params(struct mv643xx_eth_private *mp,
2474 struct mv643xx_eth_platform_data *pd)
2475{
2476 struct net_device *dev = mp->dev;
2477
2478 if (is_valid_ether_addr(pd->mac_addr))
2479 memcpy(dev->dev_addr, pd->mac_addr, 6);
2480 else
2481 uc_addr_get(mp, dev->dev_addr);
2482
fc32b0e2
LB		 2483 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2484 if (pd->rx_queue_size)
2485 mp->default_rx_ring_size = pd->rx_queue_size;
2486 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2487 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2488
f7981c1c 2489 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2490
fc32b0e2
LB		 2491 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2492 if (pd->tx_queue_size)
2493 mp->default_tx_ring_size = pd->tx_queue_size;
2494 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2495 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2496
f7981c1c 2497 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2498}
2499
ed94493f
LB		 2500static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2501 int phy_addr)
1da177e4 2502{
298cf9be 2503 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2504 struct phy_device *phydev;
2505 int start;
2506 int num;
2507 int i;
45c5d3bc 2508
ed94493f
LB		 2509 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2510 start = phy_addr_get(mp) & 0x1f;
2511 num = 32;
2512 } else {
2513 start = phy_addr & 0x1f;
2514 num = 1;
2515 }
45c5d3bc 2516
ed94493f
LB		 2517 phydev = NULL;
2518 for (i = 0; i < num; i++) {
2519 int addr = (start + i) & 0x1f;
fc32b0e2 2520
ed94493f
LB		 2521 if (bus->phy_map[addr] == NULL)
2522 mdiobus_scan(bus, addr);
1da177e4 2523
ed94493f
LB		 2524 if (phydev == NULL) {
2525 phydev = bus->phy_map[addr];
2526 if (phydev != NULL)
2527 phy_addr_set(mp, addr);
2528 }
2529 }
1da177e4 2530
ed94493f 2531 return phydev;
1da177e4
LT		 2532}
2533
ed94493f 2534static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2535{
ed94493f 2536 struct phy_device *phy = mp->phy;
c28a4f89 2537
fc32b0e2
LB		 2538 phy_reset(mp);
2539
ed94493f
LB		 2540 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2541
2542 if (speed == 0) {
2543 phy->autoneg = AUTONEG_ENABLE;
2544 phy->speed = 0;
2545 phy->duplex = 0;
2546 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2547 } else {
ed94493f
LB		 2548 phy->autoneg = AUTONEG_DISABLE;
2549 phy->advertising = 0;
2550 phy->speed = speed;
2551 phy->duplex = duplex;
c9df406f 2552 }
ed94493f 2553 phy_start_aneg(phy);
c28a4f89
JC		 2554}
2555
81600eea
LB		 2556static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2557{
2558 u32 pscr;
2559
2560 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2561 if (pscr & SERIAL_PORT_ENABLE) {
2562 pscr &= ~SERIAL_PORT_ENABLE;
2563 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2564 }
2565
2566 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2567 if (mp->phy == NULL) {
81600eea
LB		 2568 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2569 if (speed == SPEED_1000)
2570 pscr |= SET_GMII_SPEED_TO_1000;
2571 else if (speed == SPEED_100)
2572 pscr |= SET_MII_SPEED_TO_100;
2573
2574 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2575
2576 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2577 if (duplex == DUPLEX_FULL)
2578 pscr |= SET_FULL_DUPLEX_MODE;
2579 }
2580
2581 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2582}
2583
c9df406f 2584static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2585{
c9df406f 2586 struct mv643xx_eth_platform_data *pd;
e5371493 2587 struct mv643xx_eth_private *mp;
c9df406f 2588 struct net_device *dev;
c9df406f 2589 struct resource *res;
fc32b0e2 2590 int err;
1da177e4 2591
c9df406f
LB		 2592 pd = pdev->dev.platform_data;
2593 if (pd == NULL) {
fc32b0e2
LB		 2594 dev_printk(KERN_ERR, &pdev->dev,
2595 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2596 return -ENODEV;
2597 }
1da177e4 2598
c9df406f 2599 if (pd->shared == NULL) {
fc32b0e2
LB		 2600 dev_printk(KERN_ERR, &pdev->dev,
2601 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2602 return -ENODEV;
2603 }
8f518703 2604
e5ef1de1 2605 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2606 if (!dev)
2607 return -ENOMEM;
1da177e4 2608
c9df406f 2609 mp = netdev_priv(dev);
fc32b0e2
LB		 2610 platform_set_drvdata(pdev, mp);
2611
2612 mp->shared = platform_get_drvdata(pd->shared);
2613 mp->port_num = pd->port_number;
2614
c9df406f 2615 mp->dev = dev;
78fff83b 2616
fc32b0e2 2617 set_params(mp, pd);
e5ef1de1 2618 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2619
ed94493f
LB		 2620 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2621 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2622
ed94493f
LB		 2623 if (mp->phy != NULL) {
2624 phy_init(mp, pd->speed, pd->duplex);
bedfe324
LB		 2625 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2626 } else {
2627 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2628 }
ed94493f 2629
81600eea 2630 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2631
4ff3495a
LB		 2632
2633 mib_counters_clear(mp);
2634
2635 init_timer(&mp->mib_counters_timer);
2636 mp->mib_counters_timer.data = (unsigned long)mp;
2637 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2638 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2639 add_timer(&mp->mib_counters_timer);
2640
2641 spin_lock_init(&mp->mib_counters_lock);
2642
2643 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2644
2257e05c
LB		 2645 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2646
2647 init_timer(&mp->rx_oom);
2648 mp->rx_oom.data = (unsigned long)mp;
2649 mp->rx_oom.function = oom_timer_wrapper;
2650
fc32b0e2 2651
c9df406f
LB		 2652 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2653 BUG_ON(!res);
2654 dev->irq = res->start;
1da177e4 2655
8fd89211 2656 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2657 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2658 dev->open = mv643xx_eth_open;
2659 dev->stop = mv643xx_eth_stop;
c9df406f 2660 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2661 dev->set_mac_address = mv643xx_eth_set_mac_address;
2662 dev->do_ioctl = mv643xx_eth_ioctl;
2663 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2664 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2665#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2666 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2667#endif
c9df406f
LB		 2668 dev->watchdog_timeo = 2 * HZ;
2669 dev->base_addr = 0;
1da177e4 2670
c9df406f 2671 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2672 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2673
fc32b0e2 2674 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2675
c9df406f 2676 if (mp->shared->win_protect)
fc32b0e2 2677 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2678
c9df406f
LB		 2679 err = register_netdev(dev);
2680 if (err)
2681 goto out;
1da177e4 2682
e174961c
JB		 2683 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2684 mp->port_num, dev->dev_addr);
1da177e4 2685
13d64285 2686 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2687 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2688
c9df406f 2689 return 0;
1da177e4 2690
c9df406f
LB		 2691out:
2692 free_netdev(dev);
1da177e4 2693
c9df406f 2694 return err;
1da177e4
LT		 2695}
2696
c9df406f 2697static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2698{
fc32b0e2 2699 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2700
fc32b0e2 2701 unregister_netdev(mp->dev);
ed94493f
LB		 2702 if (mp->phy != NULL)
2703 phy_detach(mp->phy);
c9df406f 2704 flush_scheduled_work();
fc32b0e2 2705 free_netdev(mp->dev);
c9df406f 2706
c9df406f 2707 platform_set_drvdata(pdev, NULL);
fc32b0e2 2708
c9df406f 2709 return 0;
1da177e4
LT		 2710}
2711
c9df406f 2712static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2713{
fc32b0e2 2714 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2715
c9df406f 2716 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2717 wrl(mp, INT_MASK(mp->port_num), 0);
2718 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2719
fc32b0e2
LB		 2720 if (netif_running(mp->dev))
2721 port_reset(mp);
d0412d96
JC		 2722}
2723
c9df406f 2724static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2725 .probe = mv643xx_eth_probe,
2726 .remove = mv643xx_eth_remove,
2727 .shutdown = mv643xx_eth_shutdown,
c9df406f 2728 .driver = {
fc32b0e2 2729 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2730 .owner = THIS_MODULE,
2731 },
2732};
2733
e5371493 2734static int __init mv643xx_eth_init_module(void)
d0412d96 2735{
c9df406f 2736 int rc;
d0412d96 2737
c9df406f
LB		 2738 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2739 if (!rc) {
2740 rc = platform_driver_register(&mv643xx_eth_driver);
2741 if (rc)
2742 platform_driver_unregister(&mv643xx_eth_shared_driver);
2743 }
fc32b0e2 2744
c9df406f 2745 return rc;
d0412d96 2746}
fc32b0e2 2747module_init(mv643xx_eth_init_module);
d0412d96 2748
e5371493 2749static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2750{
c9df406f
LB		 2751 platform_driver_unregister(&mv643xx_eth_driver);
2752 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2753}
e5371493 2754module_exit(mv643xx_eth_cleanup_module);
1da177e4 2755
45675bc6
LB		 2756MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2757 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2758MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2759MODULE_LICENSE("GPL");
c9df406f 2760MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2761MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
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