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1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
1da177e4 LT |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/etherdevice.h> | |
1da177e4 LT |
44 | #include <linux/delay.h> |
45 | #include <linux/ethtool.h> | |
d052d1be | 46 | #include <linux/platform_device.h> |
fbd6a754 LB |
47 | #include <linux/module.h> |
48 | #include <linux/kernel.h> | |
49 | #include <linux/spinlock.h> | |
50 | #include <linux/workqueue.h> | |
51 | #include <linux/mii.h> | |
fbd6a754 | 52 | #include <linux/mv643xx_eth.h> |
1da177e4 LT |
53 | #include <asm/io.h> |
54 | #include <asm/types.h> | |
1da177e4 | 55 | #include <asm/system.h> |
fbd6a754 | 56 | |
e5371493 LB |
57 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
58 | static char mv643xx_eth_driver_version[] = "1.0"; | |
c9df406f | 59 | |
e5371493 LB |
60 | #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX |
61 | #define MV643XX_ETH_NAPI | |
62 | #define MV643XX_ETH_TX_FAST_REFILL | |
fbd6a754 | 63 | |
e5371493 | 64 | #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX |
fbd6a754 LB |
65 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) |
66 | #else | |
67 | #define MAX_DESCS_PER_SKB 1 | |
68 | #endif | |
69 | ||
fbd6a754 LB |
70 | /* |
71 | * Registers shared between all ports. | |
72 | */ | |
3cb4667c LB |
73 | #define PHY_ADDR 0x0000 |
74 | #define SMI_REG 0x0004 | |
75 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) | |
76 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
77 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
78 | #define WINDOW_BAR_ENABLE 0x0290 | |
79 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
80 | |
81 | /* | |
82 | * Per-port registers. | |
83 | */ | |
3cb4667c | 84 | #define PORT_CONFIG(p) (0x0400 + ((p) << 10)) |
d9a073ea | 85 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
3cb4667c LB |
86 | #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10)) |
87 | #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) | |
88 | #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) | |
89 | #define SDMA_CONFIG(p) (0x041c + ((p) << 10)) | |
90 | #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) | |
91 | #define PORT_STATUS(p) (0x0444 + ((p) << 10)) | |
a2a41689 | 92 | #define TX_FIFO_EMPTY 0x00000400 |
3cb4667c | 93 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) |
89df5fdc LB |
94 | #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10)) |
95 | #define TX_BW_RATE(p) (0x0450 + ((p) << 10)) | |
3cb4667c | 96 | #define TX_BW_MTU(p) (0x0458 + ((p) << 10)) |
89df5fdc | 97 | #define TX_BW_BURST(p) (0x045c + ((p) << 10)) |
3cb4667c | 98 | #define INT_CAUSE(p) (0x0460 + ((p) << 10)) |
226bb6b7 | 99 | #define INT_TX_END 0x07f80000 |
64da80a2 | 100 | #define INT_RX 0x0007fbfc |
073a345c | 101 | #define INT_EXT 0x00000002 |
3cb4667c | 102 | #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) |
073a345c LB |
103 | #define INT_EXT_LINK 0x00100000 |
104 | #define INT_EXT_PHY 0x00010000 | |
105 | #define INT_EXT_TX_ERROR_0 0x00000100 | |
106 | #define INT_EXT_TX_0 0x00000001 | |
3d6b35bc | 107 | #define INT_EXT_TX 0x0000ffff |
3cb4667c LB |
108 | #define INT_MASK(p) (0x0468 + ((p) << 10)) |
109 | #define INT_MASK_EXT(p) (0x046c + ((p) << 10)) | |
110 | #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) | |
1e881592 LB |
111 | #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10)) |
112 | #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10)) | |
113 | #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10)) | |
114 | #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10)) | |
64da80a2 | 115 | #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4)) |
3cb4667c | 116 | #define RXQ_COMMAND(p) (0x0680 + ((p) << 10)) |
3d6b35bc LB |
117 | #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2)) |
118 | #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4)) | |
119 | #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4)) | |
120 | #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4)) | |
3cb4667c LB |
121 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) |
122 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
123 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
124 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 125 | |
2679a550 LB |
126 | |
127 | /* | |
128 | * SDMA configuration register. | |
129 | */ | |
fbd6a754 | 130 | #define RX_BURST_SIZE_4_64BIT (2 << 1) |
fbd6a754 | 131 | #define BLM_RX_NO_SWAP (1 << 4) |
fbd6a754 | 132 | #define BLM_TX_NO_SWAP (1 << 5) |
fbd6a754 | 133 | #define TX_BURST_SIZE_4_64BIT (2 << 22) |
fbd6a754 LB |
134 | |
135 | #if defined(__BIG_ENDIAN) | |
136 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
137 | RX_BURST_SIZE_4_64BIT | \ | |
fbd6a754 LB |
138 | TX_BURST_SIZE_4_64BIT |
139 | #elif defined(__LITTLE_ENDIAN) | |
140 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
141 | RX_BURST_SIZE_4_64BIT | \ | |
142 | BLM_RX_NO_SWAP | \ | |
143 | BLM_TX_NO_SWAP | \ | |
fbd6a754 LB |
144 | TX_BURST_SIZE_4_64BIT |
145 | #else | |
146 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
147 | #endif | |
148 | ||
2beff77b LB |
149 | |
150 | /* | |
151 | * Port serial control register. | |
152 | */ | |
153 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
154 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
155 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
fbd6a754 | 156 | #define MAX_RX_PACKET_1522BYTE (1 << 17) |
fbd6a754 LB |
157 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
158 | #define MAX_RX_PACKET_MASK (7 << 17) | |
2beff77b LB |
159 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
160 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
161 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
162 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
163 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) | |
164 | #define FORCE_LINK_PASS (1 << 1) | |
165 | #define SERIAL_PORT_ENABLE (1 << 0) | |
fbd6a754 | 166 | |
cc9754b3 LB |
167 | #define DEFAULT_RX_QUEUE_SIZE 400 |
168 | #define DEFAULT_TX_QUEUE_SIZE 800 | |
fbd6a754 | 169 | |
fbd6a754 | 170 | |
7ca72a3b LB |
171 | /* |
172 | * RX/TX descriptors. | |
fbd6a754 LB |
173 | */ |
174 | #if defined(__BIG_ENDIAN) | |
cc9754b3 | 175 | struct rx_desc { |
fbd6a754 LB |
176 | u16 byte_cnt; /* Descriptor buffer byte count */ |
177 | u16 buf_size; /* Buffer size */ | |
178 | u32 cmd_sts; /* Descriptor command status */ | |
179 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
180 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
181 | }; | |
182 | ||
cc9754b3 | 183 | struct tx_desc { |
fbd6a754 LB |
184 | u16 byte_cnt; /* buffer byte count */ |
185 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
186 | u32 cmd_sts; /* Command/status field */ | |
187 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
188 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
189 | }; | |
190 | #elif defined(__LITTLE_ENDIAN) | |
cc9754b3 | 191 | struct rx_desc { |
fbd6a754 LB |
192 | u32 cmd_sts; /* Descriptor command status */ |
193 | u16 buf_size; /* Buffer size */ | |
194 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
195 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
196 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
197 | }; | |
198 | ||
cc9754b3 | 199 | struct tx_desc { |
fbd6a754 LB |
200 | u32 cmd_sts; /* Command/status field */ |
201 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
202 | u16 byte_cnt; /* buffer byte count */ | |
203 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
204 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
205 | }; | |
206 | #else | |
207 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
208 | #endif | |
209 | ||
7ca72a3b | 210 | /* RX & TX descriptor command */ |
cc9754b3 | 211 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
7ca72a3b LB |
212 | |
213 | /* RX & TX descriptor status */ | |
cc9754b3 | 214 | #define ERROR_SUMMARY 0x00000001 |
7ca72a3b LB |
215 | |
216 | /* RX descriptor status */ | |
cc9754b3 LB |
217 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
218 | #define RX_ENABLE_INTERRUPT 0x20000000 | |
219 | #define RX_FIRST_DESC 0x08000000 | |
220 | #define RX_LAST_DESC 0x04000000 | |
7ca72a3b LB |
221 | |
222 | /* TX descriptor command */ | |
cc9754b3 LB |
223 | #define TX_ENABLE_INTERRUPT 0x00800000 |
224 | #define GEN_CRC 0x00400000 | |
225 | #define TX_FIRST_DESC 0x00200000 | |
226 | #define TX_LAST_DESC 0x00100000 | |
227 | #define ZERO_PADDING 0x00080000 | |
228 | #define GEN_IP_V4_CHECKSUM 0x00040000 | |
229 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 | |
230 | #define UDP_FRAME 0x00010000 | |
7ca72a3b | 231 | |
cc9754b3 | 232 | #define TX_IHL_SHIFT 11 |
7ca72a3b LB |
233 | |
234 | ||
c9df406f | 235 | /* global *******************************************************************/ |
e5371493 | 236 | struct mv643xx_eth_shared_private { |
fc32b0e2 LB |
237 | /* |
238 | * Ethernet controller base address. | |
239 | */ | |
cc9754b3 | 240 | void __iomem *base; |
c9df406f | 241 | |
fc32b0e2 LB |
242 | /* |
243 | * Protects access to SMI_REG, which is shared between ports. | |
244 | */ | |
c9df406f LB |
245 | spinlock_t phy_lock; |
246 | ||
fc32b0e2 LB |
247 | /* |
248 | * Per-port MBUS window access register value. | |
249 | */ | |
c9df406f LB |
250 | u32 win_protect; |
251 | ||
fc32b0e2 LB |
252 | /* |
253 | * Hardware-specific parameters. | |
254 | */ | |
c9df406f | 255 | unsigned int t_clk; |
773fc3ee | 256 | int extended_rx_coal_limit; |
1e881592 | 257 | int tx_bw_control_moved; |
c9df406f LB |
258 | }; |
259 | ||
260 | ||
261 | /* per-port *****************************************************************/ | |
e5371493 | 262 | struct mib_counters { |
fbd6a754 LB |
263 | u64 good_octets_received; |
264 | u32 bad_octets_received; | |
265 | u32 internal_mac_transmit_err; | |
266 | u32 good_frames_received; | |
267 | u32 bad_frames_received; | |
268 | u32 broadcast_frames_received; | |
269 | u32 multicast_frames_received; | |
270 | u32 frames_64_octets; | |
271 | u32 frames_65_to_127_octets; | |
272 | u32 frames_128_to_255_octets; | |
273 | u32 frames_256_to_511_octets; | |
274 | u32 frames_512_to_1023_octets; | |
275 | u32 frames_1024_to_max_octets; | |
276 | u64 good_octets_sent; | |
277 | u32 good_frames_sent; | |
278 | u32 excessive_collision; | |
279 | u32 multicast_frames_sent; | |
280 | u32 broadcast_frames_sent; | |
281 | u32 unrec_mac_control_received; | |
282 | u32 fc_sent; | |
283 | u32 good_fc_received; | |
284 | u32 bad_fc_received; | |
285 | u32 undersize_received; | |
286 | u32 fragments_received; | |
287 | u32 oversize_received; | |
288 | u32 jabber_received; | |
289 | u32 mac_receive_error; | |
290 | u32 bad_crc_event; | |
291 | u32 collision; | |
292 | u32 late_collision; | |
293 | }; | |
294 | ||
8a578111 | 295 | struct rx_queue { |
64da80a2 LB |
296 | int index; |
297 | ||
8a578111 LB |
298 | int rx_ring_size; |
299 | ||
300 | int rx_desc_count; | |
301 | int rx_curr_desc; | |
302 | int rx_used_desc; | |
303 | ||
304 | struct rx_desc *rx_desc_area; | |
305 | dma_addr_t rx_desc_dma; | |
306 | int rx_desc_area_size; | |
307 | struct sk_buff **rx_skb; | |
308 | ||
309 | struct timer_list rx_oom; | |
310 | }; | |
311 | ||
13d64285 | 312 | struct tx_queue { |
3d6b35bc LB |
313 | int index; |
314 | ||
13d64285 | 315 | int tx_ring_size; |
fbd6a754 | 316 | |
13d64285 LB |
317 | int tx_desc_count; |
318 | int tx_curr_desc; | |
319 | int tx_used_desc; | |
fbd6a754 | 320 | |
5daffe94 | 321 | struct tx_desc *tx_desc_area; |
fbd6a754 LB |
322 | dma_addr_t tx_desc_dma; |
323 | int tx_desc_area_size; | |
324 | struct sk_buff **tx_skb; | |
13d64285 LB |
325 | }; |
326 | ||
327 | struct mv643xx_eth_private { | |
328 | struct mv643xx_eth_shared_private *shared; | |
fc32b0e2 | 329 | int port_num; |
13d64285 | 330 | |
fc32b0e2 | 331 | struct net_device *dev; |
fbd6a754 | 332 | |
fc32b0e2 LB |
333 | struct mv643xx_eth_shared_private *shared_smi; |
334 | int phy_addr; | |
fbd6a754 | 335 | |
fbd6a754 | 336 | spinlock_t lock; |
fbd6a754 | 337 | |
fc32b0e2 LB |
338 | struct mib_counters mib_counters; |
339 | struct work_struct tx_timeout_task; | |
fbd6a754 | 340 | struct mii_if_info mii; |
8a578111 LB |
341 | |
342 | /* | |
343 | * RX state. | |
344 | */ | |
345 | int default_rx_ring_size; | |
346 | unsigned long rx_desc_sram_addr; | |
347 | int rx_desc_sram_size; | |
64da80a2 LB |
348 | u8 rxq_mask; |
349 | int rxq_primary; | |
8a578111 | 350 | struct napi_struct napi; |
64da80a2 | 351 | struct rx_queue rxq[8]; |
13d64285 LB |
352 | |
353 | /* | |
354 | * TX state. | |
355 | */ | |
356 | int default_tx_ring_size; | |
357 | unsigned long tx_desc_sram_addr; | |
358 | int tx_desc_sram_size; | |
3d6b35bc LB |
359 | u8 txq_mask; |
360 | int txq_primary; | |
361 | struct tx_queue txq[8]; | |
13d64285 LB |
362 | #ifdef MV643XX_ETH_TX_FAST_REFILL |
363 | int tx_clean_threshold; | |
364 | #endif | |
fbd6a754 | 365 | }; |
1da177e4 | 366 | |
fbd6a754 | 367 | |
c9df406f | 368 | /* port register accessors **************************************************/ |
e5371493 | 369 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 370 | { |
cc9754b3 | 371 | return readl(mp->shared->base + offset); |
c9df406f | 372 | } |
fbd6a754 | 373 | |
e5371493 | 374 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
c9df406f | 375 | { |
cc9754b3 | 376 | writel(data, mp->shared->base + offset); |
c9df406f | 377 | } |
fbd6a754 | 378 | |
fbd6a754 | 379 | |
c9df406f | 380 | /* rxq/txq helper functions *************************************************/ |
8a578111 | 381 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
c9df406f | 382 | { |
64da80a2 | 383 | return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); |
c9df406f | 384 | } |
fbd6a754 | 385 | |
13d64285 LB |
386 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
387 | { | |
3d6b35bc | 388 | return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); |
13d64285 LB |
389 | } |
390 | ||
8a578111 | 391 | static void rxq_enable(struct rx_queue *rxq) |
c9df406f | 392 | { |
8a578111 | 393 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
64da80a2 | 394 | wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index); |
8a578111 | 395 | } |
1da177e4 | 396 | |
8a578111 LB |
397 | static void rxq_disable(struct rx_queue *rxq) |
398 | { | |
399 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); | |
64da80a2 | 400 | u8 mask = 1 << rxq->index; |
1da177e4 | 401 | |
8a578111 LB |
402 | wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8); |
403 | while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask) | |
404 | udelay(10); | |
c9df406f LB |
405 | } |
406 | ||
13d64285 | 407 | static void txq_enable(struct tx_queue *txq) |
1da177e4 | 408 | { |
13d64285 | 409 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 410 | wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index); |
1da177e4 LT |
411 | } |
412 | ||
13d64285 | 413 | static void txq_disable(struct tx_queue *txq) |
1da177e4 | 414 | { |
13d64285 | 415 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 416 | u8 mask = 1 << txq->index; |
c9df406f | 417 | |
13d64285 LB |
418 | wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8); |
419 | while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask) | |
420 | udelay(10); | |
421 | } | |
422 | ||
423 | static void __txq_maybe_wake(struct tx_queue *txq) | |
424 | { | |
425 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
426 | ||
3d6b35bc LB |
427 | /* |
428 | * netif_{stop,wake}_queue() flow control only applies to | |
429 | * the primary queue. | |
430 | */ | |
431 | BUG_ON(txq->index != mp->txq_primary); | |
432 | ||
13d64285 LB |
433 | if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB) |
434 | netif_wake_queue(mp->dev); | |
1da177e4 LT |
435 | } |
436 | ||
c9df406f LB |
437 | |
438 | /* rx ***********************************************************************/ | |
13d64285 | 439 | static void txq_reclaim(struct tx_queue *txq, int force); |
c9df406f | 440 | |
8a578111 | 441 | static void rxq_refill(struct rx_queue *rxq) |
1da177e4 | 442 | { |
8a578111 | 443 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
c9df406f | 444 | unsigned long flags; |
1da177e4 | 445 | |
c9df406f | 446 | spin_lock_irqsave(&mp->lock, flags); |
c0d0f2ca | 447 | |
8a578111 LB |
448 | while (rxq->rx_desc_count < rxq->rx_ring_size) { |
449 | int skb_size; | |
de34f225 LB |
450 | struct sk_buff *skb; |
451 | int unaligned; | |
452 | int rx; | |
453 | ||
8a578111 LB |
454 | /* |
455 | * Reserve 2+14 bytes for an ethernet header (the | |
456 | * hardware automatically prepends 2 bytes of dummy | |
457 | * data to each received packet), 4 bytes for a VLAN | |
458 | * header, and 4 bytes for the trailing FCS -- 24 | |
459 | * bytes total. | |
460 | */ | |
461 | skb_size = mp->dev->mtu + 24; | |
462 | ||
463 | skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1); | |
de34f225 | 464 | if (skb == NULL) |
1da177e4 | 465 | break; |
de34f225 | 466 | |
908b637f | 467 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
b44cd572 | 468 | if (unaligned) |
908b637f | 469 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
de34f225 | 470 | |
8a578111 LB |
471 | rxq->rx_desc_count++; |
472 | rx = rxq->rx_used_desc; | |
473 | rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size; | |
de34f225 | 474 | |
8a578111 LB |
475 | rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data, |
476 | skb_size, DMA_FROM_DEVICE); | |
477 | rxq->rx_desc_area[rx].buf_size = skb_size; | |
478 | rxq->rx_skb[rx] = skb; | |
de34f225 | 479 | wmb(); |
8a578111 | 480 | rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA | |
de34f225 LB |
481 | RX_ENABLE_INTERRUPT; |
482 | wmb(); | |
483 | ||
fc32b0e2 LB |
484 | /* |
485 | * The hardware automatically prepends 2 bytes of | |
486 | * dummy data to each received packet, so that the | |
487 | * IP header ends up 16-byte aligned. | |
488 | */ | |
489 | skb_reserve(skb, 2); | |
1da177e4 | 490 | } |
de34f225 | 491 | |
12e4ab79 | 492 | if (rxq->rx_desc_count != rxq->rx_ring_size) { |
8a578111 LB |
493 | rxq->rx_oom.expires = jiffies + (HZ / 10); |
494 | add_timer(&rxq->rx_oom); | |
1da177e4 | 495 | } |
de34f225 LB |
496 | |
497 | spin_unlock_irqrestore(&mp->lock, flags); | |
1da177e4 LT |
498 | } |
499 | ||
8a578111 | 500 | static inline void rxq_refill_timer_wrapper(unsigned long data) |
1da177e4 | 501 | { |
8a578111 | 502 | rxq_refill((struct rx_queue *)data); |
1da177e4 LT |
503 | } |
504 | ||
8a578111 | 505 | static int rxq_process(struct rx_queue *rxq, int budget) |
1da177e4 | 506 | { |
8a578111 LB |
507 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
508 | struct net_device_stats *stats = &mp->dev->stats; | |
509 | int rx; | |
1da177e4 | 510 | |
8a578111 LB |
511 | rx = 0; |
512 | while (rx < budget) { | |
fc32b0e2 | 513 | struct rx_desc *rx_desc; |
96587661 | 514 | unsigned int cmd_sts; |
fc32b0e2 | 515 | struct sk_buff *skb; |
96587661 | 516 | unsigned long flags; |
d344bff9 | 517 | |
96587661 | 518 | spin_lock_irqsave(&mp->lock, flags); |
ff561eef | 519 | |
8a578111 | 520 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
1da177e4 | 521 | |
96587661 LB |
522 | cmd_sts = rx_desc->cmd_sts; |
523 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { | |
524 | spin_unlock_irqrestore(&mp->lock, flags); | |
525 | break; | |
526 | } | |
527 | rmb(); | |
1da177e4 | 528 | |
8a578111 LB |
529 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
530 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; | |
ff561eef | 531 | |
8a578111 | 532 | rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size; |
ff561eef | 533 | |
96587661 | 534 | spin_unlock_irqrestore(&mp->lock, flags); |
1da177e4 | 535 | |
fc32b0e2 LB |
536 | dma_unmap_single(NULL, rx_desc->buf_ptr + 2, |
537 | mp->dev->mtu + 24, DMA_FROM_DEVICE); | |
8a578111 LB |
538 | rxq->rx_desc_count--; |
539 | rx++; | |
b1dd9ca1 | 540 | |
468d09f8 DF |
541 | /* |
542 | * Update statistics. | |
fc32b0e2 LB |
543 | * |
544 | * Note that the descriptor byte count includes 2 dummy | |
545 | * bytes automatically inserted by the hardware at the | |
546 | * start of the packet (which we don't count), and a 4 | |
547 | * byte CRC at the end of the packet (which we do count). | |
468d09f8 | 548 | */ |
1da177e4 | 549 | stats->rx_packets++; |
fc32b0e2 | 550 | stats->rx_bytes += rx_desc->byte_cnt - 2; |
96587661 | 551 | |
1da177e4 | 552 | /* |
fc32b0e2 LB |
553 | * In case we received a packet without first / last bits |
554 | * on, or the error summary bit is set, the packet needs | |
555 | * to be dropped. | |
1da177e4 | 556 | */ |
96587661 | 557 | if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != |
cc9754b3 | 558 | (RX_FIRST_DESC | RX_LAST_DESC)) |
96587661 | 559 | || (cmd_sts & ERROR_SUMMARY)) { |
1da177e4 | 560 | stats->rx_dropped++; |
fc32b0e2 | 561 | |
96587661 | 562 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != |
cc9754b3 | 563 | (RX_FIRST_DESC | RX_LAST_DESC)) { |
1da177e4 | 564 | if (net_ratelimit()) |
fc32b0e2 LB |
565 | dev_printk(KERN_ERR, &mp->dev->dev, |
566 | "received packet spanning " | |
567 | "multiple descriptors\n"); | |
1da177e4 | 568 | } |
fc32b0e2 | 569 | |
96587661 | 570 | if (cmd_sts & ERROR_SUMMARY) |
1da177e4 LT |
571 | stats->rx_errors++; |
572 | ||
573 | dev_kfree_skb_irq(skb); | |
574 | } else { | |
575 | /* | |
576 | * The -4 is for the CRC in the trailer of the | |
577 | * received packet | |
578 | */ | |
fc32b0e2 | 579 | skb_put(skb, rx_desc->byte_cnt - 2 - 4); |
1da177e4 | 580 | |
96587661 | 581 | if (cmd_sts & LAYER_4_CHECKSUM_OK) { |
1da177e4 LT |
582 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
583 | skb->csum = htons( | |
96587661 | 584 | (cmd_sts & 0x0007fff8) >> 3); |
1da177e4 | 585 | } |
8a578111 | 586 | skb->protocol = eth_type_trans(skb, mp->dev); |
e5371493 | 587 | #ifdef MV643XX_ETH_NAPI |
1da177e4 LT |
588 | netif_receive_skb(skb); |
589 | #else | |
590 | netif_rx(skb); | |
591 | #endif | |
592 | } | |
fc32b0e2 | 593 | |
8a578111 | 594 | mp->dev->last_rx = jiffies; |
1da177e4 | 595 | } |
fc32b0e2 | 596 | |
8a578111 | 597 | rxq_refill(rxq); |
1da177e4 | 598 | |
8a578111 | 599 | return rx; |
1da177e4 LT |
600 | } |
601 | ||
e5371493 | 602 | #ifdef MV643XX_ETH_NAPI |
e5371493 | 603 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
d0412d96 | 604 | { |
8a578111 LB |
605 | struct mv643xx_eth_private *mp; |
606 | int rx; | |
64da80a2 | 607 | int i; |
8a578111 LB |
608 | |
609 | mp = container_of(napi, struct mv643xx_eth_private, napi); | |
d0412d96 | 610 | |
e5371493 | 611 | #ifdef MV643XX_ETH_TX_FAST_REFILL |
c9df406f | 612 | if (++mp->tx_clean_threshold > 5) { |
c9df406f | 613 | mp->tx_clean_threshold = 0; |
3d6b35bc LB |
614 | for (i = 0; i < 8; i++) |
615 | if (mp->txq_mask & (1 << i)) | |
616 | txq_reclaim(mp->txq + i, 0); | |
d0412d96 | 617 | } |
c9df406f | 618 | #endif |
d0412d96 | 619 | |
64da80a2 LB |
620 | rx = 0; |
621 | for (i = 7; rx < budget && i >= 0; i--) | |
622 | if (mp->rxq_mask & (1 << i)) | |
623 | rx += rxq_process(mp->rxq + i, budget - rx); | |
d0412d96 | 624 | |
8a578111 LB |
625 | if (rx < budget) { |
626 | netif_rx_complete(mp->dev, napi); | |
627 | wrl(mp, INT_CAUSE(mp->port_num), 0); | |
628 | wrl(mp, INT_CAUSE_EXT(mp->port_num), 0); | |
226bb6b7 | 629 | wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); |
d0412d96 | 630 | } |
c9df406f | 631 | |
8a578111 | 632 | return rx; |
d0412d96 | 633 | } |
c9df406f | 634 | #endif |
d0412d96 | 635 | |
c9df406f LB |
636 | |
637 | /* tx ***********************************************************************/ | |
c9df406f | 638 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 639 | { |
13d64285 | 640 | int frag; |
1da177e4 | 641 | |
c9df406f | 642 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
13d64285 LB |
643 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
644 | if (fragp->size <= 8 && fragp->page_offset & 7) | |
c9df406f | 645 | return 1; |
1da177e4 | 646 | } |
13d64285 | 647 | |
c9df406f LB |
648 | return 0; |
649 | } | |
7303fde8 | 650 | |
13d64285 | 651 | static int txq_alloc_desc_index(struct tx_queue *txq) |
c9df406f LB |
652 | { |
653 | int tx_desc_curr; | |
d0412d96 | 654 | |
13d64285 | 655 | BUG_ON(txq->tx_desc_count >= txq->tx_ring_size); |
1da177e4 | 656 | |
13d64285 LB |
657 | tx_desc_curr = txq->tx_curr_desc; |
658 | txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size; | |
e4d00fa9 | 659 | |
13d64285 | 660 | BUG_ON(txq->tx_curr_desc == txq->tx_used_desc); |
468d09f8 | 661 | |
c9df406f LB |
662 | return tx_desc_curr; |
663 | } | |
468d09f8 | 664 | |
13d64285 | 665 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
c9df406f | 666 | { |
13d64285 | 667 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 668 | int frag; |
1da177e4 | 669 | |
13d64285 LB |
670 | for (frag = 0; frag < nr_frags; frag++) { |
671 | skb_frag_t *this_frag; | |
672 | int tx_index; | |
673 | struct tx_desc *desc; | |
674 | ||
675 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
676 | tx_index = txq_alloc_desc_index(txq); | |
677 | desc = &txq->tx_desc_area[tx_index]; | |
678 | ||
679 | /* | |
680 | * The last fragment will generate an interrupt | |
681 | * which will free the skb on TX completion. | |
682 | */ | |
683 | if (frag == nr_frags - 1) { | |
684 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | | |
685 | ZERO_PADDING | TX_LAST_DESC | | |
686 | TX_ENABLE_INTERRUPT; | |
687 | txq->tx_skb[tx_index] = skb; | |
688 | } else { | |
689 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; | |
690 | txq->tx_skb[tx_index] = NULL; | |
691 | } | |
692 | ||
c9df406f LB |
693 | desc->l4i_chk = 0; |
694 | desc->byte_cnt = this_frag->size; | |
695 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
696 | this_frag->page_offset, | |
697 | this_frag->size, | |
698 | DMA_TO_DEVICE); | |
699 | } | |
1da177e4 LT |
700 | } |
701 | ||
c9df406f LB |
702 | static inline __be16 sum16_as_be(__sum16 sum) |
703 | { | |
704 | return (__force __be16)sum; | |
705 | } | |
1da177e4 | 706 | |
13d64285 | 707 | static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) |
1da177e4 | 708 | { |
13d64285 | 709 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 710 | int tx_index; |
cc9754b3 | 711 | struct tx_desc *desc; |
c9df406f LB |
712 | u32 cmd_sts; |
713 | int length; | |
1da177e4 | 714 | |
cc9754b3 | 715 | cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
1da177e4 | 716 | |
13d64285 LB |
717 | tx_index = txq_alloc_desc_index(txq); |
718 | desc = &txq->tx_desc_area[tx_index]; | |
c9df406f LB |
719 | |
720 | if (nr_frags) { | |
13d64285 | 721 | txq_submit_frag_skb(txq, skb); |
c9df406f LB |
722 | |
723 | length = skb_headlen(skb); | |
13d64285 | 724 | txq->tx_skb[tx_index] = NULL; |
c9df406f | 725 | } else { |
cc9754b3 | 726 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; |
c9df406f | 727 | length = skb->len; |
13d64285 | 728 | txq->tx_skb[tx_index] = skb; |
c9df406f LB |
729 | } |
730 | ||
731 | desc->byte_cnt = length; | |
732 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
733 | ||
734 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
735 | BUG_ON(skb->protocol != htons(ETH_P_IP)); | |
736 | ||
cc9754b3 LB |
737 | cmd_sts |= GEN_TCP_UDP_CHECKSUM | |
738 | GEN_IP_V4_CHECKSUM | | |
739 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; | |
c9df406f LB |
740 | |
741 | switch (ip_hdr(skb)->protocol) { | |
742 | case IPPROTO_UDP: | |
cc9754b3 | 743 | cmd_sts |= UDP_FRAME; |
c9df406f LB |
744 | desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
745 | break; | |
746 | case IPPROTO_TCP: | |
747 | desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); | |
748 | break; | |
749 | default: | |
750 | BUG(); | |
751 | } | |
752 | } else { | |
753 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
cc9754b3 | 754 | cmd_sts |= 5 << TX_IHL_SHIFT; |
c9df406f LB |
755 | desc->l4i_chk = 0; |
756 | } | |
757 | ||
758 | /* ensure all other descriptors are written before first cmd_sts */ | |
759 | wmb(); | |
760 | desc->cmd_sts = cmd_sts; | |
761 | ||
762 | /* ensure all descriptors are written before poking hardware */ | |
763 | wmb(); | |
13d64285 | 764 | txq_enable(txq); |
c9df406f | 765 | |
13d64285 | 766 | txq->tx_desc_count += nr_frags + 1; |
1da177e4 | 767 | } |
1da177e4 | 768 | |
fc32b0e2 | 769 | static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 770 | { |
e5371493 | 771 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 772 | struct net_device_stats *stats = &dev->stats; |
13d64285 | 773 | struct tx_queue *txq; |
c9df406f | 774 | unsigned long flags; |
afdb57a2 | 775 | |
c9df406f LB |
776 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
777 | stats->tx_dropped++; | |
fc32b0e2 LB |
778 | dev_printk(KERN_DEBUG, &dev->dev, |
779 | "failed to linearize skb with tiny " | |
780 | "unaligned fragment\n"); | |
c9df406f LB |
781 | return NETDEV_TX_BUSY; |
782 | } | |
783 | ||
784 | spin_lock_irqsave(&mp->lock, flags); | |
785 | ||
3d6b35bc | 786 | txq = mp->txq + mp->txq_primary; |
13d64285 LB |
787 | |
788 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) { | |
c9df406f | 789 | spin_unlock_irqrestore(&mp->lock, flags); |
3d6b35bc LB |
790 | if (txq->index == mp->txq_primary && net_ratelimit()) |
791 | dev_printk(KERN_ERR, &dev->dev, | |
792 | "primary tx queue full?!\n"); | |
793 | kfree_skb(skb); | |
794 | return NETDEV_TX_OK; | |
c9df406f LB |
795 | } |
796 | ||
13d64285 | 797 | txq_submit_skb(txq, skb); |
c9df406f LB |
798 | stats->tx_bytes += skb->len; |
799 | stats->tx_packets++; | |
800 | dev->trans_start = jiffies; | |
801 | ||
3d6b35bc LB |
802 | if (txq->index == mp->txq_primary) { |
803 | int entries_left; | |
804 | ||
805 | entries_left = txq->tx_ring_size - txq->tx_desc_count; | |
806 | if (entries_left < MAX_DESCS_PER_SKB) | |
807 | netif_stop_queue(dev); | |
808 | } | |
c9df406f LB |
809 | |
810 | spin_unlock_irqrestore(&mp->lock, flags); | |
811 | ||
812 | return NETDEV_TX_OK; | |
1da177e4 LT |
813 | } |
814 | ||
c9df406f | 815 | |
89df5fdc LB |
816 | /* tx rate control **********************************************************/ |
817 | /* | |
818 | * Set total maximum TX rate (shared by all TX queues for this port) | |
819 | * to 'rate' bits per second, with a maximum burst of 'burst' bytes. | |
820 | */ | |
821 | static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) | |
822 | { | |
823 | int token_rate; | |
824 | int mtu; | |
825 | int bucket_size; | |
826 | ||
827 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
828 | if (token_rate > 1023) | |
829 | token_rate = 1023; | |
830 | ||
831 | mtu = (mp->dev->mtu + 255) >> 8; | |
832 | if (mtu > 63) | |
833 | mtu = 63; | |
834 | ||
835 | bucket_size = (burst + 255) >> 8; | |
836 | if (bucket_size > 65535) | |
837 | bucket_size = 65535; | |
838 | ||
1e881592 LB |
839 | if (mp->shared->tx_bw_control_moved) { |
840 | wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate); | |
841 | wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu); | |
842 | wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size); | |
843 | } else { | |
844 | wrl(mp, TX_BW_RATE(mp->port_num), token_rate); | |
845 | wrl(mp, TX_BW_MTU(mp->port_num), mtu); | |
846 | wrl(mp, TX_BW_BURST(mp->port_num), bucket_size); | |
847 | } | |
89df5fdc LB |
848 | } |
849 | ||
850 | static void txq_set_rate(struct tx_queue *txq, int rate, int burst) | |
851 | { | |
852 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
853 | int token_rate; | |
854 | int bucket_size; | |
855 | ||
856 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
857 | if (token_rate > 1023) | |
858 | token_rate = 1023; | |
859 | ||
860 | bucket_size = (burst + 255) >> 8; | |
861 | if (bucket_size > 65535) | |
862 | bucket_size = 65535; | |
863 | ||
3d6b35bc LB |
864 | wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14); |
865 | wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index), | |
89df5fdc LB |
866 | (bucket_size << 10) | token_rate); |
867 | } | |
868 | ||
869 | static void txq_set_fixed_prio_mode(struct tx_queue *txq) | |
870 | { | |
871 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
872 | int off; | |
873 | u32 val; | |
874 | ||
875 | /* | |
876 | * Turn on fixed priority mode. | |
877 | */ | |
1e881592 LB |
878 | if (mp->shared->tx_bw_control_moved) |
879 | off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num); | |
880 | else | |
881 | off = TXQ_FIX_PRIO_CONF(mp->port_num); | |
89df5fdc LB |
882 | |
883 | val = rdl(mp, off); | |
3d6b35bc | 884 | val |= 1 << txq->index; |
89df5fdc LB |
885 | wrl(mp, off, val); |
886 | } | |
887 | ||
888 | static void txq_set_wrr(struct tx_queue *txq, int weight) | |
889 | { | |
890 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
891 | int off; | |
892 | u32 val; | |
893 | ||
894 | /* | |
895 | * Turn off fixed priority mode. | |
896 | */ | |
1e881592 LB |
897 | if (mp->shared->tx_bw_control_moved) |
898 | off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num); | |
899 | else | |
900 | off = TXQ_FIX_PRIO_CONF(mp->port_num); | |
89df5fdc LB |
901 | |
902 | val = rdl(mp, off); | |
3d6b35bc | 903 | val &= ~(1 << txq->index); |
89df5fdc LB |
904 | wrl(mp, off, val); |
905 | ||
906 | /* | |
907 | * Configure WRR weight for this queue. | |
908 | */ | |
3d6b35bc | 909 | off = TXQ_BW_WRR_CONF(mp->port_num, txq->index); |
89df5fdc LB |
910 | |
911 | val = rdl(mp, off); | |
912 | val = (val & ~0xff) | (weight & 0xff); | |
913 | wrl(mp, off, val); | |
914 | } | |
915 | ||
916 | ||
c9df406f | 917 | /* mii management interface *************************************************/ |
fc32b0e2 LB |
918 | #define SMI_BUSY 0x10000000 |
919 | #define SMI_READ_VALID 0x08000000 | |
920 | #define SMI_OPCODE_READ 0x04000000 | |
921 | #define SMI_OPCODE_WRITE 0x00000000 | |
c9df406f | 922 | |
fc32b0e2 LB |
923 | static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr, |
924 | unsigned int reg, unsigned int *value) | |
1da177e4 | 925 | { |
cc9754b3 | 926 | void __iomem *smi_reg = mp->shared_smi->base + SMI_REG; |
c9df406f | 927 | unsigned long flags; |
1da177e4 LT |
928 | int i; |
929 | ||
c9df406f LB |
930 | /* the SMI register is a shared resource */ |
931 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
932 | ||
933 | /* wait for the SMI register to become available */ | |
cc9754b3 | 934 | for (i = 0; readl(smi_reg) & SMI_BUSY; i++) { |
e1bea50a | 935 | if (i == 1000) { |
c9df406f LB |
936 | printk("%s: PHY busy timeout\n", mp->dev->name); |
937 | goto out; | |
938 | } | |
e1bea50a | 939 | udelay(10); |
1da177e4 LT |
940 | } |
941 | ||
fc32b0e2 | 942 | writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); |
1da177e4 | 943 | |
c9df406f | 944 | /* now wait for the data to be valid */ |
cc9754b3 | 945 | for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) { |
e1bea50a | 946 | if (i == 1000) { |
c9df406f LB |
947 | printk("%s: PHY read timeout\n", mp->dev->name); |
948 | goto out; | |
949 | } | |
e1bea50a | 950 | udelay(10); |
c9df406f LB |
951 | } |
952 | ||
953 | *value = readl(smi_reg) & 0xffff; | |
954 | out: | |
955 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1da177e4 LT |
956 | } |
957 | ||
fc32b0e2 LB |
958 | static void smi_reg_write(struct mv643xx_eth_private *mp, |
959 | unsigned int addr, | |
960 | unsigned int reg, unsigned int value) | |
1da177e4 | 961 | { |
cc9754b3 | 962 | void __iomem *smi_reg = mp->shared_smi->base + SMI_REG; |
c9df406f | 963 | unsigned long flags; |
1da177e4 LT |
964 | int i; |
965 | ||
c9df406f LB |
966 | /* the SMI register is a shared resource */ |
967 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
968 | ||
969 | /* wait for the SMI register to become available */ | |
cc9754b3 | 970 | for (i = 0; readl(smi_reg) & SMI_BUSY; i++) { |
e1bea50a | 971 | if (i == 1000) { |
c9df406f LB |
972 | printk("%s: PHY busy timeout\n", mp->dev->name); |
973 | goto out; | |
974 | } | |
e1bea50a | 975 | udelay(10); |
1da177e4 LT |
976 | } |
977 | ||
fc32b0e2 LB |
978 | writel(SMI_OPCODE_WRITE | (reg << 21) | |
979 | (addr << 16) | (value & 0xffff), smi_reg); | |
c9df406f LB |
980 | out: |
981 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
982 | } | |
1da177e4 | 983 | |
c9df406f LB |
984 | |
985 | /* mib counters *************************************************************/ | |
fc32b0e2 | 986 | static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 987 | { |
fc32b0e2 | 988 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
1da177e4 LT |
989 | } |
990 | ||
fc32b0e2 | 991 | static void mib_counters_clear(struct mv643xx_eth_private *mp) |
d0412d96 | 992 | { |
fc32b0e2 LB |
993 | int i; |
994 | ||
995 | for (i = 0; i < 0x80; i += 4) | |
996 | mib_read(mp, i); | |
c9df406f | 997 | } |
d0412d96 | 998 | |
fc32b0e2 | 999 | static void mib_counters_update(struct mv643xx_eth_private *mp) |
c9df406f | 1000 | { |
e5371493 | 1001 | struct mib_counters *p = &mp->mib_counters; |
4b8e3655 | 1002 | |
fc32b0e2 LB |
1003 | p->good_octets_received += mib_read(mp, 0x00); |
1004 | p->good_octets_received += (u64)mib_read(mp, 0x04) << 32; | |
1005 | p->bad_octets_received += mib_read(mp, 0x08); | |
1006 | p->internal_mac_transmit_err += mib_read(mp, 0x0c); | |
1007 | p->good_frames_received += mib_read(mp, 0x10); | |
1008 | p->bad_frames_received += mib_read(mp, 0x14); | |
1009 | p->broadcast_frames_received += mib_read(mp, 0x18); | |
1010 | p->multicast_frames_received += mib_read(mp, 0x1c); | |
1011 | p->frames_64_octets += mib_read(mp, 0x20); | |
1012 | p->frames_65_to_127_octets += mib_read(mp, 0x24); | |
1013 | p->frames_128_to_255_octets += mib_read(mp, 0x28); | |
1014 | p->frames_256_to_511_octets += mib_read(mp, 0x2c); | |
1015 | p->frames_512_to_1023_octets += mib_read(mp, 0x30); | |
1016 | p->frames_1024_to_max_octets += mib_read(mp, 0x34); | |
1017 | p->good_octets_sent += mib_read(mp, 0x38); | |
1018 | p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32; | |
1019 | p->good_frames_sent += mib_read(mp, 0x40); | |
1020 | p->excessive_collision += mib_read(mp, 0x44); | |
1021 | p->multicast_frames_sent += mib_read(mp, 0x48); | |
1022 | p->broadcast_frames_sent += mib_read(mp, 0x4c); | |
1023 | p->unrec_mac_control_received += mib_read(mp, 0x50); | |
1024 | p->fc_sent += mib_read(mp, 0x54); | |
1025 | p->good_fc_received += mib_read(mp, 0x58); | |
1026 | p->bad_fc_received += mib_read(mp, 0x5c); | |
1027 | p->undersize_received += mib_read(mp, 0x60); | |
1028 | p->fragments_received += mib_read(mp, 0x64); | |
1029 | p->oversize_received += mib_read(mp, 0x68); | |
1030 | p->jabber_received += mib_read(mp, 0x6c); | |
1031 | p->mac_receive_error += mib_read(mp, 0x70); | |
1032 | p->bad_crc_event += mib_read(mp, 0x74); | |
1033 | p->collision += mib_read(mp, 0x78); | |
1034 | p->late_collision += mib_read(mp, 0x7c); | |
d0412d96 JC |
1035 | } |
1036 | ||
c9df406f LB |
1037 | |
1038 | /* ethtool ******************************************************************/ | |
e5371493 | 1039 | struct mv643xx_eth_stats { |
c9df406f LB |
1040 | char stat_string[ETH_GSTRING_LEN]; |
1041 | int sizeof_stat; | |
16820054 LB |
1042 | int netdev_off; |
1043 | int mp_off; | |
c9df406f LB |
1044 | }; |
1045 | ||
16820054 LB |
1046 | #define SSTAT(m) \ |
1047 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ | |
1048 | offsetof(struct net_device, stats.m), -1 } | |
1049 | ||
1050 | #define MIBSTAT(m) \ | |
1051 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ | |
1052 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } | |
1053 | ||
1054 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { | |
1055 | SSTAT(rx_packets), | |
1056 | SSTAT(tx_packets), | |
1057 | SSTAT(rx_bytes), | |
1058 | SSTAT(tx_bytes), | |
1059 | SSTAT(rx_errors), | |
1060 | SSTAT(tx_errors), | |
1061 | SSTAT(rx_dropped), | |
1062 | SSTAT(tx_dropped), | |
1063 | MIBSTAT(good_octets_received), | |
1064 | MIBSTAT(bad_octets_received), | |
1065 | MIBSTAT(internal_mac_transmit_err), | |
1066 | MIBSTAT(good_frames_received), | |
1067 | MIBSTAT(bad_frames_received), | |
1068 | MIBSTAT(broadcast_frames_received), | |
1069 | MIBSTAT(multicast_frames_received), | |
1070 | MIBSTAT(frames_64_octets), | |
1071 | MIBSTAT(frames_65_to_127_octets), | |
1072 | MIBSTAT(frames_128_to_255_octets), | |
1073 | MIBSTAT(frames_256_to_511_octets), | |
1074 | MIBSTAT(frames_512_to_1023_octets), | |
1075 | MIBSTAT(frames_1024_to_max_octets), | |
1076 | MIBSTAT(good_octets_sent), | |
1077 | MIBSTAT(good_frames_sent), | |
1078 | MIBSTAT(excessive_collision), | |
1079 | MIBSTAT(multicast_frames_sent), | |
1080 | MIBSTAT(broadcast_frames_sent), | |
1081 | MIBSTAT(unrec_mac_control_received), | |
1082 | MIBSTAT(fc_sent), | |
1083 | MIBSTAT(good_fc_received), | |
1084 | MIBSTAT(bad_fc_received), | |
1085 | MIBSTAT(undersize_received), | |
1086 | MIBSTAT(fragments_received), | |
1087 | MIBSTAT(oversize_received), | |
1088 | MIBSTAT(jabber_received), | |
1089 | MIBSTAT(mac_receive_error), | |
1090 | MIBSTAT(bad_crc_event), | |
1091 | MIBSTAT(collision), | |
1092 | MIBSTAT(late_collision), | |
c9df406f LB |
1093 | }; |
1094 | ||
e5371493 | 1095 | static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
d0412d96 | 1096 | { |
e5371493 | 1097 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
d0412d96 JC |
1098 | int err; |
1099 | ||
1100 | spin_lock_irq(&mp->lock); | |
1101 | err = mii_ethtool_gset(&mp->mii, cmd); | |
1102 | spin_unlock_irq(&mp->lock); | |
1103 | ||
fc32b0e2 LB |
1104 | /* |
1105 | * The MAC does not support 1000baseT_Half. | |
1106 | */ | |
d0412d96 JC |
1107 | cmd->supported &= ~SUPPORTED_1000baseT_Half; |
1108 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1109 | ||
1110 | return err; | |
1111 | } | |
1112 | ||
bedfe324 LB |
1113 | static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) |
1114 | { | |
1115 | cmd->supported = SUPPORTED_MII; | |
1116 | cmd->advertising = ADVERTISED_MII; | |
1117 | cmd->speed = SPEED_1000; | |
1118 | cmd->duplex = DUPLEX_FULL; | |
1119 | cmd->port = PORT_MII; | |
1120 | cmd->phy_address = 0; | |
1121 | cmd->transceiver = XCVR_INTERNAL; | |
1122 | cmd->autoneg = AUTONEG_DISABLE; | |
1123 | cmd->maxtxpkt = 1; | |
1124 | cmd->maxrxpkt = 1; | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
e5371493 | 1129 | static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 1130 | { |
e5371493 | 1131 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
ab4384a6 DF |
1132 | int err; |
1133 | ||
fc32b0e2 LB |
1134 | /* |
1135 | * The MAC does not support 1000baseT_Half. | |
1136 | */ | |
1137 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1138 | ||
c9df406f LB |
1139 | spin_lock_irq(&mp->lock); |
1140 | err = mii_ethtool_sset(&mp->mii, cmd); | |
1141 | spin_unlock_irq(&mp->lock); | |
85cf572c | 1142 | |
c9df406f LB |
1143 | return err; |
1144 | } | |
1da177e4 | 1145 | |
bedfe324 LB |
1146 | static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) |
1147 | { | |
1148 | return -EINVAL; | |
1149 | } | |
1150 | ||
fc32b0e2 LB |
1151 | static void mv643xx_eth_get_drvinfo(struct net_device *dev, |
1152 | struct ethtool_drvinfo *drvinfo) | |
c9df406f | 1153 | { |
e5371493 LB |
1154 | strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); |
1155 | strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); | |
c9df406f | 1156 | strncpy(drvinfo->fw_version, "N/A", 32); |
fc32b0e2 | 1157 | strncpy(drvinfo->bus_info, "platform", 32); |
16820054 | 1158 | drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); |
c9df406f | 1159 | } |
1da177e4 | 1160 | |
fc32b0e2 | 1161 | static int mv643xx_eth_nway_reset(struct net_device *dev) |
c9df406f | 1162 | { |
e5371493 | 1163 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1164 | |
c9df406f LB |
1165 | return mii_nway_restart(&mp->mii); |
1166 | } | |
1da177e4 | 1167 | |
bedfe324 LB |
1168 | static int mv643xx_eth_nway_reset_phyless(struct net_device *dev) |
1169 | { | |
1170 | return -EINVAL; | |
1171 | } | |
1172 | ||
c9df406f LB |
1173 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1174 | { | |
e5371493 | 1175 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1176 | |
c9df406f LB |
1177 | return mii_link_ok(&mp->mii); |
1178 | } | |
1da177e4 | 1179 | |
bedfe324 LB |
1180 | static u32 mv643xx_eth_get_link_phyless(struct net_device *dev) |
1181 | { | |
1182 | return 1; | |
1183 | } | |
1184 | ||
fc32b0e2 LB |
1185 | static void mv643xx_eth_get_strings(struct net_device *dev, |
1186 | uint32_t stringset, uint8_t *data) | |
c9df406f LB |
1187 | { |
1188 | int i; | |
1da177e4 | 1189 | |
fc32b0e2 LB |
1190 | if (stringset == ETH_SS_STATS) { |
1191 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { | |
c9df406f | 1192 | memcpy(data + i * ETH_GSTRING_LEN, |
16820054 | 1193 | mv643xx_eth_stats[i].stat_string, |
e5371493 | 1194 | ETH_GSTRING_LEN); |
c9df406f | 1195 | } |
c9df406f LB |
1196 | } |
1197 | } | |
1da177e4 | 1198 | |
fc32b0e2 LB |
1199 | static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, |
1200 | struct ethtool_stats *stats, | |
1201 | uint64_t *data) | |
c9df406f | 1202 | { |
fc32b0e2 | 1203 | struct mv643xx_eth_private *mp = dev->priv; |
c9df406f | 1204 | int i; |
1da177e4 | 1205 | |
fc32b0e2 | 1206 | mib_counters_update(mp); |
1da177e4 | 1207 | |
16820054 LB |
1208 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
1209 | const struct mv643xx_eth_stats *stat; | |
1210 | void *p; | |
1211 | ||
1212 | stat = mv643xx_eth_stats + i; | |
1213 | ||
1214 | if (stat->netdev_off >= 0) | |
1215 | p = ((void *)mp->dev) + stat->netdev_off; | |
1216 | else | |
1217 | p = ((void *)mp) + stat->mp_off; | |
1218 | ||
1219 | data[i] = (stat->sizeof_stat == 8) ? | |
1220 | *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1221 | } |
c9df406f | 1222 | } |
1da177e4 | 1223 | |
fc32b0e2 | 1224 | static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) |
c9df406f | 1225 | { |
fc32b0e2 | 1226 | if (sset == ETH_SS_STATS) |
16820054 | 1227 | return ARRAY_SIZE(mv643xx_eth_stats); |
fc32b0e2 LB |
1228 | |
1229 | return -EOPNOTSUPP; | |
c9df406f | 1230 | } |
1da177e4 | 1231 | |
e5371493 | 1232 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
fc32b0e2 LB |
1233 | .get_settings = mv643xx_eth_get_settings, |
1234 | .set_settings = mv643xx_eth_set_settings, | |
1235 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1236 | .nway_reset = mv643xx_eth_nway_reset, | |
1237 | .get_link = mv643xx_eth_get_link, | |
c9df406f | 1238 | .set_sg = ethtool_op_set_sg, |
fc32b0e2 LB |
1239 | .get_strings = mv643xx_eth_get_strings, |
1240 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
e5371493 | 1241 | .get_sset_count = mv643xx_eth_get_sset_count, |
c9df406f | 1242 | }; |
1da177e4 | 1243 | |
bedfe324 LB |
1244 | static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = { |
1245 | .get_settings = mv643xx_eth_get_settings_phyless, | |
1246 | .set_settings = mv643xx_eth_set_settings_phyless, | |
1247 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1248 | .nway_reset = mv643xx_eth_nway_reset_phyless, | |
1249 | .get_link = mv643xx_eth_get_link_phyless, | |
1250 | .set_sg = ethtool_op_set_sg, | |
1251 | .get_strings = mv643xx_eth_get_strings, | |
1252 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
1253 | .get_sset_count = mv643xx_eth_get_sset_count, | |
1254 | }; | |
1255 | ||
bea3348e | 1256 | |
c9df406f | 1257 | /* address handling *********************************************************/ |
5daffe94 | 1258 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1259 | { |
c9df406f LB |
1260 | unsigned int mac_h; |
1261 | unsigned int mac_l; | |
1da177e4 | 1262 | |
fc32b0e2 LB |
1263 | mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num)); |
1264 | mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num)); | |
1da177e4 | 1265 | |
5daffe94 LB |
1266 | addr[0] = (mac_h >> 24) & 0xff; |
1267 | addr[1] = (mac_h >> 16) & 0xff; | |
1268 | addr[2] = (mac_h >> 8) & 0xff; | |
1269 | addr[3] = mac_h & 0xff; | |
1270 | addr[4] = (mac_l >> 8) & 0xff; | |
1271 | addr[5] = mac_l & 0xff; | |
c9df406f | 1272 | } |
1da177e4 | 1273 | |
e5371493 | 1274 | static void init_mac_tables(struct mv643xx_eth_private *mp) |
c9df406f | 1275 | { |
fc32b0e2 | 1276 | int i; |
1da177e4 | 1277 | |
fc32b0e2 LB |
1278 | for (i = 0; i < 0x100; i += 4) { |
1279 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0); | |
1280 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0); | |
c9df406f | 1281 | } |
fc32b0e2 LB |
1282 | |
1283 | for (i = 0; i < 0x10; i += 4) | |
1284 | wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0); | |
c9df406f | 1285 | } |
d0412d96 | 1286 | |
e5371493 | 1287 | static void set_filter_table_entry(struct mv643xx_eth_private *mp, |
fc32b0e2 | 1288 | int table, unsigned char entry) |
c9df406f LB |
1289 | { |
1290 | unsigned int table_reg; | |
ab4384a6 | 1291 | |
c9df406f | 1292 | /* Set "accepts frame bit" at specified table entry */ |
fc32b0e2 LB |
1293 | table_reg = rdl(mp, table + (entry & 0xfc)); |
1294 | table_reg |= 0x01 << (8 * (entry & 3)); | |
1295 | wrl(mp, table + (entry & 0xfc), table_reg); | |
1da177e4 LT |
1296 | } |
1297 | ||
5daffe94 | 1298 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
1da177e4 | 1299 | { |
c9df406f LB |
1300 | unsigned int mac_h; |
1301 | unsigned int mac_l; | |
1302 | int table; | |
1da177e4 | 1303 | |
fc32b0e2 LB |
1304 | mac_l = (addr[4] << 8) | addr[5]; |
1305 | mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; | |
ff561eef | 1306 | |
fc32b0e2 LB |
1307 | wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l); |
1308 | wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h); | |
1da177e4 | 1309 | |
fc32b0e2 | 1310 | table = UNICAST_TABLE(mp->port_num); |
5daffe94 | 1311 | set_filter_table_entry(mp, table, addr[5] & 0x0f); |
1da177e4 LT |
1312 | } |
1313 | ||
fc32b0e2 | 1314 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) |
1da177e4 | 1315 | { |
e5371493 | 1316 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1317 | |
fc32b0e2 LB |
1318 | /* +2 is for the offset of the HW addr type */ |
1319 | memcpy(dev->dev_addr, addr + 2, 6); | |
1320 | ||
cc9754b3 LB |
1321 | init_mac_tables(mp); |
1322 | uc_addr_set(mp, dev->dev_addr); | |
1da177e4 LT |
1323 | |
1324 | return 0; | |
1325 | } | |
1326 | ||
69876569 LB |
1327 | static int addr_crc(unsigned char *addr) |
1328 | { | |
1329 | int crc = 0; | |
1330 | int i; | |
1331 | ||
1332 | for (i = 0; i < 6; i++) { | |
1333 | int j; | |
1334 | ||
1335 | crc = (crc ^ addr[i]) << 8; | |
1336 | for (j = 7; j >= 0; j--) { | |
1337 | if (crc & (0x100 << j)) | |
1338 | crc ^= 0x107 << j; | |
1339 | } | |
1340 | } | |
1341 | ||
1342 | return crc; | |
1343 | } | |
1344 | ||
fc32b0e2 | 1345 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) |
1da177e4 | 1346 | { |
fc32b0e2 LB |
1347 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1348 | u32 port_config; | |
1349 | struct dev_addr_list *addr; | |
1350 | int i; | |
c8aaea25 | 1351 | |
fc32b0e2 LB |
1352 | port_config = rdl(mp, PORT_CONFIG(mp->port_num)); |
1353 | if (dev->flags & IFF_PROMISC) | |
1354 | port_config |= UNICAST_PROMISCUOUS_MODE; | |
1355 | else | |
1356 | port_config &= ~UNICAST_PROMISCUOUS_MODE; | |
1357 | wrl(mp, PORT_CONFIG(mp->port_num), port_config); | |
1da177e4 | 1358 | |
fc32b0e2 LB |
1359 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { |
1360 | int port_num = mp->port_num; | |
1361 | u32 accept = 0x01010101; | |
c8aaea25 | 1362 | |
fc32b0e2 LB |
1363 | for (i = 0; i < 0x100; i += 4) { |
1364 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); | |
1365 | wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); | |
c9df406f LB |
1366 | } |
1367 | return; | |
1368 | } | |
c8aaea25 | 1369 | |
fc32b0e2 LB |
1370 | for (i = 0; i < 0x100; i += 4) { |
1371 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0); | |
1372 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0); | |
1da177e4 LT |
1373 | } |
1374 | ||
fc32b0e2 LB |
1375 | for (addr = dev->mc_list; addr != NULL; addr = addr->next) { |
1376 | u8 *a = addr->da_addr; | |
1377 | int table; | |
324ff2c1 | 1378 | |
fc32b0e2 LB |
1379 | if (addr->da_addrlen != 6) |
1380 | continue; | |
1da177e4 | 1381 | |
fc32b0e2 LB |
1382 | if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { |
1383 | table = SPECIAL_MCAST_TABLE(mp->port_num); | |
1384 | set_filter_table_entry(mp, table, a[5]); | |
1385 | } else { | |
1386 | int crc = addr_crc(a); | |
1da177e4 | 1387 | |
fc32b0e2 LB |
1388 | table = OTHER_MCAST_TABLE(mp->port_num); |
1389 | set_filter_table_entry(mp, table, crc); | |
1390 | } | |
1391 | } | |
c9df406f | 1392 | } |
c8aaea25 | 1393 | |
c8aaea25 | 1394 | |
c9df406f | 1395 | /* rx/tx queue initialisation ***********************************************/ |
64da80a2 | 1396 | static int rxq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1397 | { |
64da80a2 | 1398 | struct rx_queue *rxq = mp->rxq + index; |
8a578111 LB |
1399 | struct rx_desc *rx_desc; |
1400 | int size; | |
c9df406f LB |
1401 | int i; |
1402 | ||
64da80a2 LB |
1403 | rxq->index = index; |
1404 | ||
8a578111 LB |
1405 | rxq->rx_ring_size = mp->default_rx_ring_size; |
1406 | ||
1407 | rxq->rx_desc_count = 0; | |
1408 | rxq->rx_curr_desc = 0; | |
1409 | rxq->rx_used_desc = 0; | |
1410 | ||
1411 | size = rxq->rx_ring_size * sizeof(struct rx_desc); | |
1412 | ||
64da80a2 | 1413 | if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) { |
8a578111 LB |
1414 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, |
1415 | mp->rx_desc_sram_size); | |
1416 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; | |
1417 | } else { | |
1418 | rxq->rx_desc_area = dma_alloc_coherent(NULL, size, | |
1419 | &rxq->rx_desc_dma, | |
1420 | GFP_KERNEL); | |
f7ea3337 PJ |
1421 | } |
1422 | ||
8a578111 LB |
1423 | if (rxq->rx_desc_area == NULL) { |
1424 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1425 | "can't allocate rx ring (%d bytes)\n", size); | |
1426 | goto out; | |
1427 | } | |
1428 | memset(rxq->rx_desc_area, 0, size); | |
1da177e4 | 1429 | |
8a578111 LB |
1430 | rxq->rx_desc_area_size = size; |
1431 | rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), | |
1432 | GFP_KERNEL); | |
1433 | if (rxq->rx_skb == NULL) { | |
1434 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1435 | "can't allocate rx skb ring\n"); | |
1436 | goto out_free; | |
1437 | } | |
1438 | ||
1439 | rx_desc = (struct rx_desc *)rxq->rx_desc_area; | |
1440 | for (i = 0; i < rxq->rx_ring_size; i++) { | |
1441 | int nexti = (i + 1) % rxq->rx_ring_size; | |
1442 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + | |
1443 | nexti * sizeof(struct rx_desc); | |
1444 | } | |
1445 | ||
1446 | init_timer(&rxq->rx_oom); | |
1447 | rxq->rx_oom.data = (unsigned long)rxq; | |
1448 | rxq->rx_oom.function = rxq_refill_timer_wrapper; | |
1449 | ||
1450 | return 0; | |
1451 | ||
1452 | ||
1453 | out_free: | |
64da80a2 | 1454 | if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) |
8a578111 LB |
1455 | iounmap(rxq->rx_desc_area); |
1456 | else | |
1457 | dma_free_coherent(NULL, size, | |
1458 | rxq->rx_desc_area, | |
1459 | rxq->rx_desc_dma); | |
1460 | ||
1461 | out: | |
1462 | return -ENOMEM; | |
c9df406f | 1463 | } |
c8aaea25 | 1464 | |
8a578111 | 1465 | static void rxq_deinit(struct rx_queue *rxq) |
c9df406f | 1466 | { |
8a578111 LB |
1467 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1468 | int i; | |
1469 | ||
1470 | rxq_disable(rxq); | |
c8aaea25 | 1471 | |
8a578111 | 1472 | del_timer_sync(&rxq->rx_oom); |
c9df406f | 1473 | |
8a578111 LB |
1474 | for (i = 0; i < rxq->rx_ring_size; i++) { |
1475 | if (rxq->rx_skb[i]) { | |
1476 | dev_kfree_skb(rxq->rx_skb[i]); | |
1477 | rxq->rx_desc_count--; | |
1da177e4 | 1478 | } |
c8aaea25 | 1479 | } |
1da177e4 | 1480 | |
8a578111 LB |
1481 | if (rxq->rx_desc_count) { |
1482 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1483 | "error freeing rx ring -- %d skbs stuck\n", | |
1484 | rxq->rx_desc_count); | |
1485 | } | |
1486 | ||
64da80a2 LB |
1487 | if (rxq->index == mp->rxq_primary && |
1488 | rxq->rx_desc_area_size <= mp->rx_desc_sram_size) | |
8a578111 | 1489 | iounmap(rxq->rx_desc_area); |
c9df406f | 1490 | else |
8a578111 LB |
1491 | dma_free_coherent(NULL, rxq->rx_desc_area_size, |
1492 | rxq->rx_desc_area, rxq->rx_desc_dma); | |
1493 | ||
1494 | kfree(rxq->rx_skb); | |
c9df406f | 1495 | } |
1da177e4 | 1496 | |
3d6b35bc | 1497 | static int txq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1498 | { |
3d6b35bc | 1499 | struct tx_queue *txq = mp->txq + index; |
13d64285 LB |
1500 | struct tx_desc *tx_desc; |
1501 | int size; | |
c9df406f | 1502 | int i; |
1da177e4 | 1503 | |
3d6b35bc LB |
1504 | txq->index = index; |
1505 | ||
13d64285 LB |
1506 | txq->tx_ring_size = mp->default_tx_ring_size; |
1507 | ||
1508 | txq->tx_desc_count = 0; | |
1509 | txq->tx_curr_desc = 0; | |
1510 | txq->tx_used_desc = 0; | |
1511 | ||
1512 | size = txq->tx_ring_size * sizeof(struct tx_desc); | |
1513 | ||
3d6b35bc | 1514 | if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) { |
13d64285 LB |
1515 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, |
1516 | mp->tx_desc_sram_size); | |
1517 | txq->tx_desc_dma = mp->tx_desc_sram_addr; | |
1518 | } else { | |
1519 | txq->tx_desc_area = dma_alloc_coherent(NULL, size, | |
1520 | &txq->tx_desc_dma, | |
1521 | GFP_KERNEL); | |
1522 | } | |
1523 | ||
1524 | if (txq->tx_desc_area == NULL) { | |
1525 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1526 | "can't allocate tx ring (%d bytes)\n", size); | |
1527 | goto out; | |
c9df406f | 1528 | } |
13d64285 LB |
1529 | memset(txq->tx_desc_area, 0, size); |
1530 | ||
1531 | txq->tx_desc_area_size = size; | |
1532 | txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb), | |
1533 | GFP_KERNEL); | |
1534 | if (txq->tx_skb == NULL) { | |
1535 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1536 | "can't allocate tx skb ring\n"); | |
1537 | goto out_free; | |
1538 | } | |
1539 | ||
1540 | tx_desc = (struct tx_desc *)txq->tx_desc_area; | |
1541 | for (i = 0; i < txq->tx_ring_size; i++) { | |
1542 | int nexti = (i + 1) % txq->tx_ring_size; | |
1543 | tx_desc[i].next_desc_ptr = txq->tx_desc_dma + | |
1544 | nexti * sizeof(struct tx_desc); | |
1545 | } | |
1546 | ||
1547 | return 0; | |
1548 | ||
c9df406f | 1549 | |
13d64285 | 1550 | out_free: |
3d6b35bc | 1551 | if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) |
13d64285 LB |
1552 | iounmap(txq->tx_desc_area); |
1553 | else | |
1554 | dma_free_coherent(NULL, size, | |
1555 | txq->tx_desc_area, | |
1556 | txq->tx_desc_dma); | |
c9df406f | 1557 | |
13d64285 LB |
1558 | out: |
1559 | return -ENOMEM; | |
c8aaea25 | 1560 | } |
1da177e4 | 1561 | |
13d64285 | 1562 | static void txq_reclaim(struct tx_queue *txq, int force) |
c8aaea25 | 1563 | { |
13d64285 | 1564 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
c8aaea25 | 1565 | unsigned long flags; |
1da177e4 | 1566 | |
13d64285 LB |
1567 | spin_lock_irqsave(&mp->lock, flags); |
1568 | while (txq->tx_desc_count > 0) { | |
1569 | int tx_index; | |
1570 | struct tx_desc *desc; | |
1571 | u32 cmd_sts; | |
1572 | struct sk_buff *skb; | |
1573 | dma_addr_t addr; | |
1574 | int count; | |
4d64e718 | 1575 | |
13d64285 LB |
1576 | tx_index = txq->tx_used_desc; |
1577 | desc = &txq->tx_desc_area[tx_index]; | |
c9df406f | 1578 | cmd_sts = desc->cmd_sts; |
4d64e718 | 1579 | |
13d64285 LB |
1580 | if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) |
1581 | break; | |
1da177e4 | 1582 | |
13d64285 LB |
1583 | txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size; |
1584 | txq->tx_desc_count--; | |
1da177e4 | 1585 | |
c9df406f LB |
1586 | addr = desc->buf_ptr; |
1587 | count = desc->byte_cnt; | |
13d64285 LB |
1588 | skb = txq->tx_skb[tx_index]; |
1589 | txq->tx_skb[tx_index] = NULL; | |
c8aaea25 | 1590 | |
cc9754b3 | 1591 | if (cmd_sts & ERROR_SUMMARY) { |
13d64285 LB |
1592 | dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); |
1593 | mp->dev->stats.tx_errors++; | |
c9df406f | 1594 | } |
1da177e4 | 1595 | |
13d64285 LB |
1596 | /* |
1597 | * Drop mp->lock while we free the skb. | |
1598 | */ | |
c9df406f | 1599 | spin_unlock_irqrestore(&mp->lock, flags); |
1da177e4 | 1600 | |
cc9754b3 | 1601 | if (cmd_sts & TX_FIRST_DESC) |
c9df406f LB |
1602 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); |
1603 | else | |
1604 | dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); | |
c2e5b352 | 1605 | |
c9df406f LB |
1606 | if (skb) |
1607 | dev_kfree_skb_irq(skb); | |
63c9e549 | 1608 | |
13d64285 | 1609 | spin_lock_irqsave(&mp->lock, flags); |
c9df406f | 1610 | } |
13d64285 | 1611 | spin_unlock_irqrestore(&mp->lock, flags); |
c9df406f | 1612 | } |
1da177e4 | 1613 | |
13d64285 | 1614 | static void txq_deinit(struct tx_queue *txq) |
c9df406f | 1615 | { |
13d64285 | 1616 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
fa3959f4 | 1617 | |
13d64285 LB |
1618 | txq_disable(txq); |
1619 | txq_reclaim(txq, 1); | |
1da177e4 | 1620 | |
13d64285 | 1621 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
1da177e4 | 1622 | |
3d6b35bc LB |
1623 | if (txq->index == mp->txq_primary && |
1624 | txq->tx_desc_area_size <= mp->tx_desc_sram_size) | |
13d64285 | 1625 | iounmap(txq->tx_desc_area); |
c9df406f | 1626 | else |
13d64285 LB |
1627 | dma_free_coherent(NULL, txq->tx_desc_area_size, |
1628 | txq->tx_desc_area, txq->tx_desc_dma); | |
1629 | ||
1630 | kfree(txq->tx_skb); | |
c9df406f | 1631 | } |
1da177e4 | 1632 | |
1da177e4 | 1633 | |
c9df406f | 1634 | /* netdev ops and related ***************************************************/ |
fc32b0e2 | 1635 | static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) |
c9df406f | 1636 | { |
13d64285 LB |
1637 | u32 pscr_o; |
1638 | u32 pscr_n; | |
1da177e4 | 1639 | |
13d64285 | 1640 | pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); |
63c9e549 | 1641 | |
c9df406f | 1642 | /* clear speed, duplex and rx buffer size fields */ |
13d64285 LB |
1643 | pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 | |
1644 | SET_GMII_SPEED_TO_1000 | | |
1645 | SET_FULL_DUPLEX_MODE | | |
1646 | MAX_RX_PACKET_MASK); | |
1da177e4 | 1647 | |
fc32b0e2 | 1648 | if (speed == SPEED_1000) { |
13d64285 LB |
1649 | pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE; |
1650 | } else { | |
fc32b0e2 | 1651 | if (speed == SPEED_100) |
13d64285 LB |
1652 | pscr_n |= SET_MII_SPEED_TO_100; |
1653 | pscr_n |= MAX_RX_PACKET_1522BYTE; | |
c9df406f | 1654 | } |
1da177e4 | 1655 | |
fc32b0e2 | 1656 | if (duplex == DUPLEX_FULL) |
13d64285 LB |
1657 | pscr_n |= SET_FULL_DUPLEX_MODE; |
1658 | ||
1659 | if (pscr_n != pscr_o) { | |
1660 | if ((pscr_o & SERIAL_PORT_ENABLE) == 0) | |
1661 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); | |
c9df406f | 1662 | else { |
3d6b35bc LB |
1663 | int i; |
1664 | ||
1665 | for (i = 0; i < 8; i++) | |
1666 | if (mp->txq_mask & (1 << i)) | |
1667 | txq_disable(mp->txq + i); | |
1668 | ||
13d64285 LB |
1669 | pscr_o &= ~SERIAL_PORT_ENABLE; |
1670 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o); | |
1671 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); | |
1672 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); | |
3d6b35bc LB |
1673 | |
1674 | for (i = 0; i < 8; i++) | |
1675 | if (mp->txq_mask & (1 << i)) | |
1676 | txq_enable(mp->txq + i); | |
c9df406f LB |
1677 | } |
1678 | } | |
1679 | } | |
84dd619e | 1680 | |
fc32b0e2 | 1681 | static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) |
c9df406f LB |
1682 | { |
1683 | struct net_device *dev = (struct net_device *)dev_id; | |
e5371493 | 1684 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
fc32b0e2 LB |
1685 | u32 int_cause; |
1686 | u32 int_cause_ext; | |
226bb6b7 | 1687 | u32 txq_active; |
ce4e2e45 | 1688 | |
226bb6b7 LB |
1689 | int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & |
1690 | (INT_TX_END | INT_RX | INT_EXT); | |
fc32b0e2 LB |
1691 | if (int_cause == 0) |
1692 | return IRQ_NONE; | |
1693 | ||
1694 | int_cause_ext = 0; | |
cc9754b3 | 1695 | if (int_cause & INT_EXT) { |
13d64285 | 1696 | int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num)) |
073a345c | 1697 | & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
13d64285 | 1698 | wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext); |
c9df406f | 1699 | } |
1da177e4 | 1700 | |
fc32b0e2 | 1701 | if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) { |
bedfe324 | 1702 | if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) { |
3d6b35bc | 1703 | int i; |
13d64285 | 1704 | |
bedfe324 LB |
1705 | if (mp->phy_addr != -1) { |
1706 | struct ethtool_cmd cmd; | |
1707 | ||
1708 | mii_ethtool_gset(&mp->mii, &cmd); | |
1709 | update_pscr(mp, cmd.speed, cmd.duplex); | |
1710 | } | |
1711 | ||
3d6b35bc LB |
1712 | for (i = 0; i < 8; i++) |
1713 | if (mp->txq_mask & (1 << i)) | |
1714 | txq_enable(mp->txq + i); | |
1715 | ||
c9df406f LB |
1716 | if (!netif_carrier_ok(dev)) { |
1717 | netif_carrier_on(dev); | |
3d6b35bc | 1718 | __txq_maybe_wake(mp->txq + mp->txq_primary); |
c9df406f LB |
1719 | } |
1720 | } else if (netif_carrier_ok(dev)) { | |
1721 | netif_stop_queue(dev); | |
1722 | netif_carrier_off(dev); | |
1723 | } | |
1724 | } | |
1da177e4 | 1725 | |
64da80a2 LB |
1726 | /* |
1727 | * RxBuffer or RxError set for any of the 8 queues? | |
1728 | */ | |
e5371493 | 1729 | #ifdef MV643XX_ETH_NAPI |
cc9754b3 | 1730 | if (int_cause & INT_RX) { |
13d64285 | 1731 | wrl(mp, INT_MASK(mp->port_num), 0x00000000); |
13d64285 | 1732 | rdl(mp, INT_MASK(mp->port_num)); |
1da177e4 | 1733 | |
c9df406f | 1734 | netif_rx_schedule(dev, &mp->napi); |
84dd619e | 1735 | } |
c9df406f | 1736 | #else |
64da80a2 LB |
1737 | if (int_cause & INT_RX) { |
1738 | int i; | |
1739 | ||
1740 | for (i = 7; i >= 0; i--) | |
1741 | if (mp->rxq_mask & (1 << i)) | |
1742 | rxq_process(mp->rxq + i, INT_MAX); | |
1743 | } | |
c9df406f | 1744 | #endif |
fc32b0e2 | 1745 | |
226bb6b7 LB |
1746 | txq_active = rdl(mp, TXQ_COMMAND(mp->port_num)); |
1747 | ||
3d6b35bc LB |
1748 | /* |
1749 | * TxBuffer or TxError set for any of the 8 queues? | |
1750 | */ | |
13d64285 | 1751 | if (int_cause_ext & INT_EXT_TX) { |
3d6b35bc LB |
1752 | int i; |
1753 | ||
1754 | for (i = 0; i < 8; i++) | |
1755 | if (mp->txq_mask & (1 << i)) | |
1756 | txq_reclaim(mp->txq + i, 0); | |
226bb6b7 | 1757 | } |
3d6b35bc | 1758 | |
226bb6b7 LB |
1759 | /* |
1760 | * Any TxEnd interrupts? | |
1761 | */ | |
1762 | if (int_cause & INT_TX_END) { | |
1763 | int i; | |
1764 | ||
1765 | wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END)); | |
1766 | for (i = 0; i < 8; i++) { | |
1767 | struct tx_queue *txq = mp->txq + i; | |
1768 | if (txq->tx_desc_count && !((txq_active >> i) & 1)) | |
1769 | txq_enable(txq); | |
1770 | } | |
1771 | } | |
1772 | ||
1773 | /* | |
1774 | * Enough space again in the primary TX queue for a full packet? | |
1775 | */ | |
1776 | if (int_cause_ext & INT_EXT_TX) { | |
1777 | struct tx_queue *txq = mp->txq + mp->txq_primary; | |
1778 | __txq_maybe_wake(txq); | |
13d64285 | 1779 | } |
1da177e4 | 1780 | |
c9df406f | 1781 | return IRQ_HANDLED; |
1da177e4 LT |
1782 | } |
1783 | ||
e5371493 | 1784 | static void phy_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 1785 | { |
fc32b0e2 | 1786 | unsigned int data; |
1da177e4 | 1787 | |
fc32b0e2 LB |
1788 | smi_reg_read(mp, mp->phy_addr, 0, &data); |
1789 | data |= 0x8000; | |
1790 | smi_reg_write(mp, mp->phy_addr, 0, data); | |
1da177e4 | 1791 | |
c9df406f LB |
1792 | do { |
1793 | udelay(1); | |
fc32b0e2 LB |
1794 | smi_reg_read(mp, mp->phy_addr, 0, &data); |
1795 | } while (data & 0x8000); | |
1da177e4 LT |
1796 | } |
1797 | ||
fc32b0e2 | 1798 | static void port_start(struct mv643xx_eth_private *mp) |
1da177e4 | 1799 | { |
d0412d96 | 1800 | u32 pscr; |
8a578111 | 1801 | int i; |
1da177e4 | 1802 | |
8a578111 LB |
1803 | /* |
1804 | * Configure basic link parameters. | |
1805 | */ | |
1806 | pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); | |
1807 | pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); | |
1808 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1809 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | | |
1810 | DISABLE_AUTO_NEG_SPEED_GMII | | |
1811 | DISABLE_AUTO_NEG_FOR_DUPLEX | | |
1812 | DO_NOT_FORCE_LINK_FAIL | | |
1813 | SERIAL_PORT_CONTROL_RESERVED; | |
1814 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1815 | pscr |= SERIAL_PORT_ENABLE; | |
1816 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1da177e4 | 1817 | |
8a578111 LB |
1818 | wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE); |
1819 | ||
bedfe324 LB |
1820 | /* |
1821 | * Perform PHY reset, if there is a PHY. | |
1822 | */ | |
1823 | if (mp->phy_addr != -1) { | |
1824 | struct ethtool_cmd cmd; | |
1825 | ||
1826 | mv643xx_eth_get_settings(mp->dev, &cmd); | |
1827 | phy_reset(mp); | |
1828 | mv643xx_eth_set_settings(mp->dev, &cmd); | |
1829 | } | |
1da177e4 | 1830 | |
13d64285 LB |
1831 | /* |
1832 | * Configure TX path and queues. | |
1833 | */ | |
89df5fdc | 1834 | tx_set_rate(mp, 1000000000, 16777216); |
3d6b35bc LB |
1835 | for (i = 0; i < 8; i++) { |
1836 | struct tx_queue *txq = mp->txq + i; | |
1837 | int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i); | |
13d64285 LB |
1838 | u32 addr; |
1839 | ||
3d6b35bc LB |
1840 | if ((mp->txq_mask & (1 << i)) == 0) |
1841 | continue; | |
1842 | ||
13d64285 LB |
1843 | addr = (u32)txq->tx_desc_dma; |
1844 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); | |
1845 | wrl(mp, off, addr); | |
89df5fdc LB |
1846 | |
1847 | txq_set_rate(txq, 1000000000, 16777216); | |
1848 | txq_set_fixed_prio_mode(txq); | |
13d64285 LB |
1849 | } |
1850 | ||
fc32b0e2 LB |
1851 | /* |
1852 | * Add configured unicast address to address filter table. | |
1853 | */ | |
1854 | uc_addr_set(mp, mp->dev->dev_addr); | |
1da177e4 | 1855 | |
d9a073ea LB |
1856 | /* |
1857 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
1858 | * frames to RX queue #0. | |
1859 | */ | |
8a578111 | 1860 | wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000); |
01999873 | 1861 | |
376489a2 LB |
1862 | /* |
1863 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
1864 | */ | |
8a578111 | 1865 | wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000); |
01999873 | 1866 | |
8a578111 | 1867 | /* |
64da80a2 | 1868 | * Enable the receive queues. |
8a578111 | 1869 | */ |
64da80a2 LB |
1870 | for (i = 0; i < 8; i++) { |
1871 | struct rx_queue *rxq = mp->rxq + i; | |
1872 | int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i); | |
8a578111 | 1873 | u32 addr; |
1da177e4 | 1874 | |
64da80a2 LB |
1875 | if ((mp->rxq_mask & (1 << i)) == 0) |
1876 | continue; | |
1877 | ||
8a578111 LB |
1878 | addr = (u32)rxq->rx_desc_dma; |
1879 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); | |
1880 | wrl(mp, off, addr); | |
1da177e4 | 1881 | |
8a578111 LB |
1882 | rxq_enable(rxq); |
1883 | } | |
1da177e4 LT |
1884 | } |
1885 | ||
ffd86bbe | 1886 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay) |
1da177e4 | 1887 | { |
c9df406f | 1888 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
773fc3ee | 1889 | u32 val; |
1da177e4 | 1890 | |
773fc3ee LB |
1891 | val = rdl(mp, SDMA_CONFIG(mp->port_num)); |
1892 | if (mp->shared->extended_rx_coal_limit) { | |
1893 | if (coal > 0xffff) | |
1894 | coal = 0xffff; | |
1895 | val &= ~0x023fff80; | |
1896 | val |= (coal & 0x8000) << 10; | |
1897 | val |= (coal & 0x7fff) << 7; | |
1898 | } else { | |
1899 | if (coal > 0x3fff) | |
1900 | coal = 0x3fff; | |
1901 | val &= ~0x003fff00; | |
1902 | val |= (coal & 0x3fff) << 8; | |
1903 | } | |
1904 | wrl(mp, SDMA_CONFIG(mp->port_num), val); | |
1da177e4 LT |
1905 | } |
1906 | ||
ffd86bbe | 1907 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay) |
1da177e4 | 1908 | { |
c9df406f | 1909 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 1910 | |
fc32b0e2 LB |
1911 | if (coal > 0x3fff) |
1912 | coal = 0x3fff; | |
1913 | wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4); | |
16e03018 DF |
1914 | } |
1915 | ||
c9df406f | 1916 | static int mv643xx_eth_open(struct net_device *dev) |
16e03018 | 1917 | { |
e5371493 | 1918 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 1919 | int err; |
64da80a2 | 1920 | int i; |
16e03018 | 1921 | |
fc32b0e2 LB |
1922 | wrl(mp, INT_CAUSE(mp->port_num), 0); |
1923 | wrl(mp, INT_CAUSE_EXT(mp->port_num), 0); | |
1924 | rdl(mp, INT_CAUSE_EXT(mp->port_num)); | |
c9df406f | 1925 | |
fc32b0e2 LB |
1926 | err = request_irq(dev->irq, mv643xx_eth_irq, |
1927 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, | |
1928 | dev->name, dev); | |
c9df406f | 1929 | if (err) { |
fc32b0e2 | 1930 | dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); |
c9df406f | 1931 | return -EAGAIN; |
16e03018 DF |
1932 | } |
1933 | ||
fc32b0e2 | 1934 | init_mac_tables(mp); |
16e03018 | 1935 | |
64da80a2 LB |
1936 | for (i = 0; i < 8; i++) { |
1937 | if ((mp->rxq_mask & (1 << i)) == 0) | |
1938 | continue; | |
1939 | ||
1940 | err = rxq_init(mp, i); | |
1941 | if (err) { | |
1942 | while (--i >= 0) | |
1943 | if (mp->rxq_mask & (1 << i)) | |
1944 | rxq_deinit(mp->rxq + i); | |
1945 | goto out; | |
1946 | } | |
1947 | ||
1948 | rxq_refill(mp->rxq + i); | |
1949 | } | |
8a578111 | 1950 | |
3d6b35bc LB |
1951 | for (i = 0; i < 8; i++) { |
1952 | if ((mp->txq_mask & (1 << i)) == 0) | |
1953 | continue; | |
1954 | ||
1955 | err = txq_init(mp, i); | |
1956 | if (err) { | |
1957 | while (--i >= 0) | |
1958 | if (mp->txq_mask & (1 << i)) | |
1959 | txq_deinit(mp->txq + i); | |
1960 | goto out_free; | |
1961 | } | |
1962 | } | |
16e03018 | 1963 | |
e5371493 | 1964 | #ifdef MV643XX_ETH_NAPI |
c9df406f LB |
1965 | napi_enable(&mp->napi); |
1966 | #endif | |
16e03018 | 1967 | |
fc32b0e2 | 1968 | port_start(mp); |
16e03018 | 1969 | |
ffd86bbe LB |
1970 | set_rx_coal(mp, 0); |
1971 | set_tx_coal(mp, 0); | |
16e03018 | 1972 | |
fc32b0e2 LB |
1973 | wrl(mp, INT_MASK_EXT(mp->port_num), |
1974 | INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); | |
16e03018 | 1975 | |
226bb6b7 | 1976 | wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); |
16e03018 | 1977 | |
c9df406f LB |
1978 | return 0; |
1979 | ||
13d64285 | 1980 | |
fc32b0e2 | 1981 | out_free: |
64da80a2 LB |
1982 | for (i = 0; i < 8; i++) |
1983 | if (mp->rxq_mask & (1 << i)) | |
1984 | rxq_deinit(mp->rxq + i); | |
fc32b0e2 | 1985 | out: |
c9df406f LB |
1986 | free_irq(dev->irq, dev); |
1987 | ||
1988 | return err; | |
16e03018 DF |
1989 | } |
1990 | ||
e5371493 | 1991 | static void port_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 1992 | { |
fc32b0e2 | 1993 | unsigned int data; |
64da80a2 | 1994 | int i; |
1da177e4 | 1995 | |
64da80a2 LB |
1996 | for (i = 0; i < 8; i++) { |
1997 | if (mp->rxq_mask & (1 << i)) | |
1998 | rxq_disable(mp->rxq + i); | |
3d6b35bc LB |
1999 | if (mp->txq_mask & (1 << i)) |
2000 | txq_disable(mp->txq + i); | |
64da80a2 | 2001 | } |
13d64285 LB |
2002 | while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY)) |
2003 | udelay(10); | |
1da177e4 | 2004 | |
c9df406f | 2005 | /* Reset the Enable bit in the Configuration Register */ |
fc32b0e2 LB |
2006 | data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); |
2007 | data &= ~(SERIAL_PORT_ENABLE | | |
2008 | DO_NOT_FORCE_LINK_FAIL | | |
2009 | FORCE_LINK_PASS); | |
2010 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data); | |
1da177e4 LT |
2011 | } |
2012 | ||
c9df406f | 2013 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 | 2014 | { |
e5371493 | 2015 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
64da80a2 | 2016 | int i; |
1da177e4 | 2017 | |
fc32b0e2 LB |
2018 | wrl(mp, INT_MASK(mp->port_num), 0x00000000); |
2019 | rdl(mp, INT_MASK(mp->port_num)); | |
1da177e4 | 2020 | |
e5371493 | 2021 | #ifdef MV643XX_ETH_NAPI |
c9df406f LB |
2022 | napi_disable(&mp->napi); |
2023 | #endif | |
2024 | netif_carrier_off(dev); | |
2025 | netif_stop_queue(dev); | |
1da177e4 | 2026 | |
fc32b0e2 LB |
2027 | free_irq(dev->irq, dev); |
2028 | ||
cc9754b3 | 2029 | port_reset(mp); |
fc32b0e2 | 2030 | mib_counters_update(mp); |
1da177e4 | 2031 | |
64da80a2 LB |
2032 | for (i = 0; i < 8; i++) { |
2033 | if (mp->rxq_mask & (1 << i)) | |
2034 | rxq_deinit(mp->rxq + i); | |
3d6b35bc LB |
2035 | if (mp->txq_mask & (1 << i)) |
2036 | txq_deinit(mp->txq + i); | |
64da80a2 | 2037 | } |
1da177e4 | 2038 | |
c9df406f | 2039 | return 0; |
1da177e4 LT |
2040 | } |
2041 | ||
fc32b0e2 | 2042 | static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2043 | { |
e5371493 | 2044 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2045 | |
bedfe324 LB |
2046 | if (mp->phy_addr != -1) |
2047 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); | |
2048 | ||
2049 | return -EOPNOTSUPP; | |
1da177e4 LT |
2050 | } |
2051 | ||
c9df406f | 2052 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2053 | { |
89df5fdc LB |
2054 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
2055 | ||
fc32b0e2 | 2056 | if (new_mtu < 64 || new_mtu > 9500) |
c9df406f | 2057 | return -EINVAL; |
1da177e4 | 2058 | |
c9df406f | 2059 | dev->mtu = new_mtu; |
89df5fdc LB |
2060 | tx_set_rate(mp, 1000000000, 16777216); |
2061 | ||
c9df406f LB |
2062 | if (!netif_running(dev)) |
2063 | return 0; | |
1da177e4 | 2064 | |
c9df406f LB |
2065 | /* |
2066 | * Stop and then re-open the interface. This will allocate RX | |
2067 | * skbs of the new MTU. | |
2068 | * There is a possible danger that the open will not succeed, | |
fc32b0e2 | 2069 | * due to memory being full. |
c9df406f LB |
2070 | */ |
2071 | mv643xx_eth_stop(dev); | |
2072 | if (mv643xx_eth_open(dev)) { | |
fc32b0e2 LB |
2073 | dev_printk(KERN_ERR, &dev->dev, |
2074 | "fatal error on re-opening device after " | |
2075 | "MTU change\n"); | |
c9df406f LB |
2076 | } |
2077 | ||
2078 | return 0; | |
1da177e4 LT |
2079 | } |
2080 | ||
fc32b0e2 | 2081 | static void tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2082 | { |
fc32b0e2 | 2083 | struct mv643xx_eth_private *mp; |
1da177e4 | 2084 | |
fc32b0e2 LB |
2085 | mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); |
2086 | if (netif_running(mp->dev)) { | |
2087 | netif_stop_queue(mp->dev); | |
c9df406f | 2088 | |
fc32b0e2 LB |
2089 | port_reset(mp); |
2090 | port_start(mp); | |
c9df406f | 2091 | |
3d6b35bc | 2092 | __txq_maybe_wake(mp->txq + mp->txq_primary); |
fc32b0e2 | 2093 | } |
c9df406f LB |
2094 | } |
2095 | ||
c9df406f | 2096 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2097 | { |
e5371493 | 2098 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2099 | |
fc32b0e2 | 2100 | dev_printk(KERN_INFO, &dev->dev, "tx timeout\n"); |
d0412d96 | 2101 | |
c9df406f | 2102 | schedule_work(&mp->tx_timeout_task); |
1da177e4 LT |
2103 | } |
2104 | ||
c9df406f | 2105 | #ifdef CONFIG_NET_POLL_CONTROLLER |
fc32b0e2 | 2106 | static void mv643xx_eth_netpoll(struct net_device *dev) |
9f8dd319 | 2107 | { |
fc32b0e2 | 2108 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2109 | |
fc32b0e2 LB |
2110 | wrl(mp, INT_MASK(mp->port_num), 0x00000000); |
2111 | rdl(mp, INT_MASK(mp->port_num)); | |
c9df406f | 2112 | |
fc32b0e2 | 2113 | mv643xx_eth_irq(dev->irq, dev); |
c9df406f | 2114 | |
226bb6b7 | 2115 | wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT); |
9f8dd319 | 2116 | } |
c9df406f | 2117 | #endif |
9f8dd319 | 2118 | |
fc32b0e2 | 2119 | static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg) |
9f8dd319 | 2120 | { |
e5371493 | 2121 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f LB |
2122 | int val; |
2123 | ||
fc32b0e2 LB |
2124 | smi_reg_read(mp, addr, reg, &val); |
2125 | ||
c9df406f | 2126 | return val; |
9f8dd319 DF |
2127 | } |
2128 | ||
fc32b0e2 | 2129 | static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val) |
9f8dd319 | 2130 | { |
e5371493 | 2131 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
fc32b0e2 | 2132 | smi_reg_write(mp, addr, reg, val); |
c9df406f | 2133 | } |
9f8dd319 | 2134 | |
9f8dd319 | 2135 | |
c9df406f | 2136 | /* platform glue ************************************************************/ |
e5371493 LB |
2137 | static void |
2138 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, | |
2139 | struct mbus_dram_target_info *dram) | |
c9df406f | 2140 | { |
cc9754b3 | 2141 | void __iomem *base = msp->base; |
c9df406f LB |
2142 | u32 win_enable; |
2143 | u32 win_protect; | |
2144 | int i; | |
9f8dd319 | 2145 | |
c9df406f LB |
2146 | for (i = 0; i < 6; i++) { |
2147 | writel(0, base + WINDOW_BASE(i)); | |
2148 | writel(0, base + WINDOW_SIZE(i)); | |
2149 | if (i < 4) | |
2150 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2151 | } |
2152 | ||
c9df406f LB |
2153 | win_enable = 0x3f; |
2154 | win_protect = 0; | |
2155 | ||
2156 | for (i = 0; i < dram->num_cs; i++) { | |
2157 | struct mbus_dram_window *cs = dram->cs + i; | |
2158 | ||
2159 | writel((cs->base & 0xffff0000) | | |
2160 | (cs->mbus_attr << 8) | | |
2161 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2162 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2163 | ||
2164 | win_enable &= ~(1 << i); | |
2165 | win_protect |= 3 << (2 * i); | |
2166 | } | |
2167 | ||
2168 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2169 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2170 | } |
2171 | ||
773fc3ee LB |
2172 | static void infer_hw_params(struct mv643xx_eth_shared_private *msp) |
2173 | { | |
2174 | /* | |
2175 | * Check whether we have a 14-bit coal limit field in bits | |
2176 | * [21:8], or a 16-bit coal limit in bits [25,21:7] of the | |
2177 | * SDMA config register. | |
2178 | */ | |
2179 | writel(0x02000000, msp->base + SDMA_CONFIG(0)); | |
2180 | if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000) | |
2181 | msp->extended_rx_coal_limit = 1; | |
2182 | else | |
2183 | msp->extended_rx_coal_limit = 0; | |
1e881592 LB |
2184 | |
2185 | /* | |
2186 | * Check whether the TX rate control registers are in the | |
2187 | * old or the new place. | |
2188 | */ | |
2189 | writel(1, msp->base + TX_BW_MTU_MOVED(0)); | |
2190 | if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) | |
2191 | msp->tx_bw_control_moved = 1; | |
2192 | else | |
2193 | msp->tx_bw_control_moved = 0; | |
773fc3ee LB |
2194 | } |
2195 | ||
c9df406f | 2196 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2197 | { |
e5371493 | 2198 | static int mv643xx_eth_version_printed = 0; |
c9df406f | 2199 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
e5371493 | 2200 | struct mv643xx_eth_shared_private *msp; |
c9df406f LB |
2201 | struct resource *res; |
2202 | int ret; | |
9f8dd319 | 2203 | |
e5371493 | 2204 | if (!mv643xx_eth_version_printed++) |
c9df406f | 2205 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); |
9f8dd319 | 2206 | |
c9df406f LB |
2207 | ret = -EINVAL; |
2208 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2209 | if (res == NULL) | |
2210 | goto out; | |
9f8dd319 | 2211 | |
c9df406f LB |
2212 | ret = -ENOMEM; |
2213 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2214 | if (msp == NULL) | |
2215 | goto out; | |
2216 | memset(msp, 0, sizeof(*msp)); | |
2217 | ||
cc9754b3 LB |
2218 | msp->base = ioremap(res->start, res->end - res->start + 1); |
2219 | if (msp->base == NULL) | |
c9df406f LB |
2220 | goto out_free; |
2221 | ||
2222 | spin_lock_init(&msp->phy_lock); | |
c9df406f LB |
2223 | |
2224 | /* | |
2225 | * (Re-)program MBUS remapping windows if we are asked to. | |
2226 | */ | |
2227 | if (pd != NULL && pd->dram != NULL) | |
2228 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2229 | ||
fc32b0e2 LB |
2230 | /* |
2231 | * Detect hardware parameters. | |
2232 | */ | |
2233 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
773fc3ee | 2234 | infer_hw_params(msp); |
fc32b0e2 LB |
2235 | |
2236 | platform_set_drvdata(pdev, msp); | |
2237 | ||
c9df406f LB |
2238 | return 0; |
2239 | ||
2240 | out_free: | |
2241 | kfree(msp); | |
2242 | out: | |
2243 | return ret; | |
2244 | } | |
2245 | ||
2246 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2247 | { | |
e5371493 | 2248 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
c9df406f | 2249 | |
cc9754b3 | 2250 | iounmap(msp->base); |
c9df406f LB |
2251 | kfree(msp); |
2252 | ||
2253 | return 0; | |
9f8dd319 DF |
2254 | } |
2255 | ||
c9df406f | 2256 | static struct platform_driver mv643xx_eth_shared_driver = { |
fc32b0e2 LB |
2257 | .probe = mv643xx_eth_shared_probe, |
2258 | .remove = mv643xx_eth_shared_remove, | |
c9df406f | 2259 | .driver = { |
fc32b0e2 | 2260 | .name = MV643XX_ETH_SHARED_NAME, |
c9df406f LB |
2261 | .owner = THIS_MODULE, |
2262 | }, | |
2263 | }; | |
2264 | ||
e5371493 | 2265 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
1da177e4 | 2266 | { |
c9df406f | 2267 | int addr_shift = 5 * mp->port_num; |
fc32b0e2 | 2268 | u32 data; |
1da177e4 | 2269 | |
fc32b0e2 LB |
2270 | data = rdl(mp, PHY_ADDR); |
2271 | data &= ~(0x1f << addr_shift); | |
2272 | data |= (phy_addr & 0x1f) << addr_shift; | |
2273 | wrl(mp, PHY_ADDR, data); | |
1da177e4 LT |
2274 | } |
2275 | ||
e5371493 | 2276 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
1da177e4 | 2277 | { |
fc32b0e2 LB |
2278 | unsigned int data; |
2279 | ||
2280 | data = rdl(mp, PHY_ADDR); | |
2281 | ||
2282 | return (data >> (5 * mp->port_num)) & 0x1f; | |
2283 | } | |
2284 | ||
2285 | static void set_params(struct mv643xx_eth_private *mp, | |
2286 | struct mv643xx_eth_platform_data *pd) | |
2287 | { | |
2288 | struct net_device *dev = mp->dev; | |
2289 | ||
2290 | if (is_valid_ether_addr(pd->mac_addr)) | |
2291 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2292 | else | |
2293 | uc_addr_get(mp, dev->dev_addr); | |
2294 | ||
2295 | if (pd->phy_addr == -1) { | |
2296 | mp->shared_smi = NULL; | |
2297 | mp->phy_addr = -1; | |
2298 | } else { | |
2299 | mp->shared_smi = mp->shared; | |
2300 | if (pd->shared_smi != NULL) | |
2301 | mp->shared_smi = platform_get_drvdata(pd->shared_smi); | |
2302 | ||
2303 | if (pd->force_phy_addr || pd->phy_addr) { | |
2304 | mp->phy_addr = pd->phy_addr & 0x3f; | |
2305 | phy_addr_set(mp, mp->phy_addr); | |
2306 | } else { | |
2307 | mp->phy_addr = phy_addr_get(mp); | |
2308 | } | |
2309 | } | |
1da177e4 | 2310 | |
fc32b0e2 LB |
2311 | mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
2312 | if (pd->rx_queue_size) | |
2313 | mp->default_rx_ring_size = pd->rx_queue_size; | |
2314 | mp->rx_desc_sram_addr = pd->rx_sram_addr; | |
2315 | mp->rx_desc_sram_size = pd->rx_sram_size; | |
1da177e4 | 2316 | |
64da80a2 LB |
2317 | if (pd->rx_queue_mask) |
2318 | mp->rxq_mask = pd->rx_queue_mask; | |
2319 | else | |
2320 | mp->rxq_mask = 0x01; | |
2321 | mp->rxq_primary = fls(mp->rxq_mask) - 1; | |
2322 | ||
fc32b0e2 LB |
2323 | mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
2324 | if (pd->tx_queue_size) | |
2325 | mp->default_tx_ring_size = pd->tx_queue_size; | |
2326 | mp->tx_desc_sram_addr = pd->tx_sram_addr; | |
2327 | mp->tx_desc_sram_size = pd->tx_sram_size; | |
3d6b35bc LB |
2328 | |
2329 | if (pd->tx_queue_mask) | |
2330 | mp->txq_mask = pd->tx_queue_mask; | |
2331 | else | |
2332 | mp->txq_mask = 0x01; | |
2333 | mp->txq_primary = fls(mp->txq_mask) - 1; | |
1da177e4 LT |
2334 | } |
2335 | ||
e5371493 | 2336 | static int phy_detect(struct mv643xx_eth_private *mp) |
1da177e4 | 2337 | { |
fc32b0e2 LB |
2338 | unsigned int data; |
2339 | unsigned int data2; | |
2340 | ||
2341 | smi_reg_read(mp, mp->phy_addr, 0, &data); | |
2342 | smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000); | |
1da177e4 | 2343 | |
fc32b0e2 LB |
2344 | smi_reg_read(mp, mp->phy_addr, 0, &data2); |
2345 | if (((data ^ data2) & 0x1000) == 0) | |
2346 | return -ENODEV; | |
1da177e4 | 2347 | |
fc32b0e2 | 2348 | smi_reg_write(mp, mp->phy_addr, 0, data); |
1da177e4 | 2349 | |
c9df406f | 2350 | return 0; |
1da177e4 LT |
2351 | } |
2352 | ||
fc32b0e2 LB |
2353 | static int phy_init(struct mv643xx_eth_private *mp, |
2354 | struct mv643xx_eth_platform_data *pd) | |
c28a4f89 | 2355 | { |
fc32b0e2 LB |
2356 | struct ethtool_cmd cmd; |
2357 | int err; | |
c28a4f89 | 2358 | |
fc32b0e2 LB |
2359 | err = phy_detect(mp); |
2360 | if (err) { | |
2361 | dev_printk(KERN_INFO, &mp->dev->dev, | |
2362 | "no PHY detected at addr %d\n", mp->phy_addr); | |
2363 | return err; | |
2364 | } | |
2365 | phy_reset(mp); | |
2366 | ||
2367 | mp->mii.phy_id = mp->phy_addr; | |
2368 | mp->mii.phy_id_mask = 0x3f; | |
2369 | mp->mii.reg_num_mask = 0x1f; | |
2370 | mp->mii.dev = mp->dev; | |
2371 | mp->mii.mdio_read = mv643xx_eth_mdio_read; | |
2372 | mp->mii.mdio_write = mv643xx_eth_mdio_write; | |
c28a4f89 | 2373 | |
fc32b0e2 | 2374 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); |
c9df406f | 2375 | |
fc32b0e2 LB |
2376 | memset(&cmd, 0, sizeof(cmd)); |
2377 | ||
2378 | cmd.port = PORT_MII; | |
2379 | cmd.transceiver = XCVR_INTERNAL; | |
2380 | cmd.phy_address = mp->phy_addr; | |
2381 | if (pd->speed == 0) { | |
2382 | cmd.autoneg = AUTONEG_ENABLE; | |
2383 | cmd.speed = SPEED_100; | |
2384 | cmd.advertising = ADVERTISED_10baseT_Half | | |
2385 | ADVERTISED_10baseT_Full | | |
2386 | ADVERTISED_100baseT_Half | | |
2387 | ADVERTISED_100baseT_Full; | |
c9df406f | 2388 | if (mp->mii.supports_gmii) |
fc32b0e2 | 2389 | cmd.advertising |= ADVERTISED_1000baseT_Full; |
c9df406f | 2390 | } else { |
fc32b0e2 LB |
2391 | cmd.autoneg = AUTONEG_DISABLE; |
2392 | cmd.speed = pd->speed; | |
2393 | cmd.duplex = pd->duplex; | |
c9df406f | 2394 | } |
fc32b0e2 LB |
2395 | |
2396 | update_pscr(mp, cmd.speed, cmd.duplex); | |
2397 | mv643xx_eth_set_settings(mp->dev, &cmd); | |
2398 | ||
2399 | return 0; | |
c28a4f89 JC |
2400 | } |
2401 | ||
c9df406f | 2402 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2403 | { |
c9df406f | 2404 | struct mv643xx_eth_platform_data *pd; |
e5371493 | 2405 | struct mv643xx_eth_private *mp; |
c9df406f | 2406 | struct net_device *dev; |
c9df406f | 2407 | struct resource *res; |
c9df406f | 2408 | DECLARE_MAC_BUF(mac); |
fc32b0e2 | 2409 | int err; |
1da177e4 | 2410 | |
c9df406f LB |
2411 | pd = pdev->dev.platform_data; |
2412 | if (pd == NULL) { | |
fc32b0e2 LB |
2413 | dev_printk(KERN_ERR, &pdev->dev, |
2414 | "no mv643xx_eth_platform_data\n"); | |
c9df406f LB |
2415 | return -ENODEV; |
2416 | } | |
1da177e4 | 2417 | |
c9df406f | 2418 | if (pd->shared == NULL) { |
fc32b0e2 LB |
2419 | dev_printk(KERN_ERR, &pdev->dev, |
2420 | "no mv643xx_eth_platform_data->shared\n"); | |
c9df406f LB |
2421 | return -ENODEV; |
2422 | } | |
8f518703 | 2423 | |
e5371493 | 2424 | dev = alloc_etherdev(sizeof(struct mv643xx_eth_private)); |
c9df406f LB |
2425 | if (!dev) |
2426 | return -ENOMEM; | |
1da177e4 | 2427 | |
c9df406f | 2428 | mp = netdev_priv(dev); |
fc32b0e2 LB |
2429 | platform_set_drvdata(pdev, mp); |
2430 | ||
2431 | mp->shared = platform_get_drvdata(pd->shared); | |
2432 | mp->port_num = pd->port_number; | |
2433 | ||
c9df406f | 2434 | mp->dev = dev; |
e5371493 LB |
2435 | #ifdef MV643XX_ETH_NAPI |
2436 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64); | |
c9df406f | 2437 | #endif |
1da177e4 | 2438 | |
fc32b0e2 LB |
2439 | set_params(mp, pd); |
2440 | ||
2441 | spin_lock_init(&mp->lock); | |
2442 | ||
2443 | mib_counters_clear(mp); | |
2444 | INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); | |
2445 | ||
bedfe324 LB |
2446 | if (mp->phy_addr != -1) { |
2447 | err = phy_init(mp, pd); | |
2448 | if (err) | |
2449 | goto out; | |
2450 | ||
2451 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); | |
2452 | } else { | |
2453 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless); | |
2454 | } | |
fc32b0e2 LB |
2455 | |
2456 | ||
c9df406f LB |
2457 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2458 | BUG_ON(!res); | |
2459 | dev->irq = res->start; | |
1da177e4 | 2460 | |
fc32b0e2 | 2461 | dev->hard_start_xmit = mv643xx_eth_xmit; |
c9df406f LB |
2462 | dev->open = mv643xx_eth_open; |
2463 | dev->stop = mv643xx_eth_stop; | |
c9df406f | 2464 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; |
fc32b0e2 LB |
2465 | dev->set_mac_address = mv643xx_eth_set_mac_address; |
2466 | dev->do_ioctl = mv643xx_eth_ioctl; | |
2467 | dev->change_mtu = mv643xx_eth_change_mtu; | |
c9df406f | 2468 | dev->tx_timeout = mv643xx_eth_tx_timeout; |
c9df406f | 2469 | #ifdef CONFIG_NET_POLL_CONTROLLER |
e5371493 | 2470 | dev->poll_controller = mv643xx_eth_netpoll; |
c9df406f | 2471 | #endif |
c9df406f LB |
2472 | dev->watchdog_timeo = 2 * HZ; |
2473 | dev->base_addr = 0; | |
1da177e4 | 2474 | |
e5371493 | 2475 | #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX |
b4de9051 | 2476 | /* |
c9df406f LB |
2477 | * Zero copy can only work if we use Discovery II memory. Else, we will |
2478 | * have to map the buffers to ISA memory which is only 16 MB | |
b4de9051 | 2479 | */ |
c9df406f | 2480 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
c9df406f | 2481 | #endif |
1da177e4 | 2482 | |
fc32b0e2 | 2483 | SET_NETDEV_DEV(dev, &pdev->dev); |
8f518703 | 2484 | |
c9df406f | 2485 | if (mp->shared->win_protect) |
fc32b0e2 | 2486 | wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); |
1da177e4 | 2487 | |
c9df406f LB |
2488 | err = register_netdev(dev); |
2489 | if (err) | |
2490 | goto out; | |
1da177e4 | 2491 | |
fc32b0e2 LB |
2492 | dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n", |
2493 | mp->port_num, print_mac(mac, dev->dev_addr)); | |
1da177e4 | 2494 | |
c9df406f | 2495 | if (dev->features & NETIF_F_SG) |
fc32b0e2 | 2496 | dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n"); |
1da177e4 | 2497 | |
c9df406f | 2498 | if (dev->features & NETIF_F_IP_CSUM) |
fc32b0e2 | 2499 | dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n"); |
1da177e4 | 2500 | |
e5371493 | 2501 | #ifdef MV643XX_ETH_NAPI |
fc32b0e2 | 2502 | dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n"); |
c9df406f | 2503 | #endif |
1da177e4 | 2504 | |
13d64285 | 2505 | if (mp->tx_desc_sram_size > 0) |
fc32b0e2 | 2506 | dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n"); |
1da177e4 | 2507 | |
c9df406f | 2508 | return 0; |
1da177e4 | 2509 | |
c9df406f LB |
2510 | out: |
2511 | free_netdev(dev); | |
1da177e4 | 2512 | |
c9df406f | 2513 | return err; |
1da177e4 LT |
2514 | } |
2515 | ||
c9df406f | 2516 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2517 | { |
fc32b0e2 | 2518 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
1da177e4 | 2519 | |
fc32b0e2 | 2520 | unregister_netdev(mp->dev); |
c9df406f | 2521 | flush_scheduled_work(); |
fc32b0e2 | 2522 | free_netdev(mp->dev); |
c9df406f | 2523 | |
c9df406f | 2524 | platform_set_drvdata(pdev, NULL); |
fc32b0e2 | 2525 | |
c9df406f | 2526 | return 0; |
1da177e4 LT |
2527 | } |
2528 | ||
c9df406f | 2529 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2530 | { |
fc32b0e2 | 2531 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
d0412d96 | 2532 | |
c9df406f | 2533 | /* Mask all interrupts on ethernet port */ |
fc32b0e2 LB |
2534 | wrl(mp, INT_MASK(mp->port_num), 0); |
2535 | rdl(mp, INT_MASK(mp->port_num)); | |
c9df406f | 2536 | |
fc32b0e2 LB |
2537 | if (netif_running(mp->dev)) |
2538 | port_reset(mp); | |
d0412d96 JC |
2539 | } |
2540 | ||
c9df406f | 2541 | static struct platform_driver mv643xx_eth_driver = { |
fc32b0e2 LB |
2542 | .probe = mv643xx_eth_probe, |
2543 | .remove = mv643xx_eth_remove, | |
2544 | .shutdown = mv643xx_eth_shutdown, | |
c9df406f | 2545 | .driver = { |
fc32b0e2 | 2546 | .name = MV643XX_ETH_NAME, |
c9df406f LB |
2547 | .owner = THIS_MODULE, |
2548 | }, | |
2549 | }; | |
2550 | ||
e5371493 | 2551 | static int __init mv643xx_eth_init_module(void) |
d0412d96 | 2552 | { |
c9df406f | 2553 | int rc; |
d0412d96 | 2554 | |
c9df406f LB |
2555 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
2556 | if (!rc) { | |
2557 | rc = platform_driver_register(&mv643xx_eth_driver); | |
2558 | if (rc) | |
2559 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
2560 | } | |
fc32b0e2 | 2561 | |
c9df406f | 2562 | return rc; |
d0412d96 | 2563 | } |
fc32b0e2 | 2564 | module_init(mv643xx_eth_init_module); |
d0412d96 | 2565 | |
e5371493 | 2566 | static void __exit mv643xx_eth_cleanup_module(void) |
d0412d96 | 2567 | { |
c9df406f LB |
2568 | platform_driver_unregister(&mv643xx_eth_driver); |
2569 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 | 2570 | } |
e5371493 | 2571 | module_exit(mv643xx_eth_cleanup_module); |
1da177e4 | 2572 | |
fc32b0e2 LB |
2573 | MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani " |
2574 | "and Dale Farnsworth"); | |
c9df406f | 2575 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
fc32b0e2 | 2576 | MODULE_LICENSE("GPL"); |
c9df406f | 2577 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |
fc32b0e2 | 2578 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |