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1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
c3efab8e | 41 | #include <linux/ip.h> |
1da177e4 LT |
42 | #include <linux/tcp.h> |
43 | #include <linux/udp.h> | |
44 | #include <linux/etherdevice.h> | |
1da177e4 LT |
45 | #include <linux/delay.h> |
46 | #include <linux/ethtool.h> | |
d052d1be | 47 | #include <linux/platform_device.h> |
fbd6a754 LB |
48 | #include <linux/module.h> |
49 | #include <linux/kernel.h> | |
50 | #include <linux/spinlock.h> | |
51 | #include <linux/workqueue.h> | |
ed94493f | 52 | #include <linux/phy.h> |
fbd6a754 | 53 | #include <linux/mv643xx_eth.h> |
10a9948d LB |
54 | #include <linux/io.h> |
55 | #include <linux/types.h> | |
eaf5d590 | 56 | #include <linux/inet_lro.h> |
1da177e4 | 57 | #include <asm/system.h> |
fbd6a754 | 58 | |
e5371493 | 59 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
042af53c | 60 | static char mv643xx_eth_driver_version[] = "1.4"; |
c9df406f | 61 | |
fbd6a754 | 62 | |
fbd6a754 LB |
63 | /* |
64 | * Registers shared between all ports. | |
65 | */ | |
3cb4667c LB |
66 | #define PHY_ADDR 0x0000 |
67 | #define SMI_REG 0x0004 | |
45c5d3bc LB |
68 | #define SMI_BUSY 0x10000000 |
69 | #define SMI_READ_VALID 0x08000000 | |
70 | #define SMI_OPCODE_READ 0x04000000 | |
71 | #define SMI_OPCODE_WRITE 0x00000000 | |
72 | #define ERR_INT_CAUSE 0x0080 | |
73 | #define ERR_INT_SMI_DONE 0x00000010 | |
74 | #define ERR_INT_MASK 0x0084 | |
3cb4667c LB |
75 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) |
76 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
77 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
78 | #define WINDOW_BAR_ENABLE 0x0290 | |
79 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
80 | |
81 | /* | |
37a6084f LB |
82 | * Main per-port registers. These live at offset 0x0400 for |
83 | * port #0, 0x0800 for port #1, and 0x0c00 for port #2. | |
fbd6a754 | 84 | */ |
37a6084f | 85 | #define PORT_CONFIG 0x0000 |
d9a073ea | 86 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
37a6084f LB |
87 | #define PORT_CONFIG_EXT 0x0004 |
88 | #define MAC_ADDR_LOW 0x0014 | |
89 | #define MAC_ADDR_HIGH 0x0018 | |
90 | #define SDMA_CONFIG 0x001c | |
becfad97 LB |
91 | #define TX_BURST_SIZE_16_64BIT 0x01000000 |
92 | #define TX_BURST_SIZE_4_64BIT 0x00800000 | |
93 | #define BLM_TX_NO_SWAP 0x00000020 | |
94 | #define BLM_RX_NO_SWAP 0x00000010 | |
95 | #define RX_BURST_SIZE_16_64BIT 0x00000008 | |
96 | #define RX_BURST_SIZE_4_64BIT 0x00000004 | |
37a6084f | 97 | #define PORT_SERIAL_CONTROL 0x003c |
becfad97 LB |
98 | #define SET_MII_SPEED_TO_100 0x01000000 |
99 | #define SET_GMII_SPEED_TO_1000 0x00800000 | |
100 | #define SET_FULL_DUPLEX_MODE 0x00200000 | |
101 | #define MAX_RX_PACKET_9700BYTE 0x000a0000 | |
102 | #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 | |
103 | #define DO_NOT_FORCE_LINK_FAIL 0x00000400 | |
104 | #define SERIAL_PORT_CONTROL_RESERVED 0x00000200 | |
105 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 | |
106 | #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 | |
107 | #define FORCE_LINK_PASS 0x00000002 | |
108 | #define SERIAL_PORT_ENABLE 0x00000001 | |
37a6084f | 109 | #define PORT_STATUS 0x0044 |
a2a41689 | 110 | #define TX_FIFO_EMPTY 0x00000400 |
ae9ae064 | 111 | #define TX_IN_PROGRESS 0x00000080 |
2f7eb47a LB |
112 | #define PORT_SPEED_MASK 0x00000030 |
113 | #define PORT_SPEED_1000 0x00000010 | |
114 | #define PORT_SPEED_100 0x00000020 | |
115 | #define PORT_SPEED_10 0x00000000 | |
116 | #define FLOW_CONTROL_ENABLED 0x00000008 | |
117 | #define FULL_DUPLEX 0x00000004 | |
81600eea | 118 | #define LINK_UP 0x00000002 |
37a6084f LB |
119 | #define TXQ_COMMAND 0x0048 |
120 | #define TXQ_FIX_PRIO_CONF 0x004c | |
121 | #define TX_BW_RATE 0x0050 | |
122 | #define TX_BW_MTU 0x0058 | |
123 | #define TX_BW_BURST 0x005c | |
124 | #define INT_CAUSE 0x0060 | |
226bb6b7 | 125 | #define INT_TX_END 0x07f80000 |
e0ca8410 | 126 | #define INT_TX_END_0 0x00080000 |
befefe21 | 127 | #define INT_RX 0x000003fc |
e0ca8410 | 128 | #define INT_RX_0 0x00000004 |
073a345c | 129 | #define INT_EXT 0x00000002 |
37a6084f | 130 | #define INT_CAUSE_EXT 0x0064 |
befefe21 LB |
131 | #define INT_EXT_LINK_PHY 0x00110000 |
132 | #define INT_EXT_TX 0x000000ff | |
37a6084f LB |
133 | #define INT_MASK 0x0068 |
134 | #define INT_MASK_EXT 0x006c | |
135 | #define TX_FIFO_URGENT_THRESHOLD 0x0074 | |
136 | #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc | |
137 | #define TX_BW_RATE_MOVED 0x00e0 | |
138 | #define TX_BW_MTU_MOVED 0x00e8 | |
139 | #define TX_BW_BURST_MOVED 0x00ec | |
140 | #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) | |
141 | #define RXQ_COMMAND 0x0280 | |
142 | #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) | |
143 | #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) | |
144 | #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) | |
145 | #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) | |
146 | ||
147 | /* | |
148 | * Misc per-port registers. | |
149 | */ | |
3cb4667c LB |
150 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) |
151 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
152 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
153 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 154 | |
2679a550 LB |
155 | |
156 | /* | |
becfad97 | 157 | * SDMA configuration register default value. |
2679a550 | 158 | */ |
fbd6a754 LB |
159 | #if defined(__BIG_ENDIAN) |
160 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
161 | (RX_BURST_SIZE_4_64BIT | \ |
162 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
163 | #elif defined(__LITTLE_ENDIAN) |
164 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
165 | (RX_BURST_SIZE_4_64BIT | \ |
166 | BLM_RX_NO_SWAP | \ | |
167 | BLM_TX_NO_SWAP | \ | |
168 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
169 | #else |
170 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
171 | #endif | |
172 | ||
2beff77b LB |
173 | |
174 | /* | |
becfad97 | 175 | * Misc definitions. |
2beff77b | 176 | */ |
becfad97 LB |
177 | #define DEFAULT_RX_QUEUE_SIZE 128 |
178 | #define DEFAULT_TX_QUEUE_SIZE 256 | |
7fd96ce4 | 179 | #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) |
fbd6a754 | 180 | |
fbd6a754 | 181 | |
7ca72a3b LB |
182 | /* |
183 | * RX/TX descriptors. | |
fbd6a754 LB |
184 | */ |
185 | #if defined(__BIG_ENDIAN) | |
cc9754b3 | 186 | struct rx_desc { |
fbd6a754 LB |
187 | u16 byte_cnt; /* Descriptor buffer byte count */ |
188 | u16 buf_size; /* Buffer size */ | |
189 | u32 cmd_sts; /* Descriptor command status */ | |
190 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
191 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
192 | }; | |
193 | ||
cc9754b3 | 194 | struct tx_desc { |
fbd6a754 LB |
195 | u16 byte_cnt; /* buffer byte count */ |
196 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
197 | u32 cmd_sts; /* Command/status field */ | |
198 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
199 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
200 | }; | |
201 | #elif defined(__LITTLE_ENDIAN) | |
cc9754b3 | 202 | struct rx_desc { |
fbd6a754 LB |
203 | u32 cmd_sts; /* Descriptor command status */ |
204 | u16 buf_size; /* Buffer size */ | |
205 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
206 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
207 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
208 | }; | |
209 | ||
cc9754b3 | 210 | struct tx_desc { |
fbd6a754 LB |
211 | u32 cmd_sts; /* Command/status field */ |
212 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
213 | u16 byte_cnt; /* buffer byte count */ | |
214 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
215 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
216 | }; | |
217 | #else | |
218 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
219 | #endif | |
220 | ||
7ca72a3b | 221 | /* RX & TX descriptor command */ |
cc9754b3 | 222 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
7ca72a3b LB |
223 | |
224 | /* RX & TX descriptor status */ | |
cc9754b3 | 225 | #define ERROR_SUMMARY 0x00000001 |
7ca72a3b LB |
226 | |
227 | /* RX descriptor status */ | |
cc9754b3 LB |
228 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
229 | #define RX_ENABLE_INTERRUPT 0x20000000 | |
230 | #define RX_FIRST_DESC 0x08000000 | |
231 | #define RX_LAST_DESC 0x04000000 | |
eaf5d590 LB |
232 | #define RX_IP_HDR_OK 0x02000000 |
233 | #define RX_PKT_IS_IPV4 0x01000000 | |
234 | #define RX_PKT_IS_ETHERNETV2 0x00800000 | |
235 | #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 | |
236 | #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 | |
237 | #define RX_PKT_IS_VLAN_TAGGED 0x00080000 | |
7ca72a3b LB |
238 | |
239 | /* TX descriptor command */ | |
cc9754b3 LB |
240 | #define TX_ENABLE_INTERRUPT 0x00800000 |
241 | #define GEN_CRC 0x00400000 | |
242 | #define TX_FIRST_DESC 0x00200000 | |
243 | #define TX_LAST_DESC 0x00100000 | |
244 | #define ZERO_PADDING 0x00080000 | |
245 | #define GEN_IP_V4_CHECKSUM 0x00040000 | |
246 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 | |
247 | #define UDP_FRAME 0x00010000 | |
e32b6617 LB |
248 | #define MAC_HDR_EXTRA_4_BYTES 0x00008000 |
249 | #define MAC_HDR_EXTRA_8_BYTES 0x00000200 | |
7ca72a3b | 250 | |
cc9754b3 | 251 | #define TX_IHL_SHIFT 11 |
7ca72a3b LB |
252 | |
253 | ||
c9df406f | 254 | /* global *******************************************************************/ |
e5371493 | 255 | struct mv643xx_eth_shared_private { |
fc32b0e2 LB |
256 | /* |
257 | * Ethernet controller base address. | |
258 | */ | |
cc9754b3 | 259 | void __iomem *base; |
c9df406f | 260 | |
fc0eb9f2 LB |
261 | /* |
262 | * Points at the right SMI instance to use. | |
263 | */ | |
264 | struct mv643xx_eth_shared_private *smi; | |
265 | ||
fc32b0e2 | 266 | /* |
ed94493f | 267 | * Provides access to local SMI interface. |
fc32b0e2 | 268 | */ |
298cf9be | 269 | struct mii_bus *smi_bus; |
c9df406f | 270 | |
45c5d3bc LB |
271 | /* |
272 | * If we have access to the error interrupt pin (which is | |
273 | * somewhat misnamed as it not only reflects internal errors | |
274 | * but also reflects SMI completion), use that to wait for | |
275 | * SMI access completion instead of polling the SMI busy bit. | |
276 | */ | |
277 | int err_interrupt; | |
278 | wait_queue_head_t smi_busy_wait; | |
279 | ||
fc32b0e2 LB |
280 | /* |
281 | * Per-port MBUS window access register value. | |
282 | */ | |
c9df406f LB |
283 | u32 win_protect; |
284 | ||
fc32b0e2 LB |
285 | /* |
286 | * Hardware-specific parameters. | |
287 | */ | |
c9df406f | 288 | unsigned int t_clk; |
773fc3ee | 289 | int extended_rx_coal_limit; |
457b1d5a | 290 | int tx_bw_control; |
c9df406f LB |
291 | }; |
292 | ||
457b1d5a LB |
293 | #define TX_BW_CONTROL_ABSENT 0 |
294 | #define TX_BW_CONTROL_OLD_LAYOUT 1 | |
295 | #define TX_BW_CONTROL_NEW_LAYOUT 2 | |
296 | ||
e7d2f4db LB |
297 | static int mv643xx_eth_open(struct net_device *dev); |
298 | static int mv643xx_eth_stop(struct net_device *dev); | |
299 | ||
c9df406f LB |
300 | |
301 | /* per-port *****************************************************************/ | |
e5371493 | 302 | struct mib_counters { |
fbd6a754 LB |
303 | u64 good_octets_received; |
304 | u32 bad_octets_received; | |
305 | u32 internal_mac_transmit_err; | |
306 | u32 good_frames_received; | |
307 | u32 bad_frames_received; | |
308 | u32 broadcast_frames_received; | |
309 | u32 multicast_frames_received; | |
310 | u32 frames_64_octets; | |
311 | u32 frames_65_to_127_octets; | |
312 | u32 frames_128_to_255_octets; | |
313 | u32 frames_256_to_511_octets; | |
314 | u32 frames_512_to_1023_octets; | |
315 | u32 frames_1024_to_max_octets; | |
316 | u64 good_octets_sent; | |
317 | u32 good_frames_sent; | |
318 | u32 excessive_collision; | |
319 | u32 multicast_frames_sent; | |
320 | u32 broadcast_frames_sent; | |
321 | u32 unrec_mac_control_received; | |
322 | u32 fc_sent; | |
323 | u32 good_fc_received; | |
324 | u32 bad_fc_received; | |
325 | u32 undersize_received; | |
326 | u32 fragments_received; | |
327 | u32 oversize_received; | |
328 | u32 jabber_received; | |
329 | u32 mac_receive_error; | |
330 | u32 bad_crc_event; | |
331 | u32 collision; | |
332 | u32 late_collision; | |
333 | }; | |
334 | ||
eaf5d590 LB |
335 | struct lro_counters { |
336 | u32 lro_aggregated; | |
337 | u32 lro_flushed; | |
338 | u32 lro_no_desc; | |
339 | }; | |
340 | ||
8a578111 | 341 | struct rx_queue { |
64da80a2 LB |
342 | int index; |
343 | ||
8a578111 LB |
344 | int rx_ring_size; |
345 | ||
346 | int rx_desc_count; | |
347 | int rx_curr_desc; | |
348 | int rx_used_desc; | |
349 | ||
350 | struct rx_desc *rx_desc_area; | |
351 | dma_addr_t rx_desc_dma; | |
352 | int rx_desc_area_size; | |
353 | struct sk_buff **rx_skb; | |
eaf5d590 | 354 | |
eaf5d590 LB |
355 | struct net_lro_mgr lro_mgr; |
356 | struct net_lro_desc lro_arr[8]; | |
8a578111 LB |
357 | }; |
358 | ||
13d64285 | 359 | struct tx_queue { |
3d6b35bc LB |
360 | int index; |
361 | ||
13d64285 | 362 | int tx_ring_size; |
fbd6a754 | 363 | |
13d64285 LB |
364 | int tx_desc_count; |
365 | int tx_curr_desc; | |
366 | int tx_used_desc; | |
fbd6a754 | 367 | |
5daffe94 | 368 | struct tx_desc *tx_desc_area; |
fbd6a754 LB |
369 | dma_addr_t tx_desc_dma; |
370 | int tx_desc_area_size; | |
99ab08e0 LB |
371 | |
372 | struct sk_buff_head tx_skb; | |
8fd89211 LB |
373 | |
374 | unsigned long tx_packets; | |
375 | unsigned long tx_bytes; | |
376 | unsigned long tx_dropped; | |
13d64285 LB |
377 | }; |
378 | ||
379 | struct mv643xx_eth_private { | |
380 | struct mv643xx_eth_shared_private *shared; | |
37a6084f | 381 | void __iomem *base; |
fc32b0e2 | 382 | int port_num; |
13d64285 | 383 | |
fc32b0e2 | 384 | struct net_device *dev; |
fbd6a754 | 385 | |
ed94493f | 386 | struct phy_device *phy; |
fbd6a754 | 387 | |
4ff3495a LB |
388 | struct timer_list mib_counters_timer; |
389 | spinlock_t mib_counters_lock; | |
fc32b0e2 | 390 | struct mib_counters mib_counters; |
4ff3495a | 391 | |
eaf5d590 LB |
392 | struct lro_counters lro_counters; |
393 | ||
fc32b0e2 | 394 | struct work_struct tx_timeout_task; |
8a578111 | 395 | |
1fa38c58 | 396 | struct napi_struct napi; |
e0ca8410 | 397 | u32 int_mask; |
1319ebad | 398 | u8 oom; |
1fa38c58 LB |
399 | u8 work_link; |
400 | u8 work_tx; | |
401 | u8 work_tx_end; | |
402 | u8 work_rx; | |
403 | u8 work_rx_refill; | |
1fa38c58 | 404 | |
2bcb4b0f LB |
405 | int skb_size; |
406 | struct sk_buff_head rx_recycle; | |
407 | ||
8a578111 LB |
408 | /* |
409 | * RX state. | |
410 | */ | |
e7d2f4db | 411 | int rx_ring_size; |
8a578111 LB |
412 | unsigned long rx_desc_sram_addr; |
413 | int rx_desc_sram_size; | |
f7981c1c | 414 | int rxq_count; |
2257e05c | 415 | struct timer_list rx_oom; |
64da80a2 | 416 | struct rx_queue rxq[8]; |
13d64285 LB |
417 | |
418 | /* | |
419 | * TX state. | |
420 | */ | |
e7d2f4db | 421 | int tx_ring_size; |
13d64285 LB |
422 | unsigned long tx_desc_sram_addr; |
423 | int tx_desc_sram_size; | |
f7981c1c | 424 | int txq_count; |
3d6b35bc | 425 | struct tx_queue txq[8]; |
fbd6a754 | 426 | }; |
1da177e4 | 427 | |
fbd6a754 | 428 | |
c9df406f | 429 | /* port register accessors **************************************************/ |
e5371493 | 430 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 431 | { |
cc9754b3 | 432 | return readl(mp->shared->base + offset); |
c9df406f | 433 | } |
fbd6a754 | 434 | |
37a6084f LB |
435 | static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) |
436 | { | |
437 | return readl(mp->base + offset); | |
438 | } | |
439 | ||
e5371493 | 440 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
c9df406f | 441 | { |
cc9754b3 | 442 | writel(data, mp->shared->base + offset); |
c9df406f | 443 | } |
fbd6a754 | 444 | |
37a6084f LB |
445 | static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) |
446 | { | |
447 | writel(data, mp->base + offset); | |
448 | } | |
449 | ||
fbd6a754 | 450 | |
c9df406f | 451 | /* rxq/txq helper functions *************************************************/ |
8a578111 | 452 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
c9df406f | 453 | { |
64da80a2 | 454 | return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); |
c9df406f | 455 | } |
fbd6a754 | 456 | |
13d64285 LB |
457 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
458 | { | |
3d6b35bc | 459 | return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); |
13d64285 LB |
460 | } |
461 | ||
8a578111 | 462 | static void rxq_enable(struct rx_queue *rxq) |
c9df406f | 463 | { |
8a578111 | 464 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
37a6084f | 465 | wrlp(mp, RXQ_COMMAND, 1 << rxq->index); |
8a578111 | 466 | } |
1da177e4 | 467 | |
8a578111 LB |
468 | static void rxq_disable(struct rx_queue *rxq) |
469 | { | |
470 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); | |
64da80a2 | 471 | u8 mask = 1 << rxq->index; |
1da177e4 | 472 | |
37a6084f LB |
473 | wrlp(mp, RXQ_COMMAND, mask << 8); |
474 | while (rdlp(mp, RXQ_COMMAND) & mask) | |
8a578111 | 475 | udelay(10); |
c9df406f LB |
476 | } |
477 | ||
6b368f68 LB |
478 | static void txq_reset_hw_ptr(struct tx_queue *txq) |
479 | { | |
480 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
6b368f68 LB |
481 | u32 addr; |
482 | ||
483 | addr = (u32)txq->tx_desc_dma; | |
484 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); | |
37a6084f | 485 | wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); |
6b368f68 LB |
486 | } |
487 | ||
13d64285 | 488 | static void txq_enable(struct tx_queue *txq) |
1da177e4 | 489 | { |
13d64285 | 490 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
37a6084f | 491 | wrlp(mp, TXQ_COMMAND, 1 << txq->index); |
1da177e4 LT |
492 | } |
493 | ||
13d64285 | 494 | static void txq_disable(struct tx_queue *txq) |
1da177e4 | 495 | { |
13d64285 | 496 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 497 | u8 mask = 1 << txq->index; |
c9df406f | 498 | |
37a6084f LB |
499 | wrlp(mp, TXQ_COMMAND, mask << 8); |
500 | while (rdlp(mp, TXQ_COMMAND) & mask) | |
13d64285 LB |
501 | udelay(10); |
502 | } | |
503 | ||
1fa38c58 | 504 | static void txq_maybe_wake(struct tx_queue *txq) |
13d64285 LB |
505 | { |
506 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
e5ef1de1 | 507 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
3d6b35bc | 508 | |
8fd89211 LB |
509 | if (netif_tx_queue_stopped(nq)) { |
510 | __netif_tx_lock(nq, smp_processor_id()); | |
511 | if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1) | |
512 | netif_tx_wake_queue(nq); | |
513 | __netif_tx_unlock(nq); | |
514 | } | |
1da177e4 LT |
515 | } |
516 | ||
c9df406f | 517 | |
1fa38c58 | 518 | /* rx napi ******************************************************************/ |
eaf5d590 LB |
519 | static int |
520 | mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph, | |
521 | u64 *hdr_flags, void *priv) | |
522 | { | |
523 | unsigned long cmd_sts = (unsigned long)priv; | |
524 | ||
525 | /* | |
526 | * Make sure that this packet is Ethernet II, is not VLAN | |
527 | * tagged, is IPv4, has a valid IP header, and is TCP. | |
528 | */ | |
529 | if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | | |
530 | RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK | | |
531 | RX_PKT_IS_VLAN_TAGGED)) != | |
532 | (RX_IP_HDR_OK | RX_PKT_IS_IPV4 | | |
533 | RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4)) | |
534 | return -1; | |
535 | ||
536 | skb_reset_network_header(skb); | |
537 | skb_set_transport_header(skb, ip_hdrlen(skb)); | |
538 | *iphdr = ip_hdr(skb); | |
539 | *tcph = tcp_hdr(skb); | |
540 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
541 | ||
542 | return 0; | |
543 | } | |
eaf5d590 | 544 | |
8a578111 | 545 | static int rxq_process(struct rx_queue *rxq, int budget) |
1da177e4 | 546 | { |
8a578111 LB |
547 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
548 | struct net_device_stats *stats = &mp->dev->stats; | |
eaf5d590 | 549 | int lro_flush_needed; |
8a578111 | 550 | int rx; |
1da177e4 | 551 | |
eaf5d590 | 552 | lro_flush_needed = 0; |
8a578111 | 553 | rx = 0; |
9e1f3772 | 554 | while (rx < budget && rxq->rx_desc_count) { |
fc32b0e2 | 555 | struct rx_desc *rx_desc; |
96587661 | 556 | unsigned int cmd_sts; |
fc32b0e2 | 557 | struct sk_buff *skb; |
6b8f90c2 | 558 | u16 byte_cnt; |
ff561eef | 559 | |
8a578111 | 560 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
1da177e4 | 561 | |
96587661 | 562 | cmd_sts = rx_desc->cmd_sts; |
2257e05c | 563 | if (cmd_sts & BUFFER_OWNED_BY_DMA) |
96587661 | 564 | break; |
96587661 | 565 | rmb(); |
1da177e4 | 566 | |
8a578111 LB |
567 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
568 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; | |
ff561eef | 569 | |
9da78745 LB |
570 | rxq->rx_curr_desc++; |
571 | if (rxq->rx_curr_desc == rxq->rx_ring_size) | |
572 | rxq->rx_curr_desc = 0; | |
ff561eef | 573 | |
eb0519b5 | 574 | dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, |
abe78717 | 575 | rx_desc->buf_size, DMA_FROM_DEVICE); |
8a578111 LB |
576 | rxq->rx_desc_count--; |
577 | rx++; | |
b1dd9ca1 | 578 | |
1fa38c58 LB |
579 | mp->work_rx_refill |= 1 << rxq->index; |
580 | ||
6b8f90c2 LB |
581 | byte_cnt = rx_desc->byte_cnt; |
582 | ||
468d09f8 DF |
583 | /* |
584 | * Update statistics. | |
fc32b0e2 LB |
585 | * |
586 | * Note that the descriptor byte count includes 2 dummy | |
587 | * bytes automatically inserted by the hardware at the | |
588 | * start of the packet (which we don't count), and a 4 | |
589 | * byte CRC at the end of the packet (which we do count). | |
468d09f8 | 590 | */ |
1da177e4 | 591 | stats->rx_packets++; |
6b8f90c2 | 592 | stats->rx_bytes += byte_cnt - 2; |
96587661 | 593 | |
1da177e4 | 594 | /* |
fc32b0e2 LB |
595 | * In case we received a packet without first / last bits |
596 | * on, or the error summary bit is set, the packet needs | |
597 | * to be dropped. | |
1da177e4 | 598 | */ |
f61e5547 LB |
599 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) |
600 | != (RX_FIRST_DESC | RX_LAST_DESC)) | |
601 | goto err; | |
602 | ||
603 | /* | |
604 | * The -4 is for the CRC in the trailer of the | |
605 | * received packet | |
606 | */ | |
607 | skb_put(skb, byte_cnt - 2 - 4); | |
608 | ||
609 | if (cmd_sts & LAYER_4_CHECKSUM_OK) | |
610 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
611 | skb->protocol = eth_type_trans(skb, mp->dev); | |
eaf5d590 | 612 | |
eaf5d590 LB |
613 | if (skb->dev->features & NETIF_F_LRO && |
614 | skb->ip_summed == CHECKSUM_UNNECESSARY) { | |
615 | lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts); | |
616 | lro_flush_needed = 1; | |
617 | } else | |
eaf5d590 | 618 | netif_receive_skb(skb); |
f61e5547 LB |
619 | |
620 | continue; | |
621 | ||
622 | err: | |
623 | stats->rx_dropped++; | |
624 | ||
625 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != | |
626 | (RX_FIRST_DESC | RX_LAST_DESC)) { | |
627 | if (net_ratelimit()) | |
628 | dev_printk(KERN_ERR, &mp->dev->dev, | |
629 | "received packet spanning " | |
630 | "multiple descriptors\n"); | |
1da177e4 | 631 | } |
f61e5547 LB |
632 | |
633 | if (cmd_sts & ERROR_SUMMARY) | |
634 | stats->rx_errors++; | |
635 | ||
636 | dev_kfree_skb(skb); | |
1da177e4 | 637 | } |
fc32b0e2 | 638 | |
eaf5d590 LB |
639 | if (lro_flush_needed) |
640 | lro_flush_all(&rxq->lro_mgr); | |
eaf5d590 | 641 | |
1fa38c58 LB |
642 | if (rx < budget) |
643 | mp->work_rx &= ~(1 << rxq->index); | |
644 | ||
8a578111 | 645 | return rx; |
1da177e4 LT |
646 | } |
647 | ||
1fa38c58 | 648 | static int rxq_refill(struct rx_queue *rxq, int budget) |
d0412d96 | 649 | { |
1fa38c58 | 650 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1fa38c58 | 651 | int refilled; |
8a578111 | 652 | |
1fa38c58 LB |
653 | refilled = 0; |
654 | while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { | |
655 | struct sk_buff *skb; | |
1fa38c58 | 656 | int rx; |
53771522 | 657 | struct rx_desc *rx_desc; |
530e557a | 658 | int size; |
d0412d96 | 659 | |
2bcb4b0f LB |
660 | skb = __skb_dequeue(&mp->rx_recycle); |
661 | if (skb == NULL) | |
7fd96ce4 | 662 | skb = dev_alloc_skb(mp->skb_size); |
2bcb4b0f | 663 | |
1fa38c58 | 664 | if (skb == NULL) { |
1319ebad | 665 | mp->oom = 1; |
1fa38c58 LB |
666 | goto oom; |
667 | } | |
d0412d96 | 668 | |
7fd96ce4 LB |
669 | if (SKB_DMA_REALIGN) |
670 | skb_reserve(skb, SKB_DMA_REALIGN); | |
2257e05c | 671 | |
1fa38c58 LB |
672 | refilled++; |
673 | rxq->rx_desc_count++; | |
c9df406f | 674 | |
1fa38c58 LB |
675 | rx = rxq->rx_used_desc++; |
676 | if (rxq->rx_used_desc == rxq->rx_ring_size) | |
677 | rxq->rx_used_desc = 0; | |
2257e05c | 678 | |
53771522 LB |
679 | rx_desc = rxq->rx_desc_area + rx; |
680 | ||
530e557a | 681 | size = skb->end - skb->data; |
eb0519b5 | 682 | rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, |
530e557a | 683 | skb->data, size, |
eb0519b5 | 684 | DMA_FROM_DEVICE); |
530e557a | 685 | rx_desc->buf_size = size; |
1fa38c58 LB |
686 | rxq->rx_skb[rx] = skb; |
687 | wmb(); | |
53771522 | 688 | rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; |
1fa38c58 | 689 | wmb(); |
2257e05c | 690 | |
1fa38c58 LB |
691 | /* |
692 | * The hardware automatically prepends 2 bytes of | |
693 | * dummy data to each received packet, so that the | |
694 | * IP header ends up 16-byte aligned. | |
695 | */ | |
696 | skb_reserve(skb, 2); | |
697 | } | |
698 | ||
699 | if (refilled < budget) | |
700 | mp->work_rx_refill &= ~(1 << rxq->index); | |
701 | ||
702 | oom: | |
703 | return refilled; | |
d0412d96 JC |
704 | } |
705 | ||
c9df406f LB |
706 | |
707 | /* tx ***********************************************************************/ | |
c9df406f | 708 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 709 | { |
13d64285 | 710 | int frag; |
1da177e4 | 711 | |
c9df406f | 712 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
13d64285 LB |
713 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
714 | if (fragp->size <= 8 && fragp->page_offset & 7) | |
c9df406f | 715 | return 1; |
1da177e4 | 716 | } |
13d64285 | 717 | |
c9df406f LB |
718 | return 0; |
719 | } | |
7303fde8 | 720 | |
13d64285 | 721 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
c9df406f | 722 | { |
eb0519b5 | 723 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 724 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 725 | int frag; |
1da177e4 | 726 | |
13d64285 LB |
727 | for (frag = 0; frag < nr_frags; frag++) { |
728 | skb_frag_t *this_frag; | |
729 | int tx_index; | |
730 | struct tx_desc *desc; | |
731 | ||
732 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
66823b92 LB |
733 | tx_index = txq->tx_curr_desc++; |
734 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
735 | txq->tx_curr_desc = 0; | |
13d64285 LB |
736 | desc = &txq->tx_desc_area[tx_index]; |
737 | ||
738 | /* | |
739 | * The last fragment will generate an interrupt | |
740 | * which will free the skb on TX completion. | |
741 | */ | |
742 | if (frag == nr_frags - 1) { | |
743 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | | |
744 | ZERO_PADDING | TX_LAST_DESC | | |
745 | TX_ENABLE_INTERRUPT; | |
13d64285 LB |
746 | } else { |
747 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; | |
13d64285 LB |
748 | } |
749 | ||
c9df406f LB |
750 | desc->l4i_chk = 0; |
751 | desc->byte_cnt = this_frag->size; | |
eb0519b5 GP |
752 | desc->buf_ptr = dma_map_page(mp->dev->dev.parent, |
753 | this_frag->page, | |
754 | this_frag->page_offset, | |
755 | this_frag->size, DMA_TO_DEVICE); | |
c9df406f | 756 | } |
1da177e4 LT |
757 | } |
758 | ||
c9df406f LB |
759 | static inline __be16 sum16_as_be(__sum16 sum) |
760 | { | |
761 | return (__force __be16)sum; | |
762 | } | |
1da177e4 | 763 | |
4df89bd5 | 764 | static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) |
1da177e4 | 765 | { |
8fa89bf5 | 766 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 767 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 768 | int tx_index; |
cc9754b3 | 769 | struct tx_desc *desc; |
c9df406f | 770 | u32 cmd_sts; |
4df89bd5 | 771 | u16 l4i_chk; |
c9df406f | 772 | int length; |
1da177e4 | 773 | |
cc9754b3 | 774 | cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
4df89bd5 | 775 | l4i_chk = 0; |
c9df406f LB |
776 | |
777 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
4df89bd5 | 778 | int tag_bytes; |
e32b6617 LB |
779 | |
780 | BUG_ON(skb->protocol != htons(ETH_P_IP) && | |
781 | skb->protocol != htons(ETH_P_8021Q)); | |
c9df406f | 782 | |
4df89bd5 LB |
783 | tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN; |
784 | if (unlikely(tag_bytes & ~12)) { | |
785 | if (skb_checksum_help(skb) == 0) | |
786 | goto no_csum; | |
787 | kfree_skb(skb); | |
788 | return 1; | |
789 | } | |
c9df406f | 790 | |
4df89bd5 | 791 | if (tag_bytes & 4) |
e32b6617 | 792 | cmd_sts |= MAC_HDR_EXTRA_4_BYTES; |
4df89bd5 | 793 | if (tag_bytes & 8) |
e32b6617 | 794 | cmd_sts |= MAC_HDR_EXTRA_8_BYTES; |
4df89bd5 LB |
795 | |
796 | cmd_sts |= GEN_TCP_UDP_CHECKSUM | | |
797 | GEN_IP_V4_CHECKSUM | | |
798 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; | |
e32b6617 | 799 | |
c9df406f LB |
800 | switch (ip_hdr(skb)->protocol) { |
801 | case IPPROTO_UDP: | |
cc9754b3 | 802 | cmd_sts |= UDP_FRAME; |
4df89bd5 | 803 | l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
c9df406f LB |
804 | break; |
805 | case IPPROTO_TCP: | |
4df89bd5 | 806 | l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); |
c9df406f LB |
807 | break; |
808 | default: | |
809 | BUG(); | |
810 | } | |
811 | } else { | |
4df89bd5 | 812 | no_csum: |
c9df406f | 813 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
cc9754b3 | 814 | cmd_sts |= 5 << TX_IHL_SHIFT; |
c9df406f LB |
815 | } |
816 | ||
66823b92 LB |
817 | tx_index = txq->tx_curr_desc++; |
818 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
819 | txq->tx_curr_desc = 0; | |
4df89bd5 LB |
820 | desc = &txq->tx_desc_area[tx_index]; |
821 | ||
822 | if (nr_frags) { | |
823 | txq_submit_frag_skb(txq, skb); | |
824 | length = skb_headlen(skb); | |
825 | } else { | |
826 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; | |
827 | length = skb->len; | |
828 | } | |
829 | ||
830 | desc->l4i_chk = l4i_chk; | |
831 | desc->byte_cnt = length; | |
eb0519b5 GP |
832 | desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, |
833 | length, DMA_TO_DEVICE); | |
4df89bd5 | 834 | |
99ab08e0 LB |
835 | __skb_queue_tail(&txq->tx_skb, skb); |
836 | ||
c9df406f LB |
837 | /* ensure all other descriptors are written before first cmd_sts */ |
838 | wmb(); | |
839 | desc->cmd_sts = cmd_sts; | |
840 | ||
1fa38c58 LB |
841 | /* clear TX_END status */ |
842 | mp->work_tx_end &= ~(1 << txq->index); | |
8fa89bf5 | 843 | |
c9df406f LB |
844 | /* ensure all descriptors are written before poking hardware */ |
845 | wmb(); | |
13d64285 | 846 | txq_enable(txq); |
c9df406f | 847 | |
13d64285 | 848 | txq->tx_desc_count += nr_frags + 1; |
4df89bd5 LB |
849 | |
850 | return 0; | |
1da177e4 | 851 | } |
1da177e4 | 852 | |
0ccfe64d | 853 | static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 854 | { |
e5371493 | 855 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
e5ef1de1 | 856 | int queue; |
13d64285 | 857 | struct tx_queue *txq; |
e5ef1de1 | 858 | struct netdev_queue *nq; |
afdb57a2 | 859 | |
8fd89211 LB |
860 | queue = skb_get_queue_mapping(skb); |
861 | txq = mp->txq + queue; | |
862 | nq = netdev_get_tx_queue(dev, queue); | |
863 | ||
c9df406f | 864 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
8fd89211 | 865 | txq->tx_dropped++; |
fc32b0e2 LB |
866 | dev_printk(KERN_DEBUG, &dev->dev, |
867 | "failed to linearize skb with tiny " | |
868 | "unaligned fragment\n"); | |
c9df406f LB |
869 | return NETDEV_TX_BUSY; |
870 | } | |
871 | ||
17cd0a59 | 872 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { |
e5ef1de1 LB |
873 | if (net_ratelimit()) |
874 | dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n"); | |
3d6b35bc LB |
875 | kfree_skb(skb); |
876 | return NETDEV_TX_OK; | |
c9df406f LB |
877 | } |
878 | ||
4df89bd5 LB |
879 | if (!txq_submit_skb(txq, skb)) { |
880 | int entries_left; | |
881 | ||
882 | txq->tx_bytes += skb->len; | |
883 | txq->tx_packets++; | |
884 | dev->trans_start = jiffies; | |
c9df406f | 885 | |
4df89bd5 LB |
886 | entries_left = txq->tx_ring_size - txq->tx_desc_count; |
887 | if (entries_left < MAX_SKB_FRAGS + 1) | |
888 | netif_tx_stop_queue(nq); | |
889 | } | |
c9df406f | 890 | |
c9df406f | 891 | return NETDEV_TX_OK; |
1da177e4 LT |
892 | } |
893 | ||
c9df406f | 894 | |
1fa38c58 LB |
895 | /* tx napi ******************************************************************/ |
896 | static void txq_kick(struct tx_queue *txq) | |
897 | { | |
898 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 899 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
900 | u32 hw_desc_ptr; |
901 | u32 expected_ptr; | |
902 | ||
8fd89211 | 903 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 | 904 | |
37a6084f | 905 | if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) |
1fa38c58 LB |
906 | goto out; |
907 | ||
37a6084f | 908 | hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); |
1fa38c58 LB |
909 | expected_ptr = (u32)txq->tx_desc_dma + |
910 | txq->tx_curr_desc * sizeof(struct tx_desc); | |
911 | ||
912 | if (hw_desc_ptr != expected_ptr) | |
913 | txq_enable(txq); | |
914 | ||
915 | out: | |
8fd89211 | 916 | __netif_tx_unlock(nq); |
1fa38c58 LB |
917 | |
918 | mp->work_tx_end &= ~(1 << txq->index); | |
919 | } | |
920 | ||
921 | static int txq_reclaim(struct tx_queue *txq, int budget, int force) | |
922 | { | |
923 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 924 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
925 | int reclaimed; |
926 | ||
8fd89211 | 927 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 LB |
928 | |
929 | reclaimed = 0; | |
930 | while (reclaimed < budget && txq->tx_desc_count > 0) { | |
931 | int tx_index; | |
932 | struct tx_desc *desc; | |
933 | u32 cmd_sts; | |
934 | struct sk_buff *skb; | |
1fa38c58 LB |
935 | |
936 | tx_index = txq->tx_used_desc; | |
937 | desc = &txq->tx_desc_area[tx_index]; | |
938 | cmd_sts = desc->cmd_sts; | |
939 | ||
940 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { | |
941 | if (!force) | |
942 | break; | |
943 | desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; | |
944 | } | |
945 | ||
946 | txq->tx_used_desc = tx_index + 1; | |
947 | if (txq->tx_used_desc == txq->tx_ring_size) | |
948 | txq->tx_used_desc = 0; | |
949 | ||
950 | reclaimed++; | |
951 | txq->tx_desc_count--; | |
952 | ||
99ab08e0 LB |
953 | skb = NULL; |
954 | if (cmd_sts & TX_LAST_DESC) | |
955 | skb = __skb_dequeue(&txq->tx_skb); | |
1fa38c58 LB |
956 | |
957 | if (cmd_sts & ERROR_SUMMARY) { | |
958 | dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); | |
959 | mp->dev->stats.tx_errors++; | |
960 | } | |
961 | ||
a418950c | 962 | if (cmd_sts & TX_FIRST_DESC) { |
eb0519b5 | 963 | dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr, |
a418950c LB |
964 | desc->byte_cnt, DMA_TO_DEVICE); |
965 | } else { | |
eb0519b5 | 966 | dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr, |
a418950c LB |
967 | desc->byte_cnt, DMA_TO_DEVICE); |
968 | } | |
1fa38c58 | 969 | |
2bcb4b0f LB |
970 | if (skb != NULL) { |
971 | if (skb_queue_len(&mp->rx_recycle) < | |
e7d2f4db | 972 | mp->rx_ring_size && |
7fd96ce4 | 973 | skb_recycle_check(skb, mp->skb_size)) |
2bcb4b0f LB |
974 | __skb_queue_head(&mp->rx_recycle, skb); |
975 | else | |
976 | dev_kfree_skb(skb); | |
977 | } | |
1fa38c58 LB |
978 | } |
979 | ||
8fd89211 LB |
980 | __netif_tx_unlock(nq); |
981 | ||
1fa38c58 LB |
982 | if (reclaimed < budget) |
983 | mp->work_tx &= ~(1 << txq->index); | |
984 | ||
1fa38c58 LB |
985 | return reclaimed; |
986 | } | |
987 | ||
988 | ||
89df5fdc LB |
989 | /* tx rate control **********************************************************/ |
990 | /* | |
991 | * Set total maximum TX rate (shared by all TX queues for this port) | |
992 | * to 'rate' bits per second, with a maximum burst of 'burst' bytes. | |
993 | */ | |
994 | static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) | |
995 | { | |
996 | int token_rate; | |
997 | int mtu; | |
998 | int bucket_size; | |
999 | ||
1000 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
1001 | if (token_rate > 1023) | |
1002 | token_rate = 1023; | |
1003 | ||
1004 | mtu = (mp->dev->mtu + 255) >> 8; | |
1005 | if (mtu > 63) | |
1006 | mtu = 63; | |
1007 | ||
1008 | bucket_size = (burst + 255) >> 8; | |
1009 | if (bucket_size > 65535) | |
1010 | bucket_size = 65535; | |
1011 | ||
457b1d5a LB |
1012 | switch (mp->shared->tx_bw_control) { |
1013 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f LB |
1014 | wrlp(mp, TX_BW_RATE, token_rate); |
1015 | wrlp(mp, TX_BW_MTU, mtu); | |
1016 | wrlp(mp, TX_BW_BURST, bucket_size); | |
457b1d5a LB |
1017 | break; |
1018 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f LB |
1019 | wrlp(mp, TX_BW_RATE_MOVED, token_rate); |
1020 | wrlp(mp, TX_BW_MTU_MOVED, mtu); | |
1021 | wrlp(mp, TX_BW_BURST_MOVED, bucket_size); | |
457b1d5a | 1022 | break; |
1e881592 | 1023 | } |
89df5fdc LB |
1024 | } |
1025 | ||
1026 | static void txq_set_rate(struct tx_queue *txq, int rate, int burst) | |
1027 | { | |
1028 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1029 | int token_rate; | |
1030 | int bucket_size; | |
1031 | ||
1032 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
1033 | if (token_rate > 1023) | |
1034 | token_rate = 1023; | |
1035 | ||
1036 | bucket_size = (burst + 255) >> 8; | |
1037 | if (bucket_size > 65535) | |
1038 | bucket_size = 65535; | |
1039 | ||
37a6084f LB |
1040 | wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); |
1041 | wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); | |
89df5fdc LB |
1042 | } |
1043 | ||
1044 | static void txq_set_fixed_prio_mode(struct tx_queue *txq) | |
1045 | { | |
1046 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1047 | int off; | |
1048 | u32 val; | |
1049 | ||
1050 | /* | |
1051 | * Turn on fixed priority mode. | |
1052 | */ | |
457b1d5a LB |
1053 | off = 0; |
1054 | switch (mp->shared->tx_bw_control) { | |
1055 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f | 1056 | off = TXQ_FIX_PRIO_CONF; |
457b1d5a LB |
1057 | break; |
1058 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f | 1059 | off = TXQ_FIX_PRIO_CONF_MOVED; |
457b1d5a LB |
1060 | break; |
1061 | } | |
89df5fdc | 1062 | |
457b1d5a | 1063 | if (off) { |
37a6084f | 1064 | val = rdlp(mp, off); |
457b1d5a | 1065 | val |= 1 << txq->index; |
37a6084f | 1066 | wrlp(mp, off, val); |
457b1d5a | 1067 | } |
89df5fdc LB |
1068 | } |
1069 | ||
89df5fdc | 1070 | |
c9df406f | 1071 | /* mii management interface *************************************************/ |
45c5d3bc LB |
1072 | static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id) |
1073 | { | |
1074 | struct mv643xx_eth_shared_private *msp = dev_id; | |
1075 | ||
1076 | if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) { | |
1077 | writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE); | |
1078 | wake_up(&msp->smi_busy_wait); | |
1079 | return IRQ_HANDLED; | |
1080 | } | |
1081 | ||
1082 | return IRQ_NONE; | |
1083 | } | |
c9df406f | 1084 | |
45c5d3bc | 1085 | static int smi_is_done(struct mv643xx_eth_shared_private *msp) |
1da177e4 | 1086 | { |
45c5d3bc LB |
1087 | return !(readl(msp->base + SMI_REG) & SMI_BUSY); |
1088 | } | |
1da177e4 | 1089 | |
45c5d3bc LB |
1090 | static int smi_wait_ready(struct mv643xx_eth_shared_private *msp) |
1091 | { | |
1092 | if (msp->err_interrupt == NO_IRQ) { | |
1093 | int i; | |
c9df406f | 1094 | |
45c5d3bc LB |
1095 | for (i = 0; !smi_is_done(msp); i++) { |
1096 | if (i == 10) | |
1097 | return -ETIMEDOUT; | |
1098 | msleep(10); | |
c9df406f | 1099 | } |
45c5d3bc LB |
1100 | |
1101 | return 0; | |
1102 | } | |
1103 | ||
ee04448d LB |
1104 | if (!smi_is_done(msp)) { |
1105 | wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), | |
1106 | msecs_to_jiffies(100)); | |
1107 | if (!smi_is_done(msp)) | |
1108 | return -ETIMEDOUT; | |
1109 | } | |
45c5d3bc LB |
1110 | |
1111 | return 0; | |
1112 | } | |
1113 | ||
ed94493f | 1114 | static int smi_bus_read(struct mii_bus *bus, int addr, int reg) |
45c5d3bc | 1115 | { |
ed94493f | 1116 | struct mv643xx_eth_shared_private *msp = bus->priv; |
45c5d3bc LB |
1117 | void __iomem *smi_reg = msp->base + SMI_REG; |
1118 | int ret; | |
1119 | ||
45c5d3bc | 1120 | if (smi_wait_ready(msp)) { |
10a9948d | 1121 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f | 1122 | return -ETIMEDOUT; |
1da177e4 LT |
1123 | } |
1124 | ||
fc32b0e2 | 1125 | writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); |
1da177e4 | 1126 | |
45c5d3bc | 1127 | if (smi_wait_ready(msp)) { |
10a9948d | 1128 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f | 1129 | return -ETIMEDOUT; |
45c5d3bc LB |
1130 | } |
1131 | ||
1132 | ret = readl(smi_reg); | |
1133 | if (!(ret & SMI_READ_VALID)) { | |
10a9948d | 1134 | printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n"); |
ed94493f | 1135 | return -ENODEV; |
c9df406f LB |
1136 | } |
1137 | ||
ed94493f | 1138 | return ret & 0xffff; |
1da177e4 LT |
1139 | } |
1140 | ||
ed94493f | 1141 | static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val) |
1da177e4 | 1142 | { |
ed94493f | 1143 | struct mv643xx_eth_shared_private *msp = bus->priv; |
45c5d3bc | 1144 | void __iomem *smi_reg = msp->base + SMI_REG; |
1da177e4 | 1145 | |
45c5d3bc | 1146 | if (smi_wait_ready(msp)) { |
10a9948d | 1147 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
45c5d3bc | 1148 | return -ETIMEDOUT; |
1da177e4 LT |
1149 | } |
1150 | ||
fc32b0e2 | 1151 | writel(SMI_OPCODE_WRITE | (reg << 21) | |
ed94493f | 1152 | (addr << 16) | (val & 0xffff), smi_reg); |
45c5d3bc | 1153 | |
ed94493f | 1154 | if (smi_wait_ready(msp)) { |
10a9948d | 1155 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f LB |
1156 | return -ETIMEDOUT; |
1157 | } | |
45c5d3bc LB |
1158 | |
1159 | return 0; | |
c9df406f | 1160 | } |
1da177e4 | 1161 | |
c9df406f | 1162 | |
8fd89211 LB |
1163 | /* statistics ***************************************************************/ |
1164 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) | |
1165 | { | |
1166 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1167 | struct net_device_stats *stats = &dev->stats; | |
1168 | unsigned long tx_packets = 0; | |
1169 | unsigned long tx_bytes = 0; | |
1170 | unsigned long tx_dropped = 0; | |
1171 | int i; | |
1172 | ||
1173 | for (i = 0; i < mp->txq_count; i++) { | |
1174 | struct tx_queue *txq = mp->txq + i; | |
1175 | ||
1176 | tx_packets += txq->tx_packets; | |
1177 | tx_bytes += txq->tx_bytes; | |
1178 | tx_dropped += txq->tx_dropped; | |
1179 | } | |
1180 | ||
1181 | stats->tx_packets = tx_packets; | |
1182 | stats->tx_bytes = tx_bytes; | |
1183 | stats->tx_dropped = tx_dropped; | |
1184 | ||
1185 | return stats; | |
1186 | } | |
1187 | ||
eaf5d590 LB |
1188 | static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp) |
1189 | { | |
1190 | u32 lro_aggregated = 0; | |
1191 | u32 lro_flushed = 0; | |
1192 | u32 lro_no_desc = 0; | |
1193 | int i; | |
1194 | ||
eaf5d590 LB |
1195 | for (i = 0; i < mp->rxq_count; i++) { |
1196 | struct rx_queue *rxq = mp->rxq + i; | |
1197 | ||
1198 | lro_aggregated += rxq->lro_mgr.stats.aggregated; | |
1199 | lro_flushed += rxq->lro_mgr.stats.flushed; | |
1200 | lro_no_desc += rxq->lro_mgr.stats.no_desc; | |
1201 | } | |
eaf5d590 LB |
1202 | |
1203 | mp->lro_counters.lro_aggregated = lro_aggregated; | |
1204 | mp->lro_counters.lro_flushed = lro_flushed; | |
1205 | mp->lro_counters.lro_no_desc = lro_no_desc; | |
1206 | } | |
1207 | ||
fc32b0e2 | 1208 | static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 1209 | { |
fc32b0e2 | 1210 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
1da177e4 LT |
1211 | } |
1212 | ||
fc32b0e2 | 1213 | static void mib_counters_clear(struct mv643xx_eth_private *mp) |
d0412d96 | 1214 | { |
fc32b0e2 LB |
1215 | int i; |
1216 | ||
1217 | for (i = 0; i < 0x80; i += 4) | |
1218 | mib_read(mp, i); | |
c9df406f | 1219 | } |
d0412d96 | 1220 | |
fc32b0e2 | 1221 | static void mib_counters_update(struct mv643xx_eth_private *mp) |
c9df406f | 1222 | { |
e5371493 | 1223 | struct mib_counters *p = &mp->mib_counters; |
4b8e3655 | 1224 | |
57e8f26a | 1225 | spin_lock_bh(&mp->mib_counters_lock); |
fc32b0e2 | 1226 | p->good_octets_received += mib_read(mp, 0x00); |
fc32b0e2 LB |
1227 | p->bad_octets_received += mib_read(mp, 0x08); |
1228 | p->internal_mac_transmit_err += mib_read(mp, 0x0c); | |
1229 | p->good_frames_received += mib_read(mp, 0x10); | |
1230 | p->bad_frames_received += mib_read(mp, 0x14); | |
1231 | p->broadcast_frames_received += mib_read(mp, 0x18); | |
1232 | p->multicast_frames_received += mib_read(mp, 0x1c); | |
1233 | p->frames_64_octets += mib_read(mp, 0x20); | |
1234 | p->frames_65_to_127_octets += mib_read(mp, 0x24); | |
1235 | p->frames_128_to_255_octets += mib_read(mp, 0x28); | |
1236 | p->frames_256_to_511_octets += mib_read(mp, 0x2c); | |
1237 | p->frames_512_to_1023_octets += mib_read(mp, 0x30); | |
1238 | p->frames_1024_to_max_octets += mib_read(mp, 0x34); | |
1239 | p->good_octets_sent += mib_read(mp, 0x38); | |
fc32b0e2 LB |
1240 | p->good_frames_sent += mib_read(mp, 0x40); |
1241 | p->excessive_collision += mib_read(mp, 0x44); | |
1242 | p->multicast_frames_sent += mib_read(mp, 0x48); | |
1243 | p->broadcast_frames_sent += mib_read(mp, 0x4c); | |
1244 | p->unrec_mac_control_received += mib_read(mp, 0x50); | |
1245 | p->fc_sent += mib_read(mp, 0x54); | |
1246 | p->good_fc_received += mib_read(mp, 0x58); | |
1247 | p->bad_fc_received += mib_read(mp, 0x5c); | |
1248 | p->undersize_received += mib_read(mp, 0x60); | |
1249 | p->fragments_received += mib_read(mp, 0x64); | |
1250 | p->oversize_received += mib_read(mp, 0x68); | |
1251 | p->jabber_received += mib_read(mp, 0x6c); | |
1252 | p->mac_receive_error += mib_read(mp, 0x70); | |
1253 | p->bad_crc_event += mib_read(mp, 0x74); | |
1254 | p->collision += mib_read(mp, 0x78); | |
1255 | p->late_collision += mib_read(mp, 0x7c); | |
57e8f26a | 1256 | spin_unlock_bh(&mp->mib_counters_lock); |
4ff3495a LB |
1257 | |
1258 | mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); | |
1259 | } | |
1260 | ||
1261 | static void mib_counters_timer_wrapper(unsigned long _mp) | |
1262 | { | |
1263 | struct mv643xx_eth_private *mp = (void *)_mp; | |
1264 | ||
1265 | mib_counters_update(mp); | |
d0412d96 JC |
1266 | } |
1267 | ||
c9df406f | 1268 | |
3e508034 LB |
1269 | /* interrupt coalescing *****************************************************/ |
1270 | /* | |
1271 | * Hardware coalescing parameters are set in units of 64 t_clk | |
1272 | * cycles. I.e.: | |
1273 | * | |
1274 | * coal_delay_in_usec = 64000000 * register_value / t_clk_rate | |
1275 | * | |
1276 | * register_value = coal_delay_in_usec * t_clk_rate / 64000000 | |
1277 | * | |
1278 | * In the ->set*() methods, we round the computed register value | |
1279 | * to the nearest integer. | |
1280 | */ | |
1281 | static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) | |
1282 | { | |
1283 | u32 val = rdlp(mp, SDMA_CONFIG); | |
1284 | u64 temp; | |
1285 | ||
1286 | if (mp->shared->extended_rx_coal_limit) | |
1287 | temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); | |
1288 | else | |
1289 | temp = (val & 0x003fff00) >> 8; | |
1290 | ||
1291 | temp *= 64000000; | |
1292 | do_div(temp, mp->shared->t_clk); | |
1293 | ||
1294 | return (unsigned int)temp; | |
1295 | } | |
1296 | ||
1297 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1298 | { | |
1299 | u64 temp; | |
1300 | u32 val; | |
1301 | ||
1302 | temp = (u64)usec * mp->shared->t_clk; | |
1303 | temp += 31999999; | |
1304 | do_div(temp, 64000000); | |
1305 | ||
1306 | val = rdlp(mp, SDMA_CONFIG); | |
1307 | if (mp->shared->extended_rx_coal_limit) { | |
1308 | if (temp > 0xffff) | |
1309 | temp = 0xffff; | |
1310 | val &= ~0x023fff80; | |
1311 | val |= (temp & 0x8000) << 10; | |
1312 | val |= (temp & 0x7fff) << 7; | |
1313 | } else { | |
1314 | if (temp > 0x3fff) | |
1315 | temp = 0x3fff; | |
1316 | val &= ~0x003fff00; | |
1317 | val |= (temp & 0x3fff) << 8; | |
1318 | } | |
1319 | wrlp(mp, SDMA_CONFIG, val); | |
1320 | } | |
1321 | ||
1322 | static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) | |
1323 | { | |
1324 | u64 temp; | |
1325 | ||
1326 | temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; | |
1327 | temp *= 64000000; | |
1328 | do_div(temp, mp->shared->t_clk); | |
1329 | ||
1330 | return (unsigned int)temp; | |
1331 | } | |
1332 | ||
1333 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1334 | { | |
1335 | u64 temp; | |
1336 | ||
1337 | temp = (u64)usec * mp->shared->t_clk; | |
1338 | temp += 31999999; | |
1339 | do_div(temp, 64000000); | |
1340 | ||
1341 | if (temp > 0x3fff) | |
1342 | temp = 0x3fff; | |
1343 | ||
1344 | wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); | |
1345 | } | |
1346 | ||
1347 | ||
c9df406f | 1348 | /* ethtool ******************************************************************/ |
e5371493 | 1349 | struct mv643xx_eth_stats { |
c9df406f LB |
1350 | char stat_string[ETH_GSTRING_LEN]; |
1351 | int sizeof_stat; | |
16820054 LB |
1352 | int netdev_off; |
1353 | int mp_off; | |
c9df406f LB |
1354 | }; |
1355 | ||
16820054 LB |
1356 | #define SSTAT(m) \ |
1357 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ | |
1358 | offsetof(struct net_device, stats.m), -1 } | |
1359 | ||
1360 | #define MIBSTAT(m) \ | |
1361 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ | |
1362 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } | |
1363 | ||
eaf5d590 LB |
1364 | #define LROSTAT(m) \ |
1365 | { #m, FIELD_SIZEOF(struct lro_counters, m), \ | |
1366 | -1, offsetof(struct mv643xx_eth_private, lro_counters.m) } | |
1367 | ||
16820054 LB |
1368 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { |
1369 | SSTAT(rx_packets), | |
1370 | SSTAT(tx_packets), | |
1371 | SSTAT(rx_bytes), | |
1372 | SSTAT(tx_bytes), | |
1373 | SSTAT(rx_errors), | |
1374 | SSTAT(tx_errors), | |
1375 | SSTAT(rx_dropped), | |
1376 | SSTAT(tx_dropped), | |
1377 | MIBSTAT(good_octets_received), | |
1378 | MIBSTAT(bad_octets_received), | |
1379 | MIBSTAT(internal_mac_transmit_err), | |
1380 | MIBSTAT(good_frames_received), | |
1381 | MIBSTAT(bad_frames_received), | |
1382 | MIBSTAT(broadcast_frames_received), | |
1383 | MIBSTAT(multicast_frames_received), | |
1384 | MIBSTAT(frames_64_octets), | |
1385 | MIBSTAT(frames_65_to_127_octets), | |
1386 | MIBSTAT(frames_128_to_255_octets), | |
1387 | MIBSTAT(frames_256_to_511_octets), | |
1388 | MIBSTAT(frames_512_to_1023_octets), | |
1389 | MIBSTAT(frames_1024_to_max_octets), | |
1390 | MIBSTAT(good_octets_sent), | |
1391 | MIBSTAT(good_frames_sent), | |
1392 | MIBSTAT(excessive_collision), | |
1393 | MIBSTAT(multicast_frames_sent), | |
1394 | MIBSTAT(broadcast_frames_sent), | |
1395 | MIBSTAT(unrec_mac_control_received), | |
1396 | MIBSTAT(fc_sent), | |
1397 | MIBSTAT(good_fc_received), | |
1398 | MIBSTAT(bad_fc_received), | |
1399 | MIBSTAT(undersize_received), | |
1400 | MIBSTAT(fragments_received), | |
1401 | MIBSTAT(oversize_received), | |
1402 | MIBSTAT(jabber_received), | |
1403 | MIBSTAT(mac_receive_error), | |
1404 | MIBSTAT(bad_crc_event), | |
1405 | MIBSTAT(collision), | |
1406 | MIBSTAT(late_collision), | |
eaf5d590 LB |
1407 | LROSTAT(lro_aggregated), |
1408 | LROSTAT(lro_flushed), | |
1409 | LROSTAT(lro_no_desc), | |
c9df406f LB |
1410 | }; |
1411 | ||
10a9948d | 1412 | static int |
6bdf576e LB |
1413 | mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, |
1414 | struct ethtool_cmd *cmd) | |
d0412d96 | 1415 | { |
d0412d96 JC |
1416 | int err; |
1417 | ||
ed94493f LB |
1418 | err = phy_read_status(mp->phy); |
1419 | if (err == 0) | |
1420 | err = phy_ethtool_gset(mp->phy, cmd); | |
d0412d96 | 1421 | |
fc32b0e2 LB |
1422 | /* |
1423 | * The MAC does not support 1000baseT_Half. | |
1424 | */ | |
d0412d96 JC |
1425 | cmd->supported &= ~SUPPORTED_1000baseT_Half; |
1426 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1427 | ||
1428 | return err; | |
1429 | } | |
1430 | ||
10a9948d | 1431 | static int |
6bdf576e | 1432 | mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, |
10a9948d | 1433 | struct ethtool_cmd *cmd) |
bedfe324 | 1434 | { |
81600eea LB |
1435 | u32 port_status; |
1436 | ||
37a6084f | 1437 | port_status = rdlp(mp, PORT_STATUS); |
81600eea | 1438 | |
bedfe324 LB |
1439 | cmd->supported = SUPPORTED_MII; |
1440 | cmd->advertising = ADVERTISED_MII; | |
81600eea LB |
1441 | switch (port_status & PORT_SPEED_MASK) { |
1442 | case PORT_SPEED_10: | |
1443 | cmd->speed = SPEED_10; | |
1444 | break; | |
1445 | case PORT_SPEED_100: | |
1446 | cmd->speed = SPEED_100; | |
1447 | break; | |
1448 | case PORT_SPEED_1000: | |
1449 | cmd->speed = SPEED_1000; | |
1450 | break; | |
1451 | default: | |
1452 | cmd->speed = -1; | |
1453 | break; | |
1454 | } | |
1455 | cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; | |
bedfe324 LB |
1456 | cmd->port = PORT_MII; |
1457 | cmd->phy_address = 0; | |
1458 | cmd->transceiver = XCVR_INTERNAL; | |
1459 | cmd->autoneg = AUTONEG_DISABLE; | |
1460 | cmd->maxtxpkt = 1; | |
1461 | cmd->maxrxpkt = 1; | |
1462 | ||
1463 | return 0; | |
1464 | } | |
1465 | ||
6bdf576e LB |
1466 | static int |
1467 | mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1468 | { | |
1469 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1470 | ||
1471 | if (mp->phy != NULL) | |
1472 | return mv643xx_eth_get_settings_phy(mp, cmd); | |
1473 | else | |
1474 | return mv643xx_eth_get_settings_phyless(mp, cmd); | |
1475 | } | |
1476 | ||
10a9948d LB |
1477 | static int |
1478 | mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1da177e4 | 1479 | { |
e5371493 | 1480 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
ab4384a6 | 1481 | |
6bdf576e LB |
1482 | if (mp->phy == NULL) |
1483 | return -EINVAL; | |
1484 | ||
fc32b0e2 LB |
1485 | /* |
1486 | * The MAC does not support 1000baseT_Half. | |
1487 | */ | |
1488 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1489 | ||
ed94493f | 1490 | return phy_ethtool_sset(mp->phy, cmd); |
c9df406f | 1491 | } |
1da177e4 | 1492 | |
fc32b0e2 LB |
1493 | static void mv643xx_eth_get_drvinfo(struct net_device *dev, |
1494 | struct ethtool_drvinfo *drvinfo) | |
c9df406f | 1495 | { |
e5371493 LB |
1496 | strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); |
1497 | strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); | |
c9df406f | 1498 | strncpy(drvinfo->fw_version, "N/A", 32); |
fc32b0e2 | 1499 | strncpy(drvinfo->bus_info, "platform", 32); |
16820054 | 1500 | drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); |
c9df406f | 1501 | } |
1da177e4 | 1502 | |
fc32b0e2 | 1503 | static int mv643xx_eth_nway_reset(struct net_device *dev) |
c9df406f | 1504 | { |
e5371493 | 1505 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1506 | |
6bdf576e LB |
1507 | if (mp->phy == NULL) |
1508 | return -EINVAL; | |
1da177e4 | 1509 | |
6bdf576e | 1510 | return genphy_restart_aneg(mp->phy); |
bedfe324 LB |
1511 | } |
1512 | ||
c9df406f LB |
1513 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1514 | { | |
ed94493f | 1515 | return !!netif_carrier_ok(dev); |
bedfe324 LB |
1516 | } |
1517 | ||
3e508034 LB |
1518 | static int |
1519 | mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1520 | { | |
1521 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1522 | ||
1523 | ec->rx_coalesce_usecs = get_rx_coal(mp); | |
1524 | ec->tx_coalesce_usecs = get_tx_coal(mp); | |
1525 | ||
1526 | return 0; | |
1527 | } | |
1528 | ||
1529 | static int | |
1530 | mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1531 | { | |
1532 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1533 | ||
1534 | set_rx_coal(mp, ec->rx_coalesce_usecs); | |
1535 | set_tx_coal(mp, ec->tx_coalesce_usecs); | |
1536 | ||
1537 | return 0; | |
1538 | } | |
1539 | ||
e7d2f4db LB |
1540 | static void |
1541 | mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1542 | { | |
1543 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1544 | ||
1545 | er->rx_max_pending = 4096; | |
1546 | er->tx_max_pending = 4096; | |
1547 | er->rx_mini_max_pending = 0; | |
1548 | er->rx_jumbo_max_pending = 0; | |
1549 | ||
1550 | er->rx_pending = mp->rx_ring_size; | |
1551 | er->tx_pending = mp->tx_ring_size; | |
1552 | er->rx_mini_pending = 0; | |
1553 | er->rx_jumbo_pending = 0; | |
1554 | } | |
1555 | ||
1556 | static int | |
1557 | mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1558 | { | |
1559 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1560 | ||
1561 | if (er->rx_mini_pending || er->rx_jumbo_pending) | |
1562 | return -EINVAL; | |
1563 | ||
1564 | mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; | |
1565 | mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096; | |
1566 | ||
1567 | if (netif_running(dev)) { | |
1568 | mv643xx_eth_stop(dev); | |
1569 | if (mv643xx_eth_open(dev)) { | |
1570 | dev_printk(KERN_ERR, &dev->dev, | |
1571 | "fatal error on re-opening device after " | |
1572 | "ring param change\n"); | |
1573 | return -ENOMEM; | |
1574 | } | |
1575 | } | |
1576 | ||
1577 | return 0; | |
1578 | } | |
1579 | ||
d888b373 LB |
1580 | static u32 |
1581 | mv643xx_eth_get_rx_csum(struct net_device *dev) | |
1582 | { | |
1583 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1584 | ||
1585 | return !!(rdlp(mp, PORT_CONFIG) & 0x02000000); | |
1586 | } | |
1587 | ||
1588 | static int | |
1589 | mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum) | |
1590 | { | |
1591 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1592 | ||
1593 | wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); | |
1594 | ||
1595 | return 0; | |
1596 | } | |
1597 | ||
fc32b0e2 LB |
1598 | static void mv643xx_eth_get_strings(struct net_device *dev, |
1599 | uint32_t stringset, uint8_t *data) | |
c9df406f LB |
1600 | { |
1601 | int i; | |
1da177e4 | 1602 | |
fc32b0e2 LB |
1603 | if (stringset == ETH_SS_STATS) { |
1604 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { | |
c9df406f | 1605 | memcpy(data + i * ETH_GSTRING_LEN, |
16820054 | 1606 | mv643xx_eth_stats[i].stat_string, |
e5371493 | 1607 | ETH_GSTRING_LEN); |
c9df406f | 1608 | } |
c9df406f LB |
1609 | } |
1610 | } | |
1da177e4 | 1611 | |
fc32b0e2 LB |
1612 | static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, |
1613 | struct ethtool_stats *stats, | |
1614 | uint64_t *data) | |
c9df406f | 1615 | { |
b9873841 | 1616 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 1617 | int i; |
1da177e4 | 1618 | |
8fd89211 | 1619 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 1620 | mib_counters_update(mp); |
eaf5d590 | 1621 | mv643xx_eth_grab_lro_stats(mp); |
1da177e4 | 1622 | |
16820054 LB |
1623 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
1624 | const struct mv643xx_eth_stats *stat; | |
1625 | void *p; | |
1626 | ||
1627 | stat = mv643xx_eth_stats + i; | |
1628 | ||
1629 | if (stat->netdev_off >= 0) | |
1630 | p = ((void *)mp->dev) + stat->netdev_off; | |
1631 | else | |
1632 | p = ((void *)mp) + stat->mp_off; | |
1633 | ||
1634 | data[i] = (stat->sizeof_stat == 8) ? | |
1635 | *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1636 | } |
c9df406f | 1637 | } |
1da177e4 | 1638 | |
fc32b0e2 | 1639 | static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) |
c9df406f | 1640 | { |
fc32b0e2 | 1641 | if (sset == ETH_SS_STATS) |
16820054 | 1642 | return ARRAY_SIZE(mv643xx_eth_stats); |
fc32b0e2 LB |
1643 | |
1644 | return -EOPNOTSUPP; | |
c9df406f | 1645 | } |
1da177e4 | 1646 | |
e5371493 | 1647 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
fc32b0e2 LB |
1648 | .get_settings = mv643xx_eth_get_settings, |
1649 | .set_settings = mv643xx_eth_set_settings, | |
1650 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1651 | .nway_reset = mv643xx_eth_nway_reset, | |
1652 | .get_link = mv643xx_eth_get_link, | |
3e508034 LB |
1653 | .get_coalesce = mv643xx_eth_get_coalesce, |
1654 | .set_coalesce = mv643xx_eth_set_coalesce, | |
e7d2f4db LB |
1655 | .get_ringparam = mv643xx_eth_get_ringparam, |
1656 | .set_ringparam = mv643xx_eth_set_ringparam, | |
d888b373 LB |
1657 | .get_rx_csum = mv643xx_eth_get_rx_csum, |
1658 | .set_rx_csum = mv643xx_eth_set_rx_csum, | |
b8df184f | 1659 | .set_tx_csum = ethtool_op_set_tx_csum, |
c9df406f | 1660 | .set_sg = ethtool_op_set_sg, |
fc32b0e2 LB |
1661 | .get_strings = mv643xx_eth_get_strings, |
1662 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
eaf5d590 LB |
1663 | .get_flags = ethtool_op_get_flags, |
1664 | .set_flags = ethtool_op_set_flags, | |
e5371493 | 1665 | .get_sset_count = mv643xx_eth_get_sset_count, |
c9df406f | 1666 | }; |
1da177e4 | 1667 | |
bea3348e | 1668 | |
c9df406f | 1669 | /* address handling *********************************************************/ |
5daffe94 | 1670 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1671 | { |
66e63ffb LB |
1672 | unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); |
1673 | unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); | |
1da177e4 | 1674 | |
5daffe94 LB |
1675 | addr[0] = (mac_h >> 24) & 0xff; |
1676 | addr[1] = (mac_h >> 16) & 0xff; | |
1677 | addr[2] = (mac_h >> 8) & 0xff; | |
1678 | addr[3] = mac_h & 0xff; | |
1679 | addr[4] = (mac_l >> 8) & 0xff; | |
1680 | addr[5] = mac_l & 0xff; | |
c9df406f | 1681 | } |
1da177e4 | 1682 | |
66e63ffb | 1683 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1684 | { |
66e63ffb LB |
1685 | wrlp(mp, MAC_ADDR_HIGH, |
1686 | (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); | |
1687 | wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); | |
c9df406f | 1688 | } |
d0412d96 | 1689 | |
66e63ffb | 1690 | static u32 uc_addr_filter_mask(struct net_device *dev) |
c9df406f | 1691 | { |
ccffad25 | 1692 | struct netdev_hw_addr *ha; |
66e63ffb | 1693 | u32 nibbles; |
1da177e4 | 1694 | |
66e63ffb LB |
1695 | if (dev->flags & IFF_PROMISC) |
1696 | return 0; | |
1da177e4 | 1697 | |
66e63ffb | 1698 | nibbles = 1 << (dev->dev_addr[5] & 0x0f); |
32e7bfc4 | 1699 | netdev_for_each_uc_addr(ha, dev) { |
ccffad25 | 1700 | if (memcmp(dev->dev_addr, ha->addr, 5)) |
66e63ffb | 1701 | return 0; |
ccffad25 | 1702 | if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0) |
66e63ffb | 1703 | return 0; |
ff561eef | 1704 | |
ccffad25 | 1705 | nibbles |= 1 << (ha->addr[5] & 0x0f); |
66e63ffb | 1706 | } |
1da177e4 | 1707 | |
66e63ffb | 1708 | return nibbles; |
1da177e4 LT |
1709 | } |
1710 | ||
66e63ffb | 1711 | static void mv643xx_eth_program_unicast_filter(struct net_device *dev) |
1da177e4 | 1712 | { |
e5371493 | 1713 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1714 | u32 port_config; |
1715 | u32 nibbles; | |
1716 | int i; | |
1da177e4 | 1717 | |
cc9754b3 | 1718 | uc_addr_set(mp, dev->dev_addr); |
1da177e4 | 1719 | |
6877f54e PS |
1720 | port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE; |
1721 | ||
66e63ffb LB |
1722 | nibbles = uc_addr_filter_mask(dev); |
1723 | if (!nibbles) { | |
1724 | port_config |= UNICAST_PROMISCUOUS_MODE; | |
6877f54e | 1725 | nibbles = 0xffff; |
66e63ffb LB |
1726 | } |
1727 | ||
1728 | for (i = 0; i < 16; i += 4) { | |
1729 | int off = UNICAST_TABLE(mp->port_num) + i; | |
1730 | u32 v; | |
1731 | ||
1732 | v = 0; | |
1733 | if (nibbles & 1) | |
1734 | v |= 0x00000001; | |
1735 | if (nibbles & 2) | |
1736 | v |= 0x00000100; | |
1737 | if (nibbles & 4) | |
1738 | v |= 0x00010000; | |
1739 | if (nibbles & 8) | |
1740 | v |= 0x01000000; | |
1741 | nibbles >>= 4; | |
1742 | ||
1743 | wrl(mp, off, v); | |
1744 | } | |
1745 | ||
66e63ffb | 1746 | wrlp(mp, PORT_CONFIG, port_config); |
1da177e4 LT |
1747 | } |
1748 | ||
69876569 LB |
1749 | static int addr_crc(unsigned char *addr) |
1750 | { | |
1751 | int crc = 0; | |
1752 | int i; | |
1753 | ||
1754 | for (i = 0; i < 6; i++) { | |
1755 | int j; | |
1756 | ||
1757 | crc = (crc ^ addr[i]) << 8; | |
1758 | for (j = 7; j >= 0; j--) { | |
1759 | if (crc & (0x100 << j)) | |
1760 | crc ^= 0x107 << j; | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | return crc; | |
1765 | } | |
1766 | ||
66e63ffb | 1767 | static void mv643xx_eth_program_multicast_filter(struct net_device *dev) |
1da177e4 | 1768 | { |
fc32b0e2 | 1769 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1770 | u32 *mc_spec; |
1771 | u32 *mc_other; | |
fc32b0e2 LB |
1772 | struct dev_addr_list *addr; |
1773 | int i; | |
c8aaea25 | 1774 | |
fc32b0e2 | 1775 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { |
66e63ffb LB |
1776 | int port_num; |
1777 | u32 accept; | |
c8aaea25 | 1778 | |
66e63ffb LB |
1779 | oom: |
1780 | port_num = mp->port_num; | |
1781 | accept = 0x01010101; | |
fc32b0e2 LB |
1782 | for (i = 0; i < 0x100; i += 4) { |
1783 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); | |
1784 | wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); | |
c9df406f LB |
1785 | } |
1786 | return; | |
1787 | } | |
c8aaea25 | 1788 | |
82a5bd6a | 1789 | mc_spec = kmalloc(0x200, GFP_ATOMIC); |
66e63ffb LB |
1790 | if (mc_spec == NULL) |
1791 | goto oom; | |
1792 | mc_other = mc_spec + (0x100 >> 2); | |
1793 | ||
1794 | memset(mc_spec, 0, 0x100); | |
1795 | memset(mc_other, 0, 0x100); | |
1da177e4 | 1796 | |
fc32b0e2 LB |
1797 | for (addr = dev->mc_list; addr != NULL; addr = addr->next) { |
1798 | u8 *a = addr->da_addr; | |
66e63ffb LB |
1799 | u32 *table; |
1800 | int entry; | |
1da177e4 | 1801 | |
fc32b0e2 | 1802 | if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { |
66e63ffb LB |
1803 | table = mc_spec; |
1804 | entry = a[5]; | |
fc32b0e2 | 1805 | } else { |
66e63ffb LB |
1806 | table = mc_other; |
1807 | entry = addr_crc(a); | |
fc32b0e2 | 1808 | } |
66e63ffb | 1809 | |
2b448334 | 1810 | table[entry >> 2] |= 1 << (8 * (entry & 3)); |
fc32b0e2 | 1811 | } |
66e63ffb LB |
1812 | |
1813 | for (i = 0; i < 0x100; i += 4) { | |
1814 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]); | |
1815 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]); | |
1816 | } | |
1817 | ||
1818 | kfree(mc_spec); | |
1819 | } | |
1820 | ||
1821 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
1822 | { | |
1823 | mv643xx_eth_program_unicast_filter(dev); | |
1824 | mv643xx_eth_program_multicast_filter(dev); | |
1825 | } | |
1826 | ||
1827 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
1828 | { | |
1829 | struct sockaddr *sa = addr; | |
1830 | ||
a29ec08a DK |
1831 | if (!is_valid_ether_addr(sa->sa_data)) |
1832 | return -EINVAL; | |
1833 | ||
66e63ffb LB |
1834 | memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); |
1835 | ||
1836 | netif_addr_lock_bh(dev); | |
1837 | mv643xx_eth_program_unicast_filter(dev); | |
1838 | netif_addr_unlock_bh(dev); | |
1839 | ||
1840 | return 0; | |
c9df406f | 1841 | } |
c8aaea25 | 1842 | |
c8aaea25 | 1843 | |
c9df406f | 1844 | /* rx/tx queue initialisation ***********************************************/ |
64da80a2 | 1845 | static int rxq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1846 | { |
64da80a2 | 1847 | struct rx_queue *rxq = mp->rxq + index; |
8a578111 LB |
1848 | struct rx_desc *rx_desc; |
1849 | int size; | |
c9df406f LB |
1850 | int i; |
1851 | ||
64da80a2 LB |
1852 | rxq->index = index; |
1853 | ||
e7d2f4db | 1854 | rxq->rx_ring_size = mp->rx_ring_size; |
8a578111 LB |
1855 | |
1856 | rxq->rx_desc_count = 0; | |
1857 | rxq->rx_curr_desc = 0; | |
1858 | rxq->rx_used_desc = 0; | |
1859 | ||
1860 | size = rxq->rx_ring_size * sizeof(struct rx_desc); | |
1861 | ||
f7981c1c | 1862 | if (index == 0 && size <= mp->rx_desc_sram_size) { |
8a578111 LB |
1863 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, |
1864 | mp->rx_desc_sram_size); | |
1865 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; | |
1866 | } else { | |
eb0519b5 GP |
1867 | rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, |
1868 | size, &rxq->rx_desc_dma, | |
1869 | GFP_KERNEL); | |
f7ea3337 PJ |
1870 | } |
1871 | ||
8a578111 LB |
1872 | if (rxq->rx_desc_area == NULL) { |
1873 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1874 | "can't allocate rx ring (%d bytes)\n", size); | |
1875 | goto out; | |
1876 | } | |
1877 | memset(rxq->rx_desc_area, 0, size); | |
1da177e4 | 1878 | |
8a578111 LB |
1879 | rxq->rx_desc_area_size = size; |
1880 | rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), | |
1881 | GFP_KERNEL); | |
1882 | if (rxq->rx_skb == NULL) { | |
1883 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1884 | "can't allocate rx skb ring\n"); | |
1885 | goto out_free; | |
1886 | } | |
1887 | ||
1888 | rx_desc = (struct rx_desc *)rxq->rx_desc_area; | |
1889 | for (i = 0; i < rxq->rx_ring_size; i++) { | |
9da78745 LB |
1890 | int nexti; |
1891 | ||
1892 | nexti = i + 1; | |
1893 | if (nexti == rxq->rx_ring_size) | |
1894 | nexti = 0; | |
1895 | ||
8a578111 LB |
1896 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + |
1897 | nexti * sizeof(struct rx_desc); | |
1898 | } | |
1899 | ||
eaf5d590 LB |
1900 | rxq->lro_mgr.dev = mp->dev; |
1901 | memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats)); | |
1902 | rxq->lro_mgr.features = LRO_F_NAPI; | |
1903 | rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1904 | rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
1905 | rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr); | |
1906 | rxq->lro_mgr.max_aggr = 32; | |
1907 | rxq->lro_mgr.frag_align_pad = 0; | |
1908 | rxq->lro_mgr.lro_arr = rxq->lro_arr; | |
1909 | rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header; | |
1910 | ||
1911 | memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr)); | |
eaf5d590 | 1912 | |
8a578111 LB |
1913 | return 0; |
1914 | ||
1915 | ||
1916 | out_free: | |
f7981c1c | 1917 | if (index == 0 && size <= mp->rx_desc_sram_size) |
8a578111 LB |
1918 | iounmap(rxq->rx_desc_area); |
1919 | else | |
eb0519b5 | 1920 | dma_free_coherent(mp->dev->dev.parent, size, |
8a578111 LB |
1921 | rxq->rx_desc_area, |
1922 | rxq->rx_desc_dma); | |
1923 | ||
1924 | out: | |
1925 | return -ENOMEM; | |
c9df406f | 1926 | } |
c8aaea25 | 1927 | |
8a578111 | 1928 | static void rxq_deinit(struct rx_queue *rxq) |
c9df406f | 1929 | { |
8a578111 LB |
1930 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1931 | int i; | |
1932 | ||
1933 | rxq_disable(rxq); | |
c8aaea25 | 1934 | |
8a578111 LB |
1935 | for (i = 0; i < rxq->rx_ring_size; i++) { |
1936 | if (rxq->rx_skb[i]) { | |
1937 | dev_kfree_skb(rxq->rx_skb[i]); | |
1938 | rxq->rx_desc_count--; | |
1da177e4 | 1939 | } |
c8aaea25 | 1940 | } |
1da177e4 | 1941 | |
8a578111 LB |
1942 | if (rxq->rx_desc_count) { |
1943 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1944 | "error freeing rx ring -- %d skbs stuck\n", | |
1945 | rxq->rx_desc_count); | |
1946 | } | |
1947 | ||
f7981c1c | 1948 | if (rxq->index == 0 && |
64da80a2 | 1949 | rxq->rx_desc_area_size <= mp->rx_desc_sram_size) |
8a578111 | 1950 | iounmap(rxq->rx_desc_area); |
c9df406f | 1951 | else |
eb0519b5 | 1952 | dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, |
8a578111 LB |
1953 | rxq->rx_desc_area, rxq->rx_desc_dma); |
1954 | ||
1955 | kfree(rxq->rx_skb); | |
c9df406f | 1956 | } |
1da177e4 | 1957 | |
3d6b35bc | 1958 | static int txq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1959 | { |
3d6b35bc | 1960 | struct tx_queue *txq = mp->txq + index; |
13d64285 LB |
1961 | struct tx_desc *tx_desc; |
1962 | int size; | |
c9df406f | 1963 | int i; |
1da177e4 | 1964 | |
3d6b35bc LB |
1965 | txq->index = index; |
1966 | ||
e7d2f4db | 1967 | txq->tx_ring_size = mp->tx_ring_size; |
13d64285 LB |
1968 | |
1969 | txq->tx_desc_count = 0; | |
1970 | txq->tx_curr_desc = 0; | |
1971 | txq->tx_used_desc = 0; | |
1972 | ||
1973 | size = txq->tx_ring_size * sizeof(struct tx_desc); | |
1974 | ||
f7981c1c | 1975 | if (index == 0 && size <= mp->tx_desc_sram_size) { |
13d64285 LB |
1976 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, |
1977 | mp->tx_desc_sram_size); | |
1978 | txq->tx_desc_dma = mp->tx_desc_sram_addr; | |
1979 | } else { | |
eb0519b5 GP |
1980 | txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, |
1981 | size, &txq->tx_desc_dma, | |
1982 | GFP_KERNEL); | |
13d64285 LB |
1983 | } |
1984 | ||
1985 | if (txq->tx_desc_area == NULL) { | |
1986 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1987 | "can't allocate tx ring (%d bytes)\n", size); | |
99ab08e0 | 1988 | return -ENOMEM; |
c9df406f | 1989 | } |
13d64285 LB |
1990 | memset(txq->tx_desc_area, 0, size); |
1991 | ||
1992 | txq->tx_desc_area_size = size; | |
13d64285 LB |
1993 | |
1994 | tx_desc = (struct tx_desc *)txq->tx_desc_area; | |
1995 | for (i = 0; i < txq->tx_ring_size; i++) { | |
6b368f68 | 1996 | struct tx_desc *txd = tx_desc + i; |
9da78745 LB |
1997 | int nexti; |
1998 | ||
1999 | nexti = i + 1; | |
2000 | if (nexti == txq->tx_ring_size) | |
2001 | nexti = 0; | |
6b368f68 LB |
2002 | |
2003 | txd->cmd_sts = 0; | |
2004 | txd->next_desc_ptr = txq->tx_desc_dma + | |
13d64285 LB |
2005 | nexti * sizeof(struct tx_desc); |
2006 | } | |
2007 | ||
99ab08e0 | 2008 | skb_queue_head_init(&txq->tx_skb); |
c9df406f | 2009 | |
99ab08e0 | 2010 | return 0; |
c8aaea25 | 2011 | } |
1da177e4 | 2012 | |
13d64285 | 2013 | static void txq_deinit(struct tx_queue *txq) |
c9df406f | 2014 | { |
13d64285 | 2015 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
fa3959f4 | 2016 | |
13d64285 | 2017 | txq_disable(txq); |
1fa38c58 | 2018 | txq_reclaim(txq, txq->tx_ring_size, 1); |
1da177e4 | 2019 | |
13d64285 | 2020 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
1da177e4 | 2021 | |
f7981c1c | 2022 | if (txq->index == 0 && |
3d6b35bc | 2023 | txq->tx_desc_area_size <= mp->tx_desc_sram_size) |
13d64285 | 2024 | iounmap(txq->tx_desc_area); |
c9df406f | 2025 | else |
eb0519b5 | 2026 | dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, |
13d64285 | 2027 | txq->tx_desc_area, txq->tx_desc_dma); |
c9df406f | 2028 | } |
1da177e4 | 2029 | |
1da177e4 | 2030 | |
c9df406f | 2031 | /* netdev ops and related ***************************************************/ |
1fa38c58 LB |
2032 | static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) |
2033 | { | |
2034 | u32 int_cause; | |
2035 | u32 int_cause_ext; | |
2036 | ||
e0ca8410 | 2037 | int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask; |
1fa38c58 LB |
2038 | if (int_cause == 0) |
2039 | return 0; | |
2040 | ||
2041 | int_cause_ext = 0; | |
e0ca8410 SB |
2042 | if (int_cause & INT_EXT) { |
2043 | int_cause &= ~INT_EXT; | |
37a6084f | 2044 | int_cause_ext = rdlp(mp, INT_CAUSE_EXT); |
e0ca8410 | 2045 | } |
1fa38c58 | 2046 | |
1fa38c58 | 2047 | if (int_cause) { |
37a6084f | 2048 | wrlp(mp, INT_CAUSE, ~int_cause); |
1fa38c58 | 2049 | mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & |
37a6084f | 2050 | ~(rdlp(mp, TXQ_COMMAND) & 0xff); |
1fa38c58 LB |
2051 | mp->work_rx |= (int_cause & INT_RX) >> 2; |
2052 | } | |
2053 | ||
2054 | int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; | |
2055 | if (int_cause_ext) { | |
37a6084f | 2056 | wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); |
1fa38c58 LB |
2057 | if (int_cause_ext & INT_EXT_LINK_PHY) |
2058 | mp->work_link = 1; | |
2059 | mp->work_tx |= int_cause_ext & INT_EXT_TX; | |
2060 | } | |
2061 | ||
2062 | return 1; | |
2063 | } | |
2064 | ||
2065 | static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) | |
2066 | { | |
2067 | struct net_device *dev = (struct net_device *)dev_id; | |
2068 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
2069 | ||
2070 | if (unlikely(!mv643xx_eth_collect_events(mp))) | |
2071 | return IRQ_NONE; | |
2072 | ||
37a6084f | 2073 | wrlp(mp, INT_MASK, 0); |
1fa38c58 LB |
2074 | napi_schedule(&mp->napi); |
2075 | ||
2076 | return IRQ_HANDLED; | |
2077 | } | |
2078 | ||
2f7eb47a LB |
2079 | static void handle_link_event(struct mv643xx_eth_private *mp) |
2080 | { | |
2081 | struct net_device *dev = mp->dev; | |
2082 | u32 port_status; | |
2083 | int speed; | |
2084 | int duplex; | |
2085 | int fc; | |
2086 | ||
37a6084f | 2087 | port_status = rdlp(mp, PORT_STATUS); |
2f7eb47a LB |
2088 | if (!(port_status & LINK_UP)) { |
2089 | if (netif_carrier_ok(dev)) { | |
2090 | int i; | |
2091 | ||
2092 | printk(KERN_INFO "%s: link down\n", dev->name); | |
2093 | ||
2094 | netif_carrier_off(dev); | |
2f7eb47a | 2095 | |
f7981c1c | 2096 | for (i = 0; i < mp->txq_count; i++) { |
2f7eb47a LB |
2097 | struct tx_queue *txq = mp->txq + i; |
2098 | ||
1fa38c58 | 2099 | txq_reclaim(txq, txq->tx_ring_size, 1); |
f7981c1c | 2100 | txq_reset_hw_ptr(txq); |
2f7eb47a LB |
2101 | } |
2102 | } | |
2103 | return; | |
2104 | } | |
2105 | ||
2106 | switch (port_status & PORT_SPEED_MASK) { | |
2107 | case PORT_SPEED_10: | |
2108 | speed = 10; | |
2109 | break; | |
2110 | case PORT_SPEED_100: | |
2111 | speed = 100; | |
2112 | break; | |
2113 | case PORT_SPEED_1000: | |
2114 | speed = 1000; | |
2115 | break; | |
2116 | default: | |
2117 | speed = -1; | |
2118 | break; | |
2119 | } | |
2120 | duplex = (port_status & FULL_DUPLEX) ? 1 : 0; | |
2121 | fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; | |
2122 | ||
2123 | printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " | |
2124 | "flow control %sabled\n", dev->name, | |
2125 | speed, duplex ? "full" : "half", | |
2126 | fc ? "en" : "dis"); | |
2127 | ||
4fdeca3f | 2128 | if (!netif_carrier_ok(dev)) |
2f7eb47a | 2129 | netif_carrier_on(dev); |
2f7eb47a LB |
2130 | } |
2131 | ||
1fa38c58 | 2132 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
c9df406f | 2133 | { |
1fa38c58 LB |
2134 | struct mv643xx_eth_private *mp; |
2135 | int work_done; | |
ce4e2e45 | 2136 | |
1fa38c58 | 2137 | mp = container_of(napi, struct mv643xx_eth_private, napi); |
fc32b0e2 | 2138 | |
1319ebad LB |
2139 | if (unlikely(mp->oom)) { |
2140 | mp->oom = 0; | |
2141 | del_timer(&mp->rx_oom); | |
2142 | } | |
1da177e4 | 2143 | |
1fa38c58 LB |
2144 | work_done = 0; |
2145 | while (work_done < budget) { | |
2146 | u8 queue_mask; | |
2147 | int queue; | |
2148 | int work_tbd; | |
2149 | ||
2150 | if (mp->work_link) { | |
2151 | mp->work_link = 0; | |
2152 | handle_link_event(mp); | |
26ef1f17 | 2153 | work_done++; |
1fa38c58 LB |
2154 | continue; |
2155 | } | |
1da177e4 | 2156 | |
1319ebad LB |
2157 | queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; |
2158 | if (likely(!mp->oom)) | |
2159 | queue_mask |= mp->work_rx_refill; | |
2160 | ||
1fa38c58 LB |
2161 | if (!queue_mask) { |
2162 | if (mv643xx_eth_collect_events(mp)) | |
2163 | continue; | |
2164 | break; | |
2165 | } | |
1da177e4 | 2166 | |
1fa38c58 LB |
2167 | queue = fls(queue_mask) - 1; |
2168 | queue_mask = 1 << queue; | |
2169 | ||
2170 | work_tbd = budget - work_done; | |
2171 | if (work_tbd > 16) | |
2172 | work_tbd = 16; | |
2173 | ||
2174 | if (mp->work_tx_end & queue_mask) { | |
2175 | txq_kick(mp->txq + queue); | |
2176 | } else if (mp->work_tx & queue_mask) { | |
2177 | work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); | |
2178 | txq_maybe_wake(mp->txq + queue); | |
2179 | } else if (mp->work_rx & queue_mask) { | |
2180 | work_done += rxq_process(mp->rxq + queue, work_tbd); | |
1319ebad | 2181 | } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { |
1fa38c58 LB |
2182 | work_done += rxq_refill(mp->rxq + queue, work_tbd); |
2183 | } else { | |
2184 | BUG(); | |
2185 | } | |
84dd619e | 2186 | } |
fc32b0e2 | 2187 | |
1fa38c58 | 2188 | if (work_done < budget) { |
1319ebad | 2189 | if (mp->oom) |
1fa38c58 LB |
2190 | mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); |
2191 | napi_complete(napi); | |
e0ca8410 | 2192 | wrlp(mp, INT_MASK, mp->int_mask); |
226bb6b7 | 2193 | } |
3d6b35bc | 2194 | |
1fa38c58 LB |
2195 | return work_done; |
2196 | } | |
8fa89bf5 | 2197 | |
1fa38c58 LB |
2198 | static inline void oom_timer_wrapper(unsigned long data) |
2199 | { | |
2200 | struct mv643xx_eth_private *mp = (void *)data; | |
1da177e4 | 2201 | |
1fa38c58 | 2202 | napi_schedule(&mp->napi); |
1da177e4 LT |
2203 | } |
2204 | ||
e5371493 | 2205 | static void phy_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2206 | { |
45c5d3bc LB |
2207 | int data; |
2208 | ||
ed94493f | 2209 | data = phy_read(mp->phy, MII_BMCR); |
45c5d3bc LB |
2210 | if (data < 0) |
2211 | return; | |
1da177e4 | 2212 | |
7f106c1d | 2213 | data |= BMCR_RESET; |
ed94493f | 2214 | if (phy_write(mp->phy, MII_BMCR, data) < 0) |
45c5d3bc | 2215 | return; |
1da177e4 | 2216 | |
c9df406f | 2217 | do { |
ed94493f | 2218 | data = phy_read(mp->phy, MII_BMCR); |
45c5d3bc | 2219 | } while (data >= 0 && data & BMCR_RESET); |
1da177e4 LT |
2220 | } |
2221 | ||
fc32b0e2 | 2222 | static void port_start(struct mv643xx_eth_private *mp) |
1da177e4 | 2223 | { |
d0412d96 | 2224 | u32 pscr; |
8a578111 | 2225 | int i; |
1da177e4 | 2226 | |
bedfe324 LB |
2227 | /* |
2228 | * Perform PHY reset, if there is a PHY. | |
2229 | */ | |
ed94493f | 2230 | if (mp->phy != NULL) { |
bedfe324 LB |
2231 | struct ethtool_cmd cmd; |
2232 | ||
2233 | mv643xx_eth_get_settings(mp->dev, &cmd); | |
2234 | phy_reset(mp); | |
2235 | mv643xx_eth_set_settings(mp->dev, &cmd); | |
2236 | } | |
1da177e4 | 2237 | |
81600eea LB |
2238 | /* |
2239 | * Configure basic link parameters. | |
2240 | */ | |
37a6084f | 2241 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2242 | |
2243 | pscr |= SERIAL_PORT_ENABLE; | |
37a6084f | 2244 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2245 | |
2246 | pscr |= DO_NOT_FORCE_LINK_FAIL; | |
ed94493f | 2247 | if (mp->phy == NULL) |
81600eea | 2248 | pscr |= FORCE_LINK_PASS; |
37a6084f | 2249 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea | 2250 | |
13d64285 LB |
2251 | /* |
2252 | * Configure TX path and queues. | |
2253 | */ | |
89df5fdc | 2254 | tx_set_rate(mp, 1000000000, 16777216); |
f7981c1c | 2255 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc | 2256 | struct tx_queue *txq = mp->txq + i; |
13d64285 | 2257 | |
6b368f68 | 2258 | txq_reset_hw_ptr(txq); |
89df5fdc LB |
2259 | txq_set_rate(txq, 1000000000, 16777216); |
2260 | txq_set_fixed_prio_mode(txq); | |
13d64285 LB |
2261 | } |
2262 | ||
d9a073ea LB |
2263 | /* |
2264 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
170e7108 LB |
2265 | * frames to RX queue #0, and include the pseudo-header when |
2266 | * calculating receive checksums. | |
d9a073ea | 2267 | */ |
37a6084f | 2268 | wrlp(mp, PORT_CONFIG, 0x02000000); |
01999873 | 2269 | |
376489a2 LB |
2270 | /* |
2271 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
2272 | */ | |
37a6084f | 2273 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); |
01999873 | 2274 | |
5a893922 LB |
2275 | /* |
2276 | * Add configured unicast addresses to address filter table. | |
2277 | */ | |
2278 | mv643xx_eth_program_unicast_filter(mp->dev); | |
2279 | ||
8a578111 | 2280 | /* |
64da80a2 | 2281 | * Enable the receive queues. |
8a578111 | 2282 | */ |
f7981c1c | 2283 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 | 2284 | struct rx_queue *rxq = mp->rxq + i; |
8a578111 | 2285 | u32 addr; |
1da177e4 | 2286 | |
8a578111 LB |
2287 | addr = (u32)rxq->rx_desc_dma; |
2288 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); | |
37a6084f | 2289 | wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); |
1da177e4 | 2290 | |
8a578111 LB |
2291 | rxq_enable(rxq); |
2292 | } | |
1da177e4 LT |
2293 | } |
2294 | ||
2bcb4b0f LB |
2295 | static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) |
2296 | { | |
2297 | int skb_size; | |
2298 | ||
2299 | /* | |
2300 | * Reserve 2+14 bytes for an ethernet header (the hardware | |
2301 | * automatically prepends 2 bytes of dummy data to each | |
2302 | * received packet), 16 bytes for up to four VLAN tags, and | |
2303 | * 4 bytes for the trailing FCS -- 36 bytes total. | |
2304 | */ | |
2305 | skb_size = mp->dev->mtu + 36; | |
2306 | ||
2307 | /* | |
2308 | * Make sure that the skb size is a multiple of 8 bytes, as | |
2309 | * the lower three bits of the receive descriptor's buffer | |
2310 | * size field are ignored by the hardware. | |
2311 | */ | |
2312 | mp->skb_size = (skb_size + 7) & ~7; | |
7fd96ce4 LB |
2313 | |
2314 | /* | |
2315 | * If NET_SKB_PAD is smaller than a cache line, | |
2316 | * netdev_alloc_skb() will cause skb->data to be misaligned | |
2317 | * to a cache line boundary. If this is the case, include | |
2318 | * some extra space to allow re-aligning the data area. | |
2319 | */ | |
2320 | mp->skb_size += SKB_DMA_REALIGN; | |
2bcb4b0f LB |
2321 | } |
2322 | ||
c9df406f | 2323 | static int mv643xx_eth_open(struct net_device *dev) |
16e03018 | 2324 | { |
e5371493 | 2325 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2326 | int err; |
64da80a2 | 2327 | int i; |
16e03018 | 2328 | |
37a6084f LB |
2329 | wrlp(mp, INT_CAUSE, 0); |
2330 | wrlp(mp, INT_CAUSE_EXT, 0); | |
2331 | rdlp(mp, INT_CAUSE_EXT); | |
c9df406f | 2332 | |
fc32b0e2 | 2333 | err = request_irq(dev->irq, mv643xx_eth_irq, |
2a1867a7 | 2334 | IRQF_SHARED, dev->name, dev); |
c9df406f | 2335 | if (err) { |
fc32b0e2 | 2336 | dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); |
c9df406f | 2337 | return -EAGAIN; |
16e03018 DF |
2338 | } |
2339 | ||
2bcb4b0f LB |
2340 | mv643xx_eth_recalc_skb_size(mp); |
2341 | ||
2257e05c LB |
2342 | napi_enable(&mp->napi); |
2343 | ||
2bcb4b0f LB |
2344 | skb_queue_head_init(&mp->rx_recycle); |
2345 | ||
e0ca8410 SB |
2346 | mp->int_mask = INT_EXT; |
2347 | ||
f7981c1c | 2348 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 LB |
2349 | err = rxq_init(mp, i); |
2350 | if (err) { | |
2351 | while (--i >= 0) | |
f7981c1c | 2352 | rxq_deinit(mp->rxq + i); |
64da80a2 LB |
2353 | goto out; |
2354 | } | |
2355 | ||
1fa38c58 | 2356 | rxq_refill(mp->rxq + i, INT_MAX); |
e0ca8410 | 2357 | mp->int_mask |= INT_RX_0 << i; |
2257e05c LB |
2358 | } |
2359 | ||
1319ebad | 2360 | if (mp->oom) { |
2257e05c LB |
2361 | mp->rx_oom.expires = jiffies + (HZ / 10); |
2362 | add_timer(&mp->rx_oom); | |
64da80a2 | 2363 | } |
8a578111 | 2364 | |
f7981c1c | 2365 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc LB |
2366 | err = txq_init(mp, i); |
2367 | if (err) { | |
2368 | while (--i >= 0) | |
f7981c1c | 2369 | txq_deinit(mp->txq + i); |
3d6b35bc LB |
2370 | goto out_free; |
2371 | } | |
e0ca8410 | 2372 | mp->int_mask |= INT_TX_END_0 << i; |
3d6b35bc | 2373 | } |
16e03018 | 2374 | |
fc32b0e2 | 2375 | port_start(mp); |
16e03018 | 2376 | |
37a6084f | 2377 | wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); |
e0ca8410 | 2378 | wrlp(mp, INT_MASK, mp->int_mask); |
16e03018 | 2379 | |
c9df406f LB |
2380 | return 0; |
2381 | ||
13d64285 | 2382 | |
fc32b0e2 | 2383 | out_free: |
f7981c1c LB |
2384 | for (i = 0; i < mp->rxq_count; i++) |
2385 | rxq_deinit(mp->rxq + i); | |
fc32b0e2 | 2386 | out: |
c9df406f LB |
2387 | free_irq(dev->irq, dev); |
2388 | ||
2389 | return err; | |
16e03018 DF |
2390 | } |
2391 | ||
e5371493 | 2392 | static void port_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2393 | { |
fc32b0e2 | 2394 | unsigned int data; |
64da80a2 | 2395 | int i; |
1da177e4 | 2396 | |
f7981c1c LB |
2397 | for (i = 0; i < mp->rxq_count; i++) |
2398 | rxq_disable(mp->rxq + i); | |
2399 | for (i = 0; i < mp->txq_count; i++) | |
2400 | txq_disable(mp->txq + i); | |
ae9ae064 LB |
2401 | |
2402 | while (1) { | |
37a6084f | 2403 | u32 ps = rdlp(mp, PORT_STATUS); |
ae9ae064 LB |
2404 | |
2405 | if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) | |
2406 | break; | |
13d64285 | 2407 | udelay(10); |
ae9ae064 | 2408 | } |
1da177e4 | 2409 | |
c9df406f | 2410 | /* Reset the Enable bit in the Configuration Register */ |
37a6084f | 2411 | data = rdlp(mp, PORT_SERIAL_CONTROL); |
fc32b0e2 LB |
2412 | data &= ~(SERIAL_PORT_ENABLE | |
2413 | DO_NOT_FORCE_LINK_FAIL | | |
2414 | FORCE_LINK_PASS); | |
37a6084f | 2415 | wrlp(mp, PORT_SERIAL_CONTROL, data); |
1da177e4 LT |
2416 | } |
2417 | ||
c9df406f | 2418 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 | 2419 | { |
e5371493 | 2420 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
64da80a2 | 2421 | int i; |
1da177e4 | 2422 | |
fe65e704 | 2423 | wrlp(mp, INT_MASK_EXT, 0x00000000); |
37a6084f LB |
2424 | wrlp(mp, INT_MASK, 0x00000000); |
2425 | rdlp(mp, INT_MASK); | |
1da177e4 | 2426 | |
c9df406f | 2427 | napi_disable(&mp->napi); |
78fff83b | 2428 | |
2257e05c LB |
2429 | del_timer_sync(&mp->rx_oom); |
2430 | ||
c9df406f | 2431 | netif_carrier_off(dev); |
1da177e4 | 2432 | |
fc32b0e2 LB |
2433 | free_irq(dev->irq, dev); |
2434 | ||
cc9754b3 | 2435 | port_reset(mp); |
8fd89211 | 2436 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 2437 | mib_counters_update(mp); |
57e8f26a | 2438 | del_timer_sync(&mp->mib_counters_timer); |
1da177e4 | 2439 | |
2bcb4b0f LB |
2440 | skb_queue_purge(&mp->rx_recycle); |
2441 | ||
f7981c1c LB |
2442 | for (i = 0; i < mp->rxq_count; i++) |
2443 | rxq_deinit(mp->rxq + i); | |
2444 | for (i = 0; i < mp->txq_count; i++) | |
2445 | txq_deinit(mp->txq + i); | |
1da177e4 | 2446 | |
c9df406f | 2447 | return 0; |
1da177e4 LT |
2448 | } |
2449 | ||
fc32b0e2 | 2450 | static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2451 | { |
e5371493 | 2452 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2453 | |
ed94493f LB |
2454 | if (mp->phy != NULL) |
2455 | return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd); | |
bedfe324 LB |
2456 | |
2457 | return -EOPNOTSUPP; | |
1da177e4 LT |
2458 | } |
2459 | ||
c9df406f | 2460 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2461 | { |
89df5fdc LB |
2462 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
2463 | ||
fc32b0e2 | 2464 | if (new_mtu < 64 || new_mtu > 9500) |
c9df406f | 2465 | return -EINVAL; |
1da177e4 | 2466 | |
c9df406f | 2467 | dev->mtu = new_mtu; |
2bcb4b0f | 2468 | mv643xx_eth_recalc_skb_size(mp); |
89df5fdc LB |
2469 | tx_set_rate(mp, 1000000000, 16777216); |
2470 | ||
c9df406f LB |
2471 | if (!netif_running(dev)) |
2472 | return 0; | |
1da177e4 | 2473 | |
c9df406f LB |
2474 | /* |
2475 | * Stop and then re-open the interface. This will allocate RX | |
2476 | * skbs of the new MTU. | |
2477 | * There is a possible danger that the open will not succeed, | |
fc32b0e2 | 2478 | * due to memory being full. |
c9df406f LB |
2479 | */ |
2480 | mv643xx_eth_stop(dev); | |
2481 | if (mv643xx_eth_open(dev)) { | |
fc32b0e2 LB |
2482 | dev_printk(KERN_ERR, &dev->dev, |
2483 | "fatal error on re-opening device after " | |
2484 | "MTU change\n"); | |
c9df406f LB |
2485 | } |
2486 | ||
2487 | return 0; | |
1da177e4 LT |
2488 | } |
2489 | ||
fc32b0e2 | 2490 | static void tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2491 | { |
fc32b0e2 | 2492 | struct mv643xx_eth_private *mp; |
1da177e4 | 2493 | |
fc32b0e2 LB |
2494 | mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); |
2495 | if (netif_running(mp->dev)) { | |
e5ef1de1 | 2496 | netif_tx_stop_all_queues(mp->dev); |
fc32b0e2 LB |
2497 | port_reset(mp); |
2498 | port_start(mp); | |
e5ef1de1 | 2499 | netif_tx_wake_all_queues(mp->dev); |
fc32b0e2 | 2500 | } |
c9df406f LB |
2501 | } |
2502 | ||
c9df406f | 2503 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2504 | { |
e5371493 | 2505 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2506 | |
fc32b0e2 | 2507 | dev_printk(KERN_INFO, &dev->dev, "tx timeout\n"); |
d0412d96 | 2508 | |
c9df406f | 2509 | schedule_work(&mp->tx_timeout_task); |
1da177e4 LT |
2510 | } |
2511 | ||
c9df406f | 2512 | #ifdef CONFIG_NET_POLL_CONTROLLER |
fc32b0e2 | 2513 | static void mv643xx_eth_netpoll(struct net_device *dev) |
9f8dd319 | 2514 | { |
fc32b0e2 | 2515 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2516 | |
37a6084f LB |
2517 | wrlp(mp, INT_MASK, 0x00000000); |
2518 | rdlp(mp, INT_MASK); | |
c9df406f | 2519 | |
fc32b0e2 | 2520 | mv643xx_eth_irq(dev->irq, dev); |
c9df406f | 2521 | |
e0ca8410 | 2522 | wrlp(mp, INT_MASK, mp->int_mask); |
9f8dd319 | 2523 | } |
c9df406f | 2524 | #endif |
9f8dd319 | 2525 | |
9f8dd319 | 2526 | |
c9df406f | 2527 | /* platform glue ************************************************************/ |
e5371493 LB |
2528 | static void |
2529 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, | |
2530 | struct mbus_dram_target_info *dram) | |
c9df406f | 2531 | { |
cc9754b3 | 2532 | void __iomem *base = msp->base; |
c9df406f LB |
2533 | u32 win_enable; |
2534 | u32 win_protect; | |
2535 | int i; | |
9f8dd319 | 2536 | |
c9df406f LB |
2537 | for (i = 0; i < 6; i++) { |
2538 | writel(0, base + WINDOW_BASE(i)); | |
2539 | writel(0, base + WINDOW_SIZE(i)); | |
2540 | if (i < 4) | |
2541 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2542 | } |
2543 | ||
c9df406f LB |
2544 | win_enable = 0x3f; |
2545 | win_protect = 0; | |
2546 | ||
2547 | for (i = 0; i < dram->num_cs; i++) { | |
2548 | struct mbus_dram_window *cs = dram->cs + i; | |
2549 | ||
2550 | writel((cs->base & 0xffff0000) | | |
2551 | (cs->mbus_attr << 8) | | |
2552 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2553 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2554 | ||
2555 | win_enable &= ~(1 << i); | |
2556 | win_protect |= 3 << (2 * i); | |
2557 | } | |
2558 | ||
2559 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2560 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2561 | } |
2562 | ||
773fc3ee LB |
2563 | static void infer_hw_params(struct mv643xx_eth_shared_private *msp) |
2564 | { | |
2565 | /* | |
2566 | * Check whether we have a 14-bit coal limit field in bits | |
2567 | * [21:8], or a 16-bit coal limit in bits [25,21:7] of the | |
2568 | * SDMA config register. | |
2569 | */ | |
37a6084f LB |
2570 | writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); |
2571 | if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) | |
773fc3ee LB |
2572 | msp->extended_rx_coal_limit = 1; |
2573 | else | |
2574 | msp->extended_rx_coal_limit = 0; | |
1e881592 LB |
2575 | |
2576 | /* | |
457b1d5a LB |
2577 | * Check whether the MAC supports TX rate control, and if |
2578 | * yes, whether its associated registers are in the old or | |
2579 | * the new place. | |
1e881592 | 2580 | */ |
37a6084f LB |
2581 | writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); |
2582 | if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { | |
457b1d5a LB |
2583 | msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; |
2584 | } else { | |
37a6084f LB |
2585 | writel(7, msp->base + 0x0400 + TX_BW_RATE); |
2586 | if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) | |
457b1d5a LB |
2587 | msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; |
2588 | else | |
2589 | msp->tx_bw_control = TX_BW_CONTROL_ABSENT; | |
2590 | } | |
773fc3ee LB |
2591 | } |
2592 | ||
c9df406f | 2593 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2594 | { |
10a9948d | 2595 | static int mv643xx_eth_version_printed; |
c9df406f | 2596 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
e5371493 | 2597 | struct mv643xx_eth_shared_private *msp; |
c9df406f LB |
2598 | struct resource *res; |
2599 | int ret; | |
9f8dd319 | 2600 | |
e5371493 | 2601 | if (!mv643xx_eth_version_printed++) |
7dde154d LB |
2602 | printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet " |
2603 | "driver version %s\n", mv643xx_eth_driver_version); | |
9f8dd319 | 2604 | |
c9df406f LB |
2605 | ret = -EINVAL; |
2606 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2607 | if (res == NULL) | |
2608 | goto out; | |
9f8dd319 | 2609 | |
c9df406f LB |
2610 | ret = -ENOMEM; |
2611 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2612 | if (msp == NULL) | |
2613 | goto out; | |
2614 | memset(msp, 0, sizeof(*msp)); | |
2615 | ||
cc9754b3 LB |
2616 | msp->base = ioremap(res->start, res->end - res->start + 1); |
2617 | if (msp->base == NULL) | |
c9df406f LB |
2618 | goto out_free; |
2619 | ||
ed94493f LB |
2620 | /* |
2621 | * Set up and register SMI bus. | |
2622 | */ | |
2623 | if (pd == NULL || pd->shared_smi == NULL) { | |
298cf9be LB |
2624 | msp->smi_bus = mdiobus_alloc(); |
2625 | if (msp->smi_bus == NULL) | |
ed94493f | 2626 | goto out_unmap; |
298cf9be LB |
2627 | |
2628 | msp->smi_bus->priv = msp; | |
2629 | msp->smi_bus->name = "mv643xx_eth smi"; | |
2630 | msp->smi_bus->read = smi_bus_read; | |
2631 | msp->smi_bus->write = smi_bus_write, | |
2632 | snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); | |
2633 | msp->smi_bus->parent = &pdev->dev; | |
2634 | msp->smi_bus->phy_mask = 0xffffffff; | |
2635 | if (mdiobus_register(msp->smi_bus) < 0) | |
2636 | goto out_free_mii_bus; | |
ed94493f LB |
2637 | msp->smi = msp; |
2638 | } else { | |
fc0eb9f2 | 2639 | msp->smi = platform_get_drvdata(pd->shared_smi); |
ed94493f | 2640 | } |
c9df406f | 2641 | |
45c5d3bc LB |
2642 | msp->err_interrupt = NO_IRQ; |
2643 | init_waitqueue_head(&msp->smi_busy_wait); | |
2644 | ||
2645 | /* | |
2646 | * Check whether the error interrupt is hooked up. | |
2647 | */ | |
2648 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
2649 | if (res != NULL) { | |
2650 | int err; | |
2651 | ||
2652 | err = request_irq(res->start, mv643xx_eth_err_irq, | |
2653 | IRQF_SHARED, "mv643xx_eth", msp); | |
2654 | if (!err) { | |
2655 | writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK); | |
2656 | msp->err_interrupt = res->start; | |
2657 | } | |
2658 | } | |
2659 | ||
c9df406f LB |
2660 | /* |
2661 | * (Re-)program MBUS remapping windows if we are asked to. | |
2662 | */ | |
2663 | if (pd != NULL && pd->dram != NULL) | |
2664 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2665 | ||
fc32b0e2 LB |
2666 | /* |
2667 | * Detect hardware parameters. | |
2668 | */ | |
2669 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
773fc3ee | 2670 | infer_hw_params(msp); |
fc32b0e2 LB |
2671 | |
2672 | platform_set_drvdata(pdev, msp); | |
2673 | ||
c9df406f LB |
2674 | return 0; |
2675 | ||
298cf9be LB |
2676 | out_free_mii_bus: |
2677 | mdiobus_free(msp->smi_bus); | |
ed94493f LB |
2678 | out_unmap: |
2679 | iounmap(msp->base); | |
c9df406f LB |
2680 | out_free: |
2681 | kfree(msp); | |
2682 | out: | |
2683 | return ret; | |
2684 | } | |
2685 | ||
2686 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2687 | { | |
e5371493 | 2688 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
ed94493f | 2689 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
c9df406f | 2690 | |
298cf9be | 2691 | if (pd == NULL || pd->shared_smi == NULL) { |
298cf9be | 2692 | mdiobus_unregister(msp->smi_bus); |
bcb3336c | 2693 | mdiobus_free(msp->smi_bus); |
298cf9be | 2694 | } |
45c5d3bc LB |
2695 | if (msp->err_interrupt != NO_IRQ) |
2696 | free_irq(msp->err_interrupt, msp); | |
cc9754b3 | 2697 | iounmap(msp->base); |
c9df406f LB |
2698 | kfree(msp); |
2699 | ||
2700 | return 0; | |
9f8dd319 DF |
2701 | } |
2702 | ||
c9df406f | 2703 | static struct platform_driver mv643xx_eth_shared_driver = { |
fc32b0e2 LB |
2704 | .probe = mv643xx_eth_shared_probe, |
2705 | .remove = mv643xx_eth_shared_remove, | |
c9df406f | 2706 | .driver = { |
fc32b0e2 | 2707 | .name = MV643XX_ETH_SHARED_NAME, |
c9df406f LB |
2708 | .owner = THIS_MODULE, |
2709 | }, | |
2710 | }; | |
2711 | ||
e5371493 | 2712 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
1da177e4 | 2713 | { |
c9df406f | 2714 | int addr_shift = 5 * mp->port_num; |
fc32b0e2 | 2715 | u32 data; |
1da177e4 | 2716 | |
fc32b0e2 LB |
2717 | data = rdl(mp, PHY_ADDR); |
2718 | data &= ~(0x1f << addr_shift); | |
2719 | data |= (phy_addr & 0x1f) << addr_shift; | |
2720 | wrl(mp, PHY_ADDR, data); | |
1da177e4 LT |
2721 | } |
2722 | ||
e5371493 | 2723 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
1da177e4 | 2724 | { |
fc32b0e2 LB |
2725 | unsigned int data; |
2726 | ||
2727 | data = rdl(mp, PHY_ADDR); | |
2728 | ||
2729 | return (data >> (5 * mp->port_num)) & 0x1f; | |
2730 | } | |
2731 | ||
2732 | static void set_params(struct mv643xx_eth_private *mp, | |
2733 | struct mv643xx_eth_platform_data *pd) | |
2734 | { | |
2735 | struct net_device *dev = mp->dev; | |
2736 | ||
2737 | if (is_valid_ether_addr(pd->mac_addr)) | |
2738 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2739 | else | |
2740 | uc_addr_get(mp, dev->dev_addr); | |
2741 | ||
e7d2f4db | 2742 | mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
fc32b0e2 | 2743 | if (pd->rx_queue_size) |
e7d2f4db | 2744 | mp->rx_ring_size = pd->rx_queue_size; |
fc32b0e2 LB |
2745 | mp->rx_desc_sram_addr = pd->rx_sram_addr; |
2746 | mp->rx_desc_sram_size = pd->rx_sram_size; | |
1da177e4 | 2747 | |
f7981c1c | 2748 | mp->rxq_count = pd->rx_queue_count ? : 1; |
64da80a2 | 2749 | |
e7d2f4db | 2750 | mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
fc32b0e2 | 2751 | if (pd->tx_queue_size) |
e7d2f4db | 2752 | mp->tx_ring_size = pd->tx_queue_size; |
fc32b0e2 LB |
2753 | mp->tx_desc_sram_addr = pd->tx_sram_addr; |
2754 | mp->tx_desc_sram_size = pd->tx_sram_size; | |
3d6b35bc | 2755 | |
f7981c1c | 2756 | mp->txq_count = pd->tx_queue_count ? : 1; |
1da177e4 LT |
2757 | } |
2758 | ||
ed94493f LB |
2759 | static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, |
2760 | int phy_addr) | |
1da177e4 | 2761 | { |
298cf9be | 2762 | struct mii_bus *bus = mp->shared->smi->smi_bus; |
ed94493f LB |
2763 | struct phy_device *phydev; |
2764 | int start; | |
2765 | int num; | |
2766 | int i; | |
45c5d3bc | 2767 | |
ed94493f LB |
2768 | if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { |
2769 | start = phy_addr_get(mp) & 0x1f; | |
2770 | num = 32; | |
2771 | } else { | |
2772 | start = phy_addr & 0x1f; | |
2773 | num = 1; | |
2774 | } | |
45c5d3bc | 2775 | |
ed94493f LB |
2776 | phydev = NULL; |
2777 | for (i = 0; i < num; i++) { | |
2778 | int addr = (start + i) & 0x1f; | |
fc32b0e2 | 2779 | |
ed94493f LB |
2780 | if (bus->phy_map[addr] == NULL) |
2781 | mdiobus_scan(bus, addr); | |
1da177e4 | 2782 | |
ed94493f LB |
2783 | if (phydev == NULL) { |
2784 | phydev = bus->phy_map[addr]; | |
2785 | if (phydev != NULL) | |
2786 | phy_addr_set(mp, addr); | |
2787 | } | |
2788 | } | |
1da177e4 | 2789 | |
ed94493f | 2790 | return phydev; |
1da177e4 LT |
2791 | } |
2792 | ||
ed94493f | 2793 | static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) |
c28a4f89 | 2794 | { |
ed94493f | 2795 | struct phy_device *phy = mp->phy; |
c28a4f89 | 2796 | |
fc32b0e2 LB |
2797 | phy_reset(mp); |
2798 | ||
db1d7bf7 | 2799 | phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII); |
ed94493f LB |
2800 | |
2801 | if (speed == 0) { | |
2802 | phy->autoneg = AUTONEG_ENABLE; | |
2803 | phy->speed = 0; | |
2804 | phy->duplex = 0; | |
2805 | phy->advertising = phy->supported | ADVERTISED_Autoneg; | |
c9df406f | 2806 | } else { |
ed94493f LB |
2807 | phy->autoneg = AUTONEG_DISABLE; |
2808 | phy->advertising = 0; | |
2809 | phy->speed = speed; | |
2810 | phy->duplex = duplex; | |
c9df406f | 2811 | } |
ed94493f | 2812 | phy_start_aneg(phy); |
c28a4f89 JC |
2813 | } |
2814 | ||
81600eea LB |
2815 | static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) |
2816 | { | |
2817 | u32 pscr; | |
2818 | ||
37a6084f | 2819 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2820 | if (pscr & SERIAL_PORT_ENABLE) { |
2821 | pscr &= ~SERIAL_PORT_ENABLE; | |
37a6084f | 2822 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2823 | } |
2824 | ||
2825 | pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; | |
ed94493f | 2826 | if (mp->phy == NULL) { |
81600eea LB |
2827 | pscr |= DISABLE_AUTO_NEG_SPEED_GMII; |
2828 | if (speed == SPEED_1000) | |
2829 | pscr |= SET_GMII_SPEED_TO_1000; | |
2830 | else if (speed == SPEED_100) | |
2831 | pscr |= SET_MII_SPEED_TO_100; | |
2832 | ||
2833 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; | |
2834 | ||
2835 | pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; | |
2836 | if (duplex == DUPLEX_FULL) | |
2837 | pscr |= SET_FULL_DUPLEX_MODE; | |
2838 | } | |
2839 | ||
37a6084f | 2840 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2841 | } |
2842 | ||
ea8a8642 LB |
2843 | static const struct net_device_ops mv643xx_eth_netdev_ops = { |
2844 | .ndo_open = mv643xx_eth_open, | |
2845 | .ndo_stop = mv643xx_eth_stop, | |
2846 | .ndo_start_xmit = mv643xx_eth_xmit, | |
2847 | .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, | |
2848 | .ndo_set_mac_address = mv643xx_eth_set_mac_address, | |
2849 | .ndo_do_ioctl = mv643xx_eth_ioctl, | |
2850 | .ndo_change_mtu = mv643xx_eth_change_mtu, | |
2851 | .ndo_tx_timeout = mv643xx_eth_tx_timeout, | |
2852 | .ndo_get_stats = mv643xx_eth_get_stats, | |
2853 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2854 | .ndo_poll_controller = mv643xx_eth_netpoll, | |
2855 | #endif | |
2856 | }; | |
2857 | ||
c9df406f | 2858 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2859 | { |
c9df406f | 2860 | struct mv643xx_eth_platform_data *pd; |
e5371493 | 2861 | struct mv643xx_eth_private *mp; |
c9df406f | 2862 | struct net_device *dev; |
c9df406f | 2863 | struct resource *res; |
fc32b0e2 | 2864 | int err; |
1da177e4 | 2865 | |
c9df406f LB |
2866 | pd = pdev->dev.platform_data; |
2867 | if (pd == NULL) { | |
fc32b0e2 LB |
2868 | dev_printk(KERN_ERR, &pdev->dev, |
2869 | "no mv643xx_eth_platform_data\n"); | |
c9df406f LB |
2870 | return -ENODEV; |
2871 | } | |
1da177e4 | 2872 | |
c9df406f | 2873 | if (pd->shared == NULL) { |
fc32b0e2 LB |
2874 | dev_printk(KERN_ERR, &pdev->dev, |
2875 | "no mv643xx_eth_platform_data->shared\n"); | |
c9df406f LB |
2876 | return -ENODEV; |
2877 | } | |
8f518703 | 2878 | |
e5ef1de1 | 2879 | dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); |
c9df406f LB |
2880 | if (!dev) |
2881 | return -ENOMEM; | |
1da177e4 | 2882 | |
c9df406f | 2883 | mp = netdev_priv(dev); |
fc32b0e2 LB |
2884 | platform_set_drvdata(pdev, mp); |
2885 | ||
2886 | mp->shared = platform_get_drvdata(pd->shared); | |
37a6084f | 2887 | mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); |
fc32b0e2 LB |
2888 | mp->port_num = pd->port_number; |
2889 | ||
c9df406f | 2890 | mp->dev = dev; |
78fff83b | 2891 | |
fc32b0e2 | 2892 | set_params(mp, pd); |
e5ef1de1 | 2893 | dev->real_num_tx_queues = mp->txq_count; |
fc32b0e2 | 2894 | |
ed94493f LB |
2895 | if (pd->phy_addr != MV643XX_ETH_PHY_NONE) |
2896 | mp->phy = phy_scan(mp, pd->phy_addr); | |
bedfe324 | 2897 | |
6bdf576e | 2898 | if (mp->phy != NULL) |
ed94493f | 2899 | phy_init(mp, pd->speed, pd->duplex); |
6bdf576e LB |
2900 | |
2901 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); | |
ed94493f | 2902 | |
81600eea | 2903 | init_pscr(mp, pd->speed, pd->duplex); |
fc32b0e2 | 2904 | |
4ff3495a LB |
2905 | |
2906 | mib_counters_clear(mp); | |
2907 | ||
2908 | init_timer(&mp->mib_counters_timer); | |
2909 | mp->mib_counters_timer.data = (unsigned long)mp; | |
2910 | mp->mib_counters_timer.function = mib_counters_timer_wrapper; | |
2911 | mp->mib_counters_timer.expires = jiffies + 30 * HZ; | |
2912 | add_timer(&mp->mib_counters_timer); | |
2913 | ||
2914 | spin_lock_init(&mp->mib_counters_lock); | |
2915 | ||
2916 | INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); | |
2917 | ||
2257e05c LB |
2918 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128); |
2919 | ||
2920 | init_timer(&mp->rx_oom); | |
2921 | mp->rx_oom.data = (unsigned long)mp; | |
2922 | mp->rx_oom.function = oom_timer_wrapper; | |
2923 | ||
fc32b0e2 | 2924 | |
c9df406f LB |
2925 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2926 | BUG_ON(!res); | |
2927 | dev->irq = res->start; | |
1da177e4 | 2928 | |
ea8a8642 LB |
2929 | dev->netdev_ops = &mv643xx_eth_netdev_ops; |
2930 | ||
c9df406f LB |
2931 | dev->watchdog_timeo = 2 * HZ; |
2932 | dev->base_addr = 0; | |
1da177e4 | 2933 | |
c9df406f | 2934 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
e32b6617 | 2935 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 | 2936 | |
fc32b0e2 | 2937 | SET_NETDEV_DEV(dev, &pdev->dev); |
8f518703 | 2938 | |
c9df406f | 2939 | if (mp->shared->win_protect) |
fc32b0e2 | 2940 | wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); |
1da177e4 | 2941 | |
a5fe3616 LB |
2942 | netif_carrier_off(dev); |
2943 | ||
b5e86db4 LB |
2944 | wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); |
2945 | ||
4fb0a54a | 2946 | set_rx_coal(mp, 250); |
a5fe3616 LB |
2947 | set_tx_coal(mp, 0); |
2948 | ||
c9df406f LB |
2949 | err = register_netdev(dev); |
2950 | if (err) | |
2951 | goto out; | |
1da177e4 | 2952 | |
e174961c JB |
2953 | dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n", |
2954 | mp->port_num, dev->dev_addr); | |
1da177e4 | 2955 | |
13d64285 | 2956 | if (mp->tx_desc_sram_size > 0) |
fc32b0e2 | 2957 | dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n"); |
1da177e4 | 2958 | |
c9df406f | 2959 | return 0; |
1da177e4 | 2960 | |
c9df406f LB |
2961 | out: |
2962 | free_netdev(dev); | |
1da177e4 | 2963 | |
c9df406f | 2964 | return err; |
1da177e4 LT |
2965 | } |
2966 | ||
c9df406f | 2967 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2968 | { |
fc32b0e2 | 2969 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
1da177e4 | 2970 | |
fc32b0e2 | 2971 | unregister_netdev(mp->dev); |
ed94493f LB |
2972 | if (mp->phy != NULL) |
2973 | phy_detach(mp->phy); | |
c9df406f | 2974 | flush_scheduled_work(); |
fc32b0e2 | 2975 | free_netdev(mp->dev); |
c9df406f | 2976 | |
c9df406f | 2977 | platform_set_drvdata(pdev, NULL); |
fc32b0e2 | 2978 | |
c9df406f | 2979 | return 0; |
1da177e4 LT |
2980 | } |
2981 | ||
c9df406f | 2982 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2983 | { |
fc32b0e2 | 2984 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
d0412d96 | 2985 | |
c9df406f | 2986 | /* Mask all interrupts on ethernet port */ |
37a6084f LB |
2987 | wrlp(mp, INT_MASK, 0); |
2988 | rdlp(mp, INT_MASK); | |
c9df406f | 2989 | |
fc32b0e2 LB |
2990 | if (netif_running(mp->dev)) |
2991 | port_reset(mp); | |
d0412d96 JC |
2992 | } |
2993 | ||
c9df406f | 2994 | static struct platform_driver mv643xx_eth_driver = { |
fc32b0e2 LB |
2995 | .probe = mv643xx_eth_probe, |
2996 | .remove = mv643xx_eth_remove, | |
2997 | .shutdown = mv643xx_eth_shutdown, | |
c9df406f | 2998 | .driver = { |
fc32b0e2 | 2999 | .name = MV643XX_ETH_NAME, |
c9df406f LB |
3000 | .owner = THIS_MODULE, |
3001 | }, | |
3002 | }; | |
3003 | ||
e5371493 | 3004 | static int __init mv643xx_eth_init_module(void) |
d0412d96 | 3005 | { |
c9df406f | 3006 | int rc; |
d0412d96 | 3007 | |
c9df406f LB |
3008 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
3009 | if (!rc) { | |
3010 | rc = platform_driver_register(&mv643xx_eth_driver); | |
3011 | if (rc) | |
3012 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
3013 | } | |
fc32b0e2 | 3014 | |
c9df406f | 3015 | return rc; |
d0412d96 | 3016 | } |
fc32b0e2 | 3017 | module_init(mv643xx_eth_init_module); |
d0412d96 | 3018 | |
e5371493 | 3019 | static void __exit mv643xx_eth_cleanup_module(void) |
d0412d96 | 3020 | { |
c9df406f LB |
3021 | platform_driver_unregister(&mv643xx_eth_driver); |
3022 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 | 3023 | } |
e5371493 | 3024 | module_exit(mv643xx_eth_cleanup_module); |
1da177e4 | 3025 | |
45675bc6 LB |
3026 | MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " |
3027 | "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); | |
c9df406f | 3028 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
fc32b0e2 | 3029 | MODULE_LICENSE("GPL"); |
c9df406f | 3030 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |
fc32b0e2 | 3031 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |