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1da177e4 LT |
1 | #ifndef __MV643XX_ETH_H__ |
2 | #define __MV643XX_ETH_H__ | |
3 | ||
4 | #include <linux/version.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/kernel.h> | |
7 | #include <linux/spinlock.h> | |
8 | #include <linux/workqueue.h> | |
9 | ||
10 | #include <linux/mv643xx.h> | |
11 | ||
12 | #define BIT0 0x00000001 | |
13 | #define BIT1 0x00000002 | |
14 | #define BIT2 0x00000004 | |
15 | #define BIT3 0x00000008 | |
16 | #define BIT4 0x00000010 | |
17 | #define BIT5 0x00000020 | |
18 | #define BIT6 0x00000040 | |
19 | #define BIT7 0x00000080 | |
20 | #define BIT8 0x00000100 | |
21 | #define BIT9 0x00000200 | |
22 | #define BIT10 0x00000400 | |
23 | #define BIT11 0x00000800 | |
24 | #define BIT12 0x00001000 | |
25 | #define BIT13 0x00002000 | |
26 | #define BIT14 0x00004000 | |
27 | #define BIT15 0x00008000 | |
28 | #define BIT16 0x00010000 | |
29 | #define BIT17 0x00020000 | |
30 | #define BIT18 0x00040000 | |
31 | #define BIT19 0x00080000 | |
32 | #define BIT20 0x00100000 | |
33 | #define BIT21 0x00200000 | |
34 | #define BIT22 0x00400000 | |
35 | #define BIT23 0x00800000 | |
36 | #define BIT24 0x01000000 | |
37 | #define BIT25 0x02000000 | |
38 | #define BIT26 0x04000000 | |
39 | #define BIT27 0x08000000 | |
40 | #define BIT28 0x10000000 | |
41 | #define BIT29 0x20000000 | |
42 | #define BIT30 0x40000000 | |
43 | #define BIT31 0x80000000 | |
44 | ||
45 | /* | |
46 | * The first part is the high level driver of the gigE ethernet ports. | |
47 | */ | |
48 | ||
49 | /* Checksum offload for Tx works for most packets, but | |
50 | * fails if previous packet sent did not use hw csum | |
51 | */ | |
52 | #undef MV643XX_CHECKSUM_OFFLOAD_TX | |
53 | #define MV643XX_NAPI | |
54 | #define MV643XX_TX_FAST_REFILL | |
55 | #undef MV643XX_RX_QUEUE_FILL_ON_TASK /* Does not work, yet */ | |
56 | #undef MV643XX_COAL | |
57 | ||
58 | /* | |
59 | * Number of RX / TX descriptors on RX / TX rings. | |
60 | * Note that allocating RX descriptors is done by allocating the RX | |
61 | * ring AND a preallocated RX buffers (skb's) for each descriptor. | |
62 | * The TX descriptors only allocates the TX descriptors ring, | |
63 | * with no pre allocated TX buffers (skb's are allocated by higher layers. | |
64 | */ | |
65 | ||
66 | /* Default TX ring size is 1000 descriptors */ | |
67 | #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000 | |
68 | ||
69 | /* Default RX ring size is 400 descriptors */ | |
70 | #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400 | |
71 | ||
72 | #define MV643XX_TX_COAL 100 | |
73 | #ifdef MV643XX_COAL | |
74 | #define MV643XX_RX_COAL 100 | |
75 | #endif | |
76 | ||
77 | /* | |
78 | * The second part is the low level driver of the gigE ethernet ports. | |
79 | */ | |
80 | ||
81 | /* | |
82 | * Header File for : MV-643xx network interface header | |
83 | * | |
84 | * DESCRIPTION: | |
85 | * This header file contains macros typedefs and function declaration for | |
86 | * the Marvell Gig Bit Ethernet Controller. | |
87 | * | |
88 | * DEPENDENCIES: | |
89 | * None. | |
90 | * | |
91 | */ | |
92 | ||
93 | /* MAC accepet/reject macros */ | |
94 | #define ACCEPT_MAC_ADDR 0 | |
95 | #define REJECT_MAC_ADDR 1 | |
96 | ||
97 | /* Buffer offset from buffer pointer */ | |
98 | #define RX_BUF_OFFSET 0x2 | |
99 | ||
100 | /* Gigabit Ethernet Unit Global Registers */ | |
101 | ||
102 | /* MIB Counters register definitions */ | |
103 | #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 | |
104 | #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 | |
105 | #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 | |
106 | #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc | |
107 | #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 | |
108 | #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 | |
109 | #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 | |
110 | #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c | |
111 | #define ETH_MIB_FRAMES_64_OCTETS 0x20 | |
112 | #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 | |
113 | #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 | |
114 | #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c | |
115 | #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 | |
116 | #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 | |
117 | #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 | |
118 | #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c | |
119 | #define ETH_MIB_GOOD_FRAMES_SENT 0x40 | |
120 | #define ETH_MIB_EXCESSIVE_COLLISION 0x44 | |
121 | #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 | |
122 | #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c | |
123 | #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 | |
124 | #define ETH_MIB_FC_SENT 0x54 | |
125 | #define ETH_MIB_GOOD_FC_RECEIVED 0x58 | |
126 | #define ETH_MIB_BAD_FC_RECEIVED 0x5c | |
127 | #define ETH_MIB_UNDERSIZE_RECEIVED 0x60 | |
128 | #define ETH_MIB_FRAGMENTS_RECEIVED 0x64 | |
129 | #define ETH_MIB_OVERSIZE_RECEIVED 0x68 | |
130 | #define ETH_MIB_JABBER_RECEIVED 0x6c | |
131 | #define ETH_MIB_MAC_RECEIVE_ERROR 0x70 | |
132 | #define ETH_MIB_BAD_CRC_EVENT 0x74 | |
133 | #define ETH_MIB_COLLISION 0x78 | |
134 | #define ETH_MIB_LATE_COLLISION 0x7c | |
135 | ||
136 | /* Port serial status reg (PSR) */ | |
137 | #define ETH_INTERFACE_GMII_MII 0 | |
138 | #define ETH_INTERFACE_PCM BIT0 | |
139 | #define ETH_LINK_IS_DOWN 0 | |
140 | #define ETH_LINK_IS_UP BIT1 | |
141 | #define ETH_PORT_AT_HALF_DUPLEX 0 | |
142 | #define ETH_PORT_AT_FULL_DUPLEX BIT2 | |
143 | #define ETH_RX_FLOW_CTRL_DISABLED 0 | |
144 | #define ETH_RX_FLOW_CTRL_ENBALED BIT3 | |
145 | #define ETH_GMII_SPEED_100_10 0 | |
146 | #define ETH_GMII_SPEED_1000 BIT4 | |
147 | #define ETH_MII_SPEED_10 0 | |
148 | #define ETH_MII_SPEED_100 BIT5 | |
149 | #define ETH_NO_TX 0 | |
150 | #define ETH_TX_IN_PROGRESS BIT7 | |
151 | #define ETH_BYPASS_NO_ACTIVE 0 | |
152 | #define ETH_BYPASS_ACTIVE BIT8 | |
153 | #define ETH_PORT_NOT_AT_PARTITION_STATE 0 | |
154 | #define ETH_PORT_AT_PARTITION_STATE BIT9 | |
155 | #define ETH_PORT_TX_FIFO_NOT_EMPTY 0 | |
156 | #define ETH_PORT_TX_FIFO_EMPTY BIT10 | |
157 | ||
158 | #define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) | |
159 | #define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 | |
160 | #define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) | |
161 | #define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) | |
162 | #define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) | |
163 | ||
164 | /* SMI reg */ | |
165 | #define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ | |
166 | #define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ | |
167 | #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ | |
168 | #define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ | |
169 | ||
170 | /* SDMA command status fields macros */ | |
171 | ||
172 | /* Tx & Rx descriptors status */ | |
173 | #define ETH_ERROR_SUMMARY (BIT0) | |
174 | ||
175 | /* Tx & Rx descriptors command */ | |
176 | #define ETH_BUFFER_OWNED_BY_DMA (BIT31) | |
177 | ||
178 | /* Tx descriptors status */ | |
179 | #define ETH_LC_ERROR (0 ) | |
180 | #define ETH_UR_ERROR (BIT1 ) | |
181 | #define ETH_RL_ERROR (BIT2 ) | |
182 | #define ETH_LLC_SNAP_FORMAT (BIT9 ) | |
183 | ||
184 | /* Rx descriptors status */ | |
185 | #define ETH_CRC_ERROR (0 ) | |
186 | #define ETH_OVERRUN_ERROR (BIT1 ) | |
187 | #define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) | |
188 | #define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) | |
189 | #define ETH_VLAN_TAGGED (BIT19) | |
190 | #define ETH_BPDU_FRAME (BIT20) | |
191 | #define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) | |
192 | #define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) | |
193 | #define ETH_OTHER_FRAME_TYPE (BIT22) | |
194 | #define ETH_LAYER_2_IS_ETH_V_2 (BIT23) | |
195 | #define ETH_FRAME_TYPE_IP_V_4 (BIT24) | |
196 | #define ETH_FRAME_HEADER_OK (BIT25) | |
197 | #define ETH_RX_LAST_DESC (BIT26) | |
198 | #define ETH_RX_FIRST_DESC (BIT27) | |
199 | #define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) | |
200 | #define ETH_RX_ENABLE_INTERRUPT (BIT29) | |
201 | #define ETH_LAYER_4_CHECKSUM_OK (BIT30) | |
202 | ||
203 | /* Rx descriptors byte count */ | |
204 | #define ETH_FRAME_FRAGMENTED (BIT2) | |
205 | ||
206 | /* Tx descriptors command */ | |
207 | #define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) | |
208 | #define ETH_FRAME_SET_TO_VLAN (BIT15) | |
209 | #define ETH_TCP_FRAME (0 ) | |
210 | #define ETH_UDP_FRAME (BIT16) | |
211 | #define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) | |
212 | #define ETH_GEN_IP_V_4_CHECKSUM (BIT18) | |
213 | #define ETH_ZERO_PADDING (BIT19) | |
214 | #define ETH_TX_LAST_DESC (BIT20) | |
215 | #define ETH_TX_FIRST_DESC (BIT21) | |
216 | #define ETH_GEN_CRC (BIT22) | |
217 | #define ETH_TX_ENABLE_INTERRUPT (BIT23) | |
218 | #define ETH_AUTO_MODE (BIT30) | |
219 | ||
220 | /* typedefs */ | |
221 | ||
222 | typedef enum _eth_func_ret_status { | |
223 | ETH_OK, /* Returned as expected. */ | |
224 | ETH_ERROR, /* Fundamental error. */ | |
225 | ETH_RETRY, /* Could not process request. Try later.*/ | |
226 | ETH_END_OF_JOB, /* Ring has nothing to process. */ | |
227 | ETH_QUEUE_FULL, /* Ring resource error. */ | |
228 | ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ | |
229 | } ETH_FUNC_RET_STATUS; | |
230 | ||
231 | typedef enum _eth_target { | |
232 | ETH_TARGET_DRAM, | |
233 | ETH_TARGET_DEVICE, | |
234 | ETH_TARGET_CBS, | |
235 | ETH_TARGET_PCI0, | |
236 | ETH_TARGET_PCI1 | |
237 | } ETH_TARGET; | |
238 | ||
239 | /* These are for big-endian machines. Little endian needs different | |
240 | * definitions. | |
241 | */ | |
242 | #if defined(__BIG_ENDIAN) | |
243 | struct eth_rx_desc { | |
244 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
245 | u16 buf_size; /* Buffer size */ | |
246 | u32 cmd_sts; /* Descriptor command status */ | |
247 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
248 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
249 | }; | |
250 | ||
251 | struct eth_tx_desc { | |
252 | u16 byte_cnt; /* buffer byte count */ | |
253 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
254 | u32 cmd_sts; /* Command/status field */ | |
255 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
256 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
257 | }; | |
258 | ||
259 | #elif defined(__LITTLE_ENDIAN) | |
260 | struct eth_rx_desc { | |
261 | u32 cmd_sts; /* Descriptor command status */ | |
262 | u16 buf_size; /* Buffer size */ | |
263 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
264 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
265 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
266 | }; | |
267 | ||
268 | struct eth_tx_desc { | |
269 | u32 cmd_sts; /* Command/status field */ | |
270 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
271 | u16 byte_cnt; /* buffer byte count */ | |
272 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
273 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
274 | }; | |
275 | #else | |
276 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
277 | #endif | |
278 | ||
279 | /* Unified struct for Rx and Tx operations. The user is not required to */ | |
280 | /* be familier with neither Tx nor Rx descriptors. */ | |
281 | struct pkt_info { | |
282 | unsigned short byte_cnt; /* Descriptor buffer byte count */ | |
283 | unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ | |
284 | unsigned int cmd_sts; /* Descriptor command status */ | |
285 | dma_addr_t buf_ptr; /* Descriptor buffer pointer */ | |
286 | struct sk_buff *return_info; /* User resource return information */ | |
287 | }; | |
288 | ||
289 | /* Ethernet port specific infomation */ | |
290 | ||
291 | struct mv643xx_mib_counters { | |
292 | u64 good_octets_received; | |
293 | u32 bad_octets_received; | |
294 | u32 internal_mac_transmit_err; | |
295 | u32 good_frames_received; | |
296 | u32 bad_frames_received; | |
297 | u32 broadcast_frames_received; | |
298 | u32 multicast_frames_received; | |
299 | u32 frames_64_octets; | |
300 | u32 frames_65_to_127_octets; | |
301 | u32 frames_128_to_255_octets; | |
302 | u32 frames_256_to_511_octets; | |
303 | u32 frames_512_to_1023_octets; | |
304 | u32 frames_1024_to_max_octets; | |
305 | u64 good_octets_sent; | |
306 | u32 good_frames_sent; | |
307 | u32 excessive_collision; | |
308 | u32 multicast_frames_sent; | |
309 | u32 broadcast_frames_sent; | |
310 | u32 unrec_mac_control_received; | |
311 | u32 fc_sent; | |
312 | u32 good_fc_received; | |
313 | u32 bad_fc_received; | |
314 | u32 undersize_received; | |
315 | u32 fragments_received; | |
316 | u32 oversize_received; | |
317 | u32 jabber_received; | |
318 | u32 mac_receive_error; | |
319 | u32 bad_crc_event; | |
320 | u32 collision; | |
321 | u32 late_collision; | |
322 | }; | |
323 | ||
324 | struct mv643xx_private { | |
325 | int port_num; /* User Ethernet port number */ | |
326 | u8 port_mac_addr[6]; /* User defined port MAC address.*/ | |
327 | u32 port_config; /* User port configuration value*/ | |
328 | u32 port_config_extend; /* User port config extend value*/ | |
329 | u32 port_sdma_config; /* User port SDMA config value */ | |
330 | u32 port_serial_control; /* User port serial control value */ | |
331 | u32 port_tx_queue_command; /* Port active Tx queues summary*/ | |
332 | u32 port_rx_queue_command; /* Port active Rx queues summary*/ | |
333 | ||
334 | u32 rx_sram_addr; /* Base address of rx sram area */ | |
335 | u32 rx_sram_size; /* Size of rx sram area */ | |
336 | u32 tx_sram_addr; /* Base address of tx sram area */ | |
337 | u32 tx_sram_size; /* Size of tx sram area */ | |
338 | ||
339 | int rx_resource_err; /* Rx ring resource error flag */ | |
340 | int tx_resource_err; /* Tx ring resource error flag */ | |
341 | ||
342 | /* Tx/Rx rings managment indexes fields. For driver use */ | |
343 | ||
344 | /* Next available and first returning Rx resource */ | |
345 | int rx_curr_desc_q, rx_used_desc_q; | |
346 | ||
347 | /* Next available and first returning Tx resource */ | |
348 | int tx_curr_desc_q, tx_used_desc_q; | |
349 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
350 | int tx_first_desc_q; | |
351 | u32 tx_first_command; | |
352 | #endif | |
353 | ||
354 | #ifdef MV643XX_TX_FAST_REFILL | |
355 | u32 tx_clean_threshold; | |
356 | #endif | |
357 | ||
358 | struct eth_rx_desc *p_rx_desc_area; | |
359 | dma_addr_t rx_desc_dma; | |
360 | unsigned int rx_desc_area_size; | |
361 | struct sk_buff **rx_skb; | |
362 | ||
363 | struct eth_tx_desc *p_tx_desc_area; | |
364 | dma_addr_t tx_desc_dma; | |
365 | unsigned int tx_desc_area_size; | |
366 | struct sk_buff **tx_skb; | |
367 | ||
368 | struct work_struct tx_timeout_task; | |
369 | ||
370 | /* | |
371 | * Former struct mv643xx_eth_priv members start here | |
372 | */ | |
373 | struct net_device_stats stats; | |
374 | struct mv643xx_mib_counters mib_counters; | |
375 | spinlock_t lock; | |
376 | /* Size of Tx Ring per queue */ | |
377 | unsigned int tx_ring_size; | |
378 | /* Ammont of SKBs outstanding on Tx queue */ | |
379 | unsigned int tx_ring_skbs; | |
380 | /* Size of Rx Ring per queue */ | |
381 | unsigned int rx_ring_size; | |
382 | /* Ammount of SKBs allocated to Rx Ring per queue */ | |
383 | unsigned int rx_ring_skbs; | |
384 | ||
385 | /* | |
386 | * rx_task used to fill RX ring out of bottom half context | |
387 | */ | |
388 | struct work_struct rx_task; | |
389 | ||
390 | /* | |
391 | * Used in case RX Ring is empty, which can be caused when | |
392 | * system does not have resources (skb's) | |
393 | */ | |
394 | struct timer_list timeout; | |
395 | long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES))); | |
396 | unsigned rx_timer_flag; | |
397 | ||
398 | u32 rx_int_coal; | |
399 | u32 tx_int_coal; | |
400 | }; | |
401 | ||
402 | /* ethernet.h API list */ | |
403 | ||
404 | /* Port operation control routines */ | |
405 | static void eth_port_init(struct mv643xx_private *mp); | |
406 | static void eth_port_reset(unsigned int eth_port_num); | |
407 | static void eth_port_start(struct mv643xx_private *mp); | |
408 | ||
409 | static void ethernet_set_config_reg(unsigned int eth_port_num, | |
410 | unsigned int value); | |
411 | static unsigned int ethernet_get_config_reg(unsigned int eth_port_num); | |
412 | ||
413 | /* Port MAC address routines */ | |
414 | static void eth_port_uc_addr_set(unsigned int eth_port_num, | |
415 | unsigned char *p_addr); | |
416 | ||
417 | /* PHY and MIB routines */ | |
418 | static void ethernet_phy_reset(unsigned int eth_port_num); | |
419 | ||
420 | static void eth_port_write_smi_reg(unsigned int eth_port_num, | |
421 | unsigned int phy_reg, unsigned int value); | |
422 | ||
423 | static void eth_port_read_smi_reg(unsigned int eth_port_num, | |
424 | unsigned int phy_reg, unsigned int *value); | |
425 | ||
426 | static void eth_clear_mib_counters(unsigned int eth_port_num); | |
427 | ||
428 | /* Port data flow control routines */ | |
429 | static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp, | |
430 | struct pkt_info *p_pkt_info); | |
431 | static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp, | |
432 | struct pkt_info *p_pkt_info); | |
433 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, | |
434 | struct pkt_info *p_pkt_info); | |
435 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, | |
436 | struct pkt_info *p_pkt_info); | |
437 | ||
438 | #endif /* __MV643XX_ETH_H__ */ |