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myri10ge: update firmware headers
[mirror_ubuntu-jammy-kernel.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
0da34b6d
BG		 52#include <linux/ip.h>
53#include <linux/inet.h>
54#include <linux/in.h>
55#include <linux/ethtool.h>
56#include <linux/firmware.h>
57#include <linux/delay.h>
58#include <linux/version.h>
59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
e0d7c526 78#define MYRI10GE_VERSION_STR "1.3.2-1.287"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
0da34b6d 105struct myri10ge_rx_buffer_state {
dd50f336
BG		 106 struct page *page;
107 int page_offset;
0da34b6d
BG		 108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110};
111
112struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117};
118
119struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123};
124
125struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 130 struct page *page;
131 dma_addr_t bus;
132 int page_offset;
0da34b6d 133 int cnt;
dd50f336 134 int fill_cnt;
0da34b6d
BG		 135 int alloc_fail;
136 int mask; /* number of rx slots -1 */
dd50f336 137 int watchdog_needed;
0da34b6d
BG		 138};
139
140struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
144 char *req_bytes;
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int boundary; /* boundary transmits cannot cross */
148 int req ____cacheline_aligned; /* transmit slots submitted */
149 int pkt_start; /* packets started */
150 int done ____cacheline_aligned; /* transmit slots completed */
151 int pkt_done; /* packets completed */
152};
153
154struct myri10ge_rx_done {
155 struct mcp_slot *entry;
156 dma_addr_t bus;
157 int cnt;
158 int idx;
1e6e9342
AG		 159 struct net_lro_mgr lro_mgr;
160 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 161};
162
163struct myri10ge_priv {
164 int running; /* running? */
165 int csum_flag; /* rx_csums? */
166 struct myri10ge_tx_buf tx; /* transmit ring */
167 struct myri10ge_rx_buf rx_small;
168 struct myri10ge_rx_buf rx_big;
169 struct myri10ge_rx_done rx_done;
170 int small_bytes;
dd50f336 171 int big_bytes;
0da34b6d 172 struct net_device *dev;
bea3348e 173 struct napi_struct napi;
0da34b6d
BG		 174 struct net_device_stats stats;
175 u8 __iomem *sram;
176 int sram_size;
177 unsigned long board_span;
178 unsigned long iomem_base;
40f6cff5
AV		 179 __be32 __iomem *irq_claim;
180 __be32 __iomem *irq_deassert;
0da34b6d
BG		 181 char *mac_addr_string;
182 struct mcp_cmd_response *cmd;
183 dma_addr_t cmd_bus;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 struct pci_dev *pdev;
187 int msi_enabled;
66341fff 188 u32 link_state;
0da34b6d
BG		 189 unsigned int rdma_tags_available;
190 int intr_coal_delay;
40f6cff5 191 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 192 int mtrr;
276e26c3 193 int wc_enabled;
0da34b6d
BG		 194 int wake_queue;
195 int stop_queue;
196 int down_cnt;
197 wait_queue_head_t down_wq;
198 struct work_struct watchdog_work;
199 struct timer_list watchdog_timer;
200 int watchdog_tx_done;
c54772e7 201 int watchdog_tx_req;
626fda94 202 int watchdog_pause;
0da34b6d
BG		 203 int watchdog_resets;
204 int tx_linearized;
205 int pause;
206 char *fw_name;
207 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
208 char fw_version[128];
9dc6f0e7
BG		 209 int fw_ver_major;
210 int fw_ver_minor;
211 int fw_ver_tiny;
212 int adopted_rx_filter_bug;
0da34b6d
BG		 213 u8 mac_addr[6]; /* eeprom mac address */
214 unsigned long serial_number;
215 int vendor_specific_offset;
85a7ea1b 216 int fw_multicast_support;
4f93fde0
BG		 217 unsigned long features;
218 u32 max_tso6;
0da34b6d
BG		 219 u32 read_dma;
220 u32 write_dma;
221 u32 read_write_dma;
c58ac5ca
BG		 222 u32 link_changes;
223 u32 msg_enable;
0da34b6d
BG		 224};
225
226static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
227static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
228
229static char *myri10ge_fw_name = NULL;
230module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
231MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
232
233static int myri10ge_ecrc_enable = 1;
234module_param(myri10ge_ecrc_enable, int, S_IRUGO);
235MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
236
237static int myri10ge_max_intr_slots = 1024;
238module_param(myri10ge_max_intr_slots, int, S_IRUGO);
239MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
240
241static int myri10ge_small_bytes = -1; /* -1 == auto */
242module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
243MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
244
245static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 246module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
0da34b6d
BG		 247MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
248
f761fae1 249static int myri10ge_intr_coal_delay = 75;
0da34b6d
BG		 250module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
251MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
252
253static int myri10ge_flow_control = 1;
254module_param(myri10ge_flow_control, int, S_IRUGO);
255MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
256
257static int myri10ge_deassert_wait = 1;
258module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
259MODULE_PARM_DESC(myri10ge_deassert_wait,
260 "Wait when deasserting legacy interrupts\n");
261
262static int myri10ge_force_firmware = 0;
263module_param(myri10ge_force_firmware, int, S_IRUGO);
264MODULE_PARM_DESC(myri10ge_force_firmware,
265 "Force firmware to assume aligned completions\n");
266
0da34b6d
BG		 267static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
268module_param(myri10ge_initial_mtu, int, S_IRUGO);
269MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
270
271static int myri10ge_napi_weight = 64;
272module_param(myri10ge_napi_weight, int, S_IRUGO);
273MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
274
275static int myri10ge_watchdog_timeout = 1;
276module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
277MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
278
279static int myri10ge_max_irq_loops = 1048576;
280module_param(myri10ge_max_irq_loops, int, S_IRUGO);
281MODULE_PARM_DESC(myri10ge_max_irq_loops,
282 "Set stuck legacy IRQ detection threshold\n");
283
c58ac5ca
BG		 284#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
285
286static int myri10ge_debug = -1; /* defaults above */
287module_param(myri10ge_debug, int, 0);
288MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
289
1e6e9342
AG		 290static int myri10ge_lro = 1;
291module_param(myri10ge_lro, int, S_IRUGO);
292MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload\n");
293
294static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
295module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
296MODULE_PARM_DESC(myri10ge_lro, "Number of LRO packets to be aggregated\n");
297
dd50f336
BG		 298static int myri10ge_fill_thresh = 256;
299module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
300MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
301
f181137f
BG		 302static int myri10ge_reset_recover = 1;
303
f761fae1 304static int myri10ge_wcfifo = 0;
6ebc087a
BG		 305module_param(myri10ge_wcfifo, int, S_IRUGO);
306MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
307
0da34b6d
BG		 308#define MYRI10GE_FW_OFFSET 1024*1024
309#define MYRI10GE_HIGHPART_TO_U32(X) \
310(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
311#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
312
313#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
314
2f76216f 315static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 316static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 317
6250223e 318static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 319{
6250223e 320 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 321}
322
0da34b6d
BG		 323static int
324myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
325 struct myri10ge_cmd *data, int atomic)
326{
327 struct mcp_cmd *buf;
328 char buf_bytes[sizeof(*buf) + 8];
329 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 330 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 331 u32 dma_low, dma_high, result, value;
332 int sleep_total = 0;
333
334 /* ensure buf is aligned to 8 bytes */
335 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
336
337 buf->data0 = htonl(data->data0);
338 buf->data1 = htonl(data->data1);
339 buf->data2 = htonl(data->data2);
340 buf->cmd = htonl(cmd);
341 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
342 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
343
344 buf->response_addr.low = htonl(dma_low);
345 buf->response_addr.high = htonl(dma_high);
40f6cff5 346 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 347 mb();
348 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
349
350 /* wait up to 15ms. Longest command is the DMA benchmark,
351 * which is capped at 5ms, but runs from a timeout handler
352 * that runs every 7.8ms. So a 15ms timeout leaves us with
353 * a 2.2ms margin
354 */
355 if (atomic) {
356 /* if atomic is set, do not sleep,
357 * and try to get the completion quickly
358 * (1ms will be enough for those commands) */
359 for (sleep_total = 0;
360 sleep_total < 1000
40f6cff5 361 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 362 sleep_total += 10)
363 udelay(10);
364 } else {
365 /* use msleep for most command */
366 for (sleep_total = 0;
367 sleep_total < 15
40f6cff5 368 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 369 sleep_total++)
370 msleep(1);
371 }
372
373 result = ntohl(response->result);
374 value = ntohl(response->data);
375 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
376 if (result == 0) {
377 data->data0 = value;
378 return 0;
85a7ea1b
BG		 379 } else if (result == MXGEFW_CMD_UNKNOWN) {
380 return -ENOSYS;
5443e9ea
BG		 381 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
382 return -E2BIG;
0da34b6d
BG		 383 } else {
384 dev_err(&mgp->pdev->dev,
385 "command %d failed, result = %d\n",
386 cmd, result);
387 return -ENXIO;
388 }
389 }
390
391 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
392 cmd, result);
393 return -EAGAIN;
394}
395
396/*
397 * The eeprom strings on the lanaiX have the format
398 * SN=x\0
399 * MAC=x:x:x:x:x:x\0
400 * PT:ddd mmm xx xx:xx:xx xx\0
401 * PV:ddd mmm xx xx:xx:xx xx\0
402 */
403static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
404{
405 char *ptr, *limit;
406 int i;
407
408 ptr = mgp->eeprom_strings;
409 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
410
411 while (*ptr != '\0' && ptr < limit) {
412 if (memcmp(ptr, "MAC=", 4) == 0) {
413 ptr += 4;
414 mgp->mac_addr_string = ptr;
415 for (i = 0; i < 6; i++) {
416 if ((ptr + 2) > limit)
417 goto abort;
418 mgp->mac_addr[i] =
419 simple_strtoul(ptr, &ptr, 16);
420 ptr += 1;
421 }
422 }
423 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
424 ptr += 3;
425 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
426 }
427 while (ptr < limit && *ptr++) ;
428 }
429
430 return 0;
431
432abort:
433 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
434 return -ENXIO;
435}
436
437/*
438 * Enable or disable periodic RDMAs from the host to make certain
439 * chipsets resend dropped PCIe messages
440 */
441
442static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
443{
444 char __iomem *submit;
40f6cff5 445 __be32 buf[16];
0da34b6d
BG		 446 u32 dma_low, dma_high;
447 int i;
448
449 /* clear confirmation addr */
450 mgp->cmd->data = 0;
451 mb();
452
453 /* send a rdma command to the PCIe engine, and wait for the
454 * response in the confirmation address. The firmware should
455 * write a -1 there to indicate it is alive and well
456 */
457 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
458 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
459
460 buf[0] = htonl(dma_high); /* confirm addr MSW */
461 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 462 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 463 buf[3] = htonl(dma_high); /* dummy addr MSW */
464 buf[4] = htonl(dma_low); /* dummy addr LSW */
465 buf[5] = htonl(enable); /* enable? */
466
e700f9f4 467 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 468
469 myri10ge_pio_copy(submit, &buf, sizeof(buf));
470 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
471 msleep(1);
472 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
473 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
474 (enable ? "enable" : "disable"));
475}
476
477static int
478myri10ge_validate_firmware(struct myri10ge_priv *mgp,
479 struct mcp_gen_header *hdr)
480{
481 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 482
483 /* check firmware type */
484 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
485 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
486 return -EINVAL;
487 }
488
489 /* save firmware version for ethtool */
490 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
491
9dc6f0e7
BG		 492 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
493 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 494
9dc6f0e7
BG		 495 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
496 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 497 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
498 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
499 MXGEFW_VERSION_MINOR);
500 return -EINVAL;
501 }
502 return 0;
503}
504
505static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
506{
507 unsigned crc, reread_crc;
508 const struct firmware *fw;
509 struct device *dev = &mgp->pdev->dev;
510 struct mcp_gen_header *hdr;
511 size_t hdr_offset;
512 int status;
e454358a 513 unsigned i;
0da34b6d
BG		 514
515 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
516 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
517 mgp->fw_name);
518 status = -EINVAL;
519 goto abort_with_nothing;
520 }
521
522 /* check size */
523
524 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
525 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
526 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
527 status = -EINVAL;
528 goto abort_with_fw;
529 }
530
531 /* check id */
40f6cff5 532 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 533 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
534 dev_err(dev, "Bad firmware file\n");
535 status = -EINVAL;
536 goto abort_with_fw;
537 }
538 hdr = (void *)(fw->data + hdr_offset);
539
540 status = myri10ge_validate_firmware(mgp, hdr);
541 if (status != 0)
542 goto abort_with_fw;
543
544 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 545 for (i = 0; i < fw->size; i += 256) {
546 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
547 fw->data + i,
548 min(256U, (unsigned)(fw->size - i)));
549 mb();
550 readb(mgp->sram);
b10c0668 551 }
0da34b6d
BG		 552 /* corruption checking is good for parity recovery and buggy chipset */
553 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
554 reread_crc = crc32(~0, fw->data, fw->size);
555 if (crc != reread_crc) {
556 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
557 (unsigned)fw->size, reread_crc, crc);
558 status = -EIO;
559 goto abort_with_fw;
560 }
561 *size = (u32) fw->size;
562
563abort_with_fw:
564 release_firmware(fw);
565
566abort_with_nothing:
567 return status;
568}
569
570static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
571{
572 struct mcp_gen_header *hdr;
573 struct device *dev = &mgp->pdev->dev;
574 const size_t bytes = sizeof(struct mcp_gen_header);
575 size_t hdr_offset;
576 int status;
577
578 /* find running firmware header */
66341fff 579 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 580
581 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
582 dev_err(dev, "Running firmware has bad header offset (%d)\n",
583 (int)hdr_offset);
584 return -EIO;
585 }
586
587 /* copy header of running firmware from SRAM to host memory to
588 * validate firmware */
589 hdr = kmalloc(bytes, GFP_KERNEL);
590 if (hdr == NULL) {
591 dev_err(dev, "could not malloc firmware hdr\n");
592 return -ENOMEM;
593 }
594 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
595 status = myri10ge_validate_firmware(mgp, hdr);
596 kfree(hdr);
9dc6f0e7
BG		 597
598 /* check to see if adopted firmware has bug where adopting
599 * it will cause broadcasts to be filtered unless the NIC
600 * is kept in ALLMULTI mode */
601 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
602 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
603 mgp->adopted_rx_filter_bug = 1;
604 dev_warn(dev, "Adopting fw %d.%d.%d: "
605 "working around rx filter bug\n",
606 mgp->fw_ver_major, mgp->fw_ver_minor,
607 mgp->fw_ver_tiny);
608 }
0da34b6d
BG		 609 return status;
610}
611
612static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
613{
614 char __iomem *submit;
40f6cff5 615 __be32 buf[16];
0da34b6d
BG		 616 u32 dma_low, dma_high, size;
617 int status, i;
4f93fde0 618 struct myri10ge_cmd cmd;
0da34b6d 619
b10c0668 620 size = 0;
0da34b6d
BG		 621 status = myri10ge_load_hotplug_firmware(mgp, &size);
622 if (status) {
623 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
624
625 /* Do not attempt to adopt firmware if there
626 * was a bad crc */
627 if (status == -EIO)
628 return status;
629
630 status = myri10ge_adopt_running_firmware(mgp);
631 if (status != 0) {
632 dev_err(&mgp->pdev->dev,
633 "failed to adopt running firmware\n");
634 return status;
635 }
636 dev_info(&mgp->pdev->dev,
637 "Successfully adopted running firmware\n");
638 if (mgp->tx.boundary == 4096) {
639 dev_warn(&mgp->pdev->dev,
640 "Using firmware currently running on NIC"
641 ". For optimal\n");
642 dev_warn(&mgp->pdev->dev,
643 "performance consider loading optimized "
644 "firmware\n");
645 dev_warn(&mgp->pdev->dev, "via hotplug\n");
646 }
647
648 mgp->fw_name = "adopted";
649 mgp->tx.boundary = 2048;
650 return status;
651 }
652
653 /* clear confirmation addr */
654 mgp->cmd->data = 0;
655 mb();
656
657 /* send a reload command to the bootstrap MCP, and wait for the
658 * response in the confirmation address. The firmware should
659 * write a -1 there to indicate it is alive and well
660 */
661 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
662 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
663
664 buf[0] = htonl(dma_high); /* confirm addr MSW */
665 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 666 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 667
668 /* FIX: All newest firmware should un-protect the bottom of
669 * the sram before handoff. However, the very first interfaces
670 * do not. Therefore the handoff copy must skip the first 8 bytes
671 */
672 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
673 buf[4] = htonl(size - 8); /* length of code */
674 buf[5] = htonl(8); /* where to copy to */
675 buf[6] = htonl(0); /* where to jump to */
676
e700f9f4 677 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 678
679 myri10ge_pio_copy(submit, &buf, sizeof(buf));
680 mb();
681 msleep(1);
682 mb();
683 i = 0;
684 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
685 msleep(1);
686 i++;
687 }
688 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
689 dev_err(&mgp->pdev->dev, "handoff failed\n");
690 return -ENXIO;
691 }
692 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 693 myri10ge_dummy_rdma(mgp, 1);
0da34b6d 694
4f93fde0
BG		 695 /* probe for IPv6 TSO support */
696 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
697 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
698 &cmd, 0);
699 if (status == 0) {
700 mgp->max_tso6 = cmd.data0;
701 mgp->features |= NETIF_F_TSO6;
702 }
0da34b6d
BG		 703 return 0;
704}
705
706static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
707{
708 struct myri10ge_cmd cmd;
709 int status;
710
711 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
712 | (addr[2] << 8) | addr[3]);
713
714 cmd.data1 = ((addr[4] << 8) | (addr[5]));
715
716 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
717 return status;
718}
719
720static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
721{
722 struct myri10ge_cmd cmd;
723 int status, ctl;
724
725 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
726 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
727
728 if (status) {
729 printk(KERN_ERR
730 "myri10ge: %s: Failed to set flow control mode\n",
731 mgp->dev->name);
732 return status;
733 }
734 mgp->pause = pause;
735 return 0;
736}
737
738static void
739myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
740{
741 struct myri10ge_cmd cmd;
742 int status, ctl;
743
744 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
745 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
746 if (status)
747 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
748 mgp->dev->name);
749}
750
0d6ac257 751static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 752{
753 struct myri10ge_cmd cmd;
754 int status;
0da34b6d 755 u32 len;
34fdccea
BG		 756 struct page *dmatest_page;
757 dma_addr_t dmatest_bus;
0d6ac257
BG		 758 char *test = " ";
759
760 dmatest_page = alloc_page(GFP_KERNEL);
761 if (!dmatest_page)
762 return -ENOMEM;
763 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
764 DMA_BIDIRECTIONAL);
765
766 /* Run a small DMA test.
767 * The magic multipliers to the length tell the firmware
768 * to do DMA read, write, or read+write tests. The
769 * results are returned in cmd.data0. The upper 16
770 * bits or the return is the number of transfers completed.
771 * The lower 16 bits is the time in 0.5us ticks that the
772 * transfers took to complete.
773 */
774
775 len = mgp->tx.boundary;
776
777 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
778 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
779 cmd.data2 = len * 0x10000;
780 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
781 if (status != 0) {
782 test = "read";
783 goto abort;
784 }
785 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
786 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
787 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
788 cmd.data2 = len * 0x1;
789 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
790 if (status != 0) {
791 test = "write";
792 goto abort;
793 }
794 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
795
796 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
797 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
798 cmd.data2 = len * 0x10001;
799 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
800 if (status != 0) {
801 test = "read/write";
802 goto abort;
803 }
804 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
805 (cmd.data0 & 0xffff);
806
807abort:
808 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
809 put_page(dmatest_page);
810
811 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
812 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
813 test, status);
814
815 return status;
816}
817
818static int myri10ge_reset(struct myri10ge_priv *mgp)
819{
820 struct myri10ge_cmd cmd;
821 int status;
822 size_t bytes;
0da34b6d
BG		 823
824 /* try to send a reset command to the card to see if it
825 * is alive */
826 memset(&cmd, 0, sizeof(cmd));
827 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
828 if (status != 0) {
829 dev_err(&mgp->pdev->dev, "failed reset\n");
830 return -ENXIO;
831 }
0d6ac257
BG		 832
833 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0da34b6d
BG		 834
835 /* Now exchange information about interrupts */
836
837 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
838 memset(mgp->rx_done.entry, 0, bytes);
839 cmd.data0 = (u32) bytes;
840 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
841 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
842 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
843 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
844
845 status |=
846 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 847 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 848 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
849 &cmd, 0);
850 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 851
0da34b6d
BG		 852 status |= myri10ge_send_cmd
853 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 854 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 855 if (status != 0) {
856 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
857 return status;
858 }
40f6cff5 859 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 860
0da34b6d
BG		 861 memset(mgp->rx_done.entry, 0, bytes);
862
863 /* reset mcp/driver shared state back to 0 */
864 mgp->tx.req = 0;
865 mgp->tx.done = 0;
866 mgp->tx.pkt_start = 0;
867 mgp->tx.pkt_done = 0;
868 mgp->rx_big.cnt = 0;
869 mgp->rx_small.cnt = 0;
870 mgp->rx_done.idx = 0;
871 mgp->rx_done.cnt = 0;
c58ac5ca 872 mgp->link_changes = 0;
0da34b6d 873 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 874 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 875 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 876 return status;
877}
878
879static inline void
880myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
881 struct mcp_kreq_ether_recv *src)
882{
40f6cff5 883 __be32 low;
0da34b6d
BG		 884
885 low = src->addr_low;
40f6cff5 886 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 887 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
888 mb();
889 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 890 mb();
891 src->addr_low = low;
40f6cff5 892 put_be32(low, &dst->addr_low);
0da34b6d
BG		 893 mb();
894}
895
40f6cff5 896static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 897{
898 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
899
40f6cff5 900 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 901 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
902 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
903 skb->csum = hw_csum;
84fa7933 904 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 905 }
906}
907
dd50f336
BG		 908static inline void
909myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
910 struct skb_frag_struct *rx_frags, int len, int hlen)
911{
912 struct skb_frag_struct *skb_frags;
913
914 skb->len = skb->data_len = len;
915 skb->truesize = len + sizeof(struct sk_buff);
916 /* attach the page(s) */
917
918 skb_frags = skb_shinfo(skb)->frags;
919 while (len > 0) {
920 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
921 len -= rx_frags->size;
922 skb_frags++;
923 rx_frags++;
924 skb_shinfo(skb)->nr_frags++;
925 }
926
927 /* pskb_may_pull is not available in irq context, but
928 * skb_pull() (for ether_pad and eth_type_trans()) requires
929 * the beginning of the packet in skb_headlen(), move it
930 * manually */
27d7ff46 931 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 932 skb_shinfo(skb)->frags[0].page_offset += hlen;
933 skb_shinfo(skb)->frags[0].size -= hlen;
934 skb->data_len -= hlen;
935 skb->tail += hlen;
936 skb_pull(skb, MXGEFW_PAD);
937}
938
939static void
940myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
941 int bytes, int watchdog)
942{
943 struct page *page;
944 int idx;
945
946 if (unlikely(rx->watchdog_needed && !watchdog))
947 return;
948
949 /* try to refill entire ring */
950 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
951 idx = rx->fill_cnt & rx->mask;
ae8509b1 952 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 953 /* we can use part of previous page */
954 get_page(rx->page);
955 } else {
956 /* we need a new page */
957 page =
958 alloc_pages(GFP_ATOMIC | __GFP_COMP,
959 MYRI10GE_ALLOC_ORDER);
960 if (unlikely(page == NULL)) {
961 if (rx->fill_cnt - rx->cnt < 16)
962 rx->watchdog_needed = 1;
963 return;
964 }
965 rx->page = page;
966 rx->page_offset = 0;
967 rx->bus = pci_map_page(mgp->pdev, page, 0,
968 MYRI10GE_ALLOC_SIZE,
969 PCI_DMA_FROMDEVICE);
970 }
971 rx->info[idx].page = rx->page;
972 rx->info[idx].page_offset = rx->page_offset;
973 /* note that this is the address of the start of the
974 * page */
975 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
976 rx->shadow[idx].addr_low =
977 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
978 rx->shadow[idx].addr_high =
979 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
980
981 /* start next packet on a cacheline boundary */
982 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 983
984#if MYRI10GE_ALLOC_SIZE > 4096
985 /* don't cross a 4KB boundary */
986 if ((rx->page_offset >> 12) !=
987 ((rx->page_offset + bytes - 1) >> 12))
988 rx->page_offset = (rx->page_offset + 4096) & ~4095;
989#endif
dd50f336
BG		 990 rx->fill_cnt++;
991
992 /* copy 8 descriptors to the firmware at a time */
993 if ((idx & 7) == 7) {
994 if (rx->wc_fifo == NULL)
995 myri10ge_submit_8rx(&rx->lanai[idx - 7],
996 &rx->shadow[idx - 7]);
997 else {
998 mb();
999 myri10ge_pio_copy(rx->wc_fifo,
1000 &rx->shadow[idx - 7], 64);
1001 }
1002 }
1003 }
1004}
1005
1006static inline void
1007myri10ge_unmap_rx_page(struct pci_dev *pdev,
1008 struct myri10ge_rx_buffer_state *info, int bytes)
1009{
1010 /* unmap the recvd page if we're the only or last user of it */
1011 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1012 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1013 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1014 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1015 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1016 }
1017}
1018
1019#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1020 * page into an skb */
1021
1022static inline int
52ea6fb3
BG		 1023myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1024 int bytes, int len, __wsum csum)
dd50f336
BG		 1025{
1026 struct sk_buff *skb;
1027 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1028 int i, idx, hlen, remainder;
1029 struct pci_dev *pdev = mgp->pdev;
1030 struct net_device *dev = mgp->dev;
1031 u8 *va;
1032
1033 len += MXGEFW_PAD;
1034 idx = rx->cnt & rx->mask;
1035 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1036 prefetch(va);
1037 /* Fill skb_frag_struct(s) with data from our receive */
1038 for (i = 0, remainder = len; remainder > 0; i++) {
1039 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1040 rx_frags[i].page = rx->info[idx].page;
1041 rx_frags[i].page_offset = rx->info[idx].page_offset;
1042 if (remainder < MYRI10GE_ALLOC_SIZE)
1043 rx_frags[i].size = remainder;
1044 else
1045 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1046 rx->cnt++;
1047 idx = rx->cnt & rx->mask;
1048 remainder -= MYRI10GE_ALLOC_SIZE;
1049 }
1050
1e6e9342
AG		 1051 if (mgp->csum_flag && myri10ge_lro) {
1052 rx_frags[0].page_offset += MXGEFW_PAD;
1053 rx_frags[0].size -= MXGEFW_PAD;
1054 len -= MXGEFW_PAD;
1055 lro_receive_frags(&mgp->rx_done.lro_mgr, rx_frags,
66341fff
AV		 1056 len, len,
1057 /* opaque, will come back in get_frag_header */
1058 (void *)(__force unsigned long)csum,
1059 csum);
1e6e9342
AG		 1060 return 1;
1061 }
1062
dd50f336
BG		 1063 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1064
e636b2ea
BG		 1065 /* allocate an skb to attach the page(s) to. This is done
1066 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1067
1068 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1069 if (unlikely(skb == NULL)) {
1070 mgp->stats.rx_dropped++;
1071 do {
1072 i--;
1073 put_page(rx_frags[i].page);
1074 } while (i != 0);
1075 return 0;
1076 }
1077
1078 /* Attach the pages to the skb, and trim off any padding */
1079 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1080 if (skb_shinfo(skb)->frags[0].size <= 0) {
1081 put_page(skb_shinfo(skb)->frags[0].page);
1082 skb_shinfo(skb)->nr_frags = 0;
1083 }
1084 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1085
1086 if (mgp->csum_flag) {
1087 if ((skb->protocol == htons(ETH_P_IP)) ||
1088 (skb->protocol == htons(ETH_P_IPV6))) {
1089 skb->csum = csum;
1090 skb->ip_summed = CHECKSUM_COMPLETE;
1091 } else
1092 myri10ge_vlan_ip_csum(skb, csum);
1093 }
1094 netif_receive_skb(skb);
1095 dev->last_rx = jiffies;
1096 return 1;
1097}
1098
0da34b6d
BG		 1099static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1100{
1101 struct pci_dev *pdev = mgp->pdev;
1102 struct myri10ge_tx_buf *tx = &mgp->tx;
1103 struct sk_buff *skb;
1104 int idx, len;
0da34b6d
BG		 1105
1106 while (tx->pkt_done != mcp_index) {
1107 idx = tx->done & tx->mask;
1108 skb = tx->info[idx].skb;
1109
1110 /* Mark as free */
1111 tx->info[idx].skb = NULL;
1112 if (tx->info[idx].last) {
1113 tx->pkt_done++;
1114 tx->info[idx].last = 0;
1115 }
1116 tx->done++;
1117 len = pci_unmap_len(&tx->info[idx], len);
1118 pci_unmap_len_set(&tx->info[idx], len, 0);
1119 if (skb) {
1120 mgp->stats.tx_bytes += skb->len;
1121 mgp->stats.tx_packets++;
1122 dev_kfree_skb_irq(skb);
1123 if (len)
1124 pci_unmap_single(pdev,
1125 pci_unmap_addr(&tx->info[idx],
1126 bus), len,
1127 PCI_DMA_TODEVICE);
1128 } else {
1129 if (len)
1130 pci_unmap_page(pdev,
1131 pci_unmap_addr(&tx->info[idx],
1132 bus), len,
1133 PCI_DMA_TODEVICE);
1134 }
0da34b6d
BG		 1135 }
1136 /* start the queue if we've stopped it */
1137 if (netif_queue_stopped(mgp->dev)
1138 && tx->req - tx->done < (tx->mask >> 1)) {
1139 mgp->wake_queue++;
1140 netif_wake_queue(mgp->dev);
1141 }
1142}
1143
bea3348e 1144static inline int myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int budget)
0da34b6d
BG		 1145{
1146 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1147 unsigned long rx_bytes = 0;
1148 unsigned long rx_packets = 0;
1149 unsigned long rx_ok;
1150
1151 int idx = rx_done->idx;
1152 int cnt = rx_done->cnt;
bea3348e 1153 int work_done = 0;
0da34b6d 1154 u16 length;
40f6cff5 1155 __wsum checksum;
0da34b6d 1156
c956a240 1157 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1158 length = ntohs(rx_done->entry[idx].length);
1159 rx_done->entry[idx].length = 0;
40f6cff5 1160 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1161 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1162 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1163 mgp->small_bytes,
1164 length, checksum);
0da34b6d 1165 else
52ea6fb3
BG		 1166 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1167 mgp->big_bytes,
1168 length, checksum);
0da34b6d
BG		 1169 rx_packets += rx_ok;
1170 rx_bytes += rx_ok * (unsigned long)length;
1171 cnt++;
1172 idx = cnt & (myri10ge_max_intr_slots - 1);
c956a240 1173 work_done++;
0da34b6d
BG		 1174 }
1175 rx_done->idx = idx;
1176 rx_done->cnt = cnt;
1177 mgp->stats.rx_packets += rx_packets;
1178 mgp->stats.rx_bytes += rx_bytes;
c7dab99b 1179
1e6e9342
AG		 1180 if (myri10ge_lro)
1181 lro_flush_all(&rx_done->lro_mgr);
1182
c7dab99b
BG		 1183 /* restock receive rings if needed */
1184 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1185 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1186 mgp->small_bytes + MXGEFW_PAD, 0);
1187 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1188 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1189
bea3348e 1190 return work_done;
0da34b6d
BG		 1191}
1192
1193static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1194{
1195 struct mcp_irq_data *stats = mgp->fw_stats;
1196
1197 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1198 unsigned link_up = ntohl(stats->link_up);
1199 if (mgp->link_state != link_up) {
1200 mgp->link_state = link_up;
1201
1202 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1203 if (netif_msg_link(mgp))
1204 printk(KERN_INFO
1205 "myri10ge: %s: link up\n",
1206 mgp->dev->name);
0da34b6d 1207 netif_carrier_on(mgp->dev);
c58ac5ca 1208 mgp->link_changes++;
0da34b6d 1209 } else {
c58ac5ca
BG		 1210 if (netif_msg_link(mgp))
1211 printk(KERN_INFO
798a95db
BG		 1212 "myri10ge: %s: link %s\n",
1213 mgp->dev->name,
1214 (link_up == MXGEFW_LINK_MYRINET ?
1215 "mismatch (Myrinet detected)" :
1216 "down"));
0da34b6d 1217 netif_carrier_off(mgp->dev);
c58ac5ca 1218 mgp->link_changes++;
0da34b6d
BG		 1219 }
1220 }
1221 if (mgp->rdma_tags_available !=
1222 ntohl(mgp->fw_stats->rdma_tags_available)) {
1223 mgp->rdma_tags_available =
1224 ntohl(mgp->fw_stats->rdma_tags_available);
1225 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1226 "%d tags left\n", mgp->dev->name,
1227 mgp->rdma_tags_available);
1228 }
1229 mgp->down_cnt += stats->link_down;
1230 if (stats->link_down)
1231 wake_up(&mgp->down_wq);
1232 }
1233}
1234
bea3348e 1235static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1236{
e636b2ea
BG		 1237 struct myri10ge_priv *mgp =
1238 container_of(napi, struct myri10ge_priv, napi);
bea3348e 1239 struct net_device *netdev = mgp->dev;
bea3348e 1240 int work_done;
0da34b6d
BG		 1241
1242 /* process as many rx events as NAPI will allow */
bea3348e 1243 work_done = myri10ge_clean_rx_done(mgp, budget);
0da34b6d 1244
4ec24119 1245 if (work_done < budget) {
bea3348e 1246 netif_rx_complete(netdev, napi);
40f6cff5 1247 put_be32(htonl(3), mgp->irq_claim);
0da34b6d 1248 }
bea3348e 1249 return work_done;
0da34b6d
BG		 1250}
1251
7d12e780 1252static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1253{
1254 struct myri10ge_priv *mgp = arg;
1255 struct mcp_irq_data *stats = mgp->fw_stats;
1256 struct myri10ge_tx_buf *tx = &mgp->tx;
1257 u32 send_done_count;
1258 int i;
1259
1260 /* make sure it is our IRQ, and that the DMA has finished */
1261 if (unlikely(!stats->valid))
1262 return (IRQ_NONE);
1263
1264 /* low bit indicates receives are present, so schedule
1265 * napi poll handler */
1266 if (stats->valid & 1)
bea3348e 1267 netif_rx_schedule(mgp->dev, &mgp->napi);
0da34b6d
BG		 1268
1269 if (!mgp->msi_enabled) {
40f6cff5 1270 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1271 if (!myri10ge_deassert_wait)
1272 stats->valid = 0;
1273 mb();
1274 } else
1275 stats->valid = 0;
1276
1277 /* Wait for IRQ line to go low, if using INTx */
1278 i = 0;
1279 while (1) {
1280 i++;
1281 /* check for transmit completes and receives */
1282 send_done_count = ntohl(stats->send_done_count);
1283 if (send_done_count != tx->pkt_done)
1284 myri10ge_tx_done(mgp, (int)send_done_count);
1285 if (unlikely(i > myri10ge_max_irq_loops)) {
1286 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1287 mgp->dev->name);
1288 stats->valid = 0;
1289 schedule_work(&mgp->watchdog_work);
1290 }
1291 if (likely(stats->valid == 0))
1292 break;
1293 cpu_relax();
1294 barrier();
1295 }
1296
1297 myri10ge_check_statblock(mgp);
1298
40f6cff5 1299 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1300 return (IRQ_HANDLED);
1301}
1302
1303static int
1304myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1305{
1306 cmd->autoneg = AUTONEG_DISABLE;
1307 cmd->speed = SPEED_10000;
1308 cmd->duplex = DUPLEX_FULL;
1309 return 0;
1310}
1311
1312static void
1313myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1314{
1315 struct myri10ge_priv *mgp = netdev_priv(netdev);
1316
1317 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1318 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1319 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1320 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1321}
1322
1323static int
1324myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1325{
1326 struct myri10ge_priv *mgp = netdev_priv(netdev);
1327 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1328 return 0;
1329}
1330
1331static int
1332myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1333{
1334 struct myri10ge_priv *mgp = netdev_priv(netdev);
1335
1336 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1337 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1338 return 0;
1339}
1340
1341static void
1342myri10ge_get_pauseparam(struct net_device *netdev,
1343 struct ethtool_pauseparam *pause)
1344{
1345 struct myri10ge_priv *mgp = netdev_priv(netdev);
1346
1347 pause->autoneg = 0;
1348 pause->rx_pause = mgp->pause;
1349 pause->tx_pause = mgp->pause;
1350}
1351
1352static int
1353myri10ge_set_pauseparam(struct net_device *netdev,
1354 struct ethtool_pauseparam *pause)
1355{
1356 struct myri10ge_priv *mgp = netdev_priv(netdev);
1357
1358 if (pause->tx_pause != mgp->pause)
1359 return myri10ge_change_pause(mgp, pause->tx_pause);
1360 if (pause->rx_pause != mgp->pause)
1361 return myri10ge_change_pause(mgp, pause->tx_pause);
1362 if (pause->autoneg != 0)
1363 return -EINVAL;
1364 return 0;
1365}
1366
1367static void
1368myri10ge_get_ringparam(struct net_device *netdev,
1369 struct ethtool_ringparam *ring)
1370{
1371 struct myri10ge_priv *mgp = netdev_priv(netdev);
1372
1373 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1374 ring->rx_max_pending = mgp->rx_big.mask + 1;
1375 ring->rx_jumbo_max_pending = 0;
1376 ring->tx_max_pending = mgp->rx_small.mask + 1;
1377 ring->rx_mini_pending = ring->rx_mini_max_pending;
1378 ring->rx_pending = ring->rx_max_pending;
1379 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1380 ring->tx_pending = ring->tx_max_pending;
1381}
1382
1383static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1384{
1385 struct myri10ge_priv *mgp = netdev_priv(netdev);
1386 if (mgp->csum_flag)
1387 return 1;
1388 else
1389 return 0;
1390}
1391
1392static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1393{
1394 struct myri10ge_priv *mgp = netdev_priv(netdev);
1395 if (csum_enabled)
1396 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1397 else
1398 mgp->csum_flag = 0;
1399 return 0;
1400}
1401
4f93fde0
BG		 1402static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1403{
1404 struct myri10ge_priv *mgp = netdev_priv(netdev);
1405 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1406
1407 if (tso_enabled)
1408 netdev->features |= flags;
1409 else
1410 netdev->features &= ~flags;
1411 return 0;
1412}
1413
0da34b6d
BG		 1414static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1415 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1416 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1417 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1418 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1419 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1420 "tx_heartbeat_errors", "tx_window_errors",
1421 /* device-specific stats */
2c1a1088 1422 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1423 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1424 "serial_number", "tx_pkt_start", "tx_pkt_done",
1425 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1426 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1427 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1428 "dropped_link_error_or_filtered",
1429 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1430 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1431 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1e6e9342
AG		 1432 "dropped_no_big_buffer", "LRO aggregated", "LRO flushed",
1433 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1434};
1435
1436#define MYRI10GE_NET_STATS_LEN 21
4c3616cd 1437#define MYRI10GE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_stats)
0da34b6d
BG		 1438
1439static void
1440myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1441{
1442 switch (stringset) {
1443 case ETH_SS_STATS:
1444 memcpy(data, *myri10ge_gstrings_stats,
1445 sizeof(myri10ge_gstrings_stats));
1446 break;
1447 }
1448}
1449
b9f2c044 1450static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1451{
b9f2c044
JG		 1452 switch (sset) {
1453 case ETH_SS_STATS:
1454 return MYRI10GE_STATS_LEN;
1455 default:
1456 return -EOPNOTSUPP;
1457 }
0da34b6d
BG		 1458}
1459
1460static void
1461myri10ge_get_ethtool_stats(struct net_device *netdev,
1462 struct ethtool_stats *stats, u64 * data)
1463{
1464 struct myri10ge_priv *mgp = netdev_priv(netdev);
1465 int i;
1466
1467 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1468 data[i] = ((unsigned long *)&mgp->stats)[i];
1469
2c1a1088 1470 data[i++] = (unsigned int)mgp->tx.boundary;
276e26c3 1471 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1472 data[i++] = (unsigned int)mgp->pdev->irq;
1473 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1474 data[i++] = (unsigned int)mgp->read_dma;
1475 data[i++] = (unsigned int)mgp->write_dma;
1476 data[i++] = (unsigned int)mgp->read_write_dma;
1477 data[i++] = (unsigned int)mgp->serial_number;
1478 data[i++] = (unsigned int)mgp->tx.pkt_start;
1479 data[i++] = (unsigned int)mgp->tx.pkt_done;
1480 data[i++] = (unsigned int)mgp->tx.req;
1481 data[i++] = (unsigned int)mgp->tx.done;
1482 data[i++] = (unsigned int)mgp->rx_small.cnt;
1483 data[i++] = (unsigned int)mgp->rx_big.cnt;
1484 data[i++] = (unsigned int)mgp->wake_queue;
1485 data[i++] = (unsigned int)mgp->stop_queue;
1486 data[i++] = (unsigned int)mgp->watchdog_resets;
1487 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1488 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1489 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1490 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1491 data[i++] =
1492 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
cee505db
BG		 1493 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1494 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1495 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1496 data[i++] =
1497 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
85a7ea1b
BG		 1498 data[i++] =
1499 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1500 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1501 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1502 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1503 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1e6e9342
AG		 1504 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated;
1505 data[i++] = mgp->rx_done.lro_mgr.stats.flushed;
1506 if (mgp->rx_done.lro_mgr.stats.flushed)
1507 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated /
1508 mgp->rx_done.lro_mgr.stats.flushed;
1509 else
1510 data[i++] = 0;
1511 data[i++] = mgp->rx_done.lro_mgr.stats.no_desc;
0da34b6d
BG		 1512}
1513
c58ac5ca
BG		 1514static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1515{
1516 struct myri10ge_priv *mgp = netdev_priv(netdev);
1517 mgp->msg_enable = value;
1518}
1519
1520static u32 myri10ge_get_msglevel(struct net_device *netdev)
1521{
1522 struct myri10ge_priv *mgp = netdev_priv(netdev);
1523 return mgp->msg_enable;
1524}
1525
7282d491 1526static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1527 .get_settings = myri10ge_get_settings,
1528 .get_drvinfo = myri10ge_get_drvinfo,
1529 .get_coalesce = myri10ge_get_coalesce,
1530 .set_coalesce = myri10ge_set_coalesce,
1531 .get_pauseparam = myri10ge_get_pauseparam,
1532 .set_pauseparam = myri10ge_set_pauseparam,
1533 .get_ringparam = myri10ge_get_ringparam,
1534 .get_rx_csum = myri10ge_get_rx_csum,
1535 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1536 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1537 .set_sg = ethtool_op_set_sg,
4f93fde0 1538 .set_tso = myri10ge_set_tso,
6ffdd071 1539 .get_link = ethtool_op_get_link,
0da34b6d 1540 .get_strings = myri10ge_get_strings,
b9f2c044 1541 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1542 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1543 .set_msglevel = myri10ge_set_msglevel,
1544 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1545};
1546
1547static int myri10ge_allocate_rings(struct net_device *dev)
1548{
1549 struct myri10ge_priv *mgp;
1550 struct myri10ge_cmd cmd;
1551 int tx_ring_size, rx_ring_size;
1552 int tx_ring_entries, rx_ring_entries;
1553 int i, status;
1554 size_t bytes;
1555
1556 mgp = netdev_priv(dev);
1557
1558 /* get ring sizes */
1559
1560 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1561 tx_ring_size = cmd.data0;
1562 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1563 if (status != 0)
1564 return status;
0da34b6d
BG		 1565 rx_ring_size = cmd.data0;
1566
1567 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1568 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1569 mgp->tx.mask = tx_ring_entries - 1;
1570 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1571
355c7265
BG		 1572 status = -ENOMEM;
1573
0da34b6d
BG		 1574 /* allocate the host shadow rings */
1575
1576 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1577 * sizeof(*mgp->tx.req_list);
1578 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1579 if (mgp->tx.req_bytes == NULL)
1580 goto abort_with_nothing;
1581
1582 /* ensure req_list entries are aligned to 8 bytes */
1583 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1584 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1585
1586 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1587 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1588 if (mgp->rx_small.shadow == NULL)
1589 goto abort_with_tx_req_bytes;
1590
1591 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1592 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1593 if (mgp->rx_big.shadow == NULL)
1594 goto abort_with_rx_small_shadow;
1595
1596 /* allocate the host info rings */
1597
1598 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1599 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1600 if (mgp->tx.info == NULL)
1601 goto abort_with_rx_big_shadow;
1602
1603 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1604 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1605 if (mgp->rx_small.info == NULL)
1606 goto abort_with_tx_info;
1607
1608 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1609 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1610 if (mgp->rx_big.info == NULL)
1611 goto abort_with_rx_small_info;
1612
1613 /* Fill the receive rings */
c7dab99b
BG		 1614 mgp->rx_big.cnt = 0;
1615 mgp->rx_small.cnt = 0;
1616 mgp->rx_big.fill_cnt = 0;
1617 mgp->rx_small.fill_cnt = 0;
1618 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1619 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1620 mgp->rx_small.watchdog_needed = 0;
1621 mgp->rx_big.watchdog_needed = 0;
1622 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1623 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1624
c7dab99b
BG		 1625 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1626 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1627 dev->name, mgp->rx_small.fill_cnt);
1628 goto abort_with_rx_small_ring;
0da34b6d
BG		 1629 }
1630
c7dab99b
BG		 1631 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1632 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1633 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1634 dev->name, mgp->rx_big.fill_cnt);
1635 goto abort_with_rx_big_ring;
0da34b6d
BG		 1636 }
1637
1638 return 0;
1639
1640abort_with_rx_big_ring:
c7dab99b
BG		 1641 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1642 int idx = i & mgp->rx_big.mask;
1643 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1644 mgp->big_bytes);
1645 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1646 }
1647
1648abort_with_rx_small_ring:
c7dab99b
BG		 1649 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1650 int idx = i & mgp->rx_small.mask;
1651 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1652 mgp->small_bytes + MXGEFW_PAD);
1653 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1654 }
c7dab99b 1655
0da34b6d
BG		 1656 kfree(mgp->rx_big.info);
1657
1658abort_with_rx_small_info:
1659 kfree(mgp->rx_small.info);
1660
1661abort_with_tx_info:
1662 kfree(mgp->tx.info);
1663
1664abort_with_rx_big_shadow:
1665 kfree(mgp->rx_big.shadow);
1666
1667abort_with_rx_small_shadow:
1668 kfree(mgp->rx_small.shadow);
1669
1670abort_with_tx_req_bytes:
1671 kfree(mgp->tx.req_bytes);
1672 mgp->tx.req_bytes = NULL;
1673 mgp->tx.req_list = NULL;
1674
1675abort_with_nothing:
1676 return status;
1677}
1678
1679static void myri10ge_free_rings(struct net_device *dev)
1680{
1681 struct myri10ge_priv *mgp;
1682 struct sk_buff *skb;
1683 struct myri10ge_tx_buf *tx;
1684 int i, len, idx;
1685
1686 mgp = netdev_priv(dev);
1687
c7dab99b
BG		 1688 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1689 idx = i & mgp->rx_big.mask;
1690 if (i == mgp->rx_big.fill_cnt - 1)
1691 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1692 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1693 mgp->big_bytes);
1694 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1695 }
1696
c7dab99b
BG		 1697 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1698 idx = i & mgp->rx_small.mask;
1699 if (i == mgp->rx_small.fill_cnt - 1)
1700 mgp->rx_small.info[idx].page_offset =
1701 MYRI10GE_ALLOC_SIZE;
1702 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1703 mgp->small_bytes + MXGEFW_PAD);
1704 put_page(mgp->rx_small.info[idx].page);
1705 }
0da34b6d
BG		 1706 tx = &mgp->tx;
1707 while (tx->done != tx->req) {
1708 idx = tx->done & tx->mask;
1709 skb = tx->info[idx].skb;
1710
1711 /* Mark as free */
1712 tx->info[idx].skb = NULL;
1713 tx->done++;
1714 len = pci_unmap_len(&tx->info[idx], len);
1715 pci_unmap_len_set(&tx->info[idx], len, 0);
1716 if (skb) {
1717 mgp->stats.tx_dropped++;
1718 dev_kfree_skb_any(skb);
1719 if (len)
1720 pci_unmap_single(mgp->pdev,
1721 pci_unmap_addr(&tx->info[idx],
1722 bus), len,
1723 PCI_DMA_TODEVICE);
1724 } else {
1725 if (len)
1726 pci_unmap_page(mgp->pdev,
1727 pci_unmap_addr(&tx->info[idx],
1728 bus), len,
1729 PCI_DMA_TODEVICE);
1730 }
1731 }
1732 kfree(mgp->rx_big.info);
1733
1734 kfree(mgp->rx_small.info);
1735
1736 kfree(mgp->tx.info);
1737
1738 kfree(mgp->rx_big.shadow);
1739
1740 kfree(mgp->rx_small.shadow);
1741
1742 kfree(mgp->tx.req_bytes);
1743 mgp->tx.req_bytes = NULL;
1744 mgp->tx.req_list = NULL;
1745}
1746
df30a740
BG		 1747static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1748{
1749 struct pci_dev *pdev = mgp->pdev;
1750 int status;
1751
1752 if (myri10ge_msi) {
1753 status = pci_enable_msi(pdev);
1754 if (status != 0)
1755 dev_err(&pdev->dev,
1756 "Error %d setting up MSI; falling back to xPIC\n",
1757 status);
1758 else
1759 mgp->msi_enabled = 1;
1760 } else {
1761 mgp->msi_enabled = 0;
1762 }
1763 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1764 mgp->dev->name, mgp);
1765 if (status != 0) {
1766 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1767 if (mgp->msi_enabled)
1768 pci_disable_msi(pdev);
1769 }
1770 return status;
1771}
1772
1773static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1774{
1775 struct pci_dev *pdev = mgp->pdev;
1776
1777 free_irq(pdev->irq, mgp);
1778 if (mgp->msi_enabled)
1779 pci_disable_msi(pdev);
1780}
1781
1e6e9342
AG		 1782static int
1783myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1784 void **ip_hdr, void **tcpudp_hdr,
1785 u64 * hdr_flags, void *priv)
1786{
1787 struct ethhdr *eh;
1788 struct vlan_ethhdr *veh;
1789 struct iphdr *iph;
1790 u8 *va = page_address(frag->page) + frag->page_offset;
1791 unsigned long ll_hlen;
66341fff
AV		 1792 /* passed opaque through lro_receive_frags() */
1793 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 1794
1795 /* find the mac header, aborting if not IPv4 */
1796
1797 eh = (struct ethhdr *)va;
1798 *mac_hdr = eh;
1799 ll_hlen = ETH_HLEN;
1800 if (eh->h_proto != htons(ETH_P_IP)) {
1801 if (eh->h_proto == htons(ETH_P_8021Q)) {
1802 veh = (struct vlan_ethhdr *)va;
1803 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1804 return -1;
1805
1806 ll_hlen += VLAN_HLEN;
1807
1808 /*
1809 * HW checksum starts ETH_HLEN bytes into
1810 * frame, so we must subtract off the VLAN
1811 * header's checksum before csum can be used
1812 */
1813 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1814 VLAN_HLEN, 0));
1815 } else {
1816 return -1;
1817 }
1818 }
1819 *hdr_flags = LRO_IPV4;
1820
1821 iph = (struct iphdr *)(va + ll_hlen);
1822 *ip_hdr = iph;
1823 if (iph->protocol != IPPROTO_TCP)
1824 return -1;
1825 *hdr_flags |= LRO_TCP;
1826 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1827
1828 /* verify the IP checksum */
1829 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1830 return -1;
1831
1832 /* verify the checksum */
1833 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1834 ntohs(iph->tot_len) - (iph->ihl << 2),
1835 IPPROTO_TCP, csum)))
1836 return -1;
1837
1838 return 0;
1839}
1840
0da34b6d
BG		 1841static int myri10ge_open(struct net_device *dev)
1842{
1843 struct myri10ge_priv *mgp;
1844 struct myri10ge_cmd cmd;
1e6e9342 1845 struct net_lro_mgr *lro_mgr;
0da34b6d
BG		 1846 int status, big_pow2;
1847
1848 mgp = netdev_priv(dev);
1849
1850 if (mgp->running != MYRI10GE_ETH_STOPPED)
1851 return -EBUSY;
1852
1853 mgp->running = MYRI10GE_ETH_STARTING;
1854 status = myri10ge_reset(mgp);
1855 if (status != 0) {
1856 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1857 goto abort_with_nothing;
0da34b6d
BG		 1858 }
1859
df30a740
BG		 1860 status = myri10ge_request_irq(mgp);
1861 if (status != 0)
1862 goto abort_with_nothing;
1863
0da34b6d
BG		 1864 /* decide what small buffer size to use. For good TCP rx
1865 * performance, it is important to not receive 1514 byte
1866 * frames into jumbo buffers, as it confuses the socket buffer
1867 * accounting code, leading to drops and erratic performance.
1868 */
1869
1870 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1871 /* enough for a TCP header */
1872 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1873 ? (128 - MXGEFW_PAD)
1874 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1875 else
de3c4507
BG		 1876 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1877 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1878
1879 /* Override the small buffer size? */
1880 if (myri10ge_small_bytes > 0)
1881 mgp->small_bytes = myri10ge_small_bytes;
1882
0da34b6d
BG		 1883 /* get the lanai pointers to the send and receive rings */
1884
1885 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1886 mgp->tx.lanai =
1887 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1888
1889 status |=
1890 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1891 mgp->rx_small.lanai =
1892 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1893
1894 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1895 mgp->rx_big.lanai =
1896 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1897
1898 if (status != 0) {
1899 printk(KERN_ERR
1900 "myri10ge: %s: failed to get ring sizes or locations\n",
1901 dev->name);
1902 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1903 goto abort_with_irq;
0da34b6d
BG		 1904 }
1905
276e26c3 1906 if (myri10ge_wcfifo && mgp->wc_enabled) {
e700f9f4
BG		 1907 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1908 mgp->rx_small.wc_fifo =
1909 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1910 mgp->rx_big.wc_fifo =
1911 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1912 } else {
1913 mgp->tx.wc_fifo = NULL;
1914 mgp->rx_small.wc_fifo = NULL;
1915 mgp->rx_big.wc_fifo = NULL;
1916 }
1917
0da34b6d
BG		 1918 /* Firmware needs the big buff size as a power of 2. Lie and
1919 * tell him the buffer is larger, because we only use 1
1920 * buffer/pkt, and the mtu will prevent overruns.
1921 */
13348bee 1922 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 1923 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 1924 while (!is_power_of_2(big_pow2))
c7dab99b 1925 big_pow2++;
13348bee 1926 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1927 } else {
1928 big_pow2 = MYRI10GE_ALLOC_SIZE;
1929 mgp->big_bytes = big_pow2;
1930 }
1931
1932 status = myri10ge_allocate_rings(dev);
1933 if (status != 0)
df30a740 1934 goto abort_with_irq;
0da34b6d
BG		 1935
1936 /* now give firmware buffers sizes, and MTU */
1937 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1938 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1939 cmd.data0 = mgp->small_bytes;
1940 status |=
1941 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1942 cmd.data0 = big_pow2;
1943 status |=
1944 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1945 if (status) {
1946 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1947 dev->name);
1948 goto abort_with_rings;
1949 }
1950
1951 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1952 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1953 cmd.data2 = sizeof(struct mcp_irq_data);
1954 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1955 if (status == -ENOSYS) {
1956 dma_addr_t bus = mgp->fw_stats_bus;
1957 bus += offsetof(struct mcp_irq_data, send_done_count);
1958 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1959 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1960 status = myri10ge_send_cmd(mgp,
1961 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1962 &cmd, 0);
1963 /* Firmware cannot support multicast without STATS_DMA_V2 */
1964 mgp->fw_multicast_support = 0;
1965 } else {
1966 mgp->fw_multicast_support = 1;
1967 }
0da34b6d
BG		 1968 if (status) {
1969 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1970 dev->name);
1971 goto abort_with_rings;
1972 }
1973
66341fff 1974 mgp->link_state = ~0U;
0da34b6d
BG		 1975 mgp->rdma_tags_available = 15;
1976
1e6e9342
AG		 1977 lro_mgr = &mgp->rx_done.lro_mgr;
1978 lro_mgr->dev = dev;
1979 lro_mgr->features = LRO_F_NAPI;
1980 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
1981 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
1982 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
1983 lro_mgr->lro_arr = mgp->rx_done.lro_desc;
1984 lro_mgr->get_frag_header = myri10ge_get_frag_header;
1985 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
621544eb 1986 lro_mgr->frag_align_pad = 2;
1e6e9342
AG		 1987 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
1988 lro_mgr->max_aggr = MAX_SKB_FRAGS;
1989
bea3348e 1990 napi_enable(&mgp->napi); /* must happen prior to any irq */
0da34b6d
BG		 1991
1992 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1993 if (status) {
1994 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1995 dev->name);
1996 goto abort_with_rings;
1997 }
1998
1999 mgp->wake_queue = 0;
2000 mgp->stop_queue = 0;
2001 mgp->running = MYRI10GE_ETH_RUNNING;
2002 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2003 add_timer(&mgp->watchdog_timer);
2004 netif_wake_queue(dev);
2005 return 0;
2006
2007abort_with_rings:
2008 myri10ge_free_rings(dev);
2009
df30a740
BG		 2010abort_with_irq:
2011 myri10ge_free_irq(mgp);
2012
0da34b6d
BG		 2013abort_with_nothing:
2014 mgp->running = MYRI10GE_ETH_STOPPED;
2015 return -ENOMEM;
2016}
2017
2018static int myri10ge_close(struct net_device *dev)
2019{
2020 struct myri10ge_priv *mgp;
2021 struct myri10ge_cmd cmd;
2022 int status, old_down_cnt;
2023
2024 mgp = netdev_priv(dev);
2025
2026 if (mgp->running != MYRI10GE_ETH_RUNNING)
2027 return 0;
2028
2029 if (mgp->tx.req_bytes == NULL)
2030 return 0;
2031
2032 del_timer_sync(&mgp->watchdog_timer);
2033 mgp->running = MYRI10GE_ETH_STOPPING;
bea3348e 2034 napi_disable(&mgp->napi);
0da34b6d
BG		 2035 netif_carrier_off(dev);
2036 netif_stop_queue(dev);
2037 old_down_cnt = mgp->down_cnt;
2038 mb();
2039 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2040 if (status)
2041 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2042 dev->name);
2043
2044 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2045 if (old_down_cnt == mgp->down_cnt)
2046 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2047
2048 netif_tx_disable(dev);
df30a740 2049 myri10ge_free_irq(mgp);
0da34b6d
BG		 2050 myri10ge_free_rings(dev);
2051
2052 mgp->running = MYRI10GE_ETH_STOPPED;
2053 return 0;
2054}
2055
2056/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2057 * backwards one at a time and handle ring wraps */
2058
2059static inline void
2060myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2061 struct mcp_kreq_ether_send *src, int cnt)
2062{
2063 int idx, starting_slot;
2064 starting_slot = tx->req;
2065 while (cnt > 1) {
2066 cnt--;
2067 idx = (starting_slot + cnt) & tx->mask;
2068 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2069 mb();
2070 }
2071}
2072
2073/*
2074 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2075 * at most 32 bytes at a time, so as to avoid involving the software
2076 * pio handler in the nic. We re-write the first segment's flags
2077 * to mark them valid only after writing the entire chain.
2078 */
2079
2080static inline void
2081myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2082 int cnt)
2083{
2084 int idx, i;
2085 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2086 struct mcp_kreq_ether_send *srcp;
2087 u8 last_flags;
2088
2089 idx = tx->req & tx->mask;
2090
2091 last_flags = src->flags;
2092 src->flags = 0;
2093 mb();
2094 dst = dstp = &tx->lanai[idx];
2095 srcp = src;
2096
2097 if ((idx + cnt) < tx->mask) {
2098 for (i = 0; i < (cnt - 1); i += 2) {
2099 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2100 mb(); /* force write every 32 bytes */
2101 srcp += 2;
2102 dstp += 2;
2103 }
2104 } else {
2105 /* submit all but the first request, and ensure
2106 * that it is submitted below */
2107 myri10ge_submit_req_backwards(tx, src, cnt);
2108 i = 0;
2109 }
2110 if (i < cnt) {
2111 /* submit the first request */
2112 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2113 mb(); /* barrier before setting valid flag */
2114 }
2115
2116 /* re-write the last 32-bits with the valid flags */
2117 src->flags = last_flags;
40f6cff5 2118 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2119 tx->req += cnt;
2120 mb();
2121}
2122
2123static inline void
2124myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2125 struct mcp_kreq_ether_send *src, int cnt)
2126{
2127 tx->req += cnt;
2128 mb();
2129 while (cnt >= 4) {
2130 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2131 mb();
2132 src += 4;
2133 cnt -= 4;
2134 }
2135 if (cnt > 0) {
2136 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2137 * needs to be so that we don't overrun it */
e700f9f4
BG		 2138 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2139 src, 64);
0da34b6d
BG		 2140 mb();
2141 }
2142}
2143
2144/*
2145 * Transmit a packet. We need to split the packet so that a single
2146 * segment does not cross myri10ge->tx.boundary, so this makes segment
2147 * counting tricky. So rather than try to count segments up front, we
2148 * just give up if there are too few segments to hold a reasonably
2149 * fragmented packet currently available. If we run
2150 * out of segments while preparing a packet for DMA, we just linearize
2151 * it and try again.
2152 */
2153
2154static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2155{
2156 struct myri10ge_priv *mgp = netdev_priv(dev);
2157 struct mcp_kreq_ether_send *req;
2158 struct myri10ge_tx_buf *tx = &mgp->tx;
2159 struct skb_frag_struct *frag;
2160 dma_addr_t bus;
40f6cff5
AV		 2161 u32 low;
2162 __be32 high_swapped;
0da34b6d
BG		 2163 unsigned int len;
2164 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2165 u16 pseudo_hdr_offset, cksum_offset;
2166 int cum_len, seglen, boundary, rdma_count;
2167 u8 flags, odd_flag;
2168
2169again:
2170 req = tx->req_list;
2171 avail = tx->mask - 1 - (tx->req - tx->done);
2172
2173 mss = 0;
2174 max_segments = MXGEFW_MAX_SEND_DESC;
2175
917690cd 2176 if (skb_is_gso(skb)) {
7967168c 2177 mss = skb_shinfo(skb)->gso_size;
917690cd 2178 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2179 }
0da34b6d
BG		 2180
2181 if ((unlikely(avail < max_segments))) {
2182 /* we are out of transmit resources */
2183 mgp->stop_queue++;
2184 netif_stop_queue(dev);
2185 return 1;
2186 }
2187
2188 /* Setup checksum offloading, if needed */
2189 cksum_offset = 0;
2190 pseudo_hdr_offset = 0;
2191 odd_flag = 0;
2192 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2193 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2194 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2195 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2196 /* If the headers are excessively large, then we must
2197 * fall back to a software checksum */
4f93fde0
BG		 2198 if (unlikely(!mss && (cksum_offset > 255 ||
2199 pseudo_hdr_offset > 127))) {
84fa7933 2200 if (skb_checksum_help(skb))
0da34b6d
BG		 2201 goto drop;
2202 cksum_offset = 0;
2203 pseudo_hdr_offset = 0;
2204 } else {
0da34b6d
BG		 2205 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2206 flags |= MXGEFW_FLAGS_CKSUM;
2207 }
2208 }
2209
2210 cum_len = 0;
2211
0da34b6d
BG		 2212 if (mss) { /* TSO */
2213 /* this removes any CKSUM flag from before */
2214 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2215
2216 /* negative cum_len signifies to the
2217 * send loop that we are still in the
2218 * header portion of the TSO packet.
4f93fde0 2219 * TSO header can be at most 1KB long */
ab6a5bb6 2220 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2221
4f93fde0
BG		 2222 /* for IPv6 TSO, the checksum offset stores the
2223 * TCP header length, to save the firmware from
2224 * the need to parse the headers */
2225 if (skb_is_gso_v6(skb)) {
2226 cksum_offset = tcp_hdrlen(skb);
2227 /* Can only handle headers <= max_tso6 long */
2228 if (unlikely(-cum_len > mgp->max_tso6))
2229 return myri10ge_sw_tso(skb, dev);
2230 }
0da34b6d
BG		 2231 /* for TSO, pseudo_hdr_offset holds mss.
2232 * The firmware figures out where to put
2233 * the checksum by parsing the header. */
40f6cff5 2234 pseudo_hdr_offset = mss;
0da34b6d 2235 } else
0da34b6d
BG		 2236 /* Mark small packets, and pad out tiny packets */
2237 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2238 flags |= MXGEFW_FLAGS_SMALL;
2239
2240 /* pad frames to at least ETH_ZLEN bytes */
2241 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2242 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2243 /* The packet is gone, so we must
2244 * return 0 */
2245 mgp->stats.tx_dropped += 1;
2246 return 0;
2247 }
2248 /* adjust the len to account for the zero pad
2249 * so that the nic can know how long it is */
2250 skb->len = ETH_ZLEN;
2251 }
2252 }
2253
2254 /* map the skb for DMA */
2255 len = skb->len - skb->data_len;
2256 idx = tx->req & tx->mask;
2257 tx->info[idx].skb = skb;
2258 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2259 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2260 pci_unmap_len_set(&tx->info[idx], len, len);
2261
2262 frag_cnt = skb_shinfo(skb)->nr_frags;
2263 frag_idx = 0;
2264 count = 0;
2265 rdma_count = 0;
2266
2267 /* "rdma_count" is the number of RDMAs belonging to the
2268 * current packet BEFORE the current send request. For
2269 * non-TSO packets, this is equal to "count".
2270 * For TSO packets, rdma_count needs to be reset
2271 * to 0 after a segment cut.
2272 *
2273 * The rdma_count field of the send request is
2274 * the number of RDMAs of the packet starting at
2275 * that request. For TSO send requests with one ore more cuts
2276 * in the middle, this is the number of RDMAs starting
2277 * after the last cut in the request. All previous
2278 * segments before the last cut implicitly have 1 RDMA.
2279 *
2280 * Since the number of RDMAs is not known beforehand,
2281 * it must be filled-in retroactively - after each
2282 * segmentation cut or at the end of the entire packet.
2283 */
2284
2285 while (1) {
2286 /* Break the SKB or Fragment up into pieces which
2287 * do not cross mgp->tx.boundary */
2288 low = MYRI10GE_LOWPART_TO_U32(bus);
2289 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2290 while (len) {
2291 u8 flags_next;
2292 int cum_len_next;
2293
2294 if (unlikely(count == max_segments))
2295 goto abort_linearize;
2296
2297 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2298 seglen = boundary - low;
2299 if (seglen > len)
2300 seglen = len;
2301 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2302 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2303 if (mss) { /* TSO */
2304 (req - rdma_count)->rdma_count = rdma_count + 1;
2305
2306 if (likely(cum_len >= 0)) { /* payload */
2307 int next_is_first, chop;
2308
2309 chop = (cum_len_next > mss);
2310 cum_len_next = cum_len_next % mss;
2311 next_is_first = (cum_len_next == 0);
2312 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2313 flags_next |= next_is_first *
2314 MXGEFW_FLAGS_FIRST;
2315 rdma_count |= -(chop | next_is_first);
2316 rdma_count += chop & !next_is_first;
2317 } else if (likely(cum_len_next >= 0)) { /* header ends */
2318 int small;
2319
2320 rdma_count = -1;
2321 cum_len_next = 0;
2322 seglen = -cum_len;
2323 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2324 flags_next = MXGEFW_FLAGS_TSO_PLD |
2325 MXGEFW_FLAGS_FIRST |
2326 (small * MXGEFW_FLAGS_SMALL);
2327 }
2328 }
0da34b6d
BG		 2329 req->addr_high = high_swapped;
2330 req->addr_low = htonl(low);
40f6cff5 2331 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2332 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2333 req->rdma_count = 1;
2334 req->length = htons(seglen);
2335 req->cksum_offset = cksum_offset;
2336 req->flags = flags | ((cum_len & 1) * odd_flag);
2337
2338 low += seglen;
2339 len -= seglen;
2340 cum_len = cum_len_next;
2341 flags = flags_next;
2342 req++;
2343 count++;
2344 rdma_count++;
4f93fde0
BG		 2345 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2346 if (unlikely(cksum_offset > seglen))
2347 cksum_offset -= seglen;
2348 else
2349 cksum_offset = 0;
2350 }
0da34b6d
BG		 2351 }
2352 if (frag_idx == frag_cnt)
2353 break;
2354
2355 /* map next fragment for DMA */
2356 idx = (count + tx->req) & tx->mask;
2357 frag = &skb_shinfo(skb)->frags[frag_idx];
2358 frag_idx++;
2359 len = frag->size;
2360 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2361 len, PCI_DMA_TODEVICE);
2362 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2363 pci_unmap_len_set(&tx->info[idx], len, len);
2364 }
2365
2366 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2367 if (mss)
2368 do {
2369 req--;
2370 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2371 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2372 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2373 idx = ((count - 1) + tx->req) & tx->mask;
2374 tx->info[idx].last = 1;
2375 if (tx->wc_fifo == NULL)
2376 myri10ge_submit_req(tx, tx->req_list, count);
2377 else
2378 myri10ge_submit_req_wc(tx, tx->req_list, count);
2379 tx->pkt_start++;
2380 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2381 mgp->stop_queue++;
2382 netif_stop_queue(dev);
2383 }
2384 dev->trans_start = jiffies;
2385 return 0;
2386
2387abort_linearize:
2388 /* Free any DMA resources we've alloced and clear out the skb
2389 * slot so as to not trip up assertions, and to avoid a
2390 * double-free if linearizing fails */
2391
2392 last_idx = (idx + 1) & tx->mask;
2393 idx = tx->req & tx->mask;
2394 tx->info[idx].skb = NULL;
2395 do {
2396 len = pci_unmap_len(&tx->info[idx], len);
2397 if (len) {
2398 if (tx->info[idx].skb != NULL)
2399 pci_unmap_single(mgp->pdev,
2400 pci_unmap_addr(&tx->info[idx],
2401 bus), len,
2402 PCI_DMA_TODEVICE);
2403 else
2404 pci_unmap_page(mgp->pdev,
2405 pci_unmap_addr(&tx->info[idx],
2406 bus), len,
2407 PCI_DMA_TODEVICE);
2408 pci_unmap_len_set(&tx->info[idx], len, 0);
2409 tx->info[idx].skb = NULL;
2410 }
2411 idx = (idx + 1) & tx->mask;
2412 } while (idx != last_idx);
89114afd 2413 if (skb_is_gso(skb)) {
0da34b6d
BG		 2414 printk(KERN_ERR
2415 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2416 mgp->dev->name);
2417 goto drop;
2418 }
2419
bec0e859 2420 if (skb_linearize(skb))
0da34b6d
BG		 2421 goto drop;
2422
2423 mgp->tx_linearized++;
2424 goto again;
2425
2426drop:
2427 dev_kfree_skb_any(skb);
2428 mgp->stats.tx_dropped += 1;
2429 return 0;
2430
2431}
2432
4f93fde0
BG		 2433static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2434{
2435 struct sk_buff *segs, *curr;
2436 struct myri10ge_priv *mgp = dev->priv;
2437 int status;
2438
2439 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2440 if (IS_ERR(segs))
4f93fde0
BG		 2441 goto drop;
2442
2443 while (segs) {
2444 curr = segs;
2445 segs = segs->next;
2446 curr->next = NULL;
2447 status = myri10ge_xmit(curr, dev);
2448 if (status != 0) {
2449 dev_kfree_skb_any(curr);
2450 if (segs != NULL) {
2451 curr = segs;
2452 segs = segs->next;
2453 curr->next = NULL;
2454 dev_kfree_skb_any(segs);
2455 }
2456 goto drop;
2457 }
2458 }
2459 dev_kfree_skb_any(skb);
2460 return 0;
2461
2462drop:
2463 dev_kfree_skb_any(skb);
2464 mgp->stats.tx_dropped += 1;
2465 return 0;
2466}
2467
0da34b6d
BG		 2468static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2469{
2470 struct myri10ge_priv *mgp = netdev_priv(dev);
2471 return &mgp->stats;
2472}
2473
2474static void myri10ge_set_multicast_list(struct net_device *dev)
2475{
85a7ea1b
BG		 2476 struct myri10ge_cmd cmd;
2477 struct myri10ge_priv *mgp;
2478 struct dev_mc_list *mc_list;
6250223e 2479 __be32 data[2] = { 0, 0 };
85a7ea1b 2480 int err;
0795af57 2481 DECLARE_MAC_BUF(mac);
85a7ea1b
BG		 2482
2483 mgp = netdev_priv(dev);
0da34b6d
BG		 2484 /* can be called from atomic contexts,
2485 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2486 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2487
2488 /* This firmware is known to not support multicast */
2f76216f 2489 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2490 return;
2491
2492 /* Disable multicast filtering */
2493
2494 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2495 if (err != 0) {
2496 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2497 " error status: %d\n", dev->name, err);
2498 goto abort;
2499 }
2500
2f76216f 2501 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2502 /* request to disable multicast filtering, so quit here */
2503 return;
2504 }
2505
2506 /* Flush the filters */
2507
2508 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2509 &cmd, 1);
2510 if (err != 0) {
2511 printk(KERN_ERR
2512 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2513 ", error status: %d\n", dev->name, err);
2514 goto abort;
2515 }
2516
2517 /* Walk the multicast list, and add each address */
2518 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2519 memcpy(data, &mc_list->dmi_addr, 6);
2520 cmd.data0 = ntohl(data[0]);
2521 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2522 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2523 &cmd, 1);
2524
2525 if (err != 0) {
2526 printk(KERN_ERR "myri10ge: %s: Failed "
2527 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2528 "%d\t", dev->name, err);
0795af57
JP		 2529 printk(KERN_ERR "MAC %s\n",
2530 print_mac(mac, mc_list->dmi_addr));
85a7ea1b
BG		 2531 goto abort;
2532 }
2533 }
2534 /* Enable multicast filtering */
2535 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2536 if (err != 0) {
2537 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2538 "error status: %d\n", dev->name, err);
2539 goto abort;
2540 }
2541
2542 return;
2543
2544abort:
2545 return;
0da34b6d
BG		 2546}
2547
2548static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2549{
2550 struct sockaddr *sa = addr;
2551 struct myri10ge_priv *mgp = netdev_priv(dev);
2552 int status;
2553
2554 if (!is_valid_ether_addr(sa->sa_data))
2555 return -EADDRNOTAVAIL;
2556
2557 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2558 if (status != 0) {
2559 printk(KERN_ERR
2560 "myri10ge: %s: changing mac address failed with %d\n",
2561 dev->name, status);
2562 return status;
2563 }
2564
2565 /* change the dev structure */
2566 memcpy(dev->dev_addr, sa->sa_data, 6);
2567 return 0;
2568}
2569
2570static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2571{
2572 struct myri10ge_priv *mgp = netdev_priv(dev);
2573 int error = 0;
2574
2575 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2576 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2577 dev->name, new_mtu);
2578 return -EINVAL;
2579 }
2580 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2581 dev->name, dev->mtu, new_mtu);
2582 if (mgp->running) {
2583 /* if we change the mtu on an active device, we must
2584 * reset the device so the firmware sees the change */
2585 myri10ge_close(dev);
2586 dev->mtu = new_mtu;
2587 myri10ge_open(dev);
2588 } else
2589 dev->mtu = new_mtu;
2590
2591 return error;
2592}
2593
2594/*
2595 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2596 * Only do it if the bridge is a root port since we don't want to disturb
2597 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2598 */
2599
0da34b6d
BG		 2600static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2601{
2602 struct pci_dev *bridge = mgp->pdev->bus->self;
2603 struct device *dev = &mgp->pdev->dev;
2604 unsigned cap;
2605 unsigned err_cap;
2606 u16 val;
2607 u8 ext_type;
2608 int ret;
2609
2610 if (!myri10ge_ecrc_enable || !bridge)
2611 return;
2612
2613 /* check that the bridge is a root port */
2614 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2615 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2616 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2617 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2618 if (myri10ge_ecrc_enable > 1) {
2619 struct pci_dev *old_bridge = bridge;
2620
2621 /* Walk the hierarchy up to the root port
2622 * where ECRC has to be enabled */
2623 do {
2624 bridge = bridge->bus->self;
2625 if (!bridge) {
2626 dev_err(dev,
2627 "Failed to find root port"
2628 " to force ECRC\n");
2629 return;
2630 }
2631 cap =
2632 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2633 pci_read_config_word(bridge,
2634 cap + PCI_CAP_FLAGS, &val);
2635 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2636 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2637
2638 dev_info(dev,
2639 "Forcing ECRC on non-root port %s"
2640 " (enabling on root port %s)\n",
2641 pci_name(old_bridge), pci_name(bridge));
2642 } else {
2643 dev_err(dev,
2644 "Not enabling ECRC on non-root port %s\n",
2645 pci_name(bridge));
2646 return;
2647 }
2648 }
2649
2650 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2651 if (!cap)
2652 return;
2653
2654 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2655 if (ret) {
2656 dev_err(dev, "failed reading ext-conf-space of %s\n",
2657 pci_name(bridge));
2658 dev_err(dev, "\t pci=nommconf in use? "
2659 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2660 return;
2661 }
2662 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2663 return;
2664
2665 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2666 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2667 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 2668}
2669
2670/*
2671 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2672 * when the PCI-E Completion packets are aligned on an 8-byte
2673 * boundary. Some PCI-E chip sets always align Completion packets; on
2674 * the ones that do not, the alignment can be enforced by enabling
2675 * ECRC generation (if supported).
2676 *
2677 * When PCI-E Completion packets are not aligned, it is actually more
2678 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2679 *
2680 * If the driver can neither enable ECRC nor verify that it has
2681 * already been enabled, then it must use a firmware image which works
2682 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2683 * should also ensure that it never gives the device a Read-DMA which is
2684 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2685 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2686 * firmware image, and set tx.boundary to 4KB.
2687 */
2688
5443e9ea 2689static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 2690{
5443e9ea
BG		 2691 struct pci_dev *pdev = mgp->pdev;
2692 struct device *dev = &pdev->dev;
302d242c 2693 int status;
0da34b6d 2694
5443e9ea
BG		 2695 mgp->tx.boundary = 4096;
2696 /*
2697 * Verify the max read request size was set to 4KB
2698 * before trying the test with 4KB.
2699 */
302d242c
BG		 2700 status = pcie_get_readrq(pdev);
2701 if (status < 0) {
5443e9ea
BG		 2702 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2703 goto abort;
2704 }
302d242c
BG		 2705 if (status != 4096) {
2706 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
5443e9ea
BG		 2707 mgp->tx.boundary = 2048;
2708 }
2709 /*
2710 * load the optimized firmware (which assumes aligned PCIe
2711 * completions) in order to see if it works on this host.
2712 */
2713 mgp->fw_name = myri10ge_fw_aligned;
2714 status = myri10ge_load_firmware(mgp);
2715 if (status != 0) {
2716 goto abort;
2717 }
2718
2719 /*
2720 * Enable ECRC if possible
2721 */
2722 myri10ge_enable_ecrc(mgp);
2723
2724 /*
2725 * Run a DMA test which watches for unaligned completions and
2726 * aborts on the first one seen.
2727 */
2728
2729 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2730 if (status == 0)
2731 return; /* keep the aligned firmware */
2732
2733 if (status != -E2BIG)
2734 dev_warn(dev, "DMA test failed: %d\n", status);
2735 if (status == -ENOSYS)
2736 dev_warn(dev, "Falling back to ethp! "
2737 "Please install up to date fw\n");
2738abort:
2739 /* fall back to using the unaligned firmware */
0da34b6d
BG		 2740 mgp->tx.boundary = 2048;
2741 mgp->fw_name = myri10ge_fw_unaligned;
2742
5443e9ea
BG		 2743}
2744
2745static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2746{
0da34b6d 2747 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2748 int link_width, exp_cap;
2749 u16 lnk;
2750
2751 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2752 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2753 link_width = (lnk >> 4) & 0x3f;
2754
ce7f9368
BG		 2755 /* Check to see if Link is less than 8 or if the
2756 * upstream bridge is known to provide aligned
2757 * completions */
2758 if (link_width < 8) {
2759 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2760 link_width);
2761 mgp->tx.boundary = 4096;
2762 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 2763 } else {
2764 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 2765 }
2766 } else {
2767 if (myri10ge_force_firmware == 1) {
2768 dev_info(&mgp->pdev->dev,
2769 "Assuming aligned completions (forced)\n");
2770 mgp->tx.boundary = 4096;
2771 mgp->fw_name = myri10ge_fw_aligned;
2772 } else {
2773 dev_info(&mgp->pdev->dev,
2774 "Assuming unaligned completions (forced)\n");
2775 mgp->tx.boundary = 2048;
2776 mgp->fw_name = myri10ge_fw_unaligned;
2777 }
2778 }
2779 if (myri10ge_fw_name != NULL) {
2780 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2781 myri10ge_fw_name);
2782 mgp->fw_name = myri10ge_fw_name;
2783 }
2784}
2785
0da34b6d 2786#ifdef CONFIG_PM
0da34b6d
BG		 2787static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2788{
2789 struct myri10ge_priv *mgp;
2790 struct net_device *netdev;
2791
2792 mgp = pci_get_drvdata(pdev);
2793 if (mgp == NULL)
2794 return -EINVAL;
2795 netdev = mgp->dev;
2796
2797 netif_device_detach(netdev);
2798 if (netif_running(netdev)) {
2799 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2800 rtnl_lock();
2801 myri10ge_close(netdev);
2802 rtnl_unlock();
2803 }
2804 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2805 pci_save_state(pdev);
0da34b6d 2806 pci_disable_device(pdev);
1a63e846
BG		 2807
2808 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2809}
2810
2811static int myri10ge_resume(struct pci_dev *pdev)
2812{
2813 struct myri10ge_priv *mgp;
2814 struct net_device *netdev;
2815 int status;
2816 u16 vendor;
2817
2818 mgp = pci_get_drvdata(pdev);
2819 if (mgp == NULL)
2820 return -EINVAL;
2821 netdev = mgp->dev;
2822 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2823 msleep(5); /* give card time to respond */
2824 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2825 if (vendor == 0xffff) {
2826 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2827 mgp->dev->name);
2828 return -EIO;
2829 }
83f6e152 2830
1a63e846
BG		 2831 status = pci_restore_state(pdev);
2832 if (status)
2833 return status;
4c2248cc
BG		 2834
2835 status = pci_enable_device(pdev);
1a63e846 2836 if (status) {
4c2248cc 2837 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2838 return status;
4c2248cc
BG		 2839 }
2840
0da34b6d
BG		 2841 pci_set_master(pdev);
2842
0da34b6d 2843 myri10ge_reset(mgp);
013b68bf 2844 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2845
2846 /* Save configuration space to be restored if the
2847 * nic resets due to a parity error */
83f6e152 2848 pci_save_state(pdev);
0da34b6d
BG		 2849
2850 if (netif_running(netdev)) {
2851 rtnl_lock();
df30a740 2852 status = myri10ge_open(netdev);
0da34b6d 2853 rtnl_unlock();
df30a740
BG		 2854 if (status != 0)
2855 goto abort_with_enabled;
2856
0da34b6d
BG		 2857 }
2858 netif_device_attach(netdev);
2859
2860 return 0;
2861
4c2248cc
BG		 2862abort_with_enabled:
2863 pci_disable_device(pdev);
0da34b6d
BG		 2864 return -EIO;
2865
2866}
0da34b6d
BG		 2867#endif /* CONFIG_PM */
2868
2869static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2870{
2871 struct pci_dev *pdev = mgp->pdev;
2872 int vs = mgp->vendor_specific_offset;
2873 u32 reboot;
2874
2875 /*enter read32 mode */
2876 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2877
2878 /*read REBOOT_STATUS (0xfffffff0) */
2879 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2880 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2881 return reboot;
2882}
2883
2884/*
2885 * This watchdog is used to check whether the board has suffered
2886 * from a parity error and needs to be recovered.
2887 */
c4028958 2888static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2889{
c4028958 2890 struct myri10ge_priv *mgp =
6250223e 2891 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2892 u32 reboot;
2893 int status;
2894 u16 cmd, vendor;
2895
2896 mgp->watchdog_resets++;
2897 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2898 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2899 /* Bus master DMA disabled? Check to see
2900 * if the card rebooted due to a parity error
2901 * For now, just report it */
2902 reboot = myri10ge_read_reboot(mgp);
2903 printk(KERN_ERR
f181137f
BG		 2904 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2905 mgp->dev->name, reboot,
2906 myri10ge_reset_recover ? " " : " not");
2907 if (myri10ge_reset_recover == 0)
2908 return;
2909
2910 myri10ge_reset_recover--;
2911
0da34b6d
BG		 2912 /*
2913 * A rebooted nic will come back with config space as
2914 * it was after power was applied to PCIe bus.
2915 * Attempt to restore config space which was saved
2916 * when the driver was loaded, or the last time the
2917 * nic was resumed from power saving mode.
2918 */
83f6e152 2919 pci_restore_state(mgp->pdev);
7adda30c
BG		 2920
2921 /* save state again for accounting reasons */
83f6e152 2922 pci_save_state(mgp->pdev);
7adda30c 2923
0da34b6d
BG		 2924 } else {
2925 /* if we get back -1's from our slot, perhaps somebody
2926 * powered off our card. Don't try to reset it in
2927 * this case */
2928 if (cmd == 0xffff) {
2929 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2930 if (vendor == 0xffff) {
2931 printk(KERN_ERR
2932 "myri10ge: %s: device disappeared!\n",
2933 mgp->dev->name);
2934 return;
2935 }
2936 }
2937 /* Perhaps it is a software error. Try to reset */
2938
2939 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2940 mgp->dev->name);
2941 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2942 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2943 mgp->tx.pkt_start, mgp->tx.pkt_done,
2944 (int)ntohl(mgp->fw_stats->send_done_count));
2945 msleep(2000);
2946 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2947 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2948 mgp->tx.pkt_start, mgp->tx.pkt_done,
2949 (int)ntohl(mgp->fw_stats->send_done_count));
2950 }
2951 rtnl_lock();
2952 myri10ge_close(mgp->dev);
2953 status = myri10ge_load_firmware(mgp);
2954 if (status != 0)
2955 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2956 mgp->dev->name);
2957 else
2958 myri10ge_open(mgp->dev);
2959 rtnl_unlock();
2960}
2961
2962/*
2963 * We use our own timer routine rather than relying upon
2964 * netdev->tx_timeout because we have a very large hardware transmit
2965 * queue. Due to the large queue, the netdev->tx_timeout function
2966 * cannot detect a NIC with a parity error in a timely fashion if the
2967 * NIC is lightly loaded.
2968 */
2969static void myri10ge_watchdog_timer(unsigned long arg)
2970{
2971 struct myri10ge_priv *mgp;
626fda94 2972 u32 rx_pause_cnt;
0da34b6d
BG		 2973
2974 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2975
2976 if (mgp->rx_small.watchdog_needed) {
2977 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2978 mgp->small_bytes + MXGEFW_PAD, 1);
2979 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2980 myri10ge_fill_thresh)
2981 mgp->rx_small.watchdog_needed = 0;
2982 }
2983 if (mgp->rx_big.watchdog_needed) {
2984 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2985 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2986 myri10ge_fill_thresh)
2987 mgp->rx_big.watchdog_needed = 0;
2988 }
626fda94 2989 rx_pause_cnt = ntohl(mgp->fw_stats->dropped_pause);
c7dab99b 2990
0da34b6d 2991 if (mgp->tx.req != mgp->tx.done &&
c54772e7 2992 mgp->tx.done == mgp->watchdog_tx_done &&
626fda94 2993 mgp->watchdog_tx_req != mgp->watchdog_tx_done) {
0da34b6d 2994 /* nic seems like it might be stuck.. */
626fda94
BG		 2995 if (rx_pause_cnt != mgp->watchdog_pause) {
2996 if (net_ratelimit())
2997 printk(KERN_WARNING "myri10ge %s:"
2998 "TX paused, check link partner\n",
2999 mgp->dev->name);
3000 } else {
3001 schedule_work(&mgp->watchdog_work);
3002 return;
3003 }
3004 }
3005 /* rearm timer */
3006 mod_timer(&mgp->watchdog_timer,
3007 jiffies + myri10ge_watchdog_timeout * HZ);
0da34b6d 3008 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 3009 mgp->watchdog_tx_req = mgp->tx.req;
626fda94 3010 mgp->watchdog_pause = rx_pause_cnt;
0da34b6d
BG		 3011}
3012
3013static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3014{
3015 struct net_device *netdev;
3016 struct myri10ge_priv *mgp;
3017 struct device *dev = &pdev->dev;
3018 size_t bytes;
3019 int i;
3020 int status = -ENXIO;
0da34b6d 3021 int dac_enabled;
0da34b6d
BG		 3022
3023 netdev = alloc_etherdev(sizeof(*mgp));
3024 if (netdev == NULL) {
3025 dev_err(dev, "Could not allocate ethernet device\n");
3026 return -ENOMEM;
3027 }
3028
b245fb67
MH		 3029 SET_NETDEV_DEV(netdev, &pdev->dev);
3030
0da34b6d 3031 mgp = netdev_priv(netdev);
0da34b6d 3032 mgp->dev = netdev;
e636b2ea 3033 netif_napi_add(netdev, &mgp->napi, myri10ge_poll, myri10ge_napi_weight);
0da34b6d
BG		 3034 mgp->pdev = pdev;
3035 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3036 mgp->pause = myri10ge_flow_control;
3037 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3038 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 3039 init_waitqueue_head(&mgp->down_wq);
3040
3041 if (pci_enable_device(pdev)) {
3042 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3043 status = -ENODEV;
3044 goto abort_with_netdev;
3045 }
0da34b6d
BG		 3046
3047 /* Find the vendor-specific cap so we can check
3048 * the reboot register later on */
3049 mgp->vendor_specific_offset
3050 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3051
3052 /* Set our max read request to 4KB */
302d242c 3053 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3054 if (status != 0) {
3055 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3056 status);
3057 goto abort_with_netdev;
3058 }
3059
3060 pci_set_master(pdev);
3061 dac_enabled = 1;
3062 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3063 if (status != 0) {
3064 dac_enabled = 0;
3065 dev_err(&pdev->dev,
898eb71c
JP		 3066 "64-bit pci address mask was refused, "
3067 "trying 32-bit\n");
0da34b6d
BG		 3068 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3069 }
3070 if (status != 0) {
3071 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3072 goto abort_with_netdev;
3073 }
b10c0668
BG		 3074 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3075 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 3076 if (mgp->cmd == NULL)
3077 goto abort_with_netdev;
3078
b10c0668
BG		 3079 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3080 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 3081 if (mgp->fw_stats == NULL)
3082 goto abort_with_cmd;
3083
3084 mgp->board_span = pci_resource_len(pdev, 0);
3085 mgp->iomem_base = pci_resource_start(pdev, 0);
3086 mgp->mtrr = -1;
276e26c3 3087 mgp->wc_enabled = 0;
0da34b6d
BG		 3088#ifdef CONFIG_MTRR
3089 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3090 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3091 if (mgp->mtrr >= 0)
3092 mgp->wc_enabled = 1;
0da34b6d
BG		 3093#endif
3094 /* Hack. need to get rid of these magic numbers */
3095 mgp->sram_size =
3096 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3097 if (mgp->sram_size > mgp->board_span) {
3098 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3099 mgp->board_span);
3100 goto abort_with_wc;
3101 }
3102 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3103 if (mgp->sram == NULL) {
3104 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3105 mgp->board_span, mgp->iomem_base);
3106 status = -ENXIO;
3107 goto abort_with_wc;
3108 }
3109 memcpy_fromio(mgp->eeprom_strings,
3110 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3111 MYRI10GE_EEPROM_STRINGS_SIZE);
3112 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3113 status = myri10ge_read_mac_addr(mgp);
3114 if (status)
3115 goto abort_with_ioremap;
3116
3117 for (i = 0; i < ETH_ALEN; i++)
3118 netdev->dev_addr[i] = mgp->mac_addr[i];
3119
3120 /* allocate rx done ring */
3121 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3122 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3123 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 3124 if (mgp->rx_done.entry == NULL)
3125 goto abort_with_ioremap;
3126 memset(mgp->rx_done.entry, 0, bytes);
3127
5443e9ea
BG		 3128 myri10ge_select_firmware(mgp);
3129
0da34b6d
BG		 3130 status = myri10ge_load_firmware(mgp);
3131 if (status != 0) {
3132 dev_err(&pdev->dev, "failed to load firmware\n");
3133 goto abort_with_rx_done;
3134 }
3135
3136 status = myri10ge_reset(mgp);
3137 if (status != 0) {
3138 dev_err(&pdev->dev, "failed reset\n");
3139 goto abort_with_firmware;
3140 }
3141
0da34b6d
BG		 3142 pci_set_drvdata(pdev, mgp);
3143 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3144 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3145 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3146 myri10ge_initial_mtu = 68;
3147 netdev->mtu = myri10ge_initial_mtu;
3148 netdev->open = myri10ge_open;
3149 netdev->stop = myri10ge_close;
3150 netdev->hard_start_xmit = myri10ge_xmit;
3151 netdev->get_stats = myri10ge_get_stats;
3152 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 3153 netdev->change_mtu = myri10ge_change_mtu;
3154 netdev->set_multicast_list = myri10ge_set_multicast_list;
3155 netdev->set_mac_address = myri10ge_set_mac_address;
4f93fde0 3156 netdev->features = mgp->features;
0da34b6d
BG		 3157 if (dac_enabled)
3158 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3159
21d05db1
BG		 3160 /* make sure we can get an irq, and that MSI can be
3161 * setup (if available). Also ensure netdev->irq
3162 * is set to correct value if MSI is enabled */
3163 status = myri10ge_request_irq(mgp);
3164 if (status != 0)
3165 goto abort_with_firmware;
3166 netdev->irq = pdev->irq;
3167 myri10ge_free_irq(mgp);
3168
0da34b6d
BG		 3169 /* Save configuration space to be restored if the
3170 * nic resets due to a parity error */
83f6e152 3171 pci_save_state(pdev);
0da34b6d
BG		 3172
3173 /* Setup the watchdog timer */
3174 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3175 (unsigned long)mgp);
3176
3177 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3178 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3179 status = register_netdev(netdev);
3180 if (status != 0) {
3181 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3182 goto abort_with_state;
0da34b6d 3183 }
21d05db1
BG		 3184 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3185 (mgp->msi_enabled ? "MSI" : "xPIC"),
3186 netdev->irq, mgp->tx.boundary, mgp->fw_name,
276e26c3 3187 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3188
3189 return 0;
3190
7adda30c 3191abort_with_state:
83f6e152 3192 pci_restore_state(pdev);
0da34b6d
BG		 3193
3194abort_with_firmware:
3195 myri10ge_dummy_rdma(mgp, 0);
3196
3197abort_with_rx_done:
3198 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3199 dma_free_coherent(&pdev->dev, bytes,
3200 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3201
3202abort_with_ioremap:
3203 iounmap(mgp->sram);
3204
3205abort_with_wc:
3206#ifdef CONFIG_MTRR
3207 if (mgp->mtrr >= 0)
3208 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3209#endif
b10c0668
BG		 3210 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3211 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 3212
3213abort_with_cmd:
b10c0668
BG		 3214 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3215 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3216
3217abort_with_netdev:
3218
3219 free_netdev(netdev);
3220 return status;
3221}
3222
3223/*
3224 * myri10ge_remove
3225 *
3226 * Does what is necessary to shutdown one Myrinet device. Called
3227 * once for each Myrinet card by the kernel when a module is
3228 * unloaded.
3229 */
3230static void myri10ge_remove(struct pci_dev *pdev)
3231{
3232 struct myri10ge_priv *mgp;
3233 struct net_device *netdev;
3234 size_t bytes;
3235
3236 mgp = pci_get_drvdata(pdev);
3237 if (mgp == NULL)
3238 return;
3239
3240 flush_scheduled_work();
3241 netdev = mgp->dev;
3242 unregister_netdev(netdev);
0da34b6d
BG		 3243
3244 myri10ge_dummy_rdma(mgp, 0);
3245
7adda30c 3246 /* avoid a memory leak */
83f6e152 3247 pci_restore_state(pdev);
7adda30c 3248
0da34b6d 3249 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3250 dma_free_coherent(&pdev->dev, bytes,
3251 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3252
3253 iounmap(mgp->sram);
3254
3255#ifdef CONFIG_MTRR
3256 if (mgp->mtrr >= 0)
3257 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3258#endif
b10c0668
BG		 3259 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3260 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3261
b10c0668
BG		 3262 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3263 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3264
3265 free_netdev(netdev);
3266 pci_set_drvdata(pdev, NULL);
3267}
3268
b10c0668 3269#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3270#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 3271
3272static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3273 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3274 {PCI_DEVICE
3275 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3276 {0},
3277};
3278
3279static struct pci_driver myri10ge_driver = {
3280 .name = "myri10ge",
3281 .probe = myri10ge_probe,
3282 .remove = myri10ge_remove,
3283 .id_table = myri10ge_pci_tbl,
3284#ifdef CONFIG_PM
3285 .suspend = myri10ge_suspend,
3286 .resume = myri10ge_resume,
3287#endif
3288};
3289
3290static __init int myri10ge_init_module(void)
3291{
3292 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3293 MYRI10GE_VERSION_STR);
3294 return pci_register_driver(&myri10ge_driver);
3295}
3296
3297module_init(myri10ge_init_module);
3298
3299static __exit void myri10ge_cleanup_module(void)
3300{
3301 pci_unregister_driver(&myri10ge_driver);
3302}
3303
3304module_exit(myri10ge_cleanup_module);
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