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[mirror_ubuntu-zesty-kernel.git] / drivers / net / myri10ge / myri10ge.c
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0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
e3fd5534 4 * Copyright (C) 2005 - 2009 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
78ca90ea
JP		 41#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42
0da34b6d
BG		 43#include <linux/tcp.h>
44#include <linux/netdevice.h>
45#include <linux/skbuff.h>
46#include <linux/string.h>
47#include <linux/module.h>
48#include <linux/pci.h>
b10c0668 49#include <linux/dma-mapping.h>
0da34b6d
BG		 50#include <linux/etherdevice.h>
51#include <linux/if_ether.h>
52#include <linux/if_vlan.h>
1e6e9342 53#include <linux/inet_lro.h>
981813d8 54#include <linux/dca.h>
0da34b6d
BG		 55#include <linux/ip.h>
56#include <linux/inet.h>
57#include <linux/in.h>
58#include <linux/ethtool.h>
59#include <linux/firmware.h>
60#include <linux/delay.h>
0da34b6d
BG		 61#include <linux/timer.h>
62#include <linux/vmalloc.h>
63#include <linux/crc32.h>
64#include <linux/moduleparam.h>
65#include <linux/io.h>
199126a2 66#include <linux/log2.h>
5a0e3ad6 67#include <linux/slab.h>
0da34b6d 68#include <net/checksum.h>
1e6e9342
AG		 69#include <net/ip.h>
70#include <net/tcp.h>
0da34b6d
BG		 71#include <asm/byteorder.h>
72#include <asm/io.h>
0da34b6d
BG		 73#include <asm/processor.h>
74#ifdef CONFIG_MTRR
75#include <asm/mtrr.h>
76#endif
77
78#include "myri10ge_mcp.h"
79#include "myri10ge_mcp_gen_header.h"
80
2a3f2790 81#define MYRI10GE_VERSION_STR "1.5.2-1.459"
0da34b6d
BG		 82
83MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
84MODULE_AUTHOR("Maintainer: help@myri.com");
85MODULE_VERSION(MYRI10GE_VERSION_STR);
86MODULE_LICENSE("Dual BSD/GPL");
87
88#define MYRI10GE_MAX_ETHER_MTU 9014
89
90#define MYRI10GE_ETH_STOPPED 0
91#define MYRI10GE_ETH_STOPPING 1
92#define MYRI10GE_ETH_STARTING 2
93#define MYRI10GE_ETH_RUNNING 3
94#define MYRI10GE_ETH_OPEN_FAILED 4
95
96#define MYRI10GE_EEPROM_STRINGS_SIZE 256
97#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 98#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
99#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 100
40f6cff5 101#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 102#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
103
dd50f336
BG		 104#define MYRI10GE_ALLOC_ORDER 0
105#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
106#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
107
236bb5e6
BG		 108#define MYRI10GE_MAX_SLICES 32
109
0da34b6d 110struct myri10ge_rx_buffer_state {
dd50f336
BG		 111 struct page *page;
112 int page_offset;
c755b4b6
FT		 113 DEFINE_DMA_UNMAP_ADDR(bus);
114 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 115};
116
117struct myri10ge_tx_buffer_state {
118 struct sk_buff *skb;
119 int last;
c755b4b6
FT		 120 DEFINE_DMA_UNMAP_ADDR(bus);
121 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 122};
123
124struct myri10ge_cmd {
125 u32 data0;
126 u32 data1;
127 u32 data2;
128};
129
130struct myri10ge_rx_buf {
131 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 132 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
133 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 134 struct page *page;
135 dma_addr_t bus;
136 int page_offset;
0da34b6d 137 int cnt;
dd50f336 138 int fill_cnt;
0da34b6d
BG		 139 int alloc_fail;
140 int mask; /* number of rx slots -1 */
dd50f336 141 int watchdog_needed;
0da34b6d
BG		 142};
143
144struct myri10ge_tx_buf {
145 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 146 __be32 __iomem *send_go; /* "go" doorbell ptr */
147 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 148 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
149 char *req_bytes;
150 struct myri10ge_tx_buffer_state *info;
151 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 152 int req ____cacheline_aligned; /* transmit slots submitted */
153 int pkt_start; /* packets started */
b53bef84
BG		 154 int stop_queue;
155 int linearized;
0da34b6d
BG		 156 int done ____cacheline_aligned; /* transmit slots completed */
157 int pkt_done; /* packets completed */
b53bef84 158 int wake_queue;
236bb5e6 159 int queue_active;
0da34b6d
BG		 160};
161
162struct myri10ge_rx_done {
163 struct mcp_slot *entry;
164 dma_addr_t bus;
165 int cnt;
166 int idx;
1e6e9342
AG		 167 struct net_lro_mgr lro_mgr;
168 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 169};
170
b53bef84
BG		 171struct myri10ge_slice_netstats {
172 unsigned long rx_packets;
173 unsigned long tx_packets;
174 unsigned long rx_bytes;
175 unsigned long tx_bytes;
176 unsigned long rx_dropped;
177 unsigned long tx_dropped;
178};
179
180struct myri10ge_slice_state {
0da34b6d
BG		 181 struct myri10ge_tx_buf tx; /* transmit ring */
182 struct myri10ge_rx_buf rx_small;
183 struct myri10ge_rx_buf rx_big;
184 struct myri10ge_rx_done rx_done;
b53bef84
BG		 185 struct net_device *dev;
186 struct napi_struct napi;
187 struct myri10ge_priv *mgp;
188 struct myri10ge_slice_netstats stats;
189 __be32 __iomem *irq_claim;
190 struct mcp_irq_data *fw_stats;
191 dma_addr_t fw_stats_bus;
192 int watchdog_tx_done;
193 int watchdog_tx_req;
d0234215 194 int watchdog_rx_done;
5dd2d332 195#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 196 int cached_dca_tag;
197 int cpu;
198 __be32 __iomem *dca_tag;
199#endif
0dcffac1 200 char irq_desc[32];
b53bef84
BG		 201};
202
203struct myri10ge_priv {
0dcffac1 204 struct myri10ge_slice_state *ss;
b53bef84 205 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 206 int num_slices;
b53bef84
BG		 207 int running; /* running? */
208 int csum_flag; /* rx_csums? */
0da34b6d 209 int small_bytes;
dd50f336 210 int big_bytes;
fa0a90d9 211 int max_intr_slots;
0da34b6d 212 struct net_device *dev;
b53bef84 213 spinlock_t stats_lock;
0da34b6d
BG		 214 u8 __iomem *sram;
215 int sram_size;
216 unsigned long board_span;
217 unsigned long iomem_base;
40f6cff5 218 __be32 __iomem *irq_deassert;
0da34b6d
BG		 219 char *mac_addr_string;
220 struct mcp_cmd_response *cmd;
221 dma_addr_t cmd_bus;
0da34b6d
BG		 222 struct pci_dev *pdev;
223 int msi_enabled;
0dcffac1
BG		 224 int msix_enabled;
225 struct msix_entry *msix_vectors;
5dd2d332 226#ifdef CONFIG_MYRI10GE_DCA
981813d8 227 int dca_enabled;
ef09aadf 228 int relaxed_order;
981813d8 229#endif
66341fff 230 u32 link_state;
0da34b6d
BG		 231 unsigned int rdma_tags_available;
232 int intr_coal_delay;
40f6cff5 233 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 234 int mtrr;
276e26c3 235 int wc_enabled;
0da34b6d
BG		 236 int down_cnt;
237 wait_queue_head_t down_wq;
238 struct work_struct watchdog_work;
239 struct timer_list watchdog_timer;
0da34b6d 240 int watchdog_resets;
b53bef84 241 int watchdog_pause;
0da34b6d 242 int pause;
7d351035 243 bool fw_name_allocated;
0da34b6d
BG		 244 char *fw_name;
245 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 246 char *product_code_string;
0da34b6d 247 char fw_version[128];
9dc6f0e7
BG		 248 int fw_ver_major;
249 int fw_ver_minor;
250 int fw_ver_tiny;
251 int adopted_rx_filter_bug;
0da34b6d
BG		 252 u8 mac_addr[6]; /* eeprom mac address */
253 unsigned long serial_number;
254 int vendor_specific_offset;
85a7ea1b 255 int fw_multicast_support;
4f93fde0
BG		 256 unsigned long features;
257 u32 max_tso6;
0da34b6d
BG		 258 u32 read_dma;
259 u32 write_dma;
260 u32 read_write_dma;
c58ac5ca
BG		 261 u32 link_changes;
262 u32 msg_enable;
2d90b0aa 263 unsigned int board_number;
d0234215 264 int rebooted;
0da34b6d
BG		 265};
266
267static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
268static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 269static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
270static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
b9721d5a
BH		 271MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
272MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
273MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
274MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
0da34b6d 275
7d351035 276/* Careful: must be accessed under kparam_block_sysfs_write */
0da34b6d
BG		 277static char *myri10ge_fw_name = NULL;
278module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 279MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 280
2d90b0aa
BG		 281#define MYRI10GE_MAX_BOARDS 8
282static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 283 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 284module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
285 0444);
286MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
287
0da34b6d
BG		 288static int myri10ge_ecrc_enable = 1;
289module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 290MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 291
0da34b6d
BG		 292static int myri10ge_small_bytes = -1; /* -1 == auto */
293module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 294MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 295
296static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 297module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 298MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 299
f761fae1 300static int myri10ge_intr_coal_delay = 75;
0da34b6d 301module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 302MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 303
304static int myri10ge_flow_control = 1;
305module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 306MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 307
308static int myri10ge_deassert_wait = 1;
309module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
310MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 311 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 312
313static int myri10ge_force_firmware = 0;
314module_param(myri10ge_force_firmware, int, S_IRUGO);
315MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 316 "Force firmware to assume aligned completions");
0da34b6d 317
0da34b6d
BG		 318static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
319module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 320MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 321
322static int myri10ge_napi_weight = 64;
323module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 324MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 325
326static int myri10ge_watchdog_timeout = 1;
327module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 328MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 329
330static int myri10ge_max_irq_loops = 1048576;
331module_param(myri10ge_max_irq_loops, int, S_IRUGO);
332MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 333 "Set stuck legacy IRQ detection threshold");
0da34b6d 334
c58ac5ca
BG		 335#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
336
337static int myri10ge_debug = -1; /* defaults above */
338module_param(myri10ge_debug, int, 0);
339MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
340
1e6e9342
AG		 341static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
342module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 343MODULE_PARM_DESC(myri10ge_lro_max_pkts,
344 "Number of LRO packets to be aggregated");
1e6e9342 345
dd50f336
BG		 346static int myri10ge_fill_thresh = 256;
347module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 348MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 349
f181137f
BG		 350static int myri10ge_reset_recover = 1;
351
0dcffac1
BG		 352static int myri10ge_max_slices = 1;
353module_param(myri10ge_max_slices, int, S_IRUGO);
354MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
355
4b860abf 356static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
0dcffac1
BG		 357module_param(myri10ge_rss_hash, int, S_IRUGO);
358MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
359
981813d8
BG		 360static int myri10ge_dca = 1;
361module_param(myri10ge_dca, int, S_IRUGO);
362MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
363
0da34b6d
BG		 364#define MYRI10GE_FW_OFFSET 1024*1024
365#define MYRI10GE_HIGHPART_TO_U32(X) \
366(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
367#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
368
369#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
370
2f76216f 371static void myri10ge_set_multicast_list(struct net_device *dev);
61357325
SH		 372static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
373 struct net_device *dev);
2f76216f 374
6250223e 375static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 376{
6250223e 377 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 378}
379
59081825
BG		 380static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
381
7d351035
RR		 382static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
383{
384 if (mgp->fw_name_allocated)
385 kfree(mgp->fw_name);
386 mgp->fw_name = name;
387 mgp->fw_name_allocated = allocated;
388}
389
0da34b6d
BG		 390static int
391myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
392 struct myri10ge_cmd *data, int atomic)
393{
394 struct mcp_cmd *buf;
395 char buf_bytes[sizeof(*buf) + 8];
396 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 397 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 398 u32 dma_low, dma_high, result, value;
399 int sleep_total = 0;
400
401 /* ensure buf is aligned to 8 bytes */
402 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
403
404 buf->data0 = htonl(data->data0);
405 buf->data1 = htonl(data->data1);
406 buf->data2 = htonl(data->data2);
407 buf->cmd = htonl(cmd);
408 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
409 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
410
411 buf->response_addr.low = htonl(dma_low);
412 buf->response_addr.high = htonl(dma_high);
40f6cff5 413 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 414 mb();
415 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
416
417 /* wait up to 15ms. Longest command is the DMA benchmark,
418 * which is capped at 5ms, but runs from a timeout handler
419 * that runs every 7.8ms. So a 15ms timeout leaves us with
420 * a 2.2ms margin
421 */
422 if (atomic) {
423 /* if atomic is set, do not sleep,
424 * and try to get the completion quickly
425 * (1ms will be enough for those commands) */
426 for (sleep_total = 0;
8e95a202
JP		 427 sleep_total < 1000 &&
428 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 429 sleep_total += 10) {
0da34b6d 430 udelay(10);
bd2db0cf
BG		 431 mb();
432 }
0da34b6d
BG		 433 } else {
434 /* use msleep for most command */
435 for (sleep_total = 0;
8e95a202
JP		 436 sleep_total < 15 &&
437 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 438 sleep_total++)
439 msleep(1);
440 }
441
442 result = ntohl(response->result);
443 value = ntohl(response->data);
444 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
445 if (result == 0) {
446 data->data0 = value;
447 return 0;
85a7ea1b
BG		 448 } else if (result == MXGEFW_CMD_UNKNOWN) {
449 return -ENOSYS;
5443e9ea
BG		 450 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
451 return -E2BIG;
236bb5e6
BG		 452 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
453 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
454 (data->
455 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
456 0) {
457 return -ERANGE;
0da34b6d
BG		 458 } else {
459 dev_err(&mgp->pdev->dev,
460 "command %d failed, result = %d\n",
461 cmd, result);
462 return -ENXIO;
463 }
464 }
465
466 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
467 cmd, result);
468 return -EAGAIN;
469}
470
471/*
472 * The eeprom strings on the lanaiX have the format
473 * SN=x\0
474 * MAC=x:x:x:x:x:x\0
475 * PT:ddd mmm xx xx:xx:xx xx\0
476 * PV:ddd mmm xx xx:xx:xx xx\0
477 */
478static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
479{
480 char *ptr, *limit;
481 int i;
482
483 ptr = mgp->eeprom_strings;
484 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
485
486 while (*ptr != '\0' && ptr < limit) {
487 if (memcmp(ptr, "MAC=", 4) == 0) {
488 ptr += 4;
489 mgp->mac_addr_string = ptr;
490 for (i = 0; i < 6; i++) {
491 if ((ptr + 2) > limit)
492 goto abort;
493 mgp->mac_addr[i] =
494 simple_strtoul(ptr, &ptr, 16);
495 ptr += 1;
496 }
497 }
c0bf8801
BG		 498 if (memcmp(ptr, "PC=", 3) == 0) {
499 ptr += 3;
500 mgp->product_code_string = ptr;
501 }
0da34b6d
BG		 502 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
503 ptr += 3;
504 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
505 }
506 while (ptr < limit && *ptr++) ;
507 }
508
509 return 0;
510
511abort:
512 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
513 return -ENXIO;
514}
515
516/*
517 * Enable or disable periodic RDMAs from the host to make certain
518 * chipsets resend dropped PCIe messages
519 */
520
521static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
522{
523 char __iomem *submit;
f8fd57c1 524 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 525 u32 dma_low, dma_high;
526 int i;
527
528 /* clear confirmation addr */
529 mgp->cmd->data = 0;
530 mb();
531
532 /* send a rdma command to the PCIe engine, and wait for the
533 * response in the confirmation address. The firmware should
534 * write a -1 there to indicate it is alive and well
535 */
536 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
537 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
538
539 buf[0] = htonl(dma_high); /* confirm addr MSW */
540 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 541 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 542 buf[3] = htonl(dma_high); /* dummy addr MSW */
543 buf[4] = htonl(dma_low); /* dummy addr LSW */
544 buf[5] = htonl(enable); /* enable? */
545
e700f9f4 546 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 547
548 myri10ge_pio_copy(submit, &buf, sizeof(buf));
549 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
550 msleep(1);
551 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
552 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
553 (enable ? "enable" : "disable"));
554}
555
556static int
557myri10ge_validate_firmware(struct myri10ge_priv *mgp,
558 struct mcp_gen_header *hdr)
559{
560 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 561
562 /* check firmware type */
563 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
564 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
565 return -EINVAL;
566 }
567
568 /* save firmware version for ethtool */
569 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
570
9dc6f0e7
BG		 571 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
572 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 573
8e95a202
JP		 574 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
575 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 576 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
577 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
578 MXGEFW_VERSION_MINOR);
579 return -EINVAL;
580 }
581 return 0;
582}
583
584static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
585{
586 unsigned crc, reread_crc;
587 const struct firmware *fw;
588 struct device *dev = &mgp->pdev->dev;
b0d31d6b 589 unsigned char *fw_readback;
0da34b6d
BG		 590 struct mcp_gen_header *hdr;
591 size_t hdr_offset;
592 int status;
e454358a 593 unsigned i;
0da34b6d
BG		 594
595 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
596 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
597 mgp->fw_name);
598 status = -EINVAL;
599 goto abort_with_nothing;
600 }
601
602 /* check size */
603
604 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
605 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
606 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
607 status = -EINVAL;
608 goto abort_with_fw;
609 }
610
611 /* check id */
40f6cff5 612 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 613 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
614 dev_err(dev, "Bad firmware file\n");
615 status = -EINVAL;
616 goto abort_with_fw;
617 }
618 hdr = (void *)(fw->data + hdr_offset);
619
620 status = myri10ge_validate_firmware(mgp, hdr);
621 if (status != 0)
622 goto abort_with_fw;
623
624 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 625 for (i = 0; i < fw->size; i += 256) {
626 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
627 fw->data + i,
628 min(256U, (unsigned)(fw->size - i)));
629 mb();
630 readb(mgp->sram);
b10c0668 631 }
b0d31d6b
DW		 632 fw_readback = vmalloc(fw->size);
633 if (!fw_readback) {
634 status = -ENOMEM;
635 goto abort_with_fw;
636 }
0da34b6d 637 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 638 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
639 reread_crc = crc32(~0, fw_readback, fw->size);
640 vfree(fw_readback);
0da34b6d
BG		 641 if (crc != reread_crc) {
642 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
643 (unsigned)fw->size, reread_crc, crc);
644 status = -EIO;
645 goto abort_with_fw;
646 }
647 *size = (u32) fw->size;
648
649abort_with_fw:
650 release_firmware(fw);
651
652abort_with_nothing:
653 return status;
654}
655
656static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
657{
658 struct mcp_gen_header *hdr;
659 struct device *dev = &mgp->pdev->dev;
660 const size_t bytes = sizeof(struct mcp_gen_header);
661 size_t hdr_offset;
662 int status;
663
664 /* find running firmware header */
66341fff 665 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 666
667 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
668 dev_err(dev, "Running firmware has bad header offset (%d)\n",
669 (int)hdr_offset);
670 return -EIO;
671 }
672
673 /* copy header of running firmware from SRAM to host memory to
674 * validate firmware */
675 hdr = kmalloc(bytes, GFP_KERNEL);
676 if (hdr == NULL) {
677 dev_err(dev, "could not malloc firmware hdr\n");
678 return -ENOMEM;
679 }
680 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
681 status = myri10ge_validate_firmware(mgp, hdr);
682 kfree(hdr);
9dc6f0e7
BG		 683
684 /* check to see if adopted firmware has bug where adopting
685 * it will cause broadcasts to be filtered unless the NIC
686 * is kept in ALLMULTI mode */
687 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
688 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
689 mgp->adopted_rx_filter_bug = 1;
690 dev_warn(dev, "Adopting fw %d.%d.%d: "
691 "working around rx filter bug\n",
692 mgp->fw_ver_major, mgp->fw_ver_minor,
693 mgp->fw_ver_tiny);
694 }
0da34b6d
BG		 695 return status;
696}
697
0178ec3d 698static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 699{
700 struct myri10ge_cmd cmd;
701 int status;
702
703 /* probe for IPv6 TSO support */
704 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
705 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
706 &cmd, 0);
707 if (status == 0) {
708 mgp->max_tso6 = cmd.data0;
709 mgp->features |= NETIF_F_TSO6;
710 }
711
712 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
713 if (status != 0) {
714 dev_err(&mgp->pdev->dev,
715 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
716 return -ENXIO;
717 }
718
719 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
720
721 return 0;
722}
723
0dcffac1 724static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 725{
726 char __iomem *submit;
f8fd57c1 727 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 728 u32 dma_low, dma_high, size;
729 int status, i;
730
b10c0668 731 size = 0;
0da34b6d
BG		 732 status = myri10ge_load_hotplug_firmware(mgp, &size);
733 if (status) {
0dcffac1
BG		 734 if (!adopt)
735 return status;
0da34b6d
BG		 736 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
737
738 /* Do not attempt to adopt firmware if there
739 * was a bad crc */
740 if (status == -EIO)
741 return status;
742
743 status = myri10ge_adopt_running_firmware(mgp);
744 if (status != 0) {
745 dev_err(&mgp->pdev->dev,
746 "failed to adopt running firmware\n");
747 return status;
748 }
749 dev_info(&mgp->pdev->dev,
750 "Successfully adopted running firmware\n");
b53bef84 751 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 752 dev_warn(&mgp->pdev->dev,
753 "Using firmware currently running on NIC"
754 ". For optimal\n");
755 dev_warn(&mgp->pdev->dev,
756 "performance consider loading optimized "
757 "firmware\n");
758 dev_warn(&mgp->pdev->dev, "via hotplug\n");
759 }
760
7d351035 761 set_fw_name(mgp, "adopted", false);
b53bef84 762 mgp->tx_boundary = 2048;
fa0a90d9
BG		 763 myri10ge_dummy_rdma(mgp, 1);
764 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 765 return status;
766 }
767
768 /* clear confirmation addr */
769 mgp->cmd->data = 0;
770 mb();
771
772 /* send a reload command to the bootstrap MCP, and wait for the
773 * response in the confirmation address. The firmware should
774 * write a -1 there to indicate it is alive and well
775 */
776 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
777 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
778
779 buf[0] = htonl(dma_high); /* confirm addr MSW */
780 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 781 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 782
783 /* FIX: All newest firmware should un-protect the bottom of
784 * the sram before handoff. However, the very first interfaces
785 * do not. Therefore the handoff copy must skip the first 8 bytes
786 */
787 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
788 buf[4] = htonl(size - 8); /* length of code */
789 buf[5] = htonl(8); /* where to copy to */
790 buf[6] = htonl(0); /* where to jump to */
791
e700f9f4 792 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 793
794 myri10ge_pio_copy(submit, &buf, sizeof(buf));
795 mb();
796 msleep(1);
797 mb();
798 i = 0;
d93ca2a4
BG		 799 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
800 msleep(1 << i);
0da34b6d
BG		 801 i++;
802 }
803 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
804 dev_err(&mgp->pdev->dev, "handoff failed\n");
805 return -ENXIO;
806 }
9a71db72 807 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 808 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 809
fa0a90d9 810 return status;
0da34b6d
BG		 811}
812
813static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
814{
815 struct myri10ge_cmd cmd;
816 int status;
817
818 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
819 | (addr[2] << 8) | addr[3]);
820
821 cmd.data1 = ((addr[4] << 8) | (addr[5]));
822
823 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
824 return status;
825}
826
827static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
828{
829 struct myri10ge_cmd cmd;
830 int status, ctl;
831
832 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
833 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
834
835 if (status) {
78ca90ea 836 netdev_err(mgp->dev, "Failed to set flow control mode\n");
0da34b6d
BG		 837 return status;
838 }
839 mgp->pause = pause;
840 return 0;
841}
842
843static void
844myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
845{
846 struct myri10ge_cmd cmd;
847 int status, ctl;
848
849 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
850 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
851 if (status)
78ca90ea 852 netdev_err(mgp->dev, "Failed to set promisc mode\n");
0da34b6d
BG		 853}
854
0d6ac257 855static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 856{
857 struct myri10ge_cmd cmd;
858 int status;
0da34b6d 859 u32 len;
34fdccea
BG		 860 struct page *dmatest_page;
861 dma_addr_t dmatest_bus;
0d6ac257
BG		 862 char *test = " ";
863
864 dmatest_page = alloc_page(GFP_KERNEL);
865 if (!dmatest_page)
866 return -ENOMEM;
867 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
868 DMA_BIDIRECTIONAL);
869
870 /* Run a small DMA test.
871 * The magic multipliers to the length tell the firmware
872 * to do DMA read, write, or read+write tests. The
873 * results are returned in cmd.data0. The upper 16
874 * bits or the return is the number of transfers completed.
875 * The lower 16 bits is the time in 0.5us ticks that the
876 * transfers took to complete.
877 */
878
b53bef84 879 len = mgp->tx_boundary;
0d6ac257
BG		 880
881 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
882 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
883 cmd.data2 = len * 0x10000;
884 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
885 if (status != 0) {
886 test = "read";
887 goto abort;
888 }
889 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
890 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
891 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
892 cmd.data2 = len * 0x1;
893 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
894 if (status != 0) {
895 test = "write";
896 goto abort;
897 }
898 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
899
900 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
901 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
902 cmd.data2 = len * 0x10001;
903 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
904 if (status != 0) {
905 test = "read/write";
906 goto abort;
907 }
908 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
909 (cmd.data0 & 0xffff);
910
911abort:
912 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
913 put_page(dmatest_page);
914
915 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
916 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
917 test, status);
918
919 return status;
920}
921
922static int myri10ge_reset(struct myri10ge_priv *mgp)
923{
924 struct myri10ge_cmd cmd;
0dcffac1
BG		 925 struct myri10ge_slice_state *ss;
926 int i, status;
0d6ac257 927 size_t bytes;
5dd2d332 928#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 929 unsigned long dca_tag_off;
930#endif
0da34b6d
BG		 931
932 /* try to send a reset command to the card to see if it
933 * is alive */
934 memset(&cmd, 0, sizeof(cmd));
935 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
936 if (status != 0) {
937 dev_err(&mgp->pdev->dev, "failed reset\n");
938 return -ENXIO;
939 }
0d6ac257
BG		 940
941 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 942 /*
943 * Use non-ndis mcp_slot (eg, 4 bytes total,
944 * no toeplitz hash value returned. Older firmware will
945 * not understand this command, but will use the correct
946 * sized mcp_slot, so we ignore error returns
947 */
948 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
949 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 950
951 /* Now exchange information about interrupts */
952
0dcffac1 953 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 954 cmd.data0 = (u32) bytes;
955 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 956
957 /*
958 * Even though we already know how many slices are supported
959 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
960 * has magic side effects, and must be called after a reset.
961 * It must be called prior to calling any RSS related cmds,
962 * including assigning an interrupt queue for anything but
963 * slice 0. It must also be called *after*
964 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
965 * the firmware to compute offsets.
966 */
967
968 if (mgp->num_slices > 1) {
969
970 /* ask the maximum number of slices it supports */
971 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
972 &cmd, 0);
973 if (status != 0) {
974 dev_err(&mgp->pdev->dev,
975 "failed to get number of slices\n");
976 }
977
978 /*
979 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
980 * to setting up the interrupt queue DMA
981 */
982
983 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 984 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
985 if (mgp->dev->real_num_tx_queues > 1)
986 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 987 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
988 &cmd, 0);
236bb5e6
BG		 989
990 /* Firmware older than 1.4.32 only supports multiple
991 * RX queues, so if we get an error, first retry using a
992 * single TX queue before giving up */
993 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
c9920268 994 netif_set_real_num_tx_queues(mgp->dev, 1);
236bb5e6
BG		 995 cmd.data0 = mgp->num_slices;
996 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
997 status = myri10ge_send_cmd(mgp,
998 MXGEFW_CMD_ENABLE_RSS_QUEUES,
999 &cmd, 0);
1000 }
1001
0dcffac1
BG		 1002 if (status != 0) {
1003 dev_err(&mgp->pdev->dev,
1004 "failed to set number of slices\n");
1005
1006 return status;
1007 }
1008 }
1009 for (i = 0; i < mgp->num_slices; i++) {
1010 ss = &mgp->ss[i];
1011 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1012 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1013 cmd.data2 = i;
1014 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1015 &cmd, 0);
1016 };
0da34b6d
BG		 1017
1018 status |=
1019 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1020 for (i = 0; i < mgp->num_slices; i++) {
1021 ss = &mgp->ss[i];
1022 ss->irq_claim =
1023 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1024 }
df30a740
BG		 1025 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1026 &cmd, 0);
1027 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1028
0da34b6d
BG		 1029 status |= myri10ge_send_cmd
1030 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1031 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1032 if (status != 0) {
1033 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1034 return status;
1035 }
40f6cff5 1036 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1037
5dd2d332 1038#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1039 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1040 dca_tag_off = cmd.data0;
1041 for (i = 0; i < mgp->num_slices; i++) {
1042 ss = &mgp->ss[i];
1043 if (status == 0) {
1044 ss->dca_tag = (__iomem __be32 *)
1045 (mgp->sram + dca_tag_off + 4 * i);
1046 } else {
1047 ss->dca_tag = NULL;
1048 }
1049 }
4ee2ac51 1050#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1051
0da34b6d 1052 /* reset mcp/driver shared state back to 0 */
0dcffac1 1053
c58ac5ca 1054 mgp->link_changes = 0;
0dcffac1
BG		 1055 for (i = 0; i < mgp->num_slices; i++) {
1056 ss = &mgp->ss[i];
1057
1058 memset(ss->rx_done.entry, 0, bytes);
1059 ss->tx.req = 0;
1060 ss->tx.done = 0;
1061 ss->tx.pkt_start = 0;
1062 ss->tx.pkt_done = 0;
1063 ss->rx_big.cnt = 0;
1064 ss->rx_small.cnt = 0;
1065 ss->rx_done.idx = 0;
1066 ss->rx_done.cnt = 0;
1067 ss->tx.wake_queue = 0;
1068 ss->tx.stop_queue = 0;
1069 }
1070
0da34b6d 1071 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1072 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1073 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1074 return status;
1075}
1076
5dd2d332 1077#ifdef CONFIG_MYRI10GE_DCA
ef09aadf
AG		 1078static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
1079{
1080 int ret, cap, err;
1081 u16 ctl;
1082
1083 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1084 if (!cap)
1085 return 0;
1086
1087 err = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
1088 ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
1089 if (ret != on) {
1090 ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1091 ctl |= (on << 4);
1092 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
1093 }
1094 return ret;
1095}
1096
981813d8
BG		 1097static void
1098myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1099{
981813d8
BG		 1100 ss->cached_dca_tag = tag;
1101 put_be32(htonl(tag), ss->dca_tag);
1102}
1103
1104static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1105{
1106 int cpu = get_cpu();
1107 int tag;
1108
1109 if (cpu != ss->cpu) {
ef09aadf 1110 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
981813d8
BG		 1111 if (ss->cached_dca_tag != tag)
1112 myri10ge_write_dca(ss, cpu, tag);
ef09aadf 1113 ss->cpu = cpu;
981813d8
BG		 1114 }
1115 put_cpu();
1116}
1117
1118static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1119{
1120 int err, i;
1121 struct pci_dev *pdev = mgp->pdev;
1122
1123 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1124 return;
1125 if (!myri10ge_dca) {
1126 dev_err(&pdev->dev, "dca disabled by administrator\n");
1127 return;
1128 }
1129 err = dca_add_requester(&pdev->dev);
1130 if (err) {
330554cb
BG		 1131 if (err != -ENODEV)
1132 dev_err(&pdev->dev,
1133 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1134 return;
1135 }
ef09aadf 1136 mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
981813d8 1137 mgp->dca_enabled = 1;
ef09aadf
AG		 1138 for (i = 0; i < mgp->num_slices; i++) {
1139 mgp->ss[i].cpu = -1;
1140 mgp->ss[i].cached_dca_tag = -1;
1141 myri10ge_update_dca(&mgp->ss[i]);
1142 }
981813d8
BG		 1143}
1144
1145static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1146{
1147 struct pci_dev *pdev = mgp->pdev;
1148 int err;
1149
1150 if (!mgp->dca_enabled)
1151 return;
1152 mgp->dca_enabled = 0;
ef09aadf
AG		 1153 if (mgp->relaxed_order)
1154 myri10ge_toggle_relaxed(pdev, 1);
981813d8
BG		 1155 err = dca_remove_requester(&pdev->dev);
1156}
1157
1158static int myri10ge_notify_dca_device(struct device *dev, void *data)
1159{
1160 struct myri10ge_priv *mgp;
1161 unsigned long event;
1162
1163 mgp = dev_get_drvdata(dev);
1164 event = *(unsigned long *)data;
1165
1166 if (event == DCA_PROVIDER_ADD)
1167 myri10ge_setup_dca(mgp);
1168 else if (event == DCA_PROVIDER_REMOVE)
1169 myri10ge_teardown_dca(mgp);
1170 return 0;
1171}
4ee2ac51 1172#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1173
0da34b6d
BG		 1174static inline void
1175myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1176 struct mcp_kreq_ether_recv *src)
1177{
40f6cff5 1178 __be32 low;
0da34b6d
BG		 1179
1180 low = src->addr_low;
284901a9 1181 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1182 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1183 mb();
1184 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1185 mb();
1186 src->addr_low = low;
40f6cff5 1187 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1188 mb();
1189}
1190
40f6cff5 1191static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1192{
1193 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1194
40f6cff5 1195 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1196 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1197 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1198 skb->csum = hw_csum;
84fa7933 1199 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1200 }
1201}
1202
dd50f336
BG		 1203static inline void
1204myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1205 struct skb_frag_struct *rx_frags, int len, int hlen)
1206{
1207 struct skb_frag_struct *skb_frags;
1208
1209 skb->len = skb->data_len = len;
1210 skb->truesize = len + sizeof(struct sk_buff);
1211 /* attach the page(s) */
1212
1213 skb_frags = skb_shinfo(skb)->frags;
1214 while (len > 0) {
1215 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1216 len -= rx_frags->size;
1217 skb_frags++;
1218 rx_frags++;
1219 skb_shinfo(skb)->nr_frags++;
1220 }
1221
1222 /* pskb_may_pull is not available in irq context, but
1223 * skb_pull() (for ether_pad and eth_type_trans()) requires
1224 * the beginning of the packet in skb_headlen(), move it
1225 * manually */
27d7ff46 1226 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1227 skb_shinfo(skb)->frags[0].page_offset += hlen;
1228 skb_shinfo(skb)->frags[0].size -= hlen;
1229 skb->data_len -= hlen;
1230 skb->tail += hlen;
1231 skb_pull(skb, MXGEFW_PAD);
1232}
1233
1234static void
1235myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1236 int bytes, int watchdog)
1237{
1238 struct page *page;
1239 int idx;
2a3f2790
BG		 1240#if MYRI10GE_ALLOC_SIZE > 4096
1241 int end_offset;
1242#endif
dd50f336
BG		 1243
1244 if (unlikely(rx->watchdog_needed && !watchdog))
1245 return;
1246
1247 /* try to refill entire ring */
1248 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1249 idx = rx->fill_cnt & rx->mask;
ae8509b1 1250 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1251 /* we can use part of previous page */
1252 get_page(rx->page);
1253 } else {
1254 /* we need a new page */
1255 page =
1256 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1257 MYRI10GE_ALLOC_ORDER);
1258 if (unlikely(page == NULL)) {
1259 if (rx->fill_cnt - rx->cnt < 16)
1260 rx->watchdog_needed = 1;
1261 return;
1262 }
1263 rx->page = page;
1264 rx->page_offset = 0;
1265 rx->bus = pci_map_page(mgp->pdev, page, 0,
1266 MYRI10GE_ALLOC_SIZE,
1267 PCI_DMA_FROMDEVICE);
1268 }
1269 rx->info[idx].page = rx->page;
1270 rx->info[idx].page_offset = rx->page_offset;
1271 /* note that this is the address of the start of the
1272 * page */
c755b4b6 1273 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
dd50f336
BG		 1274 rx->shadow[idx].addr_low =
1275 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1276 rx->shadow[idx].addr_high =
1277 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1278
1279 /* start next packet on a cacheline boundary */
1280 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1281
1282#if MYRI10GE_ALLOC_SIZE > 4096
1283 /* don't cross a 4KB boundary */
2a3f2790
BG		 1284 end_offset = rx->page_offset + bytes - 1;
1285 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1286 rx->page_offset = end_offset & ~4095;
ae8509b1 1287#endif
dd50f336
BG		 1288 rx->fill_cnt++;
1289
1290 /* copy 8 descriptors to the firmware at a time */
1291 if ((idx & 7) == 7) {
e454e7e2
BG		 1292 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1293 &rx->shadow[idx - 7]);
dd50f336
BG		 1294 }
1295 }
1296}
1297
1298static inline void
1299myri10ge_unmap_rx_page(struct pci_dev *pdev,
1300 struct myri10ge_rx_buffer_state *info, int bytes)
1301{
1302 /* unmap the recvd page if we're the only or last user of it */
1303 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1304 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
c755b4b6 1305 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
dd50f336
BG		 1306 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1307 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1308 }
1309}
1310
1311#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1312 * page into an skb */
1313
1314static inline int
b53bef84 1315myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
52ea6fb3 1316 int bytes, int len, __wsum csum)
dd50f336 1317{
b53bef84 1318 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1319 struct sk_buff *skb;
1320 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1321 int i, idx, hlen, remainder;
1322 struct pci_dev *pdev = mgp->pdev;
1323 struct net_device *dev = mgp->dev;
1324 u8 *va;
1325
1326 len += MXGEFW_PAD;
1327 idx = rx->cnt & rx->mask;
1328 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1329 prefetch(va);
1330 /* Fill skb_frag_struct(s) with data from our receive */
1331 for (i = 0, remainder = len; remainder > 0; i++) {
1332 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1333 rx_frags[i].page = rx->info[idx].page;
1334 rx_frags[i].page_offset = rx->info[idx].page_offset;
1335 if (remainder < MYRI10GE_ALLOC_SIZE)
1336 rx_frags[i].size = remainder;
1337 else
1338 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1339 rx->cnt++;
1340 idx = rx->cnt & rx->mask;
1341 remainder -= MYRI10GE_ALLOC_SIZE;
1342 }
1343
3a0c7d2d 1344 if (dev->features & NETIF_F_LRO) {
1e6e9342
AG		 1345 rx_frags[0].page_offset += MXGEFW_PAD;
1346 rx_frags[0].size -= MXGEFW_PAD;
1347 len -= MXGEFW_PAD;
b53bef84 1348 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1349 /* opaque, will come back in get_frag_header */
0dcffac1 1350 len, len,
b53bef84 1351 (void *)(__force unsigned long)csum, csum);
0dcffac1 1352
1e6e9342
AG		 1353 return 1;
1354 }
1355
dd50f336
BG		 1356 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1357
e636b2ea
BG		 1358 /* allocate an skb to attach the page(s) to. This is done
1359 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1360
1361 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1362 if (unlikely(skb == NULL)) {
d6279c88 1363 ss->stats.rx_dropped++;
dd50f336
BG		 1364 do {
1365 i--;
1366 put_page(rx_frags[i].page);
1367 } while (i != 0);
1368 return 0;
1369 }
1370
1371 /* Attach the pages to the skb, and trim off any padding */
1372 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1373 if (skb_shinfo(skb)->frags[0].size <= 0) {
1374 put_page(skb_shinfo(skb)->frags[0].page);
1375 skb_shinfo(skb)->nr_frags = 0;
1376 }
1377 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 1378 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
dd50f336
BG		 1379
1380 if (mgp->csum_flag) {
1381 if ((skb->protocol == htons(ETH_P_IP)) ||
1382 (skb->protocol == htons(ETH_P_IPV6))) {
1383 skb->csum = csum;
1384 skb->ip_summed = CHECKSUM_COMPLETE;
1385 } else
1386 myri10ge_vlan_ip_csum(skb, csum);
1387 }
1388 netif_receive_skb(skb);
dd50f336
BG		 1389 return 1;
1390}
1391
b53bef84
BG		 1392static inline void
1393myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1394{
b53bef84
BG		 1395 struct pci_dev *pdev = ss->mgp->pdev;
1396 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1397 struct netdev_queue *dev_queue;
0da34b6d
BG		 1398 struct sk_buff *skb;
1399 int idx, len;
0da34b6d
BG		 1400
1401 while (tx->pkt_done != mcp_index) {
1402 idx = tx->done & tx->mask;
1403 skb = tx->info[idx].skb;
1404
1405 /* Mark as free */
1406 tx->info[idx].skb = NULL;
1407 if (tx->info[idx].last) {
1408 tx->pkt_done++;
1409 tx->info[idx].last = 0;
1410 }
1411 tx->done++;
c755b4b6
FT		 1412 len = dma_unmap_len(&tx->info[idx], len);
1413 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 1414 if (skb) {
b53bef84
BG		 1415 ss->stats.tx_bytes += skb->len;
1416 ss->stats.tx_packets++;
0da34b6d
BG		 1417 dev_kfree_skb_irq(skb);
1418 if (len)
1419 pci_unmap_single(pdev,
c755b4b6 1420 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1421 bus), len,
1422 PCI_DMA_TODEVICE);
1423 } else {
1424 if (len)
1425 pci_unmap_page(pdev,
c755b4b6 1426 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1427 bus), len,
1428 PCI_DMA_TODEVICE);
1429 }
0da34b6d 1430 }
236bb5e6
BG		 1431
1432 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1433 /*
1434 * Make a minimal effort to prevent the NIC from polling an
1435 * idle tx queue. If we can't get the lock we leave the queue
1436 * active. In this case, either a thread was about to start
1437 * using the queue anyway, or we lost a race and the NIC will
1438 * waste some of its resources polling an inactive queue for a
1439 * while.
1440 */
1441
1442 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1443 __netif_tx_trylock(dev_queue)) {
1444 if (tx->req == tx->done) {
1445 tx->queue_active = 0;
1446 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1447 mb();
6824a105 1448 mmiowb();
236bb5e6
BG		 1449 }
1450 __netif_tx_unlock(dev_queue);
1451 }
1452
0da34b6d 1453 /* start the queue if we've stopped it */
8e95a202
JP		 1454 if (netif_tx_queue_stopped(dev_queue) &&
1455 tx->req - tx->done < (tx->mask >> 1)) {
b53bef84 1456 tx->wake_queue++;
236bb5e6 1457 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1458 }
1459}
1460
b53bef84
BG		 1461static inline int
1462myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1463{
b53bef84
BG		 1464 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1465 struct myri10ge_priv *mgp = ss->mgp;
18af3e7c 1466 struct net_device *netdev = mgp->dev;
0da34b6d
BG		 1467 unsigned long rx_bytes = 0;
1468 unsigned long rx_packets = 0;
1469 unsigned long rx_ok;
1470
1471 int idx = rx_done->idx;
1472 int cnt = rx_done->cnt;
bea3348e 1473 int work_done = 0;
0da34b6d 1474 u16 length;
40f6cff5 1475 __wsum checksum;
0da34b6d 1476
c956a240 1477 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1478 length = ntohs(rx_done->entry[idx].length);
1479 rx_done->entry[idx].length = 0;
40f6cff5 1480 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1481 if (length <= mgp->small_bytes)
b53bef84 1482 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
52ea6fb3
BG		 1483 mgp->small_bytes,
1484 length, checksum);
0da34b6d 1485 else
b53bef84 1486 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
52ea6fb3
BG		 1487 mgp->big_bytes,
1488 length, checksum);
0da34b6d
BG		 1489 rx_packets += rx_ok;
1490 rx_bytes += rx_ok * (unsigned long)length;
1491 cnt++;
014377a1 1492 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1493 work_done++;
0da34b6d
BG		 1494 }
1495 rx_done->idx = idx;
1496 rx_done->cnt = cnt;
b53bef84
BG		 1497 ss->stats.rx_packets += rx_packets;
1498 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1499
18af3e7c 1500 if (netdev->features & NETIF_F_LRO)
1e6e9342
AG		 1501 lro_flush_all(&rx_done->lro_mgr);
1502
c7dab99b 1503 /* restock receive rings if needed */
b53bef84
BG		 1504 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1505 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1506 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1507 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1508 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1509
bea3348e 1510 return work_done;
0da34b6d
BG		 1511}
1512
1513static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1514{
0dcffac1 1515 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1516
1517 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1518 unsigned link_up = ntohl(stats->link_up);
1519 if (mgp->link_state != link_up) {
1520 mgp->link_state = link_up;
1521
1522 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca 1523 if (netif_msg_link(mgp))
78ca90ea 1524 netdev_info(mgp->dev, "link up\n");
0da34b6d 1525 netif_carrier_on(mgp->dev);
c58ac5ca 1526 mgp->link_changes++;
0da34b6d 1527 } else {
c58ac5ca 1528 if (netif_msg_link(mgp))
78ca90ea
JP		 1529 netdev_info(mgp->dev, "link %s\n",
1530 link_up == MXGEFW_LINK_MYRINET ?
1531 "mismatch (Myrinet detected)" :
1532 "down");
0da34b6d 1533 netif_carrier_off(mgp->dev);
c58ac5ca 1534 mgp->link_changes++;
0da34b6d
BG		 1535 }
1536 }
1537 if (mgp->rdma_tags_available !=
b53bef84 1538 ntohl(stats->rdma_tags_available)) {
0da34b6d 1539 mgp->rdma_tags_available =
b53bef84 1540 ntohl(stats->rdma_tags_available);
78ca90ea
JP		 1541 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1542 mgp->rdma_tags_available);
0da34b6d
BG		 1543 }
1544 mgp->down_cnt += stats->link_down;
1545 if (stats->link_down)
1546 wake_up(&mgp->down_wq);
1547 }
1548}
1549
bea3348e 1550static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1551{
b53bef84
BG		 1552 struct myri10ge_slice_state *ss =
1553 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1554 int work_done;
0da34b6d 1555
5dd2d332 1556#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1557 if (ss->mgp->dca_enabled)
1558 myri10ge_update_dca(ss);
1559#endif
1560
0da34b6d 1561 /* process as many rx events as NAPI will allow */
b53bef84 1562 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1563
4ec24119 1564 if (work_done < budget) {
288379f0 1565 napi_complete(napi);
b53bef84 1566 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1567 }
bea3348e 1568 return work_done;
0da34b6d
BG		 1569}
1570
7d12e780 1571static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1572{
b53bef84
BG		 1573 struct myri10ge_slice_state *ss = arg;
1574 struct myri10ge_priv *mgp = ss->mgp;
1575 struct mcp_irq_data *stats = ss->fw_stats;
1576 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1577 u32 send_done_count;
1578 int i;
1579
236bb5e6
BG		 1580 /* an interrupt on a non-zero receive-only slice is implicitly
1581 * valid since MSI-X irqs are not shared */
1582 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1583 napi_schedule(&ss->napi);
807540ba 1584 return IRQ_HANDLED;
0dcffac1
BG		 1585 }
1586
0da34b6d
BG		 1587 /* make sure it is our IRQ, and that the DMA has finished */
1588 if (unlikely(!stats->valid))
807540ba 1589 return IRQ_NONE;
0da34b6d
BG		 1590
1591 /* low bit indicates receives are present, so schedule
1592 * napi poll handler */
1593 if (stats->valid & 1)
288379f0 1594 napi_schedule(&ss->napi);
0da34b6d 1595
0dcffac1 1596 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1597 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1598 if (!myri10ge_deassert_wait)
1599 stats->valid = 0;
1600 mb();
1601 } else
1602 stats->valid = 0;
1603
1604 /* Wait for IRQ line to go low, if using INTx */
1605 i = 0;
1606 while (1) {
1607 i++;
1608 /* check for transmit completes and receives */
1609 send_done_count = ntohl(stats->send_done_count);
1610 if (send_done_count != tx->pkt_done)
b53bef84 1611 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d 1612 if (unlikely(i > myri10ge_max_irq_loops)) {
78ca90ea 1613 netdev_err(mgp->dev, "irq stuck?\n");
0da34b6d
BG		 1614 stats->valid = 0;
1615 schedule_work(&mgp->watchdog_work);
1616 }
1617 if (likely(stats->valid == 0))
1618 break;
1619 cpu_relax();
1620 barrier();
1621 }
1622
236bb5e6
BG		 1623 /* Only slice 0 updates stats */
1624 if (ss == mgp->ss)
1625 myri10ge_check_statblock(mgp);
0da34b6d 1626
b53bef84 1627 put_be32(htonl(3), ss->irq_claim + 1);
807540ba 1628 return IRQ_HANDLED;
0da34b6d
BG		 1629}
1630
1631static int
1632myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1633{
c0bf8801
BG		 1634 struct myri10ge_priv *mgp = netdev_priv(netdev);
1635 char *ptr;
1636 int i;
1637
0da34b6d
BG		 1638 cmd->autoneg = AUTONEG_DISABLE;
1639 cmd->speed = SPEED_10000;
1640 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1641
1642 /*
1643 * parse the product code to deterimine the interface type
1644 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1645 * after the 3rd dash in the driver's cached copy of the
1646 * EEPROM's product code string.
1647 */
1648 ptr = mgp->product_code_string;
1649 if (ptr == NULL) {
78ca90ea 1650 netdev_err(netdev, "Missing product code\n");
c0bf8801
BG		 1651 return 0;
1652 }
1653 for (i = 0; i < 3; i++, ptr++) {
1654 ptr = strchr(ptr, '-');
1655 if (ptr == NULL) {
78ca90ea
JP		 1656 netdev_err(netdev, "Invalid product code %s\n",
1657 mgp->product_code_string);
c0bf8801
BG		 1658 return 0;
1659 }
1660 }
196f17eb
BG		 1661 if (*ptr == '2')
1662 ptr++;
1663 if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1664 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
c0bf8801 1665 cmd->port = PORT_FIBRE;
196f17eb
BG		 1666 cmd->supported |= SUPPORTED_FIBRE;
1667 cmd->advertising |= ADVERTISED_FIBRE;
1668 } else {
1669 cmd->port = PORT_OTHER;
c0bf8801 1670 }
196f17eb
BG		 1671 if (*ptr == 'R' || *ptr == 'S')
1672 cmd->transceiver = XCVR_EXTERNAL;
1673 else
1674 cmd->transceiver = XCVR_INTERNAL;
1675
0da34b6d
BG		 1676 return 0;
1677}
1678
1679static void
1680myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1681{
1682 struct myri10ge_priv *mgp = netdev_priv(netdev);
1683
1684 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1685 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1686 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1687 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1688}
1689
1690static int
1691myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1692{
1693 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1694
0da34b6d
BG		 1695 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1696 return 0;
1697}
1698
1699static int
1700myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1701{
1702 struct myri10ge_priv *mgp = netdev_priv(netdev);
1703
1704 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1705 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1706 return 0;
1707}
1708
1709static void
1710myri10ge_get_pauseparam(struct net_device *netdev,
1711 struct ethtool_pauseparam *pause)
1712{
1713 struct myri10ge_priv *mgp = netdev_priv(netdev);
1714
1715 pause->autoneg = 0;
1716 pause->rx_pause = mgp->pause;
1717 pause->tx_pause = mgp->pause;
1718}
1719
1720static int
1721myri10ge_set_pauseparam(struct net_device *netdev,
1722 struct ethtool_pauseparam *pause)
1723{
1724 struct myri10ge_priv *mgp = netdev_priv(netdev);
1725
1726 if (pause->tx_pause != mgp->pause)
1727 return myri10ge_change_pause(mgp, pause->tx_pause);
1728 if (pause->rx_pause != mgp->pause)
2488f56d 1729 return myri10ge_change_pause(mgp, pause->rx_pause);
0da34b6d
BG		 1730 if (pause->autoneg != 0)
1731 return -EINVAL;
1732 return 0;
1733}
1734
1735static void
1736myri10ge_get_ringparam(struct net_device *netdev,
1737 struct ethtool_ringparam *ring)
1738{
1739 struct myri10ge_priv *mgp = netdev_priv(netdev);
1740
0dcffac1
BG		 1741 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1742 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1743 ring->rx_jumbo_max_pending = 0;
6498be3f 1744 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1745 ring->rx_mini_pending = ring->rx_mini_max_pending;
1746 ring->rx_pending = ring->rx_max_pending;
1747 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1748 ring->tx_pending = ring->tx_max_pending;
1749}
1750
1751static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1752{
1753 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1754
0da34b6d
BG		 1755 if (mgp->csum_flag)
1756 return 1;
1757 else
1758 return 0;
1759}
1760
1761static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1762{
1763 struct myri10ge_priv *mgp = netdev_priv(netdev);
3a0c7d2d 1764 int err = 0;
99f5f87e 1765
0da34b6d
BG		 1766 if (csum_enabled)
1767 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3a0c7d2d 1768 else {
1437ce39 1769 netdev->features &= ~NETIF_F_LRO;
0da34b6d 1770 mgp->csum_flag = 0;
3a0c7d2d
BG		 1771
1772 }
1773 return err;
0da34b6d
BG		 1774}
1775
4f93fde0
BG		 1776static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1777{
1778 struct myri10ge_priv *mgp = netdev_priv(netdev);
1779 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1780
1781 if (tso_enabled)
1782 netdev->features |= flags;
1783 else
1784 netdev->features &= ~flags;
1785 return 0;
1786}
1787
b53bef84 1788static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1789 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1790 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1791 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1792 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1793 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1794 "tx_heartbeat_errors", "tx_window_errors",
1795 /* device-specific stats */
0dcffac1 1796 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1797 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1798 "serial_number", "watchdog_resets",
5dd2d332 1799#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1800 "dca_capable_firmware", "dca_device_present",
981813d8 1801#endif
c58ac5ca 1802 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1803 "dropped_link_error_or_filtered",
1804 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1805 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1806 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1807 "dropped_no_big_buffer"
1808};
1809
1810static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1811 "----------- slice ---------",
1812 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1813 "rx_small_cnt", "rx_big_cnt",
1814 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1815 "LRO flushed",
1e6e9342 1816 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1817};
1818
1819#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1820#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1821#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1822
1823static void
1824myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1825{
0dcffac1
BG		 1826 struct myri10ge_priv *mgp = netdev_priv(netdev);
1827 int i;
1828
0da34b6d
BG		 1829 switch (stringset) {
1830 case ETH_SS_STATS:
b53bef84
BG		 1831 memcpy(data, *myri10ge_gstrings_main_stats,
1832 sizeof(myri10ge_gstrings_main_stats));
1833 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1834 for (i = 0; i < mgp->num_slices; i++) {
1835 memcpy(data, *myri10ge_gstrings_slice_stats,
1836 sizeof(myri10ge_gstrings_slice_stats));
1837 data += sizeof(myri10ge_gstrings_slice_stats);
1838 }
0da34b6d
BG		 1839 break;
1840 }
1841}
1842
b9f2c044 1843static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1844{
0dcffac1
BG		 1845 struct myri10ge_priv *mgp = netdev_priv(netdev);
1846
b9f2c044
JG		 1847 switch (sset) {
1848 case ETH_SS_STATS:
0dcffac1
BG		 1849 return MYRI10GE_MAIN_STATS_LEN +
1850 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1851 default:
1852 return -EOPNOTSUPP;
1853 }
0da34b6d
BG		 1854}
1855
1856static void
1857myri10ge_get_ethtool_stats(struct net_device *netdev,
1858 struct ethtool_stats *stats, u64 * data)
1859{
1860 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1861 struct myri10ge_slice_state *ss;
0dcffac1 1862 int slice;
0da34b6d
BG		 1863 int i;
1864
59081825
BG		 1865 /* force stats update */
1866 (void)myri10ge_get_stats(netdev);
0da34b6d 1867 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
6dc34941 1868 data[i] = ((unsigned long *)&netdev->stats)[i];
0da34b6d 1869
b53bef84 1870 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1871 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1872 data[i++] = (unsigned int)mgp->pdev->irq;
1873 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1874 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1875 data[i++] = (unsigned int)mgp->read_dma;
1876 data[i++] = (unsigned int)mgp->write_dma;
1877 data[i++] = (unsigned int)mgp->read_write_dma;
1878 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1879 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1880#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1881 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1882 data[i++] = (unsigned int)(mgp->dca_enabled);
1883#endif
c58ac5ca 1884 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1885
1886 /* firmware stats are useful only in the first slice */
0dcffac1 1887 ss = &mgp->ss[0];
b53bef84
BG		 1888 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1889 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1890 data[i++] =
b53bef84
BG		 1891 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1892 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1893 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1894 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1895 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1896 data[i++] =
b53bef84
BG		 1897 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1898 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1899 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1900 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1901 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1902
0dcffac1
BG		 1903 for (slice = 0; slice < mgp->num_slices; slice++) {
1904 ss = &mgp->ss[slice];
1905 data[i++] = slice;
1906 data[i++] = (unsigned int)ss->tx.pkt_start;
1907 data[i++] = (unsigned int)ss->tx.pkt_done;
1908 data[i++] = (unsigned int)ss->tx.req;
1909 data[i++] = (unsigned int)ss->tx.done;
1910 data[i++] = (unsigned int)ss->rx_small.cnt;
1911 data[i++] = (unsigned int)ss->rx_big.cnt;
1912 data[i++] = (unsigned int)ss->tx.wake_queue;
1913 data[i++] = (unsigned int)ss->tx.stop_queue;
1914 data[i++] = (unsigned int)ss->tx.linearized;
1915 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1916 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1917 if (ss->rx_done.lro_mgr.stats.flushed)
1918 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1919 ss->rx_done.lro_mgr.stats.flushed;
1920 else
1921 data[i++] = 0;
1922 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1923 }
0da34b6d
BG		 1924}
1925
c58ac5ca
BG		 1926static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1927{
1928 struct myri10ge_priv *mgp = netdev_priv(netdev);
1929 mgp->msg_enable = value;
1930}
1931
1932static u32 myri10ge_get_msglevel(struct net_device *netdev)
1933{
1934 struct myri10ge_priv *mgp = netdev_priv(netdev);
1935 return mgp->msg_enable;
1936}
1937
1437ce39
BH		 1938static int myri10ge_set_flags(struct net_device *netdev, u32 value)
1939{
1940 return ethtool_op_set_flags(netdev, value, ETH_FLAG_LRO);
1941}
1942
7282d491 1943static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1944 .get_settings = myri10ge_get_settings,
1945 .get_drvinfo = myri10ge_get_drvinfo,
1946 .get_coalesce = myri10ge_get_coalesce,
1947 .set_coalesce = myri10ge_set_coalesce,
1948 .get_pauseparam = myri10ge_get_pauseparam,
1949 .set_pauseparam = myri10ge_set_pauseparam,
1950 .get_ringparam = myri10ge_get_ringparam,
1951 .get_rx_csum = myri10ge_get_rx_csum,
1952 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1953 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1954 .set_sg = ethtool_op_set_sg,
4f93fde0 1955 .set_tso = myri10ge_set_tso,
6ffdd071 1956 .get_link = ethtool_op_get_link,
0da34b6d 1957 .get_strings = myri10ge_get_strings,
b9f2c044 1958 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1959 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1960 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d
BG		 1961 .get_msglevel = myri10ge_get_msglevel,
1962 .get_flags = ethtool_op_get_flags,
1437ce39 1963 .set_flags = myri10ge_set_flags
0da34b6d
BG		 1964};
1965
b53bef84 1966static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1967{
b53bef84 1968 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1969 struct myri10ge_cmd cmd;
b53bef84 1970 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1971 int tx_ring_size, rx_ring_size;
1972 int tx_ring_entries, rx_ring_entries;
0dcffac1 1973 int i, slice, status;
0da34b6d
BG		 1974 size_t bytes;
1975
0da34b6d 1976 /* get ring sizes */
0dcffac1
BG		 1977 slice = ss - mgp->ss;
1978 cmd.data0 = slice;
0da34b6d
BG		 1979 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1980 tx_ring_size = cmd.data0;
0dcffac1 1981 cmd.data0 = slice;
0da34b6d 1982 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1983 if (status != 0)
1984 return status;
0da34b6d
BG		 1985 rx_ring_size = cmd.data0;
1986
1987 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1988 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1989 ss->tx.mask = tx_ring_entries - 1;
1990 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1991
355c7265
BG		 1992 status = -ENOMEM;
1993
0da34b6d
BG		 1994 /* allocate the host shadow rings */
1995
1996 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1997 * sizeof(*ss->tx.req_list);
1998 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1999 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 2000 goto abort_with_nothing;
2001
2002 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 2003 ss->tx.req_list = (struct mcp_kreq_ether_send *)
2004 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 2005 ss->tx.queue_active = 0;
0da34b6d 2006
b53bef84
BG		 2007 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
2008 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
2009 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 2010 goto abort_with_tx_req_bytes;
2011
b53bef84
BG		 2012 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
2013 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
2014 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 2015 goto abort_with_rx_small_shadow;
2016
2017 /* allocate the host info rings */
2018
b53bef84
BG		 2019 bytes = tx_ring_entries * sizeof(*ss->tx.info);
2020 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
2021 if (ss->tx.info == NULL)
0da34b6d
BG		 2022 goto abort_with_rx_big_shadow;
2023
b53bef84
BG		 2024 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
2025 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
2026 if (ss->rx_small.info == NULL)
0da34b6d
BG		 2027 goto abort_with_tx_info;
2028
b53bef84
BG		 2029 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
2030 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
2031 if (ss->rx_big.info == NULL)
0da34b6d
BG		 2032 goto abort_with_rx_small_info;
2033
2034 /* Fill the receive rings */
b53bef84
BG		 2035 ss->rx_big.cnt = 0;
2036 ss->rx_small.cnt = 0;
2037 ss->rx_big.fill_cnt = 0;
2038 ss->rx_small.fill_cnt = 0;
2039 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2040 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2041 ss->rx_small.watchdog_needed = 0;
2042 ss->rx_big.watchdog_needed = 0;
2043 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 2044 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 2045
b53bef84 2046 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
78ca90ea
JP		 2047 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2048 slice, ss->rx_small.fill_cnt);
c7dab99b 2049 goto abort_with_rx_small_ring;
0da34b6d
BG		 2050 }
2051
b53bef84
BG		 2052 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2053 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
78ca90ea
JP		 2054 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2055 slice, ss->rx_big.fill_cnt);
c7dab99b 2056 goto abort_with_rx_big_ring;
0da34b6d
BG		 2057 }
2058
2059 return 0;
2060
2061abort_with_rx_big_ring:
b53bef84
BG		 2062 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2063 int idx = i & ss->rx_big.mask;
2064 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2065 mgp->big_bytes);
b53bef84 2066 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2067 }
2068
2069abort_with_rx_small_ring:
b53bef84
BG		 2070 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2071 int idx = i & ss->rx_small.mask;
2072 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2073 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2074 put_page(ss->rx_small.info[idx].page);
0da34b6d 2075 }
c7dab99b 2076
b53bef84 2077 kfree(ss->rx_big.info);
0da34b6d
BG		 2078
2079abort_with_rx_small_info:
b53bef84 2080 kfree(ss->rx_small.info);
0da34b6d
BG		 2081
2082abort_with_tx_info:
b53bef84 2083 kfree(ss->tx.info);
0da34b6d
BG		 2084
2085abort_with_rx_big_shadow:
b53bef84 2086 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2087
2088abort_with_rx_small_shadow:
b53bef84 2089 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2090
2091abort_with_tx_req_bytes:
b53bef84
BG		 2092 kfree(ss->tx.req_bytes);
2093 ss->tx.req_bytes = NULL;
2094 ss->tx.req_list = NULL;
0da34b6d
BG		 2095
2096abort_with_nothing:
2097 return status;
2098}
2099
b53bef84 2100static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2101{
b53bef84 2102 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2103 struct sk_buff *skb;
2104 struct myri10ge_tx_buf *tx;
2105 int i, len, idx;
2106
0dcffac1
BG		 2107 /* If not allocated, skip it */
2108 if (ss->tx.req_list == NULL)
2109 return;
2110
b53bef84
BG		 2111 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2112 idx = i & ss->rx_big.mask;
2113 if (i == ss->rx_big.fill_cnt - 1)
2114 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2115 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2116 mgp->big_bytes);
b53bef84 2117 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2118 }
2119
b53bef84
BG		 2120 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2121 idx = i & ss->rx_small.mask;
2122 if (i == ss->rx_small.fill_cnt - 1)
2123 ss->rx_small.info[idx].page_offset =
c7dab99b 2124 MYRI10GE_ALLOC_SIZE;
b53bef84 2125 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2126 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2127 put_page(ss->rx_small.info[idx].page);
c7dab99b 2128 }
b53bef84 2129 tx = &ss->tx;
0da34b6d
BG		 2130 while (tx->done != tx->req) {
2131 idx = tx->done & tx->mask;
2132 skb = tx->info[idx].skb;
2133
2134 /* Mark as free */
2135 tx->info[idx].skb = NULL;
2136 tx->done++;
c755b4b6
FT		 2137 len = dma_unmap_len(&tx->info[idx], len);
2138 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 2139 if (skb) {
b53bef84 2140 ss->stats.tx_dropped++;
0da34b6d
BG		 2141 dev_kfree_skb_any(skb);
2142 if (len)
2143 pci_unmap_single(mgp->pdev,
c755b4b6 2144 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2145 bus), len,
2146 PCI_DMA_TODEVICE);
2147 } else {
2148 if (len)
2149 pci_unmap_page(mgp->pdev,
c755b4b6 2150 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2151 bus), len,
2152 PCI_DMA_TODEVICE);
2153 }
2154 }
b53bef84 2155 kfree(ss->rx_big.info);
0da34b6d 2156
b53bef84 2157 kfree(ss->rx_small.info);
0da34b6d 2158
b53bef84 2159 kfree(ss->tx.info);
0da34b6d 2160
b53bef84 2161 kfree(ss->rx_big.shadow);
0da34b6d 2162
b53bef84 2163 kfree(ss->rx_small.shadow);
0da34b6d 2164
b53bef84
BG		 2165 kfree(ss->tx.req_bytes);
2166 ss->tx.req_bytes = NULL;
2167 ss->tx.req_list = NULL;
0da34b6d
BG		 2168}
2169
df30a740
BG		 2170static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2171{
2172 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2173 struct myri10ge_slice_state *ss;
2174 struct net_device *netdev = mgp->dev;
2175 int i;
df30a740
BG		 2176 int status;
2177
0dcffac1
BG		 2178 mgp->msi_enabled = 0;
2179 mgp->msix_enabled = 0;
2180 status = 0;
df30a740 2181 if (myri10ge_msi) {
0dcffac1
BG		 2182 if (mgp->num_slices > 1) {
2183 status =
2184 pci_enable_msix(pdev, mgp->msix_vectors,
2185 mgp->num_slices);
2186 if (status == 0) {
2187 mgp->msix_enabled = 1;
2188 } else {
2189 dev_err(&pdev->dev,
2190 "Error %d setting up MSI-X\n", status);
2191 return status;
2192 }
2193 }
2194 if (mgp->msix_enabled == 0) {
2195 status = pci_enable_msi(pdev);
2196 if (status != 0) {
2197 dev_err(&pdev->dev,
2198 "Error %d setting up MSI; falling back to xPIC\n",
2199 status);
2200 } else {
2201 mgp->msi_enabled = 1;
2202 }
2203 }
df30a740 2204 }
0dcffac1
BG		 2205 if (mgp->msix_enabled) {
2206 for (i = 0; i < mgp->num_slices; i++) {
2207 ss = &mgp->ss[i];
2208 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2209 "%s:slice-%d", netdev->name, i);
2210 status = request_irq(mgp->msix_vectors[i].vector,
2211 myri10ge_intr, 0, ss->irq_desc,
2212 ss);
2213 if (status != 0) {
2214 dev_err(&pdev->dev,
2215 "slice %d failed to allocate IRQ\n", i);
2216 i--;
2217 while (i >= 0) {
2218 free_irq(mgp->msix_vectors[i].vector,
2219 &mgp->ss[i]);
2220 i--;
2221 }
2222 pci_disable_msix(pdev);
2223 return status;
2224 }
2225 }
2226 } else {
2227 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2228 mgp->dev->name, &mgp->ss[0]);
2229 if (status != 0) {
2230 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2231 if (mgp->msi_enabled)
2232 pci_disable_msi(pdev);
2233 }
df30a740
BG		 2234 }
2235 return status;
2236}
2237
2238static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2239{
2240 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2241 int i;
df30a740 2242
0dcffac1
BG		 2243 if (mgp->msix_enabled) {
2244 for (i = 0; i < mgp->num_slices; i++)
2245 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2246 } else {
2247 free_irq(pdev->irq, &mgp->ss[0]);
2248 }
df30a740
BG		 2249 if (mgp->msi_enabled)
2250 pci_disable_msi(pdev);
0dcffac1
BG		 2251 if (mgp->msix_enabled)
2252 pci_disable_msix(pdev);
df30a740
BG		 2253}
2254
1e6e9342
AG		 2255static int
2256myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2257 void **ip_hdr, void **tcpudp_hdr,
2258 u64 * hdr_flags, void *priv)
2259{
2260 struct ethhdr *eh;
2261 struct vlan_ethhdr *veh;
2262 struct iphdr *iph;
2263 u8 *va = page_address(frag->page) + frag->page_offset;
2264 unsigned long ll_hlen;
66341fff
AV		 2265 /* passed opaque through lro_receive_frags() */
2266 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2267
2268 /* find the mac header, aborting if not IPv4 */
2269
2270 eh = (struct ethhdr *)va;
2271 *mac_hdr = eh;
2272 ll_hlen = ETH_HLEN;
2273 if (eh->h_proto != htons(ETH_P_IP)) {
2274 if (eh->h_proto == htons(ETH_P_8021Q)) {
2275 veh = (struct vlan_ethhdr *)va;
2276 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2277 return -1;
2278
2279 ll_hlen += VLAN_HLEN;
2280
2281 /*
2282 * HW checksum starts ETH_HLEN bytes into
2283 * frame, so we must subtract off the VLAN
2284 * header's checksum before csum can be used
2285 */
2286 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2287 VLAN_HLEN, 0));
2288 } else {
2289 return -1;
2290 }
2291 }
2292 *hdr_flags = LRO_IPV4;
2293
2294 iph = (struct iphdr *)(va + ll_hlen);
2295 *ip_hdr = iph;
2296 if (iph->protocol != IPPROTO_TCP)
2297 return -1;
bcb09dc2
BG		 2298 if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2299 return -1;
1e6e9342
AG		 2300 *hdr_flags |= LRO_TCP;
2301 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2302
2303 /* verify the IP checksum */
2304 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2305 return -1;
2306
2307 /* verify the checksum */
2308 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2309 ntohs(iph->tot_len) - (iph->ihl << 2),
2310 IPPROTO_TCP, csum)))
2311 return -1;
2312
2313 return 0;
2314}
2315
77929732
BG		 2316static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2317{
2318 struct myri10ge_cmd cmd;
2319 struct myri10ge_slice_state *ss;
2320 int status;
2321
2322 ss = &mgp->ss[slice];
236bb5e6
BG		 2323 status = 0;
2324 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2325 cmd.data0 = slice;
2326 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2327 &cmd, 0);
2328 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2329 (mgp->sram + cmd.data0);
2330 }
77929732
BG		 2331 cmd.data0 = slice;
2332 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2333 &cmd, 0);
2334 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2335 (mgp->sram + cmd.data0);
2336
2337 cmd.data0 = slice;
2338 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2339 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2340 (mgp->sram + cmd.data0);
2341
236bb5e6
BG		 2342 ss->tx.send_go = (__iomem __be32 *)
2343 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2344 ss->tx.send_stop = (__iomem __be32 *)
2345 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2346 return status;
2347
2348}
2349
2350static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2351{
2352 struct myri10ge_cmd cmd;
2353 struct myri10ge_slice_state *ss;
2354 int status;
2355
2356 ss = &mgp->ss[slice];
2357 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2358 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2359 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2360 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2361 if (status == -ENOSYS) {
2362 dma_addr_t bus = ss->fw_stats_bus;
2363 if (slice != 0)
2364 return -EINVAL;
2365 bus += offsetof(struct mcp_irq_data, send_done_count);
2366 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2367 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2368 status = myri10ge_send_cmd(mgp,
2369 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2370 &cmd, 0);
2371 /* Firmware cannot support multicast without STATS_DMA_V2 */
2372 mgp->fw_multicast_support = 0;
2373 } else {
2374 mgp->fw_multicast_support = 1;
2375 }
2376 return 0;
2377}
77929732 2378
0da34b6d
BG		 2379static int myri10ge_open(struct net_device *dev)
2380{
0dcffac1 2381 struct myri10ge_slice_state *ss;
b53bef84 2382 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2383 struct myri10ge_cmd cmd;
0dcffac1
BG		 2384 int i, status, big_pow2, slice;
2385 u8 *itable;
1e6e9342 2386 struct net_lro_mgr *lro_mgr;
0da34b6d 2387
0da34b6d
BG		 2388 if (mgp->running != MYRI10GE_ETH_STOPPED)
2389 return -EBUSY;
2390
2391 mgp->running = MYRI10GE_ETH_STARTING;
2392 status = myri10ge_reset(mgp);
2393 if (status != 0) {
78ca90ea 2394 netdev_err(dev, "failed reset\n");
df30a740 2395 goto abort_with_nothing;
0da34b6d
BG		 2396 }
2397
0dcffac1
BG		 2398 if (mgp->num_slices > 1) {
2399 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2400 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2401 if (mgp->dev->real_num_tx_queues > 1)
2402 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2403 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2404 &cmd, 0);
2405 if (status != 0) {
78ca90ea 2406 netdev_err(dev, "failed to set number of slices\n");
0dcffac1
BG		 2407 goto abort_with_nothing;
2408 }
2409 /* setup the indirection table */
2410 cmd.data0 = mgp->num_slices;
2411 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2412 &cmd, 0);
2413
2414 status |= myri10ge_send_cmd(mgp,
2415 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2416 &cmd, 0);
2417 if (status != 0) {
78ca90ea 2418 netdev_err(dev, "failed to setup rss tables\n");
236bb5e6 2419 goto abort_with_nothing;
0dcffac1
BG		 2420 }
2421
2422 /* just enable an identity mapping */
2423 itable = mgp->sram + cmd.data0;
2424 for (i = 0; i < mgp->num_slices; i++)
2425 __raw_writeb(i, &itable[i]);
2426
2427 cmd.data0 = 1;
2428 cmd.data1 = myri10ge_rss_hash;
2429 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2430 &cmd, 0);
2431 if (status != 0) {
78ca90ea 2432 netdev_err(dev, "failed to enable slices\n");
0dcffac1
BG		 2433 goto abort_with_nothing;
2434 }
2435 }
2436
df30a740
BG		 2437 status = myri10ge_request_irq(mgp);
2438 if (status != 0)
2439 goto abort_with_nothing;
2440
0da34b6d
BG		 2441 /* decide what small buffer size to use. For good TCP rx
2442 * performance, it is important to not receive 1514 byte
2443 * frames into jumbo buffers, as it confuses the socket buffer
2444 * accounting code, leading to drops and erratic performance.
2445 */
2446
2447 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2448 /* enough for a TCP header */
2449 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2450 ? (128 - MXGEFW_PAD)
2451 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2452 else
de3c4507
BG		 2453 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2454 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2455
2456 /* Override the small buffer size? */
2457 if (myri10ge_small_bytes > 0)
2458 mgp->small_bytes = myri10ge_small_bytes;
2459
0da34b6d
BG		 2460 /* Firmware needs the big buff size as a power of 2. Lie and
2461 * tell him the buffer is larger, because we only use 1
2462 * buffer/pkt, and the mtu will prevent overruns.
2463 */
13348bee 2464 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2465 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2466 while (!is_power_of_2(big_pow2))
c7dab99b 2467 big_pow2++;
13348bee 2468 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2469 } else {
2470 big_pow2 = MYRI10GE_ALLOC_SIZE;
2471 mgp->big_bytes = big_pow2;
2472 }
2473
0dcffac1
BG		 2474 /* setup the per-slice data structures */
2475 for (slice = 0; slice < mgp->num_slices; slice++) {
2476 ss = &mgp->ss[slice];
2477
2478 status = myri10ge_get_txrx(mgp, slice);
2479 if (status != 0) {
78ca90ea 2480 netdev_err(dev, "failed to get ring sizes or locations\n");
0dcffac1
BG		 2481 goto abort_with_rings;
2482 }
2483 status = myri10ge_allocate_rings(ss);
2484 if (status != 0)
2485 goto abort_with_rings;
236bb5e6
BG		 2486
2487 /* only firmware which supports multiple TX queues
2488 * supports setting up the tx stats on non-zero
2489 * slices */
2490 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2491 status = myri10ge_set_stats(mgp, slice);
2492 if (status) {
78ca90ea 2493 netdev_err(dev, "Couldn't set stats DMA\n");
0dcffac1
BG		 2494 goto abort_with_rings;
2495 }
2496
2497 lro_mgr = &ss->rx_done.lro_mgr;
2498 lro_mgr->dev = dev;
2499 lro_mgr->features = LRO_F_NAPI;
2500 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2501 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2502 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2503 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2504 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2505 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
636d2f68 2506 lro_mgr->frag_align_pad = 2;
0dcffac1
BG		 2507 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2508 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2509
2510 /* must happen prior to any irq */
2511 napi_enable(&(ss)->napi);
2512 }
0da34b6d
BG		 2513
2514 /* now give firmware buffers sizes, and MTU */
2515 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2516 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2517 cmd.data0 = mgp->small_bytes;
2518 status |=
2519 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2520 cmd.data0 = big_pow2;
2521 status |=
2522 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2523 if (status) {
78ca90ea 2524 netdev_err(dev, "Couldn't set buffer sizes\n");
0da34b6d
BG		 2525 goto abort_with_rings;
2526 }
2527
0dcffac1
BG		 2528 /*
2529 * Set Linux style TSO mode; this is needed only on newer
2530 * firmware versions. Older versions default to Linux
2531 * style TSO
2532 */
2533 cmd.data0 = 0;
2534 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2535 if (status && status != -ENOSYS) {
78ca90ea 2536 netdev_err(dev, "Couldn't set TSO mode\n");
0da34b6d
BG		 2537 goto abort_with_rings;
2538 }
2539
66341fff 2540 mgp->link_state = ~0U;
0da34b6d
BG		 2541 mgp->rdma_tags_available = 15;
2542
0da34b6d
BG		 2543 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2544 if (status) {
78ca90ea 2545 netdev_err(dev, "Couldn't bring up link\n");
0da34b6d
BG		 2546 goto abort_with_rings;
2547 }
2548
0da34b6d
BG		 2549 mgp->running = MYRI10GE_ETH_RUNNING;
2550 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2551 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2552 netif_tx_wake_all_queues(dev);
2553
0da34b6d
BG		 2554 return 0;
2555
2556abort_with_rings:
051d36f3
BG		 2557 while (slice) {
2558 slice--;
2559 napi_disable(&mgp->ss[slice].napi);
2560 }
0dcffac1
BG		 2561 for (i = 0; i < mgp->num_slices; i++)
2562 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2563
df30a740
BG		 2564 myri10ge_free_irq(mgp);
2565
0da34b6d
BG		 2566abort_with_nothing:
2567 mgp->running = MYRI10GE_ETH_STOPPED;
2568 return -ENOMEM;
2569}
2570
2571static int myri10ge_close(struct net_device *dev)
2572{
b53bef84 2573 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2574 struct myri10ge_cmd cmd;
2575 int status, old_down_cnt;
0dcffac1 2576 int i;
0da34b6d 2577
0da34b6d
BG		 2578 if (mgp->running != MYRI10GE_ETH_RUNNING)
2579 return 0;
2580
0dcffac1 2581 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2582 return 0;
2583
2584 del_timer_sync(&mgp->watchdog_timer);
2585 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2586 for (i = 0; i < mgp->num_slices; i++) {
2587 napi_disable(&mgp->ss[i].napi);
2588 }
0da34b6d 2589 netif_carrier_off(dev);
236bb5e6
BG		 2590
2591 netif_tx_stop_all_queues(dev);
d0234215
BG		 2592 if (mgp->rebooted == 0) {
2593 old_down_cnt = mgp->down_cnt;
2594 mb();
2595 status =
2596 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2597 if (status)
78ca90ea 2598 netdev_err(dev, "Couldn't bring down link\n");
0da34b6d 2599
d0234215
BG		 2600 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2601 HZ);
2602 if (old_down_cnt == mgp->down_cnt)
78ca90ea 2603 netdev_err(dev, "never got down irq\n");
d0234215 2604 }
0da34b6d 2605 netif_tx_disable(dev);
df30a740 2606 myri10ge_free_irq(mgp);
0dcffac1
BG		 2607 for (i = 0; i < mgp->num_slices; i++)
2608 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2609
2610 mgp->running = MYRI10GE_ETH_STOPPED;
2611 return 0;
2612}
2613
2614/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2615 * backwards one at a time and handle ring wraps */
2616
2617static inline void
2618myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2619 struct mcp_kreq_ether_send *src, int cnt)
2620{
2621 int idx, starting_slot;
2622 starting_slot = tx->req;
2623 while (cnt > 1) {
2624 cnt--;
2625 idx = (starting_slot + cnt) & tx->mask;
2626 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2627 mb();
2628 }
2629}
2630
2631/*
2632 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2633 * at most 32 bytes at a time, so as to avoid involving the software
2634 * pio handler in the nic. We re-write the first segment's flags
2635 * to mark them valid only after writing the entire chain.
2636 */
2637
2638static inline void
2639myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2640 int cnt)
2641{
2642 int idx, i;
2643 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2644 struct mcp_kreq_ether_send *srcp;
2645 u8 last_flags;
2646
2647 idx = tx->req & tx->mask;
2648
2649 last_flags = src->flags;
2650 src->flags = 0;
2651 mb();
2652 dst = dstp = &tx->lanai[idx];
2653 srcp = src;
2654
2655 if ((idx + cnt) < tx->mask) {
2656 for (i = 0; i < (cnt - 1); i += 2) {
2657 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2658 mb(); /* force write every 32 bytes */
2659 srcp += 2;
2660 dstp += 2;
2661 }
2662 } else {
2663 /* submit all but the first request, and ensure
2664 * that it is submitted below */
2665 myri10ge_submit_req_backwards(tx, src, cnt);
2666 i = 0;
2667 }
2668 if (i < cnt) {
2669 /* submit the first request */
2670 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2671 mb(); /* barrier before setting valid flag */
2672 }
2673
2674 /* re-write the last 32-bits with the valid flags */
2675 src->flags = last_flags;
40f6cff5 2676 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2677 tx->req += cnt;
2678 mb();
2679}
2680
0da34b6d
BG		 2681/*
2682 * Transmit a packet. We need to split the packet so that a single
b53bef84 2683 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2684 * counting tricky. So rather than try to count segments up front, we
2685 * just give up if there are too few segments to hold a reasonably
2686 * fragmented packet currently available. If we run
2687 * out of segments while preparing a packet for DMA, we just linearize
2688 * it and try again.
2689 */
2690
61357325
SH		 2691static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2692 struct net_device *dev)
0da34b6d
BG		 2693{
2694 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2695 struct myri10ge_slice_state *ss;
0da34b6d 2696 struct mcp_kreq_ether_send *req;
b53bef84 2697 struct myri10ge_tx_buf *tx;
0da34b6d 2698 struct skb_frag_struct *frag;
236bb5e6 2699 struct netdev_queue *netdev_queue;
0da34b6d 2700 dma_addr_t bus;
40f6cff5
AV		 2701 u32 low;
2702 __be32 high_swapped;
0da34b6d
BG		 2703 unsigned int len;
2704 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2705 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2706 int cum_len, seglen, boundary, rdma_count;
2707 u8 flags, odd_flag;
2708
236bb5e6 2709 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2710 ss = &mgp->ss[queue];
2711 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2712 tx = &ss->tx;
236bb5e6 2713
0da34b6d
BG		 2714again:
2715 req = tx->req_list;
2716 avail = tx->mask - 1 - (tx->req - tx->done);
2717
2718 mss = 0;
2719 max_segments = MXGEFW_MAX_SEND_DESC;
2720
917690cd 2721 if (skb_is_gso(skb)) {
7967168c 2722 mss = skb_shinfo(skb)->gso_size;
917690cd 2723 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2724 }
0da34b6d
BG		 2725
2726 if ((unlikely(avail < max_segments))) {
2727 /* we are out of transmit resources */
b53bef84 2728 tx->stop_queue++;
236bb5e6 2729 netif_tx_stop_queue(netdev_queue);
5b548140 2730 return NETDEV_TX_BUSY;
0da34b6d
BG		 2731 }
2732
2733 /* Setup checksum offloading, if needed */
2734 cksum_offset = 0;
2735 pseudo_hdr_offset = 0;
2736 odd_flag = 0;
2737 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2738 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0d0b1672 2739 cksum_offset = skb_checksum_start_offset(skb);
ff1dcadb 2740 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2741 /* If the headers are excessively large, then we must
2742 * fall back to a software checksum */
4f93fde0
BG		 2743 if (unlikely(!mss && (cksum_offset > 255 ||
2744 pseudo_hdr_offset > 127))) {
84fa7933 2745 if (skb_checksum_help(skb))
0da34b6d
BG		 2746 goto drop;
2747 cksum_offset = 0;
2748 pseudo_hdr_offset = 0;
2749 } else {
0da34b6d
BG		 2750 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2751 flags |= MXGEFW_FLAGS_CKSUM;
2752 }
2753 }
2754
2755 cum_len = 0;
2756
0da34b6d
BG		 2757 if (mss) { /* TSO */
2758 /* this removes any CKSUM flag from before */
2759 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2760
2761 /* negative cum_len signifies to the
2762 * send loop that we are still in the
2763 * header portion of the TSO packet.
4f93fde0 2764 * TSO header can be at most 1KB long */
ab6a5bb6 2765 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2766
4f93fde0
BG		 2767 /* for IPv6 TSO, the checksum offset stores the
2768 * TCP header length, to save the firmware from
2769 * the need to parse the headers */
2770 if (skb_is_gso_v6(skb)) {
2771 cksum_offset = tcp_hdrlen(skb);
2772 /* Can only handle headers <= max_tso6 long */
2773 if (unlikely(-cum_len > mgp->max_tso6))
2774 return myri10ge_sw_tso(skb, dev);
2775 }
0da34b6d
BG		 2776 /* for TSO, pseudo_hdr_offset holds mss.
2777 * The firmware figures out where to put
2778 * the checksum by parsing the header. */
40f6cff5 2779 pseudo_hdr_offset = mss;
0da34b6d 2780 } else
0da34b6d
BG		 2781 /* Mark small packets, and pad out tiny packets */
2782 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2783 flags |= MXGEFW_FLAGS_SMALL;
2784
2785 /* pad frames to at least ETH_ZLEN bytes */
2786 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2787 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2788 /* The packet is gone, so we must
2789 * return 0 */
b53bef84 2790 ss->stats.tx_dropped += 1;
6ed10654 2791 return NETDEV_TX_OK;
0da34b6d
BG		 2792 }
2793 /* adjust the len to account for the zero pad
2794 * so that the nic can know how long it is */
2795 skb->len = ETH_ZLEN;
2796 }
2797 }
2798
2799 /* map the skb for DMA */
e743d313 2800 len = skb_headlen(skb);
0da34b6d
BG		 2801 idx = tx->req & tx->mask;
2802 tx->info[idx].skb = skb;
2803 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
c755b4b6
FT		 2804 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2805 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2806
2807 frag_cnt = skb_shinfo(skb)->nr_frags;
2808 frag_idx = 0;
2809 count = 0;
2810 rdma_count = 0;
2811
2812 /* "rdma_count" is the number of RDMAs belonging to the
2813 * current packet BEFORE the current send request. For
2814 * non-TSO packets, this is equal to "count".
2815 * For TSO packets, rdma_count needs to be reset
2816 * to 0 after a segment cut.
2817 *
2818 * The rdma_count field of the send request is
2819 * the number of RDMAs of the packet starting at
2820 * that request. For TSO send requests with one ore more cuts
2821 * in the middle, this is the number of RDMAs starting
2822 * after the last cut in the request. All previous
2823 * segments before the last cut implicitly have 1 RDMA.
2824 *
2825 * Since the number of RDMAs is not known beforehand,
2826 * it must be filled-in retroactively - after each
2827 * segmentation cut or at the end of the entire packet.
2828 */
2829
2830 while (1) {
2831 /* Break the SKB or Fragment up into pieces which
b53bef84 2832 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2833 low = MYRI10GE_LOWPART_TO_U32(bus);
2834 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2835 while (len) {
2836 u8 flags_next;
2837 int cum_len_next;
2838
2839 if (unlikely(count == max_segments))
2840 goto abort_linearize;
2841
b53bef84
BG		 2842 boundary =
2843 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2844 seglen = boundary - low;
2845 if (seglen > len)
2846 seglen = len;
2847 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2848 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2849 if (mss) { /* TSO */
2850 (req - rdma_count)->rdma_count = rdma_count + 1;
2851
2852 if (likely(cum_len >= 0)) { /* payload */
2853 int next_is_first, chop;
2854
2855 chop = (cum_len_next > mss);
2856 cum_len_next = cum_len_next % mss;
2857 next_is_first = (cum_len_next == 0);
2858 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2859 flags_next |= next_is_first *
2860 MXGEFW_FLAGS_FIRST;
2861 rdma_count |= -(chop | next_is_first);
2862 rdma_count += chop & !next_is_first;
2863 } else if (likely(cum_len_next >= 0)) { /* header ends */
2864 int small;
2865
2866 rdma_count = -1;
2867 cum_len_next = 0;
2868 seglen = -cum_len;
2869 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2870 flags_next = MXGEFW_FLAGS_TSO_PLD |
2871 MXGEFW_FLAGS_FIRST |
2872 (small * MXGEFW_FLAGS_SMALL);
2873 }
2874 }
0da34b6d
BG		 2875 req->addr_high = high_swapped;
2876 req->addr_low = htonl(low);
40f6cff5 2877 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2878 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2879 req->rdma_count = 1;
2880 req->length = htons(seglen);
2881 req->cksum_offset = cksum_offset;
2882 req->flags = flags | ((cum_len & 1) * odd_flag);
2883
2884 low += seglen;
2885 len -= seglen;
2886 cum_len = cum_len_next;
2887 flags = flags_next;
2888 req++;
2889 count++;
2890 rdma_count++;
4f93fde0
BG		 2891 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2892 if (unlikely(cksum_offset > seglen))
2893 cksum_offset -= seglen;
2894 else
2895 cksum_offset = 0;
2896 }
0da34b6d
BG		 2897 }
2898 if (frag_idx == frag_cnt)
2899 break;
2900
2901 /* map next fragment for DMA */
2902 idx = (count + tx->req) & tx->mask;
2903 frag = &skb_shinfo(skb)->frags[frag_idx];
2904 frag_idx++;
2905 len = frag->size;
2906 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2907 len, PCI_DMA_TODEVICE);
c755b4b6
FT		 2908 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2909 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2910 }
2911
2912 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2913 if (mss)
2914 do {
2915 req--;
2916 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2917 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2918 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2919 idx = ((count - 1) + tx->req) & tx->mask;
2920 tx->info[idx].last = 1;
e454e7e2 2921 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2922 /* if using multiple tx queues, make sure NIC polls the
2923 * current slice */
2924 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2925 tx->queue_active = 1;
2926 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2927 mb();
6824a105 2928 mmiowb();
236bb5e6 2929 }
0da34b6d
BG		 2930 tx->pkt_start++;
2931 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2932 tx->stop_queue++;
236bb5e6 2933 netif_tx_stop_queue(netdev_queue);
0da34b6d 2934 }
6ed10654 2935 return NETDEV_TX_OK;
0da34b6d
BG		 2936
2937abort_linearize:
2938 /* Free any DMA resources we've alloced and clear out the skb
2939 * slot so as to not trip up assertions, and to avoid a
2940 * double-free if linearizing fails */
2941
2942 last_idx = (idx + 1) & tx->mask;
2943 idx = tx->req & tx->mask;
2944 tx->info[idx].skb = NULL;
2945 do {
c755b4b6 2946 len = dma_unmap_len(&tx->info[idx], len);
0da34b6d
BG		 2947 if (len) {
2948 if (tx->info[idx].skb != NULL)
2949 pci_unmap_single(mgp->pdev,
c755b4b6 2950 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2951 bus), len,
2952 PCI_DMA_TODEVICE);
2953 else
2954 pci_unmap_page(mgp->pdev,
c755b4b6 2955 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2956 bus), len,
2957 PCI_DMA_TODEVICE);
c755b4b6 2958 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d
BG		 2959 tx->info[idx].skb = NULL;
2960 }
2961 idx = (idx + 1) & tx->mask;
2962 } while (idx != last_idx);
89114afd 2963 if (skb_is_gso(skb)) {
78ca90ea 2964 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
0da34b6d
BG		 2965 goto drop;
2966 }
2967
bec0e859 2968 if (skb_linearize(skb))
0da34b6d
BG		 2969 goto drop;
2970
b53bef84 2971 tx->linearized++;
0da34b6d
BG		 2972 goto again;
2973
2974drop:
2975 dev_kfree_skb_any(skb);
b53bef84 2976 ss->stats.tx_dropped += 1;
6ed10654 2977 return NETDEV_TX_OK;
0da34b6d
BG		 2978
2979}
2980
61357325
SH		 2981static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2982 struct net_device *dev)
4f93fde0
BG		 2983{
2984 struct sk_buff *segs, *curr;
b53bef84 2985 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 2986 struct myri10ge_slice_state *ss;
61357325 2987 netdev_tx_t status;
4f93fde0
BG		 2988
2989 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2990 if (IS_ERR(segs))
4f93fde0
BG		 2991 goto drop;
2992
2993 while (segs) {
2994 curr = segs;
2995 segs = segs->next;
2996 curr->next = NULL;
2997 status = myri10ge_xmit(curr, dev);
2998 if (status != 0) {
2999 dev_kfree_skb_any(curr);
3000 if (segs != NULL) {
3001 curr = segs;
3002 segs = segs->next;
3003 curr->next = NULL;
3004 dev_kfree_skb_any(segs);
3005 }
3006 goto drop;
3007 }
3008 }
3009 dev_kfree_skb_any(skb);
ec634fe3 3010 return NETDEV_TX_OK;
4f93fde0
BG		 3011
3012drop:
d6279c88 3013 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 3014 dev_kfree_skb_any(skb);
d6279c88 3015 ss->stats.tx_dropped += 1;
ec634fe3 3016 return NETDEV_TX_OK;
4f93fde0
BG		 3017}
3018
0da34b6d
BG		 3019static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
3020{
3021 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1 3022 struct myri10ge_slice_netstats *slice_stats;
6dc34941 3023 struct net_device_stats *stats = &dev->stats;
0dcffac1
BG		 3024 int i;
3025
59081825 3026 spin_lock(&mgp->stats_lock);
0dcffac1
BG		 3027 memset(stats, 0, sizeof(*stats));
3028 for (i = 0; i < mgp->num_slices; i++) {
3029 slice_stats = &mgp->ss[i].stats;
3030 stats->rx_packets += slice_stats->rx_packets;
3031 stats->tx_packets += slice_stats->tx_packets;
3032 stats->rx_bytes += slice_stats->rx_bytes;
3033 stats->tx_bytes += slice_stats->tx_bytes;
3034 stats->rx_dropped += slice_stats->rx_dropped;
3035 stats->tx_dropped += slice_stats->tx_dropped;
3036 }
59081825 3037 spin_unlock(&mgp->stats_lock);
0dcffac1 3038 return stats;
0da34b6d
BG		 3039}
3040
3041static void myri10ge_set_multicast_list(struct net_device *dev)
3042{
b53bef84 3043 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 3044 struct myri10ge_cmd cmd;
22bedad3 3045 struct netdev_hw_addr *ha;
6250223e 3046 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 3047 int err;
3048
0da34b6d
BG		 3049 /* can be called from atomic contexts,
3050 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 3051 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3052
3053 /* This firmware is known to not support multicast */
2f76216f 3054 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 3055 return;
3056
3057 /* Disable multicast filtering */
3058
3059 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3060 if (err != 0) {
78ca90ea
JP		 3061 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3062 err);
85a7ea1b
BG		 3063 goto abort;
3064 }
3065
2f76216f 3066 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3067 /* request to disable multicast filtering, so quit here */
3068 return;
3069 }
3070
3071 /* Flush the filters */
3072
3073 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3074 &cmd, 1);
3075 if (err != 0) {
78ca90ea
JP		 3076 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3077 err);
85a7ea1b
BG		 3078 goto abort;
3079 }
3080
3081 /* Walk the multicast list, and add each address */
22bedad3
JP		 3082 netdev_for_each_mc_addr(ha, dev) {
3083 memcpy(data, &ha->addr, 6);
40f6cff5
AV		 3084 cmd.data0 = ntohl(data[0]);
3085 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3086 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3087 &cmd, 1);
3088
3089 if (err != 0) {
78ca90ea 3090 netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
22bedad3 3091 err, ha->addr);
85a7ea1b
BG		 3092 goto abort;
3093 }
3094 }
3095 /* Enable multicast filtering */
3096 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3097 if (err != 0) {
78ca90ea
JP		 3098 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3099 err);
85a7ea1b
BG		 3100 goto abort;
3101 }
3102
3103 return;
3104
3105abort:
3106 return;
0da34b6d
BG		 3107}
3108
3109static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3110{
3111 struct sockaddr *sa = addr;
3112 struct myri10ge_priv *mgp = netdev_priv(dev);
3113 int status;
3114
3115 if (!is_valid_ether_addr(sa->sa_data))
3116 return -EADDRNOTAVAIL;
3117
3118 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3119 if (status != 0) {
78ca90ea
JP		 3120 netdev_err(dev, "changing mac address failed with %d\n",
3121 status);
0da34b6d
BG		 3122 return status;
3123 }
3124
3125 /* change the dev structure */
3126 memcpy(dev->dev_addr, sa->sa_data, 6);
3127 return 0;
3128}
3129
3130static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3131{
3132 struct myri10ge_priv *mgp = netdev_priv(dev);
3133 int error = 0;
3134
3135 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
78ca90ea 3136 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
0da34b6d
BG		 3137 return -EINVAL;
3138 }
78ca90ea 3139 netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
0da34b6d
BG		 3140 if (mgp->running) {
3141 /* if we change the mtu on an active device, we must
3142 * reset the device so the firmware sees the change */
3143 myri10ge_close(dev);
3144 dev->mtu = new_mtu;
3145 myri10ge_open(dev);
3146 } else
3147 dev->mtu = new_mtu;
3148
3149 return error;
3150}
3151
3152/*
3153 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3154 * Only do it if the bridge is a root port since we don't want to disturb
3155 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3156 */
3157
0da34b6d
BG		 3158static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3159{
3160 struct pci_dev *bridge = mgp->pdev->bus->self;
3161 struct device *dev = &mgp->pdev->dev;
3162 unsigned cap;
3163 unsigned err_cap;
3164 u16 val;
3165 u8 ext_type;
3166 int ret;
3167
3168 if (!myri10ge_ecrc_enable || !bridge)
3169 return;
3170
3171 /* check that the bridge is a root port */
3172 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3173 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3174 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3175 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3176 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3177 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3178
3179 /* Walk the hierarchy up to the root port
3180 * where ECRC has to be enabled */
3181 do {
eca3fd83 3182 prev_bridge = bridge;
0da34b6d 3183 bridge = bridge->bus->self;
eca3fd83 3184 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3185 dev_err(dev,
3186 "Failed to find root port"
3187 " to force ECRC\n");
3188 return;
3189 }
3190 cap =
3191 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3192 pci_read_config_word(bridge,
3193 cap + PCI_CAP_FLAGS, &val);
3194 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3195 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3196
3197 dev_info(dev,
3198 "Forcing ECRC on non-root port %s"
3199 " (enabling on root port %s)\n",
3200 pci_name(old_bridge), pci_name(bridge));
3201 } else {
3202 dev_err(dev,
3203 "Not enabling ECRC on non-root port %s\n",
3204 pci_name(bridge));
3205 return;
3206 }
3207 }
3208
3209 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3210 if (!cap)
3211 return;
3212
3213 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3214 if (ret) {
3215 dev_err(dev, "failed reading ext-conf-space of %s\n",
3216 pci_name(bridge));
3217 dev_err(dev, "\t pci=nommconf in use? "
3218 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3219 return;
3220 }
3221 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3222 return;
3223
3224 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3225 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3226 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3227}
3228
3229/*
3230 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3231 * when the PCI-E Completion packets are aligned on an 8-byte
3232 * boundary. Some PCI-E chip sets always align Completion packets; on
3233 * the ones that do not, the alignment can be enforced by enabling
3234 * ECRC generation (if supported).
3235 *
3236 * When PCI-E Completion packets are not aligned, it is actually more
3237 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3238 *
3239 * If the driver can neither enable ECRC nor verify that it has
3240 * already been enabled, then it must use a firmware image which works
0dcffac1 3241 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3242 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3243 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3244 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3245 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3246 */
3247
5443e9ea 3248static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3249{
5443e9ea
BG		 3250 struct pci_dev *pdev = mgp->pdev;
3251 struct device *dev = &pdev->dev;
302d242c 3252 int status;
0da34b6d 3253
b53bef84 3254 mgp->tx_boundary = 4096;
5443e9ea
BG		 3255 /*
3256 * Verify the max read request size was set to 4KB
3257 * before trying the test with 4KB.
3258 */
302d242c
BG		 3259 status = pcie_get_readrq(pdev);
3260 if (status < 0) {
5443e9ea
BG		 3261 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3262 goto abort;
3263 }
302d242c
BG		 3264 if (status != 4096) {
3265 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3266 mgp->tx_boundary = 2048;
5443e9ea
BG		 3267 }
3268 /*
3269 * load the optimized firmware (which assumes aligned PCIe
3270 * completions) in order to see if it works on this host.
3271 */
7d351035 3272 set_fw_name(mgp, myri10ge_fw_aligned, false);
0dcffac1 3273 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3274 if (status != 0) {
3275 goto abort;
3276 }
3277
3278 /*
3279 * Enable ECRC if possible
3280 */
3281 myri10ge_enable_ecrc(mgp);
3282
3283 /*
3284 * Run a DMA test which watches for unaligned completions and
3285 * aborts on the first one seen.
3286 */
3287
3288 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3289 if (status == 0)
3290 return; /* keep the aligned firmware */
3291
3292 if (status != -E2BIG)
3293 dev_warn(dev, "DMA test failed: %d\n", status);
3294 if (status == -ENOSYS)
3295 dev_warn(dev, "Falling back to ethp! "
3296 "Please install up to date fw\n");
3297abort:
3298 /* fall back to using the unaligned firmware */
b53bef84 3299 mgp->tx_boundary = 2048;
7d351035 3300 set_fw_name(mgp, myri10ge_fw_unaligned, false);
0da34b6d 3301
5443e9ea
BG		 3302}
3303
3304static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3305{
2d90b0aa
BG		 3306 int overridden = 0;
3307
0da34b6d 3308 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3309 int link_width, exp_cap;
3310 u16 lnk;
3311
3312 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3313 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3314 link_width = (lnk >> 4) & 0x3f;
3315
ce7f9368
BG		 3316 /* Check to see if Link is less than 8 or if the
3317 * upstream bridge is known to provide aligned
3318 * completions */
3319 if (link_width < 8) {
3320 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3321 link_width);
b53bef84 3322 mgp->tx_boundary = 4096;
7d351035 3323 set_fw_name(mgp, myri10ge_fw_aligned, false);
5443e9ea
BG		 3324 } else {
3325 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3326 }
3327 } else {
3328 if (myri10ge_force_firmware == 1) {
3329 dev_info(&mgp->pdev->dev,
3330 "Assuming aligned completions (forced)\n");
b53bef84 3331 mgp->tx_boundary = 4096;
7d351035 3332 set_fw_name(mgp, myri10ge_fw_aligned, false);
0da34b6d
BG		 3333 } else {
3334 dev_info(&mgp->pdev->dev,
3335 "Assuming unaligned completions (forced)\n");
b53bef84 3336 mgp->tx_boundary = 2048;
7d351035 3337 set_fw_name(mgp, myri10ge_fw_unaligned, false);
0da34b6d
BG		 3338 }
3339 }
7d351035
RR		 3340
3341 kparam_block_sysfs_write(myri10ge_fw_name);
0da34b6d 3342 if (myri10ge_fw_name != NULL) {
7d351035
RR		 3343 char *fw_name = kstrdup(myri10ge_fw_name, GFP_KERNEL);
3344 if (fw_name) {
3345 overridden = 1;
3346 set_fw_name(mgp, fw_name, true);
3347 }
0da34b6d 3348 }
7d351035
RR		 3349 kparam_unblock_sysfs_write(myri10ge_fw_name);
3350
2d90b0aa
BG		 3351 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3352 myri10ge_fw_names[mgp->board_number] != NULL &&
3353 strlen(myri10ge_fw_names[mgp->board_number])) {
7d351035 3354 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
2d90b0aa
BG		 3355 overridden = 1;
3356 }
3357 if (overridden)
3358 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3359 mgp->fw_name);
0da34b6d
BG		 3360}
3361
0da34b6d 3362#ifdef CONFIG_PM
0da34b6d
BG		 3363static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3364{
3365 struct myri10ge_priv *mgp;
3366 struct net_device *netdev;
3367
3368 mgp = pci_get_drvdata(pdev);
3369 if (mgp == NULL)
3370 return -EINVAL;
3371 netdev = mgp->dev;
3372
3373 netif_device_detach(netdev);
3374 if (netif_running(netdev)) {
78ca90ea 3375 netdev_info(netdev, "closing\n");
0da34b6d
BG		 3376 rtnl_lock();
3377 myri10ge_close(netdev);
3378 rtnl_unlock();
3379 }
3380 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3381 pci_save_state(pdev);
0da34b6d 3382 pci_disable_device(pdev);
1a63e846
BG		 3383
3384 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3385}
3386
3387static int myri10ge_resume(struct pci_dev *pdev)
3388{
3389 struct myri10ge_priv *mgp;
3390 struct net_device *netdev;
3391 int status;
3392 u16 vendor;
3393
3394 mgp = pci_get_drvdata(pdev);
3395 if (mgp == NULL)
3396 return -EINVAL;
3397 netdev = mgp->dev;
3398 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3399 msleep(5); /* give card time to respond */
3400 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3401 if (vendor == 0xffff) {
78ca90ea 3402 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3403 return -EIO;
3404 }
83f6e152 3405
1d3c16a8 3406 pci_restore_state(pdev);
4c2248cc
BG		 3407
3408 status = pci_enable_device(pdev);
1a63e846 3409 if (status) {
4c2248cc 3410 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3411 return status;
4c2248cc
BG		 3412 }
3413
0da34b6d
BG		 3414 pci_set_master(pdev);
3415
0da34b6d 3416 myri10ge_reset(mgp);
013b68bf 3417 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3418
3419 /* Save configuration space to be restored if the
3420 * nic resets due to a parity error */
83f6e152 3421 pci_save_state(pdev);
0da34b6d
BG		 3422
3423 if (netif_running(netdev)) {
3424 rtnl_lock();
df30a740 3425 status = myri10ge_open(netdev);
0da34b6d 3426 rtnl_unlock();
df30a740
BG		 3427 if (status != 0)
3428 goto abort_with_enabled;
3429
0da34b6d
BG		 3430 }
3431 netif_device_attach(netdev);
3432
3433 return 0;
3434
4c2248cc
BG		 3435abort_with_enabled:
3436 pci_disable_device(pdev);
0da34b6d
BG		 3437 return -EIO;
3438
3439}
0da34b6d
BG		 3440#endif /* CONFIG_PM */
3441
3442static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3443{
3444 struct pci_dev *pdev = mgp->pdev;
3445 int vs = mgp->vendor_specific_offset;
3446 u32 reboot;
3447
3448 /*enter read32 mode */
3449 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3450
3451 /*read REBOOT_STATUS (0xfffffff0) */
3452 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3453 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3454 return reboot;
3455}
3456
3457/*
3458 * This watchdog is used to check whether the board has suffered
3459 * from a parity error and needs to be recovered.
3460 */
c4028958 3461static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3462{
c4028958 3463 struct myri10ge_priv *mgp =
6250223e 3464 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3465 struct myri10ge_tx_buf *tx;
0da34b6d 3466 u32 reboot;
d0234215 3467 int status, rebooted;
0dcffac1 3468 int i;
0da34b6d
BG		 3469 u16 cmd, vendor;
3470
3471 mgp->watchdog_resets++;
3472 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
d0234215 3473 rebooted = 0;
0da34b6d
BG		 3474 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3475 /* Bus master DMA disabled? Check to see
3476 * if the card rebooted due to a parity error
3477 * For now, just report it */
3478 reboot = myri10ge_read_reboot(mgp);
78ca90ea
JP		 3479 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3480 reboot,
3481 myri10ge_reset_recover ? "" : " not");
f181137f
BG		 3482 if (myri10ge_reset_recover == 0)
3483 return;
d0234215
BG		 3484 rtnl_lock();
3485 mgp->rebooted = 1;
3486 rebooted = 1;
3487 myri10ge_close(mgp->dev);
f181137f 3488 myri10ge_reset_recover--;
d0234215 3489 mgp->rebooted = 0;
0da34b6d
BG		 3490 /*
3491 * A rebooted nic will come back with config space as
3492 * it was after power was applied to PCIe bus.
3493 * Attempt to restore config space which was saved
3494 * when the driver was loaded, or the last time the
3495 * nic was resumed from power saving mode.
3496 */
83f6e152 3497 pci_restore_state(mgp->pdev);
7adda30c
BG		 3498
3499 /* save state again for accounting reasons */
83f6e152 3500 pci_save_state(mgp->pdev);
7adda30c 3501
0da34b6d
BG		 3502 } else {
3503 /* if we get back -1's from our slot, perhaps somebody
3504 * powered off our card. Don't try to reset it in
3505 * this case */
3506 if (cmd == 0xffff) {
3507 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3508 if (vendor == 0xffff) {
78ca90ea 3509 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3510 return;
3511 }
3512 }
3513 /* Perhaps it is a software error. Try to reset */
3514
78ca90ea 3515 netdev_err(mgp->dev, "device timeout, resetting\n");
0dcffac1
BG		 3516 for (i = 0; i < mgp->num_slices; i++) {
3517 tx = &mgp->ss[i].tx;
78ca90ea
JP		 3518 netdev_err(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3519 i, tx->queue_active, tx->req,
3520 tx->done, tx->pkt_start, tx->pkt_done,
3521 (int)ntohl(mgp->ss[i].fw_stats->
3522 send_done_count));
0dcffac1 3523 msleep(2000);
78ca90ea
JP		 3524 netdev_info(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3525 i, tx->queue_active, tx->req,
3526 tx->done, tx->pkt_start, tx->pkt_done,
3527 (int)ntohl(mgp->ss[i].fw_stats->
3528 send_done_count));
0dcffac1 3529 }
0da34b6d 3530 }
236bb5e6 3531
d0234215
BG		 3532 if (!rebooted) {
3533 rtnl_lock();
3534 myri10ge_close(mgp->dev);
3535 }
0dcffac1 3536 status = myri10ge_load_firmware(mgp, 1);
0da34b6d 3537 if (status != 0)
78ca90ea 3538 netdev_err(mgp->dev, "failed to load firmware\n");
0da34b6d
BG		 3539 else
3540 myri10ge_open(mgp->dev);
3541 rtnl_unlock();
3542}
3543
3544/*
3545 * We use our own timer routine rather than relying upon
3546 * netdev->tx_timeout because we have a very large hardware transmit
3547 * queue. Due to the large queue, the netdev->tx_timeout function
3548 * cannot detect a NIC with a parity error in a timely fashion if the
3549 * NIC is lightly loaded.
3550 */
3551static void myri10ge_watchdog_timer(unsigned long arg)
3552{
3553 struct myri10ge_priv *mgp;
b53bef84 3554 struct myri10ge_slice_state *ss;
d0234215 3555 int i, reset_needed, busy_slice_cnt;
626fda94 3556 u32 rx_pause_cnt;
d0234215 3557 u16 cmd;
0da34b6d
BG		 3558
3559 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3560
0dcffac1 3561 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
d0234215 3562 busy_slice_cnt = 0;
0dcffac1
BG		 3563 for (i = 0, reset_needed = 0;
3564 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3565
0dcffac1
BG		 3566 ss = &mgp->ss[i];
3567 if (ss->rx_small.watchdog_needed) {
3568 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3569 mgp->small_bytes + MXGEFW_PAD,
3570 1);
3571 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3572 myri10ge_fill_thresh)
3573 ss->rx_small.watchdog_needed = 0;
3574 }
3575 if (ss->rx_big.watchdog_needed) {
3576 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3577 mgp->big_bytes, 1);
3578 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3579 myri10ge_fill_thresh)
3580 ss->rx_big.watchdog_needed = 0;
3581 }
3582
3583 if (ss->tx.req != ss->tx.done &&
3584 ss->tx.done == ss->watchdog_tx_done &&
3585 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3586 /* nic seems like it might be stuck.. */
3587 if (rx_pause_cnt != mgp->watchdog_pause) {
3588 if (net_ratelimit())
78ca90ea
JP		 3589 netdev_err(mgp->dev, "slice %d: TX paused, check link partner\n",
3590 i);
0dcffac1 3591 } else {
78ca90ea 3592 netdev_warn(mgp->dev, "slice %d stuck:", i);
0dcffac1
BG		 3593 reset_needed = 1;
3594 }
626fda94 3595 }
d0234215
BG		 3596 if (ss->watchdog_tx_done != ss->tx.done ||
3597 ss->watchdog_rx_done != ss->rx_done.cnt) {
3598 busy_slice_cnt++;
3599 }
0dcffac1
BG		 3600 ss->watchdog_tx_done = ss->tx.done;
3601 ss->watchdog_tx_req = ss->tx.req;
d0234215
BG		 3602 ss->watchdog_rx_done = ss->rx_done.cnt;
3603 }
3604 /* if we've sent or received no traffic, poll the NIC to
3605 * ensure it is still there. Otherwise, we risk not noticing
3606 * an error in a timely fashion */
3607 if (busy_slice_cnt == 0) {
3608 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3609 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3610 reset_needed = 1;
3611 }
626fda94 3612 }
626fda94 3613 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3614
3615 if (reset_needed) {
3616 schedule_work(&mgp->watchdog_work);
3617 } else {
3618 /* rearm timer */
3619 mod_timer(&mgp->watchdog_timer,
3620 jiffies + myri10ge_watchdog_timeout * HZ);
3621 }
0da34b6d
BG		 3622}
3623
77929732
BG		 3624static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3625{
3626 struct myri10ge_slice_state *ss;
3627 struct pci_dev *pdev = mgp->pdev;
3628 size_t bytes;
3629 int i;
3630
3631 if (mgp->ss == NULL)
3632 return;
3633
3634 for (i = 0; i < mgp->num_slices; i++) {
3635 ss = &mgp->ss[i];
3636 if (ss->rx_done.entry != NULL) {
3637 bytes = mgp->max_intr_slots *
3638 sizeof(*ss->rx_done.entry);
3639 dma_free_coherent(&pdev->dev, bytes,
3640 ss->rx_done.entry, ss->rx_done.bus);
3641 ss->rx_done.entry = NULL;
3642 }
3643 if (ss->fw_stats != NULL) {
3644 bytes = sizeof(*ss->fw_stats);
3645 dma_free_coherent(&pdev->dev, bytes,
3646 ss->fw_stats, ss->fw_stats_bus);
3647 ss->fw_stats = NULL;
3648 }
3649 }
3650 kfree(mgp->ss);
3651 mgp->ss = NULL;
3652}
3653
3654static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3655{
3656 struct myri10ge_slice_state *ss;
3657 struct pci_dev *pdev = mgp->pdev;
3658 size_t bytes;
3659 int i;
3660
3661 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3662 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3663 if (mgp->ss == NULL) {
3664 return -ENOMEM;
3665 }
3666
3667 for (i = 0; i < mgp->num_slices; i++) {
3668 ss = &mgp->ss[i];
3669 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3670 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3671 &ss->rx_done.bus,
3672 GFP_KERNEL);
3673 if (ss->rx_done.entry == NULL)
3674 goto abort;
3675 memset(ss->rx_done.entry, 0, bytes);
3676 bytes = sizeof(*ss->fw_stats);
3677 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3678 &ss->fw_stats_bus,
3679 GFP_KERNEL);
3680 if (ss->fw_stats == NULL)
3681 goto abort;
3682 ss->mgp = mgp;
3683 ss->dev = mgp->dev;
3684 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3685 myri10ge_napi_weight);
3686 }
3687 return 0;
3688abort:
3689 myri10ge_free_slices(mgp);
3690 return -ENOMEM;
3691}
3692
3693/*
3694 * This function determines the number of slices supported.
3695 * The number slices is the minumum of the number of CPUS,
3696 * the number of MSI-X irqs supported, the number of slices
3697 * supported by the firmware
3698 */
3699static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3700{
3701 struct myri10ge_cmd cmd;
3702 struct pci_dev *pdev = mgp->pdev;
3703 char *old_fw;
7d351035 3704 bool old_allocated;
77929732
BG		 3705 int i, status, ncpus, msix_cap;
3706
3707 mgp->num_slices = 1;
3708 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3709 ncpus = num_online_cpus();
3710
3711 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3712 (myri10ge_max_slices == -1 && ncpus < 2))
3713 return;
3714
3715 /* try to load the slice aware rss firmware */
3716 old_fw = mgp->fw_name;
7d351035
RR		 3717 old_allocated = mgp->fw_name_allocated;
3718 /* don't free old_fw if we override it. */
3719 mgp->fw_name_allocated = false;
3720
13b2738c
BG		 3721 if (myri10ge_fw_name != NULL) {
3722 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3723 myri10ge_fw_name);
7d351035 3724 set_fw_name(mgp, myri10ge_fw_name, false);
13b2738c 3725 } else if (old_fw == myri10ge_fw_aligned)
7d351035 3726 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
77929732 3727 else
7d351035 3728 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
77929732
BG		 3729 status = myri10ge_load_firmware(mgp, 0);
3730 if (status != 0) {
3731 dev_info(&pdev->dev, "Rss firmware not found\n");
7d351035
RR		 3732 if (old_allocated)
3733 kfree(old_fw);
77929732
BG		 3734 return;
3735 }
3736
3737 /* hit the board with a reset to ensure it is alive */
3738 memset(&cmd, 0, sizeof(cmd));
3739 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3740 if (status != 0) {
3741 dev_err(&mgp->pdev->dev, "failed reset\n");
3742 goto abort_with_fw;
77929732
BG		 3743 }
3744
3745 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3746
3747 /* tell it the size of the interrupt queues */
3748 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3749 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3750 if (status != 0) {
3751 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3752 goto abort_with_fw;
3753 }
3754
3755 /* ask the maximum number of slices it supports */
3756 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3757 if (status != 0)
3758 goto abort_with_fw;
3759 else
3760 mgp->num_slices = cmd.data0;
3761
3762 /* Only allow multiple slices if MSI-X is usable */
3763 if (!myri10ge_msi) {
3764 goto abort_with_fw;
3765 }
3766
3767 /* if the admin did not specify a limit to how many
3768 * slices we should use, cap it automatically to the
3769 * number of CPUs currently online */
3770 if (myri10ge_max_slices == -1)
3771 myri10ge_max_slices = ncpus;
3772
3773 if (mgp->num_slices > myri10ge_max_slices)
3774 mgp->num_slices = myri10ge_max_slices;
3775
3776 /* Now try to allocate as many MSI-X vectors as we have
3777 * slices. We give up on MSI-X if we can only get a single
3778 * vector. */
3779
baeb2ffa
JP		 3780 mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3781 GFP_KERNEL);
77929732
BG		 3782 if (mgp->msix_vectors == NULL)
3783 goto disable_msix;
3784 for (i = 0; i < mgp->num_slices; i++) {
3785 mgp->msix_vectors[i].entry = i;
3786 }
3787
3788 while (mgp->num_slices > 1) {
3789 /* make sure it is a power of two */
3790 while (!is_power_of_2(mgp->num_slices))
3791 mgp->num_slices--;
3792 if (mgp->num_slices == 1)
3793 goto disable_msix;
3794 status = pci_enable_msix(pdev, mgp->msix_vectors,
3795 mgp->num_slices);
3796 if (status == 0) {
3797 pci_disable_msix(pdev);
7d351035
RR		 3798 if (old_allocated)
3799 kfree(old_fw);
77929732
BG		 3800 return;
3801 }
3802 if (status > 0)
3803 mgp->num_slices = status;
3804 else
3805 goto disable_msix;
3806 }
3807
3808disable_msix:
3809 if (mgp->msix_vectors != NULL) {
3810 kfree(mgp->msix_vectors);
3811 mgp->msix_vectors = NULL;
3812 }
3813
3814abort_with_fw:
3815 mgp->num_slices = 1;
7d351035 3816 set_fw_name(mgp, old_fw, old_allocated);
77929732
BG		 3817 myri10ge_load_firmware(mgp, 0);
3818}
77929732 3819
8126089f
SH		 3820static const struct net_device_ops myri10ge_netdev_ops = {
3821 .ndo_open = myri10ge_open,
3822 .ndo_stop = myri10ge_close,
3823 .ndo_start_xmit = myri10ge_xmit,
3824 .ndo_get_stats = myri10ge_get_stats,
3825 .ndo_validate_addr = eth_validate_addr,
3826 .ndo_change_mtu = myri10ge_change_mtu,
3827 .ndo_set_multicast_list = myri10ge_set_multicast_list,
3828 .ndo_set_mac_address = myri10ge_set_mac_address,
3829};
3830
0da34b6d
BG		 3831static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3832{
3833 struct net_device *netdev;
3834 struct myri10ge_priv *mgp;
3835 struct device *dev = &pdev->dev;
0da34b6d
BG		 3836 int i;
3837 int status = -ENXIO;
0da34b6d 3838 int dac_enabled;
00b5e505 3839 unsigned hdr_offset, ss_offset;
2d90b0aa 3840 static int board_number;
0da34b6d 3841
236bb5e6 3842 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
0da34b6d
BG		 3843 if (netdev == NULL) {
3844 dev_err(dev, "Could not allocate ethernet device\n");
3845 return -ENOMEM;
3846 }
3847
b245fb67
MH		 3848 SET_NETDEV_DEV(netdev, &pdev->dev);
3849
0da34b6d 3850 mgp = netdev_priv(netdev);
0da34b6d
BG		 3851 mgp->dev = netdev;
3852 mgp->pdev = pdev;
3853 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3854 mgp->pause = myri10ge_flow_control;
3855 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3856 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3857 mgp->board_number = board_number;
0da34b6d
BG		 3858 init_waitqueue_head(&mgp->down_wq);
3859
3860 if (pci_enable_device(pdev)) {
3861 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3862 status = -ENODEV;
3863 goto abort_with_netdev;
3864 }
0da34b6d
BG		 3865
3866 /* Find the vendor-specific cap so we can check
3867 * the reboot register later on */
3868 mgp->vendor_specific_offset
3869 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3870
3871 /* Set our max read request to 4KB */
302d242c 3872 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3873 if (status != 0) {
3874 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3875 status);
e3fd5534 3876 goto abort_with_enabled;
0da34b6d
BG		 3877 }
3878
3879 pci_set_master(pdev);
3880 dac_enabled = 1;
6a35528a 3881 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3882 if (status != 0) {
3883 dac_enabled = 0;
3884 dev_err(&pdev->dev,
898eb71c
JP		 3885 "64-bit pci address mask was refused, "
3886 "trying 32-bit\n");
284901a9 3887 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 3888 }
3889 if (status != 0) {
3890 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 3891 goto abort_with_enabled;
0da34b6d 3892 }
6a35528a 3893 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 3894 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3895 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 3896 if (mgp->cmd == NULL)
e3fd5534 3897 goto abort_with_enabled;
0da34b6d 3898
0da34b6d
BG		 3899 mgp->board_span = pci_resource_len(pdev, 0);
3900 mgp->iomem_base = pci_resource_start(pdev, 0);
3901 mgp->mtrr = -1;
276e26c3 3902 mgp->wc_enabled = 0;
0da34b6d
BG		 3903#ifdef CONFIG_MTRR
3904 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3905 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3906 if (mgp->mtrr >= 0)
3907 mgp->wc_enabled = 1;
0da34b6d 3908#endif
c7f80993 3909 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3910 if (mgp->sram == NULL) {
3911 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3912 mgp->board_span, mgp->iomem_base);
3913 status = -ENXIO;
c7f80993 3914 goto abort_with_mtrr;
0da34b6d 3915 }
00b5e505
BG		 3916 hdr_offset =
3917 ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3918 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3919 mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3920 if (mgp->sram_size > mgp->board_span ||
3921 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3922 dev_err(&pdev->dev,
3923 "invalid sram_size %dB or board span %ldB\n",
3924 mgp->sram_size, mgp->board_span);
3925 goto abort_with_ioremap;
3926 }
0da34b6d 3927 memcpy_fromio(mgp->eeprom_strings,
00b5e505 3928 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 3929 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3930 status = myri10ge_read_mac_addr(mgp);
3931 if (status)
3932 goto abort_with_ioremap;
3933
3934 for (i = 0; i < ETH_ALEN; i++)
3935 netdev->dev_addr[i] = mgp->mac_addr[i];
3936
5443e9ea
BG		 3937 myri10ge_select_firmware(mgp);
3938
0dcffac1 3939 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3940 if (status != 0) {
3941 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3942 goto abort_with_ioremap;
3943 }
3944 myri10ge_probe_slices(mgp);
3945 status = myri10ge_alloc_slices(mgp);
3946 if (status != 0) {
3947 dev_err(&pdev->dev, "failed to alloc slice state\n");
3948 goto abort_with_firmware;
0da34b6d 3949 }
c9920268
BH		 3950 netif_set_real_num_tx_queues(netdev, mgp->num_slices);
3951 netif_set_real_num_rx_queues(netdev, mgp->num_slices);
0da34b6d
BG		 3952 status = myri10ge_reset(mgp);
3953 if (status != 0) {
3954 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3955 goto abort_with_slices;
0da34b6d 3956 }
5dd2d332 3957#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3958 myri10ge_setup_dca(mgp);
3959#endif
0da34b6d
BG		 3960 pci_set_drvdata(pdev, mgp);
3961 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3962 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3963 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3964 myri10ge_initial_mtu = 68;
8126089f
SH		 3965
3966 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 3967 netdev->mtu = myri10ge_initial_mtu;
0da34b6d 3968 netdev->base_addr = mgp->iomem_base;
4f93fde0 3969 netdev->features = mgp->features;
236bb5e6 3970
0da34b6d
BG		 3971 if (dac_enabled)
3972 netdev->features |= NETIF_F_HIGHDMA;
2552c31b 3973 netdev->features |= NETIF_F_LRO;
0da34b6d 3974
dddc045e
BG		 3975 netdev->vlan_features |= mgp->features;
3976 if (mgp->fw_ver_tiny < 37)
3977 netdev->vlan_features &= ~NETIF_F_TSO6;
3978 if (mgp->fw_ver_tiny < 32)
3979 netdev->vlan_features &= ~NETIF_F_TSO;
3980
21d05db1
BG		 3981 /* make sure we can get an irq, and that MSI can be
3982 * setup (if available). Also ensure netdev->irq
3983 * is set to correct value if MSI is enabled */
3984 status = myri10ge_request_irq(mgp);
3985 if (status != 0)
3986 goto abort_with_firmware;
3987 netdev->irq = pdev->irq;
3988 myri10ge_free_irq(mgp);
3989
0da34b6d
BG		 3990 /* Save configuration space to be restored if the
3991 * nic resets due to a parity error */
83f6e152 3992 pci_save_state(pdev);
0da34b6d
BG		 3993
3994 /* Setup the watchdog timer */
3995 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3996 (unsigned long)mgp);
3997
59081825 3998 spin_lock_init(&mgp->stats_lock);
0da34b6d 3999 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 4000 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 4001 status = register_netdev(netdev);
4002 if (status != 0) {
4003 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 4004 goto abort_with_state;
0da34b6d 4005 }
0dcffac1
BG		 4006 if (mgp->msix_enabled)
4007 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
4008 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
4009 (mgp->wc_enabled ? "Enabled" : "Disabled"));
4010 else
4011 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
4012 mgp->msi_enabled ? "MSI" : "xPIC",
4013 netdev->irq, mgp->tx_boundary, mgp->fw_name,
4014 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 4015
2d90b0aa 4016 board_number++;
0da34b6d
BG		 4017 return 0;
4018
7adda30c 4019abort_with_state:
83f6e152 4020 pci_restore_state(pdev);
0da34b6d 4021
0dcffac1
BG		 4022abort_with_slices:
4023 myri10ge_free_slices(mgp);
4024
0da34b6d
BG		 4025abort_with_firmware:
4026 myri10ge_dummy_rdma(mgp, 0);
4027
0da34b6d 4028abort_with_ioremap:
0f840011
BG		 4029 if (mgp->mac_addr_string != NULL)
4030 dev_err(&pdev->dev,
4031 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
4032 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 4033 iounmap(mgp->sram);
4034
c7f80993 4035abort_with_mtrr:
0da34b6d
BG		 4036#ifdef CONFIG_MTRR
4037 if (mgp->mtrr >= 0)
4038 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4039#endif
b10c0668
BG		 4040 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4041 mgp->cmd, mgp->cmd_bus);
0da34b6d 4042
e3fd5534
BG		 4043abort_with_enabled:
4044 pci_disable_device(pdev);
0da34b6d 4045
e3fd5534 4046abort_with_netdev:
7d351035 4047 set_fw_name(mgp, NULL, false);
0da34b6d
BG		 4048 free_netdev(netdev);
4049 return status;
4050}
4051
4052/*
4053 * myri10ge_remove
4054 *
4055 * Does what is necessary to shutdown one Myrinet device. Called
4056 * once for each Myrinet card by the kernel when a module is
4057 * unloaded.
4058 */
4059static void myri10ge_remove(struct pci_dev *pdev)
4060{
4061 struct myri10ge_priv *mgp;
4062 struct net_device *netdev;
0da34b6d
BG		 4063
4064 mgp = pci_get_drvdata(pdev);
4065 if (mgp == NULL)
4066 return;
4067
23f333a2 4068 cancel_work_sync(&mgp->watchdog_work);
0da34b6d
BG		 4069 netdev = mgp->dev;
4070 unregister_netdev(netdev);
0da34b6d 4071
5dd2d332 4072#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4073 myri10ge_teardown_dca(mgp);
4074#endif
0da34b6d
BG		 4075 myri10ge_dummy_rdma(mgp, 0);
4076
7adda30c 4077 /* avoid a memory leak */
83f6e152 4078 pci_restore_state(pdev);
7adda30c 4079
0da34b6d
BG		 4080 iounmap(mgp->sram);
4081
4082#ifdef CONFIG_MTRR
4083 if (mgp->mtrr >= 0)
4084 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4085#endif
0dcffac1
BG		 4086 myri10ge_free_slices(mgp);
4087 if (mgp->msix_vectors != NULL)
4088 kfree(mgp->msix_vectors);
b10c0668
BG		 4089 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4090 mgp->cmd, mgp->cmd_bus);
0da34b6d 4091
7d351035 4092 set_fw_name(mgp, NULL, false);
0da34b6d 4093 free_netdev(netdev);
e3fd5534 4094 pci_disable_device(pdev);
0da34b6d
BG		 4095 pci_set_drvdata(pdev, NULL);
4096}
4097
b10c0668 4098#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4099#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d 4100
a3aa1884 4101static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
b10c0668 4102 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4103 {PCI_DEVICE
4104 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4105 {0},
4106};
4107
97131079
BG		 4108MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4109
0da34b6d
BG		 4110static struct pci_driver myri10ge_driver = {
4111 .name = "myri10ge",
4112 .probe = myri10ge_probe,
4113 .remove = myri10ge_remove,
4114 .id_table = myri10ge_pci_tbl,
4115#ifdef CONFIG_PM
4116 .suspend = myri10ge_suspend,
4117 .resume = myri10ge_resume,
4118#endif
4119};
4120
5dd2d332 4121#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4122static int
4123myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4124{
4125 int err = driver_for_each_device(&myri10ge_driver.driver,
4126 NULL, &event,
4127 myri10ge_notify_dca_device);
4128
4129 if (err)
4130 return NOTIFY_BAD;
4131 return NOTIFY_DONE;
4132}
4133
4134static struct notifier_block myri10ge_dca_notifier = {
4135 .notifier_call = myri10ge_notify_dca,
4136 .next = NULL,
4137 .priority = 0,
4138};
4ee2ac51 4139#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4140
0da34b6d
BG		 4141static __init int myri10ge_init_module(void)
4142{
78ca90ea 4143 pr_info("Version %s\n", MYRI10GE_VERSION_STR);
0dcffac1 4144
236bb5e6 4145 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
78ca90ea
JP		 4146 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4147 myri10ge_rss_hash);
0dcffac1
BG		 4148 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4149 }
5dd2d332 4150#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4151 dca_register_notify(&myri10ge_dca_notifier);
4152#endif
236bb5e6
BG		 4153 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4154 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4155
0da34b6d
BG		 4156 return pci_register_driver(&myri10ge_driver);
4157}
4158
4159module_init(myri10ge_init_module);
4160
4161static __exit void myri10ge_cleanup_module(void)
4162{
5dd2d332 4163#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4164 dca_unregister_notify(&myri10ge_dca_notifier);
4165#endif
0da34b6d
BG		 4166 pci_unregister_driver(&myri10ge_driver);
4167}
4168
4169module_exit(myri10ge_cleanup_module);
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