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[LRO]: fix lro_gen_skb() alignment
[mirror_ubuntu-bionic-kernel.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
0da34b6d
BG		 52#include <linux/ip.h>
53#include <linux/inet.h>
54#include <linux/in.h>
55#include <linux/ethtool.h>
56#include <linux/firmware.h>
57#include <linux/delay.h>
58#include <linux/version.h>
59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
e0d7c526 78#define MYRI10GE_VERSION_STR "1.3.2-1.287"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
0da34b6d 105struct myri10ge_rx_buffer_state {
dd50f336
BG		 106 struct page *page;
107 int page_offset;
0da34b6d
BG		 108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110};
111
112struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117};
118
119struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123};
124
125struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 130 struct page *page;
131 dma_addr_t bus;
132 int page_offset;
0da34b6d 133 int cnt;
dd50f336 134 int fill_cnt;
0da34b6d
BG		 135 int alloc_fail;
136 int mask; /* number of rx slots -1 */
dd50f336 137 int watchdog_needed;
0da34b6d
BG		 138};
139
140struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
144 char *req_bytes;
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int boundary; /* boundary transmits cannot cross */
148 int req ____cacheline_aligned; /* transmit slots submitted */
149 int pkt_start; /* packets started */
150 int done ____cacheline_aligned; /* transmit slots completed */
151 int pkt_done; /* packets completed */
152};
153
154struct myri10ge_rx_done {
155 struct mcp_slot *entry;
156 dma_addr_t bus;
157 int cnt;
158 int idx;
1e6e9342
AG		 159 struct net_lro_mgr lro_mgr;
160 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 161};
162
163struct myri10ge_priv {
164 int running; /* running? */
165 int csum_flag; /* rx_csums? */
166 struct myri10ge_tx_buf tx; /* transmit ring */
167 struct myri10ge_rx_buf rx_small;
168 struct myri10ge_rx_buf rx_big;
169 struct myri10ge_rx_done rx_done;
170 int small_bytes;
dd50f336 171 int big_bytes;
0da34b6d 172 struct net_device *dev;
bea3348e 173 struct napi_struct napi;
0da34b6d
BG		 174 struct net_device_stats stats;
175 u8 __iomem *sram;
176 int sram_size;
177 unsigned long board_span;
178 unsigned long iomem_base;
40f6cff5
AV		 179 __be32 __iomem *irq_claim;
180 __be32 __iomem *irq_deassert;
0da34b6d
BG		 181 char *mac_addr_string;
182 struct mcp_cmd_response *cmd;
183 dma_addr_t cmd_bus;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 struct pci_dev *pdev;
187 int msi_enabled;
40f6cff5 188 __be32 link_state;
0da34b6d
BG		 189 unsigned int rdma_tags_available;
190 int intr_coal_delay;
40f6cff5 191 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 192 int mtrr;
276e26c3 193 int wc_enabled;
0da34b6d
BG		 194 int wake_queue;
195 int stop_queue;
196 int down_cnt;
197 wait_queue_head_t down_wq;
198 struct work_struct watchdog_work;
199 struct timer_list watchdog_timer;
200 int watchdog_tx_done;
c54772e7 201 int watchdog_tx_req;
626fda94 202 int watchdog_pause;
0da34b6d
BG		 203 int watchdog_resets;
204 int tx_linearized;
205 int pause;
206 char *fw_name;
207 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
208 char fw_version[128];
9dc6f0e7
BG		 209 int fw_ver_major;
210 int fw_ver_minor;
211 int fw_ver_tiny;
212 int adopted_rx_filter_bug;
0da34b6d
BG		 213 u8 mac_addr[6]; /* eeprom mac address */
214 unsigned long serial_number;
215 int vendor_specific_offset;
85a7ea1b 216 int fw_multicast_support;
4f93fde0
BG		 217 unsigned long features;
218 u32 max_tso6;
0da34b6d
BG		 219 u32 read_dma;
220 u32 write_dma;
221 u32 read_write_dma;
c58ac5ca
BG		 222 u32 link_changes;
223 u32 msg_enable;
0da34b6d
BG		 224};
225
226static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
227static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
228
229static char *myri10ge_fw_name = NULL;
230module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
231MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
232
233static int myri10ge_ecrc_enable = 1;
234module_param(myri10ge_ecrc_enable, int, S_IRUGO);
235MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
236
237static int myri10ge_max_intr_slots = 1024;
238module_param(myri10ge_max_intr_slots, int, S_IRUGO);
239MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
240
241static int myri10ge_small_bytes = -1; /* -1 == auto */
242module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
243MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
244
245static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 246module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
0da34b6d
BG		 247MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
248
f761fae1 249static int myri10ge_intr_coal_delay = 75;
0da34b6d
BG		 250module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
251MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
252
253static int myri10ge_flow_control = 1;
254module_param(myri10ge_flow_control, int, S_IRUGO);
255MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
256
257static int myri10ge_deassert_wait = 1;
258module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
259MODULE_PARM_DESC(myri10ge_deassert_wait,
260 "Wait when deasserting legacy interrupts\n");
261
262static int myri10ge_force_firmware = 0;
263module_param(myri10ge_force_firmware, int, S_IRUGO);
264MODULE_PARM_DESC(myri10ge_force_firmware,
265 "Force firmware to assume aligned completions\n");
266
0da34b6d
BG		 267static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
268module_param(myri10ge_initial_mtu, int, S_IRUGO);
269MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
270
271static int myri10ge_napi_weight = 64;
272module_param(myri10ge_napi_weight, int, S_IRUGO);
273MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
274
275static int myri10ge_watchdog_timeout = 1;
276module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
277MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
278
279static int myri10ge_max_irq_loops = 1048576;
280module_param(myri10ge_max_irq_loops, int, S_IRUGO);
281MODULE_PARM_DESC(myri10ge_max_irq_loops,
282 "Set stuck legacy IRQ detection threshold\n");
283
c58ac5ca
BG		 284#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
285
286static int myri10ge_debug = -1; /* defaults above */
287module_param(myri10ge_debug, int, 0);
288MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
289
1e6e9342
AG		 290static int myri10ge_lro = 1;
291module_param(myri10ge_lro, int, S_IRUGO);
292MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload\n");
293
294static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
295module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
296MODULE_PARM_DESC(myri10ge_lro, "Number of LRO packets to be aggregated\n");
297
dd50f336
BG		 298static int myri10ge_fill_thresh = 256;
299module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
300MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
301
f181137f
BG		 302static int myri10ge_reset_recover = 1;
303
f761fae1 304static int myri10ge_wcfifo = 0;
6ebc087a
BG		 305module_param(myri10ge_wcfifo, int, S_IRUGO);
306MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
307
0da34b6d
BG		 308#define MYRI10GE_FW_OFFSET 1024*1024
309#define MYRI10GE_HIGHPART_TO_U32(X) \
310(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
311#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
312
313#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
314
2f76216f 315static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 316static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 317
6250223e 318static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 319{
6250223e 320 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 321}
322
0da34b6d
BG		 323static int
324myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
325 struct myri10ge_cmd *data, int atomic)
326{
327 struct mcp_cmd *buf;
328 char buf_bytes[sizeof(*buf) + 8];
329 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 330 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 331 u32 dma_low, dma_high, result, value;
332 int sleep_total = 0;
333
334 /* ensure buf is aligned to 8 bytes */
335 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
336
337 buf->data0 = htonl(data->data0);
338 buf->data1 = htonl(data->data1);
339 buf->data2 = htonl(data->data2);
340 buf->cmd = htonl(cmd);
341 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
342 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
343
344 buf->response_addr.low = htonl(dma_low);
345 buf->response_addr.high = htonl(dma_high);
40f6cff5 346 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 347 mb();
348 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
349
350 /* wait up to 15ms. Longest command is the DMA benchmark,
351 * which is capped at 5ms, but runs from a timeout handler
352 * that runs every 7.8ms. So a 15ms timeout leaves us with
353 * a 2.2ms margin
354 */
355 if (atomic) {
356 /* if atomic is set, do not sleep,
357 * and try to get the completion quickly
358 * (1ms will be enough for those commands) */
359 for (sleep_total = 0;
360 sleep_total < 1000
40f6cff5 361 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 362 sleep_total += 10)
363 udelay(10);
364 } else {
365 /* use msleep for most command */
366 for (sleep_total = 0;
367 sleep_total < 15
40f6cff5 368 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 369 sleep_total++)
370 msleep(1);
371 }
372
373 result = ntohl(response->result);
374 value = ntohl(response->data);
375 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
376 if (result == 0) {
377 data->data0 = value;
378 return 0;
85a7ea1b
BG		 379 } else if (result == MXGEFW_CMD_UNKNOWN) {
380 return -ENOSYS;
5443e9ea
BG		 381 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
382 return -E2BIG;
0da34b6d
BG		 383 } else {
384 dev_err(&mgp->pdev->dev,
385 "command %d failed, result = %d\n",
386 cmd, result);
387 return -ENXIO;
388 }
389 }
390
391 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
392 cmd, result);
393 return -EAGAIN;
394}
395
396/*
397 * The eeprom strings on the lanaiX have the format
398 * SN=x\0
399 * MAC=x:x:x:x:x:x\0
400 * PT:ddd mmm xx xx:xx:xx xx\0
401 * PV:ddd mmm xx xx:xx:xx xx\0
402 */
403static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
404{
405 char *ptr, *limit;
406 int i;
407
408 ptr = mgp->eeprom_strings;
409 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
410
411 while (*ptr != '\0' && ptr < limit) {
412 if (memcmp(ptr, "MAC=", 4) == 0) {
413 ptr += 4;
414 mgp->mac_addr_string = ptr;
415 for (i = 0; i < 6; i++) {
416 if ((ptr + 2) > limit)
417 goto abort;
418 mgp->mac_addr[i] =
419 simple_strtoul(ptr, &ptr, 16);
420 ptr += 1;
421 }
422 }
423 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
424 ptr += 3;
425 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
426 }
427 while (ptr < limit && *ptr++) ;
428 }
429
430 return 0;
431
432abort:
433 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
434 return -ENXIO;
435}
436
437/*
438 * Enable or disable periodic RDMAs from the host to make certain
439 * chipsets resend dropped PCIe messages
440 */
441
442static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
443{
444 char __iomem *submit;
40f6cff5 445 __be32 buf[16];
0da34b6d
BG		 446 u32 dma_low, dma_high;
447 int i;
448
449 /* clear confirmation addr */
450 mgp->cmd->data = 0;
451 mb();
452
453 /* send a rdma command to the PCIe engine, and wait for the
454 * response in the confirmation address. The firmware should
455 * write a -1 there to indicate it is alive and well
456 */
457 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
458 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
459
460 buf[0] = htonl(dma_high); /* confirm addr MSW */
461 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 462 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 463 buf[3] = htonl(dma_high); /* dummy addr MSW */
464 buf[4] = htonl(dma_low); /* dummy addr LSW */
465 buf[5] = htonl(enable); /* enable? */
466
e700f9f4 467 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 468
469 myri10ge_pio_copy(submit, &buf, sizeof(buf));
470 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
471 msleep(1);
472 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
473 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
474 (enable ? "enable" : "disable"));
475}
476
477static int
478myri10ge_validate_firmware(struct myri10ge_priv *mgp,
479 struct mcp_gen_header *hdr)
480{
481 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 482
483 /* check firmware type */
484 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
485 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
486 return -EINVAL;
487 }
488
489 /* save firmware version for ethtool */
490 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
491
9dc6f0e7
BG		 492 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
493 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 494
9dc6f0e7
BG		 495 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
496 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 497 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
498 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
499 MXGEFW_VERSION_MINOR);
500 return -EINVAL;
501 }
502 return 0;
503}
504
505static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
506{
507 unsigned crc, reread_crc;
508 const struct firmware *fw;
509 struct device *dev = &mgp->pdev->dev;
510 struct mcp_gen_header *hdr;
511 size_t hdr_offset;
512 int status;
e454358a 513 unsigned i;
0da34b6d
BG		 514
515 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
516 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
517 mgp->fw_name);
518 status = -EINVAL;
519 goto abort_with_nothing;
520 }
521
522 /* check size */
523
524 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
525 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
526 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
527 status = -EINVAL;
528 goto abort_with_fw;
529 }
530
531 /* check id */
40f6cff5 532 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 533 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
534 dev_err(dev, "Bad firmware file\n");
535 status = -EINVAL;
536 goto abort_with_fw;
537 }
538 hdr = (void *)(fw->data + hdr_offset);
539
540 status = myri10ge_validate_firmware(mgp, hdr);
541 if (status != 0)
542 goto abort_with_fw;
543
544 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 545 for (i = 0; i < fw->size; i += 256) {
546 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
547 fw->data + i,
548 min(256U, (unsigned)(fw->size - i)));
549 mb();
550 readb(mgp->sram);
b10c0668 551 }
0da34b6d
BG		 552 /* corruption checking is good for parity recovery and buggy chipset */
553 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
554 reread_crc = crc32(~0, fw->data, fw->size);
555 if (crc != reread_crc) {
556 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
557 (unsigned)fw->size, reread_crc, crc);
558 status = -EIO;
559 goto abort_with_fw;
560 }
561 *size = (u32) fw->size;
562
563abort_with_fw:
564 release_firmware(fw);
565
566abort_with_nothing:
567 return status;
568}
569
570static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
571{
572 struct mcp_gen_header *hdr;
573 struct device *dev = &mgp->pdev->dev;
574 const size_t bytes = sizeof(struct mcp_gen_header);
575 size_t hdr_offset;
576 int status;
577
578 /* find running firmware header */
579 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
580
581 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
582 dev_err(dev, "Running firmware has bad header offset (%d)\n",
583 (int)hdr_offset);
584 return -EIO;
585 }
586
587 /* copy header of running firmware from SRAM to host memory to
588 * validate firmware */
589 hdr = kmalloc(bytes, GFP_KERNEL);
590 if (hdr == NULL) {
591 dev_err(dev, "could not malloc firmware hdr\n");
592 return -ENOMEM;
593 }
594 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
595 status = myri10ge_validate_firmware(mgp, hdr);
596 kfree(hdr);
9dc6f0e7
BG		 597
598 /* check to see if adopted firmware has bug where adopting
599 * it will cause broadcasts to be filtered unless the NIC
600 * is kept in ALLMULTI mode */
601 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
602 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
603 mgp->adopted_rx_filter_bug = 1;
604 dev_warn(dev, "Adopting fw %d.%d.%d: "
605 "working around rx filter bug\n",
606 mgp->fw_ver_major, mgp->fw_ver_minor,
607 mgp->fw_ver_tiny);
608 }
0da34b6d
BG		 609 return status;
610}
611
612static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
613{
614 char __iomem *submit;
40f6cff5 615 __be32 buf[16];
0da34b6d
BG		 616 u32 dma_low, dma_high, size;
617 int status, i;
4f93fde0 618 struct myri10ge_cmd cmd;
0da34b6d 619
b10c0668 620 size = 0;
0da34b6d
BG		 621 status = myri10ge_load_hotplug_firmware(mgp, &size);
622 if (status) {
623 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
624
625 /* Do not attempt to adopt firmware if there
626 * was a bad crc */
627 if (status == -EIO)
628 return status;
629
630 status = myri10ge_adopt_running_firmware(mgp);
631 if (status != 0) {
632 dev_err(&mgp->pdev->dev,
633 "failed to adopt running firmware\n");
634 return status;
635 }
636 dev_info(&mgp->pdev->dev,
637 "Successfully adopted running firmware\n");
638 if (mgp->tx.boundary == 4096) {
639 dev_warn(&mgp->pdev->dev,
640 "Using firmware currently running on NIC"
641 ". For optimal\n");
642 dev_warn(&mgp->pdev->dev,
643 "performance consider loading optimized "
644 "firmware\n");
645 dev_warn(&mgp->pdev->dev, "via hotplug\n");
646 }
647
648 mgp->fw_name = "adopted";
649 mgp->tx.boundary = 2048;
650 return status;
651 }
652
653 /* clear confirmation addr */
654 mgp->cmd->data = 0;
655 mb();
656
657 /* send a reload command to the bootstrap MCP, and wait for the
658 * response in the confirmation address. The firmware should
659 * write a -1 there to indicate it is alive and well
660 */
661 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
662 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
663
664 buf[0] = htonl(dma_high); /* confirm addr MSW */
665 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 666 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 667
668 /* FIX: All newest firmware should un-protect the bottom of
669 * the sram before handoff. However, the very first interfaces
670 * do not. Therefore the handoff copy must skip the first 8 bytes
671 */
672 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
673 buf[4] = htonl(size - 8); /* length of code */
674 buf[5] = htonl(8); /* where to copy to */
675 buf[6] = htonl(0); /* where to jump to */
676
e700f9f4 677 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 678
679 myri10ge_pio_copy(submit, &buf, sizeof(buf));
680 mb();
681 msleep(1);
682 mb();
683 i = 0;
684 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
685 msleep(1);
686 i++;
687 }
688 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
689 dev_err(&mgp->pdev->dev, "handoff failed\n");
690 return -ENXIO;
691 }
692 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 693 myri10ge_dummy_rdma(mgp, 1);
0da34b6d 694
4f93fde0
BG		 695 /* probe for IPv6 TSO support */
696 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
697 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
698 &cmd, 0);
699 if (status == 0) {
700 mgp->max_tso6 = cmd.data0;
701 mgp->features |= NETIF_F_TSO6;
702 }
0da34b6d
BG		 703 return 0;
704}
705
706static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
707{
708 struct myri10ge_cmd cmd;
709 int status;
710
711 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
712 | (addr[2] << 8) | addr[3]);
713
714 cmd.data1 = ((addr[4] << 8) | (addr[5]));
715
716 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
717 return status;
718}
719
720static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
721{
722 struct myri10ge_cmd cmd;
723 int status, ctl;
724
725 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
726 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
727
728 if (status) {
729 printk(KERN_ERR
730 "myri10ge: %s: Failed to set flow control mode\n",
731 mgp->dev->name);
732 return status;
733 }
734 mgp->pause = pause;
735 return 0;
736}
737
738static void
739myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
740{
741 struct myri10ge_cmd cmd;
742 int status, ctl;
743
744 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
745 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
746 if (status)
747 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
748 mgp->dev->name);
749}
750
0d6ac257 751static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 752{
753 struct myri10ge_cmd cmd;
754 int status;
0da34b6d 755 u32 len;
34fdccea
BG		 756 struct page *dmatest_page;
757 dma_addr_t dmatest_bus;
0d6ac257
BG		 758 char *test = " ";
759
760 dmatest_page = alloc_page(GFP_KERNEL);
761 if (!dmatest_page)
762 return -ENOMEM;
763 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
764 DMA_BIDIRECTIONAL);
765
766 /* Run a small DMA test.
767 * The magic multipliers to the length tell the firmware
768 * to do DMA read, write, or read+write tests. The
769 * results are returned in cmd.data0. The upper 16
770 * bits or the return is the number of transfers completed.
771 * The lower 16 bits is the time in 0.5us ticks that the
772 * transfers took to complete.
773 */
774
775 len = mgp->tx.boundary;
776
777 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
778 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
779 cmd.data2 = len * 0x10000;
780 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
781 if (status != 0) {
782 test = "read";
783 goto abort;
784 }
785 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
786 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
787 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
788 cmd.data2 = len * 0x1;
789 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
790 if (status != 0) {
791 test = "write";
792 goto abort;
793 }
794 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
795
796 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
797 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
798 cmd.data2 = len * 0x10001;
799 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
800 if (status != 0) {
801 test = "read/write";
802 goto abort;
803 }
804 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
805 (cmd.data0 & 0xffff);
806
807abort:
808 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
809 put_page(dmatest_page);
810
811 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
812 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
813 test, status);
814
815 return status;
816}
817
818static int myri10ge_reset(struct myri10ge_priv *mgp)
819{
820 struct myri10ge_cmd cmd;
821 int status;
822 size_t bytes;
0da34b6d
BG		 823
824 /* try to send a reset command to the card to see if it
825 * is alive */
826 memset(&cmd, 0, sizeof(cmd));
827 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
828 if (status != 0) {
829 dev_err(&mgp->pdev->dev, "failed reset\n");
830 return -ENXIO;
831 }
0d6ac257
BG		 832
833 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0da34b6d
BG		 834
835 /* Now exchange information about interrupts */
836
837 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
838 memset(mgp->rx_done.entry, 0, bytes);
839 cmd.data0 = (u32) bytes;
840 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
841 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
842 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
843 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
844
845 status |=
846 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 847 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 848 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
849 &cmd, 0);
850 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 851
0da34b6d
BG		 852 status |= myri10ge_send_cmd
853 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 854 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 855 if (status != 0) {
856 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
857 return status;
858 }
40f6cff5 859 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 860
0da34b6d
BG		 861 memset(mgp->rx_done.entry, 0, bytes);
862
863 /* reset mcp/driver shared state back to 0 */
864 mgp->tx.req = 0;
865 mgp->tx.done = 0;
866 mgp->tx.pkt_start = 0;
867 mgp->tx.pkt_done = 0;
868 mgp->rx_big.cnt = 0;
869 mgp->rx_small.cnt = 0;
870 mgp->rx_done.idx = 0;
871 mgp->rx_done.cnt = 0;
c58ac5ca 872 mgp->link_changes = 0;
0da34b6d 873 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 874 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 875 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 876 return status;
877}
878
879static inline void
880myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
881 struct mcp_kreq_ether_recv *src)
882{
40f6cff5 883 __be32 low;
0da34b6d
BG		 884
885 low = src->addr_low;
40f6cff5 886 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 887 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
888 mb();
889 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 890 mb();
891 src->addr_low = low;
40f6cff5 892 put_be32(low, &dst->addr_low);
0da34b6d
BG		 893 mb();
894}
895
40f6cff5 896static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 897{
898 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
899
40f6cff5 900 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 901 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
902 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
903 skb->csum = hw_csum;
84fa7933 904 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 905 }
906}
907
dd50f336
BG		 908static inline void
909myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
910 struct skb_frag_struct *rx_frags, int len, int hlen)
911{
912 struct skb_frag_struct *skb_frags;
913
914 skb->len = skb->data_len = len;
915 skb->truesize = len + sizeof(struct sk_buff);
916 /* attach the page(s) */
917
918 skb_frags = skb_shinfo(skb)->frags;
919 while (len > 0) {
920 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
921 len -= rx_frags->size;
922 skb_frags++;
923 rx_frags++;
924 skb_shinfo(skb)->nr_frags++;
925 }
926
927 /* pskb_may_pull is not available in irq context, but
928 * skb_pull() (for ether_pad and eth_type_trans()) requires
929 * the beginning of the packet in skb_headlen(), move it
930 * manually */
27d7ff46 931 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 932 skb_shinfo(skb)->frags[0].page_offset += hlen;
933 skb_shinfo(skb)->frags[0].size -= hlen;
934 skb->data_len -= hlen;
935 skb->tail += hlen;
936 skb_pull(skb, MXGEFW_PAD);
937}
938
939static void
940myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
941 int bytes, int watchdog)
942{
943 struct page *page;
944 int idx;
945
946 if (unlikely(rx->watchdog_needed && !watchdog))
947 return;
948
949 /* try to refill entire ring */
950 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
951 idx = rx->fill_cnt & rx->mask;
ae8509b1 952 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 953 /* we can use part of previous page */
954 get_page(rx->page);
955 } else {
956 /* we need a new page */
957 page =
958 alloc_pages(GFP_ATOMIC | __GFP_COMP,
959 MYRI10GE_ALLOC_ORDER);
960 if (unlikely(page == NULL)) {
961 if (rx->fill_cnt - rx->cnt < 16)
962 rx->watchdog_needed = 1;
963 return;
964 }
965 rx->page = page;
966 rx->page_offset = 0;
967 rx->bus = pci_map_page(mgp->pdev, page, 0,
968 MYRI10GE_ALLOC_SIZE,
969 PCI_DMA_FROMDEVICE);
970 }
971 rx->info[idx].page = rx->page;
972 rx->info[idx].page_offset = rx->page_offset;
973 /* note that this is the address of the start of the
974 * page */
975 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
976 rx->shadow[idx].addr_low =
977 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
978 rx->shadow[idx].addr_high =
979 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
980
981 /* start next packet on a cacheline boundary */
982 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 983
984#if MYRI10GE_ALLOC_SIZE > 4096
985 /* don't cross a 4KB boundary */
986 if ((rx->page_offset >> 12) !=
987 ((rx->page_offset + bytes - 1) >> 12))
988 rx->page_offset = (rx->page_offset + 4096) & ~4095;
989#endif
dd50f336
BG		 990 rx->fill_cnt++;
991
992 /* copy 8 descriptors to the firmware at a time */
993 if ((idx & 7) == 7) {
994 if (rx->wc_fifo == NULL)
995 myri10ge_submit_8rx(&rx->lanai[idx - 7],
996 &rx->shadow[idx - 7]);
997 else {
998 mb();
999 myri10ge_pio_copy(rx->wc_fifo,
1000 &rx->shadow[idx - 7], 64);
1001 }
1002 }
1003 }
1004}
1005
1006static inline void
1007myri10ge_unmap_rx_page(struct pci_dev *pdev,
1008 struct myri10ge_rx_buffer_state *info, int bytes)
1009{
1010 /* unmap the recvd page if we're the only or last user of it */
1011 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1012 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1013 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1014 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1015 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1016 }
1017}
1018
1019#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1020 * page into an skb */
1021
1022static inline int
52ea6fb3
BG		 1023myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1024 int bytes, int len, __wsum csum)
dd50f336
BG		 1025{
1026 struct sk_buff *skb;
1027 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1028 int i, idx, hlen, remainder;
1029 struct pci_dev *pdev = mgp->pdev;
1030 struct net_device *dev = mgp->dev;
1031 u8 *va;
1032
1033 len += MXGEFW_PAD;
1034 idx = rx->cnt & rx->mask;
1035 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1036 prefetch(va);
1037 /* Fill skb_frag_struct(s) with data from our receive */
1038 for (i = 0, remainder = len; remainder > 0; i++) {
1039 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1040 rx_frags[i].page = rx->info[idx].page;
1041 rx_frags[i].page_offset = rx->info[idx].page_offset;
1042 if (remainder < MYRI10GE_ALLOC_SIZE)
1043 rx_frags[i].size = remainder;
1044 else
1045 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1046 rx->cnt++;
1047 idx = rx->cnt & rx->mask;
1048 remainder -= MYRI10GE_ALLOC_SIZE;
1049 }
1050
1e6e9342
AG		 1051 if (mgp->csum_flag && myri10ge_lro) {
1052 rx_frags[0].page_offset += MXGEFW_PAD;
1053 rx_frags[0].size -= MXGEFW_PAD;
1054 len -= MXGEFW_PAD;
1055 lro_receive_frags(&mgp->rx_done.lro_mgr, rx_frags,
1056 len, len, (void *)(unsigned long)csum, csum);
1057 return 1;
1058 }
1059
dd50f336
BG		 1060 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1061
e636b2ea
BG		 1062 /* allocate an skb to attach the page(s) to. This is done
1063 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1064
1065 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1066 if (unlikely(skb == NULL)) {
1067 mgp->stats.rx_dropped++;
1068 do {
1069 i--;
1070 put_page(rx_frags[i].page);
1071 } while (i != 0);
1072 return 0;
1073 }
1074
1075 /* Attach the pages to the skb, and trim off any padding */
1076 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1077 if (skb_shinfo(skb)->frags[0].size <= 0) {
1078 put_page(skb_shinfo(skb)->frags[0].page);
1079 skb_shinfo(skb)->nr_frags = 0;
1080 }
1081 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1082
1083 if (mgp->csum_flag) {
1084 if ((skb->protocol == htons(ETH_P_IP)) ||
1085 (skb->protocol == htons(ETH_P_IPV6))) {
1086 skb->csum = csum;
1087 skb->ip_summed = CHECKSUM_COMPLETE;
1088 } else
1089 myri10ge_vlan_ip_csum(skb, csum);
1090 }
1091 netif_receive_skb(skb);
1092 dev->last_rx = jiffies;
1093 return 1;
1094}
1095
0da34b6d
BG		 1096static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1097{
1098 struct pci_dev *pdev = mgp->pdev;
1099 struct myri10ge_tx_buf *tx = &mgp->tx;
1100 struct sk_buff *skb;
1101 int idx, len;
0da34b6d
BG		 1102
1103 while (tx->pkt_done != mcp_index) {
1104 idx = tx->done & tx->mask;
1105 skb = tx->info[idx].skb;
1106
1107 /* Mark as free */
1108 tx->info[idx].skb = NULL;
1109 if (tx->info[idx].last) {
1110 tx->pkt_done++;
1111 tx->info[idx].last = 0;
1112 }
1113 tx->done++;
1114 len = pci_unmap_len(&tx->info[idx], len);
1115 pci_unmap_len_set(&tx->info[idx], len, 0);
1116 if (skb) {
1117 mgp->stats.tx_bytes += skb->len;
1118 mgp->stats.tx_packets++;
1119 dev_kfree_skb_irq(skb);
1120 if (len)
1121 pci_unmap_single(pdev,
1122 pci_unmap_addr(&tx->info[idx],
1123 bus), len,
1124 PCI_DMA_TODEVICE);
1125 } else {
1126 if (len)
1127 pci_unmap_page(pdev,
1128 pci_unmap_addr(&tx->info[idx],
1129 bus), len,
1130 PCI_DMA_TODEVICE);
1131 }
0da34b6d
BG		 1132 }
1133 /* start the queue if we've stopped it */
1134 if (netif_queue_stopped(mgp->dev)
1135 && tx->req - tx->done < (tx->mask >> 1)) {
1136 mgp->wake_queue++;
1137 netif_wake_queue(mgp->dev);
1138 }
1139}
1140
bea3348e 1141static inline int myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int budget)
0da34b6d
BG		 1142{
1143 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1144 unsigned long rx_bytes = 0;
1145 unsigned long rx_packets = 0;
1146 unsigned long rx_ok;
1147
1148 int idx = rx_done->idx;
1149 int cnt = rx_done->cnt;
bea3348e 1150 int work_done = 0;
0da34b6d 1151 u16 length;
40f6cff5 1152 __wsum checksum;
0da34b6d 1153
c956a240 1154 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1155 length = ntohs(rx_done->entry[idx].length);
1156 rx_done->entry[idx].length = 0;
40f6cff5 1157 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1158 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1159 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1160 mgp->small_bytes,
1161 length, checksum);
0da34b6d 1162 else
52ea6fb3
BG		 1163 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1164 mgp->big_bytes,
1165 length, checksum);
0da34b6d
BG		 1166 rx_packets += rx_ok;
1167 rx_bytes += rx_ok * (unsigned long)length;
1168 cnt++;
1169 idx = cnt & (myri10ge_max_intr_slots - 1);
c956a240 1170 work_done++;
0da34b6d
BG		 1171 }
1172 rx_done->idx = idx;
1173 rx_done->cnt = cnt;
1174 mgp->stats.rx_packets += rx_packets;
1175 mgp->stats.rx_bytes += rx_bytes;
c7dab99b 1176
1e6e9342
AG		 1177 if (myri10ge_lro)
1178 lro_flush_all(&rx_done->lro_mgr);
1179
c7dab99b
BG		 1180 /* restock receive rings if needed */
1181 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1182 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1183 mgp->small_bytes + MXGEFW_PAD, 0);
1184 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1185 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1186
bea3348e 1187 return work_done;
0da34b6d
BG		 1188}
1189
1190static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1191{
1192 struct mcp_irq_data *stats = mgp->fw_stats;
1193
1194 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1195 unsigned link_up = ntohl(stats->link_up);
1196 if (mgp->link_state != link_up) {
1197 mgp->link_state = link_up;
1198
1199 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1200 if (netif_msg_link(mgp))
1201 printk(KERN_INFO
1202 "myri10ge: %s: link up\n",
1203 mgp->dev->name);
0da34b6d 1204 netif_carrier_on(mgp->dev);
c58ac5ca 1205 mgp->link_changes++;
0da34b6d 1206 } else {
c58ac5ca
BG		 1207 if (netif_msg_link(mgp))
1208 printk(KERN_INFO
798a95db
BG		 1209 "myri10ge: %s: link %s\n",
1210 mgp->dev->name,
1211 (link_up == MXGEFW_LINK_MYRINET ?
1212 "mismatch (Myrinet detected)" :
1213 "down"));
0da34b6d 1214 netif_carrier_off(mgp->dev);
c58ac5ca 1215 mgp->link_changes++;
0da34b6d
BG		 1216 }
1217 }
1218 if (mgp->rdma_tags_available !=
1219 ntohl(mgp->fw_stats->rdma_tags_available)) {
1220 mgp->rdma_tags_available =
1221 ntohl(mgp->fw_stats->rdma_tags_available);
1222 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1223 "%d tags left\n", mgp->dev->name,
1224 mgp->rdma_tags_available);
1225 }
1226 mgp->down_cnt += stats->link_down;
1227 if (stats->link_down)
1228 wake_up(&mgp->down_wq);
1229 }
1230}
1231
bea3348e 1232static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1233{
e636b2ea
BG		 1234 struct myri10ge_priv *mgp =
1235 container_of(napi, struct myri10ge_priv, napi);
bea3348e 1236 struct net_device *netdev = mgp->dev;
bea3348e 1237 int work_done;
0da34b6d
BG		 1238
1239 /* process as many rx events as NAPI will allow */
bea3348e 1240 work_done = myri10ge_clean_rx_done(mgp, budget);
0da34b6d 1241
c956a240 1242 if (work_done < budget || !netif_running(netdev)) {
bea3348e 1243 netif_rx_complete(netdev, napi);
40f6cff5 1244 put_be32(htonl(3), mgp->irq_claim);
0da34b6d 1245 }
bea3348e 1246 return work_done;
0da34b6d
BG		 1247}
1248
7d12e780 1249static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1250{
1251 struct myri10ge_priv *mgp = arg;
1252 struct mcp_irq_data *stats = mgp->fw_stats;
1253 struct myri10ge_tx_buf *tx = &mgp->tx;
1254 u32 send_done_count;
1255 int i;
1256
1257 /* make sure it is our IRQ, and that the DMA has finished */
1258 if (unlikely(!stats->valid))
1259 return (IRQ_NONE);
1260
1261 /* low bit indicates receives are present, so schedule
1262 * napi poll handler */
1263 if (stats->valid & 1)
bea3348e 1264 netif_rx_schedule(mgp->dev, &mgp->napi);
0da34b6d
BG		 1265
1266 if (!mgp->msi_enabled) {
40f6cff5 1267 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1268 if (!myri10ge_deassert_wait)
1269 stats->valid = 0;
1270 mb();
1271 } else
1272 stats->valid = 0;
1273
1274 /* Wait for IRQ line to go low, if using INTx */
1275 i = 0;
1276 while (1) {
1277 i++;
1278 /* check for transmit completes and receives */
1279 send_done_count = ntohl(stats->send_done_count);
1280 if (send_done_count != tx->pkt_done)
1281 myri10ge_tx_done(mgp, (int)send_done_count);
1282 if (unlikely(i > myri10ge_max_irq_loops)) {
1283 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1284 mgp->dev->name);
1285 stats->valid = 0;
1286 schedule_work(&mgp->watchdog_work);
1287 }
1288 if (likely(stats->valid == 0))
1289 break;
1290 cpu_relax();
1291 barrier();
1292 }
1293
1294 myri10ge_check_statblock(mgp);
1295
40f6cff5 1296 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1297 return (IRQ_HANDLED);
1298}
1299
1300static int
1301myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1302{
1303 cmd->autoneg = AUTONEG_DISABLE;
1304 cmd->speed = SPEED_10000;
1305 cmd->duplex = DUPLEX_FULL;
1306 return 0;
1307}
1308
1309static void
1310myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1311{
1312 struct myri10ge_priv *mgp = netdev_priv(netdev);
1313
1314 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1315 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1316 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1317 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1318}
1319
1320static int
1321myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1322{
1323 struct myri10ge_priv *mgp = netdev_priv(netdev);
1324 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1325 return 0;
1326}
1327
1328static int
1329myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1330{
1331 struct myri10ge_priv *mgp = netdev_priv(netdev);
1332
1333 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1334 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1335 return 0;
1336}
1337
1338static void
1339myri10ge_get_pauseparam(struct net_device *netdev,
1340 struct ethtool_pauseparam *pause)
1341{
1342 struct myri10ge_priv *mgp = netdev_priv(netdev);
1343
1344 pause->autoneg = 0;
1345 pause->rx_pause = mgp->pause;
1346 pause->tx_pause = mgp->pause;
1347}
1348
1349static int
1350myri10ge_set_pauseparam(struct net_device *netdev,
1351 struct ethtool_pauseparam *pause)
1352{
1353 struct myri10ge_priv *mgp = netdev_priv(netdev);
1354
1355 if (pause->tx_pause != mgp->pause)
1356 return myri10ge_change_pause(mgp, pause->tx_pause);
1357 if (pause->rx_pause != mgp->pause)
1358 return myri10ge_change_pause(mgp, pause->tx_pause);
1359 if (pause->autoneg != 0)
1360 return -EINVAL;
1361 return 0;
1362}
1363
1364static void
1365myri10ge_get_ringparam(struct net_device *netdev,
1366 struct ethtool_ringparam *ring)
1367{
1368 struct myri10ge_priv *mgp = netdev_priv(netdev);
1369
1370 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1371 ring->rx_max_pending = mgp->rx_big.mask + 1;
1372 ring->rx_jumbo_max_pending = 0;
1373 ring->tx_max_pending = mgp->rx_small.mask + 1;
1374 ring->rx_mini_pending = ring->rx_mini_max_pending;
1375 ring->rx_pending = ring->rx_max_pending;
1376 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1377 ring->tx_pending = ring->tx_max_pending;
1378}
1379
1380static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1381{
1382 struct myri10ge_priv *mgp = netdev_priv(netdev);
1383 if (mgp->csum_flag)
1384 return 1;
1385 else
1386 return 0;
1387}
1388
1389static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1390{
1391 struct myri10ge_priv *mgp = netdev_priv(netdev);
1392 if (csum_enabled)
1393 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1394 else
1395 mgp->csum_flag = 0;
1396 return 0;
1397}
1398
4f93fde0
BG		 1399static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1400{
1401 struct myri10ge_priv *mgp = netdev_priv(netdev);
1402 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1403
1404 if (tso_enabled)
1405 netdev->features |= flags;
1406 else
1407 netdev->features &= ~flags;
1408 return 0;
1409}
1410
0da34b6d
BG		 1411static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1412 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1413 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1414 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1415 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1416 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1417 "tx_heartbeat_errors", "tx_window_errors",
1418 /* device-specific stats */
2c1a1088 1419 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1420 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1421 "serial_number", "tx_pkt_start", "tx_pkt_done",
1422 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1423 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1424 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1425 "dropped_link_error_or_filtered",
1426 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1427 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1428 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1e6e9342
AG		 1429 "dropped_no_big_buffer", "LRO aggregated", "LRO flushed",
1430 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1431};
1432
1433#define MYRI10GE_NET_STATS_LEN 21
1434#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1435
1436static void
1437myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1438{
1439 switch (stringset) {
1440 case ETH_SS_STATS:
1441 memcpy(data, *myri10ge_gstrings_stats,
1442 sizeof(myri10ge_gstrings_stats));
1443 break;
1444 }
1445}
1446
b9f2c044 1447static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1448{
b9f2c044
JG		 1449 switch (sset) {
1450 case ETH_SS_STATS:
1451 return MYRI10GE_STATS_LEN;
1452 default:
1453 return -EOPNOTSUPP;
1454 }
0da34b6d
BG		 1455}
1456
1457static void
1458myri10ge_get_ethtool_stats(struct net_device *netdev,
1459 struct ethtool_stats *stats, u64 * data)
1460{
1461 struct myri10ge_priv *mgp = netdev_priv(netdev);
1462 int i;
1463
1464 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1465 data[i] = ((unsigned long *)&mgp->stats)[i];
1466
2c1a1088 1467 data[i++] = (unsigned int)mgp->tx.boundary;
276e26c3 1468 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1469 data[i++] = (unsigned int)mgp->pdev->irq;
1470 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1471 data[i++] = (unsigned int)mgp->read_dma;
1472 data[i++] = (unsigned int)mgp->write_dma;
1473 data[i++] = (unsigned int)mgp->read_write_dma;
1474 data[i++] = (unsigned int)mgp->serial_number;
1475 data[i++] = (unsigned int)mgp->tx.pkt_start;
1476 data[i++] = (unsigned int)mgp->tx.pkt_done;
1477 data[i++] = (unsigned int)mgp->tx.req;
1478 data[i++] = (unsigned int)mgp->tx.done;
1479 data[i++] = (unsigned int)mgp->rx_small.cnt;
1480 data[i++] = (unsigned int)mgp->rx_big.cnt;
1481 data[i++] = (unsigned int)mgp->wake_queue;
1482 data[i++] = (unsigned int)mgp->stop_queue;
1483 data[i++] = (unsigned int)mgp->watchdog_resets;
1484 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1485 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1486 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1487 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1488 data[i++] =
1489 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
cee505db
BG		 1490 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1491 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1492 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1493 data[i++] =
1494 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
85a7ea1b
BG		 1495 data[i++] =
1496 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1497 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1498 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1499 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1500 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1e6e9342
AG		 1501 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated;
1502 data[i++] = mgp->rx_done.lro_mgr.stats.flushed;
1503 if (mgp->rx_done.lro_mgr.stats.flushed)
1504 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated /
1505 mgp->rx_done.lro_mgr.stats.flushed;
1506 else
1507 data[i++] = 0;
1508 data[i++] = mgp->rx_done.lro_mgr.stats.no_desc;
0da34b6d
BG		 1509}
1510
c58ac5ca
BG		 1511static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1512{
1513 struct myri10ge_priv *mgp = netdev_priv(netdev);
1514 mgp->msg_enable = value;
1515}
1516
1517static u32 myri10ge_get_msglevel(struct net_device *netdev)
1518{
1519 struct myri10ge_priv *mgp = netdev_priv(netdev);
1520 return mgp->msg_enable;
1521}
1522
7282d491 1523static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1524 .get_settings = myri10ge_get_settings,
1525 .get_drvinfo = myri10ge_get_drvinfo,
1526 .get_coalesce = myri10ge_get_coalesce,
1527 .set_coalesce = myri10ge_set_coalesce,
1528 .get_pauseparam = myri10ge_get_pauseparam,
1529 .set_pauseparam = myri10ge_set_pauseparam,
1530 .get_ringparam = myri10ge_get_ringparam,
1531 .get_rx_csum = myri10ge_get_rx_csum,
1532 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1533 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1534 .set_sg = ethtool_op_set_sg,
4f93fde0 1535 .set_tso = myri10ge_set_tso,
6ffdd071 1536 .get_link = ethtool_op_get_link,
0da34b6d 1537 .get_strings = myri10ge_get_strings,
b9f2c044 1538 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1539 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1540 .set_msglevel = myri10ge_set_msglevel,
1541 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1542};
1543
1544static int myri10ge_allocate_rings(struct net_device *dev)
1545{
1546 struct myri10ge_priv *mgp;
1547 struct myri10ge_cmd cmd;
1548 int tx_ring_size, rx_ring_size;
1549 int tx_ring_entries, rx_ring_entries;
1550 int i, status;
1551 size_t bytes;
1552
1553 mgp = netdev_priv(dev);
1554
1555 /* get ring sizes */
1556
1557 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1558 tx_ring_size = cmd.data0;
1559 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1560 if (status != 0)
1561 return status;
0da34b6d
BG		 1562 rx_ring_size = cmd.data0;
1563
1564 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1565 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1566 mgp->tx.mask = tx_ring_entries - 1;
1567 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1568
355c7265
BG		 1569 status = -ENOMEM;
1570
0da34b6d
BG		 1571 /* allocate the host shadow rings */
1572
1573 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1574 * sizeof(*mgp->tx.req_list);
1575 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1576 if (mgp->tx.req_bytes == NULL)
1577 goto abort_with_nothing;
1578
1579 /* ensure req_list entries are aligned to 8 bytes */
1580 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1581 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1582
1583 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1584 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1585 if (mgp->rx_small.shadow == NULL)
1586 goto abort_with_tx_req_bytes;
1587
1588 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1589 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1590 if (mgp->rx_big.shadow == NULL)
1591 goto abort_with_rx_small_shadow;
1592
1593 /* allocate the host info rings */
1594
1595 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1596 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1597 if (mgp->tx.info == NULL)
1598 goto abort_with_rx_big_shadow;
1599
1600 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1601 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1602 if (mgp->rx_small.info == NULL)
1603 goto abort_with_tx_info;
1604
1605 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1606 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1607 if (mgp->rx_big.info == NULL)
1608 goto abort_with_rx_small_info;
1609
1610 /* Fill the receive rings */
c7dab99b
BG		 1611 mgp->rx_big.cnt = 0;
1612 mgp->rx_small.cnt = 0;
1613 mgp->rx_big.fill_cnt = 0;
1614 mgp->rx_small.fill_cnt = 0;
1615 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1616 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1617 mgp->rx_small.watchdog_needed = 0;
1618 mgp->rx_big.watchdog_needed = 0;
1619 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1620 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1621
c7dab99b
BG		 1622 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1623 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1624 dev->name, mgp->rx_small.fill_cnt);
1625 goto abort_with_rx_small_ring;
0da34b6d
BG		 1626 }
1627
c7dab99b
BG		 1628 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1629 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1630 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1631 dev->name, mgp->rx_big.fill_cnt);
1632 goto abort_with_rx_big_ring;
0da34b6d
BG		 1633 }
1634
1635 return 0;
1636
1637abort_with_rx_big_ring:
c7dab99b
BG		 1638 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1639 int idx = i & mgp->rx_big.mask;
1640 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1641 mgp->big_bytes);
1642 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1643 }
1644
1645abort_with_rx_small_ring:
c7dab99b
BG		 1646 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1647 int idx = i & mgp->rx_small.mask;
1648 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1649 mgp->small_bytes + MXGEFW_PAD);
1650 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1651 }
c7dab99b 1652
0da34b6d
BG		 1653 kfree(mgp->rx_big.info);
1654
1655abort_with_rx_small_info:
1656 kfree(mgp->rx_small.info);
1657
1658abort_with_tx_info:
1659 kfree(mgp->tx.info);
1660
1661abort_with_rx_big_shadow:
1662 kfree(mgp->rx_big.shadow);
1663
1664abort_with_rx_small_shadow:
1665 kfree(mgp->rx_small.shadow);
1666
1667abort_with_tx_req_bytes:
1668 kfree(mgp->tx.req_bytes);
1669 mgp->tx.req_bytes = NULL;
1670 mgp->tx.req_list = NULL;
1671
1672abort_with_nothing:
1673 return status;
1674}
1675
1676static void myri10ge_free_rings(struct net_device *dev)
1677{
1678 struct myri10ge_priv *mgp;
1679 struct sk_buff *skb;
1680 struct myri10ge_tx_buf *tx;
1681 int i, len, idx;
1682
1683 mgp = netdev_priv(dev);
1684
c7dab99b
BG		 1685 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1686 idx = i & mgp->rx_big.mask;
1687 if (i == mgp->rx_big.fill_cnt - 1)
1688 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1689 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1690 mgp->big_bytes);
1691 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1692 }
1693
c7dab99b
BG		 1694 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1695 idx = i & mgp->rx_small.mask;
1696 if (i == mgp->rx_small.fill_cnt - 1)
1697 mgp->rx_small.info[idx].page_offset =
1698 MYRI10GE_ALLOC_SIZE;
1699 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1700 mgp->small_bytes + MXGEFW_PAD);
1701 put_page(mgp->rx_small.info[idx].page);
1702 }
0da34b6d
BG		 1703 tx = &mgp->tx;
1704 while (tx->done != tx->req) {
1705 idx = tx->done & tx->mask;
1706 skb = tx->info[idx].skb;
1707
1708 /* Mark as free */
1709 tx->info[idx].skb = NULL;
1710 tx->done++;
1711 len = pci_unmap_len(&tx->info[idx], len);
1712 pci_unmap_len_set(&tx->info[idx], len, 0);
1713 if (skb) {
1714 mgp->stats.tx_dropped++;
1715 dev_kfree_skb_any(skb);
1716 if (len)
1717 pci_unmap_single(mgp->pdev,
1718 pci_unmap_addr(&tx->info[idx],
1719 bus), len,
1720 PCI_DMA_TODEVICE);
1721 } else {
1722 if (len)
1723 pci_unmap_page(mgp->pdev,
1724 pci_unmap_addr(&tx->info[idx],
1725 bus), len,
1726 PCI_DMA_TODEVICE);
1727 }
1728 }
1729 kfree(mgp->rx_big.info);
1730
1731 kfree(mgp->rx_small.info);
1732
1733 kfree(mgp->tx.info);
1734
1735 kfree(mgp->rx_big.shadow);
1736
1737 kfree(mgp->rx_small.shadow);
1738
1739 kfree(mgp->tx.req_bytes);
1740 mgp->tx.req_bytes = NULL;
1741 mgp->tx.req_list = NULL;
1742}
1743
df30a740
BG		 1744static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1745{
1746 struct pci_dev *pdev = mgp->pdev;
1747 int status;
1748
1749 if (myri10ge_msi) {
1750 status = pci_enable_msi(pdev);
1751 if (status != 0)
1752 dev_err(&pdev->dev,
1753 "Error %d setting up MSI; falling back to xPIC\n",
1754 status);
1755 else
1756 mgp->msi_enabled = 1;
1757 } else {
1758 mgp->msi_enabled = 0;
1759 }
1760 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1761 mgp->dev->name, mgp);
1762 if (status != 0) {
1763 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1764 if (mgp->msi_enabled)
1765 pci_disable_msi(pdev);
1766 }
1767 return status;
1768}
1769
1770static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1771{
1772 struct pci_dev *pdev = mgp->pdev;
1773
1774 free_irq(pdev->irq, mgp);
1775 if (mgp->msi_enabled)
1776 pci_disable_msi(pdev);
1777}
1778
1e6e9342
AG		 1779static int
1780myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1781 void **ip_hdr, void **tcpudp_hdr,
1782 u64 * hdr_flags, void *priv)
1783{
1784 struct ethhdr *eh;
1785 struct vlan_ethhdr *veh;
1786 struct iphdr *iph;
1787 u8 *va = page_address(frag->page) + frag->page_offset;
1788 unsigned long ll_hlen;
1789 __wsum csum = (__wsum) (unsigned long)priv;
1790
1791 /* find the mac header, aborting if not IPv4 */
1792
1793 eh = (struct ethhdr *)va;
1794 *mac_hdr = eh;
1795 ll_hlen = ETH_HLEN;
1796 if (eh->h_proto != htons(ETH_P_IP)) {
1797 if (eh->h_proto == htons(ETH_P_8021Q)) {
1798 veh = (struct vlan_ethhdr *)va;
1799 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1800 return -1;
1801
1802 ll_hlen += VLAN_HLEN;
1803
1804 /*
1805 * HW checksum starts ETH_HLEN bytes into
1806 * frame, so we must subtract off the VLAN
1807 * header's checksum before csum can be used
1808 */
1809 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1810 VLAN_HLEN, 0));
1811 } else {
1812 return -1;
1813 }
1814 }
1815 *hdr_flags = LRO_IPV4;
1816
1817 iph = (struct iphdr *)(va + ll_hlen);
1818 *ip_hdr = iph;
1819 if (iph->protocol != IPPROTO_TCP)
1820 return -1;
1821 *hdr_flags |= LRO_TCP;
1822 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1823
1824 /* verify the IP checksum */
1825 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1826 return -1;
1827
1828 /* verify the checksum */
1829 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1830 ntohs(iph->tot_len) - (iph->ihl << 2),
1831 IPPROTO_TCP, csum)))
1832 return -1;
1833
1834 return 0;
1835}
1836
0da34b6d
BG		 1837static int myri10ge_open(struct net_device *dev)
1838{
1839 struct myri10ge_priv *mgp;
1840 struct myri10ge_cmd cmd;
1e6e9342 1841 struct net_lro_mgr *lro_mgr;
0da34b6d
BG		 1842 int status, big_pow2;
1843
1844 mgp = netdev_priv(dev);
1845
1846 if (mgp->running != MYRI10GE_ETH_STOPPED)
1847 return -EBUSY;
1848
1849 mgp->running = MYRI10GE_ETH_STARTING;
1850 status = myri10ge_reset(mgp);
1851 if (status != 0) {
1852 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1853 goto abort_with_nothing;
0da34b6d
BG		 1854 }
1855
df30a740
BG		 1856 status = myri10ge_request_irq(mgp);
1857 if (status != 0)
1858 goto abort_with_nothing;
1859
0da34b6d
BG		 1860 /* decide what small buffer size to use. For good TCP rx
1861 * performance, it is important to not receive 1514 byte
1862 * frames into jumbo buffers, as it confuses the socket buffer
1863 * accounting code, leading to drops and erratic performance.
1864 */
1865
1866 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1867 /* enough for a TCP header */
1868 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1869 ? (128 - MXGEFW_PAD)
1870 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1871 else
de3c4507
BG		 1872 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1873 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1874
1875 /* Override the small buffer size? */
1876 if (myri10ge_small_bytes > 0)
1877 mgp->small_bytes = myri10ge_small_bytes;
1878
0da34b6d
BG		 1879 /* get the lanai pointers to the send and receive rings */
1880
1881 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1882 mgp->tx.lanai =
1883 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1884
1885 status |=
1886 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1887 mgp->rx_small.lanai =
1888 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1889
1890 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1891 mgp->rx_big.lanai =
1892 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1893
1894 if (status != 0) {
1895 printk(KERN_ERR
1896 "myri10ge: %s: failed to get ring sizes or locations\n",
1897 dev->name);
1898 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1899 goto abort_with_irq;
0da34b6d
BG		 1900 }
1901
276e26c3 1902 if (myri10ge_wcfifo && mgp->wc_enabled) {
e700f9f4
BG		 1903 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1904 mgp->rx_small.wc_fifo =
1905 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1906 mgp->rx_big.wc_fifo =
1907 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1908 } else {
1909 mgp->tx.wc_fifo = NULL;
1910 mgp->rx_small.wc_fifo = NULL;
1911 mgp->rx_big.wc_fifo = NULL;
1912 }
1913
0da34b6d
BG		 1914 /* Firmware needs the big buff size as a power of 2. Lie and
1915 * tell him the buffer is larger, because we only use 1
1916 * buffer/pkt, and the mtu will prevent overruns.
1917 */
13348bee 1918 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 1919 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 1920 while (!is_power_of_2(big_pow2))
c7dab99b 1921 big_pow2++;
13348bee 1922 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1923 } else {
1924 big_pow2 = MYRI10GE_ALLOC_SIZE;
1925 mgp->big_bytes = big_pow2;
1926 }
1927
1928 status = myri10ge_allocate_rings(dev);
1929 if (status != 0)
df30a740 1930 goto abort_with_irq;
0da34b6d
BG		 1931
1932 /* now give firmware buffers sizes, and MTU */
1933 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1934 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1935 cmd.data0 = mgp->small_bytes;
1936 status |=
1937 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1938 cmd.data0 = big_pow2;
1939 status |=
1940 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1941 if (status) {
1942 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1943 dev->name);
1944 goto abort_with_rings;
1945 }
1946
1947 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1948 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1949 cmd.data2 = sizeof(struct mcp_irq_data);
1950 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1951 if (status == -ENOSYS) {
1952 dma_addr_t bus = mgp->fw_stats_bus;
1953 bus += offsetof(struct mcp_irq_data, send_done_count);
1954 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1955 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1956 status = myri10ge_send_cmd(mgp,
1957 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1958 &cmd, 0);
1959 /* Firmware cannot support multicast without STATS_DMA_V2 */
1960 mgp->fw_multicast_support = 0;
1961 } else {
1962 mgp->fw_multicast_support = 1;
1963 }
0da34b6d
BG		 1964 if (status) {
1965 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1966 dev->name);
1967 goto abort_with_rings;
1968 }
1969
40f6cff5 1970 mgp->link_state = htonl(~0U);
0da34b6d
BG		 1971 mgp->rdma_tags_available = 15;
1972
1e6e9342
AG		 1973 lro_mgr = &mgp->rx_done.lro_mgr;
1974 lro_mgr->dev = dev;
1975 lro_mgr->features = LRO_F_NAPI;
1976 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
1977 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
1978 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
1979 lro_mgr->lro_arr = mgp->rx_done.lro_desc;
1980 lro_mgr->get_frag_header = myri10ge_get_frag_header;
1981 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
621544eb 1982 lro_mgr->frag_align_pad = 2;
1e6e9342
AG		 1983 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
1984 lro_mgr->max_aggr = MAX_SKB_FRAGS;
1985
bea3348e 1986 napi_enable(&mgp->napi); /* must happen prior to any irq */
0da34b6d
BG		 1987
1988 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1989 if (status) {
1990 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1991 dev->name);
1992 goto abort_with_rings;
1993 }
1994
1995 mgp->wake_queue = 0;
1996 mgp->stop_queue = 0;
1997 mgp->running = MYRI10GE_ETH_RUNNING;
1998 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1999 add_timer(&mgp->watchdog_timer);
2000 netif_wake_queue(dev);
2001 return 0;
2002
2003abort_with_rings:
2004 myri10ge_free_rings(dev);
2005
df30a740
BG		 2006abort_with_irq:
2007 myri10ge_free_irq(mgp);
2008
0da34b6d
BG		 2009abort_with_nothing:
2010 mgp->running = MYRI10GE_ETH_STOPPED;
2011 return -ENOMEM;
2012}
2013
2014static int myri10ge_close(struct net_device *dev)
2015{
2016 struct myri10ge_priv *mgp;
2017 struct myri10ge_cmd cmd;
2018 int status, old_down_cnt;
2019
2020 mgp = netdev_priv(dev);
2021
2022 if (mgp->running != MYRI10GE_ETH_RUNNING)
2023 return 0;
2024
2025 if (mgp->tx.req_bytes == NULL)
2026 return 0;
2027
2028 del_timer_sync(&mgp->watchdog_timer);
2029 mgp->running = MYRI10GE_ETH_STOPPING;
bea3348e 2030 napi_disable(&mgp->napi);
0da34b6d
BG		 2031 netif_carrier_off(dev);
2032 netif_stop_queue(dev);
2033 old_down_cnt = mgp->down_cnt;
2034 mb();
2035 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2036 if (status)
2037 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2038 dev->name);
2039
2040 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2041 if (old_down_cnt == mgp->down_cnt)
2042 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2043
2044 netif_tx_disable(dev);
df30a740 2045 myri10ge_free_irq(mgp);
0da34b6d
BG		 2046 myri10ge_free_rings(dev);
2047
2048 mgp->running = MYRI10GE_ETH_STOPPED;
2049 return 0;
2050}
2051
2052/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2053 * backwards one at a time and handle ring wraps */
2054
2055static inline void
2056myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2057 struct mcp_kreq_ether_send *src, int cnt)
2058{
2059 int idx, starting_slot;
2060 starting_slot = tx->req;
2061 while (cnt > 1) {
2062 cnt--;
2063 idx = (starting_slot + cnt) & tx->mask;
2064 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2065 mb();
2066 }
2067}
2068
2069/*
2070 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2071 * at most 32 bytes at a time, so as to avoid involving the software
2072 * pio handler in the nic. We re-write the first segment's flags
2073 * to mark them valid only after writing the entire chain.
2074 */
2075
2076static inline void
2077myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2078 int cnt)
2079{
2080 int idx, i;
2081 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2082 struct mcp_kreq_ether_send *srcp;
2083 u8 last_flags;
2084
2085 idx = tx->req & tx->mask;
2086
2087 last_flags = src->flags;
2088 src->flags = 0;
2089 mb();
2090 dst = dstp = &tx->lanai[idx];
2091 srcp = src;
2092
2093 if ((idx + cnt) < tx->mask) {
2094 for (i = 0; i < (cnt - 1); i += 2) {
2095 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2096 mb(); /* force write every 32 bytes */
2097 srcp += 2;
2098 dstp += 2;
2099 }
2100 } else {
2101 /* submit all but the first request, and ensure
2102 * that it is submitted below */
2103 myri10ge_submit_req_backwards(tx, src, cnt);
2104 i = 0;
2105 }
2106 if (i < cnt) {
2107 /* submit the first request */
2108 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2109 mb(); /* barrier before setting valid flag */
2110 }
2111
2112 /* re-write the last 32-bits with the valid flags */
2113 src->flags = last_flags;
40f6cff5 2114 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2115 tx->req += cnt;
2116 mb();
2117}
2118
2119static inline void
2120myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2121 struct mcp_kreq_ether_send *src, int cnt)
2122{
2123 tx->req += cnt;
2124 mb();
2125 while (cnt >= 4) {
2126 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2127 mb();
2128 src += 4;
2129 cnt -= 4;
2130 }
2131 if (cnt > 0) {
2132 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2133 * needs to be so that we don't overrun it */
e700f9f4
BG		 2134 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2135 src, 64);
0da34b6d
BG		 2136 mb();
2137 }
2138}
2139
2140/*
2141 * Transmit a packet. We need to split the packet so that a single
2142 * segment does not cross myri10ge->tx.boundary, so this makes segment
2143 * counting tricky. So rather than try to count segments up front, we
2144 * just give up if there are too few segments to hold a reasonably
2145 * fragmented packet currently available. If we run
2146 * out of segments while preparing a packet for DMA, we just linearize
2147 * it and try again.
2148 */
2149
2150static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2151{
2152 struct myri10ge_priv *mgp = netdev_priv(dev);
2153 struct mcp_kreq_ether_send *req;
2154 struct myri10ge_tx_buf *tx = &mgp->tx;
2155 struct skb_frag_struct *frag;
2156 dma_addr_t bus;
40f6cff5
AV		 2157 u32 low;
2158 __be32 high_swapped;
0da34b6d
BG		 2159 unsigned int len;
2160 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2161 u16 pseudo_hdr_offset, cksum_offset;
2162 int cum_len, seglen, boundary, rdma_count;
2163 u8 flags, odd_flag;
2164
2165again:
2166 req = tx->req_list;
2167 avail = tx->mask - 1 - (tx->req - tx->done);
2168
2169 mss = 0;
2170 max_segments = MXGEFW_MAX_SEND_DESC;
2171
917690cd 2172 if (skb_is_gso(skb)) {
7967168c 2173 mss = skb_shinfo(skb)->gso_size;
917690cd 2174 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2175 }
0da34b6d
BG		 2176
2177 if ((unlikely(avail < max_segments))) {
2178 /* we are out of transmit resources */
2179 mgp->stop_queue++;
2180 netif_stop_queue(dev);
2181 return 1;
2182 }
2183
2184 /* Setup checksum offloading, if needed */
2185 cksum_offset = 0;
2186 pseudo_hdr_offset = 0;
2187 odd_flag = 0;
2188 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2189 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2190 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2191 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2192 /* If the headers are excessively large, then we must
2193 * fall back to a software checksum */
4f93fde0
BG		 2194 if (unlikely(!mss && (cksum_offset > 255 ||
2195 pseudo_hdr_offset > 127))) {
84fa7933 2196 if (skb_checksum_help(skb))
0da34b6d
BG		 2197 goto drop;
2198 cksum_offset = 0;
2199 pseudo_hdr_offset = 0;
2200 } else {
0da34b6d
BG		 2201 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2202 flags |= MXGEFW_FLAGS_CKSUM;
2203 }
2204 }
2205
2206 cum_len = 0;
2207
0da34b6d
BG		 2208 if (mss) { /* TSO */
2209 /* this removes any CKSUM flag from before */
2210 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2211
2212 /* negative cum_len signifies to the
2213 * send loop that we are still in the
2214 * header portion of the TSO packet.
4f93fde0 2215 * TSO header can be at most 1KB long */
ab6a5bb6 2216 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2217
4f93fde0
BG		 2218 /* for IPv6 TSO, the checksum offset stores the
2219 * TCP header length, to save the firmware from
2220 * the need to parse the headers */
2221 if (skb_is_gso_v6(skb)) {
2222 cksum_offset = tcp_hdrlen(skb);
2223 /* Can only handle headers <= max_tso6 long */
2224 if (unlikely(-cum_len > mgp->max_tso6))
2225 return myri10ge_sw_tso(skb, dev);
2226 }
0da34b6d
BG		 2227 /* for TSO, pseudo_hdr_offset holds mss.
2228 * The firmware figures out where to put
2229 * the checksum by parsing the header. */
40f6cff5 2230 pseudo_hdr_offset = mss;
0da34b6d 2231 } else
0da34b6d
BG		 2232 /* Mark small packets, and pad out tiny packets */
2233 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2234 flags |= MXGEFW_FLAGS_SMALL;
2235
2236 /* pad frames to at least ETH_ZLEN bytes */
2237 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2238 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2239 /* The packet is gone, so we must
2240 * return 0 */
2241 mgp->stats.tx_dropped += 1;
2242 return 0;
2243 }
2244 /* adjust the len to account for the zero pad
2245 * so that the nic can know how long it is */
2246 skb->len = ETH_ZLEN;
2247 }
2248 }
2249
2250 /* map the skb for DMA */
2251 len = skb->len - skb->data_len;
2252 idx = tx->req & tx->mask;
2253 tx->info[idx].skb = skb;
2254 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2255 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2256 pci_unmap_len_set(&tx->info[idx], len, len);
2257
2258 frag_cnt = skb_shinfo(skb)->nr_frags;
2259 frag_idx = 0;
2260 count = 0;
2261 rdma_count = 0;
2262
2263 /* "rdma_count" is the number of RDMAs belonging to the
2264 * current packet BEFORE the current send request. For
2265 * non-TSO packets, this is equal to "count".
2266 * For TSO packets, rdma_count needs to be reset
2267 * to 0 after a segment cut.
2268 *
2269 * The rdma_count field of the send request is
2270 * the number of RDMAs of the packet starting at
2271 * that request. For TSO send requests with one ore more cuts
2272 * in the middle, this is the number of RDMAs starting
2273 * after the last cut in the request. All previous
2274 * segments before the last cut implicitly have 1 RDMA.
2275 *
2276 * Since the number of RDMAs is not known beforehand,
2277 * it must be filled-in retroactively - after each
2278 * segmentation cut or at the end of the entire packet.
2279 */
2280
2281 while (1) {
2282 /* Break the SKB or Fragment up into pieces which
2283 * do not cross mgp->tx.boundary */
2284 low = MYRI10GE_LOWPART_TO_U32(bus);
2285 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2286 while (len) {
2287 u8 flags_next;
2288 int cum_len_next;
2289
2290 if (unlikely(count == max_segments))
2291 goto abort_linearize;
2292
2293 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2294 seglen = boundary - low;
2295 if (seglen > len)
2296 seglen = len;
2297 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2298 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2299 if (mss) { /* TSO */
2300 (req - rdma_count)->rdma_count = rdma_count + 1;
2301
2302 if (likely(cum_len >= 0)) { /* payload */
2303 int next_is_first, chop;
2304
2305 chop = (cum_len_next > mss);
2306 cum_len_next = cum_len_next % mss;
2307 next_is_first = (cum_len_next == 0);
2308 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2309 flags_next |= next_is_first *
2310 MXGEFW_FLAGS_FIRST;
2311 rdma_count |= -(chop | next_is_first);
2312 rdma_count += chop & !next_is_first;
2313 } else if (likely(cum_len_next >= 0)) { /* header ends */
2314 int small;
2315
2316 rdma_count = -1;
2317 cum_len_next = 0;
2318 seglen = -cum_len;
2319 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2320 flags_next = MXGEFW_FLAGS_TSO_PLD |
2321 MXGEFW_FLAGS_FIRST |
2322 (small * MXGEFW_FLAGS_SMALL);
2323 }
2324 }
0da34b6d
BG		 2325 req->addr_high = high_swapped;
2326 req->addr_low = htonl(low);
40f6cff5 2327 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2328 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2329 req->rdma_count = 1;
2330 req->length = htons(seglen);
2331 req->cksum_offset = cksum_offset;
2332 req->flags = flags | ((cum_len & 1) * odd_flag);
2333
2334 low += seglen;
2335 len -= seglen;
2336 cum_len = cum_len_next;
2337 flags = flags_next;
2338 req++;
2339 count++;
2340 rdma_count++;
4f93fde0
BG		 2341 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2342 if (unlikely(cksum_offset > seglen))
2343 cksum_offset -= seglen;
2344 else
2345 cksum_offset = 0;
2346 }
0da34b6d
BG		 2347 }
2348 if (frag_idx == frag_cnt)
2349 break;
2350
2351 /* map next fragment for DMA */
2352 idx = (count + tx->req) & tx->mask;
2353 frag = &skb_shinfo(skb)->frags[frag_idx];
2354 frag_idx++;
2355 len = frag->size;
2356 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2357 len, PCI_DMA_TODEVICE);
2358 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2359 pci_unmap_len_set(&tx->info[idx], len, len);
2360 }
2361
2362 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2363 if (mss)
2364 do {
2365 req--;
2366 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2367 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2368 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2369 idx = ((count - 1) + tx->req) & tx->mask;
2370 tx->info[idx].last = 1;
2371 if (tx->wc_fifo == NULL)
2372 myri10ge_submit_req(tx, tx->req_list, count);
2373 else
2374 myri10ge_submit_req_wc(tx, tx->req_list, count);
2375 tx->pkt_start++;
2376 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2377 mgp->stop_queue++;
2378 netif_stop_queue(dev);
2379 }
2380 dev->trans_start = jiffies;
2381 return 0;
2382
2383abort_linearize:
2384 /* Free any DMA resources we've alloced and clear out the skb
2385 * slot so as to not trip up assertions, and to avoid a
2386 * double-free if linearizing fails */
2387
2388 last_idx = (idx + 1) & tx->mask;
2389 idx = tx->req & tx->mask;
2390 tx->info[idx].skb = NULL;
2391 do {
2392 len = pci_unmap_len(&tx->info[idx], len);
2393 if (len) {
2394 if (tx->info[idx].skb != NULL)
2395 pci_unmap_single(mgp->pdev,
2396 pci_unmap_addr(&tx->info[idx],
2397 bus), len,
2398 PCI_DMA_TODEVICE);
2399 else
2400 pci_unmap_page(mgp->pdev,
2401 pci_unmap_addr(&tx->info[idx],
2402 bus), len,
2403 PCI_DMA_TODEVICE);
2404 pci_unmap_len_set(&tx->info[idx], len, 0);
2405 tx->info[idx].skb = NULL;
2406 }
2407 idx = (idx + 1) & tx->mask;
2408 } while (idx != last_idx);
89114afd 2409 if (skb_is_gso(skb)) {
0da34b6d
BG		 2410 printk(KERN_ERR
2411 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2412 mgp->dev->name);
2413 goto drop;
2414 }
2415
bec0e859 2416 if (skb_linearize(skb))
0da34b6d
BG		 2417 goto drop;
2418
2419 mgp->tx_linearized++;
2420 goto again;
2421
2422drop:
2423 dev_kfree_skb_any(skb);
2424 mgp->stats.tx_dropped += 1;
2425 return 0;
2426
2427}
2428
4f93fde0
BG		 2429static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2430{
2431 struct sk_buff *segs, *curr;
2432 struct myri10ge_priv *mgp = dev->priv;
2433 int status;
2434
2435 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2436 if (unlikely(IS_ERR(segs)))
2437 goto drop;
2438
2439 while (segs) {
2440 curr = segs;
2441 segs = segs->next;
2442 curr->next = NULL;
2443 status = myri10ge_xmit(curr, dev);
2444 if (status != 0) {
2445 dev_kfree_skb_any(curr);
2446 if (segs != NULL) {
2447 curr = segs;
2448 segs = segs->next;
2449 curr->next = NULL;
2450 dev_kfree_skb_any(segs);
2451 }
2452 goto drop;
2453 }
2454 }
2455 dev_kfree_skb_any(skb);
2456 return 0;
2457
2458drop:
2459 dev_kfree_skb_any(skb);
2460 mgp->stats.tx_dropped += 1;
2461 return 0;
2462}
2463
0da34b6d
BG		 2464static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2465{
2466 struct myri10ge_priv *mgp = netdev_priv(dev);
2467 return &mgp->stats;
2468}
2469
2470static void myri10ge_set_multicast_list(struct net_device *dev)
2471{
85a7ea1b
BG		 2472 struct myri10ge_cmd cmd;
2473 struct myri10ge_priv *mgp;
2474 struct dev_mc_list *mc_list;
6250223e 2475 __be32 data[2] = { 0, 0 };
85a7ea1b 2476 int err;
0795af57 2477 DECLARE_MAC_BUF(mac);
85a7ea1b
BG		 2478
2479 mgp = netdev_priv(dev);
0da34b6d
BG		 2480 /* can be called from atomic contexts,
2481 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2482 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2483
2484 /* This firmware is known to not support multicast */
2f76216f 2485 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2486 return;
2487
2488 /* Disable multicast filtering */
2489
2490 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2491 if (err != 0) {
2492 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2493 " error status: %d\n", dev->name, err);
2494 goto abort;
2495 }
2496
2f76216f 2497 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2498 /* request to disable multicast filtering, so quit here */
2499 return;
2500 }
2501
2502 /* Flush the filters */
2503
2504 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2505 &cmd, 1);
2506 if (err != 0) {
2507 printk(KERN_ERR
2508 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2509 ", error status: %d\n", dev->name, err);
2510 goto abort;
2511 }
2512
2513 /* Walk the multicast list, and add each address */
2514 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2515 memcpy(data, &mc_list->dmi_addr, 6);
2516 cmd.data0 = ntohl(data[0]);
2517 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2518 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2519 &cmd, 1);
2520
2521 if (err != 0) {
2522 printk(KERN_ERR "myri10ge: %s: Failed "
2523 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2524 "%d\t", dev->name, err);
0795af57
JP		 2525 printk(KERN_ERR "MAC %s\n",
2526 print_mac(mac, mc_list->dmi_addr));
85a7ea1b
BG		 2527 goto abort;
2528 }
2529 }
2530 /* Enable multicast filtering */
2531 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2532 if (err != 0) {
2533 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2534 "error status: %d\n", dev->name, err);
2535 goto abort;
2536 }
2537
2538 return;
2539
2540abort:
2541 return;
0da34b6d
BG		 2542}
2543
2544static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2545{
2546 struct sockaddr *sa = addr;
2547 struct myri10ge_priv *mgp = netdev_priv(dev);
2548 int status;
2549
2550 if (!is_valid_ether_addr(sa->sa_data))
2551 return -EADDRNOTAVAIL;
2552
2553 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2554 if (status != 0) {
2555 printk(KERN_ERR
2556 "myri10ge: %s: changing mac address failed with %d\n",
2557 dev->name, status);
2558 return status;
2559 }
2560
2561 /* change the dev structure */
2562 memcpy(dev->dev_addr, sa->sa_data, 6);
2563 return 0;
2564}
2565
2566static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2567{
2568 struct myri10ge_priv *mgp = netdev_priv(dev);
2569 int error = 0;
2570
2571 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2572 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2573 dev->name, new_mtu);
2574 return -EINVAL;
2575 }
2576 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2577 dev->name, dev->mtu, new_mtu);
2578 if (mgp->running) {
2579 /* if we change the mtu on an active device, we must
2580 * reset the device so the firmware sees the change */
2581 myri10ge_close(dev);
2582 dev->mtu = new_mtu;
2583 myri10ge_open(dev);
2584 } else
2585 dev->mtu = new_mtu;
2586
2587 return error;
2588}
2589
2590/*
2591 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2592 * Only do it if the bridge is a root port since we don't want to disturb
2593 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2594 */
2595
0da34b6d
BG		 2596static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2597{
2598 struct pci_dev *bridge = mgp->pdev->bus->self;
2599 struct device *dev = &mgp->pdev->dev;
2600 unsigned cap;
2601 unsigned err_cap;
2602 u16 val;
2603 u8 ext_type;
2604 int ret;
2605
2606 if (!myri10ge_ecrc_enable || !bridge)
2607 return;
2608
2609 /* check that the bridge is a root port */
2610 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2611 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2612 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2613 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2614 if (myri10ge_ecrc_enable > 1) {
2615 struct pci_dev *old_bridge = bridge;
2616
2617 /* Walk the hierarchy up to the root port
2618 * where ECRC has to be enabled */
2619 do {
2620 bridge = bridge->bus->self;
2621 if (!bridge) {
2622 dev_err(dev,
2623 "Failed to find root port"
2624 " to force ECRC\n");
2625 return;
2626 }
2627 cap =
2628 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2629 pci_read_config_word(bridge,
2630 cap + PCI_CAP_FLAGS, &val);
2631 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2632 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2633
2634 dev_info(dev,
2635 "Forcing ECRC on non-root port %s"
2636 " (enabling on root port %s)\n",
2637 pci_name(old_bridge), pci_name(bridge));
2638 } else {
2639 dev_err(dev,
2640 "Not enabling ECRC on non-root port %s\n",
2641 pci_name(bridge));
2642 return;
2643 }
2644 }
2645
2646 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2647 if (!cap)
2648 return;
2649
2650 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2651 if (ret) {
2652 dev_err(dev, "failed reading ext-conf-space of %s\n",
2653 pci_name(bridge));
2654 dev_err(dev, "\t pci=nommconf in use? "
2655 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2656 return;
2657 }
2658 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2659 return;
2660
2661 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2662 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2663 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 2664}
2665
2666/*
2667 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2668 * when the PCI-E Completion packets are aligned on an 8-byte
2669 * boundary. Some PCI-E chip sets always align Completion packets; on
2670 * the ones that do not, the alignment can be enforced by enabling
2671 * ECRC generation (if supported).
2672 *
2673 * When PCI-E Completion packets are not aligned, it is actually more
2674 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2675 *
2676 * If the driver can neither enable ECRC nor verify that it has
2677 * already been enabled, then it must use a firmware image which works
2678 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2679 * should also ensure that it never gives the device a Read-DMA which is
2680 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2681 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2682 * firmware image, and set tx.boundary to 4KB.
2683 */
2684
5443e9ea 2685static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 2686{
5443e9ea
BG		 2687 struct pci_dev *pdev = mgp->pdev;
2688 struct device *dev = &pdev->dev;
302d242c 2689 int status;
0da34b6d 2690
5443e9ea
BG		 2691 mgp->tx.boundary = 4096;
2692 /*
2693 * Verify the max read request size was set to 4KB
2694 * before trying the test with 4KB.
2695 */
302d242c
BG		 2696 status = pcie_get_readrq(pdev);
2697 if (status < 0) {
5443e9ea
BG		 2698 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2699 goto abort;
2700 }
302d242c
BG		 2701 if (status != 4096) {
2702 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
5443e9ea
BG		 2703 mgp->tx.boundary = 2048;
2704 }
2705 /*
2706 * load the optimized firmware (which assumes aligned PCIe
2707 * completions) in order to see if it works on this host.
2708 */
2709 mgp->fw_name = myri10ge_fw_aligned;
2710 status = myri10ge_load_firmware(mgp);
2711 if (status != 0) {
2712 goto abort;
2713 }
2714
2715 /*
2716 * Enable ECRC if possible
2717 */
2718 myri10ge_enable_ecrc(mgp);
2719
2720 /*
2721 * Run a DMA test which watches for unaligned completions and
2722 * aborts on the first one seen.
2723 */
2724
2725 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2726 if (status == 0)
2727 return; /* keep the aligned firmware */
2728
2729 if (status != -E2BIG)
2730 dev_warn(dev, "DMA test failed: %d\n", status);
2731 if (status == -ENOSYS)
2732 dev_warn(dev, "Falling back to ethp! "
2733 "Please install up to date fw\n");
2734abort:
2735 /* fall back to using the unaligned firmware */
0da34b6d
BG		 2736 mgp->tx.boundary = 2048;
2737 mgp->fw_name = myri10ge_fw_unaligned;
2738
5443e9ea
BG		 2739}
2740
2741static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2742{
0da34b6d 2743 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2744 int link_width, exp_cap;
2745 u16 lnk;
2746
2747 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2748 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2749 link_width = (lnk >> 4) & 0x3f;
2750
ce7f9368
BG		 2751 /* Check to see if Link is less than 8 or if the
2752 * upstream bridge is known to provide aligned
2753 * completions */
2754 if (link_width < 8) {
2755 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2756 link_width);
2757 mgp->tx.boundary = 4096;
2758 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 2759 } else {
2760 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 2761 }
2762 } else {
2763 if (myri10ge_force_firmware == 1) {
2764 dev_info(&mgp->pdev->dev,
2765 "Assuming aligned completions (forced)\n");
2766 mgp->tx.boundary = 4096;
2767 mgp->fw_name = myri10ge_fw_aligned;
2768 } else {
2769 dev_info(&mgp->pdev->dev,
2770 "Assuming unaligned completions (forced)\n");
2771 mgp->tx.boundary = 2048;
2772 mgp->fw_name = myri10ge_fw_unaligned;
2773 }
2774 }
2775 if (myri10ge_fw_name != NULL) {
2776 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2777 myri10ge_fw_name);
2778 mgp->fw_name = myri10ge_fw_name;
2779 }
2780}
2781
0da34b6d 2782#ifdef CONFIG_PM
0da34b6d
BG		 2783static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2784{
2785 struct myri10ge_priv *mgp;
2786 struct net_device *netdev;
2787
2788 mgp = pci_get_drvdata(pdev);
2789 if (mgp == NULL)
2790 return -EINVAL;
2791 netdev = mgp->dev;
2792
2793 netif_device_detach(netdev);
2794 if (netif_running(netdev)) {
2795 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2796 rtnl_lock();
2797 myri10ge_close(netdev);
2798 rtnl_unlock();
2799 }
2800 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2801 pci_save_state(pdev);
0da34b6d 2802 pci_disable_device(pdev);
1a63e846
BG		 2803
2804 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2805}
2806
2807static int myri10ge_resume(struct pci_dev *pdev)
2808{
2809 struct myri10ge_priv *mgp;
2810 struct net_device *netdev;
2811 int status;
2812 u16 vendor;
2813
2814 mgp = pci_get_drvdata(pdev);
2815 if (mgp == NULL)
2816 return -EINVAL;
2817 netdev = mgp->dev;
2818 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2819 msleep(5); /* give card time to respond */
2820 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2821 if (vendor == 0xffff) {
2822 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2823 mgp->dev->name);
2824 return -EIO;
2825 }
83f6e152 2826
1a63e846
BG		 2827 status = pci_restore_state(pdev);
2828 if (status)
2829 return status;
4c2248cc
BG		 2830
2831 status = pci_enable_device(pdev);
1a63e846 2832 if (status) {
4c2248cc 2833 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2834 return status;
4c2248cc
BG		 2835 }
2836
0da34b6d
BG		 2837 pci_set_master(pdev);
2838
0da34b6d 2839 myri10ge_reset(mgp);
013b68bf 2840 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2841
2842 /* Save configuration space to be restored if the
2843 * nic resets due to a parity error */
83f6e152 2844 pci_save_state(pdev);
0da34b6d
BG		 2845
2846 if (netif_running(netdev)) {
2847 rtnl_lock();
df30a740 2848 status = myri10ge_open(netdev);
0da34b6d 2849 rtnl_unlock();
df30a740
BG		 2850 if (status != 0)
2851 goto abort_with_enabled;
2852
0da34b6d
BG		 2853 }
2854 netif_device_attach(netdev);
2855
2856 return 0;
2857
4c2248cc
BG		 2858abort_with_enabled:
2859 pci_disable_device(pdev);
0da34b6d
BG		 2860 return -EIO;
2861
2862}
0da34b6d
BG		 2863#endif /* CONFIG_PM */
2864
2865static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2866{
2867 struct pci_dev *pdev = mgp->pdev;
2868 int vs = mgp->vendor_specific_offset;
2869 u32 reboot;
2870
2871 /*enter read32 mode */
2872 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2873
2874 /*read REBOOT_STATUS (0xfffffff0) */
2875 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2876 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2877 return reboot;
2878}
2879
2880/*
2881 * This watchdog is used to check whether the board has suffered
2882 * from a parity error and needs to be recovered.
2883 */
c4028958 2884static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2885{
c4028958 2886 struct myri10ge_priv *mgp =
6250223e 2887 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2888 u32 reboot;
2889 int status;
2890 u16 cmd, vendor;
2891
2892 mgp->watchdog_resets++;
2893 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2894 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2895 /* Bus master DMA disabled? Check to see
2896 * if the card rebooted due to a parity error
2897 * For now, just report it */
2898 reboot = myri10ge_read_reboot(mgp);
2899 printk(KERN_ERR
f181137f
BG		 2900 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2901 mgp->dev->name, reboot,
2902 myri10ge_reset_recover ? " " : " not");
2903 if (myri10ge_reset_recover == 0)
2904 return;
2905
2906 myri10ge_reset_recover--;
2907
0da34b6d
BG		 2908 /*
2909 * A rebooted nic will come back with config space as
2910 * it was after power was applied to PCIe bus.
2911 * Attempt to restore config space which was saved
2912 * when the driver was loaded, or the last time the
2913 * nic was resumed from power saving mode.
2914 */
83f6e152 2915 pci_restore_state(mgp->pdev);
7adda30c
BG		 2916
2917 /* save state again for accounting reasons */
83f6e152 2918 pci_save_state(mgp->pdev);
7adda30c 2919
0da34b6d
BG		 2920 } else {
2921 /* if we get back -1's from our slot, perhaps somebody
2922 * powered off our card. Don't try to reset it in
2923 * this case */
2924 if (cmd == 0xffff) {
2925 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2926 if (vendor == 0xffff) {
2927 printk(KERN_ERR
2928 "myri10ge: %s: device disappeared!\n",
2929 mgp->dev->name);
2930 return;
2931 }
2932 }
2933 /* Perhaps it is a software error. Try to reset */
2934
2935 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2936 mgp->dev->name);
2937 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2938 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2939 mgp->tx.pkt_start, mgp->tx.pkt_done,
2940 (int)ntohl(mgp->fw_stats->send_done_count));
2941 msleep(2000);
2942 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2943 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2944 mgp->tx.pkt_start, mgp->tx.pkt_done,
2945 (int)ntohl(mgp->fw_stats->send_done_count));
2946 }
2947 rtnl_lock();
2948 myri10ge_close(mgp->dev);
2949 status = myri10ge_load_firmware(mgp);
2950 if (status != 0)
2951 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2952 mgp->dev->name);
2953 else
2954 myri10ge_open(mgp->dev);
2955 rtnl_unlock();
2956}
2957
2958/*
2959 * We use our own timer routine rather than relying upon
2960 * netdev->tx_timeout because we have a very large hardware transmit
2961 * queue. Due to the large queue, the netdev->tx_timeout function
2962 * cannot detect a NIC with a parity error in a timely fashion if the
2963 * NIC is lightly loaded.
2964 */
2965static void myri10ge_watchdog_timer(unsigned long arg)
2966{
2967 struct myri10ge_priv *mgp;
626fda94 2968 u32 rx_pause_cnt;
0da34b6d
BG		 2969
2970 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2971
2972 if (mgp->rx_small.watchdog_needed) {
2973 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2974 mgp->small_bytes + MXGEFW_PAD, 1);
2975 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2976 myri10ge_fill_thresh)
2977 mgp->rx_small.watchdog_needed = 0;
2978 }
2979 if (mgp->rx_big.watchdog_needed) {
2980 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2981 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2982 myri10ge_fill_thresh)
2983 mgp->rx_big.watchdog_needed = 0;
2984 }
626fda94 2985 rx_pause_cnt = ntohl(mgp->fw_stats->dropped_pause);
c7dab99b 2986
0da34b6d 2987 if (mgp->tx.req != mgp->tx.done &&
c54772e7 2988 mgp->tx.done == mgp->watchdog_tx_done &&
626fda94 2989 mgp->watchdog_tx_req != mgp->watchdog_tx_done) {
0da34b6d 2990 /* nic seems like it might be stuck.. */
626fda94
BG		 2991 if (rx_pause_cnt != mgp->watchdog_pause) {
2992 if (net_ratelimit())
2993 printk(KERN_WARNING "myri10ge %s:"
2994 "TX paused, check link partner\n",
2995 mgp->dev->name);
2996 } else {
2997 schedule_work(&mgp->watchdog_work);
2998 return;
2999 }
3000 }
3001 /* rearm timer */
3002 mod_timer(&mgp->watchdog_timer,
3003 jiffies + myri10ge_watchdog_timeout * HZ);
0da34b6d 3004 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 3005 mgp->watchdog_tx_req = mgp->tx.req;
626fda94 3006 mgp->watchdog_pause = rx_pause_cnt;
0da34b6d
BG		 3007}
3008
3009static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3010{
3011 struct net_device *netdev;
3012 struct myri10ge_priv *mgp;
3013 struct device *dev = &pdev->dev;
3014 size_t bytes;
3015 int i;
3016 int status = -ENXIO;
0da34b6d 3017 int dac_enabled;
0da34b6d
BG		 3018
3019 netdev = alloc_etherdev(sizeof(*mgp));
3020 if (netdev == NULL) {
3021 dev_err(dev, "Could not allocate ethernet device\n");
3022 return -ENOMEM;
3023 }
3024
b245fb67
MH		 3025 SET_NETDEV_DEV(netdev, &pdev->dev);
3026
0da34b6d 3027 mgp = netdev_priv(netdev);
0da34b6d 3028 mgp->dev = netdev;
e636b2ea 3029 netif_napi_add(netdev, &mgp->napi, myri10ge_poll, myri10ge_napi_weight);
0da34b6d
BG		 3030 mgp->pdev = pdev;
3031 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3032 mgp->pause = myri10ge_flow_control;
3033 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3034 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 3035 init_waitqueue_head(&mgp->down_wq);
3036
3037 if (pci_enable_device(pdev)) {
3038 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3039 status = -ENODEV;
3040 goto abort_with_netdev;
3041 }
0da34b6d
BG		 3042
3043 /* Find the vendor-specific cap so we can check
3044 * the reboot register later on */
3045 mgp->vendor_specific_offset
3046 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3047
3048 /* Set our max read request to 4KB */
302d242c 3049 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3050 if (status != 0) {
3051 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3052 status);
3053 goto abort_with_netdev;
3054 }
3055
3056 pci_set_master(pdev);
3057 dac_enabled = 1;
3058 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3059 if (status != 0) {
3060 dac_enabled = 0;
3061 dev_err(&pdev->dev,
898eb71c
JP		 3062 "64-bit pci address mask was refused, "
3063 "trying 32-bit\n");
0da34b6d
BG		 3064 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3065 }
3066 if (status != 0) {
3067 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3068 goto abort_with_netdev;
3069 }
b10c0668
BG		 3070 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3071 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 3072 if (mgp->cmd == NULL)
3073 goto abort_with_netdev;
3074
b10c0668
BG		 3075 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3076 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 3077 if (mgp->fw_stats == NULL)
3078 goto abort_with_cmd;
3079
3080 mgp->board_span = pci_resource_len(pdev, 0);
3081 mgp->iomem_base = pci_resource_start(pdev, 0);
3082 mgp->mtrr = -1;
276e26c3 3083 mgp->wc_enabled = 0;
0da34b6d
BG		 3084#ifdef CONFIG_MTRR
3085 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3086 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3087 if (mgp->mtrr >= 0)
3088 mgp->wc_enabled = 1;
0da34b6d
BG		 3089#endif
3090 /* Hack. need to get rid of these magic numbers */
3091 mgp->sram_size =
3092 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3093 if (mgp->sram_size > mgp->board_span) {
3094 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3095 mgp->board_span);
3096 goto abort_with_wc;
3097 }
3098 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3099 if (mgp->sram == NULL) {
3100 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3101 mgp->board_span, mgp->iomem_base);
3102 status = -ENXIO;
3103 goto abort_with_wc;
3104 }
3105 memcpy_fromio(mgp->eeprom_strings,
3106 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3107 MYRI10GE_EEPROM_STRINGS_SIZE);
3108 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3109 status = myri10ge_read_mac_addr(mgp);
3110 if (status)
3111 goto abort_with_ioremap;
3112
3113 for (i = 0; i < ETH_ALEN; i++)
3114 netdev->dev_addr[i] = mgp->mac_addr[i];
3115
3116 /* allocate rx done ring */
3117 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3118 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3119 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 3120 if (mgp->rx_done.entry == NULL)
3121 goto abort_with_ioremap;
3122 memset(mgp->rx_done.entry, 0, bytes);
3123
5443e9ea
BG		 3124 myri10ge_select_firmware(mgp);
3125
0da34b6d
BG		 3126 status = myri10ge_load_firmware(mgp);
3127 if (status != 0) {
3128 dev_err(&pdev->dev, "failed to load firmware\n");
3129 goto abort_with_rx_done;
3130 }
3131
3132 status = myri10ge_reset(mgp);
3133 if (status != 0) {
3134 dev_err(&pdev->dev, "failed reset\n");
3135 goto abort_with_firmware;
3136 }
3137
0da34b6d
BG		 3138 pci_set_drvdata(pdev, mgp);
3139 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3140 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3141 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3142 myri10ge_initial_mtu = 68;
3143 netdev->mtu = myri10ge_initial_mtu;
3144 netdev->open = myri10ge_open;
3145 netdev->stop = myri10ge_close;
3146 netdev->hard_start_xmit = myri10ge_xmit;
3147 netdev->get_stats = myri10ge_get_stats;
3148 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 3149 netdev->change_mtu = myri10ge_change_mtu;
3150 netdev->set_multicast_list = myri10ge_set_multicast_list;
3151 netdev->set_mac_address = myri10ge_set_mac_address;
4f93fde0 3152 netdev->features = mgp->features;
0da34b6d
BG		 3153 if (dac_enabled)
3154 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3155
21d05db1
BG		 3156 /* make sure we can get an irq, and that MSI can be
3157 * setup (if available). Also ensure netdev->irq
3158 * is set to correct value if MSI is enabled */
3159 status = myri10ge_request_irq(mgp);
3160 if (status != 0)
3161 goto abort_with_firmware;
3162 netdev->irq = pdev->irq;
3163 myri10ge_free_irq(mgp);
3164
0da34b6d
BG		 3165 /* Save configuration space to be restored if the
3166 * nic resets due to a parity error */
83f6e152 3167 pci_save_state(pdev);
0da34b6d
BG		 3168
3169 /* Setup the watchdog timer */
3170 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3171 (unsigned long)mgp);
3172
3173 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3174 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3175 status = register_netdev(netdev);
3176 if (status != 0) {
3177 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3178 goto abort_with_state;
0da34b6d 3179 }
21d05db1
BG		 3180 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3181 (mgp->msi_enabled ? "MSI" : "xPIC"),
3182 netdev->irq, mgp->tx.boundary, mgp->fw_name,
276e26c3 3183 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3184
3185 return 0;
3186
7adda30c 3187abort_with_state:
83f6e152 3188 pci_restore_state(pdev);
0da34b6d
BG		 3189
3190abort_with_firmware:
3191 myri10ge_dummy_rdma(mgp, 0);
3192
3193abort_with_rx_done:
3194 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3195 dma_free_coherent(&pdev->dev, bytes,
3196 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3197
3198abort_with_ioremap:
3199 iounmap(mgp->sram);
3200
3201abort_with_wc:
3202#ifdef CONFIG_MTRR
3203 if (mgp->mtrr >= 0)
3204 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3205#endif
b10c0668
BG		 3206 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3207 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 3208
3209abort_with_cmd:
b10c0668
BG		 3210 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3211 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3212
3213abort_with_netdev:
3214
3215 free_netdev(netdev);
3216 return status;
3217}
3218
3219/*
3220 * myri10ge_remove
3221 *
3222 * Does what is necessary to shutdown one Myrinet device. Called
3223 * once for each Myrinet card by the kernel when a module is
3224 * unloaded.
3225 */
3226static void myri10ge_remove(struct pci_dev *pdev)
3227{
3228 struct myri10ge_priv *mgp;
3229 struct net_device *netdev;
3230 size_t bytes;
3231
3232 mgp = pci_get_drvdata(pdev);
3233 if (mgp == NULL)
3234 return;
3235
3236 flush_scheduled_work();
3237 netdev = mgp->dev;
3238 unregister_netdev(netdev);
0da34b6d
BG		 3239
3240 myri10ge_dummy_rdma(mgp, 0);
3241
7adda30c 3242 /* avoid a memory leak */
83f6e152 3243 pci_restore_state(pdev);
7adda30c 3244
0da34b6d 3245 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3246 dma_free_coherent(&pdev->dev, bytes,
3247 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3248
3249 iounmap(mgp->sram);
3250
3251#ifdef CONFIG_MTRR
3252 if (mgp->mtrr >= 0)
3253 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3254#endif
b10c0668
BG		 3255 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3256 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3257
b10c0668
BG		 3258 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3259 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3260
3261 free_netdev(netdev);
3262 pci_set_drvdata(pdev, NULL);
3263}
3264
b10c0668 3265#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3266#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 3267
3268static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3269 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3270 {PCI_DEVICE
3271 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3272 {0},
3273};
3274
3275static struct pci_driver myri10ge_driver = {
3276 .name = "myri10ge",
3277 .probe = myri10ge_probe,
3278 .remove = myri10ge_remove,
3279 .id_table = myri10ge_pci_tbl,
3280#ifdef CONFIG_PM
3281 .suspend = myri10ge_suspend,
3282 .resume = myri10ge_resume,
3283#endif
3284};
3285
3286static __init int myri10ge_init_module(void)
3287{
3288 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3289 MYRI10GE_VERSION_STR);
3290 return pci_register_driver(&myri10ge_driver);
3291}
3292
3293module_init(myri10ge_init_module);
3294
3295static __exit void myri10ge_cleanup_module(void)
3296{
3297 pci_unregister_driver(&myri10ge_driver);
3298}
3299
3300module_exit(myri10ge_cleanup_module);
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