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[B44]: port to native ssb support
[mirror_ubuntu-jammy-kernel.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
0da34b6d
BG		 52#include <linux/ip.h>
53#include <linux/inet.h>
54#include <linux/in.h>
55#include <linux/ethtool.h>
56#include <linux/firmware.h>
57#include <linux/delay.h>
58#include <linux/version.h>
59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
29728637 78#define MYRI10GE_VERSION_STR "1.3.2-1.269"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
0da34b6d 105struct myri10ge_rx_buffer_state {
dd50f336
BG		 106 struct page *page;
107 int page_offset;
0da34b6d
BG		 108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110};
111
112struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117};
118
119struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123};
124
125struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 130 struct page *page;
131 dma_addr_t bus;
132 int page_offset;
0da34b6d 133 int cnt;
dd50f336 134 int fill_cnt;
0da34b6d
BG		 135 int alloc_fail;
136 int mask; /* number of rx slots -1 */
dd50f336 137 int watchdog_needed;
0da34b6d
BG		 138};
139
140struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
144 char *req_bytes;
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int boundary; /* boundary transmits cannot cross */
148 int req ____cacheline_aligned; /* transmit slots submitted */
149 int pkt_start; /* packets started */
150 int done ____cacheline_aligned; /* transmit slots completed */
151 int pkt_done; /* packets completed */
152};
153
154struct myri10ge_rx_done {
155 struct mcp_slot *entry;
156 dma_addr_t bus;
157 int cnt;
158 int idx;
1e6e9342
AG		 159 struct net_lro_mgr lro_mgr;
160 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 161};
162
163struct myri10ge_priv {
164 int running; /* running? */
165 int csum_flag; /* rx_csums? */
166 struct myri10ge_tx_buf tx; /* transmit ring */
167 struct myri10ge_rx_buf rx_small;
168 struct myri10ge_rx_buf rx_big;
169 struct myri10ge_rx_done rx_done;
170 int small_bytes;
dd50f336 171 int big_bytes;
0da34b6d 172 struct net_device *dev;
bea3348e 173 struct napi_struct napi;
0da34b6d
BG		 174 struct net_device_stats stats;
175 u8 __iomem *sram;
176 int sram_size;
177 unsigned long board_span;
178 unsigned long iomem_base;
40f6cff5
AV		 179 __be32 __iomem *irq_claim;
180 __be32 __iomem *irq_deassert;
0da34b6d
BG		 181 char *mac_addr_string;
182 struct mcp_cmd_response *cmd;
183 dma_addr_t cmd_bus;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 struct pci_dev *pdev;
187 int msi_enabled;
40f6cff5 188 __be32 link_state;
0da34b6d
BG		 189 unsigned int rdma_tags_available;
190 int intr_coal_delay;
40f6cff5 191 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 192 int mtrr;
276e26c3 193 int wc_enabled;
0da34b6d
BG		 194 int wake_queue;
195 int stop_queue;
196 int down_cnt;
197 wait_queue_head_t down_wq;
198 struct work_struct watchdog_work;
199 struct timer_list watchdog_timer;
200 int watchdog_tx_done;
c54772e7 201 int watchdog_tx_req;
626fda94 202 int watchdog_pause;
0da34b6d
BG		 203 int watchdog_resets;
204 int tx_linearized;
205 int pause;
206 char *fw_name;
207 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
208 char fw_version[128];
9dc6f0e7
BG		 209 int fw_ver_major;
210 int fw_ver_minor;
211 int fw_ver_tiny;
212 int adopted_rx_filter_bug;
0da34b6d
BG		 213 u8 mac_addr[6]; /* eeprom mac address */
214 unsigned long serial_number;
215 int vendor_specific_offset;
85a7ea1b 216 int fw_multicast_support;
0da34b6d
BG		 217 u32 read_dma;
218 u32 write_dma;
219 u32 read_write_dma;
c58ac5ca
BG		 220 u32 link_changes;
221 u32 msg_enable;
0da34b6d
BG		 222};
223
224static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
225static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
226
227static char *myri10ge_fw_name = NULL;
228module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
229MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
230
231static int myri10ge_ecrc_enable = 1;
232module_param(myri10ge_ecrc_enable, int, S_IRUGO);
233MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
234
235static int myri10ge_max_intr_slots = 1024;
236module_param(myri10ge_max_intr_slots, int, S_IRUGO);
237MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
238
239static int myri10ge_small_bytes = -1; /* -1 == auto */
240module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
241MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
242
243static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 244module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
0da34b6d
BG		 245MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
246
f761fae1 247static int myri10ge_intr_coal_delay = 75;
0da34b6d
BG		 248module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
249MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
250
251static int myri10ge_flow_control = 1;
252module_param(myri10ge_flow_control, int, S_IRUGO);
253MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
254
255static int myri10ge_deassert_wait = 1;
256module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
257MODULE_PARM_DESC(myri10ge_deassert_wait,
258 "Wait when deasserting legacy interrupts\n");
259
260static int myri10ge_force_firmware = 0;
261module_param(myri10ge_force_firmware, int, S_IRUGO);
262MODULE_PARM_DESC(myri10ge_force_firmware,
263 "Force firmware to assume aligned completions\n");
264
0da34b6d
BG		 265static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
266module_param(myri10ge_initial_mtu, int, S_IRUGO);
267MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
268
269static int myri10ge_napi_weight = 64;
270module_param(myri10ge_napi_weight, int, S_IRUGO);
271MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
272
273static int myri10ge_watchdog_timeout = 1;
274module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
275MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
276
277static int myri10ge_max_irq_loops = 1048576;
278module_param(myri10ge_max_irq_loops, int, S_IRUGO);
279MODULE_PARM_DESC(myri10ge_max_irq_loops,
280 "Set stuck legacy IRQ detection threshold\n");
281
c58ac5ca
BG		 282#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
283
284static int myri10ge_debug = -1; /* defaults above */
285module_param(myri10ge_debug, int, 0);
286MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
287
1e6e9342
AG		 288static int myri10ge_lro = 1;
289module_param(myri10ge_lro, int, S_IRUGO);
290MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload\n");
291
292static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
293module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
294MODULE_PARM_DESC(myri10ge_lro, "Number of LRO packets to be aggregated\n");
295
dd50f336
BG		 296static int myri10ge_fill_thresh = 256;
297module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
298MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
299
f181137f
BG		 300static int myri10ge_reset_recover = 1;
301
f761fae1 302static int myri10ge_wcfifo = 0;
6ebc087a
BG		 303module_param(myri10ge_wcfifo, int, S_IRUGO);
304MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
305
0da34b6d
BG		 306#define MYRI10GE_FW_OFFSET 1024*1024
307#define MYRI10GE_HIGHPART_TO_U32(X) \
308(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
309#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
310
311#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
312
2f76216f
BG		 313static void myri10ge_set_multicast_list(struct net_device *dev);
314
6250223e 315static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 316{
6250223e 317 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 318}
319
0da34b6d
BG		 320static int
321myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
322 struct myri10ge_cmd *data, int atomic)
323{
324 struct mcp_cmd *buf;
325 char buf_bytes[sizeof(*buf) + 8];
326 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 327 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 328 u32 dma_low, dma_high, result, value;
329 int sleep_total = 0;
330
331 /* ensure buf is aligned to 8 bytes */
332 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
333
334 buf->data0 = htonl(data->data0);
335 buf->data1 = htonl(data->data1);
336 buf->data2 = htonl(data->data2);
337 buf->cmd = htonl(cmd);
338 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
339 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
340
341 buf->response_addr.low = htonl(dma_low);
342 buf->response_addr.high = htonl(dma_high);
40f6cff5 343 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 344 mb();
345 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
346
347 /* wait up to 15ms. Longest command is the DMA benchmark,
348 * which is capped at 5ms, but runs from a timeout handler
349 * that runs every 7.8ms. So a 15ms timeout leaves us with
350 * a 2.2ms margin
351 */
352 if (atomic) {
353 /* if atomic is set, do not sleep,
354 * and try to get the completion quickly
355 * (1ms will be enough for those commands) */
356 for (sleep_total = 0;
357 sleep_total < 1000
40f6cff5 358 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 359 sleep_total += 10)
360 udelay(10);
361 } else {
362 /* use msleep for most command */
363 for (sleep_total = 0;
364 sleep_total < 15
40f6cff5 365 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 366 sleep_total++)
367 msleep(1);
368 }
369
370 result = ntohl(response->result);
371 value = ntohl(response->data);
372 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
373 if (result == 0) {
374 data->data0 = value;
375 return 0;
85a7ea1b
BG		 376 } else if (result == MXGEFW_CMD_UNKNOWN) {
377 return -ENOSYS;
5443e9ea
BG		 378 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
379 return -E2BIG;
0da34b6d
BG		 380 } else {
381 dev_err(&mgp->pdev->dev,
382 "command %d failed, result = %d\n",
383 cmd, result);
384 return -ENXIO;
385 }
386 }
387
388 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
389 cmd, result);
390 return -EAGAIN;
391}
392
393/*
394 * The eeprom strings on the lanaiX have the format
395 * SN=x\0
396 * MAC=x:x:x:x:x:x\0
397 * PT:ddd mmm xx xx:xx:xx xx\0
398 * PV:ddd mmm xx xx:xx:xx xx\0
399 */
400static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
401{
402 char *ptr, *limit;
403 int i;
404
405 ptr = mgp->eeprom_strings;
406 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
407
408 while (*ptr != '\0' && ptr < limit) {
409 if (memcmp(ptr, "MAC=", 4) == 0) {
410 ptr += 4;
411 mgp->mac_addr_string = ptr;
412 for (i = 0; i < 6; i++) {
413 if ((ptr + 2) > limit)
414 goto abort;
415 mgp->mac_addr[i] =
416 simple_strtoul(ptr, &ptr, 16);
417 ptr += 1;
418 }
419 }
420 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
421 ptr += 3;
422 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
423 }
424 while (ptr < limit && *ptr++) ;
425 }
426
427 return 0;
428
429abort:
430 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
431 return -ENXIO;
432}
433
434/*
435 * Enable or disable periodic RDMAs from the host to make certain
436 * chipsets resend dropped PCIe messages
437 */
438
439static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
440{
441 char __iomem *submit;
40f6cff5 442 __be32 buf[16];
0da34b6d
BG		 443 u32 dma_low, dma_high;
444 int i;
445
446 /* clear confirmation addr */
447 mgp->cmd->data = 0;
448 mb();
449
450 /* send a rdma command to the PCIe engine, and wait for the
451 * response in the confirmation address. The firmware should
452 * write a -1 there to indicate it is alive and well
453 */
454 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
455 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
456
457 buf[0] = htonl(dma_high); /* confirm addr MSW */
458 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 459 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 460 buf[3] = htonl(dma_high); /* dummy addr MSW */
461 buf[4] = htonl(dma_low); /* dummy addr LSW */
462 buf[5] = htonl(enable); /* enable? */
463
e700f9f4 464 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 465
466 myri10ge_pio_copy(submit, &buf, sizeof(buf));
467 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
468 msleep(1);
469 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
470 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
471 (enable ? "enable" : "disable"));
472}
473
474static int
475myri10ge_validate_firmware(struct myri10ge_priv *mgp,
476 struct mcp_gen_header *hdr)
477{
478 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 479
480 /* check firmware type */
481 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
482 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
483 return -EINVAL;
484 }
485
486 /* save firmware version for ethtool */
487 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
488
9dc6f0e7
BG		 489 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
490 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 491
9dc6f0e7
BG		 492 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
493 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 494 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
495 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
496 MXGEFW_VERSION_MINOR);
497 return -EINVAL;
498 }
499 return 0;
500}
501
502static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
503{
504 unsigned crc, reread_crc;
505 const struct firmware *fw;
506 struct device *dev = &mgp->pdev->dev;
507 struct mcp_gen_header *hdr;
508 size_t hdr_offset;
509 int status;
e454358a 510 unsigned i;
0da34b6d
BG		 511
512 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
513 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
514 mgp->fw_name);
515 status = -EINVAL;
516 goto abort_with_nothing;
517 }
518
519 /* check size */
520
521 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
522 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
523 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
524 status = -EINVAL;
525 goto abort_with_fw;
526 }
527
528 /* check id */
40f6cff5 529 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 530 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
531 dev_err(dev, "Bad firmware file\n");
532 status = -EINVAL;
533 goto abort_with_fw;
534 }
535 hdr = (void *)(fw->data + hdr_offset);
536
537 status = myri10ge_validate_firmware(mgp, hdr);
538 if (status != 0)
539 goto abort_with_fw;
540
541 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 542 for (i = 0; i < fw->size; i += 256) {
543 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
544 fw->data + i,
545 min(256U, (unsigned)(fw->size - i)));
546 mb();
547 readb(mgp->sram);
b10c0668 548 }
0da34b6d
BG		 549 /* corruption checking is good for parity recovery and buggy chipset */
550 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
551 reread_crc = crc32(~0, fw->data, fw->size);
552 if (crc != reread_crc) {
553 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
554 (unsigned)fw->size, reread_crc, crc);
555 status = -EIO;
556 goto abort_with_fw;
557 }
558 *size = (u32) fw->size;
559
560abort_with_fw:
561 release_firmware(fw);
562
563abort_with_nothing:
564 return status;
565}
566
567static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
568{
569 struct mcp_gen_header *hdr;
570 struct device *dev = &mgp->pdev->dev;
571 const size_t bytes = sizeof(struct mcp_gen_header);
572 size_t hdr_offset;
573 int status;
574
575 /* find running firmware header */
576 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
577
578 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
579 dev_err(dev, "Running firmware has bad header offset (%d)\n",
580 (int)hdr_offset);
581 return -EIO;
582 }
583
584 /* copy header of running firmware from SRAM to host memory to
585 * validate firmware */
586 hdr = kmalloc(bytes, GFP_KERNEL);
587 if (hdr == NULL) {
588 dev_err(dev, "could not malloc firmware hdr\n");
589 return -ENOMEM;
590 }
591 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
592 status = myri10ge_validate_firmware(mgp, hdr);
593 kfree(hdr);
9dc6f0e7
BG		 594
595 /* check to see if adopted firmware has bug where adopting
596 * it will cause broadcasts to be filtered unless the NIC
597 * is kept in ALLMULTI mode */
598 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
599 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
600 mgp->adopted_rx_filter_bug = 1;
601 dev_warn(dev, "Adopting fw %d.%d.%d: "
602 "working around rx filter bug\n",
603 mgp->fw_ver_major, mgp->fw_ver_minor,
604 mgp->fw_ver_tiny);
605 }
0da34b6d
BG		 606 return status;
607}
608
609static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
610{
611 char __iomem *submit;
40f6cff5 612 __be32 buf[16];
0da34b6d
BG		 613 u32 dma_low, dma_high, size;
614 int status, i;
615
b10c0668 616 size = 0;
0da34b6d
BG		 617 status = myri10ge_load_hotplug_firmware(mgp, &size);
618 if (status) {
619 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
620
621 /* Do not attempt to adopt firmware if there
622 * was a bad crc */
623 if (status == -EIO)
624 return status;
625
626 status = myri10ge_adopt_running_firmware(mgp);
627 if (status != 0) {
628 dev_err(&mgp->pdev->dev,
629 "failed to adopt running firmware\n");
630 return status;
631 }
632 dev_info(&mgp->pdev->dev,
633 "Successfully adopted running firmware\n");
634 if (mgp->tx.boundary == 4096) {
635 dev_warn(&mgp->pdev->dev,
636 "Using firmware currently running on NIC"
637 ". For optimal\n");
638 dev_warn(&mgp->pdev->dev,
639 "performance consider loading optimized "
640 "firmware\n");
641 dev_warn(&mgp->pdev->dev, "via hotplug\n");
642 }
643
644 mgp->fw_name = "adopted";
645 mgp->tx.boundary = 2048;
646 return status;
647 }
648
649 /* clear confirmation addr */
650 mgp->cmd->data = 0;
651 mb();
652
653 /* send a reload command to the bootstrap MCP, and wait for the
654 * response in the confirmation address. The firmware should
655 * write a -1 there to indicate it is alive and well
656 */
657 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
658 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
659
660 buf[0] = htonl(dma_high); /* confirm addr MSW */
661 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 662 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 663
664 /* FIX: All newest firmware should un-protect the bottom of
665 * the sram before handoff. However, the very first interfaces
666 * do not. Therefore the handoff copy must skip the first 8 bytes
667 */
668 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
669 buf[4] = htonl(size - 8); /* length of code */
670 buf[5] = htonl(8); /* where to copy to */
671 buf[6] = htonl(0); /* where to jump to */
672
e700f9f4 673 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 674
675 myri10ge_pio_copy(submit, &buf, sizeof(buf));
676 mb();
677 msleep(1);
678 mb();
679 i = 0;
680 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
681 msleep(1);
682 i++;
683 }
684 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
685 dev_err(&mgp->pdev->dev, "handoff failed\n");
686 return -ENXIO;
687 }
688 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 689 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 690
691 return 0;
692}
693
694static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
695{
696 struct myri10ge_cmd cmd;
697 int status;
698
699 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
700 | (addr[2] << 8) | addr[3]);
701
702 cmd.data1 = ((addr[4] << 8) | (addr[5]));
703
704 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
705 return status;
706}
707
708static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
709{
710 struct myri10ge_cmd cmd;
711 int status, ctl;
712
713 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
714 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
715
716 if (status) {
717 printk(KERN_ERR
718 "myri10ge: %s: Failed to set flow control mode\n",
719 mgp->dev->name);
720 return status;
721 }
722 mgp->pause = pause;
723 return 0;
724}
725
726static void
727myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
728{
729 struct myri10ge_cmd cmd;
730 int status, ctl;
731
732 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
733 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
734 if (status)
735 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
736 mgp->dev->name);
737}
738
0d6ac257 739static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 740{
741 struct myri10ge_cmd cmd;
742 int status;
0da34b6d 743 u32 len;
34fdccea
BG		 744 struct page *dmatest_page;
745 dma_addr_t dmatest_bus;
0d6ac257
BG		 746 char *test = " ";
747
748 dmatest_page = alloc_page(GFP_KERNEL);
749 if (!dmatest_page)
750 return -ENOMEM;
751 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
752 DMA_BIDIRECTIONAL);
753
754 /* Run a small DMA test.
755 * The magic multipliers to the length tell the firmware
756 * to do DMA read, write, or read+write tests. The
757 * results are returned in cmd.data0. The upper 16
758 * bits or the return is the number of transfers completed.
759 * The lower 16 bits is the time in 0.5us ticks that the
760 * transfers took to complete.
761 */
762
763 len = mgp->tx.boundary;
764
765 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
766 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
767 cmd.data2 = len * 0x10000;
768 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
769 if (status != 0) {
770 test = "read";
771 goto abort;
772 }
773 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
774 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
775 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
776 cmd.data2 = len * 0x1;
777 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
778 if (status != 0) {
779 test = "write";
780 goto abort;
781 }
782 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
783
784 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
785 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
786 cmd.data2 = len * 0x10001;
787 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
788 if (status != 0) {
789 test = "read/write";
790 goto abort;
791 }
792 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
793 (cmd.data0 & 0xffff);
794
795abort:
796 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
797 put_page(dmatest_page);
798
799 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
800 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
801 test, status);
802
803 return status;
804}
805
806static int myri10ge_reset(struct myri10ge_priv *mgp)
807{
808 struct myri10ge_cmd cmd;
809 int status;
810 size_t bytes;
0da34b6d
BG		 811
812 /* try to send a reset command to the card to see if it
813 * is alive */
814 memset(&cmd, 0, sizeof(cmd));
815 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
816 if (status != 0) {
817 dev_err(&mgp->pdev->dev, "failed reset\n");
818 return -ENXIO;
819 }
0d6ac257
BG		 820
821 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0da34b6d
BG		 822
823 /* Now exchange information about interrupts */
824
825 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
826 memset(mgp->rx_done.entry, 0, bytes);
827 cmd.data0 = (u32) bytes;
828 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
829 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
830 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
831 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
832
833 status |=
834 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 835 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 836 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
837 &cmd, 0);
838 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 839
0da34b6d
BG		 840 status |= myri10ge_send_cmd
841 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 842 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 843 if (status != 0) {
844 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
845 return status;
846 }
40f6cff5 847 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 848
0da34b6d
BG		 849 memset(mgp->rx_done.entry, 0, bytes);
850
851 /* reset mcp/driver shared state back to 0 */
852 mgp->tx.req = 0;
853 mgp->tx.done = 0;
854 mgp->tx.pkt_start = 0;
855 mgp->tx.pkt_done = 0;
856 mgp->rx_big.cnt = 0;
857 mgp->rx_small.cnt = 0;
858 mgp->rx_done.idx = 0;
859 mgp->rx_done.cnt = 0;
c58ac5ca 860 mgp->link_changes = 0;
0da34b6d 861 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 862 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 863 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 864 return status;
865}
866
867static inline void
868myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
869 struct mcp_kreq_ether_recv *src)
870{
40f6cff5 871 __be32 low;
0da34b6d
BG		 872
873 low = src->addr_low;
40f6cff5 874 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 875 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
876 mb();
877 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 878 mb();
879 src->addr_low = low;
40f6cff5 880 put_be32(low, &dst->addr_low);
0da34b6d
BG		 881 mb();
882}
883
40f6cff5 884static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 885{
886 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
887
40f6cff5 888 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 889 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
890 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
891 skb->csum = hw_csum;
84fa7933 892 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 893 }
894}
895
dd50f336
BG		 896static inline void
897myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
898 struct skb_frag_struct *rx_frags, int len, int hlen)
899{
900 struct skb_frag_struct *skb_frags;
901
902 skb->len = skb->data_len = len;
903 skb->truesize = len + sizeof(struct sk_buff);
904 /* attach the page(s) */
905
906 skb_frags = skb_shinfo(skb)->frags;
907 while (len > 0) {
908 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
909 len -= rx_frags->size;
910 skb_frags++;
911 rx_frags++;
912 skb_shinfo(skb)->nr_frags++;
913 }
914
915 /* pskb_may_pull is not available in irq context, but
916 * skb_pull() (for ether_pad and eth_type_trans()) requires
917 * the beginning of the packet in skb_headlen(), move it
918 * manually */
27d7ff46 919 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 920 skb_shinfo(skb)->frags[0].page_offset += hlen;
921 skb_shinfo(skb)->frags[0].size -= hlen;
922 skb->data_len -= hlen;
923 skb->tail += hlen;
924 skb_pull(skb, MXGEFW_PAD);
925}
926
927static void
928myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
929 int bytes, int watchdog)
930{
931 struct page *page;
932 int idx;
933
934 if (unlikely(rx->watchdog_needed && !watchdog))
935 return;
936
937 /* try to refill entire ring */
938 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
939 idx = rx->fill_cnt & rx->mask;
ae8509b1 940 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 941 /* we can use part of previous page */
942 get_page(rx->page);
943 } else {
944 /* we need a new page */
945 page =
946 alloc_pages(GFP_ATOMIC | __GFP_COMP,
947 MYRI10GE_ALLOC_ORDER);
948 if (unlikely(page == NULL)) {
949 if (rx->fill_cnt - rx->cnt < 16)
950 rx->watchdog_needed = 1;
951 return;
952 }
953 rx->page = page;
954 rx->page_offset = 0;
955 rx->bus = pci_map_page(mgp->pdev, page, 0,
956 MYRI10GE_ALLOC_SIZE,
957 PCI_DMA_FROMDEVICE);
958 }
959 rx->info[idx].page = rx->page;
960 rx->info[idx].page_offset = rx->page_offset;
961 /* note that this is the address of the start of the
962 * page */
963 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
964 rx->shadow[idx].addr_low =
965 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
966 rx->shadow[idx].addr_high =
967 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
968
969 /* start next packet on a cacheline boundary */
970 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 971
972#if MYRI10GE_ALLOC_SIZE > 4096
973 /* don't cross a 4KB boundary */
974 if ((rx->page_offset >> 12) !=
975 ((rx->page_offset + bytes - 1) >> 12))
976 rx->page_offset = (rx->page_offset + 4096) & ~4095;
977#endif
dd50f336
BG		 978 rx->fill_cnt++;
979
980 /* copy 8 descriptors to the firmware at a time */
981 if ((idx & 7) == 7) {
982 if (rx->wc_fifo == NULL)
983 myri10ge_submit_8rx(&rx->lanai[idx - 7],
984 &rx->shadow[idx - 7]);
985 else {
986 mb();
987 myri10ge_pio_copy(rx->wc_fifo,
988 &rx->shadow[idx - 7], 64);
989 }
990 }
991 }
992}
993
994static inline void
995myri10ge_unmap_rx_page(struct pci_dev *pdev,
996 struct myri10ge_rx_buffer_state *info, int bytes)
997{
998 /* unmap the recvd page if we're the only or last user of it */
999 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1000 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1001 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1002 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1003 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1004 }
1005}
1006
1007#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1008 * page into an skb */
1009
1010static inline int
52ea6fb3
BG		 1011myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1012 int bytes, int len, __wsum csum)
dd50f336
BG		 1013{
1014 struct sk_buff *skb;
1015 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1016 int i, idx, hlen, remainder;
1017 struct pci_dev *pdev = mgp->pdev;
1018 struct net_device *dev = mgp->dev;
1019 u8 *va;
1020
1021 len += MXGEFW_PAD;
1022 idx = rx->cnt & rx->mask;
1023 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1024 prefetch(va);
1025 /* Fill skb_frag_struct(s) with data from our receive */
1026 for (i = 0, remainder = len; remainder > 0; i++) {
1027 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1028 rx_frags[i].page = rx->info[idx].page;
1029 rx_frags[i].page_offset = rx->info[idx].page_offset;
1030 if (remainder < MYRI10GE_ALLOC_SIZE)
1031 rx_frags[i].size = remainder;
1032 else
1033 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1034 rx->cnt++;
1035 idx = rx->cnt & rx->mask;
1036 remainder -= MYRI10GE_ALLOC_SIZE;
1037 }
1038
1e6e9342
AG		 1039 if (mgp->csum_flag && myri10ge_lro) {
1040 rx_frags[0].page_offset += MXGEFW_PAD;
1041 rx_frags[0].size -= MXGEFW_PAD;
1042 len -= MXGEFW_PAD;
1043 lro_receive_frags(&mgp->rx_done.lro_mgr, rx_frags,
1044 len, len, (void *)(unsigned long)csum, csum);
1045 return 1;
1046 }
1047
dd50f336
BG		 1048 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1049
1050 /* allocate an skb to attach the page(s) to. */
1051
1052 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1053 if (unlikely(skb == NULL)) {
1054 mgp->stats.rx_dropped++;
1055 do {
1056 i--;
1057 put_page(rx_frags[i].page);
1058 } while (i != 0);
1059 return 0;
1060 }
1061
1062 /* Attach the pages to the skb, and trim off any padding */
1063 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1064 if (skb_shinfo(skb)->frags[0].size <= 0) {
1065 put_page(skb_shinfo(skb)->frags[0].page);
1066 skb_shinfo(skb)->nr_frags = 0;
1067 }
1068 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1069
1070 if (mgp->csum_flag) {
1071 if ((skb->protocol == htons(ETH_P_IP)) ||
1072 (skb->protocol == htons(ETH_P_IPV6))) {
1073 skb->csum = csum;
1074 skb->ip_summed = CHECKSUM_COMPLETE;
1075 } else
1076 myri10ge_vlan_ip_csum(skb, csum);
1077 }
1078 netif_receive_skb(skb);
1079 dev->last_rx = jiffies;
1080 return 1;
1081}
1082
0da34b6d
BG		 1083static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1084{
1085 struct pci_dev *pdev = mgp->pdev;
1086 struct myri10ge_tx_buf *tx = &mgp->tx;
1087 struct sk_buff *skb;
1088 int idx, len;
0da34b6d
BG		 1089
1090 while (tx->pkt_done != mcp_index) {
1091 idx = tx->done & tx->mask;
1092 skb = tx->info[idx].skb;
1093
1094 /* Mark as free */
1095 tx->info[idx].skb = NULL;
1096 if (tx->info[idx].last) {
1097 tx->pkt_done++;
1098 tx->info[idx].last = 0;
1099 }
1100 tx->done++;
1101 len = pci_unmap_len(&tx->info[idx], len);
1102 pci_unmap_len_set(&tx->info[idx], len, 0);
1103 if (skb) {
1104 mgp->stats.tx_bytes += skb->len;
1105 mgp->stats.tx_packets++;
1106 dev_kfree_skb_irq(skb);
1107 if (len)
1108 pci_unmap_single(pdev,
1109 pci_unmap_addr(&tx->info[idx],
1110 bus), len,
1111 PCI_DMA_TODEVICE);
1112 } else {
1113 if (len)
1114 pci_unmap_page(pdev,
1115 pci_unmap_addr(&tx->info[idx],
1116 bus), len,
1117 PCI_DMA_TODEVICE);
1118 }
0da34b6d
BG		 1119 }
1120 /* start the queue if we've stopped it */
1121 if (netif_queue_stopped(mgp->dev)
1122 && tx->req - tx->done < (tx->mask >> 1)) {
1123 mgp->wake_queue++;
1124 netif_wake_queue(mgp->dev);
1125 }
1126}
1127
bea3348e 1128static inline int myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int budget)
0da34b6d
BG		 1129{
1130 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1131 unsigned long rx_bytes = 0;
1132 unsigned long rx_packets = 0;
1133 unsigned long rx_ok;
1134
1135 int idx = rx_done->idx;
1136 int cnt = rx_done->cnt;
bea3348e 1137 int work_done = 0;
0da34b6d 1138 u16 length;
40f6cff5 1139 __wsum checksum;
0da34b6d 1140
bea3348e 1141 while (rx_done->entry[idx].length != 0 && work_done++ < budget) {
0da34b6d
BG		 1142 length = ntohs(rx_done->entry[idx].length);
1143 rx_done->entry[idx].length = 0;
40f6cff5 1144 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1145 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1146 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1147 mgp->small_bytes,
1148 length, checksum);
0da34b6d 1149 else
52ea6fb3
BG		 1150 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1151 mgp->big_bytes,
1152 length, checksum);
0da34b6d
BG		 1153 rx_packets += rx_ok;
1154 rx_bytes += rx_ok * (unsigned long)length;
1155 cnt++;
1156 idx = cnt & (myri10ge_max_intr_slots - 1);
0da34b6d
BG		 1157 }
1158 rx_done->idx = idx;
1159 rx_done->cnt = cnt;
1160 mgp->stats.rx_packets += rx_packets;
1161 mgp->stats.rx_bytes += rx_bytes;
c7dab99b 1162
1e6e9342
AG		 1163 if (myri10ge_lro)
1164 lro_flush_all(&rx_done->lro_mgr);
1165
c7dab99b
BG		 1166 /* restock receive rings if needed */
1167 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1168 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1169 mgp->small_bytes + MXGEFW_PAD, 0);
1170 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1171 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1172
bea3348e 1173 return work_done;
0da34b6d
BG		 1174}
1175
1176static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1177{
1178 struct mcp_irq_data *stats = mgp->fw_stats;
1179
1180 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1181 unsigned link_up = ntohl(stats->link_up);
1182 if (mgp->link_state != link_up) {
1183 mgp->link_state = link_up;
1184
1185 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1186 if (netif_msg_link(mgp))
1187 printk(KERN_INFO
1188 "myri10ge: %s: link up\n",
1189 mgp->dev->name);
0da34b6d 1190 netif_carrier_on(mgp->dev);
c58ac5ca 1191 mgp->link_changes++;
0da34b6d 1192 } else {
c58ac5ca
BG		 1193 if (netif_msg_link(mgp))
1194 printk(KERN_INFO
798a95db
BG		 1195 "myri10ge: %s: link %s\n",
1196 mgp->dev->name,
1197 (link_up == MXGEFW_LINK_MYRINET ?
1198 "mismatch (Myrinet detected)" :
1199 "down"));
0da34b6d 1200 netif_carrier_off(mgp->dev);
c58ac5ca 1201 mgp->link_changes++;
0da34b6d
BG		 1202 }
1203 }
1204 if (mgp->rdma_tags_available !=
1205 ntohl(mgp->fw_stats->rdma_tags_available)) {
1206 mgp->rdma_tags_available =
1207 ntohl(mgp->fw_stats->rdma_tags_available);
1208 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1209 "%d tags left\n", mgp->dev->name,
1210 mgp->rdma_tags_available);
1211 }
1212 mgp->down_cnt += stats->link_down;
1213 if (stats->link_down)
1214 wake_up(&mgp->down_wq);
1215 }
1216}
1217
bea3348e 1218static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1219{
bea3348e
SH		 1220 struct myri10ge_priv *mgp = container_of(napi, struct myri10ge_priv, napi);
1221 struct net_device *netdev = mgp->dev;
0da34b6d 1222 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
bea3348e 1223 int work_done;
0da34b6d
BG		 1224
1225 /* process as many rx events as NAPI will allow */
bea3348e 1226 work_done = myri10ge_clean_rx_done(mgp, budget);
0da34b6d
BG		 1227
1228 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
bea3348e 1229 netif_rx_complete(netdev, napi);
40f6cff5 1230 put_be32(htonl(3), mgp->irq_claim);
0da34b6d 1231 }
bea3348e 1232 return work_done;
0da34b6d
BG		 1233}
1234
7d12e780 1235static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1236{
1237 struct myri10ge_priv *mgp = arg;
1238 struct mcp_irq_data *stats = mgp->fw_stats;
1239 struct myri10ge_tx_buf *tx = &mgp->tx;
1240 u32 send_done_count;
1241 int i;
1242
1243 /* make sure it is our IRQ, and that the DMA has finished */
1244 if (unlikely(!stats->valid))
1245 return (IRQ_NONE);
1246
1247 /* low bit indicates receives are present, so schedule
1248 * napi poll handler */
1249 if (stats->valid & 1)
bea3348e 1250 netif_rx_schedule(mgp->dev, &mgp->napi);
0da34b6d
BG		 1251
1252 if (!mgp->msi_enabled) {
40f6cff5 1253 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1254 if (!myri10ge_deassert_wait)
1255 stats->valid = 0;
1256 mb();
1257 } else
1258 stats->valid = 0;
1259
1260 /* Wait for IRQ line to go low, if using INTx */
1261 i = 0;
1262 while (1) {
1263 i++;
1264 /* check for transmit completes and receives */
1265 send_done_count = ntohl(stats->send_done_count);
1266 if (send_done_count != tx->pkt_done)
1267 myri10ge_tx_done(mgp, (int)send_done_count);
1268 if (unlikely(i > myri10ge_max_irq_loops)) {
1269 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1270 mgp->dev->name);
1271 stats->valid = 0;
1272 schedule_work(&mgp->watchdog_work);
1273 }
1274 if (likely(stats->valid == 0))
1275 break;
1276 cpu_relax();
1277 barrier();
1278 }
1279
1280 myri10ge_check_statblock(mgp);
1281
40f6cff5 1282 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1283 return (IRQ_HANDLED);
1284}
1285
1286static int
1287myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1288{
1289 cmd->autoneg = AUTONEG_DISABLE;
1290 cmd->speed = SPEED_10000;
1291 cmd->duplex = DUPLEX_FULL;
1292 return 0;
1293}
1294
1295static void
1296myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1297{
1298 struct myri10ge_priv *mgp = netdev_priv(netdev);
1299
1300 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1301 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1302 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1303 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1304}
1305
1306static int
1307myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1308{
1309 struct myri10ge_priv *mgp = netdev_priv(netdev);
1310 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1311 return 0;
1312}
1313
1314static int
1315myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1316{
1317 struct myri10ge_priv *mgp = netdev_priv(netdev);
1318
1319 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1320 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1321 return 0;
1322}
1323
1324static void
1325myri10ge_get_pauseparam(struct net_device *netdev,
1326 struct ethtool_pauseparam *pause)
1327{
1328 struct myri10ge_priv *mgp = netdev_priv(netdev);
1329
1330 pause->autoneg = 0;
1331 pause->rx_pause = mgp->pause;
1332 pause->tx_pause = mgp->pause;
1333}
1334
1335static int
1336myri10ge_set_pauseparam(struct net_device *netdev,
1337 struct ethtool_pauseparam *pause)
1338{
1339 struct myri10ge_priv *mgp = netdev_priv(netdev);
1340
1341 if (pause->tx_pause != mgp->pause)
1342 return myri10ge_change_pause(mgp, pause->tx_pause);
1343 if (pause->rx_pause != mgp->pause)
1344 return myri10ge_change_pause(mgp, pause->tx_pause);
1345 if (pause->autoneg != 0)
1346 return -EINVAL;
1347 return 0;
1348}
1349
1350static void
1351myri10ge_get_ringparam(struct net_device *netdev,
1352 struct ethtool_ringparam *ring)
1353{
1354 struct myri10ge_priv *mgp = netdev_priv(netdev);
1355
1356 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1357 ring->rx_max_pending = mgp->rx_big.mask + 1;
1358 ring->rx_jumbo_max_pending = 0;
1359 ring->tx_max_pending = mgp->rx_small.mask + 1;
1360 ring->rx_mini_pending = ring->rx_mini_max_pending;
1361 ring->rx_pending = ring->rx_max_pending;
1362 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1363 ring->tx_pending = ring->tx_max_pending;
1364}
1365
1366static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1367{
1368 struct myri10ge_priv *mgp = netdev_priv(netdev);
1369 if (mgp->csum_flag)
1370 return 1;
1371 else
1372 return 0;
1373}
1374
1375static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1376{
1377 struct myri10ge_priv *mgp = netdev_priv(netdev);
1378 if (csum_enabled)
1379 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1380 else
1381 mgp->csum_flag = 0;
1382 return 0;
1383}
1384
1385static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1386 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1387 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1388 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1389 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1390 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1391 "tx_heartbeat_errors", "tx_window_errors",
1392 /* device-specific stats */
2c1a1088 1393 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1394 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1395 "serial_number", "tx_pkt_start", "tx_pkt_done",
1396 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1397 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1398 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1399 "dropped_link_error_or_filtered",
1400 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1401 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1402 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1e6e9342
AG		 1403 "dropped_no_big_buffer", "LRO aggregated", "LRO flushed",
1404 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1405};
1406
1407#define MYRI10GE_NET_STATS_LEN 21
1408#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1409
1410static void
1411myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1412{
1413 switch (stringset) {
1414 case ETH_SS_STATS:
1415 memcpy(data, *myri10ge_gstrings_stats,
1416 sizeof(myri10ge_gstrings_stats));
1417 break;
1418 }
1419}
1420
1421static int myri10ge_get_stats_count(struct net_device *netdev)
1422{
1423 return MYRI10GE_STATS_LEN;
1424}
1425
1426static void
1427myri10ge_get_ethtool_stats(struct net_device *netdev,
1428 struct ethtool_stats *stats, u64 * data)
1429{
1430 struct myri10ge_priv *mgp = netdev_priv(netdev);
1431 int i;
1432
1433 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1434 data[i] = ((unsigned long *)&mgp->stats)[i];
1435
2c1a1088 1436 data[i++] = (unsigned int)mgp->tx.boundary;
276e26c3 1437 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1438 data[i++] = (unsigned int)mgp->pdev->irq;
1439 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1440 data[i++] = (unsigned int)mgp->read_dma;
1441 data[i++] = (unsigned int)mgp->write_dma;
1442 data[i++] = (unsigned int)mgp->read_write_dma;
1443 data[i++] = (unsigned int)mgp->serial_number;
1444 data[i++] = (unsigned int)mgp->tx.pkt_start;
1445 data[i++] = (unsigned int)mgp->tx.pkt_done;
1446 data[i++] = (unsigned int)mgp->tx.req;
1447 data[i++] = (unsigned int)mgp->tx.done;
1448 data[i++] = (unsigned int)mgp->rx_small.cnt;
1449 data[i++] = (unsigned int)mgp->rx_big.cnt;
1450 data[i++] = (unsigned int)mgp->wake_queue;
1451 data[i++] = (unsigned int)mgp->stop_queue;
1452 data[i++] = (unsigned int)mgp->watchdog_resets;
1453 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1454 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1455 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1456 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1457 data[i++] =
1458 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
cee505db
BG		 1459 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1460 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1461 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1462 data[i++] =
1463 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
85a7ea1b
BG		 1464 data[i++] =
1465 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1466 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1467 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1468 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1469 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1e6e9342
AG		 1470 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated;
1471 data[i++] = mgp->rx_done.lro_mgr.stats.flushed;
1472 if (mgp->rx_done.lro_mgr.stats.flushed)
1473 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated /
1474 mgp->rx_done.lro_mgr.stats.flushed;
1475 else
1476 data[i++] = 0;
1477 data[i++] = mgp->rx_done.lro_mgr.stats.no_desc;
0da34b6d
BG		 1478}
1479
c58ac5ca
BG		 1480static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1481{
1482 struct myri10ge_priv *mgp = netdev_priv(netdev);
1483 mgp->msg_enable = value;
1484}
1485
1486static u32 myri10ge_get_msglevel(struct net_device *netdev)
1487{
1488 struct myri10ge_priv *mgp = netdev_priv(netdev);
1489 return mgp->msg_enable;
1490}
1491
7282d491 1492static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1493 .get_settings = myri10ge_get_settings,
1494 .get_drvinfo = myri10ge_get_drvinfo,
1495 .get_coalesce = myri10ge_get_coalesce,
1496 .set_coalesce = myri10ge_set_coalesce,
1497 .get_pauseparam = myri10ge_get_pauseparam,
1498 .set_pauseparam = myri10ge_set_pauseparam,
1499 .get_ringparam = myri10ge_get_ringparam,
1500 .get_rx_csum = myri10ge_get_rx_csum,
1501 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1502 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1503 .set_sg = ethtool_op_set_sg,
0da34b6d 1504 .set_tso = ethtool_op_set_tso,
6ffdd071 1505 .get_link = ethtool_op_get_link,
0da34b6d
BG		 1506 .get_strings = myri10ge_get_strings,
1507 .get_stats_count = myri10ge_get_stats_count,
c58ac5ca
BG		 1508 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1509 .set_msglevel = myri10ge_set_msglevel,
1510 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1511};
1512
1513static int myri10ge_allocate_rings(struct net_device *dev)
1514{
1515 struct myri10ge_priv *mgp;
1516 struct myri10ge_cmd cmd;
1517 int tx_ring_size, rx_ring_size;
1518 int tx_ring_entries, rx_ring_entries;
1519 int i, status;
1520 size_t bytes;
1521
1522 mgp = netdev_priv(dev);
1523
1524 /* get ring sizes */
1525
1526 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1527 tx_ring_size = cmd.data0;
1528 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1529 if (status != 0)
1530 return status;
0da34b6d
BG		 1531 rx_ring_size = cmd.data0;
1532
1533 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1534 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1535 mgp->tx.mask = tx_ring_entries - 1;
1536 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1537
355c7265
BG		 1538 status = -ENOMEM;
1539
0da34b6d
BG		 1540 /* allocate the host shadow rings */
1541
1542 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1543 * sizeof(*mgp->tx.req_list);
1544 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1545 if (mgp->tx.req_bytes == NULL)
1546 goto abort_with_nothing;
1547
1548 /* ensure req_list entries are aligned to 8 bytes */
1549 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1550 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1551
1552 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1553 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1554 if (mgp->rx_small.shadow == NULL)
1555 goto abort_with_tx_req_bytes;
1556
1557 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1558 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1559 if (mgp->rx_big.shadow == NULL)
1560 goto abort_with_rx_small_shadow;
1561
1562 /* allocate the host info rings */
1563
1564 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1565 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1566 if (mgp->tx.info == NULL)
1567 goto abort_with_rx_big_shadow;
1568
1569 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1570 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1571 if (mgp->rx_small.info == NULL)
1572 goto abort_with_tx_info;
1573
1574 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1575 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1576 if (mgp->rx_big.info == NULL)
1577 goto abort_with_rx_small_info;
1578
1579 /* Fill the receive rings */
c7dab99b
BG		 1580 mgp->rx_big.cnt = 0;
1581 mgp->rx_small.cnt = 0;
1582 mgp->rx_big.fill_cnt = 0;
1583 mgp->rx_small.fill_cnt = 0;
1584 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1585 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1586 mgp->rx_small.watchdog_needed = 0;
1587 mgp->rx_big.watchdog_needed = 0;
1588 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1589 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1590
c7dab99b
BG		 1591 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1592 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1593 dev->name, mgp->rx_small.fill_cnt);
1594 goto abort_with_rx_small_ring;
0da34b6d
BG		 1595 }
1596
c7dab99b
BG		 1597 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1598 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1599 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1600 dev->name, mgp->rx_big.fill_cnt);
1601 goto abort_with_rx_big_ring;
0da34b6d
BG		 1602 }
1603
1604 return 0;
1605
1606abort_with_rx_big_ring:
c7dab99b
BG		 1607 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1608 int idx = i & mgp->rx_big.mask;
1609 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1610 mgp->big_bytes);
1611 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1612 }
1613
1614abort_with_rx_small_ring:
c7dab99b
BG		 1615 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1616 int idx = i & mgp->rx_small.mask;
1617 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1618 mgp->small_bytes + MXGEFW_PAD);
1619 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1620 }
c7dab99b 1621
0da34b6d
BG		 1622 kfree(mgp->rx_big.info);
1623
1624abort_with_rx_small_info:
1625 kfree(mgp->rx_small.info);
1626
1627abort_with_tx_info:
1628 kfree(mgp->tx.info);
1629
1630abort_with_rx_big_shadow:
1631 kfree(mgp->rx_big.shadow);
1632
1633abort_with_rx_small_shadow:
1634 kfree(mgp->rx_small.shadow);
1635
1636abort_with_tx_req_bytes:
1637 kfree(mgp->tx.req_bytes);
1638 mgp->tx.req_bytes = NULL;
1639 mgp->tx.req_list = NULL;
1640
1641abort_with_nothing:
1642 return status;
1643}
1644
1645static void myri10ge_free_rings(struct net_device *dev)
1646{
1647 struct myri10ge_priv *mgp;
1648 struct sk_buff *skb;
1649 struct myri10ge_tx_buf *tx;
1650 int i, len, idx;
1651
1652 mgp = netdev_priv(dev);
1653
c7dab99b
BG		 1654 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1655 idx = i & mgp->rx_big.mask;
1656 if (i == mgp->rx_big.fill_cnt - 1)
1657 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1658 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1659 mgp->big_bytes);
1660 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1661 }
1662
c7dab99b
BG		 1663 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1664 idx = i & mgp->rx_small.mask;
1665 if (i == mgp->rx_small.fill_cnt - 1)
1666 mgp->rx_small.info[idx].page_offset =
1667 MYRI10GE_ALLOC_SIZE;
1668 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1669 mgp->small_bytes + MXGEFW_PAD);
1670 put_page(mgp->rx_small.info[idx].page);
1671 }
0da34b6d
BG		 1672 tx = &mgp->tx;
1673 while (tx->done != tx->req) {
1674 idx = tx->done & tx->mask;
1675 skb = tx->info[idx].skb;
1676
1677 /* Mark as free */
1678 tx->info[idx].skb = NULL;
1679 tx->done++;
1680 len = pci_unmap_len(&tx->info[idx], len);
1681 pci_unmap_len_set(&tx->info[idx], len, 0);
1682 if (skb) {
1683 mgp->stats.tx_dropped++;
1684 dev_kfree_skb_any(skb);
1685 if (len)
1686 pci_unmap_single(mgp->pdev,
1687 pci_unmap_addr(&tx->info[idx],
1688 bus), len,
1689 PCI_DMA_TODEVICE);
1690 } else {
1691 if (len)
1692 pci_unmap_page(mgp->pdev,
1693 pci_unmap_addr(&tx->info[idx],
1694 bus), len,
1695 PCI_DMA_TODEVICE);
1696 }
1697 }
1698 kfree(mgp->rx_big.info);
1699
1700 kfree(mgp->rx_small.info);
1701
1702 kfree(mgp->tx.info);
1703
1704 kfree(mgp->rx_big.shadow);
1705
1706 kfree(mgp->rx_small.shadow);
1707
1708 kfree(mgp->tx.req_bytes);
1709 mgp->tx.req_bytes = NULL;
1710 mgp->tx.req_list = NULL;
1711}
1712
df30a740
BG		 1713static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1714{
1715 struct pci_dev *pdev = mgp->pdev;
1716 int status;
1717
1718 if (myri10ge_msi) {
1719 status = pci_enable_msi(pdev);
1720 if (status != 0)
1721 dev_err(&pdev->dev,
1722 "Error %d setting up MSI; falling back to xPIC\n",
1723 status);
1724 else
1725 mgp->msi_enabled = 1;
1726 } else {
1727 mgp->msi_enabled = 0;
1728 }
1729 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1730 mgp->dev->name, mgp);
1731 if (status != 0) {
1732 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1733 if (mgp->msi_enabled)
1734 pci_disable_msi(pdev);
1735 }
1736 return status;
1737}
1738
1739static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1740{
1741 struct pci_dev *pdev = mgp->pdev;
1742
1743 free_irq(pdev->irq, mgp);
1744 if (mgp->msi_enabled)
1745 pci_disable_msi(pdev);
1746}
1747
1e6e9342
AG		 1748static int
1749myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1750 void **ip_hdr, void **tcpudp_hdr,
1751 u64 * hdr_flags, void *priv)
1752{
1753 struct ethhdr *eh;
1754 struct vlan_ethhdr *veh;
1755 struct iphdr *iph;
1756 u8 *va = page_address(frag->page) + frag->page_offset;
1757 unsigned long ll_hlen;
1758 __wsum csum = (__wsum) (unsigned long)priv;
1759
1760 /* find the mac header, aborting if not IPv4 */
1761
1762 eh = (struct ethhdr *)va;
1763 *mac_hdr = eh;
1764 ll_hlen = ETH_HLEN;
1765 if (eh->h_proto != htons(ETH_P_IP)) {
1766 if (eh->h_proto == htons(ETH_P_8021Q)) {
1767 veh = (struct vlan_ethhdr *)va;
1768 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1769 return -1;
1770
1771 ll_hlen += VLAN_HLEN;
1772
1773 /*
1774 * HW checksum starts ETH_HLEN bytes into
1775 * frame, so we must subtract off the VLAN
1776 * header's checksum before csum can be used
1777 */
1778 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1779 VLAN_HLEN, 0));
1780 } else {
1781 return -1;
1782 }
1783 }
1784 *hdr_flags = LRO_IPV4;
1785
1786 iph = (struct iphdr *)(va + ll_hlen);
1787 *ip_hdr = iph;
1788 if (iph->protocol != IPPROTO_TCP)
1789 return -1;
1790 *hdr_flags |= LRO_TCP;
1791 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1792
1793 /* verify the IP checksum */
1794 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1795 return -1;
1796
1797 /* verify the checksum */
1798 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1799 ntohs(iph->tot_len) - (iph->ihl << 2),
1800 IPPROTO_TCP, csum)))
1801 return -1;
1802
1803 return 0;
1804}
1805
0da34b6d
BG		 1806static int myri10ge_open(struct net_device *dev)
1807{
1808 struct myri10ge_priv *mgp;
1809 struct myri10ge_cmd cmd;
1e6e9342 1810 struct net_lro_mgr *lro_mgr;
0da34b6d
BG		 1811 int status, big_pow2;
1812
1813 mgp = netdev_priv(dev);
1814
1815 if (mgp->running != MYRI10GE_ETH_STOPPED)
1816 return -EBUSY;
1817
1818 mgp->running = MYRI10GE_ETH_STARTING;
1819 status = myri10ge_reset(mgp);
1820 if (status != 0) {
1821 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1822 goto abort_with_nothing;
0da34b6d
BG		 1823 }
1824
df30a740
BG		 1825 status = myri10ge_request_irq(mgp);
1826 if (status != 0)
1827 goto abort_with_nothing;
1828
0da34b6d
BG		 1829 /* decide what small buffer size to use. For good TCP rx
1830 * performance, it is important to not receive 1514 byte
1831 * frames into jumbo buffers, as it confuses the socket buffer
1832 * accounting code, leading to drops and erratic performance.
1833 */
1834
1835 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1836 /* enough for a TCP header */
1837 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1838 ? (128 - MXGEFW_PAD)
1839 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1840 else
de3c4507
BG		 1841 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1842 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1843
1844 /* Override the small buffer size? */
1845 if (myri10ge_small_bytes > 0)
1846 mgp->small_bytes = myri10ge_small_bytes;
1847
0da34b6d
BG		 1848 /* get the lanai pointers to the send and receive rings */
1849
1850 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1851 mgp->tx.lanai =
1852 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1853
1854 status |=
1855 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1856 mgp->rx_small.lanai =
1857 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1858
1859 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1860 mgp->rx_big.lanai =
1861 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1862
1863 if (status != 0) {
1864 printk(KERN_ERR
1865 "myri10ge: %s: failed to get ring sizes or locations\n",
1866 dev->name);
1867 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1868 goto abort_with_irq;
0da34b6d
BG		 1869 }
1870
276e26c3 1871 if (myri10ge_wcfifo && mgp->wc_enabled) {
e700f9f4
BG		 1872 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1873 mgp->rx_small.wc_fifo =
1874 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1875 mgp->rx_big.wc_fifo =
1876 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1877 } else {
1878 mgp->tx.wc_fifo = NULL;
1879 mgp->rx_small.wc_fifo = NULL;
1880 mgp->rx_big.wc_fifo = NULL;
1881 }
1882
0da34b6d
BG		 1883 /* Firmware needs the big buff size as a power of 2. Lie and
1884 * tell him the buffer is larger, because we only use 1
1885 * buffer/pkt, and the mtu will prevent overruns.
1886 */
13348bee 1887 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 1888 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 1889 while (!is_power_of_2(big_pow2))
c7dab99b 1890 big_pow2++;
13348bee 1891 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1892 } else {
1893 big_pow2 = MYRI10GE_ALLOC_SIZE;
1894 mgp->big_bytes = big_pow2;
1895 }
1896
1897 status = myri10ge_allocate_rings(dev);
1898 if (status != 0)
df30a740 1899 goto abort_with_irq;
0da34b6d
BG		 1900
1901 /* now give firmware buffers sizes, and MTU */
1902 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1903 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1904 cmd.data0 = mgp->small_bytes;
1905 status |=
1906 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1907 cmd.data0 = big_pow2;
1908 status |=
1909 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1910 if (status) {
1911 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1912 dev->name);
1913 goto abort_with_rings;
1914 }
1915
1916 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1917 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1918 cmd.data2 = sizeof(struct mcp_irq_data);
1919 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1920 if (status == -ENOSYS) {
1921 dma_addr_t bus = mgp->fw_stats_bus;
1922 bus += offsetof(struct mcp_irq_data, send_done_count);
1923 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1924 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1925 status = myri10ge_send_cmd(mgp,
1926 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1927 &cmd, 0);
1928 /* Firmware cannot support multicast without STATS_DMA_V2 */
1929 mgp->fw_multicast_support = 0;
1930 } else {
1931 mgp->fw_multicast_support = 1;
1932 }
0da34b6d
BG		 1933 if (status) {
1934 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1935 dev->name);
1936 goto abort_with_rings;
1937 }
1938
40f6cff5 1939 mgp->link_state = htonl(~0U);
0da34b6d
BG		 1940 mgp->rdma_tags_available = 15;
1941
1e6e9342
AG		 1942 lro_mgr = &mgp->rx_done.lro_mgr;
1943 lro_mgr->dev = dev;
1944 lro_mgr->features = LRO_F_NAPI;
1945 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
1946 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
1947 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
1948 lro_mgr->lro_arr = mgp->rx_done.lro_desc;
1949 lro_mgr->get_frag_header = myri10ge_get_frag_header;
1950 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
1951 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
1952 lro_mgr->max_aggr = MAX_SKB_FRAGS;
1953
bea3348e 1954 napi_enable(&mgp->napi); /* must happen prior to any irq */
0da34b6d
BG		 1955
1956 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1957 if (status) {
1958 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1959 dev->name);
1960 goto abort_with_rings;
1961 }
1962
1963 mgp->wake_queue = 0;
1964 mgp->stop_queue = 0;
1965 mgp->running = MYRI10GE_ETH_RUNNING;
1966 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1967 add_timer(&mgp->watchdog_timer);
1968 netif_wake_queue(dev);
1969 return 0;
1970
1971abort_with_rings:
1972 myri10ge_free_rings(dev);
1973
df30a740
BG		 1974abort_with_irq:
1975 myri10ge_free_irq(mgp);
1976
0da34b6d
BG		 1977abort_with_nothing:
1978 mgp->running = MYRI10GE_ETH_STOPPED;
1979 return -ENOMEM;
1980}
1981
1982static int myri10ge_close(struct net_device *dev)
1983{
1984 struct myri10ge_priv *mgp;
1985 struct myri10ge_cmd cmd;
1986 int status, old_down_cnt;
1987
1988 mgp = netdev_priv(dev);
1989
1990 if (mgp->running != MYRI10GE_ETH_RUNNING)
1991 return 0;
1992
1993 if (mgp->tx.req_bytes == NULL)
1994 return 0;
1995
1996 del_timer_sync(&mgp->watchdog_timer);
1997 mgp->running = MYRI10GE_ETH_STOPPING;
bea3348e 1998 napi_disable(&mgp->napi);
0da34b6d
BG		 1999 netif_carrier_off(dev);
2000 netif_stop_queue(dev);
2001 old_down_cnt = mgp->down_cnt;
2002 mb();
2003 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2004 if (status)
2005 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2006 dev->name);
2007
2008 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2009 if (old_down_cnt == mgp->down_cnt)
2010 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2011
2012 netif_tx_disable(dev);
df30a740 2013 myri10ge_free_irq(mgp);
0da34b6d
BG		 2014 myri10ge_free_rings(dev);
2015
2016 mgp->running = MYRI10GE_ETH_STOPPED;
2017 return 0;
2018}
2019
2020/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2021 * backwards one at a time and handle ring wraps */
2022
2023static inline void
2024myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2025 struct mcp_kreq_ether_send *src, int cnt)
2026{
2027 int idx, starting_slot;
2028 starting_slot = tx->req;
2029 while (cnt > 1) {
2030 cnt--;
2031 idx = (starting_slot + cnt) & tx->mask;
2032 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2033 mb();
2034 }
2035}
2036
2037/*
2038 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2039 * at most 32 bytes at a time, so as to avoid involving the software
2040 * pio handler in the nic. We re-write the first segment's flags
2041 * to mark them valid only after writing the entire chain.
2042 */
2043
2044static inline void
2045myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2046 int cnt)
2047{
2048 int idx, i;
2049 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2050 struct mcp_kreq_ether_send *srcp;
2051 u8 last_flags;
2052
2053 idx = tx->req & tx->mask;
2054
2055 last_flags = src->flags;
2056 src->flags = 0;
2057 mb();
2058 dst = dstp = &tx->lanai[idx];
2059 srcp = src;
2060
2061 if ((idx + cnt) < tx->mask) {
2062 for (i = 0; i < (cnt - 1); i += 2) {
2063 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2064 mb(); /* force write every 32 bytes */
2065 srcp += 2;
2066 dstp += 2;
2067 }
2068 } else {
2069 /* submit all but the first request, and ensure
2070 * that it is submitted below */
2071 myri10ge_submit_req_backwards(tx, src, cnt);
2072 i = 0;
2073 }
2074 if (i < cnt) {
2075 /* submit the first request */
2076 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2077 mb(); /* barrier before setting valid flag */
2078 }
2079
2080 /* re-write the last 32-bits with the valid flags */
2081 src->flags = last_flags;
40f6cff5 2082 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2083 tx->req += cnt;
2084 mb();
2085}
2086
2087static inline void
2088myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2089 struct mcp_kreq_ether_send *src, int cnt)
2090{
2091 tx->req += cnt;
2092 mb();
2093 while (cnt >= 4) {
2094 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2095 mb();
2096 src += 4;
2097 cnt -= 4;
2098 }
2099 if (cnt > 0) {
2100 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2101 * needs to be so that we don't overrun it */
e700f9f4
BG		 2102 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2103 src, 64);
0da34b6d
BG		 2104 mb();
2105 }
2106}
2107
2108/*
2109 * Transmit a packet. We need to split the packet so that a single
2110 * segment does not cross myri10ge->tx.boundary, so this makes segment
2111 * counting tricky. So rather than try to count segments up front, we
2112 * just give up if there are too few segments to hold a reasonably
2113 * fragmented packet currently available. If we run
2114 * out of segments while preparing a packet for DMA, we just linearize
2115 * it and try again.
2116 */
2117
2118static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2119{
2120 struct myri10ge_priv *mgp = netdev_priv(dev);
2121 struct mcp_kreq_ether_send *req;
2122 struct myri10ge_tx_buf *tx = &mgp->tx;
2123 struct skb_frag_struct *frag;
2124 dma_addr_t bus;
40f6cff5
AV		 2125 u32 low;
2126 __be32 high_swapped;
0da34b6d
BG		 2127 unsigned int len;
2128 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2129 u16 pseudo_hdr_offset, cksum_offset;
2130 int cum_len, seglen, boundary, rdma_count;
2131 u8 flags, odd_flag;
2132
2133again:
2134 req = tx->req_list;
2135 avail = tx->mask - 1 - (tx->req - tx->done);
2136
2137 mss = 0;
2138 max_segments = MXGEFW_MAX_SEND_DESC;
2139
917690cd 2140 if (skb_is_gso(skb)) {
7967168c 2141 mss = skb_shinfo(skb)->gso_size;
917690cd 2142 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2143 }
0da34b6d
BG		 2144
2145 if ((unlikely(avail < max_segments))) {
2146 /* we are out of transmit resources */
2147 mgp->stop_queue++;
2148 netif_stop_queue(dev);
2149 return 1;
2150 }
2151
2152 /* Setup checksum offloading, if needed */
2153 cksum_offset = 0;
2154 pseudo_hdr_offset = 0;
2155 odd_flag = 0;
2156 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2157 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2158 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2159 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2160 /* If the headers are excessively large, then we must
2161 * fall back to a software checksum */
2162 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
84fa7933 2163 if (skb_checksum_help(skb))
0da34b6d
BG		 2164 goto drop;
2165 cksum_offset = 0;
2166 pseudo_hdr_offset = 0;
2167 } else {
0da34b6d
BG		 2168 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2169 flags |= MXGEFW_FLAGS_CKSUM;
2170 }
2171 }
2172
2173 cum_len = 0;
2174
0da34b6d
BG		 2175 if (mss) { /* TSO */
2176 /* this removes any CKSUM flag from before */
2177 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2178
2179 /* negative cum_len signifies to the
2180 * send loop that we are still in the
2181 * header portion of the TSO packet.
2182 * TSO header must be at most 134 bytes long */
ab6a5bb6 2183 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d
BG		 2184
2185 /* for TSO, pseudo_hdr_offset holds mss.
2186 * The firmware figures out where to put
2187 * the checksum by parsing the header. */
40f6cff5 2188 pseudo_hdr_offset = mss;
0da34b6d 2189 } else
0da34b6d
BG		 2190 /* Mark small packets, and pad out tiny packets */
2191 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2192 flags |= MXGEFW_FLAGS_SMALL;
2193
2194 /* pad frames to at least ETH_ZLEN bytes */
2195 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2196 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2197 /* The packet is gone, so we must
2198 * return 0 */
2199 mgp->stats.tx_dropped += 1;
2200 return 0;
2201 }
2202 /* adjust the len to account for the zero pad
2203 * so that the nic can know how long it is */
2204 skb->len = ETH_ZLEN;
2205 }
2206 }
2207
2208 /* map the skb for DMA */
2209 len = skb->len - skb->data_len;
2210 idx = tx->req & tx->mask;
2211 tx->info[idx].skb = skb;
2212 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2213 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2214 pci_unmap_len_set(&tx->info[idx], len, len);
2215
2216 frag_cnt = skb_shinfo(skb)->nr_frags;
2217 frag_idx = 0;
2218 count = 0;
2219 rdma_count = 0;
2220
2221 /* "rdma_count" is the number of RDMAs belonging to the
2222 * current packet BEFORE the current send request. For
2223 * non-TSO packets, this is equal to "count".
2224 * For TSO packets, rdma_count needs to be reset
2225 * to 0 after a segment cut.
2226 *
2227 * The rdma_count field of the send request is
2228 * the number of RDMAs of the packet starting at
2229 * that request. For TSO send requests with one ore more cuts
2230 * in the middle, this is the number of RDMAs starting
2231 * after the last cut in the request. All previous
2232 * segments before the last cut implicitly have 1 RDMA.
2233 *
2234 * Since the number of RDMAs is not known beforehand,
2235 * it must be filled-in retroactively - after each
2236 * segmentation cut or at the end of the entire packet.
2237 */
2238
2239 while (1) {
2240 /* Break the SKB or Fragment up into pieces which
2241 * do not cross mgp->tx.boundary */
2242 low = MYRI10GE_LOWPART_TO_U32(bus);
2243 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2244 while (len) {
2245 u8 flags_next;
2246 int cum_len_next;
2247
2248 if (unlikely(count == max_segments))
2249 goto abort_linearize;
2250
2251 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2252 seglen = boundary - low;
2253 if (seglen > len)
2254 seglen = len;
2255 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2256 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2257 if (mss) { /* TSO */
2258 (req - rdma_count)->rdma_count = rdma_count + 1;
2259
2260 if (likely(cum_len >= 0)) { /* payload */
2261 int next_is_first, chop;
2262
2263 chop = (cum_len_next > mss);
2264 cum_len_next = cum_len_next % mss;
2265 next_is_first = (cum_len_next == 0);
2266 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2267 flags_next |= next_is_first *
2268 MXGEFW_FLAGS_FIRST;
2269 rdma_count |= -(chop | next_is_first);
2270 rdma_count += chop & !next_is_first;
2271 } else if (likely(cum_len_next >= 0)) { /* header ends */
2272 int small;
2273
2274 rdma_count = -1;
2275 cum_len_next = 0;
2276 seglen = -cum_len;
2277 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2278 flags_next = MXGEFW_FLAGS_TSO_PLD |
2279 MXGEFW_FLAGS_FIRST |
2280 (small * MXGEFW_FLAGS_SMALL);
2281 }
2282 }
0da34b6d
BG		 2283 req->addr_high = high_swapped;
2284 req->addr_low = htonl(low);
40f6cff5 2285 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2286 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2287 req->rdma_count = 1;
2288 req->length = htons(seglen);
2289 req->cksum_offset = cksum_offset;
2290 req->flags = flags | ((cum_len & 1) * odd_flag);
2291
2292 low += seglen;
2293 len -= seglen;
2294 cum_len = cum_len_next;
2295 flags = flags_next;
2296 req++;
2297 count++;
2298 rdma_count++;
2299 if (unlikely(cksum_offset > seglen))
2300 cksum_offset -= seglen;
2301 else
2302 cksum_offset = 0;
2303 }
2304 if (frag_idx == frag_cnt)
2305 break;
2306
2307 /* map next fragment for DMA */
2308 idx = (count + tx->req) & tx->mask;
2309 frag = &skb_shinfo(skb)->frags[frag_idx];
2310 frag_idx++;
2311 len = frag->size;
2312 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2313 len, PCI_DMA_TODEVICE);
2314 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2315 pci_unmap_len_set(&tx->info[idx], len, len);
2316 }
2317
2318 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2319 if (mss)
2320 do {
2321 req--;
2322 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2323 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2324 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2325 idx = ((count - 1) + tx->req) & tx->mask;
2326 tx->info[idx].last = 1;
2327 if (tx->wc_fifo == NULL)
2328 myri10ge_submit_req(tx, tx->req_list, count);
2329 else
2330 myri10ge_submit_req_wc(tx, tx->req_list, count);
2331 tx->pkt_start++;
2332 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2333 mgp->stop_queue++;
2334 netif_stop_queue(dev);
2335 }
2336 dev->trans_start = jiffies;
2337 return 0;
2338
2339abort_linearize:
2340 /* Free any DMA resources we've alloced and clear out the skb
2341 * slot so as to not trip up assertions, and to avoid a
2342 * double-free if linearizing fails */
2343
2344 last_idx = (idx + 1) & tx->mask;
2345 idx = tx->req & tx->mask;
2346 tx->info[idx].skb = NULL;
2347 do {
2348 len = pci_unmap_len(&tx->info[idx], len);
2349 if (len) {
2350 if (tx->info[idx].skb != NULL)
2351 pci_unmap_single(mgp->pdev,
2352 pci_unmap_addr(&tx->info[idx],
2353 bus), len,
2354 PCI_DMA_TODEVICE);
2355 else
2356 pci_unmap_page(mgp->pdev,
2357 pci_unmap_addr(&tx->info[idx],
2358 bus), len,
2359 PCI_DMA_TODEVICE);
2360 pci_unmap_len_set(&tx->info[idx], len, 0);
2361 tx->info[idx].skb = NULL;
2362 }
2363 idx = (idx + 1) & tx->mask;
2364 } while (idx != last_idx);
89114afd 2365 if (skb_is_gso(skb)) {
0da34b6d
BG		 2366 printk(KERN_ERR
2367 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2368 mgp->dev->name);
2369 goto drop;
2370 }
2371
bec0e859 2372 if (skb_linearize(skb))
0da34b6d
BG		 2373 goto drop;
2374
2375 mgp->tx_linearized++;
2376 goto again;
2377
2378drop:
2379 dev_kfree_skb_any(skb);
2380 mgp->stats.tx_dropped += 1;
2381 return 0;
2382
2383}
2384
2385static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2386{
2387 struct myri10ge_priv *mgp = netdev_priv(dev);
2388 return &mgp->stats;
2389}
2390
2391static void myri10ge_set_multicast_list(struct net_device *dev)
2392{
85a7ea1b
BG		 2393 struct myri10ge_cmd cmd;
2394 struct myri10ge_priv *mgp;
2395 struct dev_mc_list *mc_list;
6250223e 2396 __be32 data[2] = { 0, 0 };
85a7ea1b 2397 int err;
0795af57 2398 DECLARE_MAC_BUF(mac);
85a7ea1b
BG		 2399
2400 mgp = netdev_priv(dev);
0da34b6d
BG		 2401 /* can be called from atomic contexts,
2402 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2403 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2404
2405 /* This firmware is known to not support multicast */
2f76216f 2406 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2407 return;
2408
2409 /* Disable multicast filtering */
2410
2411 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2412 if (err != 0) {
2413 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2414 " error status: %d\n", dev->name, err);
2415 goto abort;
2416 }
2417
2f76216f 2418 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2419 /* request to disable multicast filtering, so quit here */
2420 return;
2421 }
2422
2423 /* Flush the filters */
2424
2425 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2426 &cmd, 1);
2427 if (err != 0) {
2428 printk(KERN_ERR
2429 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2430 ", error status: %d\n", dev->name, err);
2431 goto abort;
2432 }
2433
2434 /* Walk the multicast list, and add each address */
2435 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2436 memcpy(data, &mc_list->dmi_addr, 6);
2437 cmd.data0 = ntohl(data[0]);
2438 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2439 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2440 &cmd, 1);
2441
2442 if (err != 0) {
2443 printk(KERN_ERR "myri10ge: %s: Failed "
2444 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2445 "%d\t", dev->name, err);
0795af57
JP		 2446 printk(KERN_ERR "MAC %s\n",
2447 print_mac(mac, mc_list->dmi_addr));
85a7ea1b
BG		 2448 goto abort;
2449 }
2450 }
2451 /* Enable multicast filtering */
2452 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2453 if (err != 0) {
2454 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2455 "error status: %d\n", dev->name, err);
2456 goto abort;
2457 }
2458
2459 return;
2460
2461abort:
2462 return;
0da34b6d
BG		 2463}
2464
2465static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2466{
2467 struct sockaddr *sa = addr;
2468 struct myri10ge_priv *mgp = netdev_priv(dev);
2469 int status;
2470
2471 if (!is_valid_ether_addr(sa->sa_data))
2472 return -EADDRNOTAVAIL;
2473
2474 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2475 if (status != 0) {
2476 printk(KERN_ERR
2477 "myri10ge: %s: changing mac address failed with %d\n",
2478 dev->name, status);
2479 return status;
2480 }
2481
2482 /* change the dev structure */
2483 memcpy(dev->dev_addr, sa->sa_data, 6);
2484 return 0;
2485}
2486
2487static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2488{
2489 struct myri10ge_priv *mgp = netdev_priv(dev);
2490 int error = 0;
2491
2492 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2493 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2494 dev->name, new_mtu);
2495 return -EINVAL;
2496 }
2497 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2498 dev->name, dev->mtu, new_mtu);
2499 if (mgp->running) {
2500 /* if we change the mtu on an active device, we must
2501 * reset the device so the firmware sees the change */
2502 myri10ge_close(dev);
2503 dev->mtu = new_mtu;
2504 myri10ge_open(dev);
2505 } else
2506 dev->mtu = new_mtu;
2507
2508 return error;
2509}
2510
2511/*
2512 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2513 * Only do it if the bridge is a root port since we don't want to disturb
2514 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2515 */
2516
0da34b6d
BG		 2517static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2518{
2519 struct pci_dev *bridge = mgp->pdev->bus->self;
2520 struct device *dev = &mgp->pdev->dev;
2521 unsigned cap;
2522 unsigned err_cap;
2523 u16 val;
2524 u8 ext_type;
2525 int ret;
2526
2527 if (!myri10ge_ecrc_enable || !bridge)
2528 return;
2529
2530 /* check that the bridge is a root port */
2531 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2532 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2533 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2534 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2535 if (myri10ge_ecrc_enable > 1) {
2536 struct pci_dev *old_bridge = bridge;
2537
2538 /* Walk the hierarchy up to the root port
2539 * where ECRC has to be enabled */
2540 do {
2541 bridge = bridge->bus->self;
2542 if (!bridge) {
2543 dev_err(dev,
2544 "Failed to find root port"
2545 " to force ECRC\n");
2546 return;
2547 }
2548 cap =
2549 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2550 pci_read_config_word(bridge,
2551 cap + PCI_CAP_FLAGS, &val);
2552 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2553 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2554
2555 dev_info(dev,
2556 "Forcing ECRC on non-root port %s"
2557 " (enabling on root port %s)\n",
2558 pci_name(old_bridge), pci_name(bridge));
2559 } else {
2560 dev_err(dev,
2561 "Not enabling ECRC on non-root port %s\n",
2562 pci_name(bridge));
2563 return;
2564 }
2565 }
2566
2567 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2568 if (!cap)
2569 return;
2570
2571 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2572 if (ret) {
2573 dev_err(dev, "failed reading ext-conf-space of %s\n",
2574 pci_name(bridge));
2575 dev_err(dev, "\t pci=nommconf in use? "
2576 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2577 return;
2578 }
2579 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2580 return;
2581
2582 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2583 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2584 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 2585}
2586
2587/*
2588 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2589 * when the PCI-E Completion packets are aligned on an 8-byte
2590 * boundary. Some PCI-E chip sets always align Completion packets; on
2591 * the ones that do not, the alignment can be enforced by enabling
2592 * ECRC generation (if supported).
2593 *
2594 * When PCI-E Completion packets are not aligned, it is actually more
2595 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2596 *
2597 * If the driver can neither enable ECRC nor verify that it has
2598 * already been enabled, then it must use a firmware image which works
2599 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2600 * should also ensure that it never gives the device a Read-DMA which is
2601 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2602 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2603 * firmware image, and set tx.boundary to 4KB.
2604 */
2605
5443e9ea 2606static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 2607{
5443e9ea
BG		 2608 struct pci_dev *pdev = mgp->pdev;
2609 struct device *dev = &pdev->dev;
302d242c 2610 int status;
0da34b6d 2611
5443e9ea
BG		 2612 mgp->tx.boundary = 4096;
2613 /*
2614 * Verify the max read request size was set to 4KB
2615 * before trying the test with 4KB.
2616 */
302d242c
BG		 2617 status = pcie_get_readrq(pdev);
2618 if (status < 0) {
5443e9ea
BG		 2619 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2620 goto abort;
2621 }
302d242c
BG		 2622 if (status != 4096) {
2623 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
5443e9ea
BG		 2624 mgp->tx.boundary = 2048;
2625 }
2626 /*
2627 * load the optimized firmware (which assumes aligned PCIe
2628 * completions) in order to see if it works on this host.
2629 */
2630 mgp->fw_name = myri10ge_fw_aligned;
2631 status = myri10ge_load_firmware(mgp);
2632 if (status != 0) {
2633 goto abort;
2634 }
2635
2636 /*
2637 * Enable ECRC if possible
2638 */
2639 myri10ge_enable_ecrc(mgp);
2640
2641 /*
2642 * Run a DMA test which watches for unaligned completions and
2643 * aborts on the first one seen.
2644 */
2645
2646 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2647 if (status == 0)
2648 return; /* keep the aligned firmware */
2649
2650 if (status != -E2BIG)
2651 dev_warn(dev, "DMA test failed: %d\n", status);
2652 if (status == -ENOSYS)
2653 dev_warn(dev, "Falling back to ethp! "
2654 "Please install up to date fw\n");
2655abort:
2656 /* fall back to using the unaligned firmware */
0da34b6d
BG		 2657 mgp->tx.boundary = 2048;
2658 mgp->fw_name = myri10ge_fw_unaligned;
2659
5443e9ea
BG		 2660}
2661
2662static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2663{
0da34b6d 2664 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2665 int link_width, exp_cap;
2666 u16 lnk;
2667
2668 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2669 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2670 link_width = (lnk >> 4) & 0x3f;
2671
ce7f9368
BG		 2672 /* Check to see if Link is less than 8 or if the
2673 * upstream bridge is known to provide aligned
2674 * completions */
2675 if (link_width < 8) {
2676 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2677 link_width);
2678 mgp->tx.boundary = 4096;
2679 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 2680 } else {
2681 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 2682 }
2683 } else {
2684 if (myri10ge_force_firmware == 1) {
2685 dev_info(&mgp->pdev->dev,
2686 "Assuming aligned completions (forced)\n");
2687 mgp->tx.boundary = 4096;
2688 mgp->fw_name = myri10ge_fw_aligned;
2689 } else {
2690 dev_info(&mgp->pdev->dev,
2691 "Assuming unaligned completions (forced)\n");
2692 mgp->tx.boundary = 2048;
2693 mgp->fw_name = myri10ge_fw_unaligned;
2694 }
2695 }
2696 if (myri10ge_fw_name != NULL) {
2697 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2698 myri10ge_fw_name);
2699 mgp->fw_name = myri10ge_fw_name;
2700 }
2701}
2702
0da34b6d
BG		 2703#ifdef CONFIG_PM
2704
2705static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2706{
2707 struct myri10ge_priv *mgp;
2708 struct net_device *netdev;
2709
2710 mgp = pci_get_drvdata(pdev);
2711 if (mgp == NULL)
2712 return -EINVAL;
2713 netdev = mgp->dev;
2714
2715 netif_device_detach(netdev);
2716 if (netif_running(netdev)) {
2717 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2718 rtnl_lock();
2719 myri10ge_close(netdev);
2720 rtnl_unlock();
2721 }
2722 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2723 pci_save_state(pdev);
0da34b6d 2724 pci_disable_device(pdev);
1a63e846
BG		 2725
2726 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2727}
2728
2729static int myri10ge_resume(struct pci_dev *pdev)
2730{
2731 struct myri10ge_priv *mgp;
2732 struct net_device *netdev;
2733 int status;
2734 u16 vendor;
2735
2736 mgp = pci_get_drvdata(pdev);
2737 if (mgp == NULL)
2738 return -EINVAL;
2739 netdev = mgp->dev;
2740 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2741 msleep(5); /* give card time to respond */
2742 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2743 if (vendor == 0xffff) {
2744 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2745 mgp->dev->name);
2746 return -EIO;
2747 }
83f6e152 2748
1a63e846
BG		 2749 status = pci_restore_state(pdev);
2750 if (status)
2751 return status;
4c2248cc
BG		 2752
2753 status = pci_enable_device(pdev);
1a63e846 2754 if (status) {
4c2248cc 2755 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2756 return status;
4c2248cc
BG		 2757 }
2758
0da34b6d
BG		 2759 pci_set_master(pdev);
2760
0da34b6d 2761 myri10ge_reset(mgp);
013b68bf 2762 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2763
2764 /* Save configuration space to be restored if the
2765 * nic resets due to a parity error */
83f6e152 2766 pci_save_state(pdev);
0da34b6d
BG		 2767
2768 if (netif_running(netdev)) {
2769 rtnl_lock();
df30a740 2770 status = myri10ge_open(netdev);
0da34b6d 2771 rtnl_unlock();
df30a740
BG		 2772 if (status != 0)
2773 goto abort_with_enabled;
2774
0da34b6d
BG		 2775 }
2776 netif_device_attach(netdev);
2777
2778 return 0;
2779
4c2248cc
BG		 2780abort_with_enabled:
2781 pci_disable_device(pdev);
0da34b6d
BG		 2782 return -EIO;
2783
2784}
2785
2786#endif /* CONFIG_PM */
2787
2788static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2789{
2790 struct pci_dev *pdev = mgp->pdev;
2791 int vs = mgp->vendor_specific_offset;
2792 u32 reboot;
2793
2794 /*enter read32 mode */
2795 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2796
2797 /*read REBOOT_STATUS (0xfffffff0) */
2798 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2799 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2800 return reboot;
2801}
2802
2803/*
2804 * This watchdog is used to check whether the board has suffered
2805 * from a parity error and needs to be recovered.
2806 */
c4028958 2807static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2808{
c4028958 2809 struct myri10ge_priv *mgp =
6250223e 2810 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2811 u32 reboot;
2812 int status;
2813 u16 cmd, vendor;
2814
2815 mgp->watchdog_resets++;
2816 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2817 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2818 /* Bus master DMA disabled? Check to see
2819 * if the card rebooted due to a parity error
2820 * For now, just report it */
2821 reboot = myri10ge_read_reboot(mgp);
2822 printk(KERN_ERR
f181137f
BG		 2823 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2824 mgp->dev->name, reboot,
2825 myri10ge_reset_recover ? " " : " not");
2826 if (myri10ge_reset_recover == 0)
2827 return;
2828
2829 myri10ge_reset_recover--;
2830
0da34b6d
BG		 2831 /*
2832 * A rebooted nic will come back with config space as
2833 * it was after power was applied to PCIe bus.
2834 * Attempt to restore config space which was saved
2835 * when the driver was loaded, or the last time the
2836 * nic was resumed from power saving mode.
2837 */
83f6e152 2838 pci_restore_state(mgp->pdev);
7adda30c
BG		 2839
2840 /* save state again for accounting reasons */
83f6e152 2841 pci_save_state(mgp->pdev);
7adda30c 2842
0da34b6d
BG		 2843 } else {
2844 /* if we get back -1's from our slot, perhaps somebody
2845 * powered off our card. Don't try to reset it in
2846 * this case */
2847 if (cmd == 0xffff) {
2848 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2849 if (vendor == 0xffff) {
2850 printk(KERN_ERR
2851 "myri10ge: %s: device disappeared!\n",
2852 mgp->dev->name);
2853 return;
2854 }
2855 }
2856 /* Perhaps it is a software error. Try to reset */
2857
2858 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2859 mgp->dev->name);
2860 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2861 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2862 mgp->tx.pkt_start, mgp->tx.pkt_done,
2863 (int)ntohl(mgp->fw_stats->send_done_count));
2864 msleep(2000);
2865 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2866 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2867 mgp->tx.pkt_start, mgp->tx.pkt_done,
2868 (int)ntohl(mgp->fw_stats->send_done_count));
2869 }
2870 rtnl_lock();
2871 myri10ge_close(mgp->dev);
2872 status = myri10ge_load_firmware(mgp);
2873 if (status != 0)
2874 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2875 mgp->dev->name);
2876 else
2877 myri10ge_open(mgp->dev);
2878 rtnl_unlock();
2879}
2880
2881/*
2882 * We use our own timer routine rather than relying upon
2883 * netdev->tx_timeout because we have a very large hardware transmit
2884 * queue. Due to the large queue, the netdev->tx_timeout function
2885 * cannot detect a NIC with a parity error in a timely fashion if the
2886 * NIC is lightly loaded.
2887 */
2888static void myri10ge_watchdog_timer(unsigned long arg)
2889{
2890 struct myri10ge_priv *mgp;
626fda94 2891 u32 rx_pause_cnt;
0da34b6d
BG		 2892
2893 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2894
2895 if (mgp->rx_small.watchdog_needed) {
2896 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2897 mgp->small_bytes + MXGEFW_PAD, 1);
2898 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2899 myri10ge_fill_thresh)
2900 mgp->rx_small.watchdog_needed = 0;
2901 }
2902 if (mgp->rx_big.watchdog_needed) {
2903 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2904 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2905 myri10ge_fill_thresh)
2906 mgp->rx_big.watchdog_needed = 0;
2907 }
626fda94 2908 rx_pause_cnt = ntohl(mgp->fw_stats->dropped_pause);
c7dab99b 2909
0da34b6d 2910 if (mgp->tx.req != mgp->tx.done &&
c54772e7 2911 mgp->tx.done == mgp->watchdog_tx_done &&
626fda94 2912 mgp->watchdog_tx_req != mgp->watchdog_tx_done) {
0da34b6d 2913 /* nic seems like it might be stuck.. */
626fda94
BG		 2914 if (rx_pause_cnt != mgp->watchdog_pause) {
2915 if (net_ratelimit())
2916 printk(KERN_WARNING "myri10ge %s:"
2917 "TX paused, check link partner\n",
2918 mgp->dev->name);
2919 } else {
2920 schedule_work(&mgp->watchdog_work);
2921 return;
2922 }
2923 }
2924 /* rearm timer */
2925 mod_timer(&mgp->watchdog_timer,
2926 jiffies + myri10ge_watchdog_timeout * HZ);
0da34b6d 2927 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 2928 mgp->watchdog_tx_req = mgp->tx.req;
626fda94 2929 mgp->watchdog_pause = rx_pause_cnt;
0da34b6d
BG		 2930}
2931
2932static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2933{
2934 struct net_device *netdev;
2935 struct myri10ge_priv *mgp;
2936 struct device *dev = &pdev->dev;
2937 size_t bytes;
2938 int i;
2939 int status = -ENXIO;
0da34b6d 2940 int dac_enabled;
0da34b6d
BG		 2941
2942 netdev = alloc_etherdev(sizeof(*mgp));
2943 if (netdev == NULL) {
2944 dev_err(dev, "Could not allocate ethernet device\n");
2945 return -ENOMEM;
2946 }
2947
b245fb67
MH		 2948 SET_NETDEV_DEV(netdev, &pdev->dev);
2949
0da34b6d 2950 mgp = netdev_priv(netdev);
0da34b6d 2951 mgp->dev = netdev;
bea3348e
SH		 2952 netif_napi_add(netdev, &mgp->napi,
2953 myri10ge_poll, myri10ge_napi_weight);
0da34b6d
BG		 2954 mgp->pdev = pdev;
2955 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2956 mgp->pause = myri10ge_flow_control;
2957 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 2958 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 2959 init_waitqueue_head(&mgp->down_wq);
2960
2961 if (pci_enable_device(pdev)) {
2962 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2963 status = -ENODEV;
2964 goto abort_with_netdev;
2965 }
0da34b6d
BG		 2966
2967 /* Find the vendor-specific cap so we can check
2968 * the reboot register later on */
2969 mgp->vendor_specific_offset
2970 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2971
2972 /* Set our max read request to 4KB */
302d242c 2973 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 2974 if (status != 0) {
2975 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2976 status);
2977 goto abort_with_netdev;
2978 }
2979
2980 pci_set_master(pdev);
2981 dac_enabled = 1;
2982 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2983 if (status != 0) {
2984 dac_enabled = 0;
2985 dev_err(&pdev->dev,
2986 "64-bit pci address mask was refused, trying 32-bit");
2987 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2988 }
2989 if (status != 0) {
2990 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2991 goto abort_with_netdev;
2992 }
b10c0668
BG		 2993 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2994 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 2995 if (mgp->cmd == NULL)
2996 goto abort_with_netdev;
2997
b10c0668
BG		 2998 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2999 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 3000 if (mgp->fw_stats == NULL)
3001 goto abort_with_cmd;
3002
3003 mgp->board_span = pci_resource_len(pdev, 0);
3004 mgp->iomem_base = pci_resource_start(pdev, 0);
3005 mgp->mtrr = -1;
276e26c3 3006 mgp->wc_enabled = 0;
0da34b6d
BG		 3007#ifdef CONFIG_MTRR
3008 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3009 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3010 if (mgp->mtrr >= 0)
3011 mgp->wc_enabled = 1;
0da34b6d
BG		 3012#endif
3013 /* Hack. need to get rid of these magic numbers */
3014 mgp->sram_size =
3015 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3016 if (mgp->sram_size > mgp->board_span) {
3017 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3018 mgp->board_span);
3019 goto abort_with_wc;
3020 }
3021 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3022 if (mgp->sram == NULL) {
3023 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3024 mgp->board_span, mgp->iomem_base);
3025 status = -ENXIO;
3026 goto abort_with_wc;
3027 }
3028 memcpy_fromio(mgp->eeprom_strings,
3029 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3030 MYRI10GE_EEPROM_STRINGS_SIZE);
3031 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3032 status = myri10ge_read_mac_addr(mgp);
3033 if (status)
3034 goto abort_with_ioremap;
3035
3036 for (i = 0; i < ETH_ALEN; i++)
3037 netdev->dev_addr[i] = mgp->mac_addr[i];
3038
3039 /* allocate rx done ring */
3040 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3041 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3042 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 3043 if (mgp->rx_done.entry == NULL)
3044 goto abort_with_ioremap;
3045 memset(mgp->rx_done.entry, 0, bytes);
3046
5443e9ea
BG		 3047 myri10ge_select_firmware(mgp);
3048
0da34b6d
BG		 3049 status = myri10ge_load_firmware(mgp);
3050 if (status != 0) {
3051 dev_err(&pdev->dev, "failed to load firmware\n");
3052 goto abort_with_rx_done;
3053 }
3054
3055 status = myri10ge_reset(mgp);
3056 if (status != 0) {
3057 dev_err(&pdev->dev, "failed reset\n");
3058 goto abort_with_firmware;
3059 }
3060
0da34b6d
BG		 3061 pci_set_drvdata(pdev, mgp);
3062 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3063 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3064 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3065 myri10ge_initial_mtu = 68;
3066 netdev->mtu = myri10ge_initial_mtu;
3067 netdev->open = myri10ge_open;
3068 netdev->stop = myri10ge_close;
3069 netdev->hard_start_xmit = myri10ge_xmit;
3070 netdev->get_stats = myri10ge_get_stats;
3071 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 3072 netdev->change_mtu = myri10ge_change_mtu;
3073 netdev->set_multicast_list = myri10ge_set_multicast_list;
3074 netdev->set_mac_address = myri10ge_set_mac_address;
3075 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
3076 if (dac_enabled)
3077 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3078
21d05db1
BG		 3079 /* make sure we can get an irq, and that MSI can be
3080 * setup (if available). Also ensure netdev->irq
3081 * is set to correct value if MSI is enabled */
3082 status = myri10ge_request_irq(mgp);
3083 if (status != 0)
3084 goto abort_with_firmware;
3085 netdev->irq = pdev->irq;
3086 myri10ge_free_irq(mgp);
3087
0da34b6d
BG		 3088 /* Save configuration space to be restored if the
3089 * nic resets due to a parity error */
83f6e152 3090 pci_save_state(pdev);
0da34b6d
BG		 3091
3092 /* Setup the watchdog timer */
3093 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3094 (unsigned long)mgp);
3095
3096 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3097 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3098 status = register_netdev(netdev);
3099 if (status != 0) {
3100 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3101 goto abort_with_state;
0da34b6d 3102 }
21d05db1
BG		 3103 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3104 (mgp->msi_enabled ? "MSI" : "xPIC"),
3105 netdev->irq, mgp->tx.boundary, mgp->fw_name,
276e26c3 3106 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3107
3108 return 0;
3109
7adda30c 3110abort_with_state:
83f6e152 3111 pci_restore_state(pdev);
0da34b6d
BG		 3112
3113abort_with_firmware:
3114 myri10ge_dummy_rdma(mgp, 0);
3115
3116abort_with_rx_done:
3117 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3118 dma_free_coherent(&pdev->dev, bytes,
3119 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3120
3121abort_with_ioremap:
3122 iounmap(mgp->sram);
3123
3124abort_with_wc:
3125#ifdef CONFIG_MTRR
3126 if (mgp->mtrr >= 0)
3127 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3128#endif
b10c0668
BG		 3129 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3130 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 3131
3132abort_with_cmd:
b10c0668
BG		 3133 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3134 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3135
3136abort_with_netdev:
3137
3138 free_netdev(netdev);
3139 return status;
3140}
3141
3142/*
3143 * myri10ge_remove
3144 *
3145 * Does what is necessary to shutdown one Myrinet device. Called
3146 * once for each Myrinet card by the kernel when a module is
3147 * unloaded.
3148 */
3149static void myri10ge_remove(struct pci_dev *pdev)
3150{
3151 struct myri10ge_priv *mgp;
3152 struct net_device *netdev;
3153 size_t bytes;
3154
3155 mgp = pci_get_drvdata(pdev);
3156 if (mgp == NULL)
3157 return;
3158
3159 flush_scheduled_work();
3160 netdev = mgp->dev;
3161 unregister_netdev(netdev);
0da34b6d
BG		 3162
3163 myri10ge_dummy_rdma(mgp, 0);
3164
7adda30c 3165 /* avoid a memory leak */
83f6e152 3166 pci_restore_state(pdev);
7adda30c 3167
0da34b6d 3168 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3169 dma_free_coherent(&pdev->dev, bytes,
3170 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3171
3172 iounmap(mgp->sram);
3173
3174#ifdef CONFIG_MTRR
3175 if (mgp->mtrr >= 0)
3176 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3177#endif
b10c0668
BG		 3178 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3179 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3180
b10c0668
BG		 3181 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3182 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3183
3184 free_netdev(netdev);
3185 pci_set_drvdata(pdev, NULL);
3186}
3187
b10c0668 3188#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3189#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 3190
3191static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3192 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3193 {PCI_DEVICE
3194 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3195 {0},
3196};
3197
3198static struct pci_driver myri10ge_driver = {
3199 .name = "myri10ge",
3200 .probe = myri10ge_probe,
3201 .remove = myri10ge_remove,
3202 .id_table = myri10ge_pci_tbl,
3203#ifdef CONFIG_PM
3204 .suspend = myri10ge_suspend,
3205 .resume = myri10ge_resume,
3206#endif
3207};
3208
3209static __init int myri10ge_init_module(void)
3210{
3211 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3212 MYRI10GE_VERSION_STR);
3213 return pci_register_driver(&myri10ge_driver);
3214}
3215
3216module_init(myri10ge_init_module);
3217
3218static __exit void myri10ge_cleanup_module(void)
3219{
3220 pci_unregister_driver(&myri10ge_driver);
3221}
3222
3223module_exit(myri10ge_cleanup_module);
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