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myri10ge: fix stop/go ordering even more
[mirror_ubuntu-artful-kernel.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
981813d8 52#include <linux/dca.h>
0da34b6d
BG		 53#include <linux/ip.h>
54#include <linux/inet.h>
55#include <linux/in.h>
56#include <linux/ethtool.h>
57#include <linux/firmware.h>
58#include <linux/delay.h>
0da34b6d
BG		 59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
8c2f5fa5 78#define MYRI10GE_VERSION_STR "1.4.3-1.378"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
236bb5e6
BG		 105#define MYRI10GE_MAX_SLICES 32
106
0da34b6d 107struct myri10ge_rx_buffer_state {
dd50f336
BG		 108 struct page *page;
109 int page_offset;
0da34b6d
BG		 110 DECLARE_PCI_UNMAP_ADDR(bus)
111 DECLARE_PCI_UNMAP_LEN(len)
112};
113
114struct myri10ge_tx_buffer_state {
115 struct sk_buff *skb;
116 int last;
117 DECLARE_PCI_UNMAP_ADDR(bus)
118 DECLARE_PCI_UNMAP_LEN(len)
119};
120
121struct myri10ge_cmd {
122 u32 data0;
123 u32 data1;
124 u32 data2;
125};
126
127struct myri10ge_rx_buf {
128 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 129 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
130 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 131 struct page *page;
132 dma_addr_t bus;
133 int page_offset;
0da34b6d 134 int cnt;
dd50f336 135 int fill_cnt;
0da34b6d
BG		 136 int alloc_fail;
137 int mask; /* number of rx slots -1 */
dd50f336 138 int watchdog_needed;
0da34b6d
BG		 139};
140
141struct myri10ge_tx_buf {
142 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 143 __be32 __iomem *send_go; /* "go" doorbell ptr */
144 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 145 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
146 char *req_bytes;
147 struct myri10ge_tx_buffer_state *info;
148 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 149 int req ____cacheline_aligned; /* transmit slots submitted */
150 int pkt_start; /* packets started */
b53bef84
BG		 151 int stop_queue;
152 int linearized;
0da34b6d
BG		 153 int done ____cacheline_aligned; /* transmit slots completed */
154 int pkt_done; /* packets completed */
b53bef84 155 int wake_queue;
236bb5e6 156 int queue_active;
0da34b6d
BG		 157};
158
159struct myri10ge_rx_done {
160 struct mcp_slot *entry;
161 dma_addr_t bus;
162 int cnt;
163 int idx;
1e6e9342
AG		 164 struct net_lro_mgr lro_mgr;
165 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 166};
167
b53bef84
BG		 168struct myri10ge_slice_netstats {
169 unsigned long rx_packets;
170 unsigned long tx_packets;
171 unsigned long rx_bytes;
172 unsigned long tx_bytes;
173 unsigned long rx_dropped;
174 unsigned long tx_dropped;
175};
176
177struct myri10ge_slice_state {
0da34b6d
BG		 178 struct myri10ge_tx_buf tx; /* transmit ring */
179 struct myri10ge_rx_buf rx_small;
180 struct myri10ge_rx_buf rx_big;
181 struct myri10ge_rx_done rx_done;
b53bef84
BG		 182 struct net_device *dev;
183 struct napi_struct napi;
184 struct myri10ge_priv *mgp;
185 struct myri10ge_slice_netstats stats;
186 __be32 __iomem *irq_claim;
187 struct mcp_irq_data *fw_stats;
188 dma_addr_t fw_stats_bus;
189 int watchdog_tx_done;
190 int watchdog_tx_req;
5dd2d332 191#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 192 int cached_dca_tag;
193 int cpu;
194 __be32 __iomem *dca_tag;
195#endif
0dcffac1 196 char irq_desc[32];
b53bef84
BG		 197};
198
199struct myri10ge_priv {
0dcffac1 200 struct myri10ge_slice_state *ss;
b53bef84 201 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 202 int num_slices;
b53bef84
BG		 203 int running; /* running? */
204 int csum_flag; /* rx_csums? */
0da34b6d 205 int small_bytes;
dd50f336 206 int big_bytes;
fa0a90d9 207 int max_intr_slots;
0da34b6d
BG		 208 struct net_device *dev;
209 struct net_device_stats stats;
b53bef84 210 spinlock_t stats_lock;
0da34b6d
BG		 211 u8 __iomem *sram;
212 int sram_size;
213 unsigned long board_span;
214 unsigned long iomem_base;
40f6cff5 215 __be32 __iomem *irq_deassert;
0da34b6d
BG		 216 char *mac_addr_string;
217 struct mcp_cmd_response *cmd;
218 dma_addr_t cmd_bus;
0da34b6d
BG		 219 struct pci_dev *pdev;
220 int msi_enabled;
0dcffac1
BG		 221 int msix_enabled;
222 struct msix_entry *msix_vectors;
5dd2d332 223#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 224 int dca_enabled;
225#endif
66341fff 226 u32 link_state;
0da34b6d
BG		 227 unsigned int rdma_tags_available;
228 int intr_coal_delay;
40f6cff5 229 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 230 int mtrr;
276e26c3 231 int wc_enabled;
0da34b6d
BG		 232 int down_cnt;
233 wait_queue_head_t down_wq;
234 struct work_struct watchdog_work;
235 struct timer_list watchdog_timer;
0da34b6d 236 int watchdog_resets;
b53bef84 237 int watchdog_pause;
0da34b6d
BG		 238 int pause;
239 char *fw_name;
240 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 241 char *product_code_string;
0da34b6d 242 char fw_version[128];
9dc6f0e7
BG		 243 int fw_ver_major;
244 int fw_ver_minor;
245 int fw_ver_tiny;
246 int adopted_rx_filter_bug;
0da34b6d
BG		 247 u8 mac_addr[6]; /* eeprom mac address */
248 unsigned long serial_number;
249 int vendor_specific_offset;
85a7ea1b 250 int fw_multicast_support;
4f93fde0
BG		 251 unsigned long features;
252 u32 max_tso6;
0da34b6d
BG		 253 u32 read_dma;
254 u32 write_dma;
255 u32 read_write_dma;
c58ac5ca
BG		 256 u32 link_changes;
257 u32 msg_enable;
0da34b6d
BG		 258};
259
260static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
261static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 262static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
263static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
0da34b6d
BG		 264
265static char *myri10ge_fw_name = NULL;
266module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 267MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d
BG		 268
269static int myri10ge_ecrc_enable = 1;
270module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 271MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 272
0da34b6d
BG		 273static int myri10ge_small_bytes = -1; /* -1 == auto */
274module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 275MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 276
277static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 278module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 279MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 280
f761fae1 281static int myri10ge_intr_coal_delay = 75;
0da34b6d 282module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 283MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 284
285static int myri10ge_flow_control = 1;
286module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 287MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 288
289static int myri10ge_deassert_wait = 1;
290module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
291MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 292 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 293
294static int myri10ge_force_firmware = 0;
295module_param(myri10ge_force_firmware, int, S_IRUGO);
296MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 297 "Force firmware to assume aligned completions");
0da34b6d 298
0da34b6d
BG		 299static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
300module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 301MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 302
303static int myri10ge_napi_weight = 64;
304module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 305MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 306
307static int myri10ge_watchdog_timeout = 1;
308module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 309MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 310
311static int myri10ge_max_irq_loops = 1048576;
312module_param(myri10ge_max_irq_loops, int, S_IRUGO);
313MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 314 "Set stuck legacy IRQ detection threshold");
0da34b6d 315
c58ac5ca
BG		 316#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
317
318static int myri10ge_debug = -1; /* defaults above */
319module_param(myri10ge_debug, int, 0);
320MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
321
1e6e9342
AG		 322static int myri10ge_lro = 1;
323module_param(myri10ge_lro, int, S_IRUGO);
d1ce3a0f 324MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
1e6e9342
AG		 325
326static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
327module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 328MODULE_PARM_DESC(myri10ge_lro_max_pkts,
329 "Number of LRO packets to be aggregated");
1e6e9342 330
dd50f336
BG		 331static int myri10ge_fill_thresh = 256;
332module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 333MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 334
f181137f
BG		 335static int myri10ge_reset_recover = 1;
336
0dcffac1
BG		 337static int myri10ge_max_slices = 1;
338module_param(myri10ge_max_slices, int, S_IRUGO);
339MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
340
341static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
342module_param(myri10ge_rss_hash, int, S_IRUGO);
343MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
344
981813d8
BG		 345static int myri10ge_dca = 1;
346module_param(myri10ge_dca, int, S_IRUGO);
347MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
348
0da34b6d
BG		 349#define MYRI10GE_FW_OFFSET 1024*1024
350#define MYRI10GE_HIGHPART_TO_U32(X) \
351(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
352#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
353
354#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
355
2f76216f 356static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 357static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 358
6250223e 359static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 360{
6250223e 361 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 362}
363
0da34b6d
BG		 364static int
365myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
366 struct myri10ge_cmd *data, int atomic)
367{
368 struct mcp_cmd *buf;
369 char buf_bytes[sizeof(*buf) + 8];
370 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 371 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 372 u32 dma_low, dma_high, result, value;
373 int sleep_total = 0;
374
375 /* ensure buf is aligned to 8 bytes */
376 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
377
378 buf->data0 = htonl(data->data0);
379 buf->data1 = htonl(data->data1);
380 buf->data2 = htonl(data->data2);
381 buf->cmd = htonl(cmd);
382 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
383 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
384
385 buf->response_addr.low = htonl(dma_low);
386 buf->response_addr.high = htonl(dma_high);
40f6cff5 387 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 388 mb();
389 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
390
391 /* wait up to 15ms. Longest command is the DMA benchmark,
392 * which is capped at 5ms, but runs from a timeout handler
393 * that runs every 7.8ms. So a 15ms timeout leaves us with
394 * a 2.2ms margin
395 */
396 if (atomic) {
397 /* if atomic is set, do not sleep,
398 * and try to get the completion quickly
399 * (1ms will be enough for those commands) */
400 for (sleep_total = 0;
401 sleep_total < 1000
40f6cff5 402 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 403 sleep_total += 10) {
0da34b6d 404 udelay(10);
bd2db0cf
BG		 405 mb();
406 }
0da34b6d
BG		 407 } else {
408 /* use msleep for most command */
409 for (sleep_total = 0;
410 sleep_total < 15
40f6cff5 411 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 412 sleep_total++)
413 msleep(1);
414 }
415
416 result = ntohl(response->result);
417 value = ntohl(response->data);
418 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
419 if (result == 0) {
420 data->data0 = value;
421 return 0;
85a7ea1b
BG		 422 } else if (result == MXGEFW_CMD_UNKNOWN) {
423 return -ENOSYS;
5443e9ea
BG		 424 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
425 return -E2BIG;
236bb5e6
BG		 426 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
427 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
428 (data->
429 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
430 0) {
431 return -ERANGE;
0da34b6d
BG		 432 } else {
433 dev_err(&mgp->pdev->dev,
434 "command %d failed, result = %d\n",
435 cmd, result);
436 return -ENXIO;
437 }
438 }
439
440 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
441 cmd, result);
442 return -EAGAIN;
443}
444
445/*
446 * The eeprom strings on the lanaiX have the format
447 * SN=x\0
448 * MAC=x:x:x:x:x:x\0
449 * PT:ddd mmm xx xx:xx:xx xx\0
450 * PV:ddd mmm xx xx:xx:xx xx\0
451 */
452static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
453{
454 char *ptr, *limit;
455 int i;
456
457 ptr = mgp->eeprom_strings;
458 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
459
460 while (*ptr != '\0' && ptr < limit) {
461 if (memcmp(ptr, "MAC=", 4) == 0) {
462 ptr += 4;
463 mgp->mac_addr_string = ptr;
464 for (i = 0; i < 6; i++) {
465 if ((ptr + 2) > limit)
466 goto abort;
467 mgp->mac_addr[i] =
468 simple_strtoul(ptr, &ptr, 16);
469 ptr += 1;
470 }
471 }
c0bf8801
BG		 472 if (memcmp(ptr, "PC=", 3) == 0) {
473 ptr += 3;
474 mgp->product_code_string = ptr;
475 }
0da34b6d
BG		 476 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
477 ptr += 3;
478 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
479 }
480 while (ptr < limit && *ptr++) ;
481 }
482
483 return 0;
484
485abort:
486 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
487 return -ENXIO;
488}
489
490/*
491 * Enable or disable periodic RDMAs from the host to make certain
492 * chipsets resend dropped PCIe messages
493 */
494
495static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
496{
497 char __iomem *submit;
f8fd57c1 498 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 499 u32 dma_low, dma_high;
500 int i;
501
502 /* clear confirmation addr */
503 mgp->cmd->data = 0;
504 mb();
505
506 /* send a rdma command to the PCIe engine, and wait for the
507 * response in the confirmation address. The firmware should
508 * write a -1 there to indicate it is alive and well
509 */
510 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
511 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
512
513 buf[0] = htonl(dma_high); /* confirm addr MSW */
514 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 515 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 516 buf[3] = htonl(dma_high); /* dummy addr MSW */
517 buf[4] = htonl(dma_low); /* dummy addr LSW */
518 buf[5] = htonl(enable); /* enable? */
519
e700f9f4 520 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 521
522 myri10ge_pio_copy(submit, &buf, sizeof(buf));
523 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
524 msleep(1);
525 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
526 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
527 (enable ? "enable" : "disable"));
528}
529
530static int
531myri10ge_validate_firmware(struct myri10ge_priv *mgp,
532 struct mcp_gen_header *hdr)
533{
534 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 535
536 /* check firmware type */
537 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
538 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
539 return -EINVAL;
540 }
541
542 /* save firmware version for ethtool */
543 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
544
9dc6f0e7
BG		 545 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
546 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 547
9dc6f0e7
BG		 548 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
549 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 550 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
551 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
552 MXGEFW_VERSION_MINOR);
553 return -EINVAL;
554 }
555 return 0;
556}
557
558static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
559{
560 unsigned crc, reread_crc;
561 const struct firmware *fw;
562 struct device *dev = &mgp->pdev->dev;
b0d31d6b 563 unsigned char *fw_readback;
0da34b6d
BG		 564 struct mcp_gen_header *hdr;
565 size_t hdr_offset;
566 int status;
e454358a 567 unsigned i;
0da34b6d
BG		 568
569 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
570 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
571 mgp->fw_name);
572 status = -EINVAL;
573 goto abort_with_nothing;
574 }
575
576 /* check size */
577
578 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
579 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
580 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
581 status = -EINVAL;
582 goto abort_with_fw;
583 }
584
585 /* check id */
40f6cff5 586 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 587 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
588 dev_err(dev, "Bad firmware file\n");
589 status = -EINVAL;
590 goto abort_with_fw;
591 }
592 hdr = (void *)(fw->data + hdr_offset);
593
594 status = myri10ge_validate_firmware(mgp, hdr);
595 if (status != 0)
596 goto abort_with_fw;
597
598 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 599 for (i = 0; i < fw->size; i += 256) {
600 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
601 fw->data + i,
602 min(256U, (unsigned)(fw->size - i)));
603 mb();
604 readb(mgp->sram);
b10c0668 605 }
b0d31d6b
DW		 606 fw_readback = vmalloc(fw->size);
607 if (!fw_readback) {
608 status = -ENOMEM;
609 goto abort_with_fw;
610 }
0da34b6d 611 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 612 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
613 reread_crc = crc32(~0, fw_readback, fw->size);
614 vfree(fw_readback);
0da34b6d
BG		 615 if (crc != reread_crc) {
616 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
617 (unsigned)fw->size, reread_crc, crc);
618 status = -EIO;
619 goto abort_with_fw;
620 }
621 *size = (u32) fw->size;
622
623abort_with_fw:
624 release_firmware(fw);
625
626abort_with_nothing:
627 return status;
628}
629
630static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
631{
632 struct mcp_gen_header *hdr;
633 struct device *dev = &mgp->pdev->dev;
634 const size_t bytes = sizeof(struct mcp_gen_header);
635 size_t hdr_offset;
636 int status;
637
638 /* find running firmware header */
66341fff 639 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 640
641 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
642 dev_err(dev, "Running firmware has bad header offset (%d)\n",
643 (int)hdr_offset);
644 return -EIO;
645 }
646
647 /* copy header of running firmware from SRAM to host memory to
648 * validate firmware */
649 hdr = kmalloc(bytes, GFP_KERNEL);
650 if (hdr == NULL) {
651 dev_err(dev, "could not malloc firmware hdr\n");
652 return -ENOMEM;
653 }
654 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
655 status = myri10ge_validate_firmware(mgp, hdr);
656 kfree(hdr);
9dc6f0e7
BG		 657
658 /* check to see if adopted firmware has bug where adopting
659 * it will cause broadcasts to be filtered unless the NIC
660 * is kept in ALLMULTI mode */
661 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
662 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
663 mgp->adopted_rx_filter_bug = 1;
664 dev_warn(dev, "Adopting fw %d.%d.%d: "
665 "working around rx filter bug\n",
666 mgp->fw_ver_major, mgp->fw_ver_minor,
667 mgp->fw_ver_tiny);
668 }
0da34b6d
BG		 669 return status;
670}
671
0178ec3d 672static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 673{
674 struct myri10ge_cmd cmd;
675 int status;
676
677 /* probe for IPv6 TSO support */
678 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
679 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
680 &cmd, 0);
681 if (status == 0) {
682 mgp->max_tso6 = cmd.data0;
683 mgp->features |= NETIF_F_TSO6;
684 }
685
686 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
687 if (status != 0) {
688 dev_err(&mgp->pdev->dev,
689 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
690 return -ENXIO;
691 }
692
693 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
694
695 return 0;
696}
697
0dcffac1 698static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 699{
700 char __iomem *submit;
f8fd57c1 701 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 702 u32 dma_low, dma_high, size;
703 int status, i;
704
b10c0668 705 size = 0;
0da34b6d
BG		 706 status = myri10ge_load_hotplug_firmware(mgp, &size);
707 if (status) {
0dcffac1
BG		 708 if (!adopt)
709 return status;
0da34b6d
BG		 710 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
711
712 /* Do not attempt to adopt firmware if there
713 * was a bad crc */
714 if (status == -EIO)
715 return status;
716
717 status = myri10ge_adopt_running_firmware(mgp);
718 if (status != 0) {
719 dev_err(&mgp->pdev->dev,
720 "failed to adopt running firmware\n");
721 return status;
722 }
723 dev_info(&mgp->pdev->dev,
724 "Successfully adopted running firmware\n");
b53bef84 725 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 726 dev_warn(&mgp->pdev->dev,
727 "Using firmware currently running on NIC"
728 ". For optimal\n");
729 dev_warn(&mgp->pdev->dev,
730 "performance consider loading optimized "
731 "firmware\n");
732 dev_warn(&mgp->pdev->dev, "via hotplug\n");
733 }
734
735 mgp->fw_name = "adopted";
b53bef84 736 mgp->tx_boundary = 2048;
fa0a90d9
BG		 737 myri10ge_dummy_rdma(mgp, 1);
738 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 739 return status;
740 }
741
742 /* clear confirmation addr */
743 mgp->cmd->data = 0;
744 mb();
745
746 /* send a reload command to the bootstrap MCP, and wait for the
747 * response in the confirmation address. The firmware should
748 * write a -1 there to indicate it is alive and well
749 */
750 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
751 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
752
753 buf[0] = htonl(dma_high); /* confirm addr MSW */
754 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 755 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 756
757 /* FIX: All newest firmware should un-protect the bottom of
758 * the sram before handoff. However, the very first interfaces
759 * do not. Therefore the handoff copy must skip the first 8 bytes
760 */
761 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
762 buf[4] = htonl(size - 8); /* length of code */
763 buf[5] = htonl(8); /* where to copy to */
764 buf[6] = htonl(0); /* where to jump to */
765
e700f9f4 766 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 767
768 myri10ge_pio_copy(submit, &buf, sizeof(buf));
769 mb();
770 msleep(1);
771 mb();
772 i = 0;
d93ca2a4
BG		 773 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
774 msleep(1 << i);
0da34b6d
BG		 775 i++;
776 }
777 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
778 dev_err(&mgp->pdev->dev, "handoff failed\n");
779 return -ENXIO;
780 }
9a71db72 781 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 782 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 783
fa0a90d9 784 return status;
0da34b6d
BG		 785}
786
787static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
788{
789 struct myri10ge_cmd cmd;
790 int status;
791
792 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
793 | (addr[2] << 8) | addr[3]);
794
795 cmd.data1 = ((addr[4] << 8) | (addr[5]));
796
797 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
798 return status;
799}
800
801static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
802{
803 struct myri10ge_cmd cmd;
804 int status, ctl;
805
806 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
807 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
808
809 if (status) {
810 printk(KERN_ERR
811 "myri10ge: %s: Failed to set flow control mode\n",
812 mgp->dev->name);
813 return status;
814 }
815 mgp->pause = pause;
816 return 0;
817}
818
819static void
820myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
821{
822 struct myri10ge_cmd cmd;
823 int status, ctl;
824
825 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
826 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
827 if (status)
828 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
829 mgp->dev->name);
830}
831
0d6ac257 832static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 833{
834 struct myri10ge_cmd cmd;
835 int status;
0da34b6d 836 u32 len;
34fdccea
BG		 837 struct page *dmatest_page;
838 dma_addr_t dmatest_bus;
0d6ac257
BG		 839 char *test = " ";
840
841 dmatest_page = alloc_page(GFP_KERNEL);
842 if (!dmatest_page)
843 return -ENOMEM;
844 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
845 DMA_BIDIRECTIONAL);
846
847 /* Run a small DMA test.
848 * The magic multipliers to the length tell the firmware
849 * to do DMA read, write, or read+write tests. The
850 * results are returned in cmd.data0. The upper 16
851 * bits or the return is the number of transfers completed.
852 * The lower 16 bits is the time in 0.5us ticks that the
853 * transfers took to complete.
854 */
855
b53bef84 856 len = mgp->tx_boundary;
0d6ac257
BG		 857
858 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
859 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
860 cmd.data2 = len * 0x10000;
861 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
862 if (status != 0) {
863 test = "read";
864 goto abort;
865 }
866 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
867 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
868 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
869 cmd.data2 = len * 0x1;
870 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
871 if (status != 0) {
872 test = "write";
873 goto abort;
874 }
875 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
876
877 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
878 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
879 cmd.data2 = len * 0x10001;
880 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
881 if (status != 0) {
882 test = "read/write";
883 goto abort;
884 }
885 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
886 (cmd.data0 & 0xffff);
887
888abort:
889 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
890 put_page(dmatest_page);
891
892 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
893 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
894 test, status);
895
896 return status;
897}
898
899static int myri10ge_reset(struct myri10ge_priv *mgp)
900{
901 struct myri10ge_cmd cmd;
0dcffac1
BG		 902 struct myri10ge_slice_state *ss;
903 int i, status;
0d6ac257 904 size_t bytes;
5dd2d332 905#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 906 unsigned long dca_tag_off;
907#endif
0da34b6d
BG		 908
909 /* try to send a reset command to the card to see if it
910 * is alive */
911 memset(&cmd, 0, sizeof(cmd));
912 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
913 if (status != 0) {
914 dev_err(&mgp->pdev->dev, "failed reset\n");
915 return -ENXIO;
916 }
0d6ac257
BG		 917
918 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 919 /*
920 * Use non-ndis mcp_slot (eg, 4 bytes total,
921 * no toeplitz hash value returned. Older firmware will
922 * not understand this command, but will use the correct
923 * sized mcp_slot, so we ignore error returns
924 */
925 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
926 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 927
928 /* Now exchange information about interrupts */
929
0dcffac1 930 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 931 cmd.data0 = (u32) bytes;
932 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 933
934 /*
935 * Even though we already know how many slices are supported
936 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
937 * has magic side effects, and must be called after a reset.
938 * It must be called prior to calling any RSS related cmds,
939 * including assigning an interrupt queue for anything but
940 * slice 0. It must also be called *after*
941 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
942 * the firmware to compute offsets.
943 */
944
945 if (mgp->num_slices > 1) {
946
947 /* ask the maximum number of slices it supports */
948 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
949 &cmd, 0);
950 if (status != 0) {
951 dev_err(&mgp->pdev->dev,
952 "failed to get number of slices\n");
953 }
954
955 /*
956 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
957 * to setting up the interrupt queue DMA
958 */
959
960 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 961 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
962 if (mgp->dev->real_num_tx_queues > 1)
963 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 964 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
965 &cmd, 0);
236bb5e6
BG		 966
967 /* Firmware older than 1.4.32 only supports multiple
968 * RX queues, so if we get an error, first retry using a
969 * single TX queue before giving up */
970 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
971 mgp->dev->real_num_tx_queues = 1;
972 cmd.data0 = mgp->num_slices;
973 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
974 status = myri10ge_send_cmd(mgp,
975 MXGEFW_CMD_ENABLE_RSS_QUEUES,
976 &cmd, 0);
977 }
978
0dcffac1
BG		 979 if (status != 0) {
980 dev_err(&mgp->pdev->dev,
981 "failed to set number of slices\n");
982
983 return status;
984 }
985 }
986 for (i = 0; i < mgp->num_slices; i++) {
987 ss = &mgp->ss[i];
988 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
989 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
990 cmd.data2 = i;
991 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
992 &cmd, 0);
993 };
0da34b6d
BG		 994
995 status |=
996 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 997 for (i = 0; i < mgp->num_slices; i++) {
998 ss = &mgp->ss[i];
999 ss->irq_claim =
1000 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1001 }
df30a740
BG		 1002 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1003 &cmd, 0);
1004 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1005
0da34b6d
BG		 1006 status |= myri10ge_send_cmd
1007 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1008 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1009 if (status != 0) {
1010 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1011 return status;
1012 }
40f6cff5 1013 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1014
5dd2d332 1015#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1016 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1017 dca_tag_off = cmd.data0;
1018 for (i = 0; i < mgp->num_slices; i++) {
1019 ss = &mgp->ss[i];
1020 if (status == 0) {
1021 ss->dca_tag = (__iomem __be32 *)
1022 (mgp->sram + dca_tag_off + 4 * i);
1023 } else {
1024 ss->dca_tag = NULL;
1025 }
1026 }
1027#endif /* CONFIG_DCA */
1028
0da34b6d 1029 /* reset mcp/driver shared state back to 0 */
0dcffac1 1030
c58ac5ca 1031 mgp->link_changes = 0;
0dcffac1
BG		 1032 for (i = 0; i < mgp->num_slices; i++) {
1033 ss = &mgp->ss[i];
1034
1035 memset(ss->rx_done.entry, 0, bytes);
1036 ss->tx.req = 0;
1037 ss->tx.done = 0;
1038 ss->tx.pkt_start = 0;
1039 ss->tx.pkt_done = 0;
1040 ss->rx_big.cnt = 0;
1041 ss->rx_small.cnt = 0;
1042 ss->rx_done.idx = 0;
1043 ss->rx_done.cnt = 0;
1044 ss->tx.wake_queue = 0;
1045 ss->tx.stop_queue = 0;
1046 }
1047
0da34b6d 1048 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1049 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1050 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1051 return status;
1052}
1053
5dd2d332 1054#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1055static void
1056myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1057{
1058 ss->cpu = cpu;
1059 ss->cached_dca_tag = tag;
1060 put_be32(htonl(tag), ss->dca_tag);
1061}
1062
1063static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1064{
1065 int cpu = get_cpu();
1066 int tag;
1067
1068 if (cpu != ss->cpu) {
1069 tag = dca_get_tag(cpu);
1070 if (ss->cached_dca_tag != tag)
1071 myri10ge_write_dca(ss, cpu, tag);
1072 }
1073 put_cpu();
1074}
1075
1076static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1077{
1078 int err, i;
1079 struct pci_dev *pdev = mgp->pdev;
1080
1081 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1082 return;
1083 if (!myri10ge_dca) {
1084 dev_err(&pdev->dev, "dca disabled by administrator\n");
1085 return;
1086 }
1087 err = dca_add_requester(&pdev->dev);
1088 if (err) {
330554cb
BG		 1089 if (err != -ENODEV)
1090 dev_err(&pdev->dev,
1091 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1092 return;
1093 }
1094 mgp->dca_enabled = 1;
1095 for (i = 0; i < mgp->num_slices; i++)
1096 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1097}
1098
1099static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1100{
1101 struct pci_dev *pdev = mgp->pdev;
1102 int err;
1103
1104 if (!mgp->dca_enabled)
1105 return;
1106 mgp->dca_enabled = 0;
1107 err = dca_remove_requester(&pdev->dev);
1108}
1109
1110static int myri10ge_notify_dca_device(struct device *dev, void *data)
1111{
1112 struct myri10ge_priv *mgp;
1113 unsigned long event;
1114
1115 mgp = dev_get_drvdata(dev);
1116 event = *(unsigned long *)data;
1117
1118 if (event == DCA_PROVIDER_ADD)
1119 myri10ge_setup_dca(mgp);
1120 else if (event == DCA_PROVIDER_REMOVE)
1121 myri10ge_teardown_dca(mgp);
1122 return 0;
1123}
1124#endif /* CONFIG_DCA */
1125
0da34b6d
BG		 1126static inline void
1127myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1128 struct mcp_kreq_ether_recv *src)
1129{
40f6cff5 1130 __be32 low;
0da34b6d
BG		 1131
1132 low = src->addr_low;
40f6cff5 1133 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 1134 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1135 mb();
1136 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1137 mb();
1138 src->addr_low = low;
40f6cff5 1139 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1140 mb();
1141}
1142
40f6cff5 1143static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1144{
1145 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1146
40f6cff5 1147 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1148 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1149 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1150 skb->csum = hw_csum;
84fa7933 1151 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1152 }
1153}
1154
dd50f336
BG		 1155static inline void
1156myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1157 struct skb_frag_struct *rx_frags, int len, int hlen)
1158{
1159 struct skb_frag_struct *skb_frags;
1160
1161 skb->len = skb->data_len = len;
1162 skb->truesize = len + sizeof(struct sk_buff);
1163 /* attach the page(s) */
1164
1165 skb_frags = skb_shinfo(skb)->frags;
1166 while (len > 0) {
1167 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1168 len -= rx_frags->size;
1169 skb_frags++;
1170 rx_frags++;
1171 skb_shinfo(skb)->nr_frags++;
1172 }
1173
1174 /* pskb_may_pull is not available in irq context, but
1175 * skb_pull() (for ether_pad and eth_type_trans()) requires
1176 * the beginning of the packet in skb_headlen(), move it
1177 * manually */
27d7ff46 1178 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1179 skb_shinfo(skb)->frags[0].page_offset += hlen;
1180 skb_shinfo(skb)->frags[0].size -= hlen;
1181 skb->data_len -= hlen;
1182 skb->tail += hlen;
1183 skb_pull(skb, MXGEFW_PAD);
1184}
1185
1186static void
1187myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1188 int bytes, int watchdog)
1189{
1190 struct page *page;
1191 int idx;
1192
1193 if (unlikely(rx->watchdog_needed && !watchdog))
1194 return;
1195
1196 /* try to refill entire ring */
1197 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1198 idx = rx->fill_cnt & rx->mask;
ae8509b1 1199 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1200 /* we can use part of previous page */
1201 get_page(rx->page);
1202 } else {
1203 /* we need a new page */
1204 page =
1205 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1206 MYRI10GE_ALLOC_ORDER);
1207 if (unlikely(page == NULL)) {
1208 if (rx->fill_cnt - rx->cnt < 16)
1209 rx->watchdog_needed = 1;
1210 return;
1211 }
1212 rx->page = page;
1213 rx->page_offset = 0;
1214 rx->bus = pci_map_page(mgp->pdev, page, 0,
1215 MYRI10GE_ALLOC_SIZE,
1216 PCI_DMA_FROMDEVICE);
1217 }
1218 rx->info[idx].page = rx->page;
1219 rx->info[idx].page_offset = rx->page_offset;
1220 /* note that this is the address of the start of the
1221 * page */
1222 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1223 rx->shadow[idx].addr_low =
1224 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1225 rx->shadow[idx].addr_high =
1226 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1227
1228 /* start next packet on a cacheline boundary */
1229 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1230
1231#if MYRI10GE_ALLOC_SIZE > 4096
1232 /* don't cross a 4KB boundary */
1233 if ((rx->page_offset >> 12) !=
1234 ((rx->page_offset + bytes - 1) >> 12))
1235 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1236#endif
dd50f336
BG		 1237 rx->fill_cnt++;
1238
1239 /* copy 8 descriptors to the firmware at a time */
1240 if ((idx & 7) == 7) {
e454e7e2
BG		 1241 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1242 &rx->shadow[idx - 7]);
dd50f336
BG		 1243 }
1244 }
1245}
1246
1247static inline void
1248myri10ge_unmap_rx_page(struct pci_dev *pdev,
1249 struct myri10ge_rx_buffer_state *info, int bytes)
1250{
1251 /* unmap the recvd page if we're the only or last user of it */
1252 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1253 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1254 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1255 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1256 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1257 }
1258}
1259
1260#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1261 * page into an skb */
1262
1263static inline int
b53bef84 1264myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
52ea6fb3 1265 int bytes, int len, __wsum csum)
dd50f336 1266{
b53bef84 1267 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1268 struct sk_buff *skb;
1269 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1270 int i, idx, hlen, remainder;
1271 struct pci_dev *pdev = mgp->pdev;
1272 struct net_device *dev = mgp->dev;
1273 u8 *va;
1274
1275 len += MXGEFW_PAD;
1276 idx = rx->cnt & rx->mask;
1277 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1278 prefetch(va);
1279 /* Fill skb_frag_struct(s) with data from our receive */
1280 for (i = 0, remainder = len; remainder > 0; i++) {
1281 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1282 rx_frags[i].page = rx->info[idx].page;
1283 rx_frags[i].page_offset = rx->info[idx].page_offset;
1284 if (remainder < MYRI10GE_ALLOC_SIZE)
1285 rx_frags[i].size = remainder;
1286 else
1287 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1288 rx->cnt++;
1289 idx = rx->cnt & rx->mask;
1290 remainder -= MYRI10GE_ALLOC_SIZE;
1291 }
1292
1e6e9342
AG		 1293 if (mgp->csum_flag && myri10ge_lro) {
1294 rx_frags[0].page_offset += MXGEFW_PAD;
1295 rx_frags[0].size -= MXGEFW_PAD;
1296 len -= MXGEFW_PAD;
b53bef84 1297 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1298 /* opaque, will come back in get_frag_header */
0dcffac1 1299 len, len,
b53bef84 1300 (void *)(__force unsigned long)csum, csum);
0dcffac1 1301
1e6e9342
AG		 1302 return 1;
1303 }
1304
dd50f336
BG		 1305 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1306
e636b2ea
BG		 1307 /* allocate an skb to attach the page(s) to. This is done
1308 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1309
1310 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1311 if (unlikely(skb == NULL)) {
1312 mgp->stats.rx_dropped++;
1313 do {
1314 i--;
1315 put_page(rx_frags[i].page);
1316 } while (i != 0);
1317 return 0;
1318 }
1319
1320 /* Attach the pages to the skb, and trim off any padding */
1321 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1322 if (skb_shinfo(skb)->frags[0].size <= 0) {
1323 put_page(skb_shinfo(skb)->frags[0].page);
1324 skb_shinfo(skb)->nr_frags = 0;
1325 }
1326 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1327
1328 if (mgp->csum_flag) {
1329 if ((skb->protocol == htons(ETH_P_IP)) ||
1330 (skb->protocol == htons(ETH_P_IPV6))) {
1331 skb->csum = csum;
1332 skb->ip_summed = CHECKSUM_COMPLETE;
1333 } else
1334 myri10ge_vlan_ip_csum(skb, csum);
1335 }
1336 netif_receive_skb(skb);
1337 dev->last_rx = jiffies;
1338 return 1;
1339}
1340
b53bef84
BG		 1341static inline void
1342myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1343{
b53bef84
BG		 1344 struct pci_dev *pdev = ss->mgp->pdev;
1345 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1346 struct netdev_queue *dev_queue;
0da34b6d
BG		 1347 struct sk_buff *skb;
1348 int idx, len;
0da34b6d
BG		 1349
1350 while (tx->pkt_done != mcp_index) {
1351 idx = tx->done & tx->mask;
1352 skb = tx->info[idx].skb;
1353
1354 /* Mark as free */
1355 tx->info[idx].skb = NULL;
1356 if (tx->info[idx].last) {
1357 tx->pkt_done++;
1358 tx->info[idx].last = 0;
1359 }
1360 tx->done++;
1361 len = pci_unmap_len(&tx->info[idx], len);
1362 pci_unmap_len_set(&tx->info[idx], len, 0);
1363 if (skb) {
b53bef84
BG		 1364 ss->stats.tx_bytes += skb->len;
1365 ss->stats.tx_packets++;
0da34b6d
BG		 1366 dev_kfree_skb_irq(skb);
1367 if (len)
1368 pci_unmap_single(pdev,
1369 pci_unmap_addr(&tx->info[idx],
1370 bus), len,
1371 PCI_DMA_TODEVICE);
1372 } else {
1373 if (len)
1374 pci_unmap_page(pdev,
1375 pci_unmap_addr(&tx->info[idx],
1376 bus), len,
1377 PCI_DMA_TODEVICE);
1378 }
0da34b6d 1379 }
236bb5e6
BG		 1380
1381 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1382 /*
1383 * Make a minimal effort to prevent the NIC from polling an
1384 * idle tx queue. If we can't get the lock we leave the queue
1385 * active. In this case, either a thread was about to start
1386 * using the queue anyway, or we lost a race and the NIC will
1387 * waste some of its resources polling an inactive queue for a
1388 * while.
1389 */
1390
1391 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1392 __netif_tx_trylock(dev_queue)) {
1393 if (tx->req == tx->done) {
1394 tx->queue_active = 0;
1395 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1396 mb();
6824a105 1397 mmiowb();
236bb5e6
BG		 1398 }
1399 __netif_tx_unlock(dev_queue);
1400 }
1401
0da34b6d 1402 /* start the queue if we've stopped it */
236bb5e6 1403 if (netif_tx_queue_stopped(dev_queue)
0da34b6d 1404 && tx->req - tx->done < (tx->mask >> 1)) {
b53bef84 1405 tx->wake_queue++;
236bb5e6 1406 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1407 }
1408}
1409
b53bef84
BG		 1410static inline int
1411myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1412{
b53bef84
BG		 1413 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1414 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1415 unsigned long rx_bytes = 0;
1416 unsigned long rx_packets = 0;
1417 unsigned long rx_ok;
1418
1419 int idx = rx_done->idx;
1420 int cnt = rx_done->cnt;
bea3348e 1421 int work_done = 0;
0da34b6d 1422 u16 length;
40f6cff5 1423 __wsum checksum;
0da34b6d 1424
c956a240 1425 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1426 length = ntohs(rx_done->entry[idx].length);
1427 rx_done->entry[idx].length = 0;
40f6cff5 1428 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1429 if (length <= mgp->small_bytes)
b53bef84 1430 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
52ea6fb3
BG		 1431 mgp->small_bytes,
1432 length, checksum);
0da34b6d 1433 else
b53bef84 1434 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
52ea6fb3
BG		 1435 mgp->big_bytes,
1436 length, checksum);
0da34b6d
BG		 1437 rx_packets += rx_ok;
1438 rx_bytes += rx_ok * (unsigned long)length;
1439 cnt++;
014377a1 1440 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1441 work_done++;
0da34b6d
BG		 1442 }
1443 rx_done->idx = idx;
1444 rx_done->cnt = cnt;
b53bef84
BG		 1445 ss->stats.rx_packets += rx_packets;
1446 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1447
1e6e9342
AG		 1448 if (myri10ge_lro)
1449 lro_flush_all(&rx_done->lro_mgr);
1450
c7dab99b 1451 /* restock receive rings if needed */
b53bef84
BG		 1452 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1453 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1454 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1455 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1456 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1457
bea3348e 1458 return work_done;
0da34b6d
BG		 1459}
1460
1461static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1462{
0dcffac1 1463 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1464
1465 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1466 unsigned link_up = ntohl(stats->link_up);
1467 if (mgp->link_state != link_up) {
1468 mgp->link_state = link_up;
1469
1470 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1471 if (netif_msg_link(mgp))
1472 printk(KERN_INFO
1473 "myri10ge: %s: link up\n",
1474 mgp->dev->name);
0da34b6d 1475 netif_carrier_on(mgp->dev);
c58ac5ca 1476 mgp->link_changes++;
0da34b6d 1477 } else {
c58ac5ca
BG		 1478 if (netif_msg_link(mgp))
1479 printk(KERN_INFO
798a95db
BG		 1480 "myri10ge: %s: link %s\n",
1481 mgp->dev->name,
1482 (link_up == MXGEFW_LINK_MYRINET ?
1483 "mismatch (Myrinet detected)" :
1484 "down"));
0da34b6d 1485 netif_carrier_off(mgp->dev);
c58ac5ca 1486 mgp->link_changes++;
0da34b6d
BG		 1487 }
1488 }
1489 if (mgp->rdma_tags_available !=
b53bef84 1490 ntohl(stats->rdma_tags_available)) {
0da34b6d 1491 mgp->rdma_tags_available =
b53bef84 1492 ntohl(stats->rdma_tags_available);
0da34b6d
BG		 1493 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1494 "%d tags left\n", mgp->dev->name,
1495 mgp->rdma_tags_available);
1496 }
1497 mgp->down_cnt += stats->link_down;
1498 if (stats->link_down)
1499 wake_up(&mgp->down_wq);
1500 }
1501}
1502
bea3348e 1503static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1504{
b53bef84
BG		 1505 struct myri10ge_slice_state *ss =
1506 container_of(napi, struct myri10ge_slice_state, napi);
1507 struct net_device *netdev = ss->mgp->dev;
bea3348e 1508 int work_done;
0da34b6d 1509
5dd2d332 1510#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1511 if (ss->mgp->dca_enabled)
1512 myri10ge_update_dca(ss);
1513#endif
1514
0da34b6d 1515 /* process as many rx events as NAPI will allow */
b53bef84 1516 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1517
4ec24119 1518 if (work_done < budget) {
bea3348e 1519 netif_rx_complete(netdev, napi);
b53bef84 1520 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1521 }
bea3348e 1522 return work_done;
0da34b6d
BG		 1523}
1524
7d12e780 1525static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1526{
b53bef84
BG		 1527 struct myri10ge_slice_state *ss = arg;
1528 struct myri10ge_priv *mgp = ss->mgp;
1529 struct mcp_irq_data *stats = ss->fw_stats;
1530 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1531 u32 send_done_count;
1532 int i;
1533
236bb5e6
BG		 1534 /* an interrupt on a non-zero receive-only slice is implicitly
1535 * valid since MSI-X irqs are not shared */
1536 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
0dcffac1
BG		 1537 netif_rx_schedule(ss->dev, &ss->napi);
1538 return (IRQ_HANDLED);
1539 }
1540
0da34b6d
BG		 1541 /* make sure it is our IRQ, and that the DMA has finished */
1542 if (unlikely(!stats->valid))
1543 return (IRQ_NONE);
1544
1545 /* low bit indicates receives are present, so schedule
1546 * napi poll handler */
1547 if (stats->valid & 1)
b53bef84 1548 netif_rx_schedule(ss->dev, &ss->napi);
0da34b6d 1549
0dcffac1 1550 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1551 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1552 if (!myri10ge_deassert_wait)
1553 stats->valid = 0;
1554 mb();
1555 } else
1556 stats->valid = 0;
1557
1558 /* Wait for IRQ line to go low, if using INTx */
1559 i = 0;
1560 while (1) {
1561 i++;
1562 /* check for transmit completes and receives */
1563 send_done_count = ntohl(stats->send_done_count);
1564 if (send_done_count != tx->pkt_done)
b53bef84 1565 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d
BG		 1566 if (unlikely(i > myri10ge_max_irq_loops)) {
1567 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1568 mgp->dev->name);
1569 stats->valid = 0;
1570 schedule_work(&mgp->watchdog_work);
1571 }
1572 if (likely(stats->valid == 0))
1573 break;
1574 cpu_relax();
1575 barrier();
1576 }
1577
236bb5e6
BG		 1578 /* Only slice 0 updates stats */
1579 if (ss == mgp->ss)
1580 myri10ge_check_statblock(mgp);
0da34b6d 1581
b53bef84 1582 put_be32(htonl(3), ss->irq_claim + 1);
0da34b6d
BG		 1583 return (IRQ_HANDLED);
1584}
1585
1586static int
1587myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1588{
c0bf8801
BG		 1589 struct myri10ge_priv *mgp = netdev_priv(netdev);
1590 char *ptr;
1591 int i;
1592
0da34b6d
BG		 1593 cmd->autoneg = AUTONEG_DISABLE;
1594 cmd->speed = SPEED_10000;
1595 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1596
1597 /*
1598 * parse the product code to deterimine the interface type
1599 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1600 * after the 3rd dash in the driver's cached copy of the
1601 * EEPROM's product code string.
1602 */
1603 ptr = mgp->product_code_string;
1604 if (ptr == NULL) {
1605 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
99f5f87e 1606 netdev->name);
c0bf8801
BG		 1607 return 0;
1608 }
1609 for (i = 0; i < 3; i++, ptr++) {
1610 ptr = strchr(ptr, '-');
1611 if (ptr == NULL) {
1612 printk(KERN_ERR "myri10ge: %s: Invalid product "
1613 "code %s\n", netdev->name,
1614 mgp->product_code_string);
1615 return 0;
1616 }
1617 }
1618 if (*ptr == 'R' || *ptr == 'Q') {
1619 /* We've found either an XFP or quad ribbon fiber */
1620 cmd->port = PORT_FIBRE;
1621 }
0da34b6d
BG		 1622 return 0;
1623}
1624
1625static void
1626myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1627{
1628 struct myri10ge_priv *mgp = netdev_priv(netdev);
1629
1630 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1631 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1632 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1633 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1634}
1635
1636static int
1637myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1638{
1639 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1640
0da34b6d
BG		 1641 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1642 return 0;
1643}
1644
1645static int
1646myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1647{
1648 struct myri10ge_priv *mgp = netdev_priv(netdev);
1649
1650 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1651 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1652 return 0;
1653}
1654
1655static void
1656myri10ge_get_pauseparam(struct net_device *netdev,
1657 struct ethtool_pauseparam *pause)
1658{
1659 struct myri10ge_priv *mgp = netdev_priv(netdev);
1660
1661 pause->autoneg = 0;
1662 pause->rx_pause = mgp->pause;
1663 pause->tx_pause = mgp->pause;
1664}
1665
1666static int
1667myri10ge_set_pauseparam(struct net_device *netdev,
1668 struct ethtool_pauseparam *pause)
1669{
1670 struct myri10ge_priv *mgp = netdev_priv(netdev);
1671
1672 if (pause->tx_pause != mgp->pause)
1673 return myri10ge_change_pause(mgp, pause->tx_pause);
1674 if (pause->rx_pause != mgp->pause)
1675 return myri10ge_change_pause(mgp, pause->tx_pause);
1676 if (pause->autoneg != 0)
1677 return -EINVAL;
1678 return 0;
1679}
1680
1681static void
1682myri10ge_get_ringparam(struct net_device *netdev,
1683 struct ethtool_ringparam *ring)
1684{
1685 struct myri10ge_priv *mgp = netdev_priv(netdev);
1686
0dcffac1
BG		 1687 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1688 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1689 ring->rx_jumbo_max_pending = 0;
0dcffac1 1690 ring->tx_max_pending = mgp->ss[0].rx_small.mask + 1;
0da34b6d
BG		 1691 ring->rx_mini_pending = ring->rx_mini_max_pending;
1692 ring->rx_pending = ring->rx_max_pending;
1693 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1694 ring->tx_pending = ring->tx_max_pending;
1695}
1696
1697static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1698{
1699 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1700
0da34b6d
BG		 1701 if (mgp->csum_flag)
1702 return 1;
1703 else
1704 return 0;
1705}
1706
1707static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1708{
1709 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1710
0da34b6d
BG		 1711 if (csum_enabled)
1712 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1713 else
1714 mgp->csum_flag = 0;
1715 return 0;
1716}
1717
4f93fde0
BG		 1718static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1719{
1720 struct myri10ge_priv *mgp = netdev_priv(netdev);
1721 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1722
1723 if (tso_enabled)
1724 netdev->features |= flags;
1725 else
1726 netdev->features &= ~flags;
1727 return 0;
1728}
1729
b53bef84 1730static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1731 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1732 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1733 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1734 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1735 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1736 "tx_heartbeat_errors", "tx_window_errors",
1737 /* device-specific stats */
0dcffac1 1738 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1739 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1740 "serial_number", "watchdog_resets",
5dd2d332 1741#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1742 "dca_capable_firmware", "dca_device_present",
981813d8 1743#endif
c58ac5ca 1744 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1745 "dropped_link_error_or_filtered",
1746 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1747 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1748 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1749 "dropped_no_big_buffer"
1750};
1751
1752static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1753 "----------- slice ---------",
1754 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1755 "rx_small_cnt", "rx_big_cnt",
1756 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1757 "LRO flushed",
1e6e9342 1758 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1759};
1760
1761#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1762#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1763#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1764
1765static void
1766myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1767{
0dcffac1
BG		 1768 struct myri10ge_priv *mgp = netdev_priv(netdev);
1769 int i;
1770
0da34b6d
BG		 1771 switch (stringset) {
1772 case ETH_SS_STATS:
b53bef84
BG		 1773 memcpy(data, *myri10ge_gstrings_main_stats,
1774 sizeof(myri10ge_gstrings_main_stats));
1775 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1776 for (i = 0; i < mgp->num_slices; i++) {
1777 memcpy(data, *myri10ge_gstrings_slice_stats,
1778 sizeof(myri10ge_gstrings_slice_stats));
1779 data += sizeof(myri10ge_gstrings_slice_stats);
1780 }
0da34b6d
BG		 1781 break;
1782 }
1783}
1784
b9f2c044 1785static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1786{
0dcffac1
BG		 1787 struct myri10ge_priv *mgp = netdev_priv(netdev);
1788
b9f2c044
JG		 1789 switch (sset) {
1790 case ETH_SS_STATS:
0dcffac1
BG		 1791 return MYRI10GE_MAIN_STATS_LEN +
1792 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1793 default:
1794 return -EOPNOTSUPP;
1795 }
0da34b6d
BG		 1796}
1797
1798static void
1799myri10ge_get_ethtool_stats(struct net_device *netdev,
1800 struct ethtool_stats *stats, u64 * data)
1801{
1802 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1803 struct myri10ge_slice_state *ss;
0dcffac1 1804 int slice;
0da34b6d
BG		 1805 int i;
1806
1807 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1808 data[i] = ((unsigned long *)&mgp->stats)[i];
1809
b53bef84 1810 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1811 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1812 data[i++] = (unsigned int)mgp->pdev->irq;
1813 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1814 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1815 data[i++] = (unsigned int)mgp->read_dma;
1816 data[i++] = (unsigned int)mgp->write_dma;
1817 data[i++] = (unsigned int)mgp->read_write_dma;
1818 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1819 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1820#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1821 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1822 data[i++] = (unsigned int)(mgp->dca_enabled);
1823#endif
c58ac5ca 1824 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1825
1826 /* firmware stats are useful only in the first slice */
0dcffac1 1827 ss = &mgp->ss[0];
b53bef84
BG		 1828 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1829 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1830 data[i++] =
b53bef84
BG		 1831 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1832 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1833 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1834 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1835 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1836 data[i++] =
b53bef84
BG		 1837 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1838 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1839 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1840 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1841 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1842
0dcffac1
BG		 1843 for (slice = 0; slice < mgp->num_slices; slice++) {
1844 ss = &mgp->ss[slice];
1845 data[i++] = slice;
1846 data[i++] = (unsigned int)ss->tx.pkt_start;
1847 data[i++] = (unsigned int)ss->tx.pkt_done;
1848 data[i++] = (unsigned int)ss->tx.req;
1849 data[i++] = (unsigned int)ss->tx.done;
1850 data[i++] = (unsigned int)ss->rx_small.cnt;
1851 data[i++] = (unsigned int)ss->rx_big.cnt;
1852 data[i++] = (unsigned int)ss->tx.wake_queue;
1853 data[i++] = (unsigned int)ss->tx.stop_queue;
1854 data[i++] = (unsigned int)ss->tx.linearized;
1855 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1856 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1857 if (ss->rx_done.lro_mgr.stats.flushed)
1858 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1859 ss->rx_done.lro_mgr.stats.flushed;
1860 else
1861 data[i++] = 0;
1862 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1863 }
0da34b6d
BG		 1864}
1865
c58ac5ca
BG		 1866static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1867{
1868 struct myri10ge_priv *mgp = netdev_priv(netdev);
1869 mgp->msg_enable = value;
1870}
1871
1872static u32 myri10ge_get_msglevel(struct net_device *netdev)
1873{
1874 struct myri10ge_priv *mgp = netdev_priv(netdev);
1875 return mgp->msg_enable;
1876}
1877
7282d491 1878static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1879 .get_settings = myri10ge_get_settings,
1880 .get_drvinfo = myri10ge_get_drvinfo,
1881 .get_coalesce = myri10ge_get_coalesce,
1882 .set_coalesce = myri10ge_set_coalesce,
1883 .get_pauseparam = myri10ge_get_pauseparam,
1884 .set_pauseparam = myri10ge_set_pauseparam,
1885 .get_ringparam = myri10ge_get_ringparam,
1886 .get_rx_csum = myri10ge_get_rx_csum,
1887 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1888 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1889 .set_sg = ethtool_op_set_sg,
4f93fde0 1890 .set_tso = myri10ge_set_tso,
6ffdd071 1891 .get_link = ethtool_op_get_link,
0da34b6d 1892 .get_strings = myri10ge_get_strings,
b9f2c044 1893 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1894 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1895 .set_msglevel = myri10ge_set_msglevel,
1896 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1897};
1898
b53bef84 1899static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1900{
b53bef84 1901 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1902 struct myri10ge_cmd cmd;
b53bef84 1903 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1904 int tx_ring_size, rx_ring_size;
1905 int tx_ring_entries, rx_ring_entries;
0dcffac1 1906 int i, slice, status;
0da34b6d
BG		 1907 size_t bytes;
1908
0da34b6d 1909 /* get ring sizes */
0dcffac1
BG		 1910 slice = ss - mgp->ss;
1911 cmd.data0 = slice;
0da34b6d
BG		 1912 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1913 tx_ring_size = cmd.data0;
0dcffac1 1914 cmd.data0 = slice;
0da34b6d 1915 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1916 if (status != 0)
1917 return status;
0da34b6d
BG		 1918 rx_ring_size = cmd.data0;
1919
1920 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1921 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1922 ss->tx.mask = tx_ring_entries - 1;
1923 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1924
355c7265
BG		 1925 status = -ENOMEM;
1926
0da34b6d
BG		 1927 /* allocate the host shadow rings */
1928
1929 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1930 * sizeof(*ss->tx.req_list);
1931 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1932 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1933 goto abort_with_nothing;
1934
1935 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1936 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1937 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 1938 ss->tx.queue_active = 0;
0da34b6d 1939
b53bef84
BG		 1940 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1941 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1942 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1943 goto abort_with_tx_req_bytes;
1944
b53bef84
BG		 1945 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1946 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1947 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1948 goto abort_with_rx_small_shadow;
1949
1950 /* allocate the host info rings */
1951
b53bef84
BG		 1952 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1953 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1954 if (ss->tx.info == NULL)
0da34b6d
BG		 1955 goto abort_with_rx_big_shadow;
1956
b53bef84
BG		 1957 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1958 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1959 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1960 goto abort_with_tx_info;
1961
b53bef84
BG		 1962 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1963 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1964 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1965 goto abort_with_rx_small_info;
1966
1967 /* Fill the receive rings */
b53bef84
BG		 1968 ss->rx_big.cnt = 0;
1969 ss->rx_small.cnt = 0;
1970 ss->rx_big.fill_cnt = 0;
1971 ss->rx_small.fill_cnt = 0;
1972 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1973 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1974 ss->rx_small.watchdog_needed = 0;
1975 ss->rx_big.watchdog_needed = 0;
1976 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1977 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1978
b53bef84 1979 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
0dcffac1
BG		 1980 printk(KERN_ERR
1981 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1982 dev->name, slice, ss->rx_small.fill_cnt);
c7dab99b 1983 goto abort_with_rx_small_ring;
0da34b6d
BG		 1984 }
1985
b53bef84
BG		 1986 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1987 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
0dcffac1
BG		 1988 printk(KERN_ERR
1989 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
1990 dev->name, slice, ss->rx_big.fill_cnt);
c7dab99b 1991 goto abort_with_rx_big_ring;
0da34b6d
BG		 1992 }
1993
1994 return 0;
1995
1996abort_with_rx_big_ring:
b53bef84
BG		 1997 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1998 int idx = i & ss->rx_big.mask;
1999 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2000 mgp->big_bytes);
b53bef84 2001 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2002 }
2003
2004abort_with_rx_small_ring:
b53bef84
BG		 2005 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2006 int idx = i & ss->rx_small.mask;
2007 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2008 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2009 put_page(ss->rx_small.info[idx].page);
0da34b6d 2010 }
c7dab99b 2011
b53bef84 2012 kfree(ss->rx_big.info);
0da34b6d
BG		 2013
2014abort_with_rx_small_info:
b53bef84 2015 kfree(ss->rx_small.info);
0da34b6d
BG		 2016
2017abort_with_tx_info:
b53bef84 2018 kfree(ss->tx.info);
0da34b6d
BG		 2019
2020abort_with_rx_big_shadow:
b53bef84 2021 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2022
2023abort_with_rx_small_shadow:
b53bef84 2024 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2025
2026abort_with_tx_req_bytes:
b53bef84
BG		 2027 kfree(ss->tx.req_bytes);
2028 ss->tx.req_bytes = NULL;
2029 ss->tx.req_list = NULL;
0da34b6d
BG		 2030
2031abort_with_nothing:
2032 return status;
2033}
2034
b53bef84 2035static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2036{
b53bef84 2037 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2038 struct sk_buff *skb;
2039 struct myri10ge_tx_buf *tx;
2040 int i, len, idx;
2041
0dcffac1
BG		 2042 /* If not allocated, skip it */
2043 if (ss->tx.req_list == NULL)
2044 return;
2045
b53bef84
BG		 2046 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2047 idx = i & ss->rx_big.mask;
2048 if (i == ss->rx_big.fill_cnt - 1)
2049 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2050 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2051 mgp->big_bytes);
b53bef84 2052 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2053 }
2054
b53bef84
BG		 2055 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2056 idx = i & ss->rx_small.mask;
2057 if (i == ss->rx_small.fill_cnt - 1)
2058 ss->rx_small.info[idx].page_offset =
c7dab99b 2059 MYRI10GE_ALLOC_SIZE;
b53bef84 2060 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2061 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2062 put_page(ss->rx_small.info[idx].page);
c7dab99b 2063 }
b53bef84 2064 tx = &ss->tx;
0da34b6d
BG		 2065 while (tx->done != tx->req) {
2066 idx = tx->done & tx->mask;
2067 skb = tx->info[idx].skb;
2068
2069 /* Mark as free */
2070 tx->info[idx].skb = NULL;
2071 tx->done++;
2072 len = pci_unmap_len(&tx->info[idx], len);
2073 pci_unmap_len_set(&tx->info[idx], len, 0);
2074 if (skb) {
b53bef84 2075 ss->stats.tx_dropped++;
0da34b6d
BG		 2076 dev_kfree_skb_any(skb);
2077 if (len)
2078 pci_unmap_single(mgp->pdev,
2079 pci_unmap_addr(&tx->info[idx],
2080 bus), len,
2081 PCI_DMA_TODEVICE);
2082 } else {
2083 if (len)
2084 pci_unmap_page(mgp->pdev,
2085 pci_unmap_addr(&tx->info[idx],
2086 bus), len,
2087 PCI_DMA_TODEVICE);
2088 }
2089 }
b53bef84 2090 kfree(ss->rx_big.info);
0da34b6d 2091
b53bef84 2092 kfree(ss->rx_small.info);
0da34b6d 2093
b53bef84 2094 kfree(ss->tx.info);
0da34b6d 2095
b53bef84 2096 kfree(ss->rx_big.shadow);
0da34b6d 2097
b53bef84 2098 kfree(ss->rx_small.shadow);
0da34b6d 2099
b53bef84
BG		 2100 kfree(ss->tx.req_bytes);
2101 ss->tx.req_bytes = NULL;
2102 ss->tx.req_list = NULL;
0da34b6d
BG		 2103}
2104
df30a740
BG		 2105static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2106{
2107 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2108 struct myri10ge_slice_state *ss;
2109 struct net_device *netdev = mgp->dev;
2110 int i;
df30a740
BG		 2111 int status;
2112
0dcffac1
BG		 2113 mgp->msi_enabled = 0;
2114 mgp->msix_enabled = 0;
2115 status = 0;
df30a740 2116 if (myri10ge_msi) {
0dcffac1
BG		 2117 if (mgp->num_slices > 1) {
2118 status =
2119 pci_enable_msix(pdev, mgp->msix_vectors,
2120 mgp->num_slices);
2121 if (status == 0) {
2122 mgp->msix_enabled = 1;
2123 } else {
2124 dev_err(&pdev->dev,
2125 "Error %d setting up MSI-X\n", status);
2126 return status;
2127 }
2128 }
2129 if (mgp->msix_enabled == 0) {
2130 status = pci_enable_msi(pdev);
2131 if (status != 0) {
2132 dev_err(&pdev->dev,
2133 "Error %d setting up MSI; falling back to xPIC\n",
2134 status);
2135 } else {
2136 mgp->msi_enabled = 1;
2137 }
2138 }
df30a740 2139 }
0dcffac1
BG		 2140 if (mgp->msix_enabled) {
2141 for (i = 0; i < mgp->num_slices; i++) {
2142 ss = &mgp->ss[i];
2143 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2144 "%s:slice-%d", netdev->name, i);
2145 status = request_irq(mgp->msix_vectors[i].vector,
2146 myri10ge_intr, 0, ss->irq_desc,
2147 ss);
2148 if (status != 0) {
2149 dev_err(&pdev->dev,
2150 "slice %d failed to allocate IRQ\n", i);
2151 i--;
2152 while (i >= 0) {
2153 free_irq(mgp->msix_vectors[i].vector,
2154 &mgp->ss[i]);
2155 i--;
2156 }
2157 pci_disable_msix(pdev);
2158 return status;
2159 }
2160 }
2161 } else {
2162 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2163 mgp->dev->name, &mgp->ss[0]);
2164 if (status != 0) {
2165 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2166 if (mgp->msi_enabled)
2167 pci_disable_msi(pdev);
2168 }
df30a740
BG		 2169 }
2170 return status;
2171}
2172
2173static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2174{
2175 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2176 int i;
df30a740 2177
0dcffac1
BG		 2178 if (mgp->msix_enabled) {
2179 for (i = 0; i < mgp->num_slices; i++)
2180 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2181 } else {
2182 free_irq(pdev->irq, &mgp->ss[0]);
2183 }
df30a740
BG		 2184 if (mgp->msi_enabled)
2185 pci_disable_msi(pdev);
0dcffac1
BG		 2186 if (mgp->msix_enabled)
2187 pci_disable_msix(pdev);
df30a740
BG		 2188}
2189
1e6e9342
AG		 2190static int
2191myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2192 void **ip_hdr, void **tcpudp_hdr,
2193 u64 * hdr_flags, void *priv)
2194{
2195 struct ethhdr *eh;
2196 struct vlan_ethhdr *veh;
2197 struct iphdr *iph;
2198 u8 *va = page_address(frag->page) + frag->page_offset;
2199 unsigned long ll_hlen;
66341fff
AV		 2200 /* passed opaque through lro_receive_frags() */
2201 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2202
2203 /* find the mac header, aborting if not IPv4 */
2204
2205 eh = (struct ethhdr *)va;
2206 *mac_hdr = eh;
2207 ll_hlen = ETH_HLEN;
2208 if (eh->h_proto != htons(ETH_P_IP)) {
2209 if (eh->h_proto == htons(ETH_P_8021Q)) {
2210 veh = (struct vlan_ethhdr *)va;
2211 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2212 return -1;
2213
2214 ll_hlen += VLAN_HLEN;
2215
2216 /*
2217 * HW checksum starts ETH_HLEN bytes into
2218 * frame, so we must subtract off the VLAN
2219 * header's checksum before csum can be used
2220 */
2221 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2222 VLAN_HLEN, 0));
2223 } else {
2224 return -1;
2225 }
2226 }
2227 *hdr_flags = LRO_IPV4;
2228
2229 iph = (struct iphdr *)(va + ll_hlen);
2230 *ip_hdr = iph;
2231 if (iph->protocol != IPPROTO_TCP)
2232 return -1;
2233 *hdr_flags |= LRO_TCP;
2234 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2235
2236 /* verify the IP checksum */
2237 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2238 return -1;
2239
2240 /* verify the checksum */
2241 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2242 ntohs(iph->tot_len) - (iph->ihl << 2),
2243 IPPROTO_TCP, csum)))
2244 return -1;
2245
2246 return 0;
2247}
2248
77929732
BG		 2249static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2250{
2251 struct myri10ge_cmd cmd;
2252 struct myri10ge_slice_state *ss;
2253 int status;
2254
2255 ss = &mgp->ss[slice];
236bb5e6
BG		 2256 status = 0;
2257 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2258 cmd.data0 = slice;
2259 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2260 &cmd, 0);
2261 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2262 (mgp->sram + cmd.data0);
2263 }
77929732
BG		 2264 cmd.data0 = slice;
2265 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2266 &cmd, 0);
2267 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2268 (mgp->sram + cmd.data0);
2269
2270 cmd.data0 = slice;
2271 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2272 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2273 (mgp->sram + cmd.data0);
2274
236bb5e6
BG		 2275 ss->tx.send_go = (__iomem __be32 *)
2276 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2277 ss->tx.send_stop = (__iomem __be32 *)
2278 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2279 return status;
2280
2281}
2282
2283static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2284{
2285 struct myri10ge_cmd cmd;
2286 struct myri10ge_slice_state *ss;
2287 int status;
2288
2289 ss = &mgp->ss[slice];
2290 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2291 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2292 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2293 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2294 if (status == -ENOSYS) {
2295 dma_addr_t bus = ss->fw_stats_bus;
2296 if (slice != 0)
2297 return -EINVAL;
2298 bus += offsetof(struct mcp_irq_data, send_done_count);
2299 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2300 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2301 status = myri10ge_send_cmd(mgp,
2302 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2303 &cmd, 0);
2304 /* Firmware cannot support multicast without STATS_DMA_V2 */
2305 mgp->fw_multicast_support = 0;
2306 } else {
2307 mgp->fw_multicast_support = 1;
2308 }
2309 return 0;
2310}
77929732 2311
0da34b6d
BG		 2312static int myri10ge_open(struct net_device *dev)
2313{
0dcffac1 2314 struct myri10ge_slice_state *ss;
b53bef84 2315 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2316 struct myri10ge_cmd cmd;
0dcffac1
BG		 2317 int i, status, big_pow2, slice;
2318 u8 *itable;
1e6e9342 2319 struct net_lro_mgr *lro_mgr;
0da34b6d 2320
0da34b6d
BG		 2321 if (mgp->running != MYRI10GE_ETH_STOPPED)
2322 return -EBUSY;
2323
2324 mgp->running = MYRI10GE_ETH_STARTING;
2325 status = myri10ge_reset(mgp);
2326 if (status != 0) {
2327 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 2328 goto abort_with_nothing;
0da34b6d
BG		 2329 }
2330
0dcffac1
BG		 2331 if (mgp->num_slices > 1) {
2332 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2333 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2334 if (mgp->dev->real_num_tx_queues > 1)
2335 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2336 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2337 &cmd, 0);
2338 if (status != 0) {
2339 printk(KERN_ERR
2340 "myri10ge: %s: failed to set number of slices\n",
2341 dev->name);
2342 goto abort_with_nothing;
2343 }
2344 /* setup the indirection table */
2345 cmd.data0 = mgp->num_slices;
2346 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2347 &cmd, 0);
2348
2349 status |= myri10ge_send_cmd(mgp,
2350 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2351 &cmd, 0);
2352 if (status != 0) {
2353 printk(KERN_ERR
2354 "myri10ge: %s: failed to setup rss tables\n",
2355 dev->name);
236bb5e6 2356 goto abort_with_nothing;
0dcffac1
BG		 2357 }
2358
2359 /* just enable an identity mapping */
2360 itable = mgp->sram + cmd.data0;
2361 for (i = 0; i < mgp->num_slices; i++)
2362 __raw_writeb(i, &itable[i]);
2363
2364 cmd.data0 = 1;
2365 cmd.data1 = myri10ge_rss_hash;
2366 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2367 &cmd, 0);
2368 if (status != 0) {
2369 printk(KERN_ERR
2370 "myri10ge: %s: failed to enable slices\n",
2371 dev->name);
2372 goto abort_with_nothing;
2373 }
2374 }
2375
df30a740
BG		 2376 status = myri10ge_request_irq(mgp);
2377 if (status != 0)
2378 goto abort_with_nothing;
2379
0da34b6d
BG		 2380 /* decide what small buffer size to use. For good TCP rx
2381 * performance, it is important to not receive 1514 byte
2382 * frames into jumbo buffers, as it confuses the socket buffer
2383 * accounting code, leading to drops and erratic performance.
2384 */
2385
2386 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2387 /* enough for a TCP header */
2388 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2389 ? (128 - MXGEFW_PAD)
2390 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2391 else
de3c4507
BG		 2392 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2393 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2394
2395 /* Override the small buffer size? */
2396 if (myri10ge_small_bytes > 0)
2397 mgp->small_bytes = myri10ge_small_bytes;
2398
0da34b6d
BG		 2399 /* Firmware needs the big buff size as a power of 2. Lie and
2400 * tell him the buffer is larger, because we only use 1
2401 * buffer/pkt, and the mtu will prevent overruns.
2402 */
13348bee 2403 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2404 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2405 while (!is_power_of_2(big_pow2))
c7dab99b 2406 big_pow2++;
13348bee 2407 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2408 } else {
2409 big_pow2 = MYRI10GE_ALLOC_SIZE;
2410 mgp->big_bytes = big_pow2;
2411 }
2412
0dcffac1
BG		 2413 /* setup the per-slice data structures */
2414 for (slice = 0; slice < mgp->num_slices; slice++) {
2415 ss = &mgp->ss[slice];
2416
2417 status = myri10ge_get_txrx(mgp, slice);
2418 if (status != 0) {
2419 printk(KERN_ERR
2420 "myri10ge: %s: failed to get ring sizes or locations\n",
2421 dev->name);
2422 goto abort_with_rings;
2423 }
2424 status = myri10ge_allocate_rings(ss);
2425 if (status != 0)
2426 goto abort_with_rings;
236bb5e6
BG		 2427
2428 /* only firmware which supports multiple TX queues
2429 * supports setting up the tx stats on non-zero
2430 * slices */
2431 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2432 status = myri10ge_set_stats(mgp, slice);
2433 if (status) {
2434 printk(KERN_ERR
2435 "myri10ge: %s: Couldn't set stats DMA\n",
2436 dev->name);
2437 goto abort_with_rings;
2438 }
2439
2440 lro_mgr = &ss->rx_done.lro_mgr;
2441 lro_mgr->dev = dev;
2442 lro_mgr->features = LRO_F_NAPI;
2443 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2444 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2445 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2446 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2447 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2448 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2449 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2450 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2451
2452 /* must happen prior to any irq */
2453 napi_enable(&(ss)->napi);
2454 }
0da34b6d
BG		 2455
2456 /* now give firmware buffers sizes, and MTU */
2457 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2458 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2459 cmd.data0 = mgp->small_bytes;
2460 status |=
2461 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2462 cmd.data0 = big_pow2;
2463 status |=
2464 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2465 if (status) {
2466 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2467 dev->name);
2468 goto abort_with_rings;
2469 }
2470
0dcffac1
BG		 2471 /*
2472 * Set Linux style TSO mode; this is needed only on newer
2473 * firmware versions. Older versions default to Linux
2474 * style TSO
2475 */
2476 cmd.data0 = 0;
2477 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2478 if (status && status != -ENOSYS) {
2479 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
0da34b6d
BG		 2480 dev->name);
2481 goto abort_with_rings;
2482 }
2483
66341fff 2484 mgp->link_state = ~0U;
0da34b6d
BG		 2485 mgp->rdma_tags_available = 15;
2486
0da34b6d
BG		 2487 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2488 if (status) {
2489 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2490 dev->name);
2491 goto abort_with_rings;
2492 }
2493
0da34b6d
BG		 2494 mgp->running = MYRI10GE_ETH_RUNNING;
2495 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2496 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2497 netif_tx_wake_all_queues(dev);
2498
0da34b6d
BG		 2499 return 0;
2500
2501abort_with_rings:
051d36f3
BG		 2502 while (slice) {
2503 slice--;
2504 napi_disable(&mgp->ss[slice].napi);
2505 }
0dcffac1
BG		 2506 for (i = 0; i < mgp->num_slices; i++)
2507 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2508
df30a740
BG		 2509 myri10ge_free_irq(mgp);
2510
0da34b6d
BG		 2511abort_with_nothing:
2512 mgp->running = MYRI10GE_ETH_STOPPED;
2513 return -ENOMEM;
2514}
2515
2516static int myri10ge_close(struct net_device *dev)
2517{
b53bef84 2518 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2519 struct myri10ge_cmd cmd;
2520 int status, old_down_cnt;
0dcffac1 2521 int i;
0da34b6d 2522
0da34b6d
BG		 2523 if (mgp->running != MYRI10GE_ETH_RUNNING)
2524 return 0;
2525
0dcffac1 2526 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2527 return 0;
2528
2529 del_timer_sync(&mgp->watchdog_timer);
2530 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2531 for (i = 0; i < mgp->num_slices; i++) {
2532 napi_disable(&mgp->ss[i].napi);
2533 }
0da34b6d 2534 netif_carrier_off(dev);
236bb5e6
BG		 2535
2536 netif_tx_stop_all_queues(dev);
0da34b6d
BG		 2537 old_down_cnt = mgp->down_cnt;
2538 mb();
2539 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2540 if (status)
2541 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2542 dev->name);
2543
2544 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2545 if (old_down_cnt == mgp->down_cnt)
2546 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2547
2548 netif_tx_disable(dev);
df30a740 2549 myri10ge_free_irq(mgp);
0dcffac1
BG		 2550 for (i = 0; i < mgp->num_slices; i++)
2551 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2552
2553 mgp->running = MYRI10GE_ETH_STOPPED;
2554 return 0;
2555}
2556
2557/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2558 * backwards one at a time and handle ring wraps */
2559
2560static inline void
2561myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2562 struct mcp_kreq_ether_send *src, int cnt)
2563{
2564 int idx, starting_slot;
2565 starting_slot = tx->req;
2566 while (cnt > 1) {
2567 cnt--;
2568 idx = (starting_slot + cnt) & tx->mask;
2569 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2570 mb();
2571 }
2572}
2573
2574/*
2575 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2576 * at most 32 bytes at a time, so as to avoid involving the software
2577 * pio handler in the nic. We re-write the first segment's flags
2578 * to mark them valid only after writing the entire chain.
2579 */
2580
2581static inline void
2582myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2583 int cnt)
2584{
2585 int idx, i;
2586 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2587 struct mcp_kreq_ether_send *srcp;
2588 u8 last_flags;
2589
2590 idx = tx->req & tx->mask;
2591
2592 last_flags = src->flags;
2593 src->flags = 0;
2594 mb();
2595 dst = dstp = &tx->lanai[idx];
2596 srcp = src;
2597
2598 if ((idx + cnt) < tx->mask) {
2599 for (i = 0; i < (cnt - 1); i += 2) {
2600 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2601 mb(); /* force write every 32 bytes */
2602 srcp += 2;
2603 dstp += 2;
2604 }
2605 } else {
2606 /* submit all but the first request, and ensure
2607 * that it is submitted below */
2608 myri10ge_submit_req_backwards(tx, src, cnt);
2609 i = 0;
2610 }
2611 if (i < cnt) {
2612 /* submit the first request */
2613 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2614 mb(); /* barrier before setting valid flag */
2615 }
2616
2617 /* re-write the last 32-bits with the valid flags */
2618 src->flags = last_flags;
40f6cff5 2619 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2620 tx->req += cnt;
2621 mb();
2622}
2623
0da34b6d
BG		 2624/*
2625 * Transmit a packet. We need to split the packet so that a single
b53bef84 2626 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2627 * counting tricky. So rather than try to count segments up front, we
2628 * just give up if there are too few segments to hold a reasonably
2629 * fragmented packet currently available. If we run
2630 * out of segments while preparing a packet for DMA, we just linearize
2631 * it and try again.
2632 */
2633
2634static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2635{
2636 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2637 struct myri10ge_slice_state *ss;
0da34b6d 2638 struct mcp_kreq_ether_send *req;
b53bef84 2639 struct myri10ge_tx_buf *tx;
0da34b6d 2640 struct skb_frag_struct *frag;
236bb5e6 2641 struct netdev_queue *netdev_queue;
0da34b6d 2642 dma_addr_t bus;
40f6cff5
AV		 2643 u32 low;
2644 __be32 high_swapped;
0da34b6d
BG		 2645 unsigned int len;
2646 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2647 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2648 int cum_len, seglen, boundary, rdma_count;
2649 u8 flags, odd_flag;
2650
236bb5e6 2651 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2652 ss = &mgp->ss[queue];
2653 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2654 tx = &ss->tx;
236bb5e6 2655
0da34b6d
BG		 2656again:
2657 req = tx->req_list;
2658 avail = tx->mask - 1 - (tx->req - tx->done);
2659
2660 mss = 0;
2661 max_segments = MXGEFW_MAX_SEND_DESC;
2662
917690cd 2663 if (skb_is_gso(skb)) {
7967168c 2664 mss = skb_shinfo(skb)->gso_size;
917690cd 2665 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2666 }
0da34b6d
BG		 2667
2668 if ((unlikely(avail < max_segments))) {
2669 /* we are out of transmit resources */
b53bef84 2670 tx->stop_queue++;
236bb5e6 2671 netif_tx_stop_queue(netdev_queue);
0da34b6d
BG		 2672 return 1;
2673 }
2674
2675 /* Setup checksum offloading, if needed */
2676 cksum_offset = 0;
2677 pseudo_hdr_offset = 0;
2678 odd_flag = 0;
2679 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2680 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2681 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2682 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2683 /* If the headers are excessively large, then we must
2684 * fall back to a software checksum */
4f93fde0
BG		 2685 if (unlikely(!mss && (cksum_offset > 255 ||
2686 pseudo_hdr_offset > 127))) {
84fa7933 2687 if (skb_checksum_help(skb))
0da34b6d
BG		 2688 goto drop;
2689 cksum_offset = 0;
2690 pseudo_hdr_offset = 0;
2691 } else {
0da34b6d
BG		 2692 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2693 flags |= MXGEFW_FLAGS_CKSUM;
2694 }
2695 }
2696
2697 cum_len = 0;
2698
0da34b6d
BG		 2699 if (mss) { /* TSO */
2700 /* this removes any CKSUM flag from before */
2701 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2702
2703 /* negative cum_len signifies to the
2704 * send loop that we are still in the
2705 * header portion of the TSO packet.
4f93fde0 2706 * TSO header can be at most 1KB long */
ab6a5bb6 2707 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2708
4f93fde0
BG		 2709 /* for IPv6 TSO, the checksum offset stores the
2710 * TCP header length, to save the firmware from
2711 * the need to parse the headers */
2712 if (skb_is_gso_v6(skb)) {
2713 cksum_offset = tcp_hdrlen(skb);
2714 /* Can only handle headers <= max_tso6 long */
2715 if (unlikely(-cum_len > mgp->max_tso6))
2716 return myri10ge_sw_tso(skb, dev);
2717 }
0da34b6d
BG		 2718 /* for TSO, pseudo_hdr_offset holds mss.
2719 * The firmware figures out where to put
2720 * the checksum by parsing the header. */
40f6cff5 2721 pseudo_hdr_offset = mss;
0da34b6d 2722 } else
0da34b6d
BG		 2723 /* Mark small packets, and pad out tiny packets */
2724 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2725 flags |= MXGEFW_FLAGS_SMALL;
2726
2727 /* pad frames to at least ETH_ZLEN bytes */
2728 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2729 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2730 /* The packet is gone, so we must
2731 * return 0 */
b53bef84 2732 ss->stats.tx_dropped += 1;
0da34b6d
BG		 2733 return 0;
2734 }
2735 /* adjust the len to account for the zero pad
2736 * so that the nic can know how long it is */
2737 skb->len = ETH_ZLEN;
2738 }
2739 }
2740
2741 /* map the skb for DMA */
2742 len = skb->len - skb->data_len;
2743 idx = tx->req & tx->mask;
2744 tx->info[idx].skb = skb;
2745 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2746 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2747 pci_unmap_len_set(&tx->info[idx], len, len);
2748
2749 frag_cnt = skb_shinfo(skb)->nr_frags;
2750 frag_idx = 0;
2751 count = 0;
2752 rdma_count = 0;
2753
2754 /* "rdma_count" is the number of RDMAs belonging to the
2755 * current packet BEFORE the current send request. For
2756 * non-TSO packets, this is equal to "count".
2757 * For TSO packets, rdma_count needs to be reset
2758 * to 0 after a segment cut.
2759 *
2760 * The rdma_count field of the send request is
2761 * the number of RDMAs of the packet starting at
2762 * that request. For TSO send requests with one ore more cuts
2763 * in the middle, this is the number of RDMAs starting
2764 * after the last cut in the request. All previous
2765 * segments before the last cut implicitly have 1 RDMA.
2766 *
2767 * Since the number of RDMAs is not known beforehand,
2768 * it must be filled-in retroactively - after each
2769 * segmentation cut or at the end of the entire packet.
2770 */
2771
2772 while (1) {
2773 /* Break the SKB or Fragment up into pieces which
b53bef84 2774 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2775 low = MYRI10GE_LOWPART_TO_U32(bus);
2776 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2777 while (len) {
2778 u8 flags_next;
2779 int cum_len_next;
2780
2781 if (unlikely(count == max_segments))
2782 goto abort_linearize;
2783
b53bef84
BG		 2784 boundary =
2785 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2786 seglen = boundary - low;
2787 if (seglen > len)
2788 seglen = len;
2789 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2790 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2791 if (mss) { /* TSO */
2792 (req - rdma_count)->rdma_count = rdma_count + 1;
2793
2794 if (likely(cum_len >= 0)) { /* payload */
2795 int next_is_first, chop;
2796
2797 chop = (cum_len_next > mss);
2798 cum_len_next = cum_len_next % mss;
2799 next_is_first = (cum_len_next == 0);
2800 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2801 flags_next |= next_is_first *
2802 MXGEFW_FLAGS_FIRST;
2803 rdma_count |= -(chop | next_is_first);
2804 rdma_count += chop & !next_is_first;
2805 } else if (likely(cum_len_next >= 0)) { /* header ends */
2806 int small;
2807
2808 rdma_count = -1;
2809 cum_len_next = 0;
2810 seglen = -cum_len;
2811 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2812 flags_next = MXGEFW_FLAGS_TSO_PLD |
2813 MXGEFW_FLAGS_FIRST |
2814 (small * MXGEFW_FLAGS_SMALL);
2815 }
2816 }
0da34b6d
BG		 2817 req->addr_high = high_swapped;
2818 req->addr_low = htonl(low);
40f6cff5 2819 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2820 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2821 req->rdma_count = 1;
2822 req->length = htons(seglen);
2823 req->cksum_offset = cksum_offset;
2824 req->flags = flags | ((cum_len & 1) * odd_flag);
2825
2826 low += seglen;
2827 len -= seglen;
2828 cum_len = cum_len_next;
2829 flags = flags_next;
2830 req++;
2831 count++;
2832 rdma_count++;
4f93fde0
BG		 2833 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2834 if (unlikely(cksum_offset > seglen))
2835 cksum_offset -= seglen;
2836 else
2837 cksum_offset = 0;
2838 }
0da34b6d
BG		 2839 }
2840 if (frag_idx == frag_cnt)
2841 break;
2842
2843 /* map next fragment for DMA */
2844 idx = (count + tx->req) & tx->mask;
2845 frag = &skb_shinfo(skb)->frags[frag_idx];
2846 frag_idx++;
2847 len = frag->size;
2848 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2849 len, PCI_DMA_TODEVICE);
2850 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2851 pci_unmap_len_set(&tx->info[idx], len, len);
2852 }
2853
2854 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2855 if (mss)
2856 do {
2857 req--;
2858 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2859 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2860 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2861 idx = ((count - 1) + tx->req) & tx->mask;
2862 tx->info[idx].last = 1;
e454e7e2 2863 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2864 /* if using multiple tx queues, make sure NIC polls the
2865 * current slice */
2866 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2867 tx->queue_active = 1;
2868 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2869 mb();
6824a105 2870 mmiowb();
236bb5e6 2871 }
0da34b6d
BG		 2872 tx->pkt_start++;
2873 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2874 tx->stop_queue++;
236bb5e6 2875 netif_tx_stop_queue(netdev_queue);
0da34b6d
BG		 2876 }
2877 dev->trans_start = jiffies;
2878 return 0;
2879
2880abort_linearize:
2881 /* Free any DMA resources we've alloced and clear out the skb
2882 * slot so as to not trip up assertions, and to avoid a
2883 * double-free if linearizing fails */
2884
2885 last_idx = (idx + 1) & tx->mask;
2886 idx = tx->req & tx->mask;
2887 tx->info[idx].skb = NULL;
2888 do {
2889 len = pci_unmap_len(&tx->info[idx], len);
2890 if (len) {
2891 if (tx->info[idx].skb != NULL)
2892 pci_unmap_single(mgp->pdev,
2893 pci_unmap_addr(&tx->info[idx],
2894 bus), len,
2895 PCI_DMA_TODEVICE);
2896 else
2897 pci_unmap_page(mgp->pdev,
2898 pci_unmap_addr(&tx->info[idx],
2899 bus), len,
2900 PCI_DMA_TODEVICE);
2901 pci_unmap_len_set(&tx->info[idx], len, 0);
2902 tx->info[idx].skb = NULL;
2903 }
2904 idx = (idx + 1) & tx->mask;
2905 } while (idx != last_idx);
89114afd 2906 if (skb_is_gso(skb)) {
0da34b6d
BG		 2907 printk(KERN_ERR
2908 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2909 mgp->dev->name);
2910 goto drop;
2911 }
2912
bec0e859 2913 if (skb_linearize(skb))
0da34b6d
BG		 2914 goto drop;
2915
b53bef84 2916 tx->linearized++;
0da34b6d
BG		 2917 goto again;
2918
2919drop:
2920 dev_kfree_skb_any(skb);
b53bef84 2921 ss->stats.tx_dropped += 1;
0da34b6d
BG		 2922 return 0;
2923
2924}
2925
4f93fde0
BG		 2926static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2927{
2928 struct sk_buff *segs, *curr;
b53bef84 2929 struct myri10ge_priv *mgp = netdev_priv(dev);
4f93fde0
BG		 2930 int status;
2931
2932 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2933 if (IS_ERR(segs))
4f93fde0
BG		 2934 goto drop;
2935
2936 while (segs) {
2937 curr = segs;
2938 segs = segs->next;
2939 curr->next = NULL;
2940 status = myri10ge_xmit(curr, dev);
2941 if (status != 0) {
2942 dev_kfree_skb_any(curr);
2943 if (segs != NULL) {
2944 curr = segs;
2945 segs = segs->next;
2946 curr->next = NULL;
2947 dev_kfree_skb_any(segs);
2948 }
2949 goto drop;
2950 }
2951 }
2952 dev_kfree_skb_any(skb);
2953 return 0;
2954
2955drop:
2956 dev_kfree_skb_any(skb);
2957 mgp->stats.tx_dropped += 1;
2958 return 0;
2959}
2960
0da34b6d
BG		 2961static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2962{
2963 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1
BG		 2964 struct myri10ge_slice_netstats *slice_stats;
2965 struct net_device_stats *stats = &mgp->stats;
2966 int i;
2967
2968 memset(stats, 0, sizeof(*stats));
2969 for (i = 0; i < mgp->num_slices; i++) {
2970 slice_stats = &mgp->ss[i].stats;
2971 stats->rx_packets += slice_stats->rx_packets;
2972 stats->tx_packets += slice_stats->tx_packets;
2973 stats->rx_bytes += slice_stats->rx_bytes;
2974 stats->tx_bytes += slice_stats->tx_bytes;
2975 stats->rx_dropped += slice_stats->rx_dropped;
2976 stats->tx_dropped += slice_stats->tx_dropped;
2977 }
2978 return stats;
0da34b6d
BG		 2979}
2980
2981static void myri10ge_set_multicast_list(struct net_device *dev)
2982{
b53bef84 2983 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 2984 struct myri10ge_cmd cmd;
85a7ea1b 2985 struct dev_mc_list *mc_list;
6250223e 2986 __be32 data[2] = { 0, 0 };
85a7ea1b 2987 int err;
0795af57 2988 DECLARE_MAC_BUF(mac);
85a7ea1b 2989
0da34b6d
BG		 2990 /* can be called from atomic contexts,
2991 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2992 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2993
2994 /* This firmware is known to not support multicast */
2f76216f 2995 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2996 return;
2997
2998 /* Disable multicast filtering */
2999
3000 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3001 if (err != 0) {
3002 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
3003 " error status: %d\n", dev->name, err);
3004 goto abort;
3005 }
3006
2f76216f 3007 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3008 /* request to disable multicast filtering, so quit here */
3009 return;
3010 }
3011
3012 /* Flush the filters */
3013
3014 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3015 &cmd, 1);
3016 if (err != 0) {
3017 printk(KERN_ERR
3018 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
3019 ", error status: %d\n", dev->name, err);
3020 goto abort;
3021 }
3022
3023 /* Walk the multicast list, and add each address */
3024 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 3025 memcpy(data, &mc_list->dmi_addr, 6);
3026 cmd.data0 = ntohl(data[0]);
3027 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3028 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3029 &cmd, 1);
3030
3031 if (err != 0) {
3032 printk(KERN_ERR "myri10ge: %s: Failed "
3033 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
3034 "%d\t", dev->name, err);
0795af57
JP		 3035 printk(KERN_ERR "MAC %s\n",
3036 print_mac(mac, mc_list->dmi_addr));
85a7ea1b
BG		 3037 goto abort;
3038 }
3039 }
3040 /* Enable multicast filtering */
3041 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3042 if (err != 0) {
3043 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3044 "error status: %d\n", dev->name, err);
3045 goto abort;
3046 }
3047
3048 return;
3049
3050abort:
3051 return;
0da34b6d
BG		 3052}
3053
3054static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3055{
3056 struct sockaddr *sa = addr;
3057 struct myri10ge_priv *mgp = netdev_priv(dev);
3058 int status;
3059
3060 if (!is_valid_ether_addr(sa->sa_data))
3061 return -EADDRNOTAVAIL;
3062
3063 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3064 if (status != 0) {
3065 printk(KERN_ERR
3066 "myri10ge: %s: changing mac address failed with %d\n",
3067 dev->name, status);
3068 return status;
3069 }
3070
3071 /* change the dev structure */
3072 memcpy(dev->dev_addr, sa->sa_data, 6);
3073 return 0;
3074}
3075
3076static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3077{
3078 struct myri10ge_priv *mgp = netdev_priv(dev);
3079 int error = 0;
3080
3081 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3082 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3083 dev->name, new_mtu);
3084 return -EINVAL;
3085 }
3086 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3087 dev->name, dev->mtu, new_mtu);
3088 if (mgp->running) {
3089 /* if we change the mtu on an active device, we must
3090 * reset the device so the firmware sees the change */
3091 myri10ge_close(dev);
3092 dev->mtu = new_mtu;
3093 myri10ge_open(dev);
3094 } else
3095 dev->mtu = new_mtu;
3096
3097 return error;
3098}
3099
3100/*
3101 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3102 * Only do it if the bridge is a root port since we don't want to disturb
3103 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3104 */
3105
0da34b6d
BG		 3106static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3107{
3108 struct pci_dev *bridge = mgp->pdev->bus->self;
3109 struct device *dev = &mgp->pdev->dev;
3110 unsigned cap;
3111 unsigned err_cap;
3112 u16 val;
3113 u8 ext_type;
3114 int ret;
3115
3116 if (!myri10ge_ecrc_enable || !bridge)
3117 return;
3118
3119 /* check that the bridge is a root port */
3120 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3121 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3122 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3123 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3124 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3125 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3126
3127 /* Walk the hierarchy up to the root port
3128 * where ECRC has to be enabled */
3129 do {
eca3fd83 3130 prev_bridge = bridge;
0da34b6d 3131 bridge = bridge->bus->self;
eca3fd83 3132 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3133 dev_err(dev,
3134 "Failed to find root port"
3135 " to force ECRC\n");
3136 return;
3137 }
3138 cap =
3139 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3140 pci_read_config_word(bridge,
3141 cap + PCI_CAP_FLAGS, &val);
3142 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3143 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3144
3145 dev_info(dev,
3146 "Forcing ECRC on non-root port %s"
3147 " (enabling on root port %s)\n",
3148 pci_name(old_bridge), pci_name(bridge));
3149 } else {
3150 dev_err(dev,
3151 "Not enabling ECRC on non-root port %s\n",
3152 pci_name(bridge));
3153 return;
3154 }
3155 }
3156
3157 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3158 if (!cap)
3159 return;
3160
3161 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3162 if (ret) {
3163 dev_err(dev, "failed reading ext-conf-space of %s\n",
3164 pci_name(bridge));
3165 dev_err(dev, "\t pci=nommconf in use? "
3166 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3167 return;
3168 }
3169 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3170 return;
3171
3172 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3173 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3174 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3175}
3176
3177/*
3178 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3179 * when the PCI-E Completion packets are aligned on an 8-byte
3180 * boundary. Some PCI-E chip sets always align Completion packets; on
3181 * the ones that do not, the alignment can be enforced by enabling
3182 * ECRC generation (if supported).
3183 *
3184 * When PCI-E Completion packets are not aligned, it is actually more
3185 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3186 *
3187 * If the driver can neither enable ECRC nor verify that it has
3188 * already been enabled, then it must use a firmware image which works
0dcffac1 3189 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3190 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3191 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3192 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3193 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3194 */
3195
5443e9ea 3196static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3197{
5443e9ea
BG		 3198 struct pci_dev *pdev = mgp->pdev;
3199 struct device *dev = &pdev->dev;
302d242c 3200 int status;
0da34b6d 3201
b53bef84 3202 mgp->tx_boundary = 4096;
5443e9ea
BG		 3203 /*
3204 * Verify the max read request size was set to 4KB
3205 * before trying the test with 4KB.
3206 */
302d242c
BG		 3207 status = pcie_get_readrq(pdev);
3208 if (status < 0) {
5443e9ea
BG		 3209 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3210 goto abort;
3211 }
302d242c
BG		 3212 if (status != 4096) {
3213 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3214 mgp->tx_boundary = 2048;
5443e9ea
BG		 3215 }
3216 /*
3217 * load the optimized firmware (which assumes aligned PCIe
3218 * completions) in order to see if it works on this host.
3219 */
3220 mgp->fw_name = myri10ge_fw_aligned;
0dcffac1 3221 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3222 if (status != 0) {
3223 goto abort;
3224 }
3225
3226 /*
3227 * Enable ECRC if possible
3228 */
3229 myri10ge_enable_ecrc(mgp);
3230
3231 /*
3232 * Run a DMA test which watches for unaligned completions and
3233 * aborts on the first one seen.
3234 */
3235
3236 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3237 if (status == 0)
3238 return; /* keep the aligned firmware */
3239
3240 if (status != -E2BIG)
3241 dev_warn(dev, "DMA test failed: %d\n", status);
3242 if (status == -ENOSYS)
3243 dev_warn(dev, "Falling back to ethp! "
3244 "Please install up to date fw\n");
3245abort:
3246 /* fall back to using the unaligned firmware */
b53bef84 3247 mgp->tx_boundary = 2048;
0da34b6d
BG		 3248 mgp->fw_name = myri10ge_fw_unaligned;
3249
5443e9ea
BG		 3250}
3251
3252static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3253{
0da34b6d 3254 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3255 int link_width, exp_cap;
3256 u16 lnk;
3257
3258 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3259 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3260 link_width = (lnk >> 4) & 0x3f;
3261
ce7f9368
BG		 3262 /* Check to see if Link is less than 8 or if the
3263 * upstream bridge is known to provide aligned
3264 * completions */
3265 if (link_width < 8) {
3266 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3267 link_width);
b53bef84 3268 mgp->tx_boundary = 4096;
ce7f9368 3269 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 3270 } else {
3271 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3272 }
3273 } else {
3274 if (myri10ge_force_firmware == 1) {
3275 dev_info(&mgp->pdev->dev,
3276 "Assuming aligned completions (forced)\n");
b53bef84 3277 mgp->tx_boundary = 4096;
0da34b6d
BG		 3278 mgp->fw_name = myri10ge_fw_aligned;
3279 } else {
3280 dev_info(&mgp->pdev->dev,
3281 "Assuming unaligned completions (forced)\n");
b53bef84 3282 mgp->tx_boundary = 2048;
0da34b6d
BG		 3283 mgp->fw_name = myri10ge_fw_unaligned;
3284 }
3285 }
3286 if (myri10ge_fw_name != NULL) {
3287 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3288 myri10ge_fw_name);
3289 mgp->fw_name = myri10ge_fw_name;
3290 }
3291}
3292
0da34b6d 3293#ifdef CONFIG_PM
0da34b6d
BG		 3294static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3295{
3296 struct myri10ge_priv *mgp;
3297 struct net_device *netdev;
3298
3299 mgp = pci_get_drvdata(pdev);
3300 if (mgp == NULL)
3301 return -EINVAL;
3302 netdev = mgp->dev;
3303
3304 netif_device_detach(netdev);
3305 if (netif_running(netdev)) {
3306 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3307 rtnl_lock();
3308 myri10ge_close(netdev);
3309 rtnl_unlock();
3310 }
3311 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3312 pci_save_state(pdev);
0da34b6d 3313 pci_disable_device(pdev);
1a63e846
BG		 3314
3315 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3316}
3317
3318static int myri10ge_resume(struct pci_dev *pdev)
3319{
3320 struct myri10ge_priv *mgp;
3321 struct net_device *netdev;
3322 int status;
3323 u16 vendor;
3324
3325 mgp = pci_get_drvdata(pdev);
3326 if (mgp == NULL)
3327 return -EINVAL;
3328 netdev = mgp->dev;
3329 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3330 msleep(5); /* give card time to respond */
3331 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3332 if (vendor == 0xffff) {
3333 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3334 mgp->dev->name);
3335 return -EIO;
3336 }
83f6e152 3337
1a63e846
BG		 3338 status = pci_restore_state(pdev);
3339 if (status)
3340 return status;
4c2248cc
BG		 3341
3342 status = pci_enable_device(pdev);
1a63e846 3343 if (status) {
4c2248cc 3344 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3345 return status;
4c2248cc
BG		 3346 }
3347
0da34b6d
BG		 3348 pci_set_master(pdev);
3349
0da34b6d 3350 myri10ge_reset(mgp);
013b68bf 3351 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3352
3353 /* Save configuration space to be restored if the
3354 * nic resets due to a parity error */
83f6e152 3355 pci_save_state(pdev);
0da34b6d
BG		 3356
3357 if (netif_running(netdev)) {
3358 rtnl_lock();
df30a740 3359 status = myri10ge_open(netdev);
0da34b6d 3360 rtnl_unlock();
df30a740
BG		 3361 if (status != 0)
3362 goto abort_with_enabled;
3363
0da34b6d
BG		 3364 }
3365 netif_device_attach(netdev);
3366
3367 return 0;
3368
4c2248cc
BG		 3369abort_with_enabled:
3370 pci_disable_device(pdev);
0da34b6d
BG		 3371 return -EIO;
3372
3373}
0da34b6d
BG		 3374#endif /* CONFIG_PM */
3375
3376static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3377{
3378 struct pci_dev *pdev = mgp->pdev;
3379 int vs = mgp->vendor_specific_offset;
3380 u32 reboot;
3381
3382 /*enter read32 mode */
3383 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3384
3385 /*read REBOOT_STATUS (0xfffffff0) */
3386 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3387 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3388 return reboot;
3389}
3390
3391/*
3392 * This watchdog is used to check whether the board has suffered
3393 * from a parity error and needs to be recovered.
3394 */
c4028958 3395static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3396{
c4028958 3397 struct myri10ge_priv *mgp =
6250223e 3398 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3399 struct myri10ge_tx_buf *tx;
0da34b6d
BG		 3400 u32 reboot;
3401 int status;
0dcffac1 3402 int i;
0da34b6d
BG		 3403 u16 cmd, vendor;
3404
3405 mgp->watchdog_resets++;
3406 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3407 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3408 /* Bus master DMA disabled? Check to see
3409 * if the card rebooted due to a parity error
3410 * For now, just report it */
3411 reboot = myri10ge_read_reboot(mgp);
3412 printk(KERN_ERR
f181137f
BG		 3413 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3414 mgp->dev->name, reboot,
3415 myri10ge_reset_recover ? " " : " not");
3416 if (myri10ge_reset_recover == 0)
3417 return;
3418
3419 myri10ge_reset_recover--;
3420
0da34b6d
BG		 3421 /*
3422 * A rebooted nic will come back with config space as
3423 * it was after power was applied to PCIe bus.
3424 * Attempt to restore config space which was saved
3425 * when the driver was loaded, or the last time the
3426 * nic was resumed from power saving mode.
3427 */
83f6e152 3428 pci_restore_state(mgp->pdev);
7adda30c
BG		 3429
3430 /* save state again for accounting reasons */
83f6e152 3431 pci_save_state(mgp->pdev);
7adda30c 3432
0da34b6d
BG		 3433 } else {
3434 /* if we get back -1's from our slot, perhaps somebody
3435 * powered off our card. Don't try to reset it in
3436 * this case */
3437 if (cmd == 0xffff) {
3438 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3439 if (vendor == 0xffff) {
3440 printk(KERN_ERR
3441 "myri10ge: %s: device disappeared!\n",
3442 mgp->dev->name);
3443 return;
3444 }
3445 }
3446 /* Perhaps it is a software error. Try to reset */
3447
3448 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3449 mgp->dev->name);
0dcffac1
BG		 3450 for (i = 0; i < mgp->num_slices; i++) {
3451 tx = &mgp->ss[i].tx;
3452 printk(KERN_INFO
236bb5e6
BG		 3453 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3454 mgp->dev->name, i, tx->queue_active, tx->req,
3455 tx->done, tx->pkt_start, tx->pkt_done,
0dcffac1
BG		 3456 (int)ntohl(mgp->ss[i].fw_stats->
3457 send_done_count));
3458 msleep(2000);
3459 printk(KERN_INFO
236bb5e6
BG		 3460 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3461 mgp->dev->name, i, tx->queue_active, tx->req,
3462 tx->done, tx->pkt_start, tx->pkt_done,
0dcffac1
BG		 3463 (int)ntohl(mgp->ss[i].fw_stats->
3464 send_done_count));
3465 }
0da34b6d 3466 }
236bb5e6 3467
0da34b6d
BG		 3468 rtnl_lock();
3469 myri10ge_close(mgp->dev);
0dcffac1 3470 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3471 if (status != 0)
3472 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3473 mgp->dev->name);
3474 else
3475 myri10ge_open(mgp->dev);
3476 rtnl_unlock();
3477}
3478
3479/*
3480 * We use our own timer routine rather than relying upon
3481 * netdev->tx_timeout because we have a very large hardware transmit
3482 * queue. Due to the large queue, the netdev->tx_timeout function
3483 * cannot detect a NIC with a parity error in a timely fashion if the
3484 * NIC is lightly loaded.
3485 */
3486static void myri10ge_watchdog_timer(unsigned long arg)
3487{
3488 struct myri10ge_priv *mgp;
b53bef84 3489 struct myri10ge_slice_state *ss;
0dcffac1 3490 int i, reset_needed;
626fda94 3491 u32 rx_pause_cnt;
0da34b6d
BG		 3492
3493 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3494
0dcffac1
BG		 3495 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3496 for (i = 0, reset_needed = 0;
3497 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3498
0dcffac1
BG		 3499 ss = &mgp->ss[i];
3500 if (ss->rx_small.watchdog_needed) {
3501 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3502 mgp->small_bytes + MXGEFW_PAD,
3503 1);
3504 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3505 myri10ge_fill_thresh)
3506 ss->rx_small.watchdog_needed = 0;
3507 }
3508 if (ss->rx_big.watchdog_needed) {
3509 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3510 mgp->big_bytes, 1);
3511 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3512 myri10ge_fill_thresh)
3513 ss->rx_big.watchdog_needed = 0;
3514 }
3515
3516 if (ss->tx.req != ss->tx.done &&
3517 ss->tx.done == ss->watchdog_tx_done &&
3518 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3519 /* nic seems like it might be stuck.. */
3520 if (rx_pause_cnt != mgp->watchdog_pause) {
3521 if (net_ratelimit())
236bb5e6
BG		 3522 printk(KERN_WARNING
3523 "myri10ge %s slice %d:"
0dcffac1 3524 "TX paused, check link partner\n",
236bb5e6 3525 mgp->dev->name, i);
0dcffac1 3526 } else {
236bb5e6
BG		 3527 printk(KERN_WARNING
3528 "myri10ge %s slice %d stuck:",
3529 mgp->dev->name, i);
0dcffac1
BG		 3530 reset_needed = 1;
3531 }
626fda94 3532 }
0dcffac1
BG		 3533 ss->watchdog_tx_done = ss->tx.done;
3534 ss->watchdog_tx_req = ss->tx.req;
626fda94 3535 }
626fda94 3536 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3537
3538 if (reset_needed) {
3539 schedule_work(&mgp->watchdog_work);
3540 } else {
3541 /* rearm timer */
3542 mod_timer(&mgp->watchdog_timer,
3543 jiffies + myri10ge_watchdog_timeout * HZ);
3544 }
0da34b6d
BG		 3545}
3546
77929732
BG		 3547static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3548{
3549 struct myri10ge_slice_state *ss;
3550 struct pci_dev *pdev = mgp->pdev;
3551 size_t bytes;
3552 int i;
3553
3554 if (mgp->ss == NULL)
3555 return;
3556
3557 for (i = 0; i < mgp->num_slices; i++) {
3558 ss = &mgp->ss[i];
3559 if (ss->rx_done.entry != NULL) {
3560 bytes = mgp->max_intr_slots *
3561 sizeof(*ss->rx_done.entry);
3562 dma_free_coherent(&pdev->dev, bytes,
3563 ss->rx_done.entry, ss->rx_done.bus);
3564 ss->rx_done.entry = NULL;
3565 }
3566 if (ss->fw_stats != NULL) {
3567 bytes = sizeof(*ss->fw_stats);
3568 dma_free_coherent(&pdev->dev, bytes,
3569 ss->fw_stats, ss->fw_stats_bus);
3570 ss->fw_stats = NULL;
3571 }
3572 }
3573 kfree(mgp->ss);
3574 mgp->ss = NULL;
3575}
3576
3577static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3578{
3579 struct myri10ge_slice_state *ss;
3580 struct pci_dev *pdev = mgp->pdev;
3581 size_t bytes;
3582 int i;
3583
3584 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3585 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3586 if (mgp->ss == NULL) {
3587 return -ENOMEM;
3588 }
3589
3590 for (i = 0; i < mgp->num_slices; i++) {
3591 ss = &mgp->ss[i];
3592 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3593 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3594 &ss->rx_done.bus,
3595 GFP_KERNEL);
3596 if (ss->rx_done.entry == NULL)
3597 goto abort;
3598 memset(ss->rx_done.entry, 0, bytes);
3599 bytes = sizeof(*ss->fw_stats);
3600 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3601 &ss->fw_stats_bus,
3602 GFP_KERNEL);
3603 if (ss->fw_stats == NULL)
3604 goto abort;
3605 ss->mgp = mgp;
3606 ss->dev = mgp->dev;
3607 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3608 myri10ge_napi_weight);
3609 }
3610 return 0;
3611abort:
3612 myri10ge_free_slices(mgp);
3613 return -ENOMEM;
3614}
3615
3616/*
3617 * This function determines the number of slices supported.
3618 * The number slices is the minumum of the number of CPUS,
3619 * the number of MSI-X irqs supported, the number of slices
3620 * supported by the firmware
3621 */
3622static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3623{
3624 struct myri10ge_cmd cmd;
3625 struct pci_dev *pdev = mgp->pdev;
3626 char *old_fw;
3627 int i, status, ncpus, msix_cap;
3628
3629 mgp->num_slices = 1;
3630 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3631 ncpus = num_online_cpus();
3632
3633 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3634 (myri10ge_max_slices == -1 && ncpus < 2))
3635 return;
3636
3637 /* try to load the slice aware rss firmware */
3638 old_fw = mgp->fw_name;
13b2738c
BG		 3639 if (myri10ge_fw_name != NULL) {
3640 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3641 myri10ge_fw_name);
3642 mgp->fw_name = myri10ge_fw_name;
3643 } else if (old_fw == myri10ge_fw_aligned)
77929732
BG		 3644 mgp->fw_name = myri10ge_fw_rss_aligned;
3645 else
3646 mgp->fw_name = myri10ge_fw_rss_unaligned;
3647 status = myri10ge_load_firmware(mgp, 0);
3648 if (status != 0) {
3649 dev_info(&pdev->dev, "Rss firmware not found\n");
3650 return;
3651 }
3652
3653 /* hit the board with a reset to ensure it is alive */
3654 memset(&cmd, 0, sizeof(cmd));
3655 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3656 if (status != 0) {
3657 dev_err(&mgp->pdev->dev, "failed reset\n");
3658 goto abort_with_fw;
3659 return;
3660 }
3661
3662 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3663
3664 /* tell it the size of the interrupt queues */
3665 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3666 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3667 if (status != 0) {
3668 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3669 goto abort_with_fw;
3670 }
3671
3672 /* ask the maximum number of slices it supports */
3673 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3674 if (status != 0)
3675 goto abort_with_fw;
3676 else
3677 mgp->num_slices = cmd.data0;
3678
3679 /* Only allow multiple slices if MSI-X is usable */
3680 if (!myri10ge_msi) {
3681 goto abort_with_fw;
3682 }
3683
3684 /* if the admin did not specify a limit to how many
3685 * slices we should use, cap it automatically to the
3686 * number of CPUs currently online */
3687 if (myri10ge_max_slices == -1)
3688 myri10ge_max_slices = ncpus;
3689
3690 if (mgp->num_slices > myri10ge_max_slices)
3691 mgp->num_slices = myri10ge_max_slices;
3692
3693 /* Now try to allocate as many MSI-X vectors as we have
3694 * slices. We give up on MSI-X if we can only get a single
3695 * vector. */
3696
3697 mgp->msix_vectors = kzalloc(mgp->num_slices *
3698 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3699 if (mgp->msix_vectors == NULL)
3700 goto disable_msix;
3701 for (i = 0; i < mgp->num_slices; i++) {
3702 mgp->msix_vectors[i].entry = i;
3703 }
3704
3705 while (mgp->num_slices > 1) {
3706 /* make sure it is a power of two */
3707 while (!is_power_of_2(mgp->num_slices))
3708 mgp->num_slices--;
3709 if (mgp->num_slices == 1)
3710 goto disable_msix;
3711 status = pci_enable_msix(pdev, mgp->msix_vectors,
3712 mgp->num_slices);
3713 if (status == 0) {
3714 pci_disable_msix(pdev);
3715 return;
3716 }
3717 if (status > 0)
3718 mgp->num_slices = status;
3719 else
3720 goto disable_msix;
3721 }
3722
3723disable_msix:
3724 if (mgp->msix_vectors != NULL) {
3725 kfree(mgp->msix_vectors);
3726 mgp->msix_vectors = NULL;
3727 }
3728
3729abort_with_fw:
3730 mgp->num_slices = 1;
3731 mgp->fw_name = old_fw;
3732 myri10ge_load_firmware(mgp, 0);
3733}
77929732 3734
0da34b6d
BG		 3735static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3736{
3737 struct net_device *netdev;
3738 struct myri10ge_priv *mgp;
3739 struct device *dev = &pdev->dev;
0da34b6d
BG		 3740 int i;
3741 int status = -ENXIO;
0da34b6d 3742 int dac_enabled;
0da34b6d 3743
236bb5e6 3744 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
0da34b6d
BG		 3745 if (netdev == NULL) {
3746 dev_err(dev, "Could not allocate ethernet device\n");
3747 return -ENOMEM;
3748 }
3749
b245fb67
MH		 3750 SET_NETDEV_DEV(netdev, &pdev->dev);
3751
0da34b6d 3752 mgp = netdev_priv(netdev);
0da34b6d
BG		 3753 mgp->dev = netdev;
3754 mgp->pdev = pdev;
3755 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3756 mgp->pause = myri10ge_flow_control;
3757 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3758 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 3759 init_waitqueue_head(&mgp->down_wq);
3760
3761 if (pci_enable_device(pdev)) {
3762 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3763 status = -ENODEV;
3764 goto abort_with_netdev;
3765 }
0da34b6d
BG		 3766
3767 /* Find the vendor-specific cap so we can check
3768 * the reboot register later on */
3769 mgp->vendor_specific_offset
3770 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3771
3772 /* Set our max read request to 4KB */
302d242c 3773 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3774 if (status != 0) {
3775 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3776 status);
3777 goto abort_with_netdev;
3778 }
3779
3780 pci_set_master(pdev);
3781 dac_enabled = 1;
3782 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3783 if (status != 0) {
3784 dac_enabled = 0;
3785 dev_err(&pdev->dev,
898eb71c
JP		 3786 "64-bit pci address mask was refused, "
3787 "trying 32-bit\n");
0da34b6d
BG		 3788 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3789 }
3790 if (status != 0) {
3791 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3792 goto abort_with_netdev;
3793 }
77970ea5 3794 (void)pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
b10c0668
BG		 3795 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3796 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 3797 if (mgp->cmd == NULL)
3798 goto abort_with_netdev;
3799
0da34b6d
BG		 3800 mgp->board_span = pci_resource_len(pdev, 0);
3801 mgp->iomem_base = pci_resource_start(pdev, 0);
3802 mgp->mtrr = -1;
276e26c3 3803 mgp->wc_enabled = 0;
0da34b6d
BG		 3804#ifdef CONFIG_MTRR
3805 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3806 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3807 if (mgp->mtrr >= 0)
3808 mgp->wc_enabled = 1;
0da34b6d
BG		 3809#endif
3810 /* Hack. need to get rid of these magic numbers */
3811 mgp->sram_size =
3812 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3813 if (mgp->sram_size > mgp->board_span) {
3814 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3815 mgp->board_span);
c7f80993 3816 goto abort_with_mtrr;
0da34b6d 3817 }
c7f80993 3818 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3819 if (mgp->sram == NULL) {
3820 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3821 mgp->board_span, mgp->iomem_base);
3822 status = -ENXIO;
c7f80993 3823 goto abort_with_mtrr;
0da34b6d
BG		 3824 }
3825 memcpy_fromio(mgp->eeprom_strings,
3826 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3827 MYRI10GE_EEPROM_STRINGS_SIZE);
3828 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3829 status = myri10ge_read_mac_addr(mgp);
3830 if (status)
3831 goto abort_with_ioremap;
3832
3833 for (i = 0; i < ETH_ALEN; i++)
3834 netdev->dev_addr[i] = mgp->mac_addr[i];
3835
5443e9ea
BG		 3836 myri10ge_select_firmware(mgp);
3837
0dcffac1 3838 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3839 if (status != 0) {
3840 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3841 goto abort_with_ioremap;
3842 }
3843 myri10ge_probe_slices(mgp);
3844 status = myri10ge_alloc_slices(mgp);
3845 if (status != 0) {
3846 dev_err(&pdev->dev, "failed to alloc slice state\n");
3847 goto abort_with_firmware;
0da34b6d 3848 }
236bb5e6 3849 netdev->real_num_tx_queues = mgp->num_slices;
0da34b6d
BG		 3850 status = myri10ge_reset(mgp);
3851 if (status != 0) {
3852 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3853 goto abort_with_slices;
0da34b6d 3854 }
5dd2d332 3855#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3856 myri10ge_setup_dca(mgp);
3857#endif
0da34b6d
BG		 3858 pci_set_drvdata(pdev, mgp);
3859 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3860 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3861 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3862 myri10ge_initial_mtu = 68;
3863 netdev->mtu = myri10ge_initial_mtu;
3864 netdev->open = myri10ge_open;
3865 netdev->stop = myri10ge_close;
3866 netdev->hard_start_xmit = myri10ge_xmit;
3867 netdev->get_stats = myri10ge_get_stats;
3868 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 3869 netdev->change_mtu = myri10ge_change_mtu;
3870 netdev->set_multicast_list = myri10ge_set_multicast_list;
3871 netdev->set_mac_address = myri10ge_set_mac_address;
4f93fde0 3872 netdev->features = mgp->features;
236bb5e6 3873
0da34b6d
BG		 3874 if (dac_enabled)
3875 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3876
21d05db1
BG		 3877 /* make sure we can get an irq, and that MSI can be
3878 * setup (if available). Also ensure netdev->irq
3879 * is set to correct value if MSI is enabled */
3880 status = myri10ge_request_irq(mgp);
3881 if (status != 0)
3882 goto abort_with_firmware;
3883 netdev->irq = pdev->irq;
3884 myri10ge_free_irq(mgp);
3885
0da34b6d
BG		 3886 /* Save configuration space to be restored if the
3887 * nic resets due to a parity error */
83f6e152 3888 pci_save_state(pdev);
0da34b6d
BG		 3889
3890 /* Setup the watchdog timer */
3891 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3892 (unsigned long)mgp);
3893
3894 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3895 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3896 status = register_netdev(netdev);
3897 if (status != 0) {
3898 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3899 goto abort_with_state;
0da34b6d 3900 }
0dcffac1
BG		 3901 if (mgp->msix_enabled)
3902 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3903 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3904 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3905 else
3906 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3907 mgp->msi_enabled ? "MSI" : "xPIC",
3908 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3909 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3910
3911 return 0;
3912
7adda30c 3913abort_with_state:
83f6e152 3914 pci_restore_state(pdev);
0da34b6d 3915
0dcffac1
BG		 3916abort_with_slices:
3917 myri10ge_free_slices(mgp);
3918
0da34b6d
BG		 3919abort_with_firmware:
3920 myri10ge_dummy_rdma(mgp, 0);
3921
0da34b6d
BG		 3922abort_with_ioremap:
3923 iounmap(mgp->sram);
3924
c7f80993 3925abort_with_mtrr:
0da34b6d
BG		 3926#ifdef CONFIG_MTRR
3927 if (mgp->mtrr >= 0)
3928 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3929#endif
b10c0668
BG		 3930 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3931 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3932
3933abort_with_netdev:
3934
3935 free_netdev(netdev);
3936 return status;
3937}
3938
3939/*
3940 * myri10ge_remove
3941 *
3942 * Does what is necessary to shutdown one Myrinet device. Called
3943 * once for each Myrinet card by the kernel when a module is
3944 * unloaded.
3945 */
3946static void myri10ge_remove(struct pci_dev *pdev)
3947{
3948 struct myri10ge_priv *mgp;
3949 struct net_device *netdev;
0da34b6d
BG		 3950
3951 mgp = pci_get_drvdata(pdev);
3952 if (mgp == NULL)
3953 return;
3954
3955 flush_scheduled_work();
3956 netdev = mgp->dev;
3957 unregister_netdev(netdev);
0da34b6d 3958
5dd2d332 3959#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3960 myri10ge_teardown_dca(mgp);
3961#endif
0da34b6d
BG		 3962 myri10ge_dummy_rdma(mgp, 0);
3963
7adda30c 3964 /* avoid a memory leak */
83f6e152 3965 pci_restore_state(pdev);
7adda30c 3966
0da34b6d
BG		 3967 iounmap(mgp->sram);
3968
3969#ifdef CONFIG_MTRR
3970 if (mgp->mtrr >= 0)
3971 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3972#endif
0dcffac1
BG		 3973 myri10ge_free_slices(mgp);
3974 if (mgp->msix_vectors != NULL)
3975 kfree(mgp->msix_vectors);
b10c0668
BG		 3976 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3977 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3978
3979 free_netdev(netdev);
3980 pci_set_drvdata(pdev, NULL);
3981}
3982
b10c0668 3983#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3984#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 3985
3986static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3987 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3988 {PCI_DEVICE
3989 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3990 {0},
3991};
3992
3993static struct pci_driver myri10ge_driver = {
3994 .name = "myri10ge",
3995 .probe = myri10ge_probe,
3996 .remove = myri10ge_remove,
3997 .id_table = myri10ge_pci_tbl,
3998#ifdef CONFIG_PM
3999 .suspend = myri10ge_suspend,
4000 .resume = myri10ge_resume,
4001#endif
4002};
4003
5dd2d332 4004#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4005static int
4006myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4007{
4008 int err = driver_for_each_device(&myri10ge_driver.driver,
4009 NULL, &event,
4010 myri10ge_notify_dca_device);
4011
4012 if (err)
4013 return NOTIFY_BAD;
4014 return NOTIFY_DONE;
4015}
4016
4017static struct notifier_block myri10ge_dca_notifier = {
4018 .notifier_call = myri10ge_notify_dca,
4019 .next = NULL,
4020 .priority = 0,
4021};
4022#endif /* CONFIG_DCA */
4023
0da34b6d
BG		 4024static __init int myri10ge_init_module(void)
4025{
4026 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
4027 MYRI10GE_VERSION_STR);
0dcffac1 4028
236bb5e6 4029 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
0dcffac1
BG		 4030 printk(KERN_ERR
4031 "%s: Illegal rssh hash type %d, defaulting to source port\n",
4032 myri10ge_driver.name, myri10ge_rss_hash);
4033 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4034 }
5dd2d332 4035#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4036 dca_register_notify(&myri10ge_dca_notifier);
4037#endif
236bb5e6
BG		 4038 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4039 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4040
0da34b6d
BG		 4041 return pci_register_driver(&myri10ge_driver);
4042}
4043
4044module_init(myri10ge_init_module);
4045
4046static __exit void myri10ge_cleanup_module(void)
4047{
5dd2d332 4048#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4049 dca_unregister_notify(&myri10ge_dca_notifier);
4050#endif
0da34b6d
BG		 4051 pci_unregister_driver(&myri10ge_driver);
4052}
4053
4054module_exit(myri10ge_cleanup_module);
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