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myri10ge: add barrier in myri10ge_send_cmd
[mirror_ubuntu-bionic-kernel.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
0da34b6d
BG		 52#include <linux/ip.h>
53#include <linux/inet.h>
54#include <linux/in.h>
55#include <linux/ethtool.h>
56#include <linux/firmware.h>
57#include <linux/delay.h>
58#include <linux/version.h>
59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
e0d7c526 78#define MYRI10GE_VERSION_STR "1.3.2-1.287"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
0da34b6d 105struct myri10ge_rx_buffer_state {
dd50f336
BG		 106 struct page *page;
107 int page_offset;
0da34b6d
BG		 108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110};
111
112struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117};
118
119struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123};
124
125struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 130 struct page *page;
131 dma_addr_t bus;
132 int page_offset;
0da34b6d 133 int cnt;
dd50f336 134 int fill_cnt;
0da34b6d
BG		 135 int alloc_fail;
136 int mask; /* number of rx slots -1 */
dd50f336 137 int watchdog_needed;
0da34b6d
BG		 138};
139
140struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
144 char *req_bytes;
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int boundary; /* boundary transmits cannot cross */
148 int req ____cacheline_aligned; /* transmit slots submitted */
149 int pkt_start; /* packets started */
150 int done ____cacheline_aligned; /* transmit slots completed */
151 int pkt_done; /* packets completed */
152};
153
154struct myri10ge_rx_done {
155 struct mcp_slot *entry;
156 dma_addr_t bus;
157 int cnt;
158 int idx;
1e6e9342
AG		 159 struct net_lro_mgr lro_mgr;
160 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 161};
162
163struct myri10ge_priv {
164 int running; /* running? */
165 int csum_flag; /* rx_csums? */
166 struct myri10ge_tx_buf tx; /* transmit ring */
167 struct myri10ge_rx_buf rx_small;
168 struct myri10ge_rx_buf rx_big;
169 struct myri10ge_rx_done rx_done;
170 int small_bytes;
dd50f336 171 int big_bytes;
0da34b6d 172 struct net_device *dev;
bea3348e 173 struct napi_struct napi;
0da34b6d
BG		 174 struct net_device_stats stats;
175 u8 __iomem *sram;
176 int sram_size;
177 unsigned long board_span;
178 unsigned long iomem_base;
40f6cff5
AV		 179 __be32 __iomem *irq_claim;
180 __be32 __iomem *irq_deassert;
0da34b6d
BG		 181 char *mac_addr_string;
182 struct mcp_cmd_response *cmd;
183 dma_addr_t cmd_bus;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 struct pci_dev *pdev;
187 int msi_enabled;
66341fff 188 u32 link_state;
0da34b6d
BG		 189 unsigned int rdma_tags_available;
190 int intr_coal_delay;
40f6cff5 191 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 192 int mtrr;
276e26c3 193 int wc_enabled;
0da34b6d
BG		 194 int wake_queue;
195 int stop_queue;
196 int down_cnt;
197 wait_queue_head_t down_wq;
198 struct work_struct watchdog_work;
199 struct timer_list watchdog_timer;
200 int watchdog_tx_done;
c54772e7 201 int watchdog_tx_req;
626fda94 202 int watchdog_pause;
0da34b6d
BG		 203 int watchdog_resets;
204 int tx_linearized;
205 int pause;
206 char *fw_name;
207 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 208 char *product_code_string;
0da34b6d 209 char fw_version[128];
9dc6f0e7
BG		 210 int fw_ver_major;
211 int fw_ver_minor;
212 int fw_ver_tiny;
213 int adopted_rx_filter_bug;
0da34b6d
BG		 214 u8 mac_addr[6]; /* eeprom mac address */
215 unsigned long serial_number;
216 int vendor_specific_offset;
85a7ea1b 217 int fw_multicast_support;
4f93fde0
BG		 218 unsigned long features;
219 u32 max_tso6;
0da34b6d
BG		 220 u32 read_dma;
221 u32 write_dma;
222 u32 read_write_dma;
c58ac5ca
BG		 223 u32 link_changes;
224 u32 msg_enable;
0da34b6d
BG		 225};
226
227static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
228static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
229
230static char *myri10ge_fw_name = NULL;
231module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 232MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d
BG		 233
234static int myri10ge_ecrc_enable = 1;
235module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 236MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d
BG		 237
238static int myri10ge_max_intr_slots = 1024;
239module_param(myri10ge_max_intr_slots, int, S_IRUGO);
d1ce3a0f 240MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots");
0da34b6d
BG		 241
242static int myri10ge_small_bytes = -1; /* -1 == auto */
243module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 244MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 245
246static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 247module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 248MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 249
f761fae1 250static int myri10ge_intr_coal_delay = 75;
0da34b6d 251module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 252MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 253
254static int myri10ge_flow_control = 1;
255module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 256MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 257
258static int myri10ge_deassert_wait = 1;
259module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
260MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 261 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 262
263static int myri10ge_force_firmware = 0;
264module_param(myri10ge_force_firmware, int, S_IRUGO);
265MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 266 "Force firmware to assume aligned completions");
0da34b6d 267
0da34b6d
BG		 268static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
269module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 270MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 271
272static int myri10ge_napi_weight = 64;
273module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 274MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 275
276static int myri10ge_watchdog_timeout = 1;
277module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 278MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 279
280static int myri10ge_max_irq_loops = 1048576;
281module_param(myri10ge_max_irq_loops, int, S_IRUGO);
282MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 283 "Set stuck legacy IRQ detection threshold");
0da34b6d 284
c58ac5ca
BG		 285#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
286
287static int myri10ge_debug = -1; /* defaults above */
288module_param(myri10ge_debug, int, 0);
289MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
290
1e6e9342
AG		 291static int myri10ge_lro = 1;
292module_param(myri10ge_lro, int, S_IRUGO);
d1ce3a0f 293MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
1e6e9342
AG		 294
295static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
296module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 297MODULE_PARM_DESC(myri10ge_lro_max_pkts,
298 "Number of LRO packets to be aggregated");
1e6e9342 299
dd50f336
BG		 300static int myri10ge_fill_thresh = 256;
301module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 302MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 303
f181137f
BG		 304static int myri10ge_reset_recover = 1;
305
f761fae1 306static int myri10ge_wcfifo = 0;
6ebc087a 307module_param(myri10ge_wcfifo, int, S_IRUGO);
d1ce3a0f 308MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
6ebc087a 309
0da34b6d
BG		 310#define MYRI10GE_FW_OFFSET 1024*1024
311#define MYRI10GE_HIGHPART_TO_U32(X) \
312(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
313#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
314
315#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
316
2f76216f 317static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 318static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 319
6250223e 320static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 321{
6250223e 322 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 323}
324
0da34b6d
BG		 325static int
326myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
327 struct myri10ge_cmd *data, int atomic)
328{
329 struct mcp_cmd *buf;
330 char buf_bytes[sizeof(*buf) + 8];
331 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 332 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 333 u32 dma_low, dma_high, result, value;
334 int sleep_total = 0;
335
336 /* ensure buf is aligned to 8 bytes */
337 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
338
339 buf->data0 = htonl(data->data0);
340 buf->data1 = htonl(data->data1);
341 buf->data2 = htonl(data->data2);
342 buf->cmd = htonl(cmd);
343 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
344 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
345
346 buf->response_addr.low = htonl(dma_low);
347 buf->response_addr.high = htonl(dma_high);
40f6cff5 348 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 349 mb();
350 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
351
352 /* wait up to 15ms. Longest command is the DMA benchmark,
353 * which is capped at 5ms, but runs from a timeout handler
354 * that runs every 7.8ms. So a 15ms timeout leaves us with
355 * a 2.2ms margin
356 */
357 if (atomic) {
358 /* if atomic is set, do not sleep,
359 * and try to get the completion quickly
360 * (1ms will be enough for those commands) */
361 for (sleep_total = 0;
362 sleep_total < 1000
40f6cff5 363 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 364 sleep_total += 10) {
0da34b6d 365 udelay(10);
bd2db0cf
BG		 366 mb();
367 }
0da34b6d
BG		 368 } else {
369 /* use msleep for most command */
370 for (sleep_total = 0;
371 sleep_total < 15
40f6cff5 372 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 373 sleep_total++)
374 msleep(1);
375 }
376
377 result = ntohl(response->result);
378 value = ntohl(response->data);
379 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
380 if (result == 0) {
381 data->data0 = value;
382 return 0;
85a7ea1b
BG		 383 } else if (result == MXGEFW_CMD_UNKNOWN) {
384 return -ENOSYS;
5443e9ea
BG		 385 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
386 return -E2BIG;
0da34b6d
BG		 387 } else {
388 dev_err(&mgp->pdev->dev,
389 "command %d failed, result = %d\n",
390 cmd, result);
391 return -ENXIO;
392 }
393 }
394
395 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
396 cmd, result);
397 return -EAGAIN;
398}
399
400/*
401 * The eeprom strings on the lanaiX have the format
402 * SN=x\0
403 * MAC=x:x:x:x:x:x\0
404 * PT:ddd mmm xx xx:xx:xx xx\0
405 * PV:ddd mmm xx xx:xx:xx xx\0
406 */
407static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
408{
409 char *ptr, *limit;
410 int i;
411
412 ptr = mgp->eeprom_strings;
413 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
414
415 while (*ptr != '\0' && ptr < limit) {
416 if (memcmp(ptr, "MAC=", 4) == 0) {
417 ptr += 4;
418 mgp->mac_addr_string = ptr;
419 for (i = 0; i < 6; i++) {
420 if ((ptr + 2) > limit)
421 goto abort;
422 mgp->mac_addr[i] =
423 simple_strtoul(ptr, &ptr, 16);
424 ptr += 1;
425 }
426 }
c0bf8801
BG		 427 if (memcmp(ptr, "PC=", 3) == 0) {
428 ptr += 3;
429 mgp->product_code_string = ptr;
430 }
0da34b6d
BG		 431 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
432 ptr += 3;
433 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
434 }
435 while (ptr < limit && *ptr++) ;
436 }
437
438 return 0;
439
440abort:
441 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
442 return -ENXIO;
443}
444
445/*
446 * Enable or disable periodic RDMAs from the host to make certain
447 * chipsets resend dropped PCIe messages
448 */
449
450static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
451{
452 char __iomem *submit;
f8fd57c1 453 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 454 u32 dma_low, dma_high;
455 int i;
456
457 /* clear confirmation addr */
458 mgp->cmd->data = 0;
459 mb();
460
461 /* send a rdma command to the PCIe engine, and wait for the
462 * response in the confirmation address. The firmware should
463 * write a -1 there to indicate it is alive and well
464 */
465 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
466 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
467
468 buf[0] = htonl(dma_high); /* confirm addr MSW */
469 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 470 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 471 buf[3] = htonl(dma_high); /* dummy addr MSW */
472 buf[4] = htonl(dma_low); /* dummy addr LSW */
473 buf[5] = htonl(enable); /* enable? */
474
e700f9f4 475 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 476
477 myri10ge_pio_copy(submit, &buf, sizeof(buf));
478 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
479 msleep(1);
480 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
481 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
482 (enable ? "enable" : "disable"));
483}
484
485static int
486myri10ge_validate_firmware(struct myri10ge_priv *mgp,
487 struct mcp_gen_header *hdr)
488{
489 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 490
491 /* check firmware type */
492 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
493 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
494 return -EINVAL;
495 }
496
497 /* save firmware version for ethtool */
498 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
499
9dc6f0e7
BG		 500 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
501 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 502
9dc6f0e7
BG		 503 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
504 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 505 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
506 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
507 MXGEFW_VERSION_MINOR);
508 return -EINVAL;
509 }
510 return 0;
511}
512
513static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
514{
515 unsigned crc, reread_crc;
516 const struct firmware *fw;
517 struct device *dev = &mgp->pdev->dev;
518 struct mcp_gen_header *hdr;
519 size_t hdr_offset;
520 int status;
e454358a 521 unsigned i;
0da34b6d
BG		 522
523 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
524 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
525 mgp->fw_name);
526 status = -EINVAL;
527 goto abort_with_nothing;
528 }
529
530 /* check size */
531
532 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
533 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
534 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
535 status = -EINVAL;
536 goto abort_with_fw;
537 }
538
539 /* check id */
40f6cff5 540 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 541 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
542 dev_err(dev, "Bad firmware file\n");
543 status = -EINVAL;
544 goto abort_with_fw;
545 }
546 hdr = (void *)(fw->data + hdr_offset);
547
548 status = myri10ge_validate_firmware(mgp, hdr);
549 if (status != 0)
550 goto abort_with_fw;
551
552 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 553 for (i = 0; i < fw->size; i += 256) {
554 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
555 fw->data + i,
556 min(256U, (unsigned)(fw->size - i)));
557 mb();
558 readb(mgp->sram);
b10c0668 559 }
0da34b6d
BG		 560 /* corruption checking is good for parity recovery and buggy chipset */
561 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
562 reread_crc = crc32(~0, fw->data, fw->size);
563 if (crc != reread_crc) {
564 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
565 (unsigned)fw->size, reread_crc, crc);
566 status = -EIO;
567 goto abort_with_fw;
568 }
569 *size = (u32) fw->size;
570
571abort_with_fw:
572 release_firmware(fw);
573
574abort_with_nothing:
575 return status;
576}
577
578static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
579{
580 struct mcp_gen_header *hdr;
581 struct device *dev = &mgp->pdev->dev;
582 const size_t bytes = sizeof(struct mcp_gen_header);
583 size_t hdr_offset;
584 int status;
585
586 /* find running firmware header */
66341fff 587 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 588
589 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
590 dev_err(dev, "Running firmware has bad header offset (%d)\n",
591 (int)hdr_offset);
592 return -EIO;
593 }
594
595 /* copy header of running firmware from SRAM to host memory to
596 * validate firmware */
597 hdr = kmalloc(bytes, GFP_KERNEL);
598 if (hdr == NULL) {
599 dev_err(dev, "could not malloc firmware hdr\n");
600 return -ENOMEM;
601 }
602 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
603 status = myri10ge_validate_firmware(mgp, hdr);
604 kfree(hdr);
9dc6f0e7
BG		 605
606 /* check to see if adopted firmware has bug where adopting
607 * it will cause broadcasts to be filtered unless the NIC
608 * is kept in ALLMULTI mode */
609 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
610 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
611 mgp->adopted_rx_filter_bug = 1;
612 dev_warn(dev, "Adopting fw %d.%d.%d: "
613 "working around rx filter bug\n",
614 mgp->fw_ver_major, mgp->fw_ver_minor,
615 mgp->fw_ver_tiny);
616 }
0da34b6d
BG		 617 return status;
618}
619
620static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
621{
622 char __iomem *submit;
f8fd57c1 623 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 624 u32 dma_low, dma_high, size;
625 int status, i;
4f93fde0 626 struct myri10ge_cmd cmd;
0da34b6d 627
b10c0668 628 size = 0;
0da34b6d
BG		 629 status = myri10ge_load_hotplug_firmware(mgp, &size);
630 if (status) {
631 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
632
633 /* Do not attempt to adopt firmware if there
634 * was a bad crc */
635 if (status == -EIO)
636 return status;
637
638 status = myri10ge_adopt_running_firmware(mgp);
639 if (status != 0) {
640 dev_err(&mgp->pdev->dev,
641 "failed to adopt running firmware\n");
642 return status;
643 }
644 dev_info(&mgp->pdev->dev,
645 "Successfully adopted running firmware\n");
646 if (mgp->tx.boundary == 4096) {
647 dev_warn(&mgp->pdev->dev,
648 "Using firmware currently running on NIC"
649 ". For optimal\n");
650 dev_warn(&mgp->pdev->dev,
651 "performance consider loading optimized "
652 "firmware\n");
653 dev_warn(&mgp->pdev->dev, "via hotplug\n");
654 }
655
656 mgp->fw_name = "adopted";
657 mgp->tx.boundary = 2048;
658 return status;
659 }
660
661 /* clear confirmation addr */
662 mgp->cmd->data = 0;
663 mb();
664
665 /* send a reload command to the bootstrap MCP, and wait for the
666 * response in the confirmation address. The firmware should
667 * write a -1 there to indicate it is alive and well
668 */
669 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
670 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
671
672 buf[0] = htonl(dma_high); /* confirm addr MSW */
673 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 674 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 675
676 /* FIX: All newest firmware should un-protect the bottom of
677 * the sram before handoff. However, the very first interfaces
678 * do not. Therefore the handoff copy must skip the first 8 bytes
679 */
680 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
681 buf[4] = htonl(size - 8); /* length of code */
682 buf[5] = htonl(8); /* where to copy to */
683 buf[6] = htonl(0); /* where to jump to */
684
e700f9f4 685 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 686
687 myri10ge_pio_copy(submit, &buf, sizeof(buf));
688 mb();
689 msleep(1);
690 mb();
691 i = 0;
d93ca2a4
BG		 692 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
693 msleep(1 << i);
0da34b6d
BG		 694 i++;
695 }
696 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
697 dev_err(&mgp->pdev->dev, "handoff failed\n");
698 return -ENXIO;
699 }
700 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 701 myri10ge_dummy_rdma(mgp, 1);
0da34b6d 702
4f93fde0
BG		 703 /* probe for IPv6 TSO support */
704 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
705 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
706 &cmd, 0);
707 if (status == 0) {
708 mgp->max_tso6 = cmd.data0;
709 mgp->features |= NETIF_F_TSO6;
710 }
0da34b6d
BG		 711 return 0;
712}
713
714static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
715{
716 struct myri10ge_cmd cmd;
717 int status;
718
719 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
720 | (addr[2] << 8) | addr[3]);
721
722 cmd.data1 = ((addr[4] << 8) | (addr[5]));
723
724 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
725 return status;
726}
727
728static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
729{
730 struct myri10ge_cmd cmd;
731 int status, ctl;
732
733 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
734 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
735
736 if (status) {
737 printk(KERN_ERR
738 "myri10ge: %s: Failed to set flow control mode\n",
739 mgp->dev->name);
740 return status;
741 }
742 mgp->pause = pause;
743 return 0;
744}
745
746static void
747myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
748{
749 struct myri10ge_cmd cmd;
750 int status, ctl;
751
752 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
753 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
754 if (status)
755 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
756 mgp->dev->name);
757}
758
0d6ac257 759static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 760{
761 struct myri10ge_cmd cmd;
762 int status;
0da34b6d 763 u32 len;
34fdccea
BG		 764 struct page *dmatest_page;
765 dma_addr_t dmatest_bus;
0d6ac257
BG		 766 char *test = " ";
767
768 dmatest_page = alloc_page(GFP_KERNEL);
769 if (!dmatest_page)
770 return -ENOMEM;
771 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
772 DMA_BIDIRECTIONAL);
773
774 /* Run a small DMA test.
775 * The magic multipliers to the length tell the firmware
776 * to do DMA read, write, or read+write tests. The
777 * results are returned in cmd.data0. The upper 16
778 * bits or the return is the number of transfers completed.
779 * The lower 16 bits is the time in 0.5us ticks that the
780 * transfers took to complete.
781 */
782
783 len = mgp->tx.boundary;
784
785 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
786 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
787 cmd.data2 = len * 0x10000;
788 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
789 if (status != 0) {
790 test = "read";
791 goto abort;
792 }
793 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
794 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
795 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
796 cmd.data2 = len * 0x1;
797 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
798 if (status != 0) {
799 test = "write";
800 goto abort;
801 }
802 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
803
804 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
805 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
806 cmd.data2 = len * 0x10001;
807 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
808 if (status != 0) {
809 test = "read/write";
810 goto abort;
811 }
812 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
813 (cmd.data0 & 0xffff);
814
815abort:
816 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
817 put_page(dmatest_page);
818
819 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
820 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
821 test, status);
822
823 return status;
824}
825
826static int myri10ge_reset(struct myri10ge_priv *mgp)
827{
828 struct myri10ge_cmd cmd;
829 int status;
830 size_t bytes;
0da34b6d
BG		 831
832 /* try to send a reset command to the card to see if it
833 * is alive */
834 memset(&cmd, 0, sizeof(cmd));
835 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
836 if (status != 0) {
837 dev_err(&mgp->pdev->dev, "failed reset\n");
838 return -ENXIO;
839 }
0d6ac257
BG		 840
841 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0da34b6d
BG		 842
843 /* Now exchange information about interrupts */
844
845 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
846 memset(mgp->rx_done.entry, 0, bytes);
847 cmd.data0 = (u32) bytes;
848 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
849 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
850 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
851 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
852
853 status |=
854 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 855 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 856 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
857 &cmd, 0);
858 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 859
0da34b6d
BG		 860 status |= myri10ge_send_cmd
861 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 862 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 863 if (status != 0) {
864 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
865 return status;
866 }
40f6cff5 867 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 868
0da34b6d
BG		 869 memset(mgp->rx_done.entry, 0, bytes);
870
871 /* reset mcp/driver shared state back to 0 */
872 mgp->tx.req = 0;
873 mgp->tx.done = 0;
874 mgp->tx.pkt_start = 0;
875 mgp->tx.pkt_done = 0;
876 mgp->rx_big.cnt = 0;
877 mgp->rx_small.cnt = 0;
878 mgp->rx_done.idx = 0;
879 mgp->rx_done.cnt = 0;
c58ac5ca 880 mgp->link_changes = 0;
0da34b6d 881 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 882 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 883 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 884 return status;
885}
886
887static inline void
888myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
889 struct mcp_kreq_ether_recv *src)
890{
40f6cff5 891 __be32 low;
0da34b6d
BG		 892
893 low = src->addr_low;
40f6cff5 894 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 895 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
896 mb();
897 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 898 mb();
899 src->addr_low = low;
40f6cff5 900 put_be32(low, &dst->addr_low);
0da34b6d
BG		 901 mb();
902}
903
40f6cff5 904static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 905{
906 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
907
40f6cff5 908 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 909 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
910 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
911 skb->csum = hw_csum;
84fa7933 912 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 913 }
914}
915
dd50f336
BG		 916static inline void
917myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
918 struct skb_frag_struct *rx_frags, int len, int hlen)
919{
920 struct skb_frag_struct *skb_frags;
921
922 skb->len = skb->data_len = len;
923 skb->truesize = len + sizeof(struct sk_buff);
924 /* attach the page(s) */
925
926 skb_frags = skb_shinfo(skb)->frags;
927 while (len > 0) {
928 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
929 len -= rx_frags->size;
930 skb_frags++;
931 rx_frags++;
932 skb_shinfo(skb)->nr_frags++;
933 }
934
935 /* pskb_may_pull is not available in irq context, but
936 * skb_pull() (for ether_pad and eth_type_trans()) requires
937 * the beginning of the packet in skb_headlen(), move it
938 * manually */
27d7ff46 939 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 940 skb_shinfo(skb)->frags[0].page_offset += hlen;
941 skb_shinfo(skb)->frags[0].size -= hlen;
942 skb->data_len -= hlen;
943 skb->tail += hlen;
944 skb_pull(skb, MXGEFW_PAD);
945}
946
947static void
948myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
949 int bytes, int watchdog)
950{
951 struct page *page;
952 int idx;
953
954 if (unlikely(rx->watchdog_needed && !watchdog))
955 return;
956
957 /* try to refill entire ring */
958 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
959 idx = rx->fill_cnt & rx->mask;
ae8509b1 960 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 961 /* we can use part of previous page */
962 get_page(rx->page);
963 } else {
964 /* we need a new page */
965 page =
966 alloc_pages(GFP_ATOMIC | __GFP_COMP,
967 MYRI10GE_ALLOC_ORDER);
968 if (unlikely(page == NULL)) {
969 if (rx->fill_cnt - rx->cnt < 16)
970 rx->watchdog_needed = 1;
971 return;
972 }
973 rx->page = page;
974 rx->page_offset = 0;
975 rx->bus = pci_map_page(mgp->pdev, page, 0,
976 MYRI10GE_ALLOC_SIZE,
977 PCI_DMA_FROMDEVICE);
978 }
979 rx->info[idx].page = rx->page;
980 rx->info[idx].page_offset = rx->page_offset;
981 /* note that this is the address of the start of the
982 * page */
983 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
984 rx->shadow[idx].addr_low =
985 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
986 rx->shadow[idx].addr_high =
987 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
988
989 /* start next packet on a cacheline boundary */
990 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 991
992#if MYRI10GE_ALLOC_SIZE > 4096
993 /* don't cross a 4KB boundary */
994 if ((rx->page_offset >> 12) !=
995 ((rx->page_offset + bytes - 1) >> 12))
996 rx->page_offset = (rx->page_offset + 4096) & ~4095;
997#endif
dd50f336
BG		 998 rx->fill_cnt++;
999
1000 /* copy 8 descriptors to the firmware at a time */
1001 if ((idx & 7) == 7) {
1002 if (rx->wc_fifo == NULL)
1003 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1004 &rx->shadow[idx - 7]);
1005 else {
1006 mb();
1007 myri10ge_pio_copy(rx->wc_fifo,
1008 &rx->shadow[idx - 7], 64);
1009 }
1010 }
1011 }
1012}
1013
1014static inline void
1015myri10ge_unmap_rx_page(struct pci_dev *pdev,
1016 struct myri10ge_rx_buffer_state *info, int bytes)
1017{
1018 /* unmap the recvd page if we're the only or last user of it */
1019 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1020 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1021 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1022 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1023 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1024 }
1025}
1026
1027#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1028 * page into an skb */
1029
1030static inline int
52ea6fb3
BG		 1031myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1032 int bytes, int len, __wsum csum)
dd50f336
BG		 1033{
1034 struct sk_buff *skb;
1035 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1036 int i, idx, hlen, remainder;
1037 struct pci_dev *pdev = mgp->pdev;
1038 struct net_device *dev = mgp->dev;
1039 u8 *va;
1040
1041 len += MXGEFW_PAD;
1042 idx = rx->cnt & rx->mask;
1043 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1044 prefetch(va);
1045 /* Fill skb_frag_struct(s) with data from our receive */
1046 for (i = 0, remainder = len; remainder > 0; i++) {
1047 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1048 rx_frags[i].page = rx->info[idx].page;
1049 rx_frags[i].page_offset = rx->info[idx].page_offset;
1050 if (remainder < MYRI10GE_ALLOC_SIZE)
1051 rx_frags[i].size = remainder;
1052 else
1053 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1054 rx->cnt++;
1055 idx = rx->cnt & rx->mask;
1056 remainder -= MYRI10GE_ALLOC_SIZE;
1057 }
1058
1e6e9342
AG		 1059 if (mgp->csum_flag && myri10ge_lro) {
1060 rx_frags[0].page_offset += MXGEFW_PAD;
1061 rx_frags[0].size -= MXGEFW_PAD;
1062 len -= MXGEFW_PAD;
1063 lro_receive_frags(&mgp->rx_done.lro_mgr, rx_frags,
66341fff
AV		 1064 len, len,
1065 /* opaque, will come back in get_frag_header */
1066 (void *)(__force unsigned long)csum,
1067 csum);
1e6e9342
AG		 1068 return 1;
1069 }
1070
dd50f336
BG		 1071 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1072
e636b2ea
BG		 1073 /* allocate an skb to attach the page(s) to. This is done
1074 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1075
1076 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1077 if (unlikely(skb == NULL)) {
1078 mgp->stats.rx_dropped++;
1079 do {
1080 i--;
1081 put_page(rx_frags[i].page);
1082 } while (i != 0);
1083 return 0;
1084 }
1085
1086 /* Attach the pages to the skb, and trim off any padding */
1087 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1088 if (skb_shinfo(skb)->frags[0].size <= 0) {
1089 put_page(skb_shinfo(skb)->frags[0].page);
1090 skb_shinfo(skb)->nr_frags = 0;
1091 }
1092 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1093
1094 if (mgp->csum_flag) {
1095 if ((skb->protocol == htons(ETH_P_IP)) ||
1096 (skb->protocol == htons(ETH_P_IPV6))) {
1097 skb->csum = csum;
1098 skb->ip_summed = CHECKSUM_COMPLETE;
1099 } else
1100 myri10ge_vlan_ip_csum(skb, csum);
1101 }
1102 netif_receive_skb(skb);
1103 dev->last_rx = jiffies;
1104 return 1;
1105}
1106
0da34b6d
BG		 1107static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1108{
1109 struct pci_dev *pdev = mgp->pdev;
1110 struct myri10ge_tx_buf *tx = &mgp->tx;
1111 struct sk_buff *skb;
1112 int idx, len;
0da34b6d
BG		 1113
1114 while (tx->pkt_done != mcp_index) {
1115 idx = tx->done & tx->mask;
1116 skb = tx->info[idx].skb;
1117
1118 /* Mark as free */
1119 tx->info[idx].skb = NULL;
1120 if (tx->info[idx].last) {
1121 tx->pkt_done++;
1122 tx->info[idx].last = 0;
1123 }
1124 tx->done++;
1125 len = pci_unmap_len(&tx->info[idx], len);
1126 pci_unmap_len_set(&tx->info[idx], len, 0);
1127 if (skb) {
1128 mgp->stats.tx_bytes += skb->len;
1129 mgp->stats.tx_packets++;
1130 dev_kfree_skb_irq(skb);
1131 if (len)
1132 pci_unmap_single(pdev,
1133 pci_unmap_addr(&tx->info[idx],
1134 bus), len,
1135 PCI_DMA_TODEVICE);
1136 } else {
1137 if (len)
1138 pci_unmap_page(pdev,
1139 pci_unmap_addr(&tx->info[idx],
1140 bus), len,
1141 PCI_DMA_TODEVICE);
1142 }
0da34b6d
BG		 1143 }
1144 /* start the queue if we've stopped it */
1145 if (netif_queue_stopped(mgp->dev)
1146 && tx->req - tx->done < (tx->mask >> 1)) {
1147 mgp->wake_queue++;
1148 netif_wake_queue(mgp->dev);
1149 }
1150}
1151
bea3348e 1152static inline int myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int budget)
0da34b6d
BG		 1153{
1154 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1155 unsigned long rx_bytes = 0;
1156 unsigned long rx_packets = 0;
1157 unsigned long rx_ok;
1158
1159 int idx = rx_done->idx;
1160 int cnt = rx_done->cnt;
bea3348e 1161 int work_done = 0;
0da34b6d 1162 u16 length;
40f6cff5 1163 __wsum checksum;
0da34b6d 1164
c956a240 1165 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1166 length = ntohs(rx_done->entry[idx].length);
1167 rx_done->entry[idx].length = 0;
40f6cff5 1168 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1169 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1170 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1171 mgp->small_bytes,
1172 length, checksum);
0da34b6d 1173 else
52ea6fb3
BG		 1174 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1175 mgp->big_bytes,
1176 length, checksum);
0da34b6d
BG		 1177 rx_packets += rx_ok;
1178 rx_bytes += rx_ok * (unsigned long)length;
1179 cnt++;
1180 idx = cnt & (myri10ge_max_intr_slots - 1);
c956a240 1181 work_done++;
0da34b6d
BG		 1182 }
1183 rx_done->idx = idx;
1184 rx_done->cnt = cnt;
1185 mgp->stats.rx_packets += rx_packets;
1186 mgp->stats.rx_bytes += rx_bytes;
c7dab99b 1187
1e6e9342
AG		 1188 if (myri10ge_lro)
1189 lro_flush_all(&rx_done->lro_mgr);
1190
c7dab99b
BG		 1191 /* restock receive rings if needed */
1192 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1193 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1194 mgp->small_bytes + MXGEFW_PAD, 0);
1195 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1196 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1197
bea3348e 1198 return work_done;
0da34b6d
BG		 1199}
1200
1201static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1202{
1203 struct mcp_irq_data *stats = mgp->fw_stats;
1204
1205 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1206 unsigned link_up = ntohl(stats->link_up);
1207 if (mgp->link_state != link_up) {
1208 mgp->link_state = link_up;
1209
1210 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1211 if (netif_msg_link(mgp))
1212 printk(KERN_INFO
1213 "myri10ge: %s: link up\n",
1214 mgp->dev->name);
0da34b6d 1215 netif_carrier_on(mgp->dev);
c58ac5ca 1216 mgp->link_changes++;
0da34b6d 1217 } else {
c58ac5ca
BG		 1218 if (netif_msg_link(mgp))
1219 printk(KERN_INFO
798a95db
BG		 1220 "myri10ge: %s: link %s\n",
1221 mgp->dev->name,
1222 (link_up == MXGEFW_LINK_MYRINET ?
1223 "mismatch (Myrinet detected)" :
1224 "down"));
0da34b6d 1225 netif_carrier_off(mgp->dev);
c58ac5ca 1226 mgp->link_changes++;
0da34b6d
BG		 1227 }
1228 }
1229 if (mgp->rdma_tags_available !=
1230 ntohl(mgp->fw_stats->rdma_tags_available)) {
1231 mgp->rdma_tags_available =
1232 ntohl(mgp->fw_stats->rdma_tags_available);
1233 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1234 "%d tags left\n", mgp->dev->name,
1235 mgp->rdma_tags_available);
1236 }
1237 mgp->down_cnt += stats->link_down;
1238 if (stats->link_down)
1239 wake_up(&mgp->down_wq);
1240 }
1241}
1242
bea3348e 1243static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1244{
e636b2ea
BG		 1245 struct myri10ge_priv *mgp =
1246 container_of(napi, struct myri10ge_priv, napi);
bea3348e 1247 struct net_device *netdev = mgp->dev;
bea3348e 1248 int work_done;
0da34b6d
BG		 1249
1250 /* process as many rx events as NAPI will allow */
bea3348e 1251 work_done = myri10ge_clean_rx_done(mgp, budget);
0da34b6d 1252
4ec24119 1253 if (work_done < budget) {
bea3348e 1254 netif_rx_complete(netdev, napi);
40f6cff5 1255 put_be32(htonl(3), mgp->irq_claim);
0da34b6d 1256 }
bea3348e 1257 return work_done;
0da34b6d
BG		 1258}
1259
7d12e780 1260static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1261{
1262 struct myri10ge_priv *mgp = arg;
1263 struct mcp_irq_data *stats = mgp->fw_stats;
1264 struct myri10ge_tx_buf *tx = &mgp->tx;
1265 u32 send_done_count;
1266 int i;
1267
1268 /* make sure it is our IRQ, and that the DMA has finished */
1269 if (unlikely(!stats->valid))
1270 return (IRQ_NONE);
1271
1272 /* low bit indicates receives are present, so schedule
1273 * napi poll handler */
1274 if (stats->valid & 1)
bea3348e 1275 netif_rx_schedule(mgp->dev, &mgp->napi);
0da34b6d
BG		 1276
1277 if (!mgp->msi_enabled) {
40f6cff5 1278 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1279 if (!myri10ge_deassert_wait)
1280 stats->valid = 0;
1281 mb();
1282 } else
1283 stats->valid = 0;
1284
1285 /* Wait for IRQ line to go low, if using INTx */
1286 i = 0;
1287 while (1) {
1288 i++;
1289 /* check for transmit completes and receives */
1290 send_done_count = ntohl(stats->send_done_count);
1291 if (send_done_count != tx->pkt_done)
1292 myri10ge_tx_done(mgp, (int)send_done_count);
1293 if (unlikely(i > myri10ge_max_irq_loops)) {
1294 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1295 mgp->dev->name);
1296 stats->valid = 0;
1297 schedule_work(&mgp->watchdog_work);
1298 }
1299 if (likely(stats->valid == 0))
1300 break;
1301 cpu_relax();
1302 barrier();
1303 }
1304
1305 myri10ge_check_statblock(mgp);
1306
40f6cff5 1307 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1308 return (IRQ_HANDLED);
1309}
1310
1311static int
1312myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1313{
c0bf8801
BG		 1314 struct myri10ge_priv *mgp = netdev_priv(netdev);
1315 char *ptr;
1316 int i;
1317
0da34b6d
BG		 1318 cmd->autoneg = AUTONEG_DISABLE;
1319 cmd->speed = SPEED_10000;
1320 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1321
1322 /*
1323 * parse the product code to deterimine the interface type
1324 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1325 * after the 3rd dash in the driver's cached copy of the
1326 * EEPROM's product code string.
1327 */
1328 ptr = mgp->product_code_string;
1329 if (ptr == NULL) {
1330 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1331 netdev->name);
1332 return 0;
1333 }
1334 for (i = 0; i < 3; i++, ptr++) {
1335 ptr = strchr(ptr, '-');
1336 if (ptr == NULL) {
1337 printk(KERN_ERR "myri10ge: %s: Invalid product "
1338 "code %s\n", netdev->name,
1339 mgp->product_code_string);
1340 return 0;
1341 }
1342 }
1343 if (*ptr == 'R' || *ptr == 'Q') {
1344 /* We've found either an XFP or quad ribbon fiber */
1345 cmd->port = PORT_FIBRE;
1346 }
0da34b6d
BG		 1347 return 0;
1348}
1349
1350static void
1351myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1352{
1353 struct myri10ge_priv *mgp = netdev_priv(netdev);
1354
1355 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1356 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1357 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1358 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1359}
1360
1361static int
1362myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1363{
1364 struct myri10ge_priv *mgp = netdev_priv(netdev);
1365 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1366 return 0;
1367}
1368
1369static int
1370myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1371{
1372 struct myri10ge_priv *mgp = netdev_priv(netdev);
1373
1374 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1375 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1376 return 0;
1377}
1378
1379static void
1380myri10ge_get_pauseparam(struct net_device *netdev,
1381 struct ethtool_pauseparam *pause)
1382{
1383 struct myri10ge_priv *mgp = netdev_priv(netdev);
1384
1385 pause->autoneg = 0;
1386 pause->rx_pause = mgp->pause;
1387 pause->tx_pause = mgp->pause;
1388}
1389
1390static int
1391myri10ge_set_pauseparam(struct net_device *netdev,
1392 struct ethtool_pauseparam *pause)
1393{
1394 struct myri10ge_priv *mgp = netdev_priv(netdev);
1395
1396 if (pause->tx_pause != mgp->pause)
1397 return myri10ge_change_pause(mgp, pause->tx_pause);
1398 if (pause->rx_pause != mgp->pause)
1399 return myri10ge_change_pause(mgp, pause->tx_pause);
1400 if (pause->autoneg != 0)
1401 return -EINVAL;
1402 return 0;
1403}
1404
1405static void
1406myri10ge_get_ringparam(struct net_device *netdev,
1407 struct ethtool_ringparam *ring)
1408{
1409 struct myri10ge_priv *mgp = netdev_priv(netdev);
1410
1411 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1412 ring->rx_max_pending = mgp->rx_big.mask + 1;
1413 ring->rx_jumbo_max_pending = 0;
1414 ring->tx_max_pending = mgp->rx_small.mask + 1;
1415 ring->rx_mini_pending = ring->rx_mini_max_pending;
1416 ring->rx_pending = ring->rx_max_pending;
1417 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1418 ring->tx_pending = ring->tx_max_pending;
1419}
1420
1421static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1422{
1423 struct myri10ge_priv *mgp = netdev_priv(netdev);
1424 if (mgp->csum_flag)
1425 return 1;
1426 else
1427 return 0;
1428}
1429
1430static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1431{
1432 struct myri10ge_priv *mgp = netdev_priv(netdev);
1433 if (csum_enabled)
1434 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1435 else
1436 mgp->csum_flag = 0;
1437 return 0;
1438}
1439
4f93fde0
BG		 1440static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1441{
1442 struct myri10ge_priv *mgp = netdev_priv(netdev);
1443 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1444
1445 if (tso_enabled)
1446 netdev->features |= flags;
1447 else
1448 netdev->features &= ~flags;
1449 return 0;
1450}
1451
0da34b6d
BG		 1452static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1453 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1454 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1455 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1456 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1457 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1458 "tx_heartbeat_errors", "tx_window_errors",
1459 /* device-specific stats */
2c1a1088 1460 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1461 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1462 "serial_number", "tx_pkt_start", "tx_pkt_done",
1463 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1464 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1465 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1466 "dropped_link_error_or_filtered",
1467 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1468 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1469 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1e6e9342
AG		 1470 "dropped_no_big_buffer", "LRO aggregated", "LRO flushed",
1471 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1472};
1473
1474#define MYRI10GE_NET_STATS_LEN 21
4c3616cd 1475#define MYRI10GE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_stats)
0da34b6d
BG		 1476
1477static void
1478myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1479{
1480 switch (stringset) {
1481 case ETH_SS_STATS:
1482 memcpy(data, *myri10ge_gstrings_stats,
1483 sizeof(myri10ge_gstrings_stats));
1484 break;
1485 }
1486}
1487
b9f2c044 1488static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1489{
b9f2c044
JG		 1490 switch (sset) {
1491 case ETH_SS_STATS:
1492 return MYRI10GE_STATS_LEN;
1493 default:
1494 return -EOPNOTSUPP;
1495 }
0da34b6d
BG		 1496}
1497
1498static void
1499myri10ge_get_ethtool_stats(struct net_device *netdev,
1500 struct ethtool_stats *stats, u64 * data)
1501{
1502 struct myri10ge_priv *mgp = netdev_priv(netdev);
1503 int i;
1504
1505 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1506 data[i] = ((unsigned long *)&mgp->stats)[i];
1507
2c1a1088 1508 data[i++] = (unsigned int)mgp->tx.boundary;
276e26c3 1509 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1510 data[i++] = (unsigned int)mgp->pdev->irq;
1511 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1512 data[i++] = (unsigned int)mgp->read_dma;
1513 data[i++] = (unsigned int)mgp->write_dma;
1514 data[i++] = (unsigned int)mgp->read_write_dma;
1515 data[i++] = (unsigned int)mgp->serial_number;
1516 data[i++] = (unsigned int)mgp->tx.pkt_start;
1517 data[i++] = (unsigned int)mgp->tx.pkt_done;
1518 data[i++] = (unsigned int)mgp->tx.req;
1519 data[i++] = (unsigned int)mgp->tx.done;
1520 data[i++] = (unsigned int)mgp->rx_small.cnt;
1521 data[i++] = (unsigned int)mgp->rx_big.cnt;
1522 data[i++] = (unsigned int)mgp->wake_queue;
1523 data[i++] = (unsigned int)mgp->stop_queue;
1524 data[i++] = (unsigned int)mgp->watchdog_resets;
1525 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1526 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1527 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1528 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1529 data[i++] =
1530 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
cee505db
BG		 1531 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1532 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1533 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1534 data[i++] =
1535 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
85a7ea1b
BG		 1536 data[i++] =
1537 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1538 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1539 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1540 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1541 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1e6e9342
AG		 1542 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated;
1543 data[i++] = mgp->rx_done.lro_mgr.stats.flushed;
1544 if (mgp->rx_done.lro_mgr.stats.flushed)
1545 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated /
1546 mgp->rx_done.lro_mgr.stats.flushed;
1547 else
1548 data[i++] = 0;
1549 data[i++] = mgp->rx_done.lro_mgr.stats.no_desc;
0da34b6d
BG		 1550}
1551
c58ac5ca
BG		 1552static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1553{
1554 struct myri10ge_priv *mgp = netdev_priv(netdev);
1555 mgp->msg_enable = value;
1556}
1557
1558static u32 myri10ge_get_msglevel(struct net_device *netdev)
1559{
1560 struct myri10ge_priv *mgp = netdev_priv(netdev);
1561 return mgp->msg_enable;
1562}
1563
7282d491 1564static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1565 .get_settings = myri10ge_get_settings,
1566 .get_drvinfo = myri10ge_get_drvinfo,
1567 .get_coalesce = myri10ge_get_coalesce,
1568 .set_coalesce = myri10ge_set_coalesce,
1569 .get_pauseparam = myri10ge_get_pauseparam,
1570 .set_pauseparam = myri10ge_set_pauseparam,
1571 .get_ringparam = myri10ge_get_ringparam,
1572 .get_rx_csum = myri10ge_get_rx_csum,
1573 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1574 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1575 .set_sg = ethtool_op_set_sg,
4f93fde0 1576 .set_tso = myri10ge_set_tso,
6ffdd071 1577 .get_link = ethtool_op_get_link,
0da34b6d 1578 .get_strings = myri10ge_get_strings,
b9f2c044 1579 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1580 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1581 .set_msglevel = myri10ge_set_msglevel,
1582 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1583};
1584
1585static int myri10ge_allocate_rings(struct net_device *dev)
1586{
1587 struct myri10ge_priv *mgp;
1588 struct myri10ge_cmd cmd;
1589 int tx_ring_size, rx_ring_size;
1590 int tx_ring_entries, rx_ring_entries;
1591 int i, status;
1592 size_t bytes;
1593
1594 mgp = netdev_priv(dev);
1595
1596 /* get ring sizes */
1597
1598 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1599 tx_ring_size = cmd.data0;
1600 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1601 if (status != 0)
1602 return status;
0da34b6d
BG		 1603 rx_ring_size = cmd.data0;
1604
1605 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1606 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1607 mgp->tx.mask = tx_ring_entries - 1;
1608 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1609
355c7265
BG		 1610 status = -ENOMEM;
1611
0da34b6d
BG		 1612 /* allocate the host shadow rings */
1613
1614 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1615 * sizeof(*mgp->tx.req_list);
1616 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1617 if (mgp->tx.req_bytes == NULL)
1618 goto abort_with_nothing;
1619
1620 /* ensure req_list entries are aligned to 8 bytes */
1621 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1622 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1623
1624 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1625 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1626 if (mgp->rx_small.shadow == NULL)
1627 goto abort_with_tx_req_bytes;
1628
1629 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1630 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1631 if (mgp->rx_big.shadow == NULL)
1632 goto abort_with_rx_small_shadow;
1633
1634 /* allocate the host info rings */
1635
1636 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1637 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1638 if (mgp->tx.info == NULL)
1639 goto abort_with_rx_big_shadow;
1640
1641 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1642 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1643 if (mgp->rx_small.info == NULL)
1644 goto abort_with_tx_info;
1645
1646 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1647 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1648 if (mgp->rx_big.info == NULL)
1649 goto abort_with_rx_small_info;
1650
1651 /* Fill the receive rings */
c7dab99b
BG		 1652 mgp->rx_big.cnt = 0;
1653 mgp->rx_small.cnt = 0;
1654 mgp->rx_big.fill_cnt = 0;
1655 mgp->rx_small.fill_cnt = 0;
1656 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1657 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1658 mgp->rx_small.watchdog_needed = 0;
1659 mgp->rx_big.watchdog_needed = 0;
1660 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1661 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1662
c7dab99b
BG		 1663 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1664 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1665 dev->name, mgp->rx_small.fill_cnt);
1666 goto abort_with_rx_small_ring;
0da34b6d
BG		 1667 }
1668
c7dab99b
BG		 1669 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1670 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1671 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1672 dev->name, mgp->rx_big.fill_cnt);
1673 goto abort_with_rx_big_ring;
0da34b6d
BG		 1674 }
1675
1676 return 0;
1677
1678abort_with_rx_big_ring:
c7dab99b
BG		 1679 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1680 int idx = i & mgp->rx_big.mask;
1681 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1682 mgp->big_bytes);
1683 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1684 }
1685
1686abort_with_rx_small_ring:
c7dab99b
BG		 1687 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1688 int idx = i & mgp->rx_small.mask;
1689 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1690 mgp->small_bytes + MXGEFW_PAD);
1691 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1692 }
c7dab99b 1693
0da34b6d
BG		 1694 kfree(mgp->rx_big.info);
1695
1696abort_with_rx_small_info:
1697 kfree(mgp->rx_small.info);
1698
1699abort_with_tx_info:
1700 kfree(mgp->tx.info);
1701
1702abort_with_rx_big_shadow:
1703 kfree(mgp->rx_big.shadow);
1704
1705abort_with_rx_small_shadow:
1706 kfree(mgp->rx_small.shadow);
1707
1708abort_with_tx_req_bytes:
1709 kfree(mgp->tx.req_bytes);
1710 mgp->tx.req_bytes = NULL;
1711 mgp->tx.req_list = NULL;
1712
1713abort_with_nothing:
1714 return status;
1715}
1716
1717static void myri10ge_free_rings(struct net_device *dev)
1718{
1719 struct myri10ge_priv *mgp;
1720 struct sk_buff *skb;
1721 struct myri10ge_tx_buf *tx;
1722 int i, len, idx;
1723
1724 mgp = netdev_priv(dev);
1725
c7dab99b
BG		 1726 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1727 idx = i & mgp->rx_big.mask;
1728 if (i == mgp->rx_big.fill_cnt - 1)
1729 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1730 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1731 mgp->big_bytes);
1732 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1733 }
1734
c7dab99b
BG		 1735 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1736 idx = i & mgp->rx_small.mask;
1737 if (i == mgp->rx_small.fill_cnt - 1)
1738 mgp->rx_small.info[idx].page_offset =
1739 MYRI10GE_ALLOC_SIZE;
1740 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1741 mgp->small_bytes + MXGEFW_PAD);
1742 put_page(mgp->rx_small.info[idx].page);
1743 }
0da34b6d
BG		 1744 tx = &mgp->tx;
1745 while (tx->done != tx->req) {
1746 idx = tx->done & tx->mask;
1747 skb = tx->info[idx].skb;
1748
1749 /* Mark as free */
1750 tx->info[idx].skb = NULL;
1751 tx->done++;
1752 len = pci_unmap_len(&tx->info[idx], len);
1753 pci_unmap_len_set(&tx->info[idx], len, 0);
1754 if (skb) {
1755 mgp->stats.tx_dropped++;
1756 dev_kfree_skb_any(skb);
1757 if (len)
1758 pci_unmap_single(mgp->pdev,
1759 pci_unmap_addr(&tx->info[idx],
1760 bus), len,
1761 PCI_DMA_TODEVICE);
1762 } else {
1763 if (len)
1764 pci_unmap_page(mgp->pdev,
1765 pci_unmap_addr(&tx->info[idx],
1766 bus), len,
1767 PCI_DMA_TODEVICE);
1768 }
1769 }
1770 kfree(mgp->rx_big.info);
1771
1772 kfree(mgp->rx_small.info);
1773
1774 kfree(mgp->tx.info);
1775
1776 kfree(mgp->rx_big.shadow);
1777
1778 kfree(mgp->rx_small.shadow);
1779
1780 kfree(mgp->tx.req_bytes);
1781 mgp->tx.req_bytes = NULL;
1782 mgp->tx.req_list = NULL;
1783}
1784
df30a740
BG		 1785static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1786{
1787 struct pci_dev *pdev = mgp->pdev;
1788 int status;
1789
1790 if (myri10ge_msi) {
1791 status = pci_enable_msi(pdev);
1792 if (status != 0)
1793 dev_err(&pdev->dev,
1794 "Error %d setting up MSI; falling back to xPIC\n",
1795 status);
1796 else
1797 mgp->msi_enabled = 1;
1798 } else {
1799 mgp->msi_enabled = 0;
1800 }
1801 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1802 mgp->dev->name, mgp);
1803 if (status != 0) {
1804 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1805 if (mgp->msi_enabled)
1806 pci_disable_msi(pdev);
1807 }
1808 return status;
1809}
1810
1811static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1812{
1813 struct pci_dev *pdev = mgp->pdev;
1814
1815 free_irq(pdev->irq, mgp);
1816 if (mgp->msi_enabled)
1817 pci_disable_msi(pdev);
1818}
1819
1e6e9342
AG		 1820static int
1821myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1822 void **ip_hdr, void **tcpudp_hdr,
1823 u64 * hdr_flags, void *priv)
1824{
1825 struct ethhdr *eh;
1826 struct vlan_ethhdr *veh;
1827 struct iphdr *iph;
1828 u8 *va = page_address(frag->page) + frag->page_offset;
1829 unsigned long ll_hlen;
66341fff
AV		 1830 /* passed opaque through lro_receive_frags() */
1831 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 1832
1833 /* find the mac header, aborting if not IPv4 */
1834
1835 eh = (struct ethhdr *)va;
1836 *mac_hdr = eh;
1837 ll_hlen = ETH_HLEN;
1838 if (eh->h_proto != htons(ETH_P_IP)) {
1839 if (eh->h_proto == htons(ETH_P_8021Q)) {
1840 veh = (struct vlan_ethhdr *)va;
1841 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1842 return -1;
1843
1844 ll_hlen += VLAN_HLEN;
1845
1846 /*
1847 * HW checksum starts ETH_HLEN bytes into
1848 * frame, so we must subtract off the VLAN
1849 * header's checksum before csum can be used
1850 */
1851 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1852 VLAN_HLEN, 0));
1853 } else {
1854 return -1;
1855 }
1856 }
1857 *hdr_flags = LRO_IPV4;
1858
1859 iph = (struct iphdr *)(va + ll_hlen);
1860 *ip_hdr = iph;
1861 if (iph->protocol != IPPROTO_TCP)
1862 return -1;
1863 *hdr_flags |= LRO_TCP;
1864 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1865
1866 /* verify the IP checksum */
1867 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1868 return -1;
1869
1870 /* verify the checksum */
1871 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1872 ntohs(iph->tot_len) - (iph->ihl << 2),
1873 IPPROTO_TCP, csum)))
1874 return -1;
1875
1876 return 0;
1877}
1878
0da34b6d
BG		 1879static int myri10ge_open(struct net_device *dev)
1880{
1881 struct myri10ge_priv *mgp;
1882 struct myri10ge_cmd cmd;
1e6e9342 1883 struct net_lro_mgr *lro_mgr;
0da34b6d
BG		 1884 int status, big_pow2;
1885
1886 mgp = netdev_priv(dev);
1887
1888 if (mgp->running != MYRI10GE_ETH_STOPPED)
1889 return -EBUSY;
1890
1891 mgp->running = MYRI10GE_ETH_STARTING;
1892 status = myri10ge_reset(mgp);
1893 if (status != 0) {
1894 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1895 goto abort_with_nothing;
0da34b6d
BG		 1896 }
1897
df30a740
BG		 1898 status = myri10ge_request_irq(mgp);
1899 if (status != 0)
1900 goto abort_with_nothing;
1901
0da34b6d
BG		 1902 /* decide what small buffer size to use. For good TCP rx
1903 * performance, it is important to not receive 1514 byte
1904 * frames into jumbo buffers, as it confuses the socket buffer
1905 * accounting code, leading to drops and erratic performance.
1906 */
1907
1908 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1909 /* enough for a TCP header */
1910 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1911 ? (128 - MXGEFW_PAD)
1912 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1913 else
de3c4507
BG		 1914 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1915 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1916
1917 /* Override the small buffer size? */
1918 if (myri10ge_small_bytes > 0)
1919 mgp->small_bytes = myri10ge_small_bytes;
1920
0da34b6d
BG		 1921 /* get the lanai pointers to the send and receive rings */
1922
1923 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1924 mgp->tx.lanai =
1925 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1926
1927 status |=
1928 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1929 mgp->rx_small.lanai =
1930 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1931
1932 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1933 mgp->rx_big.lanai =
1934 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1935
1936 if (status != 0) {
1937 printk(KERN_ERR
1938 "myri10ge: %s: failed to get ring sizes or locations\n",
1939 dev->name);
1940 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1941 goto abort_with_irq;
0da34b6d
BG		 1942 }
1943
276e26c3 1944 if (myri10ge_wcfifo && mgp->wc_enabled) {
e700f9f4
BG		 1945 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1946 mgp->rx_small.wc_fifo =
1947 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1948 mgp->rx_big.wc_fifo =
1949 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1950 } else {
1951 mgp->tx.wc_fifo = NULL;
1952 mgp->rx_small.wc_fifo = NULL;
1953 mgp->rx_big.wc_fifo = NULL;
1954 }
1955
0da34b6d
BG		 1956 /* Firmware needs the big buff size as a power of 2. Lie and
1957 * tell him the buffer is larger, because we only use 1
1958 * buffer/pkt, and the mtu will prevent overruns.
1959 */
13348bee 1960 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 1961 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 1962 while (!is_power_of_2(big_pow2))
c7dab99b 1963 big_pow2++;
13348bee 1964 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1965 } else {
1966 big_pow2 = MYRI10GE_ALLOC_SIZE;
1967 mgp->big_bytes = big_pow2;
1968 }
1969
1970 status = myri10ge_allocate_rings(dev);
1971 if (status != 0)
df30a740 1972 goto abort_with_irq;
0da34b6d
BG		 1973
1974 /* now give firmware buffers sizes, and MTU */
1975 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1976 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1977 cmd.data0 = mgp->small_bytes;
1978 status |=
1979 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1980 cmd.data0 = big_pow2;
1981 status |=
1982 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1983 if (status) {
1984 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1985 dev->name);
1986 goto abort_with_rings;
1987 }
1988
1989 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1990 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1991 cmd.data2 = sizeof(struct mcp_irq_data);
1992 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1993 if (status == -ENOSYS) {
1994 dma_addr_t bus = mgp->fw_stats_bus;
1995 bus += offsetof(struct mcp_irq_data, send_done_count);
1996 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1997 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1998 status = myri10ge_send_cmd(mgp,
1999 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2000 &cmd, 0);
2001 /* Firmware cannot support multicast without STATS_DMA_V2 */
2002 mgp->fw_multicast_support = 0;
2003 } else {
2004 mgp->fw_multicast_support = 1;
2005 }
0da34b6d
BG		 2006 if (status) {
2007 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
2008 dev->name);
2009 goto abort_with_rings;
2010 }
2011
66341fff 2012 mgp->link_state = ~0U;
0da34b6d
BG		 2013 mgp->rdma_tags_available = 15;
2014
1e6e9342
AG		 2015 lro_mgr = &mgp->rx_done.lro_mgr;
2016 lro_mgr->dev = dev;
2017 lro_mgr->features = LRO_F_NAPI;
2018 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2019 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2020 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2021 lro_mgr->lro_arr = mgp->rx_done.lro_desc;
2022 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2023 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
621544eb 2024 lro_mgr->frag_align_pad = 2;
1e6e9342
AG		 2025 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2026 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2027
bea3348e 2028 napi_enable(&mgp->napi); /* must happen prior to any irq */
0da34b6d
BG		 2029
2030 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2031 if (status) {
2032 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2033 dev->name);
2034 goto abort_with_rings;
2035 }
2036
2037 mgp->wake_queue = 0;
2038 mgp->stop_queue = 0;
2039 mgp->running = MYRI10GE_ETH_RUNNING;
2040 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2041 add_timer(&mgp->watchdog_timer);
2042 netif_wake_queue(dev);
2043 return 0;
2044
2045abort_with_rings:
2046 myri10ge_free_rings(dev);
2047
df30a740
BG		 2048abort_with_irq:
2049 myri10ge_free_irq(mgp);
2050
0da34b6d
BG		 2051abort_with_nothing:
2052 mgp->running = MYRI10GE_ETH_STOPPED;
2053 return -ENOMEM;
2054}
2055
2056static int myri10ge_close(struct net_device *dev)
2057{
2058 struct myri10ge_priv *mgp;
2059 struct myri10ge_cmd cmd;
2060 int status, old_down_cnt;
2061
2062 mgp = netdev_priv(dev);
2063
2064 if (mgp->running != MYRI10GE_ETH_RUNNING)
2065 return 0;
2066
2067 if (mgp->tx.req_bytes == NULL)
2068 return 0;
2069
2070 del_timer_sync(&mgp->watchdog_timer);
2071 mgp->running = MYRI10GE_ETH_STOPPING;
bea3348e 2072 napi_disable(&mgp->napi);
0da34b6d
BG		 2073 netif_carrier_off(dev);
2074 netif_stop_queue(dev);
2075 old_down_cnt = mgp->down_cnt;
2076 mb();
2077 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2078 if (status)
2079 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2080 dev->name);
2081
2082 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2083 if (old_down_cnt == mgp->down_cnt)
2084 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2085
2086 netif_tx_disable(dev);
df30a740 2087 myri10ge_free_irq(mgp);
0da34b6d
BG		 2088 myri10ge_free_rings(dev);
2089
2090 mgp->running = MYRI10GE_ETH_STOPPED;
2091 return 0;
2092}
2093
2094/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2095 * backwards one at a time and handle ring wraps */
2096
2097static inline void
2098myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2099 struct mcp_kreq_ether_send *src, int cnt)
2100{
2101 int idx, starting_slot;
2102 starting_slot = tx->req;
2103 while (cnt > 1) {
2104 cnt--;
2105 idx = (starting_slot + cnt) & tx->mask;
2106 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2107 mb();
2108 }
2109}
2110
2111/*
2112 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2113 * at most 32 bytes at a time, so as to avoid involving the software
2114 * pio handler in the nic. We re-write the first segment's flags
2115 * to mark them valid only after writing the entire chain.
2116 */
2117
2118static inline void
2119myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2120 int cnt)
2121{
2122 int idx, i;
2123 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2124 struct mcp_kreq_ether_send *srcp;
2125 u8 last_flags;
2126
2127 idx = tx->req & tx->mask;
2128
2129 last_flags = src->flags;
2130 src->flags = 0;
2131 mb();
2132 dst = dstp = &tx->lanai[idx];
2133 srcp = src;
2134
2135 if ((idx + cnt) < tx->mask) {
2136 for (i = 0; i < (cnt - 1); i += 2) {
2137 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2138 mb(); /* force write every 32 bytes */
2139 srcp += 2;
2140 dstp += 2;
2141 }
2142 } else {
2143 /* submit all but the first request, and ensure
2144 * that it is submitted below */
2145 myri10ge_submit_req_backwards(tx, src, cnt);
2146 i = 0;
2147 }
2148 if (i < cnt) {
2149 /* submit the first request */
2150 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2151 mb(); /* barrier before setting valid flag */
2152 }
2153
2154 /* re-write the last 32-bits with the valid flags */
2155 src->flags = last_flags;
40f6cff5 2156 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2157 tx->req += cnt;
2158 mb();
2159}
2160
2161static inline void
2162myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2163 struct mcp_kreq_ether_send *src, int cnt)
2164{
2165 tx->req += cnt;
2166 mb();
2167 while (cnt >= 4) {
2168 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2169 mb();
2170 src += 4;
2171 cnt -= 4;
2172 }
2173 if (cnt > 0) {
2174 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2175 * needs to be so that we don't overrun it */
e700f9f4
BG		 2176 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2177 src, 64);
0da34b6d
BG		 2178 mb();
2179 }
2180}
2181
2182/*
2183 * Transmit a packet. We need to split the packet so that a single
2184 * segment does not cross myri10ge->tx.boundary, so this makes segment
2185 * counting tricky. So rather than try to count segments up front, we
2186 * just give up if there are too few segments to hold a reasonably
2187 * fragmented packet currently available. If we run
2188 * out of segments while preparing a packet for DMA, we just linearize
2189 * it and try again.
2190 */
2191
2192static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2193{
2194 struct myri10ge_priv *mgp = netdev_priv(dev);
2195 struct mcp_kreq_ether_send *req;
2196 struct myri10ge_tx_buf *tx = &mgp->tx;
2197 struct skb_frag_struct *frag;
2198 dma_addr_t bus;
40f6cff5
AV		 2199 u32 low;
2200 __be32 high_swapped;
0da34b6d
BG		 2201 unsigned int len;
2202 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2203 u16 pseudo_hdr_offset, cksum_offset;
2204 int cum_len, seglen, boundary, rdma_count;
2205 u8 flags, odd_flag;
2206
2207again:
2208 req = tx->req_list;
2209 avail = tx->mask - 1 - (tx->req - tx->done);
2210
2211 mss = 0;
2212 max_segments = MXGEFW_MAX_SEND_DESC;
2213
917690cd 2214 if (skb_is_gso(skb)) {
7967168c 2215 mss = skb_shinfo(skb)->gso_size;
917690cd 2216 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2217 }
0da34b6d
BG		 2218
2219 if ((unlikely(avail < max_segments))) {
2220 /* we are out of transmit resources */
2221 mgp->stop_queue++;
2222 netif_stop_queue(dev);
2223 return 1;
2224 }
2225
2226 /* Setup checksum offloading, if needed */
2227 cksum_offset = 0;
2228 pseudo_hdr_offset = 0;
2229 odd_flag = 0;
2230 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2231 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2232 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2233 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2234 /* If the headers are excessively large, then we must
2235 * fall back to a software checksum */
4f93fde0
BG		 2236 if (unlikely(!mss && (cksum_offset > 255 ||
2237 pseudo_hdr_offset > 127))) {
84fa7933 2238 if (skb_checksum_help(skb))
0da34b6d
BG		 2239 goto drop;
2240 cksum_offset = 0;
2241 pseudo_hdr_offset = 0;
2242 } else {
0da34b6d
BG		 2243 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2244 flags |= MXGEFW_FLAGS_CKSUM;
2245 }
2246 }
2247
2248 cum_len = 0;
2249
0da34b6d
BG		 2250 if (mss) { /* TSO */
2251 /* this removes any CKSUM flag from before */
2252 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2253
2254 /* negative cum_len signifies to the
2255 * send loop that we are still in the
2256 * header portion of the TSO packet.
4f93fde0 2257 * TSO header can be at most 1KB long */
ab6a5bb6 2258 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2259
4f93fde0
BG		 2260 /* for IPv6 TSO, the checksum offset stores the
2261 * TCP header length, to save the firmware from
2262 * the need to parse the headers */
2263 if (skb_is_gso_v6(skb)) {
2264 cksum_offset = tcp_hdrlen(skb);
2265 /* Can only handle headers <= max_tso6 long */
2266 if (unlikely(-cum_len > mgp->max_tso6))
2267 return myri10ge_sw_tso(skb, dev);
2268 }
0da34b6d
BG		 2269 /* for TSO, pseudo_hdr_offset holds mss.
2270 * The firmware figures out where to put
2271 * the checksum by parsing the header. */
40f6cff5 2272 pseudo_hdr_offset = mss;
0da34b6d 2273 } else
0da34b6d
BG		 2274 /* Mark small packets, and pad out tiny packets */
2275 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2276 flags |= MXGEFW_FLAGS_SMALL;
2277
2278 /* pad frames to at least ETH_ZLEN bytes */
2279 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2280 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2281 /* The packet is gone, so we must
2282 * return 0 */
2283 mgp->stats.tx_dropped += 1;
2284 return 0;
2285 }
2286 /* adjust the len to account for the zero pad
2287 * so that the nic can know how long it is */
2288 skb->len = ETH_ZLEN;
2289 }
2290 }
2291
2292 /* map the skb for DMA */
2293 len = skb->len - skb->data_len;
2294 idx = tx->req & tx->mask;
2295 tx->info[idx].skb = skb;
2296 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2297 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2298 pci_unmap_len_set(&tx->info[idx], len, len);
2299
2300 frag_cnt = skb_shinfo(skb)->nr_frags;
2301 frag_idx = 0;
2302 count = 0;
2303 rdma_count = 0;
2304
2305 /* "rdma_count" is the number of RDMAs belonging to the
2306 * current packet BEFORE the current send request. For
2307 * non-TSO packets, this is equal to "count".
2308 * For TSO packets, rdma_count needs to be reset
2309 * to 0 after a segment cut.
2310 *
2311 * The rdma_count field of the send request is
2312 * the number of RDMAs of the packet starting at
2313 * that request. For TSO send requests with one ore more cuts
2314 * in the middle, this is the number of RDMAs starting
2315 * after the last cut in the request. All previous
2316 * segments before the last cut implicitly have 1 RDMA.
2317 *
2318 * Since the number of RDMAs is not known beforehand,
2319 * it must be filled-in retroactively - after each
2320 * segmentation cut or at the end of the entire packet.
2321 */
2322
2323 while (1) {
2324 /* Break the SKB or Fragment up into pieces which
2325 * do not cross mgp->tx.boundary */
2326 low = MYRI10GE_LOWPART_TO_U32(bus);
2327 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2328 while (len) {
2329 u8 flags_next;
2330 int cum_len_next;
2331
2332 if (unlikely(count == max_segments))
2333 goto abort_linearize;
2334
2335 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2336 seglen = boundary - low;
2337 if (seglen > len)
2338 seglen = len;
2339 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2340 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2341 if (mss) { /* TSO */
2342 (req - rdma_count)->rdma_count = rdma_count + 1;
2343
2344 if (likely(cum_len >= 0)) { /* payload */
2345 int next_is_first, chop;
2346
2347 chop = (cum_len_next > mss);
2348 cum_len_next = cum_len_next % mss;
2349 next_is_first = (cum_len_next == 0);
2350 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2351 flags_next |= next_is_first *
2352 MXGEFW_FLAGS_FIRST;
2353 rdma_count |= -(chop | next_is_first);
2354 rdma_count += chop & !next_is_first;
2355 } else if (likely(cum_len_next >= 0)) { /* header ends */
2356 int small;
2357
2358 rdma_count = -1;
2359 cum_len_next = 0;
2360 seglen = -cum_len;
2361 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2362 flags_next = MXGEFW_FLAGS_TSO_PLD |
2363 MXGEFW_FLAGS_FIRST |
2364 (small * MXGEFW_FLAGS_SMALL);
2365 }
2366 }
0da34b6d
BG		 2367 req->addr_high = high_swapped;
2368 req->addr_low = htonl(low);
40f6cff5 2369 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2370 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2371 req->rdma_count = 1;
2372 req->length = htons(seglen);
2373 req->cksum_offset = cksum_offset;
2374 req->flags = flags | ((cum_len & 1) * odd_flag);
2375
2376 low += seglen;
2377 len -= seglen;
2378 cum_len = cum_len_next;
2379 flags = flags_next;
2380 req++;
2381 count++;
2382 rdma_count++;
4f93fde0
BG		 2383 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2384 if (unlikely(cksum_offset > seglen))
2385 cksum_offset -= seglen;
2386 else
2387 cksum_offset = 0;
2388 }
0da34b6d
BG		 2389 }
2390 if (frag_idx == frag_cnt)
2391 break;
2392
2393 /* map next fragment for DMA */
2394 idx = (count + tx->req) & tx->mask;
2395 frag = &skb_shinfo(skb)->frags[frag_idx];
2396 frag_idx++;
2397 len = frag->size;
2398 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2399 len, PCI_DMA_TODEVICE);
2400 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2401 pci_unmap_len_set(&tx->info[idx], len, len);
2402 }
2403
2404 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2405 if (mss)
2406 do {
2407 req--;
2408 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2409 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2410 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2411 idx = ((count - 1) + tx->req) & tx->mask;
2412 tx->info[idx].last = 1;
2413 if (tx->wc_fifo == NULL)
2414 myri10ge_submit_req(tx, tx->req_list, count);
2415 else
2416 myri10ge_submit_req_wc(tx, tx->req_list, count);
2417 tx->pkt_start++;
2418 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2419 mgp->stop_queue++;
2420 netif_stop_queue(dev);
2421 }
2422 dev->trans_start = jiffies;
2423 return 0;
2424
2425abort_linearize:
2426 /* Free any DMA resources we've alloced and clear out the skb
2427 * slot so as to not trip up assertions, and to avoid a
2428 * double-free if linearizing fails */
2429
2430 last_idx = (idx + 1) & tx->mask;
2431 idx = tx->req & tx->mask;
2432 tx->info[idx].skb = NULL;
2433 do {
2434 len = pci_unmap_len(&tx->info[idx], len);
2435 if (len) {
2436 if (tx->info[idx].skb != NULL)
2437 pci_unmap_single(mgp->pdev,
2438 pci_unmap_addr(&tx->info[idx],
2439 bus), len,
2440 PCI_DMA_TODEVICE);
2441 else
2442 pci_unmap_page(mgp->pdev,
2443 pci_unmap_addr(&tx->info[idx],
2444 bus), len,
2445 PCI_DMA_TODEVICE);
2446 pci_unmap_len_set(&tx->info[idx], len, 0);
2447 tx->info[idx].skb = NULL;
2448 }
2449 idx = (idx + 1) & tx->mask;
2450 } while (idx != last_idx);
89114afd 2451 if (skb_is_gso(skb)) {
0da34b6d
BG		 2452 printk(KERN_ERR
2453 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2454 mgp->dev->name);
2455 goto drop;
2456 }
2457
bec0e859 2458 if (skb_linearize(skb))
0da34b6d
BG		 2459 goto drop;
2460
2461 mgp->tx_linearized++;
2462 goto again;
2463
2464drop:
2465 dev_kfree_skb_any(skb);
2466 mgp->stats.tx_dropped += 1;
2467 return 0;
2468
2469}
2470
4f93fde0
BG		 2471static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2472{
2473 struct sk_buff *segs, *curr;
2474 struct myri10ge_priv *mgp = dev->priv;
2475 int status;
2476
2477 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2478 if (IS_ERR(segs))
4f93fde0
BG		 2479 goto drop;
2480
2481 while (segs) {
2482 curr = segs;
2483 segs = segs->next;
2484 curr->next = NULL;
2485 status = myri10ge_xmit(curr, dev);
2486 if (status != 0) {
2487 dev_kfree_skb_any(curr);
2488 if (segs != NULL) {
2489 curr = segs;
2490 segs = segs->next;
2491 curr->next = NULL;
2492 dev_kfree_skb_any(segs);
2493 }
2494 goto drop;
2495 }
2496 }
2497 dev_kfree_skb_any(skb);
2498 return 0;
2499
2500drop:
2501 dev_kfree_skb_any(skb);
2502 mgp->stats.tx_dropped += 1;
2503 return 0;
2504}
2505
0da34b6d
BG		 2506static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2507{
2508 struct myri10ge_priv *mgp = netdev_priv(dev);
2509 return &mgp->stats;
2510}
2511
2512static void myri10ge_set_multicast_list(struct net_device *dev)
2513{
85a7ea1b
BG		 2514 struct myri10ge_cmd cmd;
2515 struct myri10ge_priv *mgp;
2516 struct dev_mc_list *mc_list;
6250223e 2517 __be32 data[2] = { 0, 0 };
85a7ea1b 2518 int err;
0795af57 2519 DECLARE_MAC_BUF(mac);
85a7ea1b
BG		 2520
2521 mgp = netdev_priv(dev);
0da34b6d
BG		 2522 /* can be called from atomic contexts,
2523 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2524 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2525
2526 /* This firmware is known to not support multicast */
2f76216f 2527 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2528 return;
2529
2530 /* Disable multicast filtering */
2531
2532 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2533 if (err != 0) {
2534 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2535 " error status: %d\n", dev->name, err);
2536 goto abort;
2537 }
2538
2f76216f 2539 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2540 /* request to disable multicast filtering, so quit here */
2541 return;
2542 }
2543
2544 /* Flush the filters */
2545
2546 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2547 &cmd, 1);
2548 if (err != 0) {
2549 printk(KERN_ERR
2550 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2551 ", error status: %d\n", dev->name, err);
2552 goto abort;
2553 }
2554
2555 /* Walk the multicast list, and add each address */
2556 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2557 memcpy(data, &mc_list->dmi_addr, 6);
2558 cmd.data0 = ntohl(data[0]);
2559 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2560 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2561 &cmd, 1);
2562
2563 if (err != 0) {
2564 printk(KERN_ERR "myri10ge: %s: Failed "
2565 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2566 "%d\t", dev->name, err);
0795af57
JP		 2567 printk(KERN_ERR "MAC %s\n",
2568 print_mac(mac, mc_list->dmi_addr));
85a7ea1b
BG		 2569 goto abort;
2570 }
2571 }
2572 /* Enable multicast filtering */
2573 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2574 if (err != 0) {
2575 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2576 "error status: %d\n", dev->name, err);
2577 goto abort;
2578 }
2579
2580 return;
2581
2582abort:
2583 return;
0da34b6d
BG		 2584}
2585
2586static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2587{
2588 struct sockaddr *sa = addr;
2589 struct myri10ge_priv *mgp = netdev_priv(dev);
2590 int status;
2591
2592 if (!is_valid_ether_addr(sa->sa_data))
2593 return -EADDRNOTAVAIL;
2594
2595 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2596 if (status != 0) {
2597 printk(KERN_ERR
2598 "myri10ge: %s: changing mac address failed with %d\n",
2599 dev->name, status);
2600 return status;
2601 }
2602
2603 /* change the dev structure */
2604 memcpy(dev->dev_addr, sa->sa_data, 6);
2605 return 0;
2606}
2607
2608static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2609{
2610 struct myri10ge_priv *mgp = netdev_priv(dev);
2611 int error = 0;
2612
2613 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2614 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2615 dev->name, new_mtu);
2616 return -EINVAL;
2617 }
2618 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2619 dev->name, dev->mtu, new_mtu);
2620 if (mgp->running) {
2621 /* if we change the mtu on an active device, we must
2622 * reset the device so the firmware sees the change */
2623 myri10ge_close(dev);
2624 dev->mtu = new_mtu;
2625 myri10ge_open(dev);
2626 } else
2627 dev->mtu = new_mtu;
2628
2629 return error;
2630}
2631
2632/*
2633 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2634 * Only do it if the bridge is a root port since we don't want to disturb
2635 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2636 */
2637
0da34b6d
BG		 2638static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2639{
2640 struct pci_dev *bridge = mgp->pdev->bus->self;
2641 struct device *dev = &mgp->pdev->dev;
2642 unsigned cap;
2643 unsigned err_cap;
2644 u16 val;
2645 u8 ext_type;
2646 int ret;
2647
2648 if (!myri10ge_ecrc_enable || !bridge)
2649 return;
2650
2651 /* check that the bridge is a root port */
2652 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2653 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2654 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2655 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2656 if (myri10ge_ecrc_enable > 1) {
2657 struct pci_dev *old_bridge = bridge;
2658
2659 /* Walk the hierarchy up to the root port
2660 * where ECRC has to be enabled */
2661 do {
2662 bridge = bridge->bus->self;
2663 if (!bridge) {
2664 dev_err(dev,
2665 "Failed to find root port"
2666 " to force ECRC\n");
2667 return;
2668 }
2669 cap =
2670 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2671 pci_read_config_word(bridge,
2672 cap + PCI_CAP_FLAGS, &val);
2673 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2674 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2675
2676 dev_info(dev,
2677 "Forcing ECRC on non-root port %s"
2678 " (enabling on root port %s)\n",
2679 pci_name(old_bridge), pci_name(bridge));
2680 } else {
2681 dev_err(dev,
2682 "Not enabling ECRC on non-root port %s\n",
2683 pci_name(bridge));
2684 return;
2685 }
2686 }
2687
2688 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2689 if (!cap)
2690 return;
2691
2692 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2693 if (ret) {
2694 dev_err(dev, "failed reading ext-conf-space of %s\n",
2695 pci_name(bridge));
2696 dev_err(dev, "\t pci=nommconf in use? "
2697 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2698 return;
2699 }
2700 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2701 return;
2702
2703 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2704 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2705 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 2706}
2707
2708/*
2709 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2710 * when the PCI-E Completion packets are aligned on an 8-byte
2711 * boundary. Some PCI-E chip sets always align Completion packets; on
2712 * the ones that do not, the alignment can be enforced by enabling
2713 * ECRC generation (if supported).
2714 *
2715 * When PCI-E Completion packets are not aligned, it is actually more
2716 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2717 *
2718 * If the driver can neither enable ECRC nor verify that it has
2719 * already been enabled, then it must use a firmware image which works
2720 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2721 * should also ensure that it never gives the device a Read-DMA which is
2722 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2723 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2724 * firmware image, and set tx.boundary to 4KB.
2725 */
2726
5443e9ea 2727static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 2728{
5443e9ea
BG		 2729 struct pci_dev *pdev = mgp->pdev;
2730 struct device *dev = &pdev->dev;
302d242c 2731 int status;
0da34b6d 2732
5443e9ea
BG		 2733 mgp->tx.boundary = 4096;
2734 /*
2735 * Verify the max read request size was set to 4KB
2736 * before trying the test with 4KB.
2737 */
302d242c
BG		 2738 status = pcie_get_readrq(pdev);
2739 if (status < 0) {
5443e9ea
BG		 2740 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2741 goto abort;
2742 }
302d242c
BG		 2743 if (status != 4096) {
2744 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
5443e9ea
BG		 2745 mgp->tx.boundary = 2048;
2746 }
2747 /*
2748 * load the optimized firmware (which assumes aligned PCIe
2749 * completions) in order to see if it works on this host.
2750 */
2751 mgp->fw_name = myri10ge_fw_aligned;
2752 status = myri10ge_load_firmware(mgp);
2753 if (status != 0) {
2754 goto abort;
2755 }
2756
2757 /*
2758 * Enable ECRC if possible
2759 */
2760 myri10ge_enable_ecrc(mgp);
2761
2762 /*
2763 * Run a DMA test which watches for unaligned completions and
2764 * aborts on the first one seen.
2765 */
2766
2767 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2768 if (status == 0)
2769 return; /* keep the aligned firmware */
2770
2771 if (status != -E2BIG)
2772 dev_warn(dev, "DMA test failed: %d\n", status);
2773 if (status == -ENOSYS)
2774 dev_warn(dev, "Falling back to ethp! "
2775 "Please install up to date fw\n");
2776abort:
2777 /* fall back to using the unaligned firmware */
0da34b6d
BG		 2778 mgp->tx.boundary = 2048;
2779 mgp->fw_name = myri10ge_fw_unaligned;
2780
5443e9ea
BG		 2781}
2782
2783static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2784{
0da34b6d 2785 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2786 int link_width, exp_cap;
2787 u16 lnk;
2788
2789 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2790 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2791 link_width = (lnk >> 4) & 0x3f;
2792
ce7f9368
BG		 2793 /* Check to see if Link is less than 8 or if the
2794 * upstream bridge is known to provide aligned
2795 * completions */
2796 if (link_width < 8) {
2797 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2798 link_width);
2799 mgp->tx.boundary = 4096;
2800 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 2801 } else {
2802 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 2803 }
2804 } else {
2805 if (myri10ge_force_firmware == 1) {
2806 dev_info(&mgp->pdev->dev,
2807 "Assuming aligned completions (forced)\n");
2808 mgp->tx.boundary = 4096;
2809 mgp->fw_name = myri10ge_fw_aligned;
2810 } else {
2811 dev_info(&mgp->pdev->dev,
2812 "Assuming unaligned completions (forced)\n");
2813 mgp->tx.boundary = 2048;
2814 mgp->fw_name = myri10ge_fw_unaligned;
2815 }
2816 }
2817 if (myri10ge_fw_name != NULL) {
2818 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2819 myri10ge_fw_name);
2820 mgp->fw_name = myri10ge_fw_name;
2821 }
2822}
2823
0da34b6d 2824#ifdef CONFIG_PM
0da34b6d
BG		 2825static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2826{
2827 struct myri10ge_priv *mgp;
2828 struct net_device *netdev;
2829
2830 mgp = pci_get_drvdata(pdev);
2831 if (mgp == NULL)
2832 return -EINVAL;
2833 netdev = mgp->dev;
2834
2835 netif_device_detach(netdev);
2836 if (netif_running(netdev)) {
2837 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2838 rtnl_lock();
2839 myri10ge_close(netdev);
2840 rtnl_unlock();
2841 }
2842 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2843 pci_save_state(pdev);
0da34b6d 2844 pci_disable_device(pdev);
1a63e846
BG		 2845
2846 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2847}
2848
2849static int myri10ge_resume(struct pci_dev *pdev)
2850{
2851 struct myri10ge_priv *mgp;
2852 struct net_device *netdev;
2853 int status;
2854 u16 vendor;
2855
2856 mgp = pci_get_drvdata(pdev);
2857 if (mgp == NULL)
2858 return -EINVAL;
2859 netdev = mgp->dev;
2860 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2861 msleep(5); /* give card time to respond */
2862 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2863 if (vendor == 0xffff) {
2864 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2865 mgp->dev->name);
2866 return -EIO;
2867 }
83f6e152 2868
1a63e846
BG		 2869 status = pci_restore_state(pdev);
2870 if (status)
2871 return status;
4c2248cc
BG		 2872
2873 status = pci_enable_device(pdev);
1a63e846 2874 if (status) {
4c2248cc 2875 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2876 return status;
4c2248cc
BG		 2877 }
2878
0da34b6d
BG		 2879 pci_set_master(pdev);
2880
0da34b6d 2881 myri10ge_reset(mgp);
013b68bf 2882 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2883
2884 /* Save configuration space to be restored if the
2885 * nic resets due to a parity error */
83f6e152 2886 pci_save_state(pdev);
0da34b6d
BG		 2887
2888 if (netif_running(netdev)) {
2889 rtnl_lock();
df30a740 2890 status = myri10ge_open(netdev);
0da34b6d 2891 rtnl_unlock();
df30a740
BG		 2892 if (status != 0)
2893 goto abort_with_enabled;
2894
0da34b6d
BG		 2895 }
2896 netif_device_attach(netdev);
2897
2898 return 0;
2899
4c2248cc
BG		 2900abort_with_enabled:
2901 pci_disable_device(pdev);
0da34b6d
BG		 2902 return -EIO;
2903
2904}
0da34b6d
BG		 2905#endif /* CONFIG_PM */
2906
2907static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2908{
2909 struct pci_dev *pdev = mgp->pdev;
2910 int vs = mgp->vendor_specific_offset;
2911 u32 reboot;
2912
2913 /*enter read32 mode */
2914 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2915
2916 /*read REBOOT_STATUS (0xfffffff0) */
2917 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2918 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2919 return reboot;
2920}
2921
2922/*
2923 * This watchdog is used to check whether the board has suffered
2924 * from a parity error and needs to be recovered.
2925 */
c4028958 2926static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2927{
c4028958 2928 struct myri10ge_priv *mgp =
6250223e 2929 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2930 u32 reboot;
2931 int status;
2932 u16 cmd, vendor;
2933
2934 mgp->watchdog_resets++;
2935 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2936 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2937 /* Bus master DMA disabled? Check to see
2938 * if the card rebooted due to a parity error
2939 * For now, just report it */
2940 reboot = myri10ge_read_reboot(mgp);
2941 printk(KERN_ERR
f181137f
BG		 2942 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2943 mgp->dev->name, reboot,
2944 myri10ge_reset_recover ? " " : " not");
2945 if (myri10ge_reset_recover == 0)
2946 return;
2947
2948 myri10ge_reset_recover--;
2949
0da34b6d
BG		 2950 /*
2951 * A rebooted nic will come back with config space as
2952 * it was after power was applied to PCIe bus.
2953 * Attempt to restore config space which was saved
2954 * when the driver was loaded, or the last time the
2955 * nic was resumed from power saving mode.
2956 */
83f6e152 2957 pci_restore_state(mgp->pdev);
7adda30c
BG		 2958
2959 /* save state again for accounting reasons */
83f6e152 2960 pci_save_state(mgp->pdev);
7adda30c 2961
0da34b6d
BG		 2962 } else {
2963 /* if we get back -1's from our slot, perhaps somebody
2964 * powered off our card. Don't try to reset it in
2965 * this case */
2966 if (cmd == 0xffff) {
2967 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2968 if (vendor == 0xffff) {
2969 printk(KERN_ERR
2970 "myri10ge: %s: device disappeared!\n",
2971 mgp->dev->name);
2972 return;
2973 }
2974 }
2975 /* Perhaps it is a software error. Try to reset */
2976
2977 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2978 mgp->dev->name);
2979 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2980 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2981 mgp->tx.pkt_start, mgp->tx.pkt_done,
2982 (int)ntohl(mgp->fw_stats->send_done_count));
2983 msleep(2000);
2984 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2985 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2986 mgp->tx.pkt_start, mgp->tx.pkt_done,
2987 (int)ntohl(mgp->fw_stats->send_done_count));
2988 }
2989 rtnl_lock();
2990 myri10ge_close(mgp->dev);
2991 status = myri10ge_load_firmware(mgp);
2992 if (status != 0)
2993 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2994 mgp->dev->name);
2995 else
2996 myri10ge_open(mgp->dev);
2997 rtnl_unlock();
2998}
2999
3000/*
3001 * We use our own timer routine rather than relying upon
3002 * netdev->tx_timeout because we have a very large hardware transmit
3003 * queue. Due to the large queue, the netdev->tx_timeout function
3004 * cannot detect a NIC with a parity error in a timely fashion if the
3005 * NIC is lightly loaded.
3006 */
3007static void myri10ge_watchdog_timer(unsigned long arg)
3008{
3009 struct myri10ge_priv *mgp;
626fda94 3010 u32 rx_pause_cnt;
0da34b6d
BG		 3011
3012 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 3013
3014 if (mgp->rx_small.watchdog_needed) {
3015 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
3016 mgp->small_bytes + MXGEFW_PAD, 1);
3017 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
3018 myri10ge_fill_thresh)
3019 mgp->rx_small.watchdog_needed = 0;
3020 }
3021 if (mgp->rx_big.watchdog_needed) {
3022 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
3023 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
3024 myri10ge_fill_thresh)
3025 mgp->rx_big.watchdog_needed = 0;
3026 }
626fda94 3027 rx_pause_cnt = ntohl(mgp->fw_stats->dropped_pause);
c7dab99b 3028
0da34b6d 3029 if (mgp->tx.req != mgp->tx.done &&
c54772e7 3030 mgp->tx.done == mgp->watchdog_tx_done &&
626fda94 3031 mgp->watchdog_tx_req != mgp->watchdog_tx_done) {
0da34b6d 3032 /* nic seems like it might be stuck.. */
626fda94
BG		 3033 if (rx_pause_cnt != mgp->watchdog_pause) {
3034 if (net_ratelimit())
3035 printk(KERN_WARNING "myri10ge %s:"
3036 "TX paused, check link partner\n",
3037 mgp->dev->name);
3038 } else {
3039 schedule_work(&mgp->watchdog_work);
3040 return;
3041 }
3042 }
3043 /* rearm timer */
3044 mod_timer(&mgp->watchdog_timer,
3045 jiffies + myri10ge_watchdog_timeout * HZ);
0da34b6d 3046 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 3047 mgp->watchdog_tx_req = mgp->tx.req;
626fda94 3048 mgp->watchdog_pause = rx_pause_cnt;
0da34b6d
BG		 3049}
3050
3051static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3052{
3053 struct net_device *netdev;
3054 struct myri10ge_priv *mgp;
3055 struct device *dev = &pdev->dev;
3056 size_t bytes;
3057 int i;
3058 int status = -ENXIO;
0da34b6d 3059 int dac_enabled;
0da34b6d
BG		 3060
3061 netdev = alloc_etherdev(sizeof(*mgp));
3062 if (netdev == NULL) {
3063 dev_err(dev, "Could not allocate ethernet device\n");
3064 return -ENOMEM;
3065 }
3066
b245fb67
MH		 3067 SET_NETDEV_DEV(netdev, &pdev->dev);
3068
0da34b6d 3069 mgp = netdev_priv(netdev);
0da34b6d 3070 mgp->dev = netdev;
e636b2ea 3071 netif_napi_add(netdev, &mgp->napi, myri10ge_poll, myri10ge_napi_weight);
0da34b6d
BG		 3072 mgp->pdev = pdev;
3073 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3074 mgp->pause = myri10ge_flow_control;
3075 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3076 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 3077 init_waitqueue_head(&mgp->down_wq);
3078
3079 if (pci_enable_device(pdev)) {
3080 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3081 status = -ENODEV;
3082 goto abort_with_netdev;
3083 }
0da34b6d
BG		 3084
3085 /* Find the vendor-specific cap so we can check
3086 * the reboot register later on */
3087 mgp->vendor_specific_offset
3088 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3089
3090 /* Set our max read request to 4KB */
302d242c 3091 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3092 if (status != 0) {
3093 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3094 status);
3095 goto abort_with_netdev;
3096 }
3097
3098 pci_set_master(pdev);
3099 dac_enabled = 1;
3100 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3101 if (status != 0) {
3102 dac_enabled = 0;
3103 dev_err(&pdev->dev,
898eb71c
JP		 3104 "64-bit pci address mask was refused, "
3105 "trying 32-bit\n");
0da34b6d
BG		 3106 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3107 }
3108 if (status != 0) {
3109 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3110 goto abort_with_netdev;
3111 }
b10c0668
BG		 3112 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3113 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 3114 if (mgp->cmd == NULL)
3115 goto abort_with_netdev;
3116
b10c0668
BG		 3117 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3118 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 3119 if (mgp->fw_stats == NULL)
3120 goto abort_with_cmd;
3121
3122 mgp->board_span = pci_resource_len(pdev, 0);
3123 mgp->iomem_base = pci_resource_start(pdev, 0);
3124 mgp->mtrr = -1;
276e26c3 3125 mgp->wc_enabled = 0;
0da34b6d
BG		 3126#ifdef CONFIG_MTRR
3127 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3128 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3129 if (mgp->mtrr >= 0)
3130 mgp->wc_enabled = 1;
0da34b6d
BG		 3131#endif
3132 /* Hack. need to get rid of these magic numbers */
3133 mgp->sram_size =
3134 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3135 if (mgp->sram_size > mgp->board_span) {
3136 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3137 mgp->board_span);
3138 goto abort_with_wc;
3139 }
3140 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3141 if (mgp->sram == NULL) {
3142 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3143 mgp->board_span, mgp->iomem_base);
3144 status = -ENXIO;
3145 goto abort_with_wc;
3146 }
3147 memcpy_fromio(mgp->eeprom_strings,
3148 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3149 MYRI10GE_EEPROM_STRINGS_SIZE);
3150 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3151 status = myri10ge_read_mac_addr(mgp);
3152 if (status)
3153 goto abort_with_ioremap;
3154
3155 for (i = 0; i < ETH_ALEN; i++)
3156 netdev->dev_addr[i] = mgp->mac_addr[i];
3157
3158 /* allocate rx done ring */
3159 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3160 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3161 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 3162 if (mgp->rx_done.entry == NULL)
3163 goto abort_with_ioremap;
3164 memset(mgp->rx_done.entry, 0, bytes);
3165
5443e9ea
BG		 3166 myri10ge_select_firmware(mgp);
3167
0da34b6d
BG		 3168 status = myri10ge_load_firmware(mgp);
3169 if (status != 0) {
3170 dev_err(&pdev->dev, "failed to load firmware\n");
3171 goto abort_with_rx_done;
3172 }
3173
3174 status = myri10ge_reset(mgp);
3175 if (status != 0) {
3176 dev_err(&pdev->dev, "failed reset\n");
3177 goto abort_with_firmware;
3178 }
3179
0da34b6d
BG		 3180 pci_set_drvdata(pdev, mgp);
3181 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3182 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3183 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3184 myri10ge_initial_mtu = 68;
3185 netdev->mtu = myri10ge_initial_mtu;
3186 netdev->open = myri10ge_open;
3187 netdev->stop = myri10ge_close;
3188 netdev->hard_start_xmit = myri10ge_xmit;
3189 netdev->get_stats = myri10ge_get_stats;
3190 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 3191 netdev->change_mtu = myri10ge_change_mtu;
3192 netdev->set_multicast_list = myri10ge_set_multicast_list;
3193 netdev->set_mac_address = myri10ge_set_mac_address;
4f93fde0 3194 netdev->features = mgp->features;
0da34b6d
BG		 3195 if (dac_enabled)
3196 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3197
21d05db1
BG		 3198 /* make sure we can get an irq, and that MSI can be
3199 * setup (if available). Also ensure netdev->irq
3200 * is set to correct value if MSI is enabled */
3201 status = myri10ge_request_irq(mgp);
3202 if (status != 0)
3203 goto abort_with_firmware;
3204 netdev->irq = pdev->irq;
3205 myri10ge_free_irq(mgp);
3206
0da34b6d
BG		 3207 /* Save configuration space to be restored if the
3208 * nic resets due to a parity error */
83f6e152 3209 pci_save_state(pdev);
0da34b6d
BG		 3210
3211 /* Setup the watchdog timer */
3212 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3213 (unsigned long)mgp);
3214
3215 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3216 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3217 status = register_netdev(netdev);
3218 if (status != 0) {
3219 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3220 goto abort_with_state;
0da34b6d 3221 }
21d05db1
BG		 3222 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3223 (mgp->msi_enabled ? "MSI" : "xPIC"),
3224 netdev->irq, mgp->tx.boundary, mgp->fw_name,
276e26c3 3225 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3226
3227 return 0;
3228
7adda30c 3229abort_with_state:
83f6e152 3230 pci_restore_state(pdev);
0da34b6d
BG		 3231
3232abort_with_firmware:
3233 myri10ge_dummy_rdma(mgp, 0);
3234
3235abort_with_rx_done:
3236 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3237 dma_free_coherent(&pdev->dev, bytes,
3238 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3239
3240abort_with_ioremap:
3241 iounmap(mgp->sram);
3242
3243abort_with_wc:
3244#ifdef CONFIG_MTRR
3245 if (mgp->mtrr >= 0)
3246 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3247#endif
b10c0668
BG		 3248 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3249 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 3250
3251abort_with_cmd:
b10c0668
BG		 3252 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3253 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3254
3255abort_with_netdev:
3256
3257 free_netdev(netdev);
3258 return status;
3259}
3260
3261/*
3262 * myri10ge_remove
3263 *
3264 * Does what is necessary to shutdown one Myrinet device. Called
3265 * once for each Myrinet card by the kernel when a module is
3266 * unloaded.
3267 */
3268static void myri10ge_remove(struct pci_dev *pdev)
3269{
3270 struct myri10ge_priv *mgp;
3271 struct net_device *netdev;
3272 size_t bytes;
3273
3274 mgp = pci_get_drvdata(pdev);
3275 if (mgp == NULL)
3276 return;
3277
3278 flush_scheduled_work();
3279 netdev = mgp->dev;
3280 unregister_netdev(netdev);
0da34b6d
BG		 3281
3282 myri10ge_dummy_rdma(mgp, 0);
3283
7adda30c 3284 /* avoid a memory leak */
83f6e152 3285 pci_restore_state(pdev);
7adda30c 3286
0da34b6d 3287 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3288 dma_free_coherent(&pdev->dev, bytes,
3289 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3290
3291 iounmap(mgp->sram);
3292
3293#ifdef CONFIG_MTRR
3294 if (mgp->mtrr >= 0)
3295 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3296#endif
b10c0668
BG		 3297 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3298 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3299
b10c0668
BG		 3300 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3301 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3302
3303 free_netdev(netdev);
3304 pci_set_drvdata(pdev, NULL);
3305}
3306
b10c0668 3307#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3308#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 3309
3310static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3311 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3312 {PCI_DEVICE
3313 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3314 {0},
3315};
3316
3317static struct pci_driver myri10ge_driver = {
3318 .name = "myri10ge",
3319 .probe = myri10ge_probe,
3320 .remove = myri10ge_remove,
3321 .id_table = myri10ge_pci_tbl,
3322#ifdef CONFIG_PM
3323 .suspend = myri10ge_suspend,
3324 .resume = myri10ge_resume,
3325#endif
3326};
3327
3328static __init int myri10ge_init_module(void)
3329{
3330 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3331 MYRI10GE_VERSION_STR);
3332 return pci_register_driver(&myri10ge_driver);
3333}
3334
3335module_init(myri10ge_init_module);
3336
3337static __exit void myri10ge_cleanup_module(void)
3338{
3339 pci_unregister_driver(&myri10ge_driver);
3340}
3341
3342module_exit(myri10ge_cleanup_module);
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