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0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
51#include <linux/ip.h>
52#include <linux/inet.h>
53#include <linux/in.h>
54#include <linux/ethtool.h>
55#include <linux/firmware.h>
56#include <linux/delay.h>
57#include <linux/version.h>
58#include <linux/timer.h>
59#include <linux/vmalloc.h>
60#include <linux/crc32.h>
61#include <linux/moduleparam.h>
62#include <linux/io.h>
63#include <net/checksum.h>
64#include <asm/byteorder.h>
65#include <asm/io.h>
0da34b6d
BG		 66#include <asm/processor.h>
67#ifdef CONFIG_MTRR
68#include <asm/mtrr.h>
69#endif
70
71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h"
73
4b2281c7 74#define MYRI10GE_VERSION_STR "1.3.0-1.233"
0da34b6d
BG		 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com");
78MODULE_VERSION(MYRI10GE_VERSION_STR);
79MODULE_LICENSE("Dual BSD/GPL");
80
81#define MYRI10GE_MAX_ETHER_MTU 9014
82
83#define MYRI10GE_ETH_STOPPED 0
84#define MYRI10GE_ETH_STOPPING 1
85#define MYRI10GE_ETH_STARTING 2
86#define MYRI10GE_ETH_RUNNING 3
87#define MYRI10GE_ETH_OPEN_FAILED 4
88
89#define MYRI10GE_EEPROM_STRINGS_SIZE 256
90#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
40f6cff5 92#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 93#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
dd50f336
BG		 95#define MYRI10GE_ALLOC_ORDER 0
96#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
97#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
98
0da34b6d 99struct myri10ge_rx_buffer_state {
dd50f336
BG		 100 struct page *page;
101 int page_offset;
0da34b6d
BG		 102 DECLARE_PCI_UNMAP_ADDR(bus)
103 DECLARE_PCI_UNMAP_LEN(len)
104};
105
106struct myri10ge_tx_buffer_state {
107 struct sk_buff *skb;
108 int last;
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
111};
112
113struct myri10ge_cmd {
114 u32 data0;
115 u32 data1;
116 u32 data2;
117};
118
119struct myri10ge_rx_buf {
120 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
121 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
122 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
123 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 124 struct page *page;
125 dma_addr_t bus;
126 int page_offset;
0da34b6d 127 int cnt;
dd50f336 128 int fill_cnt;
0da34b6d
BG		 129 int alloc_fail;
130 int mask; /* number of rx slots -1 */
dd50f336 131 int watchdog_needed;
0da34b6d
BG		 132};
133
134struct myri10ge_tx_buf {
135 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
136 u8 __iomem *wc_fifo; /* w/c send fifo address */
137 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
138 char *req_bytes;
139 struct myri10ge_tx_buffer_state *info;
140 int mask; /* number of transmit slots -1 */
141 int boundary; /* boundary transmits cannot cross */
142 int req ____cacheline_aligned; /* transmit slots submitted */
143 int pkt_start; /* packets started */
144 int done ____cacheline_aligned; /* transmit slots completed */
145 int pkt_done; /* packets completed */
146};
147
148struct myri10ge_rx_done {
149 struct mcp_slot *entry;
150 dma_addr_t bus;
151 int cnt;
152 int idx;
153};
154
155struct myri10ge_priv {
156 int running; /* running? */
157 int csum_flag; /* rx_csums? */
158 struct myri10ge_tx_buf tx; /* transmit ring */
159 struct myri10ge_rx_buf rx_small;
160 struct myri10ge_rx_buf rx_big;
161 struct myri10ge_rx_done rx_done;
162 int small_bytes;
dd50f336 163 int big_bytes;
0da34b6d
BG		 164 struct net_device *dev;
165 struct net_device_stats stats;
166 u8 __iomem *sram;
167 int sram_size;
168 unsigned long board_span;
169 unsigned long iomem_base;
40f6cff5
AV		 170 __be32 __iomem *irq_claim;
171 __be32 __iomem *irq_deassert;
0da34b6d
BG		 172 char *mac_addr_string;
173 struct mcp_cmd_response *cmd;
174 dma_addr_t cmd_bus;
175 struct mcp_irq_data *fw_stats;
176 dma_addr_t fw_stats_bus;
177 struct pci_dev *pdev;
178 int msi_enabled;
40f6cff5 179 __be32 link_state;
0da34b6d
BG		 180 unsigned int rdma_tags_available;
181 int intr_coal_delay;
40f6cff5 182 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 183 int mtrr;
276e26c3 184 int wc_enabled;
0da34b6d
BG		 185 int wake_queue;
186 int stop_queue;
187 int down_cnt;
188 wait_queue_head_t down_wq;
189 struct work_struct watchdog_work;
190 struct timer_list watchdog_timer;
191 int watchdog_tx_done;
c54772e7 192 int watchdog_tx_req;
0da34b6d
BG		 193 int watchdog_resets;
194 int tx_linearized;
195 int pause;
196 char *fw_name;
197 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
198 char fw_version[128];
9dc6f0e7
BG		 199 int fw_ver_major;
200 int fw_ver_minor;
201 int fw_ver_tiny;
202 int adopted_rx_filter_bug;
0da34b6d
BG		 203 u8 mac_addr[6]; /* eeprom mac address */
204 unsigned long serial_number;
205 int vendor_specific_offset;
85a7ea1b 206 int fw_multicast_support;
0da34b6d
BG		 207 u32 read_dma;
208 u32 write_dma;
209 u32 read_write_dma;
c58ac5ca
BG		 210 u32 link_changes;
211 u32 msg_enable;
0da34b6d
BG		 212};
213
214static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
215static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
216
217static char *myri10ge_fw_name = NULL;
218module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
219MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
220
221static int myri10ge_ecrc_enable = 1;
222module_param(myri10ge_ecrc_enable, int, S_IRUGO);
223MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
224
225static int myri10ge_max_intr_slots = 1024;
226module_param(myri10ge_max_intr_slots, int, S_IRUGO);
227MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
228
229static int myri10ge_small_bytes = -1; /* -1 == auto */
230module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
231MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
232
233static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 234module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
0da34b6d
BG		 235MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
236
f761fae1 237static int myri10ge_intr_coal_delay = 75;
0da34b6d
BG		 238module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
239MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
240
241static int myri10ge_flow_control = 1;
242module_param(myri10ge_flow_control, int, S_IRUGO);
243MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
244
245static int myri10ge_deassert_wait = 1;
246module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
247MODULE_PARM_DESC(myri10ge_deassert_wait,
248 "Wait when deasserting legacy interrupts\n");
249
250static int myri10ge_force_firmware = 0;
251module_param(myri10ge_force_firmware, int, S_IRUGO);
252MODULE_PARM_DESC(myri10ge_force_firmware,
253 "Force firmware to assume aligned completions\n");
254
0da34b6d
BG		 255static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
256module_param(myri10ge_initial_mtu, int, S_IRUGO);
257MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
258
259static int myri10ge_napi_weight = 64;
260module_param(myri10ge_napi_weight, int, S_IRUGO);
261MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
262
263static int myri10ge_watchdog_timeout = 1;
264module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
265MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
266
267static int myri10ge_max_irq_loops = 1048576;
268module_param(myri10ge_max_irq_loops, int, S_IRUGO);
269MODULE_PARM_DESC(myri10ge_max_irq_loops,
270 "Set stuck legacy IRQ detection threshold\n");
271
c58ac5ca
BG		 272#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
273
274static int myri10ge_debug = -1; /* defaults above */
275module_param(myri10ge_debug, int, 0);
276MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
277
dd50f336
BG		 278static int myri10ge_fill_thresh = 256;
279module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
280MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
281
f761fae1 282static int myri10ge_wcfifo = 0;
6ebc087a
BG		 283module_param(myri10ge_wcfifo, int, S_IRUGO);
284MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
285
0da34b6d
BG		 286#define MYRI10GE_FW_OFFSET 1024*1024
287#define MYRI10GE_HIGHPART_TO_U32(X) \
288(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
289#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
290
291#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
292
2f76216f
BG		 293static void myri10ge_set_multicast_list(struct net_device *dev);
294
6250223e 295static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 296{
6250223e 297 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 298}
299
0da34b6d
BG		 300static int
301myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
302 struct myri10ge_cmd *data, int atomic)
303{
304 struct mcp_cmd *buf;
305 char buf_bytes[sizeof(*buf) + 8];
306 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 307 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 308 u32 dma_low, dma_high, result, value;
309 int sleep_total = 0;
310
311 /* ensure buf is aligned to 8 bytes */
312 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
313
314 buf->data0 = htonl(data->data0);
315 buf->data1 = htonl(data->data1);
316 buf->data2 = htonl(data->data2);
317 buf->cmd = htonl(cmd);
318 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
319 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
320
321 buf->response_addr.low = htonl(dma_low);
322 buf->response_addr.high = htonl(dma_high);
40f6cff5 323 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 324 mb();
325 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
326
327 /* wait up to 15ms. Longest command is the DMA benchmark,
328 * which is capped at 5ms, but runs from a timeout handler
329 * that runs every 7.8ms. So a 15ms timeout leaves us with
330 * a 2.2ms margin
331 */
332 if (atomic) {
333 /* if atomic is set, do not sleep,
334 * and try to get the completion quickly
335 * (1ms will be enough for those commands) */
336 for (sleep_total = 0;
337 sleep_total < 1000
40f6cff5 338 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 339 sleep_total += 10)
340 udelay(10);
341 } else {
342 /* use msleep for most command */
343 for (sleep_total = 0;
344 sleep_total < 15
40f6cff5 345 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 346 sleep_total++)
347 msleep(1);
348 }
349
350 result = ntohl(response->result);
351 value = ntohl(response->data);
352 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
353 if (result == 0) {
354 data->data0 = value;
355 return 0;
85a7ea1b
BG		 356 } else if (result == MXGEFW_CMD_UNKNOWN) {
357 return -ENOSYS;
5443e9ea
BG		 358 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
359 return -E2BIG;
0da34b6d
BG		 360 } else {
361 dev_err(&mgp->pdev->dev,
362 "command %d failed, result = %d\n",
363 cmd, result);
364 return -ENXIO;
365 }
366 }
367
368 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
369 cmd, result);
370 return -EAGAIN;
371}
372
373/*
374 * The eeprom strings on the lanaiX have the format
375 * SN=x\0
376 * MAC=x:x:x:x:x:x\0
377 * PT:ddd mmm xx xx:xx:xx xx\0
378 * PV:ddd mmm xx xx:xx:xx xx\0
379 */
380static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
381{
382 char *ptr, *limit;
383 int i;
384
385 ptr = mgp->eeprom_strings;
386 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
387
388 while (*ptr != '\0' && ptr < limit) {
389 if (memcmp(ptr, "MAC=", 4) == 0) {
390 ptr += 4;
391 mgp->mac_addr_string = ptr;
392 for (i = 0; i < 6; i++) {
393 if ((ptr + 2) > limit)
394 goto abort;
395 mgp->mac_addr[i] =
396 simple_strtoul(ptr, &ptr, 16);
397 ptr += 1;
398 }
399 }
400 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
401 ptr += 3;
402 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
403 }
404 while (ptr < limit && *ptr++) ;
405 }
406
407 return 0;
408
409abort:
410 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
411 return -ENXIO;
412}
413
414/*
415 * Enable or disable periodic RDMAs from the host to make certain
416 * chipsets resend dropped PCIe messages
417 */
418
419static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
420{
421 char __iomem *submit;
40f6cff5 422 __be32 buf[16];
0da34b6d
BG		 423 u32 dma_low, dma_high;
424 int i;
425
426 /* clear confirmation addr */
427 mgp->cmd->data = 0;
428 mb();
429
430 /* send a rdma command to the PCIe engine, and wait for the
431 * response in the confirmation address. The firmware should
432 * write a -1 there to indicate it is alive and well
433 */
434 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
435 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
436
437 buf[0] = htonl(dma_high); /* confirm addr MSW */
438 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 439 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 440 buf[3] = htonl(dma_high); /* dummy addr MSW */
441 buf[4] = htonl(dma_low); /* dummy addr LSW */
442 buf[5] = htonl(enable); /* enable? */
443
e700f9f4 444 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 445
446 myri10ge_pio_copy(submit, &buf, sizeof(buf));
447 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
448 msleep(1);
449 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
450 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
451 (enable ? "enable" : "disable"));
452}
453
454static int
455myri10ge_validate_firmware(struct myri10ge_priv *mgp,
456 struct mcp_gen_header *hdr)
457{
458 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 459
460 /* check firmware type */
461 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
462 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
463 return -EINVAL;
464 }
465
466 /* save firmware version for ethtool */
467 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
468
9dc6f0e7
BG		 469 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
470 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 471
9dc6f0e7
BG		 472 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
473 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 474 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
475 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
476 MXGEFW_VERSION_MINOR);
477 return -EINVAL;
478 }
479 return 0;
480}
481
482static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
483{
484 unsigned crc, reread_crc;
485 const struct firmware *fw;
486 struct device *dev = &mgp->pdev->dev;
487 struct mcp_gen_header *hdr;
488 size_t hdr_offset;
489 int status;
e454358a 490 unsigned i;
0da34b6d
BG		 491
492 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
493 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
494 mgp->fw_name);
495 status = -EINVAL;
496 goto abort_with_nothing;
497 }
498
499 /* check size */
500
501 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
502 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
503 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
504 status = -EINVAL;
505 goto abort_with_fw;
506 }
507
508 /* check id */
40f6cff5 509 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 510 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
511 dev_err(dev, "Bad firmware file\n");
512 status = -EINVAL;
513 goto abort_with_fw;
514 }
515 hdr = (void *)(fw->data + hdr_offset);
516
517 status = myri10ge_validate_firmware(mgp, hdr);
518 if (status != 0)
519 goto abort_with_fw;
520
521 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 522 for (i = 0; i < fw->size; i += 256) {
523 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
524 fw->data + i,
525 min(256U, (unsigned)(fw->size - i)));
526 mb();
527 readb(mgp->sram);
b10c0668 528 }
0da34b6d
BG		 529 /* corruption checking is good for parity recovery and buggy chipset */
530 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
531 reread_crc = crc32(~0, fw->data, fw->size);
532 if (crc != reread_crc) {
533 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
534 (unsigned)fw->size, reread_crc, crc);
535 status = -EIO;
536 goto abort_with_fw;
537 }
538 *size = (u32) fw->size;
539
540abort_with_fw:
541 release_firmware(fw);
542
543abort_with_nothing:
544 return status;
545}
546
547static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
548{
549 struct mcp_gen_header *hdr;
550 struct device *dev = &mgp->pdev->dev;
551 const size_t bytes = sizeof(struct mcp_gen_header);
552 size_t hdr_offset;
553 int status;
554
555 /* find running firmware header */
556 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
557
558 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
559 dev_err(dev, "Running firmware has bad header offset (%d)\n",
560 (int)hdr_offset);
561 return -EIO;
562 }
563
564 /* copy header of running firmware from SRAM to host memory to
565 * validate firmware */
566 hdr = kmalloc(bytes, GFP_KERNEL);
567 if (hdr == NULL) {
568 dev_err(dev, "could not malloc firmware hdr\n");
569 return -ENOMEM;
570 }
571 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
572 status = myri10ge_validate_firmware(mgp, hdr);
573 kfree(hdr);
9dc6f0e7
BG		 574
575 /* check to see if adopted firmware has bug where adopting
576 * it will cause broadcasts to be filtered unless the NIC
577 * is kept in ALLMULTI mode */
578 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
579 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
580 mgp->adopted_rx_filter_bug = 1;
581 dev_warn(dev, "Adopting fw %d.%d.%d: "
582 "working around rx filter bug\n",
583 mgp->fw_ver_major, mgp->fw_ver_minor,
584 mgp->fw_ver_tiny);
585 }
0da34b6d
BG		 586 return status;
587}
588
589static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
590{
591 char __iomem *submit;
40f6cff5 592 __be32 buf[16];
0da34b6d
BG		 593 u32 dma_low, dma_high, size;
594 int status, i;
595
b10c0668 596 size = 0;
0da34b6d
BG		 597 status = myri10ge_load_hotplug_firmware(mgp, &size);
598 if (status) {
599 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
600
601 /* Do not attempt to adopt firmware if there
602 * was a bad crc */
603 if (status == -EIO)
604 return status;
605
606 status = myri10ge_adopt_running_firmware(mgp);
607 if (status != 0) {
608 dev_err(&mgp->pdev->dev,
609 "failed to adopt running firmware\n");
610 return status;
611 }
612 dev_info(&mgp->pdev->dev,
613 "Successfully adopted running firmware\n");
614 if (mgp->tx.boundary == 4096) {
615 dev_warn(&mgp->pdev->dev,
616 "Using firmware currently running on NIC"
617 ". For optimal\n");
618 dev_warn(&mgp->pdev->dev,
619 "performance consider loading optimized "
620 "firmware\n");
621 dev_warn(&mgp->pdev->dev, "via hotplug\n");
622 }
623
624 mgp->fw_name = "adopted";
625 mgp->tx.boundary = 2048;
626 return status;
627 }
628
629 /* clear confirmation addr */
630 mgp->cmd->data = 0;
631 mb();
632
633 /* send a reload command to the bootstrap MCP, and wait for the
634 * response in the confirmation address. The firmware should
635 * write a -1 there to indicate it is alive and well
636 */
637 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
638 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
639
640 buf[0] = htonl(dma_high); /* confirm addr MSW */
641 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 642 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 643
644 /* FIX: All newest firmware should un-protect the bottom of
645 * the sram before handoff. However, the very first interfaces
646 * do not. Therefore the handoff copy must skip the first 8 bytes
647 */
648 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
649 buf[4] = htonl(size - 8); /* length of code */
650 buf[5] = htonl(8); /* where to copy to */
651 buf[6] = htonl(0); /* where to jump to */
652
e700f9f4 653 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 654
655 myri10ge_pio_copy(submit, &buf, sizeof(buf));
656 mb();
657 msleep(1);
658 mb();
659 i = 0;
660 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
661 msleep(1);
662 i++;
663 }
664 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
665 dev_err(&mgp->pdev->dev, "handoff failed\n");
666 return -ENXIO;
667 }
668 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 669 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 670
671 return 0;
672}
673
674static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
675{
676 struct myri10ge_cmd cmd;
677 int status;
678
679 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
680 | (addr[2] << 8) | addr[3]);
681
682 cmd.data1 = ((addr[4] << 8) | (addr[5]));
683
684 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
685 return status;
686}
687
688static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
689{
690 struct myri10ge_cmd cmd;
691 int status, ctl;
692
693 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
694 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
695
696 if (status) {
697 printk(KERN_ERR
698 "myri10ge: %s: Failed to set flow control mode\n",
699 mgp->dev->name);
700 return status;
701 }
702 mgp->pause = pause;
703 return 0;
704}
705
706static void
707myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
708{
709 struct myri10ge_cmd cmd;
710 int status, ctl;
711
712 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
713 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
714 if (status)
715 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
716 mgp->dev->name);
717}
718
0d6ac257 719static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 720{
721 struct myri10ge_cmd cmd;
722 int status;
0da34b6d 723 u32 len;
34fdccea
BG		 724 struct page *dmatest_page;
725 dma_addr_t dmatest_bus;
0d6ac257
BG		 726 char *test = " ";
727
728 dmatest_page = alloc_page(GFP_KERNEL);
729 if (!dmatest_page)
730 return -ENOMEM;
731 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
732 DMA_BIDIRECTIONAL);
733
734 /* Run a small DMA test.
735 * The magic multipliers to the length tell the firmware
736 * to do DMA read, write, or read+write tests. The
737 * results are returned in cmd.data0. The upper 16
738 * bits or the return is the number of transfers completed.
739 * The lower 16 bits is the time in 0.5us ticks that the
740 * transfers took to complete.
741 */
742
743 len = mgp->tx.boundary;
744
745 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
746 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
747 cmd.data2 = len * 0x10000;
748 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
749 if (status != 0) {
750 test = "read";
751 goto abort;
752 }
753 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
754 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
755 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
756 cmd.data2 = len * 0x1;
757 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
758 if (status != 0) {
759 test = "write";
760 goto abort;
761 }
762 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
763
764 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
765 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
766 cmd.data2 = len * 0x10001;
767 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
768 if (status != 0) {
769 test = "read/write";
770 goto abort;
771 }
772 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
773 (cmd.data0 & 0xffff);
774
775abort:
776 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
777 put_page(dmatest_page);
778
779 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
780 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
781 test, status);
782
783 return status;
784}
785
786static int myri10ge_reset(struct myri10ge_priv *mgp)
787{
788 struct myri10ge_cmd cmd;
789 int status;
790 size_t bytes;
0da34b6d
BG		 791
792 /* try to send a reset command to the card to see if it
793 * is alive */
794 memset(&cmd, 0, sizeof(cmd));
795 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
796 if (status != 0) {
797 dev_err(&mgp->pdev->dev, "failed reset\n");
798 return -ENXIO;
799 }
0d6ac257
BG		 800
801 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0da34b6d
BG		 802
803 /* Now exchange information about interrupts */
804
805 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
806 memset(mgp->rx_done.entry, 0, bytes);
807 cmd.data0 = (u32) bytes;
808 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
809 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
810 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
811 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
812
813 status |=
814 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 815 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 816 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
817 &cmd, 0);
818 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 819
0da34b6d
BG		 820 status |= myri10ge_send_cmd
821 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 822 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 823 if (status != 0) {
824 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
825 return status;
826 }
40f6cff5 827 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 828
0da34b6d
BG		 829 memset(mgp->rx_done.entry, 0, bytes);
830
831 /* reset mcp/driver shared state back to 0 */
832 mgp->tx.req = 0;
833 mgp->tx.done = 0;
834 mgp->tx.pkt_start = 0;
835 mgp->tx.pkt_done = 0;
836 mgp->rx_big.cnt = 0;
837 mgp->rx_small.cnt = 0;
838 mgp->rx_done.idx = 0;
839 mgp->rx_done.cnt = 0;
c58ac5ca 840 mgp->link_changes = 0;
0da34b6d 841 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 842 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 843 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 844 return status;
845}
846
847static inline void
848myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
849 struct mcp_kreq_ether_recv *src)
850{
40f6cff5 851 __be32 low;
0da34b6d
BG		 852
853 low = src->addr_low;
40f6cff5 854 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 855 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
856 mb();
857 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 858 mb();
859 src->addr_low = low;
40f6cff5 860 put_be32(low, &dst->addr_low);
0da34b6d
BG		 861 mb();
862}
863
40f6cff5 864static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 865{
866 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
867
40f6cff5 868 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 869 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
870 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
871 skb->csum = hw_csum;
84fa7933 872 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 873 }
874}
875
dd50f336
BG		 876static inline void
877myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
878 struct skb_frag_struct *rx_frags, int len, int hlen)
879{
880 struct skb_frag_struct *skb_frags;
881
882 skb->len = skb->data_len = len;
883 skb->truesize = len + sizeof(struct sk_buff);
884 /* attach the page(s) */
885
886 skb_frags = skb_shinfo(skb)->frags;
887 while (len > 0) {
888 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
889 len -= rx_frags->size;
890 skb_frags++;
891 rx_frags++;
892 skb_shinfo(skb)->nr_frags++;
893 }
894
895 /* pskb_may_pull is not available in irq context, but
896 * skb_pull() (for ether_pad and eth_type_trans()) requires
897 * the beginning of the packet in skb_headlen(), move it
898 * manually */
27d7ff46 899 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 900 skb_shinfo(skb)->frags[0].page_offset += hlen;
901 skb_shinfo(skb)->frags[0].size -= hlen;
902 skb->data_len -= hlen;
903 skb->tail += hlen;
904 skb_pull(skb, MXGEFW_PAD);
905}
906
907static void
908myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
909 int bytes, int watchdog)
910{
911 struct page *page;
912 int idx;
913
914 if (unlikely(rx->watchdog_needed && !watchdog))
915 return;
916
917 /* try to refill entire ring */
918 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
919 idx = rx->fill_cnt & rx->mask;
ae8509b1 920 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 921 /* we can use part of previous page */
922 get_page(rx->page);
923 } else {
924 /* we need a new page */
925 page =
926 alloc_pages(GFP_ATOMIC | __GFP_COMP,
927 MYRI10GE_ALLOC_ORDER);
928 if (unlikely(page == NULL)) {
929 if (rx->fill_cnt - rx->cnt < 16)
930 rx->watchdog_needed = 1;
931 return;
932 }
933 rx->page = page;
934 rx->page_offset = 0;
935 rx->bus = pci_map_page(mgp->pdev, page, 0,
936 MYRI10GE_ALLOC_SIZE,
937 PCI_DMA_FROMDEVICE);
938 }
939 rx->info[idx].page = rx->page;
940 rx->info[idx].page_offset = rx->page_offset;
941 /* note that this is the address of the start of the
942 * page */
943 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
944 rx->shadow[idx].addr_low =
945 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
946 rx->shadow[idx].addr_high =
947 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
948
949 /* start next packet on a cacheline boundary */
950 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 951
952#if MYRI10GE_ALLOC_SIZE > 4096
953 /* don't cross a 4KB boundary */
954 if ((rx->page_offset >> 12) !=
955 ((rx->page_offset + bytes - 1) >> 12))
956 rx->page_offset = (rx->page_offset + 4096) & ~4095;
957#endif
dd50f336
BG		 958 rx->fill_cnt++;
959
960 /* copy 8 descriptors to the firmware at a time */
961 if ((idx & 7) == 7) {
962 if (rx->wc_fifo == NULL)
963 myri10ge_submit_8rx(&rx->lanai[idx - 7],
964 &rx->shadow[idx - 7]);
965 else {
966 mb();
967 myri10ge_pio_copy(rx->wc_fifo,
968 &rx->shadow[idx - 7], 64);
969 }
970 }
971 }
972}
973
974static inline void
975myri10ge_unmap_rx_page(struct pci_dev *pdev,
976 struct myri10ge_rx_buffer_state *info, int bytes)
977{
978 /* unmap the recvd page if we're the only or last user of it */
979 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
980 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
981 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
982 & ~(MYRI10GE_ALLOC_SIZE - 1)),
983 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
984 }
985}
986
987#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
988 * page into an skb */
989
990static inline int
52ea6fb3
BG		 991myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
992 int bytes, int len, __wsum csum)
dd50f336
BG		 993{
994 struct sk_buff *skb;
995 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
996 int i, idx, hlen, remainder;
997 struct pci_dev *pdev = mgp->pdev;
998 struct net_device *dev = mgp->dev;
999 u8 *va;
1000
1001 len += MXGEFW_PAD;
1002 idx = rx->cnt & rx->mask;
1003 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1004 prefetch(va);
1005 /* Fill skb_frag_struct(s) with data from our receive */
1006 for (i = 0, remainder = len; remainder > 0; i++) {
1007 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1008 rx_frags[i].page = rx->info[idx].page;
1009 rx_frags[i].page_offset = rx->info[idx].page_offset;
1010 if (remainder < MYRI10GE_ALLOC_SIZE)
1011 rx_frags[i].size = remainder;
1012 else
1013 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1014 rx->cnt++;
1015 idx = rx->cnt & rx->mask;
1016 remainder -= MYRI10GE_ALLOC_SIZE;
1017 }
1018
1019 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1020
1021 /* allocate an skb to attach the page(s) to. */
1022
1023 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1024 if (unlikely(skb == NULL)) {
1025 mgp->stats.rx_dropped++;
1026 do {
1027 i--;
1028 put_page(rx_frags[i].page);
1029 } while (i != 0);
1030 return 0;
1031 }
1032
1033 /* Attach the pages to the skb, and trim off any padding */
1034 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1035 if (skb_shinfo(skb)->frags[0].size <= 0) {
1036 put_page(skb_shinfo(skb)->frags[0].page);
1037 skb_shinfo(skb)->nr_frags = 0;
1038 }
1039 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1040
1041 if (mgp->csum_flag) {
1042 if ((skb->protocol == htons(ETH_P_IP)) ||
1043 (skb->protocol == htons(ETH_P_IPV6))) {
1044 skb->csum = csum;
1045 skb->ip_summed = CHECKSUM_COMPLETE;
1046 } else
1047 myri10ge_vlan_ip_csum(skb, csum);
1048 }
1049 netif_receive_skb(skb);
1050 dev->last_rx = jiffies;
1051 return 1;
1052}
1053
0da34b6d
BG		 1054static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1055{
1056 struct pci_dev *pdev = mgp->pdev;
1057 struct myri10ge_tx_buf *tx = &mgp->tx;
1058 struct sk_buff *skb;
1059 int idx, len;
1060 int limit = 0;
1061
1062 while (tx->pkt_done != mcp_index) {
1063 idx = tx->done & tx->mask;
1064 skb = tx->info[idx].skb;
1065
1066 /* Mark as free */
1067 tx->info[idx].skb = NULL;
1068 if (tx->info[idx].last) {
1069 tx->pkt_done++;
1070 tx->info[idx].last = 0;
1071 }
1072 tx->done++;
1073 len = pci_unmap_len(&tx->info[idx], len);
1074 pci_unmap_len_set(&tx->info[idx], len, 0);
1075 if (skb) {
1076 mgp->stats.tx_bytes += skb->len;
1077 mgp->stats.tx_packets++;
1078 dev_kfree_skb_irq(skb);
1079 if (len)
1080 pci_unmap_single(pdev,
1081 pci_unmap_addr(&tx->info[idx],
1082 bus), len,
1083 PCI_DMA_TODEVICE);
1084 } else {
1085 if (len)
1086 pci_unmap_page(pdev,
1087 pci_unmap_addr(&tx->info[idx],
1088 bus), len,
1089 PCI_DMA_TODEVICE);
1090 }
1091
1092 /* limit potential for livelock by only handling
1093 * 2 full tx rings per call */
1094 if (unlikely(++limit > 2 * tx->mask))
1095 break;
1096 }
1097 /* start the queue if we've stopped it */
1098 if (netif_queue_stopped(mgp->dev)
1099 && tx->req - tx->done < (tx->mask >> 1)) {
1100 mgp->wake_queue++;
1101 netif_wake_queue(mgp->dev);
1102 }
1103}
1104
1105static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1106{
1107 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1108 unsigned long rx_bytes = 0;
1109 unsigned long rx_packets = 0;
1110 unsigned long rx_ok;
1111
1112 int idx = rx_done->idx;
1113 int cnt = rx_done->cnt;
1114 u16 length;
40f6cff5 1115 __wsum checksum;
0da34b6d
BG		 1116
1117 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1118 length = ntohs(rx_done->entry[idx].length);
1119 rx_done->entry[idx].length = 0;
40f6cff5 1120 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1121 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1122 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1123 mgp->small_bytes,
1124 length, checksum);
0da34b6d 1125 else
52ea6fb3
BG		 1126 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1127 mgp->big_bytes,
1128 length, checksum);
0da34b6d
BG		 1129 rx_packets += rx_ok;
1130 rx_bytes += rx_ok * (unsigned long)length;
1131 cnt++;
1132 idx = cnt & (myri10ge_max_intr_slots - 1);
1133
1134 /* limit potential for livelock by only handling a
1135 * limited number of frames. */
1136 (*limit)--;
1137 }
1138 rx_done->idx = idx;
1139 rx_done->cnt = cnt;
1140 mgp->stats.rx_packets += rx_packets;
1141 mgp->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1142
1143 /* restock receive rings if needed */
1144 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1145 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1146 mgp->small_bytes + MXGEFW_PAD, 0);
1147 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1148 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1149
0da34b6d
BG		 1150}
1151
1152static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1153{
1154 struct mcp_irq_data *stats = mgp->fw_stats;
1155
1156 if (unlikely(stats->stats_updated)) {
1157 if (mgp->link_state != stats->link_up) {
1158 mgp->link_state = stats->link_up;
1159 if (mgp->link_state) {
c58ac5ca
BG		 1160 if (netif_msg_link(mgp))
1161 printk(KERN_INFO
1162 "myri10ge: %s: link up\n",
1163 mgp->dev->name);
0da34b6d 1164 netif_carrier_on(mgp->dev);
c58ac5ca 1165 mgp->link_changes++;
0da34b6d 1166 } else {
c58ac5ca
BG		 1167 if (netif_msg_link(mgp))
1168 printk(KERN_INFO
1169 "myri10ge: %s: link down\n",
1170 mgp->dev->name);
0da34b6d 1171 netif_carrier_off(mgp->dev);
c58ac5ca 1172 mgp->link_changes++;
0da34b6d
BG		 1173 }
1174 }
1175 if (mgp->rdma_tags_available !=
1176 ntohl(mgp->fw_stats->rdma_tags_available)) {
1177 mgp->rdma_tags_available =
1178 ntohl(mgp->fw_stats->rdma_tags_available);
1179 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1180 "%d tags left\n", mgp->dev->name,
1181 mgp->rdma_tags_available);
1182 }
1183 mgp->down_cnt += stats->link_down;
1184 if (stats->link_down)
1185 wake_up(&mgp->down_wq);
1186 }
1187}
1188
1189static int myri10ge_poll(struct net_device *netdev, int *budget)
1190{
1191 struct myri10ge_priv *mgp = netdev_priv(netdev);
1192 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1193 int limit, orig_limit, work_done;
1194
1195 /* process as many rx events as NAPI will allow */
1196 limit = min(*budget, netdev->quota);
1197 orig_limit = limit;
1198 myri10ge_clean_rx_done(mgp, &limit);
1199 work_done = orig_limit - limit;
1200 *budget -= work_done;
1201 netdev->quota -= work_done;
1202
1203 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1204 netif_rx_complete(netdev);
40f6cff5 1205 put_be32(htonl(3), mgp->irq_claim);
0da34b6d
BG		 1206 return 0;
1207 }
1208 return 1;
1209}
1210
7d12e780 1211static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1212{
1213 struct myri10ge_priv *mgp = arg;
1214 struct mcp_irq_data *stats = mgp->fw_stats;
1215 struct myri10ge_tx_buf *tx = &mgp->tx;
1216 u32 send_done_count;
1217 int i;
1218
1219 /* make sure it is our IRQ, and that the DMA has finished */
1220 if (unlikely(!stats->valid))
1221 return (IRQ_NONE);
1222
1223 /* low bit indicates receives are present, so schedule
1224 * napi poll handler */
1225 if (stats->valid & 1)
1226 netif_rx_schedule(mgp->dev);
1227
1228 if (!mgp->msi_enabled) {
40f6cff5 1229 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1230 if (!myri10ge_deassert_wait)
1231 stats->valid = 0;
1232 mb();
1233 } else
1234 stats->valid = 0;
1235
1236 /* Wait for IRQ line to go low, if using INTx */
1237 i = 0;
1238 while (1) {
1239 i++;
1240 /* check for transmit completes and receives */
1241 send_done_count = ntohl(stats->send_done_count);
1242 if (send_done_count != tx->pkt_done)
1243 myri10ge_tx_done(mgp, (int)send_done_count);
1244 if (unlikely(i > myri10ge_max_irq_loops)) {
1245 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1246 mgp->dev->name);
1247 stats->valid = 0;
1248 schedule_work(&mgp->watchdog_work);
1249 }
1250 if (likely(stats->valid == 0))
1251 break;
1252 cpu_relax();
1253 barrier();
1254 }
1255
1256 myri10ge_check_statblock(mgp);
1257
40f6cff5 1258 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1259 return (IRQ_HANDLED);
1260}
1261
1262static int
1263myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1264{
1265 cmd->autoneg = AUTONEG_DISABLE;
1266 cmd->speed = SPEED_10000;
1267 cmd->duplex = DUPLEX_FULL;
1268 return 0;
1269}
1270
1271static void
1272myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1273{
1274 struct myri10ge_priv *mgp = netdev_priv(netdev);
1275
1276 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1277 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1278 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1279 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1280}
1281
1282static int
1283myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1284{
1285 struct myri10ge_priv *mgp = netdev_priv(netdev);
1286 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1287 return 0;
1288}
1289
1290static int
1291myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1292{
1293 struct myri10ge_priv *mgp = netdev_priv(netdev);
1294
1295 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1296 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1297 return 0;
1298}
1299
1300static void
1301myri10ge_get_pauseparam(struct net_device *netdev,
1302 struct ethtool_pauseparam *pause)
1303{
1304 struct myri10ge_priv *mgp = netdev_priv(netdev);
1305
1306 pause->autoneg = 0;
1307 pause->rx_pause = mgp->pause;
1308 pause->tx_pause = mgp->pause;
1309}
1310
1311static int
1312myri10ge_set_pauseparam(struct net_device *netdev,
1313 struct ethtool_pauseparam *pause)
1314{
1315 struct myri10ge_priv *mgp = netdev_priv(netdev);
1316
1317 if (pause->tx_pause != mgp->pause)
1318 return myri10ge_change_pause(mgp, pause->tx_pause);
1319 if (pause->rx_pause != mgp->pause)
1320 return myri10ge_change_pause(mgp, pause->tx_pause);
1321 if (pause->autoneg != 0)
1322 return -EINVAL;
1323 return 0;
1324}
1325
1326static void
1327myri10ge_get_ringparam(struct net_device *netdev,
1328 struct ethtool_ringparam *ring)
1329{
1330 struct myri10ge_priv *mgp = netdev_priv(netdev);
1331
1332 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1333 ring->rx_max_pending = mgp->rx_big.mask + 1;
1334 ring->rx_jumbo_max_pending = 0;
1335 ring->tx_max_pending = mgp->rx_small.mask + 1;
1336 ring->rx_mini_pending = ring->rx_mini_max_pending;
1337 ring->rx_pending = ring->rx_max_pending;
1338 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1339 ring->tx_pending = ring->tx_max_pending;
1340}
1341
1342static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1343{
1344 struct myri10ge_priv *mgp = netdev_priv(netdev);
1345 if (mgp->csum_flag)
1346 return 1;
1347 else
1348 return 0;
1349}
1350
1351static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1352{
1353 struct myri10ge_priv *mgp = netdev_priv(netdev);
1354 if (csum_enabled)
1355 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1356 else
1357 mgp->csum_flag = 0;
1358 return 0;
1359}
1360
1361static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1362 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1363 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1364 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1365 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1366 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1367 "tx_heartbeat_errors", "tx_window_errors",
1368 /* device-specific stats */
2c1a1088 1369 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1370 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1371 "serial_number", "tx_pkt_start", "tx_pkt_done",
1372 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1373 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1374 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1375 "dropped_link_error_or_filtered",
1376 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1377 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d
BG		 1378 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1379 "dropped_no_big_buffer"
1380};
1381
1382#define MYRI10GE_NET_STATS_LEN 21
1383#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1384
1385static void
1386myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1387{
1388 switch (stringset) {
1389 case ETH_SS_STATS:
1390 memcpy(data, *myri10ge_gstrings_stats,
1391 sizeof(myri10ge_gstrings_stats));
1392 break;
1393 }
1394}
1395
1396static int myri10ge_get_stats_count(struct net_device *netdev)
1397{
1398 return MYRI10GE_STATS_LEN;
1399}
1400
1401static void
1402myri10ge_get_ethtool_stats(struct net_device *netdev,
1403 struct ethtool_stats *stats, u64 * data)
1404{
1405 struct myri10ge_priv *mgp = netdev_priv(netdev);
1406 int i;
1407
1408 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1409 data[i] = ((unsigned long *)&mgp->stats)[i];
1410
2c1a1088 1411 data[i++] = (unsigned int)mgp->tx.boundary;
276e26c3 1412 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1413 data[i++] = (unsigned int)mgp->pdev->irq;
1414 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1415 data[i++] = (unsigned int)mgp->read_dma;
1416 data[i++] = (unsigned int)mgp->write_dma;
1417 data[i++] = (unsigned int)mgp->read_write_dma;
1418 data[i++] = (unsigned int)mgp->serial_number;
1419 data[i++] = (unsigned int)mgp->tx.pkt_start;
1420 data[i++] = (unsigned int)mgp->tx.pkt_done;
1421 data[i++] = (unsigned int)mgp->tx.req;
1422 data[i++] = (unsigned int)mgp->tx.done;
1423 data[i++] = (unsigned int)mgp->rx_small.cnt;
1424 data[i++] = (unsigned int)mgp->rx_big.cnt;
1425 data[i++] = (unsigned int)mgp->wake_queue;
1426 data[i++] = (unsigned int)mgp->stop_queue;
1427 data[i++] = (unsigned int)mgp->watchdog_resets;
1428 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1429 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1430 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1431 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1432 data[i++] =
1433 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
cee505db
BG		 1434 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1435 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1436 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1437 data[i++] =
1438 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
85a7ea1b
BG		 1439 data[i++] =
1440 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1441 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1442 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1443 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1444 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1445}
1446
c58ac5ca
BG		 1447static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1448{
1449 struct myri10ge_priv *mgp = netdev_priv(netdev);
1450 mgp->msg_enable = value;
1451}
1452
1453static u32 myri10ge_get_msglevel(struct net_device *netdev)
1454{
1455 struct myri10ge_priv *mgp = netdev_priv(netdev);
1456 return mgp->msg_enable;
1457}
1458
7282d491 1459static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1460 .get_settings = myri10ge_get_settings,
1461 .get_drvinfo = myri10ge_get_drvinfo,
1462 .get_coalesce = myri10ge_get_coalesce,
1463 .set_coalesce = myri10ge_set_coalesce,
1464 .get_pauseparam = myri10ge_get_pauseparam,
1465 .set_pauseparam = myri10ge_set_pauseparam,
1466 .get_ringparam = myri10ge_get_ringparam,
1467 .get_rx_csum = myri10ge_get_rx_csum,
1468 .set_rx_csum = myri10ge_set_rx_csum,
1469 .get_tx_csum = ethtool_op_get_tx_csum,
b10c0668 1470 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d
BG		 1471 .get_sg = ethtool_op_get_sg,
1472 .set_sg = ethtool_op_set_sg,
0da34b6d
BG		 1473 .get_tso = ethtool_op_get_tso,
1474 .set_tso = ethtool_op_set_tso,
6ffdd071 1475 .get_link = ethtool_op_get_link,
0da34b6d
BG		 1476 .get_strings = myri10ge_get_strings,
1477 .get_stats_count = myri10ge_get_stats_count,
c58ac5ca
BG		 1478 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1479 .set_msglevel = myri10ge_set_msglevel,
1480 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1481};
1482
1483static int myri10ge_allocate_rings(struct net_device *dev)
1484{
1485 struct myri10ge_priv *mgp;
1486 struct myri10ge_cmd cmd;
1487 int tx_ring_size, rx_ring_size;
1488 int tx_ring_entries, rx_ring_entries;
1489 int i, status;
1490 size_t bytes;
1491
1492 mgp = netdev_priv(dev);
1493
1494 /* get ring sizes */
1495
1496 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1497 tx_ring_size = cmd.data0;
1498 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1499 if (status != 0)
1500 return status;
0da34b6d
BG		 1501 rx_ring_size = cmd.data0;
1502
1503 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1504 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1505 mgp->tx.mask = tx_ring_entries - 1;
1506 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1507
355c7265
BG		 1508 status = -ENOMEM;
1509
0da34b6d
BG		 1510 /* allocate the host shadow rings */
1511
1512 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1513 * sizeof(*mgp->tx.req_list);
1514 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1515 if (mgp->tx.req_bytes == NULL)
1516 goto abort_with_nothing;
1517
1518 /* ensure req_list entries are aligned to 8 bytes */
1519 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1520 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1521
1522 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1523 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1524 if (mgp->rx_small.shadow == NULL)
1525 goto abort_with_tx_req_bytes;
1526
1527 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1528 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1529 if (mgp->rx_big.shadow == NULL)
1530 goto abort_with_rx_small_shadow;
1531
1532 /* allocate the host info rings */
1533
1534 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1535 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1536 if (mgp->tx.info == NULL)
1537 goto abort_with_rx_big_shadow;
1538
1539 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1540 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1541 if (mgp->rx_small.info == NULL)
1542 goto abort_with_tx_info;
1543
1544 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1545 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1546 if (mgp->rx_big.info == NULL)
1547 goto abort_with_rx_small_info;
1548
1549 /* Fill the receive rings */
c7dab99b
BG		 1550 mgp->rx_big.cnt = 0;
1551 mgp->rx_small.cnt = 0;
1552 mgp->rx_big.fill_cnt = 0;
1553 mgp->rx_small.fill_cnt = 0;
1554 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1555 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1556 mgp->rx_small.watchdog_needed = 0;
1557 mgp->rx_big.watchdog_needed = 0;
1558 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1559 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1560
c7dab99b
BG		 1561 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1562 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1563 dev->name, mgp->rx_small.fill_cnt);
1564 goto abort_with_rx_small_ring;
0da34b6d
BG		 1565 }
1566
c7dab99b
BG		 1567 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1568 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1569 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1570 dev->name, mgp->rx_big.fill_cnt);
1571 goto abort_with_rx_big_ring;
0da34b6d
BG		 1572 }
1573
1574 return 0;
1575
1576abort_with_rx_big_ring:
c7dab99b
BG		 1577 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1578 int idx = i & mgp->rx_big.mask;
1579 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1580 mgp->big_bytes);
1581 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1582 }
1583
1584abort_with_rx_small_ring:
c7dab99b
BG		 1585 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1586 int idx = i & mgp->rx_small.mask;
1587 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1588 mgp->small_bytes + MXGEFW_PAD);
1589 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1590 }
c7dab99b 1591
0da34b6d
BG		 1592 kfree(mgp->rx_big.info);
1593
1594abort_with_rx_small_info:
1595 kfree(mgp->rx_small.info);
1596
1597abort_with_tx_info:
1598 kfree(mgp->tx.info);
1599
1600abort_with_rx_big_shadow:
1601 kfree(mgp->rx_big.shadow);
1602
1603abort_with_rx_small_shadow:
1604 kfree(mgp->rx_small.shadow);
1605
1606abort_with_tx_req_bytes:
1607 kfree(mgp->tx.req_bytes);
1608 mgp->tx.req_bytes = NULL;
1609 mgp->tx.req_list = NULL;
1610
1611abort_with_nothing:
1612 return status;
1613}
1614
1615static void myri10ge_free_rings(struct net_device *dev)
1616{
1617 struct myri10ge_priv *mgp;
1618 struct sk_buff *skb;
1619 struct myri10ge_tx_buf *tx;
1620 int i, len, idx;
1621
1622 mgp = netdev_priv(dev);
1623
c7dab99b
BG		 1624 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1625 idx = i & mgp->rx_big.mask;
1626 if (i == mgp->rx_big.fill_cnt - 1)
1627 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1628 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1629 mgp->big_bytes);
1630 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1631 }
1632
c7dab99b
BG		 1633 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1634 idx = i & mgp->rx_small.mask;
1635 if (i == mgp->rx_small.fill_cnt - 1)
1636 mgp->rx_small.info[idx].page_offset =
1637 MYRI10GE_ALLOC_SIZE;
1638 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1639 mgp->small_bytes + MXGEFW_PAD);
1640 put_page(mgp->rx_small.info[idx].page);
1641 }
0da34b6d
BG		 1642 tx = &mgp->tx;
1643 while (tx->done != tx->req) {
1644 idx = tx->done & tx->mask;
1645 skb = tx->info[idx].skb;
1646
1647 /* Mark as free */
1648 tx->info[idx].skb = NULL;
1649 tx->done++;
1650 len = pci_unmap_len(&tx->info[idx], len);
1651 pci_unmap_len_set(&tx->info[idx], len, 0);
1652 if (skb) {
1653 mgp->stats.tx_dropped++;
1654 dev_kfree_skb_any(skb);
1655 if (len)
1656 pci_unmap_single(mgp->pdev,
1657 pci_unmap_addr(&tx->info[idx],
1658 bus), len,
1659 PCI_DMA_TODEVICE);
1660 } else {
1661 if (len)
1662 pci_unmap_page(mgp->pdev,
1663 pci_unmap_addr(&tx->info[idx],
1664 bus), len,
1665 PCI_DMA_TODEVICE);
1666 }
1667 }
1668 kfree(mgp->rx_big.info);
1669
1670 kfree(mgp->rx_small.info);
1671
1672 kfree(mgp->tx.info);
1673
1674 kfree(mgp->rx_big.shadow);
1675
1676 kfree(mgp->rx_small.shadow);
1677
1678 kfree(mgp->tx.req_bytes);
1679 mgp->tx.req_bytes = NULL;
1680 mgp->tx.req_list = NULL;
1681}
1682
df30a740
BG		 1683static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1684{
1685 struct pci_dev *pdev = mgp->pdev;
1686 int status;
1687
1688 if (myri10ge_msi) {
1689 status = pci_enable_msi(pdev);
1690 if (status != 0)
1691 dev_err(&pdev->dev,
1692 "Error %d setting up MSI; falling back to xPIC\n",
1693 status);
1694 else
1695 mgp->msi_enabled = 1;
1696 } else {
1697 mgp->msi_enabled = 0;
1698 }
1699 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1700 mgp->dev->name, mgp);
1701 if (status != 0) {
1702 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1703 if (mgp->msi_enabled)
1704 pci_disable_msi(pdev);
1705 }
1706 return status;
1707}
1708
1709static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1710{
1711 struct pci_dev *pdev = mgp->pdev;
1712
1713 free_irq(pdev->irq, mgp);
1714 if (mgp->msi_enabled)
1715 pci_disable_msi(pdev);
1716}
1717
0da34b6d
BG		 1718static int myri10ge_open(struct net_device *dev)
1719{
1720 struct myri10ge_priv *mgp;
1721 struct myri10ge_cmd cmd;
1722 int status, big_pow2;
1723
1724 mgp = netdev_priv(dev);
1725
1726 if (mgp->running != MYRI10GE_ETH_STOPPED)
1727 return -EBUSY;
1728
1729 mgp->running = MYRI10GE_ETH_STARTING;
1730 status = myri10ge_reset(mgp);
1731 if (status != 0) {
1732 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1733 goto abort_with_nothing;
0da34b6d
BG		 1734 }
1735
df30a740
BG		 1736 status = myri10ge_request_irq(mgp);
1737 if (status != 0)
1738 goto abort_with_nothing;
1739
0da34b6d
BG		 1740 /* decide what small buffer size to use. For good TCP rx
1741 * performance, it is important to not receive 1514 byte
1742 * frames into jumbo buffers, as it confuses the socket buffer
1743 * accounting code, leading to drops and erratic performance.
1744 */
1745
1746 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1747 /* enough for a TCP header */
1748 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1749 ? (128 - MXGEFW_PAD)
1750 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1751 else
de3c4507
BG		 1752 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1753 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1754
1755 /* Override the small buffer size? */
1756 if (myri10ge_small_bytes > 0)
1757 mgp->small_bytes = myri10ge_small_bytes;
1758
0da34b6d
BG		 1759 /* get the lanai pointers to the send and receive rings */
1760
1761 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1762 mgp->tx.lanai =
1763 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1764
1765 status |=
1766 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1767 mgp->rx_small.lanai =
1768 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1769
1770 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1771 mgp->rx_big.lanai =
1772 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1773
1774 if (status != 0) {
1775 printk(KERN_ERR
1776 "myri10ge: %s: failed to get ring sizes or locations\n",
1777 dev->name);
1778 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1779 goto abort_with_irq;
0da34b6d
BG		 1780 }
1781
276e26c3 1782 if (myri10ge_wcfifo && mgp->wc_enabled) {
e700f9f4
BG		 1783 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1784 mgp->rx_small.wc_fifo =
1785 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1786 mgp->rx_big.wc_fifo =
1787 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1788 } else {
1789 mgp->tx.wc_fifo = NULL;
1790 mgp->rx_small.wc_fifo = NULL;
1791 mgp->rx_big.wc_fifo = NULL;
1792 }
1793
0da34b6d
BG		 1794 /* Firmware needs the big buff size as a power of 2. Lie and
1795 * tell him the buffer is larger, because we only use 1
1796 * buffer/pkt, and the mtu will prevent overruns.
1797 */
13348bee 1798 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1799 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1800 while ((big_pow2 & (big_pow2 - 1)) != 0)
1801 big_pow2++;
13348bee 1802 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1803 } else {
1804 big_pow2 = MYRI10GE_ALLOC_SIZE;
1805 mgp->big_bytes = big_pow2;
1806 }
1807
1808 status = myri10ge_allocate_rings(dev);
1809 if (status != 0)
df30a740 1810 goto abort_with_irq;
0da34b6d
BG		 1811
1812 /* now give firmware buffers sizes, and MTU */
1813 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1814 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1815 cmd.data0 = mgp->small_bytes;
1816 status |=
1817 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1818 cmd.data0 = big_pow2;
1819 status |=
1820 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1821 if (status) {
1822 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1823 dev->name);
1824 goto abort_with_rings;
1825 }
1826
1827 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1828 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1829 cmd.data2 = sizeof(struct mcp_irq_data);
1830 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1831 if (status == -ENOSYS) {
1832 dma_addr_t bus = mgp->fw_stats_bus;
1833 bus += offsetof(struct mcp_irq_data, send_done_count);
1834 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1835 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1836 status = myri10ge_send_cmd(mgp,
1837 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1838 &cmd, 0);
1839 /* Firmware cannot support multicast without STATS_DMA_V2 */
1840 mgp->fw_multicast_support = 0;
1841 } else {
1842 mgp->fw_multicast_support = 1;
1843 }
0da34b6d
BG		 1844 if (status) {
1845 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1846 dev->name);
1847 goto abort_with_rings;
1848 }
1849
40f6cff5 1850 mgp->link_state = htonl(~0U);
0da34b6d
BG		 1851 mgp->rdma_tags_available = 15;
1852
1853 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1854
1855 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1856 if (status) {
1857 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1858 dev->name);
1859 goto abort_with_rings;
1860 }
1861
1862 mgp->wake_queue = 0;
1863 mgp->stop_queue = 0;
1864 mgp->running = MYRI10GE_ETH_RUNNING;
1865 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1866 add_timer(&mgp->watchdog_timer);
1867 netif_wake_queue(dev);
1868 return 0;
1869
1870abort_with_rings:
1871 myri10ge_free_rings(dev);
1872
df30a740
BG		 1873abort_with_irq:
1874 myri10ge_free_irq(mgp);
1875
0da34b6d
BG		 1876abort_with_nothing:
1877 mgp->running = MYRI10GE_ETH_STOPPED;
1878 return -ENOMEM;
1879}
1880
1881static int myri10ge_close(struct net_device *dev)
1882{
1883 struct myri10ge_priv *mgp;
1884 struct myri10ge_cmd cmd;
1885 int status, old_down_cnt;
1886
1887 mgp = netdev_priv(dev);
1888
1889 if (mgp->running != MYRI10GE_ETH_RUNNING)
1890 return 0;
1891
1892 if (mgp->tx.req_bytes == NULL)
1893 return 0;
1894
1895 del_timer_sync(&mgp->watchdog_timer);
1896 mgp->running = MYRI10GE_ETH_STOPPING;
1897 netif_poll_disable(mgp->dev);
1898 netif_carrier_off(dev);
1899 netif_stop_queue(dev);
1900 old_down_cnt = mgp->down_cnt;
1901 mb();
1902 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1903 if (status)
1904 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1905 dev->name);
1906
1907 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1908 if (old_down_cnt == mgp->down_cnt)
1909 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1910
1911 netif_tx_disable(dev);
df30a740 1912 myri10ge_free_irq(mgp);
0da34b6d
BG		 1913 myri10ge_free_rings(dev);
1914
1915 mgp->running = MYRI10GE_ETH_STOPPED;
1916 return 0;
1917}
1918
1919/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1920 * backwards one at a time and handle ring wraps */
1921
1922static inline void
1923myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1924 struct mcp_kreq_ether_send *src, int cnt)
1925{
1926 int idx, starting_slot;
1927 starting_slot = tx->req;
1928 while (cnt > 1) {
1929 cnt--;
1930 idx = (starting_slot + cnt) & tx->mask;
1931 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1932 mb();
1933 }
1934}
1935
1936/*
1937 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1938 * at most 32 bytes at a time, so as to avoid involving the software
1939 * pio handler in the nic. We re-write the first segment's flags
1940 * to mark them valid only after writing the entire chain.
1941 */
1942
1943static inline void
1944myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1945 int cnt)
1946{
1947 int idx, i;
1948 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1949 struct mcp_kreq_ether_send *srcp;
1950 u8 last_flags;
1951
1952 idx = tx->req & tx->mask;
1953
1954 last_flags = src->flags;
1955 src->flags = 0;
1956 mb();
1957 dst = dstp = &tx->lanai[idx];
1958 srcp = src;
1959
1960 if ((idx + cnt) < tx->mask) {
1961 for (i = 0; i < (cnt - 1); i += 2) {
1962 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1963 mb(); /* force write every 32 bytes */
1964 srcp += 2;
1965 dstp += 2;
1966 }
1967 } else {
1968 /* submit all but the first request, and ensure
1969 * that it is submitted below */
1970 myri10ge_submit_req_backwards(tx, src, cnt);
1971 i = 0;
1972 }
1973 if (i < cnt) {
1974 /* submit the first request */
1975 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1976 mb(); /* barrier before setting valid flag */
1977 }
1978
1979 /* re-write the last 32-bits with the valid flags */
1980 src->flags = last_flags;
40f6cff5 1981 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 1982 tx->req += cnt;
1983 mb();
1984}
1985
1986static inline void
1987myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1988 struct mcp_kreq_ether_send *src, int cnt)
1989{
1990 tx->req += cnt;
1991 mb();
1992 while (cnt >= 4) {
1993 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1994 mb();
1995 src += 4;
1996 cnt -= 4;
1997 }
1998 if (cnt > 0) {
1999 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2000 * needs to be so that we don't overrun it */
e700f9f4
BG		 2001 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2002 src, 64);
0da34b6d
BG		 2003 mb();
2004 }
2005}
2006
2007/*
2008 * Transmit a packet. We need to split the packet so that a single
2009 * segment does not cross myri10ge->tx.boundary, so this makes segment
2010 * counting tricky. So rather than try to count segments up front, we
2011 * just give up if there are too few segments to hold a reasonably
2012 * fragmented packet currently available. If we run
2013 * out of segments while preparing a packet for DMA, we just linearize
2014 * it and try again.
2015 */
2016
2017static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2018{
2019 struct myri10ge_priv *mgp = netdev_priv(dev);
2020 struct mcp_kreq_ether_send *req;
2021 struct myri10ge_tx_buf *tx = &mgp->tx;
2022 struct skb_frag_struct *frag;
2023 dma_addr_t bus;
40f6cff5
AV		 2024 u32 low;
2025 __be32 high_swapped;
0da34b6d
BG		 2026 unsigned int len;
2027 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2028 u16 pseudo_hdr_offset, cksum_offset;
2029 int cum_len, seglen, boundary, rdma_count;
2030 u8 flags, odd_flag;
2031
2032again:
2033 req = tx->req_list;
2034 avail = tx->mask - 1 - (tx->req - tx->done);
2035
2036 mss = 0;
2037 max_segments = MXGEFW_MAX_SEND_DESC;
2038
917690cd 2039 if (skb_is_gso(skb)) {
7967168c 2040 mss = skb_shinfo(skb)->gso_size;
917690cd 2041 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2042 }
0da34b6d
BG		 2043
2044 if ((unlikely(avail < max_segments))) {
2045 /* we are out of transmit resources */
2046 mgp->stop_queue++;
2047 netif_stop_queue(dev);
2048 return 1;
2049 }
2050
2051 /* Setup checksum offloading, if needed */
2052 cksum_offset = 0;
2053 pseudo_hdr_offset = 0;
2054 odd_flag = 0;
2055 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2056 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2057 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2058 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2059 /* If the headers are excessively large, then we must
2060 * fall back to a software checksum */
2061 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
84fa7933 2062 if (skb_checksum_help(skb))
0da34b6d
BG		 2063 goto drop;
2064 cksum_offset = 0;
2065 pseudo_hdr_offset = 0;
2066 } else {
0da34b6d
BG		 2067 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2068 flags |= MXGEFW_FLAGS_CKSUM;
2069 }
2070 }
2071
2072 cum_len = 0;
2073
0da34b6d
BG		 2074 if (mss) { /* TSO */
2075 /* this removes any CKSUM flag from before */
2076 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2077
2078 /* negative cum_len signifies to the
2079 * send loop that we are still in the
2080 * header portion of the TSO packet.
2081 * TSO header must be at most 134 bytes long */
ab6a5bb6 2082 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d
BG		 2083
2084 /* for TSO, pseudo_hdr_offset holds mss.
2085 * The firmware figures out where to put
2086 * the checksum by parsing the header. */
40f6cff5 2087 pseudo_hdr_offset = mss;
0da34b6d 2088 } else
0da34b6d
BG		 2089 /* Mark small packets, and pad out tiny packets */
2090 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2091 flags |= MXGEFW_FLAGS_SMALL;
2092
2093 /* pad frames to at least ETH_ZLEN bytes */
2094 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2095 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2096 /* The packet is gone, so we must
2097 * return 0 */
2098 mgp->stats.tx_dropped += 1;
2099 return 0;
2100 }
2101 /* adjust the len to account for the zero pad
2102 * so that the nic can know how long it is */
2103 skb->len = ETH_ZLEN;
2104 }
2105 }
2106
2107 /* map the skb for DMA */
2108 len = skb->len - skb->data_len;
2109 idx = tx->req & tx->mask;
2110 tx->info[idx].skb = skb;
2111 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2112 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2113 pci_unmap_len_set(&tx->info[idx], len, len);
2114
2115 frag_cnt = skb_shinfo(skb)->nr_frags;
2116 frag_idx = 0;
2117 count = 0;
2118 rdma_count = 0;
2119
2120 /* "rdma_count" is the number of RDMAs belonging to the
2121 * current packet BEFORE the current send request. For
2122 * non-TSO packets, this is equal to "count".
2123 * For TSO packets, rdma_count needs to be reset
2124 * to 0 after a segment cut.
2125 *
2126 * The rdma_count field of the send request is
2127 * the number of RDMAs of the packet starting at
2128 * that request. For TSO send requests with one ore more cuts
2129 * in the middle, this is the number of RDMAs starting
2130 * after the last cut in the request. All previous
2131 * segments before the last cut implicitly have 1 RDMA.
2132 *
2133 * Since the number of RDMAs is not known beforehand,
2134 * it must be filled-in retroactively - after each
2135 * segmentation cut or at the end of the entire packet.
2136 */
2137
2138 while (1) {
2139 /* Break the SKB or Fragment up into pieces which
2140 * do not cross mgp->tx.boundary */
2141 low = MYRI10GE_LOWPART_TO_U32(bus);
2142 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2143 while (len) {
2144 u8 flags_next;
2145 int cum_len_next;
2146
2147 if (unlikely(count == max_segments))
2148 goto abort_linearize;
2149
2150 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2151 seglen = boundary - low;
2152 if (seglen > len)
2153 seglen = len;
2154 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2155 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2156 if (mss) { /* TSO */
2157 (req - rdma_count)->rdma_count = rdma_count + 1;
2158
2159 if (likely(cum_len >= 0)) { /* payload */
2160 int next_is_first, chop;
2161
2162 chop = (cum_len_next > mss);
2163 cum_len_next = cum_len_next % mss;
2164 next_is_first = (cum_len_next == 0);
2165 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2166 flags_next |= next_is_first *
2167 MXGEFW_FLAGS_FIRST;
2168 rdma_count |= -(chop | next_is_first);
2169 rdma_count += chop & !next_is_first;
2170 } else if (likely(cum_len_next >= 0)) { /* header ends */
2171 int small;
2172
2173 rdma_count = -1;
2174 cum_len_next = 0;
2175 seglen = -cum_len;
2176 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2177 flags_next = MXGEFW_FLAGS_TSO_PLD |
2178 MXGEFW_FLAGS_FIRST |
2179 (small * MXGEFW_FLAGS_SMALL);
2180 }
2181 }
0da34b6d
BG		 2182 req->addr_high = high_swapped;
2183 req->addr_low = htonl(low);
40f6cff5 2184 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2185 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2186 req->rdma_count = 1;
2187 req->length = htons(seglen);
2188 req->cksum_offset = cksum_offset;
2189 req->flags = flags | ((cum_len & 1) * odd_flag);
2190
2191 low += seglen;
2192 len -= seglen;
2193 cum_len = cum_len_next;
2194 flags = flags_next;
2195 req++;
2196 count++;
2197 rdma_count++;
2198 if (unlikely(cksum_offset > seglen))
2199 cksum_offset -= seglen;
2200 else
2201 cksum_offset = 0;
2202 }
2203 if (frag_idx == frag_cnt)
2204 break;
2205
2206 /* map next fragment for DMA */
2207 idx = (count + tx->req) & tx->mask;
2208 frag = &skb_shinfo(skb)->frags[frag_idx];
2209 frag_idx++;
2210 len = frag->size;
2211 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2212 len, PCI_DMA_TODEVICE);
2213 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2214 pci_unmap_len_set(&tx->info[idx], len, len);
2215 }
2216
2217 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2218 if (mss)
2219 do {
2220 req--;
2221 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2222 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2223 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2224 idx = ((count - 1) + tx->req) & tx->mask;
2225 tx->info[idx].last = 1;
2226 if (tx->wc_fifo == NULL)
2227 myri10ge_submit_req(tx, tx->req_list, count);
2228 else
2229 myri10ge_submit_req_wc(tx, tx->req_list, count);
2230 tx->pkt_start++;
2231 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2232 mgp->stop_queue++;
2233 netif_stop_queue(dev);
2234 }
2235 dev->trans_start = jiffies;
2236 return 0;
2237
2238abort_linearize:
2239 /* Free any DMA resources we've alloced and clear out the skb
2240 * slot so as to not trip up assertions, and to avoid a
2241 * double-free if linearizing fails */
2242
2243 last_idx = (idx + 1) & tx->mask;
2244 idx = tx->req & tx->mask;
2245 tx->info[idx].skb = NULL;
2246 do {
2247 len = pci_unmap_len(&tx->info[idx], len);
2248 if (len) {
2249 if (tx->info[idx].skb != NULL)
2250 pci_unmap_single(mgp->pdev,
2251 pci_unmap_addr(&tx->info[idx],
2252 bus), len,
2253 PCI_DMA_TODEVICE);
2254 else
2255 pci_unmap_page(mgp->pdev,
2256 pci_unmap_addr(&tx->info[idx],
2257 bus), len,
2258 PCI_DMA_TODEVICE);
2259 pci_unmap_len_set(&tx->info[idx], len, 0);
2260 tx->info[idx].skb = NULL;
2261 }
2262 idx = (idx + 1) & tx->mask;
2263 } while (idx != last_idx);
89114afd 2264 if (skb_is_gso(skb)) {
0da34b6d
BG		 2265 printk(KERN_ERR
2266 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2267 mgp->dev->name);
2268 goto drop;
2269 }
2270
bec0e859 2271 if (skb_linearize(skb))
0da34b6d
BG		 2272 goto drop;
2273
2274 mgp->tx_linearized++;
2275 goto again;
2276
2277drop:
2278 dev_kfree_skb_any(skb);
2279 mgp->stats.tx_dropped += 1;
2280 return 0;
2281
2282}
2283
2284static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2285{
2286 struct myri10ge_priv *mgp = netdev_priv(dev);
2287 return &mgp->stats;
2288}
2289
2290static void myri10ge_set_multicast_list(struct net_device *dev)
2291{
85a7ea1b
BG		 2292 struct myri10ge_cmd cmd;
2293 struct myri10ge_priv *mgp;
2294 struct dev_mc_list *mc_list;
6250223e 2295 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 2296 int err;
2297
2298 mgp = netdev_priv(dev);
0da34b6d
BG		 2299 /* can be called from atomic contexts,
2300 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2301 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2302
2303 /* This firmware is known to not support multicast */
2f76216f 2304 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2305 return;
2306
2307 /* Disable multicast filtering */
2308
2309 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2310 if (err != 0) {
2311 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2312 " error status: %d\n", dev->name, err);
2313 goto abort;
2314 }
2315
2f76216f 2316 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2317 /* request to disable multicast filtering, so quit here */
2318 return;
2319 }
2320
2321 /* Flush the filters */
2322
2323 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2324 &cmd, 1);
2325 if (err != 0) {
2326 printk(KERN_ERR
2327 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2328 ", error status: %d\n", dev->name, err);
2329 goto abort;
2330 }
2331
2332 /* Walk the multicast list, and add each address */
2333 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2334 memcpy(data, &mc_list->dmi_addr, 6);
2335 cmd.data0 = ntohl(data[0]);
2336 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2337 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2338 &cmd, 1);
2339
2340 if (err != 0) {
2341 printk(KERN_ERR "myri10ge: %s: Failed "
2342 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2343 "%d\t", dev->name, err);
2344 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2345 ((unsigned char *)&mc_list->dmi_addr)[0],
2346 ((unsigned char *)&mc_list->dmi_addr)[1],
2347 ((unsigned char *)&mc_list->dmi_addr)[2],
2348 ((unsigned char *)&mc_list->dmi_addr)[3],
2349 ((unsigned char *)&mc_list->dmi_addr)[4],
2350 ((unsigned char *)&mc_list->dmi_addr)[5]
2351 );
2352 goto abort;
2353 }
2354 }
2355 /* Enable multicast filtering */
2356 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2357 if (err != 0) {
2358 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2359 "error status: %d\n", dev->name, err);
2360 goto abort;
2361 }
2362
2363 return;
2364
2365abort:
2366 return;
0da34b6d
BG		 2367}
2368
2369static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2370{
2371 struct sockaddr *sa = addr;
2372 struct myri10ge_priv *mgp = netdev_priv(dev);
2373 int status;
2374
2375 if (!is_valid_ether_addr(sa->sa_data))
2376 return -EADDRNOTAVAIL;
2377
2378 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2379 if (status != 0) {
2380 printk(KERN_ERR
2381 "myri10ge: %s: changing mac address failed with %d\n",
2382 dev->name, status);
2383 return status;
2384 }
2385
2386 /* change the dev structure */
2387 memcpy(dev->dev_addr, sa->sa_data, 6);
2388 return 0;
2389}
2390
2391static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2392{
2393 struct myri10ge_priv *mgp = netdev_priv(dev);
2394 int error = 0;
2395
2396 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2397 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2398 dev->name, new_mtu);
2399 return -EINVAL;
2400 }
2401 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2402 dev->name, dev->mtu, new_mtu);
2403 if (mgp->running) {
2404 /* if we change the mtu on an active device, we must
2405 * reset the device so the firmware sees the change */
2406 myri10ge_close(dev);
2407 dev->mtu = new_mtu;
2408 myri10ge_open(dev);
2409 } else
2410 dev->mtu = new_mtu;
2411
2412 return error;
2413}
2414
2415/*
2416 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2417 * Only do it if the bridge is a root port since we don't want to disturb
2418 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2419 */
2420
0da34b6d
BG		 2421static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2422{
2423 struct pci_dev *bridge = mgp->pdev->bus->self;
2424 struct device *dev = &mgp->pdev->dev;
2425 unsigned cap;
2426 unsigned err_cap;
2427 u16 val;
2428 u8 ext_type;
2429 int ret;
2430
2431 if (!myri10ge_ecrc_enable || !bridge)
2432 return;
2433
2434 /* check that the bridge is a root port */
2435 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2436 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2437 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2438 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2439 if (myri10ge_ecrc_enable > 1) {
2440 struct pci_dev *old_bridge = bridge;
2441
2442 /* Walk the hierarchy up to the root port
2443 * where ECRC has to be enabled */
2444 do {
2445 bridge = bridge->bus->self;
2446 if (!bridge) {
2447 dev_err(dev,
2448 "Failed to find root port"
2449 " to force ECRC\n");
2450 return;
2451 }
2452 cap =
2453 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2454 pci_read_config_word(bridge,
2455 cap + PCI_CAP_FLAGS, &val);
2456 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2457 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2458
2459 dev_info(dev,
2460 "Forcing ECRC on non-root port %s"
2461 " (enabling on root port %s)\n",
2462 pci_name(old_bridge), pci_name(bridge));
2463 } else {
2464 dev_err(dev,
2465 "Not enabling ECRC on non-root port %s\n",
2466 pci_name(bridge));
2467 return;
2468 }
2469 }
2470
2471 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2472 if (!cap)
2473 return;
2474
2475 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2476 if (ret) {
2477 dev_err(dev, "failed reading ext-conf-space of %s\n",
2478 pci_name(bridge));
2479 dev_err(dev, "\t pci=nommconf in use? "
2480 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2481 return;
2482 }
2483 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2484 return;
2485
2486 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2487 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2488 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 2489}
2490
2491/*
2492 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2493 * when the PCI-E Completion packets are aligned on an 8-byte
2494 * boundary. Some PCI-E chip sets always align Completion packets; on
2495 * the ones that do not, the alignment can be enforced by enabling
2496 * ECRC generation (if supported).
2497 *
2498 * When PCI-E Completion packets are not aligned, it is actually more
2499 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2500 *
2501 * If the driver can neither enable ECRC nor verify that it has
2502 * already been enabled, then it must use a firmware image which works
2503 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2504 * should also ensure that it never gives the device a Read-DMA which is
2505 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2506 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2507 * firmware image, and set tx.boundary to 4KB.
2508 */
2509
5443e9ea 2510static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 2511{
5443e9ea
BG		 2512 struct pci_dev *pdev = mgp->pdev;
2513 struct device *dev = &pdev->dev;
2514 int cap, status;
2515 u16 val;
0da34b6d 2516
5443e9ea
BG		 2517 mgp->tx.boundary = 4096;
2518 /*
2519 * Verify the max read request size was set to 4KB
2520 * before trying the test with 4KB.
2521 */
2522 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2523 if (cap < 64) {
2524 dev_err(dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2525 goto abort;
2526 }
2527 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2528 if (status != 0) {
2529 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2530 goto abort;
2531 }
2532 if ((val & (5 << 12)) != (5 << 12)) {
2533 dev_warn(dev, "Max Read Request size != 4096 (0x%x)\n", val);
2534 mgp->tx.boundary = 2048;
2535 }
2536 /*
2537 * load the optimized firmware (which assumes aligned PCIe
2538 * completions) in order to see if it works on this host.
2539 */
2540 mgp->fw_name = myri10ge_fw_aligned;
2541 status = myri10ge_load_firmware(mgp);
2542 if (status != 0) {
2543 goto abort;
2544 }
2545
2546 /*
2547 * Enable ECRC if possible
2548 */
2549 myri10ge_enable_ecrc(mgp);
2550
2551 /*
2552 * Run a DMA test which watches for unaligned completions and
2553 * aborts on the first one seen.
2554 */
2555
2556 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2557 if (status == 0)
2558 return; /* keep the aligned firmware */
2559
2560 if (status != -E2BIG)
2561 dev_warn(dev, "DMA test failed: %d\n", status);
2562 if (status == -ENOSYS)
2563 dev_warn(dev, "Falling back to ethp! "
2564 "Please install up to date fw\n");
2565abort:
2566 /* fall back to using the unaligned firmware */
0da34b6d
BG		 2567 mgp->tx.boundary = 2048;
2568 mgp->fw_name = myri10ge_fw_unaligned;
2569
5443e9ea
BG		 2570}
2571
2572static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2573{
0da34b6d 2574 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2575 int link_width, exp_cap;
2576 u16 lnk;
2577
2578 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2579 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2580 link_width = (lnk >> 4) & 0x3f;
2581
ce7f9368
BG		 2582 /* Check to see if Link is less than 8 or if the
2583 * upstream bridge is known to provide aligned
2584 * completions */
2585 if (link_width < 8) {
2586 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2587 link_width);
2588 mgp->tx.boundary = 4096;
2589 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 2590 } else {
2591 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 2592 }
2593 } else {
2594 if (myri10ge_force_firmware == 1) {
2595 dev_info(&mgp->pdev->dev,
2596 "Assuming aligned completions (forced)\n");
2597 mgp->tx.boundary = 4096;
2598 mgp->fw_name = myri10ge_fw_aligned;
2599 } else {
2600 dev_info(&mgp->pdev->dev,
2601 "Assuming unaligned completions (forced)\n");
2602 mgp->tx.boundary = 2048;
2603 mgp->fw_name = myri10ge_fw_unaligned;
2604 }
2605 }
2606 if (myri10ge_fw_name != NULL) {
2607 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2608 myri10ge_fw_name);
2609 mgp->fw_name = myri10ge_fw_name;
2610 }
2611}
2612
0da34b6d
BG		 2613#ifdef CONFIG_PM
2614
2615static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2616{
2617 struct myri10ge_priv *mgp;
2618 struct net_device *netdev;
2619
2620 mgp = pci_get_drvdata(pdev);
2621 if (mgp == NULL)
2622 return -EINVAL;
2623 netdev = mgp->dev;
2624
2625 netif_device_detach(netdev);
2626 if (netif_running(netdev)) {
2627 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2628 rtnl_lock();
2629 myri10ge_close(netdev);
2630 rtnl_unlock();
2631 }
2632 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2633 pci_save_state(pdev);
0da34b6d 2634 pci_disable_device(pdev);
1a63e846
BG		 2635
2636 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2637}
2638
2639static int myri10ge_resume(struct pci_dev *pdev)
2640{
2641 struct myri10ge_priv *mgp;
2642 struct net_device *netdev;
2643 int status;
2644 u16 vendor;
2645
2646 mgp = pci_get_drvdata(pdev);
2647 if (mgp == NULL)
2648 return -EINVAL;
2649 netdev = mgp->dev;
2650 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2651 msleep(5); /* give card time to respond */
2652 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2653 if (vendor == 0xffff) {
2654 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2655 mgp->dev->name);
2656 return -EIO;
2657 }
83f6e152 2658
1a63e846
BG		 2659 status = pci_restore_state(pdev);
2660 if (status)
2661 return status;
4c2248cc
BG		 2662
2663 status = pci_enable_device(pdev);
1a63e846 2664 if (status) {
4c2248cc 2665 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2666 return status;
4c2248cc
BG		 2667 }
2668
0da34b6d
BG		 2669 pci_set_master(pdev);
2670
0da34b6d 2671 myri10ge_reset(mgp);
013b68bf 2672 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2673
2674 /* Save configuration space to be restored if the
2675 * nic resets due to a parity error */
83f6e152 2676 pci_save_state(pdev);
0da34b6d
BG		 2677
2678 if (netif_running(netdev)) {
2679 rtnl_lock();
df30a740 2680 status = myri10ge_open(netdev);
0da34b6d 2681 rtnl_unlock();
df30a740
BG		 2682 if (status != 0)
2683 goto abort_with_enabled;
2684
0da34b6d
BG		 2685 }
2686 netif_device_attach(netdev);
2687
2688 return 0;
2689
4c2248cc
BG		 2690abort_with_enabled:
2691 pci_disable_device(pdev);
0da34b6d
BG		 2692 return -EIO;
2693
2694}
2695
2696#endif /* CONFIG_PM */
2697
2698static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2699{
2700 struct pci_dev *pdev = mgp->pdev;
2701 int vs = mgp->vendor_specific_offset;
2702 u32 reboot;
2703
2704 /*enter read32 mode */
2705 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2706
2707 /*read REBOOT_STATUS (0xfffffff0) */
2708 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2709 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2710 return reboot;
2711}
2712
2713/*
2714 * This watchdog is used to check whether the board has suffered
2715 * from a parity error and needs to be recovered.
2716 */
c4028958 2717static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2718{
c4028958 2719 struct myri10ge_priv *mgp =
6250223e 2720 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2721 u32 reboot;
2722 int status;
2723 u16 cmd, vendor;
2724
2725 mgp->watchdog_resets++;
2726 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2727 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2728 /* Bus master DMA disabled? Check to see
2729 * if the card rebooted due to a parity error
2730 * For now, just report it */
2731 reboot = myri10ge_read_reboot(mgp);
2732 printk(KERN_ERR
2733 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2734 mgp->dev->name, reboot);
2735 /*
2736 * A rebooted nic will come back with config space as
2737 * it was after power was applied to PCIe bus.
2738 * Attempt to restore config space which was saved
2739 * when the driver was loaded, or the last time the
2740 * nic was resumed from power saving mode.
2741 */
83f6e152 2742 pci_restore_state(mgp->pdev);
7adda30c
BG		 2743
2744 /* save state again for accounting reasons */
83f6e152 2745 pci_save_state(mgp->pdev);
7adda30c 2746
0da34b6d
BG		 2747 } else {
2748 /* if we get back -1's from our slot, perhaps somebody
2749 * powered off our card. Don't try to reset it in
2750 * this case */
2751 if (cmd == 0xffff) {
2752 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2753 if (vendor == 0xffff) {
2754 printk(KERN_ERR
2755 "myri10ge: %s: device disappeared!\n",
2756 mgp->dev->name);
2757 return;
2758 }
2759 }
2760 /* Perhaps it is a software error. Try to reset */
2761
2762 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2763 mgp->dev->name);
2764 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2765 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2766 mgp->tx.pkt_start, mgp->tx.pkt_done,
2767 (int)ntohl(mgp->fw_stats->send_done_count));
2768 msleep(2000);
2769 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2770 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2771 mgp->tx.pkt_start, mgp->tx.pkt_done,
2772 (int)ntohl(mgp->fw_stats->send_done_count));
2773 }
2774 rtnl_lock();
2775 myri10ge_close(mgp->dev);
2776 status = myri10ge_load_firmware(mgp);
2777 if (status != 0)
2778 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2779 mgp->dev->name);
2780 else
2781 myri10ge_open(mgp->dev);
2782 rtnl_unlock();
2783}
2784
2785/*
2786 * We use our own timer routine rather than relying upon
2787 * netdev->tx_timeout because we have a very large hardware transmit
2788 * queue. Due to the large queue, the netdev->tx_timeout function
2789 * cannot detect a NIC with a parity error in a timely fashion if the
2790 * NIC is lightly loaded.
2791 */
2792static void myri10ge_watchdog_timer(unsigned long arg)
2793{
2794 struct myri10ge_priv *mgp;
2795
2796 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2797
2798 if (mgp->rx_small.watchdog_needed) {
2799 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2800 mgp->small_bytes + MXGEFW_PAD, 1);
2801 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2802 myri10ge_fill_thresh)
2803 mgp->rx_small.watchdog_needed = 0;
2804 }
2805 if (mgp->rx_big.watchdog_needed) {
2806 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2807 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2808 myri10ge_fill_thresh)
2809 mgp->rx_big.watchdog_needed = 0;
2810 }
2811
0da34b6d 2812 if (mgp->tx.req != mgp->tx.done &&
c54772e7
BG		 2813 mgp->tx.done == mgp->watchdog_tx_done &&
2814 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
0da34b6d
BG		 2815 /* nic seems like it might be stuck.. */
2816 schedule_work(&mgp->watchdog_work);
2817 else
2818 /* rearm timer */
2819 mod_timer(&mgp->watchdog_timer,
2820 jiffies + myri10ge_watchdog_timeout * HZ);
2821
2822 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 2823 mgp->watchdog_tx_req = mgp->tx.req;
0da34b6d
BG		 2824}
2825
2826static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2827{
2828 struct net_device *netdev;
2829 struct myri10ge_priv *mgp;
2830 struct device *dev = &pdev->dev;
2831 size_t bytes;
2832 int i;
2833 int status = -ENXIO;
2834 int cap;
2835 int dac_enabled;
2836 u16 val;
2837
2838 netdev = alloc_etherdev(sizeof(*mgp));
2839 if (netdev == NULL) {
2840 dev_err(dev, "Could not allocate ethernet device\n");
2841 return -ENOMEM;
2842 }
2843
2844 mgp = netdev_priv(netdev);
2845 memset(mgp, 0, sizeof(*mgp));
2846 mgp->dev = netdev;
2847 mgp->pdev = pdev;
2848 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2849 mgp->pause = myri10ge_flow_control;
2850 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 2851 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 2852 init_waitqueue_head(&mgp->down_wq);
2853
2854 if (pci_enable_device(pdev)) {
2855 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2856 status = -ENODEV;
2857 goto abort_with_netdev;
2858 }
0da34b6d
BG		 2859
2860 /* Find the vendor-specific cap so we can check
2861 * the reboot register later on */
2862 mgp->vendor_specific_offset
2863 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2864
2865 /* Set our max read request to 4KB */
2866 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2867 if (cap < 64) {
2868 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2869 goto abort_with_netdev;
2870 }
2871 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2872 if (status != 0) {
2873 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2874 status);
2875 goto abort_with_netdev;
2876 }
2877 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2878 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2879 if (status != 0) {
2880 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2881 status);
2882 goto abort_with_netdev;
2883 }
2884
2885 pci_set_master(pdev);
2886 dac_enabled = 1;
2887 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2888 if (status != 0) {
2889 dac_enabled = 0;
2890 dev_err(&pdev->dev,
2891 "64-bit pci address mask was refused, trying 32-bit");
2892 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2893 }
2894 if (status != 0) {
2895 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2896 goto abort_with_netdev;
2897 }
b10c0668
BG		 2898 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2899 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 2900 if (mgp->cmd == NULL)
2901 goto abort_with_netdev;
2902
b10c0668
BG		 2903 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2904 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 2905 if (mgp->fw_stats == NULL)
2906 goto abort_with_cmd;
2907
2908 mgp->board_span = pci_resource_len(pdev, 0);
2909 mgp->iomem_base = pci_resource_start(pdev, 0);
2910 mgp->mtrr = -1;
276e26c3 2911 mgp->wc_enabled = 0;
0da34b6d
BG		 2912#ifdef CONFIG_MTRR
2913 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2914 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 2915 if (mgp->mtrr >= 0)
2916 mgp->wc_enabled = 1;
0da34b6d
BG		 2917#endif
2918 /* Hack. need to get rid of these magic numbers */
2919 mgp->sram_size =
2920 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2921 if (mgp->sram_size > mgp->board_span) {
2922 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2923 mgp->board_span);
2924 goto abort_with_wc;
2925 }
2926 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2927 if (mgp->sram == NULL) {
2928 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2929 mgp->board_span, mgp->iomem_base);
2930 status = -ENXIO;
2931 goto abort_with_wc;
2932 }
2933 memcpy_fromio(mgp->eeprom_strings,
2934 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2935 MYRI10GE_EEPROM_STRINGS_SIZE);
2936 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2937 status = myri10ge_read_mac_addr(mgp);
2938 if (status)
2939 goto abort_with_ioremap;
2940
2941 for (i = 0; i < ETH_ALEN; i++)
2942 netdev->dev_addr[i] = mgp->mac_addr[i];
2943
2944 /* allocate rx done ring */
2945 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2946 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2947 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 2948 if (mgp->rx_done.entry == NULL)
2949 goto abort_with_ioremap;
2950 memset(mgp->rx_done.entry, 0, bytes);
2951
5443e9ea
BG		 2952 myri10ge_select_firmware(mgp);
2953
0da34b6d
BG		 2954 status = myri10ge_load_firmware(mgp);
2955 if (status != 0) {
2956 dev_err(&pdev->dev, "failed to load firmware\n");
2957 goto abort_with_rx_done;
2958 }
2959
2960 status = myri10ge_reset(mgp);
2961 if (status != 0) {
2962 dev_err(&pdev->dev, "failed reset\n");
2963 goto abort_with_firmware;
2964 }
2965
0da34b6d
BG		 2966 pci_set_drvdata(pdev, mgp);
2967 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2968 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2969 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2970 myri10ge_initial_mtu = 68;
2971 netdev->mtu = myri10ge_initial_mtu;
2972 netdev->open = myri10ge_open;
2973 netdev->stop = myri10ge_close;
2974 netdev->hard_start_xmit = myri10ge_xmit;
2975 netdev->get_stats = myri10ge_get_stats;
2976 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 2977 netdev->change_mtu = myri10ge_change_mtu;
2978 netdev->set_multicast_list = myri10ge_set_multicast_list;
2979 netdev->set_mac_address = myri10ge_set_mac_address;
2980 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2981 if (dac_enabled)
2982 netdev->features |= NETIF_F_HIGHDMA;
2983 netdev->poll = myri10ge_poll;
2984 netdev->weight = myri10ge_napi_weight;
2985
21d05db1
BG		 2986 /* make sure we can get an irq, and that MSI can be
2987 * setup (if available). Also ensure netdev->irq
2988 * is set to correct value if MSI is enabled */
2989 status = myri10ge_request_irq(mgp);
2990 if (status != 0)
2991 goto abort_with_firmware;
2992 netdev->irq = pdev->irq;
2993 myri10ge_free_irq(mgp);
2994
0da34b6d
BG		 2995 /* Save configuration space to be restored if the
2996 * nic resets due to a parity error */
83f6e152 2997 pci_save_state(pdev);
0da34b6d
BG		 2998
2999 /* Setup the watchdog timer */
3000 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3001 (unsigned long)mgp);
3002
3003 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3004 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3005 status = register_netdev(netdev);
3006 if (status != 0) {
3007 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3008 goto abort_with_state;
0da34b6d 3009 }
21d05db1
BG		 3010 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3011 (mgp->msi_enabled ? "MSI" : "xPIC"),
3012 netdev->irq, mgp->tx.boundary, mgp->fw_name,
276e26c3 3013 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3014
3015 return 0;
3016
7adda30c 3017abort_with_state:
83f6e152 3018 pci_restore_state(pdev);
0da34b6d
BG		 3019
3020abort_with_firmware:
3021 myri10ge_dummy_rdma(mgp, 0);
3022
3023abort_with_rx_done:
3024 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3025 dma_free_coherent(&pdev->dev, bytes,
3026 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3027
3028abort_with_ioremap:
3029 iounmap(mgp->sram);
3030
3031abort_with_wc:
3032#ifdef CONFIG_MTRR
3033 if (mgp->mtrr >= 0)
3034 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3035#endif
b10c0668
BG		 3036 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3037 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 3038
3039abort_with_cmd:
b10c0668
BG		 3040 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3041 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3042
3043abort_with_netdev:
3044
3045 free_netdev(netdev);
3046 return status;
3047}
3048
3049/*
3050 * myri10ge_remove
3051 *
3052 * Does what is necessary to shutdown one Myrinet device. Called
3053 * once for each Myrinet card by the kernel when a module is
3054 * unloaded.
3055 */
3056static void myri10ge_remove(struct pci_dev *pdev)
3057{
3058 struct myri10ge_priv *mgp;
3059 struct net_device *netdev;
3060 size_t bytes;
3061
3062 mgp = pci_get_drvdata(pdev);
3063 if (mgp == NULL)
3064 return;
3065
3066 flush_scheduled_work();
3067 netdev = mgp->dev;
3068 unregister_netdev(netdev);
0da34b6d
BG		 3069
3070 myri10ge_dummy_rdma(mgp, 0);
3071
7adda30c 3072 /* avoid a memory leak */
83f6e152 3073 pci_restore_state(pdev);
7adda30c 3074
0da34b6d 3075 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3076 dma_free_coherent(&pdev->dev, bytes,
3077 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3078
3079 iounmap(mgp->sram);
3080
3081#ifdef CONFIG_MTRR
3082 if (mgp->mtrr >= 0)
3083 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3084#endif
b10c0668
BG		 3085 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3086 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3087
b10c0668
BG		 3088 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3089 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3090
3091 free_netdev(netdev);
3092 pci_set_drvdata(pdev, NULL);
3093}
3094
b10c0668 3095#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
0da34b6d
BG		 3096
3097static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3098 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
0da34b6d
BG		 3099 {0},
3100};
3101
3102static struct pci_driver myri10ge_driver = {
3103 .name = "myri10ge",
3104 .probe = myri10ge_probe,
3105 .remove = myri10ge_remove,
3106 .id_table = myri10ge_pci_tbl,
3107#ifdef CONFIG_PM
3108 .suspend = myri10ge_suspend,
3109 .resume = myri10ge_resume,
3110#endif
3111};
3112
3113static __init int myri10ge_init_module(void)
3114{
3115 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3116 MYRI10GE_VERSION_STR);
3117 return pci_register_driver(&myri10ge_driver);
3118}
3119
3120module_init(myri10ge_init_module);
3121
3122static __exit void myri10ge_cleanup_module(void)
3123{
3124 pci_unregister_driver(&myri10ge_driver);
3125}
3126
3127module_exit(myri10ge_cleanup_module);
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