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0da34b6d BG |
1 | /************************************************************************* |
2 | * myri10ge.c: Myricom Myri-10G Ethernet driver. | |
3 | * | |
4a2e612a | 4 | * Copyright (C) 2005 - 2007 Myricom, Inc. |
0da34b6d BG |
5 | * All rights reserved. |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * 2. Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | |
15 | * 3. Neither the name of Myricom, Inc. nor the names of its contributors | |
16 | * may be used to endorse or promote products derived from this software | |
17 | * without specific prior written permission. | |
18 | * | |
4a2e612a BG |
19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
0da34b6d | 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
4a2e612a BG |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
29 | * POSSIBILITY OF SUCH DAMAGE. | |
0da34b6d BG |
30 | * |
31 | * | |
32 | * If the eeprom on your board is not recent enough, you will need to get a | |
33 | * newer firmware image at: | |
34 | * http://www.myri.com/scs/download-Myri10GE.html | |
35 | * | |
36 | * Contact Information: | |
37 | * <help@myri.com> | |
38 | * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006 | |
39 | *************************************************************************/ | |
40 | ||
41 | #include <linux/tcp.h> | |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/skbuff.h> | |
44 | #include <linux/string.h> | |
45 | #include <linux/module.h> | |
46 | #include <linux/pci.h> | |
b10c0668 | 47 | #include <linux/dma-mapping.h> |
0da34b6d BG |
48 | #include <linux/etherdevice.h> |
49 | #include <linux/if_ether.h> | |
50 | #include <linux/if_vlan.h> | |
51 | #include <linux/ip.h> | |
52 | #include <linux/inet.h> | |
53 | #include <linux/in.h> | |
54 | #include <linux/ethtool.h> | |
55 | #include <linux/firmware.h> | |
56 | #include <linux/delay.h> | |
57 | #include <linux/version.h> | |
58 | #include <linux/timer.h> | |
59 | #include <linux/vmalloc.h> | |
60 | #include <linux/crc32.h> | |
61 | #include <linux/moduleparam.h> | |
62 | #include <linux/io.h> | |
63 | #include <net/checksum.h> | |
64 | #include <asm/byteorder.h> | |
65 | #include <asm/io.h> | |
0da34b6d BG |
66 | #include <asm/processor.h> |
67 | #ifdef CONFIG_MTRR | |
68 | #include <asm/mtrr.h> | |
69 | #endif | |
70 | ||
71 | #include "myri10ge_mcp.h" | |
72 | #include "myri10ge_mcp_gen_header.h" | |
73 | ||
6f8a7c66 | 74 | #define MYRI10GE_VERSION_STR "1.3.1-1.248" |
0da34b6d BG |
75 | |
76 | MODULE_DESCRIPTION("Myricom 10G driver (10GbE)"); | |
77 | MODULE_AUTHOR("Maintainer: help@myri.com"); | |
78 | MODULE_VERSION(MYRI10GE_VERSION_STR); | |
79 | MODULE_LICENSE("Dual BSD/GPL"); | |
80 | ||
81 | #define MYRI10GE_MAX_ETHER_MTU 9014 | |
82 | ||
83 | #define MYRI10GE_ETH_STOPPED 0 | |
84 | #define MYRI10GE_ETH_STOPPING 1 | |
85 | #define MYRI10GE_ETH_STARTING 2 | |
86 | #define MYRI10GE_ETH_RUNNING 3 | |
87 | #define MYRI10GE_ETH_OPEN_FAILED 4 | |
88 | ||
89 | #define MYRI10GE_EEPROM_STRINGS_SIZE 256 | |
90 | #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2) | |
91 | ||
40f6cff5 | 92 | #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff) |
0da34b6d BG |
93 | #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff |
94 | ||
dd50f336 BG |
95 | #define MYRI10GE_ALLOC_ORDER 0 |
96 | #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE) | |
97 | #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1) | |
98 | ||
0da34b6d | 99 | struct myri10ge_rx_buffer_state { |
dd50f336 BG |
100 | struct page *page; |
101 | int page_offset; | |
0da34b6d BG |
102 | DECLARE_PCI_UNMAP_ADDR(bus) |
103 | DECLARE_PCI_UNMAP_LEN(len) | |
104 | }; | |
105 | ||
106 | struct myri10ge_tx_buffer_state { | |
107 | struct sk_buff *skb; | |
108 | int last; | |
109 | DECLARE_PCI_UNMAP_ADDR(bus) | |
110 | DECLARE_PCI_UNMAP_LEN(len) | |
111 | }; | |
112 | ||
113 | struct myri10ge_cmd { | |
114 | u32 data0; | |
115 | u32 data1; | |
116 | u32 data2; | |
117 | }; | |
118 | ||
119 | struct myri10ge_rx_buf { | |
120 | struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */ | |
121 | u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */ | |
122 | struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */ | |
123 | struct myri10ge_rx_buffer_state *info; | |
dd50f336 BG |
124 | struct page *page; |
125 | dma_addr_t bus; | |
126 | int page_offset; | |
0da34b6d | 127 | int cnt; |
dd50f336 | 128 | int fill_cnt; |
0da34b6d BG |
129 | int alloc_fail; |
130 | int mask; /* number of rx slots -1 */ | |
dd50f336 | 131 | int watchdog_needed; |
0da34b6d BG |
132 | }; |
133 | ||
134 | struct myri10ge_tx_buf { | |
135 | struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */ | |
136 | u8 __iomem *wc_fifo; /* w/c send fifo address */ | |
137 | struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */ | |
138 | char *req_bytes; | |
139 | struct myri10ge_tx_buffer_state *info; | |
140 | int mask; /* number of transmit slots -1 */ | |
141 | int boundary; /* boundary transmits cannot cross */ | |
142 | int req ____cacheline_aligned; /* transmit slots submitted */ | |
143 | int pkt_start; /* packets started */ | |
144 | int done ____cacheline_aligned; /* transmit slots completed */ | |
145 | int pkt_done; /* packets completed */ | |
146 | }; | |
147 | ||
148 | struct myri10ge_rx_done { | |
149 | struct mcp_slot *entry; | |
150 | dma_addr_t bus; | |
151 | int cnt; | |
152 | int idx; | |
153 | }; | |
154 | ||
155 | struct myri10ge_priv { | |
156 | int running; /* running? */ | |
157 | int csum_flag; /* rx_csums? */ | |
158 | struct myri10ge_tx_buf tx; /* transmit ring */ | |
159 | struct myri10ge_rx_buf rx_small; | |
160 | struct myri10ge_rx_buf rx_big; | |
161 | struct myri10ge_rx_done rx_done; | |
162 | int small_bytes; | |
dd50f336 | 163 | int big_bytes; |
0da34b6d BG |
164 | struct net_device *dev; |
165 | struct net_device_stats stats; | |
166 | u8 __iomem *sram; | |
167 | int sram_size; | |
168 | unsigned long board_span; | |
169 | unsigned long iomem_base; | |
40f6cff5 AV |
170 | __be32 __iomem *irq_claim; |
171 | __be32 __iomem *irq_deassert; | |
0da34b6d BG |
172 | char *mac_addr_string; |
173 | struct mcp_cmd_response *cmd; | |
174 | dma_addr_t cmd_bus; | |
175 | struct mcp_irq_data *fw_stats; | |
176 | dma_addr_t fw_stats_bus; | |
177 | struct pci_dev *pdev; | |
178 | int msi_enabled; | |
40f6cff5 | 179 | __be32 link_state; |
0da34b6d BG |
180 | unsigned int rdma_tags_available; |
181 | int intr_coal_delay; | |
40f6cff5 | 182 | __be32 __iomem *intr_coal_delay_ptr; |
0da34b6d | 183 | int mtrr; |
276e26c3 | 184 | int wc_enabled; |
0da34b6d BG |
185 | int wake_queue; |
186 | int stop_queue; | |
187 | int down_cnt; | |
188 | wait_queue_head_t down_wq; | |
189 | struct work_struct watchdog_work; | |
190 | struct timer_list watchdog_timer; | |
191 | int watchdog_tx_done; | |
c54772e7 | 192 | int watchdog_tx_req; |
0da34b6d BG |
193 | int watchdog_resets; |
194 | int tx_linearized; | |
195 | int pause; | |
196 | char *fw_name; | |
197 | char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE]; | |
198 | char fw_version[128]; | |
9dc6f0e7 BG |
199 | int fw_ver_major; |
200 | int fw_ver_minor; | |
201 | int fw_ver_tiny; | |
202 | int adopted_rx_filter_bug; | |
0da34b6d BG |
203 | u8 mac_addr[6]; /* eeprom mac address */ |
204 | unsigned long serial_number; | |
205 | int vendor_specific_offset; | |
85a7ea1b | 206 | int fw_multicast_support; |
0da34b6d BG |
207 | u32 read_dma; |
208 | u32 write_dma; | |
209 | u32 read_write_dma; | |
c58ac5ca BG |
210 | u32 link_changes; |
211 | u32 msg_enable; | |
0da34b6d BG |
212 | }; |
213 | ||
214 | static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat"; | |
215 | static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat"; | |
216 | ||
217 | static char *myri10ge_fw_name = NULL; | |
218 | module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR); | |
219 | MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n"); | |
220 | ||
221 | static int myri10ge_ecrc_enable = 1; | |
222 | module_param(myri10ge_ecrc_enable, int, S_IRUGO); | |
223 | MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n"); | |
224 | ||
225 | static int myri10ge_max_intr_slots = 1024; | |
226 | module_param(myri10ge_max_intr_slots, int, S_IRUGO); | |
227 | MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n"); | |
228 | ||
229 | static int myri10ge_small_bytes = -1; /* -1 == auto */ | |
230 | module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR); | |
231 | MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n"); | |
232 | ||
233 | static int myri10ge_msi = 1; /* enable msi by default */ | |
3621cec5 | 234 | module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR); |
0da34b6d BG |
235 | MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n"); |
236 | ||
f761fae1 | 237 | static int myri10ge_intr_coal_delay = 75; |
0da34b6d BG |
238 | module_param(myri10ge_intr_coal_delay, int, S_IRUGO); |
239 | MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n"); | |
240 | ||
241 | static int myri10ge_flow_control = 1; | |
242 | module_param(myri10ge_flow_control, int, S_IRUGO); | |
243 | MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n"); | |
244 | ||
245 | static int myri10ge_deassert_wait = 1; | |
246 | module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR); | |
247 | MODULE_PARM_DESC(myri10ge_deassert_wait, | |
248 | "Wait when deasserting legacy interrupts\n"); | |
249 | ||
250 | static int myri10ge_force_firmware = 0; | |
251 | module_param(myri10ge_force_firmware, int, S_IRUGO); | |
252 | MODULE_PARM_DESC(myri10ge_force_firmware, | |
253 | "Force firmware to assume aligned completions\n"); | |
254 | ||
0da34b6d BG |
255 | static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN; |
256 | module_param(myri10ge_initial_mtu, int, S_IRUGO); | |
257 | MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n"); | |
258 | ||
259 | static int myri10ge_napi_weight = 64; | |
260 | module_param(myri10ge_napi_weight, int, S_IRUGO); | |
261 | MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n"); | |
262 | ||
263 | static int myri10ge_watchdog_timeout = 1; | |
264 | module_param(myri10ge_watchdog_timeout, int, S_IRUGO); | |
265 | MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n"); | |
266 | ||
267 | static int myri10ge_max_irq_loops = 1048576; | |
268 | module_param(myri10ge_max_irq_loops, int, S_IRUGO); | |
269 | MODULE_PARM_DESC(myri10ge_max_irq_loops, | |
270 | "Set stuck legacy IRQ detection threshold\n"); | |
271 | ||
c58ac5ca BG |
272 | #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK |
273 | ||
274 | static int myri10ge_debug = -1; /* defaults above */ | |
275 | module_param(myri10ge_debug, int, 0); | |
276 | MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)"); | |
277 | ||
dd50f336 BG |
278 | static int myri10ge_fill_thresh = 256; |
279 | module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR); | |
280 | MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n"); | |
281 | ||
f181137f BG |
282 | static int myri10ge_reset_recover = 1; |
283 | ||
f761fae1 | 284 | static int myri10ge_wcfifo = 0; |
6ebc087a BG |
285 | module_param(myri10ge_wcfifo, int, S_IRUGO); |
286 | MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n"); | |
287 | ||
0da34b6d BG |
288 | #define MYRI10GE_FW_OFFSET 1024*1024 |
289 | #define MYRI10GE_HIGHPART_TO_U32(X) \ | |
290 | (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0) | |
291 | #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X)) | |
292 | ||
293 | #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8) | |
294 | ||
2f76216f BG |
295 | static void myri10ge_set_multicast_list(struct net_device *dev); |
296 | ||
6250223e | 297 | static inline void put_be32(__be32 val, __be32 __iomem * p) |
40f6cff5 | 298 | { |
6250223e | 299 | __raw_writel((__force __u32) val, (__force void __iomem *)p); |
40f6cff5 AV |
300 | } |
301 | ||
0da34b6d BG |
302 | static int |
303 | myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd, | |
304 | struct myri10ge_cmd *data, int atomic) | |
305 | { | |
306 | struct mcp_cmd *buf; | |
307 | char buf_bytes[sizeof(*buf) + 8]; | |
308 | struct mcp_cmd_response *response = mgp->cmd; | |
e700f9f4 | 309 | char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD; |
0da34b6d BG |
310 | u32 dma_low, dma_high, result, value; |
311 | int sleep_total = 0; | |
312 | ||
313 | /* ensure buf is aligned to 8 bytes */ | |
314 | buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8); | |
315 | ||
316 | buf->data0 = htonl(data->data0); | |
317 | buf->data1 = htonl(data->data1); | |
318 | buf->data2 = htonl(data->data2); | |
319 | buf->cmd = htonl(cmd); | |
320 | dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus); | |
321 | dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus); | |
322 | ||
323 | buf->response_addr.low = htonl(dma_low); | |
324 | buf->response_addr.high = htonl(dma_high); | |
40f6cff5 | 325 | response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT); |
0da34b6d BG |
326 | mb(); |
327 | myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf)); | |
328 | ||
329 | /* wait up to 15ms. Longest command is the DMA benchmark, | |
330 | * which is capped at 5ms, but runs from a timeout handler | |
331 | * that runs every 7.8ms. So a 15ms timeout leaves us with | |
332 | * a 2.2ms margin | |
333 | */ | |
334 | if (atomic) { | |
335 | /* if atomic is set, do not sleep, | |
336 | * and try to get the completion quickly | |
337 | * (1ms will be enough for those commands) */ | |
338 | for (sleep_total = 0; | |
339 | sleep_total < 1000 | |
40f6cff5 | 340 | && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT); |
0da34b6d BG |
341 | sleep_total += 10) |
342 | udelay(10); | |
343 | } else { | |
344 | /* use msleep for most command */ | |
345 | for (sleep_total = 0; | |
346 | sleep_total < 15 | |
40f6cff5 | 347 | && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT); |
0da34b6d BG |
348 | sleep_total++) |
349 | msleep(1); | |
350 | } | |
351 | ||
352 | result = ntohl(response->result); | |
353 | value = ntohl(response->data); | |
354 | if (result != MYRI10GE_NO_RESPONSE_RESULT) { | |
355 | if (result == 0) { | |
356 | data->data0 = value; | |
357 | return 0; | |
85a7ea1b BG |
358 | } else if (result == MXGEFW_CMD_UNKNOWN) { |
359 | return -ENOSYS; | |
5443e9ea BG |
360 | } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) { |
361 | return -E2BIG; | |
0da34b6d BG |
362 | } else { |
363 | dev_err(&mgp->pdev->dev, | |
364 | "command %d failed, result = %d\n", | |
365 | cmd, result); | |
366 | return -ENXIO; | |
367 | } | |
368 | } | |
369 | ||
370 | dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n", | |
371 | cmd, result); | |
372 | return -EAGAIN; | |
373 | } | |
374 | ||
375 | /* | |
376 | * The eeprom strings on the lanaiX have the format | |
377 | * SN=x\0 | |
378 | * MAC=x:x:x:x:x:x\0 | |
379 | * PT:ddd mmm xx xx:xx:xx xx\0 | |
380 | * PV:ddd mmm xx xx:xx:xx xx\0 | |
381 | */ | |
382 | static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp) | |
383 | { | |
384 | char *ptr, *limit; | |
385 | int i; | |
386 | ||
387 | ptr = mgp->eeprom_strings; | |
388 | limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE; | |
389 | ||
390 | while (*ptr != '\0' && ptr < limit) { | |
391 | if (memcmp(ptr, "MAC=", 4) == 0) { | |
392 | ptr += 4; | |
393 | mgp->mac_addr_string = ptr; | |
394 | for (i = 0; i < 6; i++) { | |
395 | if ((ptr + 2) > limit) | |
396 | goto abort; | |
397 | mgp->mac_addr[i] = | |
398 | simple_strtoul(ptr, &ptr, 16); | |
399 | ptr += 1; | |
400 | } | |
401 | } | |
402 | if (memcmp((const void *)ptr, "SN=", 3) == 0) { | |
403 | ptr += 3; | |
404 | mgp->serial_number = simple_strtoul(ptr, &ptr, 10); | |
405 | } | |
406 | while (ptr < limit && *ptr++) ; | |
407 | } | |
408 | ||
409 | return 0; | |
410 | ||
411 | abort: | |
412 | dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n"); | |
413 | return -ENXIO; | |
414 | } | |
415 | ||
416 | /* | |
417 | * Enable or disable periodic RDMAs from the host to make certain | |
418 | * chipsets resend dropped PCIe messages | |
419 | */ | |
420 | ||
421 | static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable) | |
422 | { | |
423 | char __iomem *submit; | |
40f6cff5 | 424 | __be32 buf[16]; |
0da34b6d BG |
425 | u32 dma_low, dma_high; |
426 | int i; | |
427 | ||
428 | /* clear confirmation addr */ | |
429 | mgp->cmd->data = 0; | |
430 | mb(); | |
431 | ||
432 | /* send a rdma command to the PCIe engine, and wait for the | |
433 | * response in the confirmation address. The firmware should | |
434 | * write a -1 there to indicate it is alive and well | |
435 | */ | |
436 | dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus); | |
437 | dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus); | |
438 | ||
439 | buf[0] = htonl(dma_high); /* confirm addr MSW */ | |
440 | buf[1] = htonl(dma_low); /* confirm addr LSW */ | |
40f6cff5 | 441 | buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */ |
0da34b6d BG |
442 | buf[3] = htonl(dma_high); /* dummy addr MSW */ |
443 | buf[4] = htonl(dma_low); /* dummy addr LSW */ | |
444 | buf[5] = htonl(enable); /* enable? */ | |
445 | ||
e700f9f4 | 446 | submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA; |
0da34b6d BG |
447 | |
448 | myri10ge_pio_copy(submit, &buf, sizeof(buf)); | |
449 | for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++) | |
450 | msleep(1); | |
451 | if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) | |
452 | dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n", | |
453 | (enable ? "enable" : "disable")); | |
454 | } | |
455 | ||
456 | static int | |
457 | myri10ge_validate_firmware(struct myri10ge_priv *mgp, | |
458 | struct mcp_gen_header *hdr) | |
459 | { | |
460 | struct device *dev = &mgp->pdev->dev; | |
0da34b6d BG |
461 | |
462 | /* check firmware type */ | |
463 | if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) { | |
464 | dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type)); | |
465 | return -EINVAL; | |
466 | } | |
467 | ||
468 | /* save firmware version for ethtool */ | |
469 | strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version)); | |
470 | ||
9dc6f0e7 BG |
471 | sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major, |
472 | &mgp->fw_ver_minor, &mgp->fw_ver_tiny); | |
0da34b6d | 473 | |
9dc6f0e7 BG |
474 | if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR |
475 | && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) { | |
0da34b6d BG |
476 | dev_err(dev, "Found firmware version %s\n", mgp->fw_version); |
477 | dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR, | |
478 | MXGEFW_VERSION_MINOR); | |
479 | return -EINVAL; | |
480 | } | |
481 | return 0; | |
482 | } | |
483 | ||
484 | static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size) | |
485 | { | |
486 | unsigned crc, reread_crc; | |
487 | const struct firmware *fw; | |
488 | struct device *dev = &mgp->pdev->dev; | |
489 | struct mcp_gen_header *hdr; | |
490 | size_t hdr_offset; | |
491 | int status; | |
e454358a | 492 | unsigned i; |
0da34b6d BG |
493 | |
494 | if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) { | |
495 | dev_err(dev, "Unable to load %s firmware image via hotplug\n", | |
496 | mgp->fw_name); | |
497 | status = -EINVAL; | |
498 | goto abort_with_nothing; | |
499 | } | |
500 | ||
501 | /* check size */ | |
502 | ||
503 | if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET || | |
504 | fw->size < MCP_HEADER_PTR_OFFSET + 4) { | |
505 | dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size); | |
506 | status = -EINVAL; | |
507 | goto abort_with_fw; | |
508 | } | |
509 | ||
510 | /* check id */ | |
40f6cff5 | 511 | hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET)); |
0da34b6d BG |
512 | if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) { |
513 | dev_err(dev, "Bad firmware file\n"); | |
514 | status = -EINVAL; | |
515 | goto abort_with_fw; | |
516 | } | |
517 | hdr = (void *)(fw->data + hdr_offset); | |
518 | ||
519 | status = myri10ge_validate_firmware(mgp, hdr); | |
520 | if (status != 0) | |
521 | goto abort_with_fw; | |
522 | ||
523 | crc = crc32(~0, fw->data, fw->size); | |
e454358a BG |
524 | for (i = 0; i < fw->size; i += 256) { |
525 | myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i, | |
526 | fw->data + i, | |
527 | min(256U, (unsigned)(fw->size - i))); | |
528 | mb(); | |
529 | readb(mgp->sram); | |
b10c0668 | 530 | } |
0da34b6d BG |
531 | /* corruption checking is good for parity recovery and buggy chipset */ |
532 | memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size); | |
533 | reread_crc = crc32(~0, fw->data, fw->size); | |
534 | if (crc != reread_crc) { | |
535 | dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n", | |
536 | (unsigned)fw->size, reread_crc, crc); | |
537 | status = -EIO; | |
538 | goto abort_with_fw; | |
539 | } | |
540 | *size = (u32) fw->size; | |
541 | ||
542 | abort_with_fw: | |
543 | release_firmware(fw); | |
544 | ||
545 | abort_with_nothing: | |
546 | return status; | |
547 | } | |
548 | ||
549 | static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp) | |
550 | { | |
551 | struct mcp_gen_header *hdr; | |
552 | struct device *dev = &mgp->pdev->dev; | |
553 | const size_t bytes = sizeof(struct mcp_gen_header); | |
554 | size_t hdr_offset; | |
555 | int status; | |
556 | ||
557 | /* find running firmware header */ | |
558 | hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)); | |
559 | ||
560 | if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) { | |
561 | dev_err(dev, "Running firmware has bad header offset (%d)\n", | |
562 | (int)hdr_offset); | |
563 | return -EIO; | |
564 | } | |
565 | ||
566 | /* copy header of running firmware from SRAM to host memory to | |
567 | * validate firmware */ | |
568 | hdr = kmalloc(bytes, GFP_KERNEL); | |
569 | if (hdr == NULL) { | |
570 | dev_err(dev, "could not malloc firmware hdr\n"); | |
571 | return -ENOMEM; | |
572 | } | |
573 | memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes); | |
574 | status = myri10ge_validate_firmware(mgp, hdr); | |
575 | kfree(hdr); | |
9dc6f0e7 BG |
576 | |
577 | /* check to see if adopted firmware has bug where adopting | |
578 | * it will cause broadcasts to be filtered unless the NIC | |
579 | * is kept in ALLMULTI mode */ | |
580 | if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 && | |
581 | mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) { | |
582 | mgp->adopted_rx_filter_bug = 1; | |
583 | dev_warn(dev, "Adopting fw %d.%d.%d: " | |
584 | "working around rx filter bug\n", | |
585 | mgp->fw_ver_major, mgp->fw_ver_minor, | |
586 | mgp->fw_ver_tiny); | |
587 | } | |
0da34b6d BG |
588 | return status; |
589 | } | |
590 | ||
591 | static int myri10ge_load_firmware(struct myri10ge_priv *mgp) | |
592 | { | |
593 | char __iomem *submit; | |
40f6cff5 | 594 | __be32 buf[16]; |
0da34b6d BG |
595 | u32 dma_low, dma_high, size; |
596 | int status, i; | |
597 | ||
b10c0668 | 598 | size = 0; |
0da34b6d BG |
599 | status = myri10ge_load_hotplug_firmware(mgp, &size); |
600 | if (status) { | |
601 | dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n"); | |
602 | ||
603 | /* Do not attempt to adopt firmware if there | |
604 | * was a bad crc */ | |
605 | if (status == -EIO) | |
606 | return status; | |
607 | ||
608 | status = myri10ge_adopt_running_firmware(mgp); | |
609 | if (status != 0) { | |
610 | dev_err(&mgp->pdev->dev, | |
611 | "failed to adopt running firmware\n"); | |
612 | return status; | |
613 | } | |
614 | dev_info(&mgp->pdev->dev, | |
615 | "Successfully adopted running firmware\n"); | |
616 | if (mgp->tx.boundary == 4096) { | |
617 | dev_warn(&mgp->pdev->dev, | |
618 | "Using firmware currently running on NIC" | |
619 | ". For optimal\n"); | |
620 | dev_warn(&mgp->pdev->dev, | |
621 | "performance consider loading optimized " | |
622 | "firmware\n"); | |
623 | dev_warn(&mgp->pdev->dev, "via hotplug\n"); | |
624 | } | |
625 | ||
626 | mgp->fw_name = "adopted"; | |
627 | mgp->tx.boundary = 2048; | |
628 | return status; | |
629 | } | |
630 | ||
631 | /* clear confirmation addr */ | |
632 | mgp->cmd->data = 0; | |
633 | mb(); | |
634 | ||
635 | /* send a reload command to the bootstrap MCP, and wait for the | |
636 | * response in the confirmation address. The firmware should | |
637 | * write a -1 there to indicate it is alive and well | |
638 | */ | |
639 | dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus); | |
640 | dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus); | |
641 | ||
642 | buf[0] = htonl(dma_high); /* confirm addr MSW */ | |
643 | buf[1] = htonl(dma_low); /* confirm addr LSW */ | |
40f6cff5 | 644 | buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */ |
0da34b6d BG |
645 | |
646 | /* FIX: All newest firmware should un-protect the bottom of | |
647 | * the sram before handoff. However, the very first interfaces | |
648 | * do not. Therefore the handoff copy must skip the first 8 bytes | |
649 | */ | |
650 | buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */ | |
651 | buf[4] = htonl(size - 8); /* length of code */ | |
652 | buf[5] = htonl(8); /* where to copy to */ | |
653 | buf[6] = htonl(0); /* where to jump to */ | |
654 | ||
e700f9f4 | 655 | submit = mgp->sram + MXGEFW_BOOT_HANDOFF; |
0da34b6d BG |
656 | |
657 | myri10ge_pio_copy(submit, &buf, sizeof(buf)); | |
658 | mb(); | |
659 | msleep(1); | |
660 | mb(); | |
661 | i = 0; | |
662 | while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) { | |
663 | msleep(1); | |
664 | i++; | |
665 | } | |
666 | if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) { | |
667 | dev_err(&mgp->pdev->dev, "handoff failed\n"); | |
668 | return -ENXIO; | |
669 | } | |
670 | dev_info(&mgp->pdev->dev, "handoff confirmed\n"); | |
9a71db72 | 671 | myri10ge_dummy_rdma(mgp, 1); |
0da34b6d BG |
672 | |
673 | return 0; | |
674 | } | |
675 | ||
676 | static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr) | |
677 | { | |
678 | struct myri10ge_cmd cmd; | |
679 | int status; | |
680 | ||
681 | cmd.data0 = ((addr[0] << 24) | (addr[1] << 16) | |
682 | | (addr[2] << 8) | addr[3]); | |
683 | ||
684 | cmd.data1 = ((addr[4] << 8) | (addr[5])); | |
685 | ||
686 | status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0); | |
687 | return status; | |
688 | } | |
689 | ||
690 | static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause) | |
691 | { | |
692 | struct myri10ge_cmd cmd; | |
693 | int status, ctl; | |
694 | ||
695 | ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL; | |
696 | status = myri10ge_send_cmd(mgp, ctl, &cmd, 0); | |
697 | ||
698 | if (status) { | |
699 | printk(KERN_ERR | |
700 | "myri10ge: %s: Failed to set flow control mode\n", | |
701 | mgp->dev->name); | |
702 | return status; | |
703 | } | |
704 | mgp->pause = pause; | |
705 | return 0; | |
706 | } | |
707 | ||
708 | static void | |
709 | myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic) | |
710 | { | |
711 | struct myri10ge_cmd cmd; | |
712 | int status, ctl; | |
713 | ||
714 | ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC; | |
715 | status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic); | |
716 | if (status) | |
717 | printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n", | |
718 | mgp->dev->name); | |
719 | } | |
720 | ||
0d6ac257 | 721 | static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type) |
0da34b6d BG |
722 | { |
723 | struct myri10ge_cmd cmd; | |
724 | int status; | |
0da34b6d | 725 | u32 len; |
34fdccea BG |
726 | struct page *dmatest_page; |
727 | dma_addr_t dmatest_bus; | |
0d6ac257 BG |
728 | char *test = " "; |
729 | ||
730 | dmatest_page = alloc_page(GFP_KERNEL); | |
731 | if (!dmatest_page) | |
732 | return -ENOMEM; | |
733 | dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE, | |
734 | DMA_BIDIRECTIONAL); | |
735 | ||
736 | /* Run a small DMA test. | |
737 | * The magic multipliers to the length tell the firmware | |
738 | * to do DMA read, write, or read+write tests. The | |
739 | * results are returned in cmd.data0. The upper 16 | |
740 | * bits or the return is the number of transfers completed. | |
741 | * The lower 16 bits is the time in 0.5us ticks that the | |
742 | * transfers took to complete. | |
743 | */ | |
744 | ||
745 | len = mgp->tx.boundary; | |
746 | ||
747 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus); | |
748 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus); | |
749 | cmd.data2 = len * 0x10000; | |
750 | status = myri10ge_send_cmd(mgp, test_type, &cmd, 0); | |
751 | if (status != 0) { | |
752 | test = "read"; | |
753 | goto abort; | |
754 | } | |
755 | mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff); | |
756 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus); | |
757 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus); | |
758 | cmd.data2 = len * 0x1; | |
759 | status = myri10ge_send_cmd(mgp, test_type, &cmd, 0); | |
760 | if (status != 0) { | |
761 | test = "write"; | |
762 | goto abort; | |
763 | } | |
764 | mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff); | |
765 | ||
766 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus); | |
767 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus); | |
768 | cmd.data2 = len * 0x10001; | |
769 | status = myri10ge_send_cmd(mgp, test_type, &cmd, 0); | |
770 | if (status != 0) { | |
771 | test = "read/write"; | |
772 | goto abort; | |
773 | } | |
774 | mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) / | |
775 | (cmd.data0 & 0xffff); | |
776 | ||
777 | abort: | |
778 | pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
779 | put_page(dmatest_page); | |
780 | ||
781 | if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST) | |
782 | dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n", | |
783 | test, status); | |
784 | ||
785 | return status; | |
786 | } | |
787 | ||
788 | static int myri10ge_reset(struct myri10ge_priv *mgp) | |
789 | { | |
790 | struct myri10ge_cmd cmd; | |
791 | int status; | |
792 | size_t bytes; | |
0da34b6d BG |
793 | |
794 | /* try to send a reset command to the card to see if it | |
795 | * is alive */ | |
796 | memset(&cmd, 0, sizeof(cmd)); | |
797 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0); | |
798 | if (status != 0) { | |
799 | dev_err(&mgp->pdev->dev, "failed reset\n"); | |
800 | return -ENXIO; | |
801 | } | |
0d6ac257 BG |
802 | |
803 | (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST); | |
0da34b6d BG |
804 | |
805 | /* Now exchange information about interrupts */ | |
806 | ||
807 | bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry); | |
808 | memset(mgp->rx_done.entry, 0, bytes); | |
809 | cmd.data0 = (u32) bytes; | |
810 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0); | |
811 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus); | |
812 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus); | |
813 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0); | |
814 | ||
815 | status |= | |
816 | myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0); | |
40f6cff5 | 817 | mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0); |
df30a740 BG |
818 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, |
819 | &cmd, 0); | |
820 | mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0); | |
0da34b6d | 821 | |
0da34b6d BG |
822 | status |= myri10ge_send_cmd |
823 | (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0); | |
40f6cff5 | 824 | mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0); |
0da34b6d BG |
825 | if (status != 0) { |
826 | dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n"); | |
827 | return status; | |
828 | } | |
40f6cff5 | 829 | put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr); |
0da34b6d | 830 | |
0da34b6d BG |
831 | memset(mgp->rx_done.entry, 0, bytes); |
832 | ||
833 | /* reset mcp/driver shared state back to 0 */ | |
834 | mgp->tx.req = 0; | |
835 | mgp->tx.done = 0; | |
836 | mgp->tx.pkt_start = 0; | |
837 | mgp->tx.pkt_done = 0; | |
838 | mgp->rx_big.cnt = 0; | |
839 | mgp->rx_small.cnt = 0; | |
840 | mgp->rx_done.idx = 0; | |
841 | mgp->rx_done.cnt = 0; | |
c58ac5ca | 842 | mgp->link_changes = 0; |
0da34b6d | 843 | status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr); |
0da34b6d | 844 | myri10ge_change_pause(mgp, mgp->pause); |
2f76216f | 845 | myri10ge_set_multicast_list(mgp->dev); |
0da34b6d BG |
846 | return status; |
847 | } | |
848 | ||
849 | static inline void | |
850 | myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst, | |
851 | struct mcp_kreq_ether_recv *src) | |
852 | { | |
40f6cff5 | 853 | __be32 low; |
0da34b6d BG |
854 | |
855 | low = src->addr_low; | |
40f6cff5 | 856 | src->addr_low = htonl(DMA_32BIT_MASK); |
e67bda55 BG |
857 | myri10ge_pio_copy(dst, src, 4 * sizeof(*src)); |
858 | mb(); | |
859 | myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src)); | |
0da34b6d BG |
860 | mb(); |
861 | src->addr_low = low; | |
40f6cff5 | 862 | put_be32(low, &dst->addr_low); |
0da34b6d BG |
863 | mb(); |
864 | } | |
865 | ||
40f6cff5 | 866 | static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum) |
0da34b6d BG |
867 | { |
868 | struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data); | |
869 | ||
40f6cff5 | 870 | if ((skb->protocol == htons(ETH_P_8021Q)) && |
0da34b6d BG |
871 | (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) || |
872 | vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) { | |
873 | skb->csum = hw_csum; | |
84fa7933 | 874 | skb->ip_summed = CHECKSUM_COMPLETE; |
0da34b6d BG |
875 | } |
876 | } | |
877 | ||
dd50f336 BG |
878 | static inline void |
879 | myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va, | |
880 | struct skb_frag_struct *rx_frags, int len, int hlen) | |
881 | { | |
882 | struct skb_frag_struct *skb_frags; | |
883 | ||
884 | skb->len = skb->data_len = len; | |
885 | skb->truesize = len + sizeof(struct sk_buff); | |
886 | /* attach the page(s) */ | |
887 | ||
888 | skb_frags = skb_shinfo(skb)->frags; | |
889 | while (len > 0) { | |
890 | memcpy(skb_frags, rx_frags, sizeof(*skb_frags)); | |
891 | len -= rx_frags->size; | |
892 | skb_frags++; | |
893 | rx_frags++; | |
894 | skb_shinfo(skb)->nr_frags++; | |
895 | } | |
896 | ||
897 | /* pskb_may_pull is not available in irq context, but | |
898 | * skb_pull() (for ether_pad and eth_type_trans()) requires | |
899 | * the beginning of the packet in skb_headlen(), move it | |
900 | * manually */ | |
27d7ff46 | 901 | skb_copy_to_linear_data(skb, va, hlen); |
dd50f336 BG |
902 | skb_shinfo(skb)->frags[0].page_offset += hlen; |
903 | skb_shinfo(skb)->frags[0].size -= hlen; | |
904 | skb->data_len -= hlen; | |
905 | skb->tail += hlen; | |
906 | skb_pull(skb, MXGEFW_PAD); | |
907 | } | |
908 | ||
909 | static void | |
910 | myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx, | |
911 | int bytes, int watchdog) | |
912 | { | |
913 | struct page *page; | |
914 | int idx; | |
915 | ||
916 | if (unlikely(rx->watchdog_needed && !watchdog)) | |
917 | return; | |
918 | ||
919 | /* try to refill entire ring */ | |
920 | while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) { | |
921 | idx = rx->fill_cnt & rx->mask; | |
ae8509b1 | 922 | if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) { |
dd50f336 BG |
923 | /* we can use part of previous page */ |
924 | get_page(rx->page); | |
925 | } else { | |
926 | /* we need a new page */ | |
927 | page = | |
928 | alloc_pages(GFP_ATOMIC | __GFP_COMP, | |
929 | MYRI10GE_ALLOC_ORDER); | |
930 | if (unlikely(page == NULL)) { | |
931 | if (rx->fill_cnt - rx->cnt < 16) | |
932 | rx->watchdog_needed = 1; | |
933 | return; | |
934 | } | |
935 | rx->page = page; | |
936 | rx->page_offset = 0; | |
937 | rx->bus = pci_map_page(mgp->pdev, page, 0, | |
938 | MYRI10GE_ALLOC_SIZE, | |
939 | PCI_DMA_FROMDEVICE); | |
940 | } | |
941 | rx->info[idx].page = rx->page; | |
942 | rx->info[idx].page_offset = rx->page_offset; | |
943 | /* note that this is the address of the start of the | |
944 | * page */ | |
945 | pci_unmap_addr_set(&rx->info[idx], bus, rx->bus); | |
946 | rx->shadow[idx].addr_low = | |
947 | htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset); | |
948 | rx->shadow[idx].addr_high = | |
949 | htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus)); | |
950 | ||
951 | /* start next packet on a cacheline boundary */ | |
952 | rx->page_offset += SKB_DATA_ALIGN(bytes); | |
ae8509b1 BG |
953 | |
954 | #if MYRI10GE_ALLOC_SIZE > 4096 | |
955 | /* don't cross a 4KB boundary */ | |
956 | if ((rx->page_offset >> 12) != | |
957 | ((rx->page_offset + bytes - 1) >> 12)) | |
958 | rx->page_offset = (rx->page_offset + 4096) & ~4095; | |
959 | #endif | |
dd50f336 BG |
960 | rx->fill_cnt++; |
961 | ||
962 | /* copy 8 descriptors to the firmware at a time */ | |
963 | if ((idx & 7) == 7) { | |
964 | if (rx->wc_fifo == NULL) | |
965 | myri10ge_submit_8rx(&rx->lanai[idx - 7], | |
966 | &rx->shadow[idx - 7]); | |
967 | else { | |
968 | mb(); | |
969 | myri10ge_pio_copy(rx->wc_fifo, | |
970 | &rx->shadow[idx - 7], 64); | |
971 | } | |
972 | } | |
973 | } | |
974 | } | |
975 | ||
976 | static inline void | |
977 | myri10ge_unmap_rx_page(struct pci_dev *pdev, | |
978 | struct myri10ge_rx_buffer_state *info, int bytes) | |
979 | { | |
980 | /* unmap the recvd page if we're the only or last user of it */ | |
981 | if (bytes >= MYRI10GE_ALLOC_SIZE / 2 || | |
982 | (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) { | |
983 | pci_unmap_page(pdev, (pci_unmap_addr(info, bus) | |
984 | & ~(MYRI10GE_ALLOC_SIZE - 1)), | |
985 | MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE); | |
986 | } | |
987 | } | |
988 | ||
989 | #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a | |
990 | * page into an skb */ | |
991 | ||
992 | static inline int | |
52ea6fb3 BG |
993 | myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx, |
994 | int bytes, int len, __wsum csum) | |
dd50f336 BG |
995 | { |
996 | struct sk_buff *skb; | |
997 | struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME]; | |
998 | int i, idx, hlen, remainder; | |
999 | struct pci_dev *pdev = mgp->pdev; | |
1000 | struct net_device *dev = mgp->dev; | |
1001 | u8 *va; | |
1002 | ||
1003 | len += MXGEFW_PAD; | |
1004 | idx = rx->cnt & rx->mask; | |
1005 | va = page_address(rx->info[idx].page) + rx->info[idx].page_offset; | |
1006 | prefetch(va); | |
1007 | /* Fill skb_frag_struct(s) with data from our receive */ | |
1008 | for (i = 0, remainder = len; remainder > 0; i++) { | |
1009 | myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes); | |
1010 | rx_frags[i].page = rx->info[idx].page; | |
1011 | rx_frags[i].page_offset = rx->info[idx].page_offset; | |
1012 | if (remainder < MYRI10GE_ALLOC_SIZE) | |
1013 | rx_frags[i].size = remainder; | |
1014 | else | |
1015 | rx_frags[i].size = MYRI10GE_ALLOC_SIZE; | |
1016 | rx->cnt++; | |
1017 | idx = rx->cnt & rx->mask; | |
1018 | remainder -= MYRI10GE_ALLOC_SIZE; | |
1019 | } | |
1020 | ||
1021 | hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN; | |
1022 | ||
1023 | /* allocate an skb to attach the page(s) to. */ | |
1024 | ||
1025 | skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16); | |
1026 | if (unlikely(skb == NULL)) { | |
1027 | mgp->stats.rx_dropped++; | |
1028 | do { | |
1029 | i--; | |
1030 | put_page(rx_frags[i].page); | |
1031 | } while (i != 0); | |
1032 | return 0; | |
1033 | } | |
1034 | ||
1035 | /* Attach the pages to the skb, and trim off any padding */ | |
1036 | myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen); | |
1037 | if (skb_shinfo(skb)->frags[0].size <= 0) { | |
1038 | put_page(skb_shinfo(skb)->frags[0].page); | |
1039 | skb_shinfo(skb)->nr_frags = 0; | |
1040 | } | |
1041 | skb->protocol = eth_type_trans(skb, dev); | |
dd50f336 BG |
1042 | |
1043 | if (mgp->csum_flag) { | |
1044 | if ((skb->protocol == htons(ETH_P_IP)) || | |
1045 | (skb->protocol == htons(ETH_P_IPV6))) { | |
1046 | skb->csum = csum; | |
1047 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1048 | } else | |
1049 | myri10ge_vlan_ip_csum(skb, csum); | |
1050 | } | |
1051 | netif_receive_skb(skb); | |
1052 | dev->last_rx = jiffies; | |
1053 | return 1; | |
1054 | } | |
1055 | ||
0da34b6d BG |
1056 | static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index) |
1057 | { | |
1058 | struct pci_dev *pdev = mgp->pdev; | |
1059 | struct myri10ge_tx_buf *tx = &mgp->tx; | |
1060 | struct sk_buff *skb; | |
1061 | int idx, len; | |
1062 | int limit = 0; | |
1063 | ||
1064 | while (tx->pkt_done != mcp_index) { | |
1065 | idx = tx->done & tx->mask; | |
1066 | skb = tx->info[idx].skb; | |
1067 | ||
1068 | /* Mark as free */ | |
1069 | tx->info[idx].skb = NULL; | |
1070 | if (tx->info[idx].last) { | |
1071 | tx->pkt_done++; | |
1072 | tx->info[idx].last = 0; | |
1073 | } | |
1074 | tx->done++; | |
1075 | len = pci_unmap_len(&tx->info[idx], len); | |
1076 | pci_unmap_len_set(&tx->info[idx], len, 0); | |
1077 | if (skb) { | |
1078 | mgp->stats.tx_bytes += skb->len; | |
1079 | mgp->stats.tx_packets++; | |
1080 | dev_kfree_skb_irq(skb); | |
1081 | if (len) | |
1082 | pci_unmap_single(pdev, | |
1083 | pci_unmap_addr(&tx->info[idx], | |
1084 | bus), len, | |
1085 | PCI_DMA_TODEVICE); | |
1086 | } else { | |
1087 | if (len) | |
1088 | pci_unmap_page(pdev, | |
1089 | pci_unmap_addr(&tx->info[idx], | |
1090 | bus), len, | |
1091 | PCI_DMA_TODEVICE); | |
1092 | } | |
1093 | ||
1094 | /* limit potential for livelock by only handling | |
1095 | * 2 full tx rings per call */ | |
1096 | if (unlikely(++limit > 2 * tx->mask)) | |
1097 | break; | |
1098 | } | |
1099 | /* start the queue if we've stopped it */ | |
1100 | if (netif_queue_stopped(mgp->dev) | |
1101 | && tx->req - tx->done < (tx->mask >> 1)) { | |
1102 | mgp->wake_queue++; | |
1103 | netif_wake_queue(mgp->dev); | |
1104 | } | |
1105 | } | |
1106 | ||
1107 | static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit) | |
1108 | { | |
1109 | struct myri10ge_rx_done *rx_done = &mgp->rx_done; | |
1110 | unsigned long rx_bytes = 0; | |
1111 | unsigned long rx_packets = 0; | |
1112 | unsigned long rx_ok; | |
1113 | ||
1114 | int idx = rx_done->idx; | |
1115 | int cnt = rx_done->cnt; | |
1116 | u16 length; | |
40f6cff5 | 1117 | __wsum checksum; |
0da34b6d BG |
1118 | |
1119 | while (rx_done->entry[idx].length != 0 && *limit != 0) { | |
1120 | length = ntohs(rx_done->entry[idx].length); | |
1121 | rx_done->entry[idx].length = 0; | |
40f6cff5 | 1122 | checksum = csum_unfold(rx_done->entry[idx].checksum); |
0da34b6d | 1123 | if (length <= mgp->small_bytes) |
52ea6fb3 BG |
1124 | rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small, |
1125 | mgp->small_bytes, | |
1126 | length, checksum); | |
0da34b6d | 1127 | else |
52ea6fb3 BG |
1128 | rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big, |
1129 | mgp->big_bytes, | |
1130 | length, checksum); | |
0da34b6d BG |
1131 | rx_packets += rx_ok; |
1132 | rx_bytes += rx_ok * (unsigned long)length; | |
1133 | cnt++; | |
1134 | idx = cnt & (myri10ge_max_intr_slots - 1); | |
1135 | ||
1136 | /* limit potential for livelock by only handling a | |
1137 | * limited number of frames. */ | |
1138 | (*limit)--; | |
1139 | } | |
1140 | rx_done->idx = idx; | |
1141 | rx_done->cnt = cnt; | |
1142 | mgp->stats.rx_packets += rx_packets; | |
1143 | mgp->stats.rx_bytes += rx_bytes; | |
c7dab99b BG |
1144 | |
1145 | /* restock receive rings if needed */ | |
1146 | if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh) | |
1147 | myri10ge_alloc_rx_pages(mgp, &mgp->rx_small, | |
1148 | mgp->small_bytes + MXGEFW_PAD, 0); | |
1149 | if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh) | |
1150 | myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0); | |
1151 | ||
0da34b6d BG |
1152 | } |
1153 | ||
1154 | static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp) | |
1155 | { | |
1156 | struct mcp_irq_data *stats = mgp->fw_stats; | |
1157 | ||
1158 | if (unlikely(stats->stats_updated)) { | |
798a95db BG |
1159 | unsigned link_up = ntohl(stats->link_up); |
1160 | if (mgp->link_state != link_up) { | |
1161 | mgp->link_state = link_up; | |
1162 | ||
1163 | if (mgp->link_state == MXGEFW_LINK_UP) { | |
c58ac5ca BG |
1164 | if (netif_msg_link(mgp)) |
1165 | printk(KERN_INFO | |
1166 | "myri10ge: %s: link up\n", | |
1167 | mgp->dev->name); | |
0da34b6d | 1168 | netif_carrier_on(mgp->dev); |
c58ac5ca | 1169 | mgp->link_changes++; |
0da34b6d | 1170 | } else { |
c58ac5ca BG |
1171 | if (netif_msg_link(mgp)) |
1172 | printk(KERN_INFO | |
798a95db BG |
1173 | "myri10ge: %s: link %s\n", |
1174 | mgp->dev->name, | |
1175 | (link_up == MXGEFW_LINK_MYRINET ? | |
1176 | "mismatch (Myrinet detected)" : | |
1177 | "down")); | |
0da34b6d | 1178 | netif_carrier_off(mgp->dev); |
c58ac5ca | 1179 | mgp->link_changes++; |
0da34b6d BG |
1180 | } |
1181 | } | |
1182 | if (mgp->rdma_tags_available != | |
1183 | ntohl(mgp->fw_stats->rdma_tags_available)) { | |
1184 | mgp->rdma_tags_available = | |
1185 | ntohl(mgp->fw_stats->rdma_tags_available); | |
1186 | printk(KERN_WARNING "myri10ge: %s: RDMA timed out! " | |
1187 | "%d tags left\n", mgp->dev->name, | |
1188 | mgp->rdma_tags_available); | |
1189 | } | |
1190 | mgp->down_cnt += stats->link_down; | |
1191 | if (stats->link_down) | |
1192 | wake_up(&mgp->down_wq); | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | static int myri10ge_poll(struct net_device *netdev, int *budget) | |
1197 | { | |
1198 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1199 | struct myri10ge_rx_done *rx_done = &mgp->rx_done; | |
1200 | int limit, orig_limit, work_done; | |
1201 | ||
1202 | /* process as many rx events as NAPI will allow */ | |
1203 | limit = min(*budget, netdev->quota); | |
1204 | orig_limit = limit; | |
1205 | myri10ge_clean_rx_done(mgp, &limit); | |
1206 | work_done = orig_limit - limit; | |
1207 | *budget -= work_done; | |
1208 | netdev->quota -= work_done; | |
1209 | ||
1210 | if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) { | |
1211 | netif_rx_complete(netdev); | |
40f6cff5 | 1212 | put_be32(htonl(3), mgp->irq_claim); |
0da34b6d BG |
1213 | return 0; |
1214 | } | |
1215 | return 1; | |
1216 | } | |
1217 | ||
7d12e780 | 1218 | static irqreturn_t myri10ge_intr(int irq, void *arg) |
0da34b6d BG |
1219 | { |
1220 | struct myri10ge_priv *mgp = arg; | |
1221 | struct mcp_irq_data *stats = mgp->fw_stats; | |
1222 | struct myri10ge_tx_buf *tx = &mgp->tx; | |
1223 | u32 send_done_count; | |
1224 | int i; | |
1225 | ||
1226 | /* make sure it is our IRQ, and that the DMA has finished */ | |
1227 | if (unlikely(!stats->valid)) | |
1228 | return (IRQ_NONE); | |
1229 | ||
1230 | /* low bit indicates receives are present, so schedule | |
1231 | * napi poll handler */ | |
1232 | if (stats->valid & 1) | |
1233 | netif_rx_schedule(mgp->dev); | |
1234 | ||
1235 | if (!mgp->msi_enabled) { | |
40f6cff5 | 1236 | put_be32(0, mgp->irq_deassert); |
0da34b6d BG |
1237 | if (!myri10ge_deassert_wait) |
1238 | stats->valid = 0; | |
1239 | mb(); | |
1240 | } else | |
1241 | stats->valid = 0; | |
1242 | ||
1243 | /* Wait for IRQ line to go low, if using INTx */ | |
1244 | i = 0; | |
1245 | while (1) { | |
1246 | i++; | |
1247 | /* check for transmit completes and receives */ | |
1248 | send_done_count = ntohl(stats->send_done_count); | |
1249 | if (send_done_count != tx->pkt_done) | |
1250 | myri10ge_tx_done(mgp, (int)send_done_count); | |
1251 | if (unlikely(i > myri10ge_max_irq_loops)) { | |
1252 | printk(KERN_WARNING "myri10ge: %s: irq stuck?\n", | |
1253 | mgp->dev->name); | |
1254 | stats->valid = 0; | |
1255 | schedule_work(&mgp->watchdog_work); | |
1256 | } | |
1257 | if (likely(stats->valid == 0)) | |
1258 | break; | |
1259 | cpu_relax(); | |
1260 | barrier(); | |
1261 | } | |
1262 | ||
1263 | myri10ge_check_statblock(mgp); | |
1264 | ||
40f6cff5 | 1265 | put_be32(htonl(3), mgp->irq_claim + 1); |
0da34b6d BG |
1266 | return (IRQ_HANDLED); |
1267 | } | |
1268 | ||
1269 | static int | |
1270 | myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
1271 | { | |
1272 | cmd->autoneg = AUTONEG_DISABLE; | |
1273 | cmd->speed = SPEED_10000; | |
1274 | cmd->duplex = DUPLEX_FULL; | |
1275 | return 0; | |
1276 | } | |
1277 | ||
1278 | static void | |
1279 | myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info) | |
1280 | { | |
1281 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1282 | ||
1283 | strlcpy(info->driver, "myri10ge", sizeof(info->driver)); | |
1284 | strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version)); | |
1285 | strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version)); | |
1286 | strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info)); | |
1287 | } | |
1288 | ||
1289 | static int | |
1290 | myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal) | |
1291 | { | |
1292 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1293 | coal->rx_coalesce_usecs = mgp->intr_coal_delay; | |
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | static int | |
1298 | myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal) | |
1299 | { | |
1300 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1301 | ||
1302 | mgp->intr_coal_delay = coal->rx_coalesce_usecs; | |
40f6cff5 | 1303 | put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr); |
0da34b6d BG |
1304 | return 0; |
1305 | } | |
1306 | ||
1307 | static void | |
1308 | myri10ge_get_pauseparam(struct net_device *netdev, | |
1309 | struct ethtool_pauseparam *pause) | |
1310 | { | |
1311 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1312 | ||
1313 | pause->autoneg = 0; | |
1314 | pause->rx_pause = mgp->pause; | |
1315 | pause->tx_pause = mgp->pause; | |
1316 | } | |
1317 | ||
1318 | static int | |
1319 | myri10ge_set_pauseparam(struct net_device *netdev, | |
1320 | struct ethtool_pauseparam *pause) | |
1321 | { | |
1322 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1323 | ||
1324 | if (pause->tx_pause != mgp->pause) | |
1325 | return myri10ge_change_pause(mgp, pause->tx_pause); | |
1326 | if (pause->rx_pause != mgp->pause) | |
1327 | return myri10ge_change_pause(mgp, pause->tx_pause); | |
1328 | if (pause->autoneg != 0) | |
1329 | return -EINVAL; | |
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | static void | |
1334 | myri10ge_get_ringparam(struct net_device *netdev, | |
1335 | struct ethtool_ringparam *ring) | |
1336 | { | |
1337 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1338 | ||
1339 | ring->rx_mini_max_pending = mgp->rx_small.mask + 1; | |
1340 | ring->rx_max_pending = mgp->rx_big.mask + 1; | |
1341 | ring->rx_jumbo_max_pending = 0; | |
1342 | ring->tx_max_pending = mgp->rx_small.mask + 1; | |
1343 | ring->rx_mini_pending = ring->rx_mini_max_pending; | |
1344 | ring->rx_pending = ring->rx_max_pending; | |
1345 | ring->rx_jumbo_pending = ring->rx_jumbo_max_pending; | |
1346 | ring->tx_pending = ring->tx_max_pending; | |
1347 | } | |
1348 | ||
1349 | static u32 myri10ge_get_rx_csum(struct net_device *netdev) | |
1350 | { | |
1351 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1352 | if (mgp->csum_flag) | |
1353 | return 1; | |
1354 | else | |
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled) | |
1359 | { | |
1360 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1361 | if (csum_enabled) | |
1362 | mgp->csum_flag = MXGEFW_FLAGS_CKSUM; | |
1363 | else | |
1364 | mgp->csum_flag = 0; | |
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = { | |
1369 | "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", | |
1370 | "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", | |
1371 | "rx_length_errors", "rx_over_errors", "rx_crc_errors", | |
1372 | "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", | |
1373 | "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", | |
1374 | "tx_heartbeat_errors", "tx_window_errors", | |
1375 | /* device-specific stats */ | |
2c1a1088 | 1376 | "tx_boundary", "WC", "irq", "MSI", |
0da34b6d BG |
1377 | "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs", |
1378 | "serial_number", "tx_pkt_start", "tx_pkt_done", | |
1379 | "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt", | |
1380 | "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized", | |
c58ac5ca | 1381 | "link_changes", "link_up", "dropped_link_overflow", |
cee505db BG |
1382 | "dropped_link_error_or_filtered", |
1383 | "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32", | |
1384 | "dropped_unicast_filtered", "dropped_multicast_filtered", | |
0da34b6d BG |
1385 | "dropped_runt", "dropped_overrun", "dropped_no_small_buffer", |
1386 | "dropped_no_big_buffer" | |
1387 | }; | |
1388 | ||
1389 | #define MYRI10GE_NET_STATS_LEN 21 | |
1390 | #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN | |
1391 | ||
1392 | static void | |
1393 | myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data) | |
1394 | { | |
1395 | switch (stringset) { | |
1396 | case ETH_SS_STATS: | |
1397 | memcpy(data, *myri10ge_gstrings_stats, | |
1398 | sizeof(myri10ge_gstrings_stats)); | |
1399 | break; | |
1400 | } | |
1401 | } | |
1402 | ||
1403 | static int myri10ge_get_stats_count(struct net_device *netdev) | |
1404 | { | |
1405 | return MYRI10GE_STATS_LEN; | |
1406 | } | |
1407 | ||
1408 | static void | |
1409 | myri10ge_get_ethtool_stats(struct net_device *netdev, | |
1410 | struct ethtool_stats *stats, u64 * data) | |
1411 | { | |
1412 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1413 | int i; | |
1414 | ||
1415 | for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++) | |
1416 | data[i] = ((unsigned long *)&mgp->stats)[i]; | |
1417 | ||
2c1a1088 | 1418 | data[i++] = (unsigned int)mgp->tx.boundary; |
276e26c3 | 1419 | data[i++] = (unsigned int)mgp->wc_enabled; |
2c1a1088 BG |
1420 | data[i++] = (unsigned int)mgp->pdev->irq; |
1421 | data[i++] = (unsigned int)mgp->msi_enabled; | |
0da34b6d BG |
1422 | data[i++] = (unsigned int)mgp->read_dma; |
1423 | data[i++] = (unsigned int)mgp->write_dma; | |
1424 | data[i++] = (unsigned int)mgp->read_write_dma; | |
1425 | data[i++] = (unsigned int)mgp->serial_number; | |
1426 | data[i++] = (unsigned int)mgp->tx.pkt_start; | |
1427 | data[i++] = (unsigned int)mgp->tx.pkt_done; | |
1428 | data[i++] = (unsigned int)mgp->tx.req; | |
1429 | data[i++] = (unsigned int)mgp->tx.done; | |
1430 | data[i++] = (unsigned int)mgp->rx_small.cnt; | |
1431 | data[i++] = (unsigned int)mgp->rx_big.cnt; | |
1432 | data[i++] = (unsigned int)mgp->wake_queue; | |
1433 | data[i++] = (unsigned int)mgp->stop_queue; | |
1434 | data[i++] = (unsigned int)mgp->watchdog_resets; | |
1435 | data[i++] = (unsigned int)mgp->tx_linearized; | |
c58ac5ca | 1436 | data[i++] = (unsigned int)mgp->link_changes; |
0da34b6d BG |
1437 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up); |
1438 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow); | |
1439 | data[i++] = | |
1440 | (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered); | |
cee505db BG |
1441 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause); |
1442 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy); | |
1443 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32); | |
1444 | data[i++] = | |
1445 | (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered); | |
85a7ea1b BG |
1446 | data[i++] = |
1447 | (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered); | |
0da34b6d BG |
1448 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt); |
1449 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun); | |
1450 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer); | |
1451 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer); | |
1452 | } | |
1453 | ||
c58ac5ca BG |
1454 | static void myri10ge_set_msglevel(struct net_device *netdev, u32 value) |
1455 | { | |
1456 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1457 | mgp->msg_enable = value; | |
1458 | } | |
1459 | ||
1460 | static u32 myri10ge_get_msglevel(struct net_device *netdev) | |
1461 | { | |
1462 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1463 | return mgp->msg_enable; | |
1464 | } | |
1465 | ||
7282d491 | 1466 | static const struct ethtool_ops myri10ge_ethtool_ops = { |
0da34b6d BG |
1467 | .get_settings = myri10ge_get_settings, |
1468 | .get_drvinfo = myri10ge_get_drvinfo, | |
1469 | .get_coalesce = myri10ge_get_coalesce, | |
1470 | .set_coalesce = myri10ge_set_coalesce, | |
1471 | .get_pauseparam = myri10ge_get_pauseparam, | |
1472 | .set_pauseparam = myri10ge_set_pauseparam, | |
1473 | .get_ringparam = myri10ge_get_ringparam, | |
1474 | .get_rx_csum = myri10ge_get_rx_csum, | |
1475 | .set_rx_csum = myri10ge_set_rx_csum, | |
1476 | .get_tx_csum = ethtool_op_get_tx_csum, | |
b10c0668 | 1477 | .set_tx_csum = ethtool_op_set_tx_hw_csum, |
0da34b6d BG |
1478 | .get_sg = ethtool_op_get_sg, |
1479 | .set_sg = ethtool_op_set_sg, | |
0da34b6d BG |
1480 | .get_tso = ethtool_op_get_tso, |
1481 | .set_tso = ethtool_op_set_tso, | |
6ffdd071 | 1482 | .get_link = ethtool_op_get_link, |
0da34b6d BG |
1483 | .get_strings = myri10ge_get_strings, |
1484 | .get_stats_count = myri10ge_get_stats_count, | |
c58ac5ca BG |
1485 | .get_ethtool_stats = myri10ge_get_ethtool_stats, |
1486 | .set_msglevel = myri10ge_set_msglevel, | |
1487 | .get_msglevel = myri10ge_get_msglevel | |
0da34b6d BG |
1488 | }; |
1489 | ||
1490 | static int myri10ge_allocate_rings(struct net_device *dev) | |
1491 | { | |
1492 | struct myri10ge_priv *mgp; | |
1493 | struct myri10ge_cmd cmd; | |
1494 | int tx_ring_size, rx_ring_size; | |
1495 | int tx_ring_entries, rx_ring_entries; | |
1496 | int i, status; | |
1497 | size_t bytes; | |
1498 | ||
1499 | mgp = netdev_priv(dev); | |
1500 | ||
1501 | /* get ring sizes */ | |
1502 | ||
1503 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0); | |
1504 | tx_ring_size = cmd.data0; | |
1505 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0); | |
355c7265 BG |
1506 | if (status != 0) |
1507 | return status; | |
0da34b6d BG |
1508 | rx_ring_size = cmd.data0; |
1509 | ||
1510 | tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send); | |
1511 | rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr); | |
1512 | mgp->tx.mask = tx_ring_entries - 1; | |
1513 | mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1; | |
1514 | ||
355c7265 BG |
1515 | status = -ENOMEM; |
1516 | ||
0da34b6d BG |
1517 | /* allocate the host shadow rings */ |
1518 | ||
1519 | bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4) | |
1520 | * sizeof(*mgp->tx.req_list); | |
1521 | mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL); | |
1522 | if (mgp->tx.req_bytes == NULL) | |
1523 | goto abort_with_nothing; | |
1524 | ||
1525 | /* ensure req_list entries are aligned to 8 bytes */ | |
1526 | mgp->tx.req_list = (struct mcp_kreq_ether_send *) | |
1527 | ALIGN((unsigned long)mgp->tx.req_bytes, 8); | |
1528 | ||
1529 | bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow); | |
1530 | mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL); | |
1531 | if (mgp->rx_small.shadow == NULL) | |
1532 | goto abort_with_tx_req_bytes; | |
1533 | ||
1534 | bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow); | |
1535 | mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL); | |
1536 | if (mgp->rx_big.shadow == NULL) | |
1537 | goto abort_with_rx_small_shadow; | |
1538 | ||
1539 | /* allocate the host info rings */ | |
1540 | ||
1541 | bytes = tx_ring_entries * sizeof(*mgp->tx.info); | |
1542 | mgp->tx.info = kzalloc(bytes, GFP_KERNEL); | |
1543 | if (mgp->tx.info == NULL) | |
1544 | goto abort_with_rx_big_shadow; | |
1545 | ||
1546 | bytes = rx_ring_entries * sizeof(*mgp->rx_small.info); | |
1547 | mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL); | |
1548 | if (mgp->rx_small.info == NULL) | |
1549 | goto abort_with_tx_info; | |
1550 | ||
1551 | bytes = rx_ring_entries * sizeof(*mgp->rx_big.info); | |
1552 | mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL); | |
1553 | if (mgp->rx_big.info == NULL) | |
1554 | goto abort_with_rx_small_info; | |
1555 | ||
1556 | /* Fill the receive rings */ | |
c7dab99b BG |
1557 | mgp->rx_big.cnt = 0; |
1558 | mgp->rx_small.cnt = 0; | |
1559 | mgp->rx_big.fill_cnt = 0; | |
1560 | mgp->rx_small.fill_cnt = 0; | |
1561 | mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE; | |
1562 | mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE; | |
1563 | mgp->rx_small.watchdog_needed = 0; | |
1564 | mgp->rx_big.watchdog_needed = 0; | |
1565 | myri10ge_alloc_rx_pages(mgp, &mgp->rx_small, | |
1566 | mgp->small_bytes + MXGEFW_PAD, 0); | |
0da34b6d | 1567 | |
c7dab99b BG |
1568 | if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) { |
1569 | printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n", | |
1570 | dev->name, mgp->rx_small.fill_cnt); | |
1571 | goto abort_with_rx_small_ring; | |
0da34b6d BG |
1572 | } |
1573 | ||
c7dab99b BG |
1574 | myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0); |
1575 | if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) { | |
1576 | printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n", | |
1577 | dev->name, mgp->rx_big.fill_cnt); | |
1578 | goto abort_with_rx_big_ring; | |
0da34b6d BG |
1579 | } |
1580 | ||
1581 | return 0; | |
1582 | ||
1583 | abort_with_rx_big_ring: | |
c7dab99b BG |
1584 | for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) { |
1585 | int idx = i & mgp->rx_big.mask; | |
1586 | myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx], | |
1587 | mgp->big_bytes); | |
1588 | put_page(mgp->rx_big.info[idx].page); | |
0da34b6d BG |
1589 | } |
1590 | ||
1591 | abort_with_rx_small_ring: | |
c7dab99b BG |
1592 | for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) { |
1593 | int idx = i & mgp->rx_small.mask; | |
1594 | myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx], | |
1595 | mgp->small_bytes + MXGEFW_PAD); | |
1596 | put_page(mgp->rx_small.info[idx].page); | |
0da34b6d | 1597 | } |
c7dab99b | 1598 | |
0da34b6d BG |
1599 | kfree(mgp->rx_big.info); |
1600 | ||
1601 | abort_with_rx_small_info: | |
1602 | kfree(mgp->rx_small.info); | |
1603 | ||
1604 | abort_with_tx_info: | |
1605 | kfree(mgp->tx.info); | |
1606 | ||
1607 | abort_with_rx_big_shadow: | |
1608 | kfree(mgp->rx_big.shadow); | |
1609 | ||
1610 | abort_with_rx_small_shadow: | |
1611 | kfree(mgp->rx_small.shadow); | |
1612 | ||
1613 | abort_with_tx_req_bytes: | |
1614 | kfree(mgp->tx.req_bytes); | |
1615 | mgp->tx.req_bytes = NULL; | |
1616 | mgp->tx.req_list = NULL; | |
1617 | ||
1618 | abort_with_nothing: | |
1619 | return status; | |
1620 | } | |
1621 | ||
1622 | static void myri10ge_free_rings(struct net_device *dev) | |
1623 | { | |
1624 | struct myri10ge_priv *mgp; | |
1625 | struct sk_buff *skb; | |
1626 | struct myri10ge_tx_buf *tx; | |
1627 | int i, len, idx; | |
1628 | ||
1629 | mgp = netdev_priv(dev); | |
1630 | ||
c7dab99b BG |
1631 | for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) { |
1632 | idx = i & mgp->rx_big.mask; | |
1633 | if (i == mgp->rx_big.fill_cnt - 1) | |
1634 | mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE; | |
1635 | myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx], | |
1636 | mgp->big_bytes); | |
1637 | put_page(mgp->rx_big.info[idx].page); | |
0da34b6d BG |
1638 | } |
1639 | ||
c7dab99b BG |
1640 | for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) { |
1641 | idx = i & mgp->rx_small.mask; | |
1642 | if (i == mgp->rx_small.fill_cnt - 1) | |
1643 | mgp->rx_small.info[idx].page_offset = | |
1644 | MYRI10GE_ALLOC_SIZE; | |
1645 | myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx], | |
1646 | mgp->small_bytes + MXGEFW_PAD); | |
1647 | put_page(mgp->rx_small.info[idx].page); | |
1648 | } | |
0da34b6d BG |
1649 | tx = &mgp->tx; |
1650 | while (tx->done != tx->req) { | |
1651 | idx = tx->done & tx->mask; | |
1652 | skb = tx->info[idx].skb; | |
1653 | ||
1654 | /* Mark as free */ | |
1655 | tx->info[idx].skb = NULL; | |
1656 | tx->done++; | |
1657 | len = pci_unmap_len(&tx->info[idx], len); | |
1658 | pci_unmap_len_set(&tx->info[idx], len, 0); | |
1659 | if (skb) { | |
1660 | mgp->stats.tx_dropped++; | |
1661 | dev_kfree_skb_any(skb); | |
1662 | if (len) | |
1663 | pci_unmap_single(mgp->pdev, | |
1664 | pci_unmap_addr(&tx->info[idx], | |
1665 | bus), len, | |
1666 | PCI_DMA_TODEVICE); | |
1667 | } else { | |
1668 | if (len) | |
1669 | pci_unmap_page(mgp->pdev, | |
1670 | pci_unmap_addr(&tx->info[idx], | |
1671 | bus), len, | |
1672 | PCI_DMA_TODEVICE); | |
1673 | } | |
1674 | } | |
1675 | kfree(mgp->rx_big.info); | |
1676 | ||
1677 | kfree(mgp->rx_small.info); | |
1678 | ||
1679 | kfree(mgp->tx.info); | |
1680 | ||
1681 | kfree(mgp->rx_big.shadow); | |
1682 | ||
1683 | kfree(mgp->rx_small.shadow); | |
1684 | ||
1685 | kfree(mgp->tx.req_bytes); | |
1686 | mgp->tx.req_bytes = NULL; | |
1687 | mgp->tx.req_list = NULL; | |
1688 | } | |
1689 | ||
df30a740 BG |
1690 | static int myri10ge_request_irq(struct myri10ge_priv *mgp) |
1691 | { | |
1692 | struct pci_dev *pdev = mgp->pdev; | |
1693 | int status; | |
1694 | ||
1695 | if (myri10ge_msi) { | |
1696 | status = pci_enable_msi(pdev); | |
1697 | if (status != 0) | |
1698 | dev_err(&pdev->dev, | |
1699 | "Error %d setting up MSI; falling back to xPIC\n", | |
1700 | status); | |
1701 | else | |
1702 | mgp->msi_enabled = 1; | |
1703 | } else { | |
1704 | mgp->msi_enabled = 0; | |
1705 | } | |
1706 | status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED, | |
1707 | mgp->dev->name, mgp); | |
1708 | if (status != 0) { | |
1709 | dev_err(&pdev->dev, "failed to allocate IRQ\n"); | |
1710 | if (mgp->msi_enabled) | |
1711 | pci_disable_msi(pdev); | |
1712 | } | |
1713 | return status; | |
1714 | } | |
1715 | ||
1716 | static void myri10ge_free_irq(struct myri10ge_priv *mgp) | |
1717 | { | |
1718 | struct pci_dev *pdev = mgp->pdev; | |
1719 | ||
1720 | free_irq(pdev->irq, mgp); | |
1721 | if (mgp->msi_enabled) | |
1722 | pci_disable_msi(pdev); | |
1723 | } | |
1724 | ||
0da34b6d BG |
1725 | static int myri10ge_open(struct net_device *dev) |
1726 | { | |
1727 | struct myri10ge_priv *mgp; | |
1728 | struct myri10ge_cmd cmd; | |
1729 | int status, big_pow2; | |
1730 | ||
1731 | mgp = netdev_priv(dev); | |
1732 | ||
1733 | if (mgp->running != MYRI10GE_ETH_STOPPED) | |
1734 | return -EBUSY; | |
1735 | ||
1736 | mgp->running = MYRI10GE_ETH_STARTING; | |
1737 | status = myri10ge_reset(mgp); | |
1738 | if (status != 0) { | |
1739 | printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name); | |
df30a740 | 1740 | goto abort_with_nothing; |
0da34b6d BG |
1741 | } |
1742 | ||
df30a740 BG |
1743 | status = myri10ge_request_irq(mgp); |
1744 | if (status != 0) | |
1745 | goto abort_with_nothing; | |
1746 | ||
0da34b6d BG |
1747 | /* decide what small buffer size to use. For good TCP rx |
1748 | * performance, it is important to not receive 1514 byte | |
1749 | * frames into jumbo buffers, as it confuses the socket buffer | |
1750 | * accounting code, leading to drops and erratic performance. | |
1751 | */ | |
1752 | ||
1753 | if (dev->mtu <= ETH_DATA_LEN) | |
c7dab99b BG |
1754 | /* enough for a TCP header */ |
1755 | mgp->small_bytes = (128 > SMP_CACHE_BYTES) | |
1756 | ? (128 - MXGEFW_PAD) | |
1757 | : (SMP_CACHE_BYTES - MXGEFW_PAD); | |
0da34b6d | 1758 | else |
de3c4507 BG |
1759 | /* enough for a vlan encapsulated ETH_DATA_LEN frame */ |
1760 | mgp->small_bytes = VLAN_ETH_FRAME_LEN; | |
0da34b6d BG |
1761 | |
1762 | /* Override the small buffer size? */ | |
1763 | if (myri10ge_small_bytes > 0) | |
1764 | mgp->small_bytes = myri10ge_small_bytes; | |
1765 | ||
0da34b6d BG |
1766 | /* get the lanai pointers to the send and receive rings */ |
1767 | ||
1768 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0); | |
1769 | mgp->tx.lanai = | |
1770 | (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0); | |
1771 | ||
1772 | status |= | |
1773 | myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0); | |
1774 | mgp->rx_small.lanai = | |
1775 | (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0); | |
1776 | ||
1777 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0); | |
1778 | mgp->rx_big.lanai = | |
1779 | (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0); | |
1780 | ||
1781 | if (status != 0) { | |
1782 | printk(KERN_ERR | |
1783 | "myri10ge: %s: failed to get ring sizes or locations\n", | |
1784 | dev->name); | |
1785 | mgp->running = MYRI10GE_ETH_STOPPED; | |
df30a740 | 1786 | goto abort_with_irq; |
0da34b6d BG |
1787 | } |
1788 | ||
276e26c3 | 1789 | if (myri10ge_wcfifo && mgp->wc_enabled) { |
e700f9f4 BG |
1790 | mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4; |
1791 | mgp->rx_small.wc_fifo = | |
1792 | (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL; | |
1793 | mgp->rx_big.wc_fifo = | |
1794 | (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG; | |
0da34b6d BG |
1795 | } else { |
1796 | mgp->tx.wc_fifo = NULL; | |
1797 | mgp->rx_small.wc_fifo = NULL; | |
1798 | mgp->rx_big.wc_fifo = NULL; | |
1799 | } | |
1800 | ||
0da34b6d BG |
1801 | /* Firmware needs the big buff size as a power of 2. Lie and |
1802 | * tell him the buffer is larger, because we only use 1 | |
1803 | * buffer/pkt, and the mtu will prevent overruns. | |
1804 | */ | |
13348bee | 1805 | big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD; |
c7dab99b BG |
1806 | if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) { |
1807 | while ((big_pow2 & (big_pow2 - 1)) != 0) | |
1808 | big_pow2++; | |
13348bee | 1809 | mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD; |
c7dab99b BG |
1810 | } else { |
1811 | big_pow2 = MYRI10GE_ALLOC_SIZE; | |
1812 | mgp->big_bytes = big_pow2; | |
1813 | } | |
1814 | ||
1815 | status = myri10ge_allocate_rings(dev); | |
1816 | if (status != 0) | |
df30a740 | 1817 | goto abort_with_irq; |
0da34b6d BG |
1818 | |
1819 | /* now give firmware buffers sizes, and MTU */ | |
1820 | cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN; | |
1821 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0); | |
1822 | cmd.data0 = mgp->small_bytes; | |
1823 | status |= | |
1824 | myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0); | |
1825 | cmd.data0 = big_pow2; | |
1826 | status |= | |
1827 | myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0); | |
1828 | if (status) { | |
1829 | printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n", | |
1830 | dev->name); | |
1831 | goto abort_with_rings; | |
1832 | } | |
1833 | ||
1834 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus); | |
1835 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus); | |
85a7ea1b BG |
1836 | cmd.data2 = sizeof(struct mcp_irq_data); |
1837 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0); | |
1838 | if (status == -ENOSYS) { | |
1839 | dma_addr_t bus = mgp->fw_stats_bus; | |
1840 | bus += offsetof(struct mcp_irq_data, send_done_count); | |
1841 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus); | |
1842 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus); | |
1843 | status = myri10ge_send_cmd(mgp, | |
1844 | MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, | |
1845 | &cmd, 0); | |
1846 | /* Firmware cannot support multicast without STATS_DMA_V2 */ | |
1847 | mgp->fw_multicast_support = 0; | |
1848 | } else { | |
1849 | mgp->fw_multicast_support = 1; | |
1850 | } | |
0da34b6d BG |
1851 | if (status) { |
1852 | printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n", | |
1853 | dev->name); | |
1854 | goto abort_with_rings; | |
1855 | } | |
1856 | ||
40f6cff5 | 1857 | mgp->link_state = htonl(~0U); |
0da34b6d BG |
1858 | mgp->rdma_tags_available = 15; |
1859 | ||
1860 | netif_poll_enable(mgp->dev); /* must happen prior to any irq */ | |
1861 | ||
1862 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0); | |
1863 | if (status) { | |
1864 | printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n", | |
1865 | dev->name); | |
1866 | goto abort_with_rings; | |
1867 | } | |
1868 | ||
1869 | mgp->wake_queue = 0; | |
1870 | mgp->stop_queue = 0; | |
1871 | mgp->running = MYRI10GE_ETH_RUNNING; | |
1872 | mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ; | |
1873 | add_timer(&mgp->watchdog_timer); | |
1874 | netif_wake_queue(dev); | |
1875 | return 0; | |
1876 | ||
1877 | abort_with_rings: | |
1878 | myri10ge_free_rings(dev); | |
1879 | ||
df30a740 BG |
1880 | abort_with_irq: |
1881 | myri10ge_free_irq(mgp); | |
1882 | ||
0da34b6d BG |
1883 | abort_with_nothing: |
1884 | mgp->running = MYRI10GE_ETH_STOPPED; | |
1885 | return -ENOMEM; | |
1886 | } | |
1887 | ||
1888 | static int myri10ge_close(struct net_device *dev) | |
1889 | { | |
1890 | struct myri10ge_priv *mgp; | |
1891 | struct myri10ge_cmd cmd; | |
1892 | int status, old_down_cnt; | |
1893 | ||
1894 | mgp = netdev_priv(dev); | |
1895 | ||
1896 | if (mgp->running != MYRI10GE_ETH_RUNNING) | |
1897 | return 0; | |
1898 | ||
1899 | if (mgp->tx.req_bytes == NULL) | |
1900 | return 0; | |
1901 | ||
1902 | del_timer_sync(&mgp->watchdog_timer); | |
1903 | mgp->running = MYRI10GE_ETH_STOPPING; | |
1904 | netif_poll_disable(mgp->dev); | |
1905 | netif_carrier_off(dev); | |
1906 | netif_stop_queue(dev); | |
1907 | old_down_cnt = mgp->down_cnt; | |
1908 | mb(); | |
1909 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0); | |
1910 | if (status) | |
1911 | printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n", | |
1912 | dev->name); | |
1913 | ||
1914 | wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ); | |
1915 | if (old_down_cnt == mgp->down_cnt) | |
1916 | printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name); | |
1917 | ||
1918 | netif_tx_disable(dev); | |
df30a740 | 1919 | myri10ge_free_irq(mgp); |
0da34b6d BG |
1920 | myri10ge_free_rings(dev); |
1921 | ||
1922 | mgp->running = MYRI10GE_ETH_STOPPED; | |
1923 | return 0; | |
1924 | } | |
1925 | ||
1926 | /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy | |
1927 | * backwards one at a time and handle ring wraps */ | |
1928 | ||
1929 | static inline void | |
1930 | myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx, | |
1931 | struct mcp_kreq_ether_send *src, int cnt) | |
1932 | { | |
1933 | int idx, starting_slot; | |
1934 | starting_slot = tx->req; | |
1935 | while (cnt > 1) { | |
1936 | cnt--; | |
1937 | idx = (starting_slot + cnt) & tx->mask; | |
1938 | myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src)); | |
1939 | mb(); | |
1940 | } | |
1941 | } | |
1942 | ||
1943 | /* | |
1944 | * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy | |
1945 | * at most 32 bytes at a time, so as to avoid involving the software | |
1946 | * pio handler in the nic. We re-write the first segment's flags | |
1947 | * to mark them valid only after writing the entire chain. | |
1948 | */ | |
1949 | ||
1950 | static inline void | |
1951 | myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src, | |
1952 | int cnt) | |
1953 | { | |
1954 | int idx, i; | |
1955 | struct mcp_kreq_ether_send __iomem *dstp, *dst; | |
1956 | struct mcp_kreq_ether_send *srcp; | |
1957 | u8 last_flags; | |
1958 | ||
1959 | idx = tx->req & tx->mask; | |
1960 | ||
1961 | last_flags = src->flags; | |
1962 | src->flags = 0; | |
1963 | mb(); | |
1964 | dst = dstp = &tx->lanai[idx]; | |
1965 | srcp = src; | |
1966 | ||
1967 | if ((idx + cnt) < tx->mask) { | |
1968 | for (i = 0; i < (cnt - 1); i += 2) { | |
1969 | myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src)); | |
1970 | mb(); /* force write every 32 bytes */ | |
1971 | srcp += 2; | |
1972 | dstp += 2; | |
1973 | } | |
1974 | } else { | |
1975 | /* submit all but the first request, and ensure | |
1976 | * that it is submitted below */ | |
1977 | myri10ge_submit_req_backwards(tx, src, cnt); | |
1978 | i = 0; | |
1979 | } | |
1980 | if (i < cnt) { | |
1981 | /* submit the first request */ | |
1982 | myri10ge_pio_copy(dstp, srcp, sizeof(*src)); | |
1983 | mb(); /* barrier before setting valid flag */ | |
1984 | } | |
1985 | ||
1986 | /* re-write the last 32-bits with the valid flags */ | |
1987 | src->flags = last_flags; | |
40f6cff5 | 1988 | put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3); |
0da34b6d BG |
1989 | tx->req += cnt; |
1990 | mb(); | |
1991 | } | |
1992 | ||
1993 | static inline void | |
1994 | myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx, | |
1995 | struct mcp_kreq_ether_send *src, int cnt) | |
1996 | { | |
1997 | tx->req += cnt; | |
1998 | mb(); | |
1999 | while (cnt >= 4) { | |
2000 | myri10ge_pio_copy(tx->wc_fifo, src, 64); | |
2001 | mb(); | |
2002 | src += 4; | |
2003 | cnt -= 4; | |
2004 | } | |
2005 | if (cnt > 0) { | |
2006 | /* pad it to 64 bytes. The src is 64 bytes bigger than it | |
2007 | * needs to be so that we don't overrun it */ | |
e700f9f4 BG |
2008 | myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt), |
2009 | src, 64); | |
0da34b6d BG |
2010 | mb(); |
2011 | } | |
2012 | } | |
2013 | ||
2014 | /* | |
2015 | * Transmit a packet. We need to split the packet so that a single | |
2016 | * segment does not cross myri10ge->tx.boundary, so this makes segment | |
2017 | * counting tricky. So rather than try to count segments up front, we | |
2018 | * just give up if there are too few segments to hold a reasonably | |
2019 | * fragmented packet currently available. If we run | |
2020 | * out of segments while preparing a packet for DMA, we just linearize | |
2021 | * it and try again. | |
2022 | */ | |
2023 | ||
2024 | static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev) | |
2025 | { | |
2026 | struct myri10ge_priv *mgp = netdev_priv(dev); | |
2027 | struct mcp_kreq_ether_send *req; | |
2028 | struct myri10ge_tx_buf *tx = &mgp->tx; | |
2029 | struct skb_frag_struct *frag; | |
2030 | dma_addr_t bus; | |
40f6cff5 AV |
2031 | u32 low; |
2032 | __be32 high_swapped; | |
0da34b6d BG |
2033 | unsigned int len; |
2034 | int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments; | |
2035 | u16 pseudo_hdr_offset, cksum_offset; | |
2036 | int cum_len, seglen, boundary, rdma_count; | |
2037 | u8 flags, odd_flag; | |
2038 | ||
2039 | again: | |
2040 | req = tx->req_list; | |
2041 | avail = tx->mask - 1 - (tx->req - tx->done); | |
2042 | ||
2043 | mss = 0; | |
2044 | max_segments = MXGEFW_MAX_SEND_DESC; | |
2045 | ||
917690cd | 2046 | if (skb_is_gso(skb)) { |
7967168c | 2047 | mss = skb_shinfo(skb)->gso_size; |
917690cd | 2048 | max_segments = MYRI10GE_MAX_SEND_DESC_TSO; |
0da34b6d | 2049 | } |
0da34b6d BG |
2050 | |
2051 | if ((unlikely(avail < max_segments))) { | |
2052 | /* we are out of transmit resources */ | |
2053 | mgp->stop_queue++; | |
2054 | netif_stop_queue(dev); | |
2055 | return 1; | |
2056 | } | |
2057 | ||
2058 | /* Setup checksum offloading, if needed */ | |
2059 | cksum_offset = 0; | |
2060 | pseudo_hdr_offset = 0; | |
2061 | odd_flag = 0; | |
2062 | flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST); | |
84fa7933 | 2063 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
ea2ae17d | 2064 | cksum_offset = skb_transport_offset(skb); |
ff1dcadb | 2065 | pseudo_hdr_offset = cksum_offset + skb->csum_offset; |
0da34b6d BG |
2066 | /* If the headers are excessively large, then we must |
2067 | * fall back to a software checksum */ | |
2068 | if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) { | |
84fa7933 | 2069 | if (skb_checksum_help(skb)) |
0da34b6d BG |
2070 | goto drop; |
2071 | cksum_offset = 0; | |
2072 | pseudo_hdr_offset = 0; | |
2073 | } else { | |
0da34b6d BG |
2074 | odd_flag = MXGEFW_FLAGS_ALIGN_ODD; |
2075 | flags |= MXGEFW_FLAGS_CKSUM; | |
2076 | } | |
2077 | } | |
2078 | ||
2079 | cum_len = 0; | |
2080 | ||
0da34b6d BG |
2081 | if (mss) { /* TSO */ |
2082 | /* this removes any CKSUM flag from before */ | |
2083 | flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST); | |
2084 | ||
2085 | /* negative cum_len signifies to the | |
2086 | * send loop that we are still in the | |
2087 | * header portion of the TSO packet. | |
2088 | * TSO header must be at most 134 bytes long */ | |
ab6a5bb6 | 2089 | cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb)); |
0da34b6d BG |
2090 | |
2091 | /* for TSO, pseudo_hdr_offset holds mss. | |
2092 | * The firmware figures out where to put | |
2093 | * the checksum by parsing the header. */ | |
40f6cff5 | 2094 | pseudo_hdr_offset = mss; |
0da34b6d | 2095 | } else |
0da34b6d BG |
2096 | /* Mark small packets, and pad out tiny packets */ |
2097 | if (skb->len <= MXGEFW_SEND_SMALL_SIZE) { | |
2098 | flags |= MXGEFW_FLAGS_SMALL; | |
2099 | ||
2100 | /* pad frames to at least ETH_ZLEN bytes */ | |
2101 | if (unlikely(skb->len < ETH_ZLEN)) { | |
5b057c6b | 2102 | if (skb_padto(skb, ETH_ZLEN)) { |
0da34b6d BG |
2103 | /* The packet is gone, so we must |
2104 | * return 0 */ | |
2105 | mgp->stats.tx_dropped += 1; | |
2106 | return 0; | |
2107 | } | |
2108 | /* adjust the len to account for the zero pad | |
2109 | * so that the nic can know how long it is */ | |
2110 | skb->len = ETH_ZLEN; | |
2111 | } | |
2112 | } | |
2113 | ||
2114 | /* map the skb for DMA */ | |
2115 | len = skb->len - skb->data_len; | |
2116 | idx = tx->req & tx->mask; | |
2117 | tx->info[idx].skb = skb; | |
2118 | bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
2119 | pci_unmap_addr_set(&tx->info[idx], bus, bus); | |
2120 | pci_unmap_len_set(&tx->info[idx], len, len); | |
2121 | ||
2122 | frag_cnt = skb_shinfo(skb)->nr_frags; | |
2123 | frag_idx = 0; | |
2124 | count = 0; | |
2125 | rdma_count = 0; | |
2126 | ||
2127 | /* "rdma_count" is the number of RDMAs belonging to the | |
2128 | * current packet BEFORE the current send request. For | |
2129 | * non-TSO packets, this is equal to "count". | |
2130 | * For TSO packets, rdma_count needs to be reset | |
2131 | * to 0 after a segment cut. | |
2132 | * | |
2133 | * The rdma_count field of the send request is | |
2134 | * the number of RDMAs of the packet starting at | |
2135 | * that request. For TSO send requests with one ore more cuts | |
2136 | * in the middle, this is the number of RDMAs starting | |
2137 | * after the last cut in the request. All previous | |
2138 | * segments before the last cut implicitly have 1 RDMA. | |
2139 | * | |
2140 | * Since the number of RDMAs is not known beforehand, | |
2141 | * it must be filled-in retroactively - after each | |
2142 | * segmentation cut or at the end of the entire packet. | |
2143 | */ | |
2144 | ||
2145 | while (1) { | |
2146 | /* Break the SKB or Fragment up into pieces which | |
2147 | * do not cross mgp->tx.boundary */ | |
2148 | low = MYRI10GE_LOWPART_TO_U32(bus); | |
2149 | high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus)); | |
2150 | while (len) { | |
2151 | u8 flags_next; | |
2152 | int cum_len_next; | |
2153 | ||
2154 | if (unlikely(count == max_segments)) | |
2155 | goto abort_linearize; | |
2156 | ||
2157 | boundary = (low + tx->boundary) & ~(tx->boundary - 1); | |
2158 | seglen = boundary - low; | |
2159 | if (seglen > len) | |
2160 | seglen = len; | |
2161 | flags_next = flags & ~MXGEFW_FLAGS_FIRST; | |
2162 | cum_len_next = cum_len + seglen; | |
0da34b6d BG |
2163 | if (mss) { /* TSO */ |
2164 | (req - rdma_count)->rdma_count = rdma_count + 1; | |
2165 | ||
2166 | if (likely(cum_len >= 0)) { /* payload */ | |
2167 | int next_is_first, chop; | |
2168 | ||
2169 | chop = (cum_len_next > mss); | |
2170 | cum_len_next = cum_len_next % mss; | |
2171 | next_is_first = (cum_len_next == 0); | |
2172 | flags |= chop * MXGEFW_FLAGS_TSO_CHOP; | |
2173 | flags_next |= next_is_first * | |
2174 | MXGEFW_FLAGS_FIRST; | |
2175 | rdma_count |= -(chop | next_is_first); | |
2176 | rdma_count += chop & !next_is_first; | |
2177 | } else if (likely(cum_len_next >= 0)) { /* header ends */ | |
2178 | int small; | |
2179 | ||
2180 | rdma_count = -1; | |
2181 | cum_len_next = 0; | |
2182 | seglen = -cum_len; | |
2183 | small = (mss <= MXGEFW_SEND_SMALL_SIZE); | |
2184 | flags_next = MXGEFW_FLAGS_TSO_PLD | | |
2185 | MXGEFW_FLAGS_FIRST | | |
2186 | (small * MXGEFW_FLAGS_SMALL); | |
2187 | } | |
2188 | } | |
0da34b6d BG |
2189 | req->addr_high = high_swapped; |
2190 | req->addr_low = htonl(low); | |
40f6cff5 | 2191 | req->pseudo_hdr_offset = htons(pseudo_hdr_offset); |
0da34b6d BG |
2192 | req->pad = 0; /* complete solid 16-byte block; does this matter? */ |
2193 | req->rdma_count = 1; | |
2194 | req->length = htons(seglen); | |
2195 | req->cksum_offset = cksum_offset; | |
2196 | req->flags = flags | ((cum_len & 1) * odd_flag); | |
2197 | ||
2198 | low += seglen; | |
2199 | len -= seglen; | |
2200 | cum_len = cum_len_next; | |
2201 | flags = flags_next; | |
2202 | req++; | |
2203 | count++; | |
2204 | rdma_count++; | |
2205 | if (unlikely(cksum_offset > seglen)) | |
2206 | cksum_offset -= seglen; | |
2207 | else | |
2208 | cksum_offset = 0; | |
2209 | } | |
2210 | if (frag_idx == frag_cnt) | |
2211 | break; | |
2212 | ||
2213 | /* map next fragment for DMA */ | |
2214 | idx = (count + tx->req) & tx->mask; | |
2215 | frag = &skb_shinfo(skb)->frags[frag_idx]; | |
2216 | frag_idx++; | |
2217 | len = frag->size; | |
2218 | bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset, | |
2219 | len, PCI_DMA_TODEVICE); | |
2220 | pci_unmap_addr_set(&tx->info[idx], bus, bus); | |
2221 | pci_unmap_len_set(&tx->info[idx], len, len); | |
2222 | } | |
2223 | ||
2224 | (req - rdma_count)->rdma_count = rdma_count; | |
0da34b6d BG |
2225 | if (mss) |
2226 | do { | |
2227 | req--; | |
2228 | req->flags |= MXGEFW_FLAGS_TSO_LAST; | |
2229 | } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP | | |
2230 | MXGEFW_FLAGS_FIRST))); | |
0da34b6d BG |
2231 | idx = ((count - 1) + tx->req) & tx->mask; |
2232 | tx->info[idx].last = 1; | |
2233 | if (tx->wc_fifo == NULL) | |
2234 | myri10ge_submit_req(tx, tx->req_list, count); | |
2235 | else | |
2236 | myri10ge_submit_req_wc(tx, tx->req_list, count); | |
2237 | tx->pkt_start++; | |
2238 | if ((avail - count) < MXGEFW_MAX_SEND_DESC) { | |
2239 | mgp->stop_queue++; | |
2240 | netif_stop_queue(dev); | |
2241 | } | |
2242 | dev->trans_start = jiffies; | |
2243 | return 0; | |
2244 | ||
2245 | abort_linearize: | |
2246 | /* Free any DMA resources we've alloced and clear out the skb | |
2247 | * slot so as to not trip up assertions, and to avoid a | |
2248 | * double-free if linearizing fails */ | |
2249 | ||
2250 | last_idx = (idx + 1) & tx->mask; | |
2251 | idx = tx->req & tx->mask; | |
2252 | tx->info[idx].skb = NULL; | |
2253 | do { | |
2254 | len = pci_unmap_len(&tx->info[idx], len); | |
2255 | if (len) { | |
2256 | if (tx->info[idx].skb != NULL) | |
2257 | pci_unmap_single(mgp->pdev, | |
2258 | pci_unmap_addr(&tx->info[idx], | |
2259 | bus), len, | |
2260 | PCI_DMA_TODEVICE); | |
2261 | else | |
2262 | pci_unmap_page(mgp->pdev, | |
2263 | pci_unmap_addr(&tx->info[idx], | |
2264 | bus), len, | |
2265 | PCI_DMA_TODEVICE); | |
2266 | pci_unmap_len_set(&tx->info[idx], len, 0); | |
2267 | tx->info[idx].skb = NULL; | |
2268 | } | |
2269 | idx = (idx + 1) & tx->mask; | |
2270 | } while (idx != last_idx); | |
89114afd | 2271 | if (skb_is_gso(skb)) { |
0da34b6d BG |
2272 | printk(KERN_ERR |
2273 | "myri10ge: %s: TSO but wanted to linearize?!?!?\n", | |
2274 | mgp->dev->name); | |
2275 | goto drop; | |
2276 | } | |
2277 | ||
bec0e859 | 2278 | if (skb_linearize(skb)) |
0da34b6d BG |
2279 | goto drop; |
2280 | ||
2281 | mgp->tx_linearized++; | |
2282 | goto again; | |
2283 | ||
2284 | drop: | |
2285 | dev_kfree_skb_any(skb); | |
2286 | mgp->stats.tx_dropped += 1; | |
2287 | return 0; | |
2288 | ||
2289 | } | |
2290 | ||
2291 | static struct net_device_stats *myri10ge_get_stats(struct net_device *dev) | |
2292 | { | |
2293 | struct myri10ge_priv *mgp = netdev_priv(dev); | |
2294 | return &mgp->stats; | |
2295 | } | |
2296 | ||
2297 | static void myri10ge_set_multicast_list(struct net_device *dev) | |
2298 | { | |
85a7ea1b BG |
2299 | struct myri10ge_cmd cmd; |
2300 | struct myri10ge_priv *mgp; | |
2301 | struct dev_mc_list *mc_list; | |
6250223e | 2302 | __be32 data[2] = { 0, 0 }; |
85a7ea1b BG |
2303 | int err; |
2304 | ||
2305 | mgp = netdev_priv(dev); | |
0da34b6d BG |
2306 | /* can be called from atomic contexts, |
2307 | * pass 1 to force atomicity in myri10ge_send_cmd() */ | |
85a7ea1b BG |
2308 | myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1); |
2309 | ||
2310 | /* This firmware is known to not support multicast */ | |
2f76216f | 2311 | if (!mgp->fw_multicast_support) |
85a7ea1b BG |
2312 | return; |
2313 | ||
2314 | /* Disable multicast filtering */ | |
2315 | ||
2316 | err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1); | |
2317 | if (err != 0) { | |
2318 | printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI," | |
2319 | " error status: %d\n", dev->name, err); | |
2320 | goto abort; | |
2321 | } | |
2322 | ||
2f76216f | 2323 | if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) { |
85a7ea1b BG |
2324 | /* request to disable multicast filtering, so quit here */ |
2325 | return; | |
2326 | } | |
2327 | ||
2328 | /* Flush the filters */ | |
2329 | ||
2330 | err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, | |
2331 | &cmd, 1); | |
2332 | if (err != 0) { | |
2333 | printk(KERN_ERR | |
2334 | "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS" | |
2335 | ", error status: %d\n", dev->name, err); | |
2336 | goto abort; | |
2337 | } | |
2338 | ||
2339 | /* Walk the multicast list, and add each address */ | |
2340 | for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) { | |
40f6cff5 AV |
2341 | memcpy(data, &mc_list->dmi_addr, 6); |
2342 | cmd.data0 = ntohl(data[0]); | |
2343 | cmd.data1 = ntohl(data[1]); | |
85a7ea1b BG |
2344 | err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP, |
2345 | &cmd, 1); | |
2346 | ||
2347 | if (err != 0) { | |
2348 | printk(KERN_ERR "myri10ge: %s: Failed " | |
2349 | "MXGEFW_JOIN_MULTICAST_GROUP, error status:" | |
2350 | "%d\t", dev->name, err); | |
2351 | printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n", | |
2352 | ((unsigned char *)&mc_list->dmi_addr)[0], | |
2353 | ((unsigned char *)&mc_list->dmi_addr)[1], | |
2354 | ((unsigned char *)&mc_list->dmi_addr)[2], | |
2355 | ((unsigned char *)&mc_list->dmi_addr)[3], | |
2356 | ((unsigned char *)&mc_list->dmi_addr)[4], | |
2357 | ((unsigned char *)&mc_list->dmi_addr)[5] | |
2358 | ); | |
2359 | goto abort; | |
2360 | } | |
2361 | } | |
2362 | /* Enable multicast filtering */ | |
2363 | err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1); | |
2364 | if (err != 0) { | |
2365 | printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI," | |
2366 | "error status: %d\n", dev->name, err); | |
2367 | goto abort; | |
2368 | } | |
2369 | ||
2370 | return; | |
2371 | ||
2372 | abort: | |
2373 | return; | |
0da34b6d BG |
2374 | } |
2375 | ||
2376 | static int myri10ge_set_mac_address(struct net_device *dev, void *addr) | |
2377 | { | |
2378 | struct sockaddr *sa = addr; | |
2379 | struct myri10ge_priv *mgp = netdev_priv(dev); | |
2380 | int status; | |
2381 | ||
2382 | if (!is_valid_ether_addr(sa->sa_data)) | |
2383 | return -EADDRNOTAVAIL; | |
2384 | ||
2385 | status = myri10ge_update_mac_address(mgp, sa->sa_data); | |
2386 | if (status != 0) { | |
2387 | printk(KERN_ERR | |
2388 | "myri10ge: %s: changing mac address failed with %d\n", | |
2389 | dev->name, status); | |
2390 | return status; | |
2391 | } | |
2392 | ||
2393 | /* change the dev structure */ | |
2394 | memcpy(dev->dev_addr, sa->sa_data, 6); | |
2395 | return 0; | |
2396 | } | |
2397 | ||
2398 | static int myri10ge_change_mtu(struct net_device *dev, int new_mtu) | |
2399 | { | |
2400 | struct myri10ge_priv *mgp = netdev_priv(dev); | |
2401 | int error = 0; | |
2402 | ||
2403 | if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) { | |
2404 | printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n", | |
2405 | dev->name, new_mtu); | |
2406 | return -EINVAL; | |
2407 | } | |
2408 | printk(KERN_INFO "%s: changing mtu from %d to %d\n", | |
2409 | dev->name, dev->mtu, new_mtu); | |
2410 | if (mgp->running) { | |
2411 | /* if we change the mtu on an active device, we must | |
2412 | * reset the device so the firmware sees the change */ | |
2413 | myri10ge_close(dev); | |
2414 | dev->mtu = new_mtu; | |
2415 | myri10ge_open(dev); | |
2416 | } else | |
2417 | dev->mtu = new_mtu; | |
2418 | ||
2419 | return error; | |
2420 | } | |
2421 | ||
2422 | /* | |
2423 | * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary. | |
2424 | * Only do it if the bridge is a root port since we don't want to disturb | |
2425 | * any other device, except if forced with myri10ge_ecrc_enable > 1. | |
2426 | */ | |
2427 | ||
0da34b6d BG |
2428 | static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp) |
2429 | { | |
2430 | struct pci_dev *bridge = mgp->pdev->bus->self; | |
2431 | struct device *dev = &mgp->pdev->dev; | |
2432 | unsigned cap; | |
2433 | unsigned err_cap; | |
2434 | u16 val; | |
2435 | u8 ext_type; | |
2436 | int ret; | |
2437 | ||
2438 | if (!myri10ge_ecrc_enable || !bridge) | |
2439 | return; | |
2440 | ||
2441 | /* check that the bridge is a root port */ | |
2442 | cap = pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
2443 | pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val); | |
2444 | ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4; | |
2445 | if (ext_type != PCI_EXP_TYPE_ROOT_PORT) { | |
2446 | if (myri10ge_ecrc_enable > 1) { | |
2447 | struct pci_dev *old_bridge = bridge; | |
2448 | ||
2449 | /* Walk the hierarchy up to the root port | |
2450 | * where ECRC has to be enabled */ | |
2451 | do { | |
2452 | bridge = bridge->bus->self; | |
2453 | if (!bridge) { | |
2454 | dev_err(dev, | |
2455 | "Failed to find root port" | |
2456 | " to force ECRC\n"); | |
2457 | return; | |
2458 | } | |
2459 | cap = | |
2460 | pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
2461 | pci_read_config_word(bridge, | |
2462 | cap + PCI_CAP_FLAGS, &val); | |
2463 | ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4; | |
2464 | } while (ext_type != PCI_EXP_TYPE_ROOT_PORT); | |
2465 | ||
2466 | dev_info(dev, | |
2467 | "Forcing ECRC on non-root port %s" | |
2468 | " (enabling on root port %s)\n", | |
2469 | pci_name(old_bridge), pci_name(bridge)); | |
2470 | } else { | |
2471 | dev_err(dev, | |
2472 | "Not enabling ECRC on non-root port %s\n", | |
2473 | pci_name(bridge)); | |
2474 | return; | |
2475 | } | |
2476 | } | |
2477 | ||
2478 | cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR); | |
0da34b6d BG |
2479 | if (!cap) |
2480 | return; | |
2481 | ||
2482 | ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap); | |
2483 | if (ret) { | |
2484 | dev_err(dev, "failed reading ext-conf-space of %s\n", | |
2485 | pci_name(bridge)); | |
2486 | dev_err(dev, "\t pci=nommconf in use? " | |
2487 | "or buggy/incomplete/absent ACPI MCFG attr?\n"); | |
2488 | return; | |
2489 | } | |
2490 | if (!(err_cap & PCI_ERR_CAP_ECRC_GENC)) | |
2491 | return; | |
2492 | ||
2493 | err_cap |= PCI_ERR_CAP_ECRC_GENE; | |
2494 | pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap); | |
2495 | dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge)); | |
0da34b6d BG |
2496 | } |
2497 | ||
2498 | /* | |
2499 | * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput | |
2500 | * when the PCI-E Completion packets are aligned on an 8-byte | |
2501 | * boundary. Some PCI-E chip sets always align Completion packets; on | |
2502 | * the ones that do not, the alignment can be enforced by enabling | |
2503 | * ECRC generation (if supported). | |
2504 | * | |
2505 | * When PCI-E Completion packets are not aligned, it is actually more | |
2506 | * efficient to limit Read-DMA transactions to 2KB, rather than 4KB. | |
2507 | * | |
2508 | * If the driver can neither enable ECRC nor verify that it has | |
2509 | * already been enabled, then it must use a firmware image which works | |
2510 | * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it | |
2511 | * should also ensure that it never gives the device a Read-DMA which is | |
2512 | * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is | |
2513 | * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat) | |
2514 | * firmware image, and set tx.boundary to 4KB. | |
2515 | */ | |
2516 | ||
5443e9ea | 2517 | static void myri10ge_firmware_probe(struct myri10ge_priv *mgp) |
0da34b6d | 2518 | { |
5443e9ea BG |
2519 | struct pci_dev *pdev = mgp->pdev; |
2520 | struct device *dev = &pdev->dev; | |
2521 | int cap, status; | |
2522 | u16 val; | |
0da34b6d | 2523 | |
5443e9ea BG |
2524 | mgp->tx.boundary = 4096; |
2525 | /* | |
2526 | * Verify the max read request size was set to 4KB | |
2527 | * before trying the test with 4KB. | |
2528 | */ | |
2529 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
2530 | if (cap < 64) { | |
2531 | dev_err(dev, "Bad PCI_CAP_ID_EXP location %d\n", cap); | |
2532 | goto abort; | |
2533 | } | |
2534 | status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val); | |
2535 | if (status != 0) { | |
2536 | dev_err(dev, "Couldn't read max read req size: %d\n", status); | |
2537 | goto abort; | |
2538 | } | |
2539 | if ((val & (5 << 12)) != (5 << 12)) { | |
2540 | dev_warn(dev, "Max Read Request size != 4096 (0x%x)\n", val); | |
2541 | mgp->tx.boundary = 2048; | |
2542 | } | |
2543 | /* | |
2544 | * load the optimized firmware (which assumes aligned PCIe | |
2545 | * completions) in order to see if it works on this host. | |
2546 | */ | |
2547 | mgp->fw_name = myri10ge_fw_aligned; | |
2548 | status = myri10ge_load_firmware(mgp); | |
2549 | if (status != 0) { | |
2550 | goto abort; | |
2551 | } | |
2552 | ||
2553 | /* | |
2554 | * Enable ECRC if possible | |
2555 | */ | |
2556 | myri10ge_enable_ecrc(mgp); | |
2557 | ||
2558 | /* | |
2559 | * Run a DMA test which watches for unaligned completions and | |
2560 | * aborts on the first one seen. | |
2561 | */ | |
2562 | ||
2563 | status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST); | |
2564 | if (status == 0) | |
2565 | return; /* keep the aligned firmware */ | |
2566 | ||
2567 | if (status != -E2BIG) | |
2568 | dev_warn(dev, "DMA test failed: %d\n", status); | |
2569 | if (status == -ENOSYS) | |
2570 | dev_warn(dev, "Falling back to ethp! " | |
2571 | "Please install up to date fw\n"); | |
2572 | abort: | |
2573 | /* fall back to using the unaligned firmware */ | |
0da34b6d BG |
2574 | mgp->tx.boundary = 2048; |
2575 | mgp->fw_name = myri10ge_fw_unaligned; | |
2576 | ||
5443e9ea BG |
2577 | } |
2578 | ||
2579 | static void myri10ge_select_firmware(struct myri10ge_priv *mgp) | |
2580 | { | |
0da34b6d | 2581 | if (myri10ge_force_firmware == 0) { |
ce7f9368 BG |
2582 | int link_width, exp_cap; |
2583 | u16 lnk; | |
2584 | ||
2585 | exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP); | |
2586 | pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk); | |
2587 | link_width = (lnk >> 4) & 0x3f; | |
2588 | ||
ce7f9368 BG |
2589 | /* Check to see if Link is less than 8 or if the |
2590 | * upstream bridge is known to provide aligned | |
2591 | * completions */ | |
2592 | if (link_width < 8) { | |
2593 | dev_info(&mgp->pdev->dev, "PCIE x%d Link\n", | |
2594 | link_width); | |
2595 | mgp->tx.boundary = 4096; | |
2596 | mgp->fw_name = myri10ge_fw_aligned; | |
5443e9ea BG |
2597 | } else { |
2598 | myri10ge_firmware_probe(mgp); | |
0da34b6d BG |
2599 | } |
2600 | } else { | |
2601 | if (myri10ge_force_firmware == 1) { | |
2602 | dev_info(&mgp->pdev->dev, | |
2603 | "Assuming aligned completions (forced)\n"); | |
2604 | mgp->tx.boundary = 4096; | |
2605 | mgp->fw_name = myri10ge_fw_aligned; | |
2606 | } else { | |
2607 | dev_info(&mgp->pdev->dev, | |
2608 | "Assuming unaligned completions (forced)\n"); | |
2609 | mgp->tx.boundary = 2048; | |
2610 | mgp->fw_name = myri10ge_fw_unaligned; | |
2611 | } | |
2612 | } | |
2613 | if (myri10ge_fw_name != NULL) { | |
2614 | dev_info(&mgp->pdev->dev, "overriding firmware to %s\n", | |
2615 | myri10ge_fw_name); | |
2616 | mgp->fw_name = myri10ge_fw_name; | |
2617 | } | |
2618 | } | |
2619 | ||
0da34b6d BG |
2620 | #ifdef CONFIG_PM |
2621 | ||
2622 | static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state) | |
2623 | { | |
2624 | struct myri10ge_priv *mgp; | |
2625 | struct net_device *netdev; | |
2626 | ||
2627 | mgp = pci_get_drvdata(pdev); | |
2628 | if (mgp == NULL) | |
2629 | return -EINVAL; | |
2630 | netdev = mgp->dev; | |
2631 | ||
2632 | netif_device_detach(netdev); | |
2633 | if (netif_running(netdev)) { | |
2634 | printk(KERN_INFO "myri10ge: closing %s\n", netdev->name); | |
2635 | rtnl_lock(); | |
2636 | myri10ge_close(netdev); | |
2637 | rtnl_unlock(); | |
2638 | } | |
2639 | myri10ge_dummy_rdma(mgp, 0); | |
83f6e152 | 2640 | pci_save_state(pdev); |
0da34b6d | 2641 | pci_disable_device(pdev); |
1a63e846 BG |
2642 | |
2643 | return pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
0da34b6d BG |
2644 | } |
2645 | ||
2646 | static int myri10ge_resume(struct pci_dev *pdev) | |
2647 | { | |
2648 | struct myri10ge_priv *mgp; | |
2649 | struct net_device *netdev; | |
2650 | int status; | |
2651 | u16 vendor; | |
2652 | ||
2653 | mgp = pci_get_drvdata(pdev); | |
2654 | if (mgp == NULL) | |
2655 | return -EINVAL; | |
2656 | netdev = mgp->dev; | |
2657 | pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */ | |
2658 | msleep(5); /* give card time to respond */ | |
2659 | pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor); | |
2660 | if (vendor == 0xffff) { | |
2661 | printk(KERN_ERR "myri10ge: %s: device disappeared!\n", | |
2662 | mgp->dev->name); | |
2663 | return -EIO; | |
2664 | } | |
83f6e152 | 2665 | |
1a63e846 BG |
2666 | status = pci_restore_state(pdev); |
2667 | if (status) | |
2668 | return status; | |
4c2248cc BG |
2669 | |
2670 | status = pci_enable_device(pdev); | |
1a63e846 | 2671 | if (status) { |
4c2248cc | 2672 | dev_err(&pdev->dev, "failed to enable device\n"); |
1a63e846 | 2673 | return status; |
4c2248cc BG |
2674 | } |
2675 | ||
0da34b6d BG |
2676 | pci_set_master(pdev); |
2677 | ||
0da34b6d | 2678 | myri10ge_reset(mgp); |
013b68bf | 2679 | myri10ge_dummy_rdma(mgp, 1); |
0da34b6d BG |
2680 | |
2681 | /* Save configuration space to be restored if the | |
2682 | * nic resets due to a parity error */ | |
83f6e152 | 2683 | pci_save_state(pdev); |
0da34b6d BG |
2684 | |
2685 | if (netif_running(netdev)) { | |
2686 | rtnl_lock(); | |
df30a740 | 2687 | status = myri10ge_open(netdev); |
0da34b6d | 2688 | rtnl_unlock(); |
df30a740 BG |
2689 | if (status != 0) |
2690 | goto abort_with_enabled; | |
2691 | ||
0da34b6d BG |
2692 | } |
2693 | netif_device_attach(netdev); | |
2694 | ||
2695 | return 0; | |
2696 | ||
4c2248cc BG |
2697 | abort_with_enabled: |
2698 | pci_disable_device(pdev); | |
0da34b6d BG |
2699 | return -EIO; |
2700 | ||
2701 | } | |
2702 | ||
2703 | #endif /* CONFIG_PM */ | |
2704 | ||
2705 | static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp) | |
2706 | { | |
2707 | struct pci_dev *pdev = mgp->pdev; | |
2708 | int vs = mgp->vendor_specific_offset; | |
2709 | u32 reboot; | |
2710 | ||
2711 | /*enter read32 mode */ | |
2712 | pci_write_config_byte(pdev, vs + 0x10, 0x3); | |
2713 | ||
2714 | /*read REBOOT_STATUS (0xfffffff0) */ | |
2715 | pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0); | |
2716 | pci_read_config_dword(pdev, vs + 0x14, &reboot); | |
2717 | return reboot; | |
2718 | } | |
2719 | ||
2720 | /* | |
2721 | * This watchdog is used to check whether the board has suffered | |
2722 | * from a parity error and needs to be recovered. | |
2723 | */ | |
c4028958 | 2724 | static void myri10ge_watchdog(struct work_struct *work) |
0da34b6d | 2725 | { |
c4028958 | 2726 | struct myri10ge_priv *mgp = |
6250223e | 2727 | container_of(work, struct myri10ge_priv, watchdog_work); |
0da34b6d BG |
2728 | u32 reboot; |
2729 | int status; | |
2730 | u16 cmd, vendor; | |
2731 | ||
2732 | mgp->watchdog_resets++; | |
2733 | pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd); | |
2734 | if ((cmd & PCI_COMMAND_MASTER) == 0) { | |
2735 | /* Bus master DMA disabled? Check to see | |
2736 | * if the card rebooted due to a parity error | |
2737 | * For now, just report it */ | |
2738 | reboot = myri10ge_read_reboot(mgp); | |
2739 | printk(KERN_ERR | |
f181137f BG |
2740 | "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n", |
2741 | mgp->dev->name, reboot, | |
2742 | myri10ge_reset_recover ? " " : " not"); | |
2743 | if (myri10ge_reset_recover == 0) | |
2744 | return; | |
2745 | ||
2746 | myri10ge_reset_recover--; | |
2747 | ||
0da34b6d BG |
2748 | /* |
2749 | * A rebooted nic will come back with config space as | |
2750 | * it was after power was applied to PCIe bus. | |
2751 | * Attempt to restore config space which was saved | |
2752 | * when the driver was loaded, or the last time the | |
2753 | * nic was resumed from power saving mode. | |
2754 | */ | |
83f6e152 | 2755 | pci_restore_state(mgp->pdev); |
7adda30c BG |
2756 | |
2757 | /* save state again for accounting reasons */ | |
83f6e152 | 2758 | pci_save_state(mgp->pdev); |
7adda30c | 2759 | |
0da34b6d BG |
2760 | } else { |
2761 | /* if we get back -1's from our slot, perhaps somebody | |
2762 | * powered off our card. Don't try to reset it in | |
2763 | * this case */ | |
2764 | if (cmd == 0xffff) { | |
2765 | pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor); | |
2766 | if (vendor == 0xffff) { | |
2767 | printk(KERN_ERR | |
2768 | "myri10ge: %s: device disappeared!\n", | |
2769 | mgp->dev->name); | |
2770 | return; | |
2771 | } | |
2772 | } | |
2773 | /* Perhaps it is a software error. Try to reset */ | |
2774 | ||
2775 | printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n", | |
2776 | mgp->dev->name); | |
2777 | printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n", | |
2778 | mgp->dev->name, mgp->tx.req, mgp->tx.done, | |
2779 | mgp->tx.pkt_start, mgp->tx.pkt_done, | |
2780 | (int)ntohl(mgp->fw_stats->send_done_count)); | |
2781 | msleep(2000); | |
2782 | printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n", | |
2783 | mgp->dev->name, mgp->tx.req, mgp->tx.done, | |
2784 | mgp->tx.pkt_start, mgp->tx.pkt_done, | |
2785 | (int)ntohl(mgp->fw_stats->send_done_count)); | |
2786 | } | |
2787 | rtnl_lock(); | |
2788 | myri10ge_close(mgp->dev); | |
2789 | status = myri10ge_load_firmware(mgp); | |
2790 | if (status != 0) | |
2791 | printk(KERN_ERR "myri10ge: %s: failed to load firmware\n", | |
2792 | mgp->dev->name); | |
2793 | else | |
2794 | myri10ge_open(mgp->dev); | |
2795 | rtnl_unlock(); | |
2796 | } | |
2797 | ||
2798 | /* | |
2799 | * We use our own timer routine rather than relying upon | |
2800 | * netdev->tx_timeout because we have a very large hardware transmit | |
2801 | * queue. Due to the large queue, the netdev->tx_timeout function | |
2802 | * cannot detect a NIC with a parity error in a timely fashion if the | |
2803 | * NIC is lightly loaded. | |
2804 | */ | |
2805 | static void myri10ge_watchdog_timer(unsigned long arg) | |
2806 | { | |
2807 | struct myri10ge_priv *mgp; | |
2808 | ||
2809 | mgp = (struct myri10ge_priv *)arg; | |
c7dab99b BG |
2810 | |
2811 | if (mgp->rx_small.watchdog_needed) { | |
2812 | myri10ge_alloc_rx_pages(mgp, &mgp->rx_small, | |
2813 | mgp->small_bytes + MXGEFW_PAD, 1); | |
2814 | if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >= | |
2815 | myri10ge_fill_thresh) | |
2816 | mgp->rx_small.watchdog_needed = 0; | |
2817 | } | |
2818 | if (mgp->rx_big.watchdog_needed) { | |
2819 | myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1); | |
2820 | if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >= | |
2821 | myri10ge_fill_thresh) | |
2822 | mgp->rx_big.watchdog_needed = 0; | |
2823 | } | |
2824 | ||
0da34b6d | 2825 | if (mgp->tx.req != mgp->tx.done && |
c54772e7 BG |
2826 | mgp->tx.done == mgp->watchdog_tx_done && |
2827 | mgp->watchdog_tx_req != mgp->watchdog_tx_done) | |
0da34b6d BG |
2828 | /* nic seems like it might be stuck.. */ |
2829 | schedule_work(&mgp->watchdog_work); | |
2830 | else | |
2831 | /* rearm timer */ | |
2832 | mod_timer(&mgp->watchdog_timer, | |
2833 | jiffies + myri10ge_watchdog_timeout * HZ); | |
2834 | ||
2835 | mgp->watchdog_tx_done = mgp->tx.done; | |
c54772e7 | 2836 | mgp->watchdog_tx_req = mgp->tx.req; |
0da34b6d BG |
2837 | } |
2838 | ||
2839 | static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
2840 | { | |
2841 | struct net_device *netdev; | |
2842 | struct myri10ge_priv *mgp; | |
2843 | struct device *dev = &pdev->dev; | |
2844 | size_t bytes; | |
2845 | int i; | |
2846 | int status = -ENXIO; | |
2847 | int cap; | |
2848 | int dac_enabled; | |
2849 | u16 val; | |
2850 | ||
2851 | netdev = alloc_etherdev(sizeof(*mgp)); | |
2852 | if (netdev == NULL) { | |
2853 | dev_err(dev, "Could not allocate ethernet device\n"); | |
2854 | return -ENOMEM; | |
2855 | } | |
2856 | ||
2857 | mgp = netdev_priv(netdev); | |
2858 | memset(mgp, 0, sizeof(*mgp)); | |
2859 | mgp->dev = netdev; | |
2860 | mgp->pdev = pdev; | |
2861 | mgp->csum_flag = MXGEFW_FLAGS_CKSUM; | |
2862 | mgp->pause = myri10ge_flow_control; | |
2863 | mgp->intr_coal_delay = myri10ge_intr_coal_delay; | |
c58ac5ca | 2864 | mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT); |
0da34b6d BG |
2865 | init_waitqueue_head(&mgp->down_wq); |
2866 | ||
2867 | if (pci_enable_device(pdev)) { | |
2868 | dev_err(&pdev->dev, "pci_enable_device call failed\n"); | |
2869 | status = -ENODEV; | |
2870 | goto abort_with_netdev; | |
2871 | } | |
0da34b6d BG |
2872 | |
2873 | /* Find the vendor-specific cap so we can check | |
2874 | * the reboot register later on */ | |
2875 | mgp->vendor_specific_offset | |
2876 | = pci_find_capability(pdev, PCI_CAP_ID_VNDR); | |
2877 | ||
2878 | /* Set our max read request to 4KB */ | |
2879 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
2880 | if (cap < 64) { | |
2881 | dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap); | |
2882 | goto abort_with_netdev; | |
2883 | } | |
2884 | status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val); | |
2885 | if (status != 0) { | |
2886 | dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n", | |
2887 | status); | |
2888 | goto abort_with_netdev; | |
2889 | } | |
2890 | val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12); | |
2891 | status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val); | |
2892 | if (status != 0) { | |
2893 | dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n", | |
2894 | status); | |
2895 | goto abort_with_netdev; | |
2896 | } | |
2897 | ||
2898 | pci_set_master(pdev); | |
2899 | dac_enabled = 1; | |
2900 | status = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
2901 | if (status != 0) { | |
2902 | dac_enabled = 0; | |
2903 | dev_err(&pdev->dev, | |
2904 | "64-bit pci address mask was refused, trying 32-bit"); | |
2905 | status = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2906 | } | |
2907 | if (status != 0) { | |
2908 | dev_err(&pdev->dev, "Error %d setting DMA mask\n", status); | |
2909 | goto abort_with_netdev; | |
2910 | } | |
b10c0668 BG |
2911 | mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd), |
2912 | &mgp->cmd_bus, GFP_KERNEL); | |
0da34b6d BG |
2913 | if (mgp->cmd == NULL) |
2914 | goto abort_with_netdev; | |
2915 | ||
b10c0668 BG |
2916 | mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats), |
2917 | &mgp->fw_stats_bus, GFP_KERNEL); | |
0da34b6d BG |
2918 | if (mgp->fw_stats == NULL) |
2919 | goto abort_with_cmd; | |
2920 | ||
2921 | mgp->board_span = pci_resource_len(pdev, 0); | |
2922 | mgp->iomem_base = pci_resource_start(pdev, 0); | |
2923 | mgp->mtrr = -1; | |
276e26c3 | 2924 | mgp->wc_enabled = 0; |
0da34b6d BG |
2925 | #ifdef CONFIG_MTRR |
2926 | mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span, | |
2927 | MTRR_TYPE_WRCOMB, 1); | |
276e26c3 BG |
2928 | if (mgp->mtrr >= 0) |
2929 | mgp->wc_enabled = 1; | |
0da34b6d BG |
2930 | #endif |
2931 | /* Hack. need to get rid of these magic numbers */ | |
2932 | mgp->sram_size = | |
2933 | 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100; | |
2934 | if (mgp->sram_size > mgp->board_span) { | |
2935 | dev_err(&pdev->dev, "board span %ld bytes too small\n", | |
2936 | mgp->board_span); | |
2937 | goto abort_with_wc; | |
2938 | } | |
2939 | mgp->sram = ioremap(mgp->iomem_base, mgp->board_span); | |
2940 | if (mgp->sram == NULL) { | |
2941 | dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n", | |
2942 | mgp->board_span, mgp->iomem_base); | |
2943 | status = -ENXIO; | |
2944 | goto abort_with_wc; | |
2945 | } | |
2946 | memcpy_fromio(mgp->eeprom_strings, | |
2947 | mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE, | |
2948 | MYRI10GE_EEPROM_STRINGS_SIZE); | |
2949 | memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2); | |
2950 | status = myri10ge_read_mac_addr(mgp); | |
2951 | if (status) | |
2952 | goto abort_with_ioremap; | |
2953 | ||
2954 | for (i = 0; i < ETH_ALEN; i++) | |
2955 | netdev->dev_addr[i] = mgp->mac_addr[i]; | |
2956 | ||
2957 | /* allocate rx done ring */ | |
2958 | bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry); | |
b10c0668 BG |
2959 | mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes, |
2960 | &mgp->rx_done.bus, GFP_KERNEL); | |
0da34b6d BG |
2961 | if (mgp->rx_done.entry == NULL) |
2962 | goto abort_with_ioremap; | |
2963 | memset(mgp->rx_done.entry, 0, bytes); | |
2964 | ||
5443e9ea BG |
2965 | myri10ge_select_firmware(mgp); |
2966 | ||
0da34b6d BG |
2967 | status = myri10ge_load_firmware(mgp); |
2968 | if (status != 0) { | |
2969 | dev_err(&pdev->dev, "failed to load firmware\n"); | |
2970 | goto abort_with_rx_done; | |
2971 | } | |
2972 | ||
2973 | status = myri10ge_reset(mgp); | |
2974 | if (status != 0) { | |
2975 | dev_err(&pdev->dev, "failed reset\n"); | |
2976 | goto abort_with_firmware; | |
2977 | } | |
2978 | ||
0da34b6d BG |
2979 | pci_set_drvdata(pdev, mgp); |
2980 | if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU) | |
2981 | myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN; | |
2982 | if ((myri10ge_initial_mtu + ETH_HLEN) < 68) | |
2983 | myri10ge_initial_mtu = 68; | |
2984 | netdev->mtu = myri10ge_initial_mtu; | |
2985 | netdev->open = myri10ge_open; | |
2986 | netdev->stop = myri10ge_close; | |
2987 | netdev->hard_start_xmit = myri10ge_xmit; | |
2988 | netdev->get_stats = myri10ge_get_stats; | |
2989 | netdev->base_addr = mgp->iomem_base; | |
0da34b6d BG |
2990 | netdev->change_mtu = myri10ge_change_mtu; |
2991 | netdev->set_multicast_list = myri10ge_set_multicast_list; | |
2992 | netdev->set_mac_address = myri10ge_set_mac_address; | |
2993 | netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO; | |
2994 | if (dac_enabled) | |
2995 | netdev->features |= NETIF_F_HIGHDMA; | |
2996 | netdev->poll = myri10ge_poll; | |
2997 | netdev->weight = myri10ge_napi_weight; | |
2998 | ||
21d05db1 BG |
2999 | /* make sure we can get an irq, and that MSI can be |
3000 | * setup (if available). Also ensure netdev->irq | |
3001 | * is set to correct value if MSI is enabled */ | |
3002 | status = myri10ge_request_irq(mgp); | |
3003 | if (status != 0) | |
3004 | goto abort_with_firmware; | |
3005 | netdev->irq = pdev->irq; | |
3006 | myri10ge_free_irq(mgp); | |
3007 | ||
0da34b6d BG |
3008 | /* Save configuration space to be restored if the |
3009 | * nic resets due to a parity error */ | |
83f6e152 | 3010 | pci_save_state(pdev); |
0da34b6d BG |
3011 | |
3012 | /* Setup the watchdog timer */ | |
3013 | setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer, | |
3014 | (unsigned long)mgp); | |
3015 | ||
3016 | SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops); | |
c4028958 | 3017 | INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog); |
0da34b6d BG |
3018 | status = register_netdev(netdev); |
3019 | if (status != 0) { | |
3020 | dev_err(&pdev->dev, "register_netdev failed: %d\n", status); | |
7adda30c | 3021 | goto abort_with_state; |
0da34b6d | 3022 | } |
21d05db1 BG |
3023 | dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n", |
3024 | (mgp->msi_enabled ? "MSI" : "xPIC"), | |
3025 | netdev->irq, mgp->tx.boundary, mgp->fw_name, | |
276e26c3 | 3026 | (mgp->wc_enabled ? "Enabled" : "Disabled")); |
0da34b6d BG |
3027 | |
3028 | return 0; | |
3029 | ||
7adda30c | 3030 | abort_with_state: |
83f6e152 | 3031 | pci_restore_state(pdev); |
0da34b6d BG |
3032 | |
3033 | abort_with_firmware: | |
3034 | myri10ge_dummy_rdma(mgp, 0); | |
3035 | ||
3036 | abort_with_rx_done: | |
3037 | bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry); | |
b10c0668 BG |
3038 | dma_free_coherent(&pdev->dev, bytes, |
3039 | mgp->rx_done.entry, mgp->rx_done.bus); | |
0da34b6d BG |
3040 | |
3041 | abort_with_ioremap: | |
3042 | iounmap(mgp->sram); | |
3043 | ||
3044 | abort_with_wc: | |
3045 | #ifdef CONFIG_MTRR | |
3046 | if (mgp->mtrr >= 0) | |
3047 | mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span); | |
3048 | #endif | |
b10c0668 BG |
3049 | dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats), |
3050 | mgp->fw_stats, mgp->fw_stats_bus); | |
0da34b6d BG |
3051 | |
3052 | abort_with_cmd: | |
b10c0668 BG |
3053 | dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd), |
3054 | mgp->cmd, mgp->cmd_bus); | |
0da34b6d BG |
3055 | |
3056 | abort_with_netdev: | |
3057 | ||
3058 | free_netdev(netdev); | |
3059 | return status; | |
3060 | } | |
3061 | ||
3062 | /* | |
3063 | * myri10ge_remove | |
3064 | * | |
3065 | * Does what is necessary to shutdown one Myrinet device. Called | |
3066 | * once for each Myrinet card by the kernel when a module is | |
3067 | * unloaded. | |
3068 | */ | |
3069 | static void myri10ge_remove(struct pci_dev *pdev) | |
3070 | { | |
3071 | struct myri10ge_priv *mgp; | |
3072 | struct net_device *netdev; | |
3073 | size_t bytes; | |
3074 | ||
3075 | mgp = pci_get_drvdata(pdev); | |
3076 | if (mgp == NULL) | |
3077 | return; | |
3078 | ||
3079 | flush_scheduled_work(); | |
3080 | netdev = mgp->dev; | |
3081 | unregister_netdev(netdev); | |
0da34b6d BG |
3082 | |
3083 | myri10ge_dummy_rdma(mgp, 0); | |
3084 | ||
7adda30c | 3085 | /* avoid a memory leak */ |
83f6e152 | 3086 | pci_restore_state(pdev); |
7adda30c | 3087 | |
0da34b6d | 3088 | bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry); |
b10c0668 BG |
3089 | dma_free_coherent(&pdev->dev, bytes, |
3090 | mgp->rx_done.entry, mgp->rx_done.bus); | |
0da34b6d BG |
3091 | |
3092 | iounmap(mgp->sram); | |
3093 | ||
3094 | #ifdef CONFIG_MTRR | |
3095 | if (mgp->mtrr >= 0) | |
3096 | mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span); | |
3097 | #endif | |
b10c0668 BG |
3098 | dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats), |
3099 | mgp->fw_stats, mgp->fw_stats_bus); | |
0da34b6d | 3100 | |
b10c0668 BG |
3101 | dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd), |
3102 | mgp->cmd, mgp->cmd_bus); | |
0da34b6d BG |
3103 | |
3104 | free_netdev(netdev); | |
3105 | pci_set_drvdata(pdev, NULL); | |
3106 | } | |
3107 | ||
b10c0668 | 3108 | #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008 |
0da34b6d BG |
3109 | |
3110 | static struct pci_device_id myri10ge_pci_tbl[] = { | |
b10c0668 | 3111 | {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)}, |
0da34b6d BG |
3112 | {0}, |
3113 | }; | |
3114 | ||
3115 | static struct pci_driver myri10ge_driver = { | |
3116 | .name = "myri10ge", | |
3117 | .probe = myri10ge_probe, | |
3118 | .remove = myri10ge_remove, | |
3119 | .id_table = myri10ge_pci_tbl, | |
3120 | #ifdef CONFIG_PM | |
3121 | .suspend = myri10ge_suspend, | |
3122 | .resume = myri10ge_resume, | |
3123 | #endif | |
3124 | }; | |
3125 | ||
3126 | static __init int myri10ge_init_module(void) | |
3127 | { | |
3128 | printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name, | |
3129 | MYRI10GE_VERSION_STR); | |
3130 | return pci_register_driver(&myri10ge_driver); | |
3131 | } | |
3132 | ||
3133 | module_init(myri10ge_init_module); | |
3134 | ||
3135 | static __exit void myri10ge_cleanup_module(void) | |
3136 | { | |
3137 | pci_unregister_driver(&myri10ge_driver); | |
3138 | } | |
3139 | ||
3140 | module_exit(myri10ge_cleanup_module); |