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[mirror_ubuntu-bionic-kernel.git] / drivers / net / myri10ge / myri10ge.c
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0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
981813d8 52#include <linux/dca.h>
0da34b6d
BG		 53#include <linux/ip.h>
54#include <linux/inet.h>
55#include <linux/in.h>
56#include <linux/ethtool.h>
57#include <linux/firmware.h>
58#include <linux/delay.h>
0da34b6d
BG		 59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
0623807a 78#define MYRI10GE_VERSION_STR "1.4.3-1.358"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
0da34b6d 105struct myri10ge_rx_buffer_state {
dd50f336
BG		 106 struct page *page;
107 int page_offset;
0da34b6d
BG		 108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110};
111
112struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117};
118
119struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123};
124
125struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 127 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
128 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 129 struct page *page;
130 dma_addr_t bus;
131 int page_offset;
0da34b6d 132 int cnt;
dd50f336 133 int fill_cnt;
0da34b6d
BG		 134 int alloc_fail;
135 int mask; /* number of rx slots -1 */
dd50f336 136 int watchdog_needed;
0da34b6d
BG		 137};
138
139struct myri10ge_tx_buf {
140 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
0da34b6d
BG		 141 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
142 char *req_bytes;
143 struct myri10ge_tx_buffer_state *info;
144 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 145 int req ____cacheline_aligned; /* transmit slots submitted */
146 int pkt_start; /* packets started */
b53bef84
BG		 147 int stop_queue;
148 int linearized;
0da34b6d
BG		 149 int done ____cacheline_aligned; /* transmit slots completed */
150 int pkt_done; /* packets completed */
b53bef84 151 int wake_queue;
0da34b6d
BG		 152};
153
154struct myri10ge_rx_done {
155 struct mcp_slot *entry;
156 dma_addr_t bus;
157 int cnt;
158 int idx;
1e6e9342
AG		 159 struct net_lro_mgr lro_mgr;
160 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 161};
162
b53bef84
BG		 163struct myri10ge_slice_netstats {
164 unsigned long rx_packets;
165 unsigned long tx_packets;
166 unsigned long rx_bytes;
167 unsigned long tx_bytes;
168 unsigned long rx_dropped;
169 unsigned long tx_dropped;
170};
171
172struct myri10ge_slice_state {
0da34b6d
BG		 173 struct myri10ge_tx_buf tx; /* transmit ring */
174 struct myri10ge_rx_buf rx_small;
175 struct myri10ge_rx_buf rx_big;
176 struct myri10ge_rx_done rx_done;
b53bef84
BG		 177 struct net_device *dev;
178 struct napi_struct napi;
179 struct myri10ge_priv *mgp;
180 struct myri10ge_slice_netstats stats;
181 __be32 __iomem *irq_claim;
182 struct mcp_irq_data *fw_stats;
183 dma_addr_t fw_stats_bus;
184 int watchdog_tx_done;
185 int watchdog_tx_req;
ead7b940 186#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 187 int cached_dca_tag;
188 int cpu;
189 __be32 __iomem *dca_tag;
190#endif
0dcffac1 191 char irq_desc[32];
b53bef84
BG		 192};
193
194struct myri10ge_priv {
0dcffac1 195 struct myri10ge_slice_state *ss;
b53bef84 196 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 197 int num_slices;
b53bef84
BG		 198 int running; /* running? */
199 int csum_flag; /* rx_csums? */
0da34b6d 200 int small_bytes;
dd50f336 201 int big_bytes;
fa0a90d9 202 int max_intr_slots;
0da34b6d
BG		 203 struct net_device *dev;
204 struct net_device_stats stats;
b53bef84 205 spinlock_t stats_lock;
0da34b6d
BG		 206 u8 __iomem *sram;
207 int sram_size;
208 unsigned long board_span;
209 unsigned long iomem_base;
40f6cff5 210 __be32 __iomem *irq_deassert;
0da34b6d
BG		 211 char *mac_addr_string;
212 struct mcp_cmd_response *cmd;
213 dma_addr_t cmd_bus;
0da34b6d
BG		 214 struct pci_dev *pdev;
215 int msi_enabled;
0dcffac1
BG		 216 int msix_enabled;
217 struct msix_entry *msix_vectors;
ead7b940 218#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 219 int dca_enabled;
220#endif
66341fff 221 u32 link_state;
0da34b6d
BG		 222 unsigned int rdma_tags_available;
223 int intr_coal_delay;
40f6cff5 224 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 225 int mtrr;
276e26c3 226 int wc_enabled;
0da34b6d
BG		 227 int down_cnt;
228 wait_queue_head_t down_wq;
229 struct work_struct watchdog_work;
230 struct timer_list watchdog_timer;
0da34b6d 231 int watchdog_resets;
b53bef84 232 int watchdog_pause;
0da34b6d
BG		 233 int pause;
234 char *fw_name;
235 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 236 char *product_code_string;
0da34b6d 237 char fw_version[128];
9dc6f0e7
BG		 238 int fw_ver_major;
239 int fw_ver_minor;
240 int fw_ver_tiny;
241 int adopted_rx_filter_bug;
0da34b6d
BG		 242 u8 mac_addr[6]; /* eeprom mac address */
243 unsigned long serial_number;
244 int vendor_specific_offset;
85a7ea1b 245 int fw_multicast_support;
4f93fde0
BG		 246 unsigned long features;
247 u32 max_tso6;
0da34b6d
BG		 248 u32 read_dma;
249 u32 write_dma;
250 u32 read_write_dma;
c58ac5ca
BG		 251 u32 link_changes;
252 u32 msg_enable;
0da34b6d
BG		 253};
254
255static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
256static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 257static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
258static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
0da34b6d
BG		 259
260static char *myri10ge_fw_name = NULL;
261module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 262MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d
BG		 263
264static int myri10ge_ecrc_enable = 1;
265module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 266MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 267
0da34b6d
BG		 268static int myri10ge_small_bytes = -1; /* -1 == auto */
269module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 270MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 271
272static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 273module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 274MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 275
f761fae1 276static int myri10ge_intr_coal_delay = 75;
0da34b6d 277module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 278MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 279
280static int myri10ge_flow_control = 1;
281module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 282MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 283
284static int myri10ge_deassert_wait = 1;
285module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
286MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 287 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 288
289static int myri10ge_force_firmware = 0;
290module_param(myri10ge_force_firmware, int, S_IRUGO);
291MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 292 "Force firmware to assume aligned completions");
0da34b6d 293
0da34b6d
BG		 294static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
295module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 296MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 297
298static int myri10ge_napi_weight = 64;
299module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 300MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 301
302static int myri10ge_watchdog_timeout = 1;
303module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 304MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 305
306static int myri10ge_max_irq_loops = 1048576;
307module_param(myri10ge_max_irq_loops, int, S_IRUGO);
308MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 309 "Set stuck legacy IRQ detection threshold");
0da34b6d 310
c58ac5ca
BG		 311#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
312
313static int myri10ge_debug = -1; /* defaults above */
314module_param(myri10ge_debug, int, 0);
315MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
316
1e6e9342
AG		 317static int myri10ge_lro = 1;
318module_param(myri10ge_lro, int, S_IRUGO);
d1ce3a0f 319MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
1e6e9342
AG		 320
321static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
322module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 323MODULE_PARM_DESC(myri10ge_lro_max_pkts,
324 "Number of LRO packets to be aggregated");
1e6e9342 325
dd50f336
BG		 326static int myri10ge_fill_thresh = 256;
327module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 328MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 329
f181137f
BG		 330static int myri10ge_reset_recover = 1;
331
0dcffac1
BG		 332static int myri10ge_max_slices = 1;
333module_param(myri10ge_max_slices, int, S_IRUGO);
334MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
335
336static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
337module_param(myri10ge_rss_hash, int, S_IRUGO);
338MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
339
981813d8
BG		 340static int myri10ge_dca = 1;
341module_param(myri10ge_dca, int, S_IRUGO);
342MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
343
0da34b6d
BG		 344#define MYRI10GE_FW_OFFSET 1024*1024
345#define MYRI10GE_HIGHPART_TO_U32(X) \
346(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
347#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
348
349#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
350
2f76216f 351static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 352static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 353
6250223e 354static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 355{
6250223e 356 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 357}
358
0da34b6d
BG		 359static int
360myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
361 struct myri10ge_cmd *data, int atomic)
362{
363 struct mcp_cmd *buf;
364 char buf_bytes[sizeof(*buf) + 8];
365 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 366 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 367 u32 dma_low, dma_high, result, value;
368 int sleep_total = 0;
369
370 /* ensure buf is aligned to 8 bytes */
371 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
372
373 buf->data0 = htonl(data->data0);
374 buf->data1 = htonl(data->data1);
375 buf->data2 = htonl(data->data2);
376 buf->cmd = htonl(cmd);
377 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
378 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
379
380 buf->response_addr.low = htonl(dma_low);
381 buf->response_addr.high = htonl(dma_high);
40f6cff5 382 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 383 mb();
384 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
385
386 /* wait up to 15ms. Longest command is the DMA benchmark,
387 * which is capped at 5ms, but runs from a timeout handler
388 * that runs every 7.8ms. So a 15ms timeout leaves us with
389 * a 2.2ms margin
390 */
391 if (atomic) {
392 /* if atomic is set, do not sleep,
393 * and try to get the completion quickly
394 * (1ms will be enough for those commands) */
395 for (sleep_total = 0;
396 sleep_total < 1000
40f6cff5 397 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 398 sleep_total += 10) {
0da34b6d 399 udelay(10);
bd2db0cf
BG		 400 mb();
401 }
0da34b6d
BG		 402 } else {
403 /* use msleep for most command */
404 for (sleep_total = 0;
405 sleep_total < 15
40f6cff5 406 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 407 sleep_total++)
408 msleep(1);
409 }
410
411 result = ntohl(response->result);
412 value = ntohl(response->data);
413 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
414 if (result == 0) {
415 data->data0 = value;
416 return 0;
85a7ea1b
BG		 417 } else if (result == MXGEFW_CMD_UNKNOWN) {
418 return -ENOSYS;
5443e9ea
BG		 419 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
420 return -E2BIG;
0da34b6d
BG		 421 } else {
422 dev_err(&mgp->pdev->dev,
423 "command %d failed, result = %d\n",
424 cmd, result);
425 return -ENXIO;
426 }
427 }
428
429 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
430 cmd, result);
431 return -EAGAIN;
432}
433
434/*
435 * The eeprom strings on the lanaiX have the format
436 * SN=x\0
437 * MAC=x:x:x:x:x:x\0
438 * PT:ddd mmm xx xx:xx:xx xx\0
439 * PV:ddd mmm xx xx:xx:xx xx\0
440 */
441static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
442{
443 char *ptr, *limit;
444 int i;
445
446 ptr = mgp->eeprom_strings;
447 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
448
449 while (*ptr != '\0' && ptr < limit) {
450 if (memcmp(ptr, "MAC=", 4) == 0) {
451 ptr += 4;
452 mgp->mac_addr_string = ptr;
453 for (i = 0; i < 6; i++) {
454 if ((ptr + 2) > limit)
455 goto abort;
456 mgp->mac_addr[i] =
457 simple_strtoul(ptr, &ptr, 16);
458 ptr += 1;
459 }
460 }
c0bf8801
BG		 461 if (memcmp(ptr, "PC=", 3) == 0) {
462 ptr += 3;
463 mgp->product_code_string = ptr;
464 }
0da34b6d
BG		 465 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
466 ptr += 3;
467 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
468 }
469 while (ptr < limit && *ptr++) ;
470 }
471
472 return 0;
473
474abort:
475 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
476 return -ENXIO;
477}
478
479/*
480 * Enable or disable periodic RDMAs from the host to make certain
481 * chipsets resend dropped PCIe messages
482 */
483
484static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
485{
486 char __iomem *submit;
f8fd57c1 487 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 488 u32 dma_low, dma_high;
489 int i;
490
491 /* clear confirmation addr */
492 mgp->cmd->data = 0;
493 mb();
494
495 /* send a rdma command to the PCIe engine, and wait for the
496 * response in the confirmation address. The firmware should
497 * write a -1 there to indicate it is alive and well
498 */
499 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
500 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
501
502 buf[0] = htonl(dma_high); /* confirm addr MSW */
503 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 504 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 505 buf[3] = htonl(dma_high); /* dummy addr MSW */
506 buf[4] = htonl(dma_low); /* dummy addr LSW */
507 buf[5] = htonl(enable); /* enable? */
508
e700f9f4 509 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 510
511 myri10ge_pio_copy(submit, &buf, sizeof(buf));
512 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
513 msleep(1);
514 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
515 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
516 (enable ? "enable" : "disable"));
517}
518
519static int
520myri10ge_validate_firmware(struct myri10ge_priv *mgp,
521 struct mcp_gen_header *hdr)
522{
523 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 524
525 /* check firmware type */
526 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
527 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
528 return -EINVAL;
529 }
530
531 /* save firmware version for ethtool */
532 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
533
9dc6f0e7
BG		 534 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
535 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 536
9dc6f0e7
BG		 537 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
538 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 539 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
540 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
541 MXGEFW_VERSION_MINOR);
542 return -EINVAL;
543 }
544 return 0;
545}
546
547static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
548{
549 unsigned crc, reread_crc;
550 const struct firmware *fw;
551 struct device *dev = &mgp->pdev->dev;
b0d31d6b 552 unsigned char *fw_readback;
0da34b6d
BG		 553 struct mcp_gen_header *hdr;
554 size_t hdr_offset;
555 int status;
e454358a 556 unsigned i;
0da34b6d
BG		 557
558 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
559 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
560 mgp->fw_name);
561 status = -EINVAL;
562 goto abort_with_nothing;
563 }
564
565 /* check size */
566
567 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
568 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
569 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
570 status = -EINVAL;
571 goto abort_with_fw;
572 }
573
574 /* check id */
40f6cff5 575 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 576 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
577 dev_err(dev, "Bad firmware file\n");
578 status = -EINVAL;
579 goto abort_with_fw;
580 }
581 hdr = (void *)(fw->data + hdr_offset);
582
583 status = myri10ge_validate_firmware(mgp, hdr);
584 if (status != 0)
585 goto abort_with_fw;
586
587 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 588 for (i = 0; i < fw->size; i += 256) {
589 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
590 fw->data + i,
591 min(256U, (unsigned)(fw->size - i)));
592 mb();
593 readb(mgp->sram);
b10c0668 594 }
b0d31d6b
DW		 595 fw_readback = vmalloc(fw->size);
596 if (!fw_readback) {
597 status = -ENOMEM;
598 goto abort_with_fw;
599 }
0da34b6d 600 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 601 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
602 reread_crc = crc32(~0, fw_readback, fw->size);
603 vfree(fw_readback);
0da34b6d
BG		 604 if (crc != reread_crc) {
605 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
606 (unsigned)fw->size, reread_crc, crc);
607 status = -EIO;
608 goto abort_with_fw;
609 }
610 *size = (u32) fw->size;
611
612abort_with_fw:
613 release_firmware(fw);
614
615abort_with_nothing:
616 return status;
617}
618
619static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
620{
621 struct mcp_gen_header *hdr;
622 struct device *dev = &mgp->pdev->dev;
623 const size_t bytes = sizeof(struct mcp_gen_header);
624 size_t hdr_offset;
625 int status;
626
627 /* find running firmware header */
66341fff 628 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 629
630 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
631 dev_err(dev, "Running firmware has bad header offset (%d)\n",
632 (int)hdr_offset);
633 return -EIO;
634 }
635
636 /* copy header of running firmware from SRAM to host memory to
637 * validate firmware */
638 hdr = kmalloc(bytes, GFP_KERNEL);
639 if (hdr == NULL) {
640 dev_err(dev, "could not malloc firmware hdr\n");
641 return -ENOMEM;
642 }
643 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
644 status = myri10ge_validate_firmware(mgp, hdr);
645 kfree(hdr);
9dc6f0e7
BG		 646
647 /* check to see if adopted firmware has bug where adopting
648 * it will cause broadcasts to be filtered unless the NIC
649 * is kept in ALLMULTI mode */
650 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
651 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
652 mgp->adopted_rx_filter_bug = 1;
653 dev_warn(dev, "Adopting fw %d.%d.%d: "
654 "working around rx filter bug\n",
655 mgp->fw_ver_major, mgp->fw_ver_minor,
656 mgp->fw_ver_tiny);
657 }
0da34b6d
BG		 658 return status;
659}
660
0178ec3d 661static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 662{
663 struct myri10ge_cmd cmd;
664 int status;
665
666 /* probe for IPv6 TSO support */
667 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
668 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
669 &cmd, 0);
670 if (status == 0) {
671 mgp->max_tso6 = cmd.data0;
672 mgp->features |= NETIF_F_TSO6;
673 }
674
675 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
676 if (status != 0) {
677 dev_err(&mgp->pdev->dev,
678 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
679 return -ENXIO;
680 }
681
682 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
683
684 return 0;
685}
686
0dcffac1 687static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 688{
689 char __iomem *submit;
f8fd57c1 690 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 691 u32 dma_low, dma_high, size;
692 int status, i;
693
b10c0668 694 size = 0;
0da34b6d
BG		 695 status = myri10ge_load_hotplug_firmware(mgp, &size);
696 if (status) {
0dcffac1
BG		 697 if (!adopt)
698 return status;
0da34b6d
BG		 699 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
700
701 /* Do not attempt to adopt firmware if there
702 * was a bad crc */
703 if (status == -EIO)
704 return status;
705
706 status = myri10ge_adopt_running_firmware(mgp);
707 if (status != 0) {
708 dev_err(&mgp->pdev->dev,
709 "failed to adopt running firmware\n");
710 return status;
711 }
712 dev_info(&mgp->pdev->dev,
713 "Successfully adopted running firmware\n");
b53bef84 714 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 715 dev_warn(&mgp->pdev->dev,
716 "Using firmware currently running on NIC"
717 ". For optimal\n");
718 dev_warn(&mgp->pdev->dev,
719 "performance consider loading optimized "
720 "firmware\n");
721 dev_warn(&mgp->pdev->dev, "via hotplug\n");
722 }
723
724 mgp->fw_name = "adopted";
b53bef84 725 mgp->tx_boundary = 2048;
fa0a90d9
BG		 726 myri10ge_dummy_rdma(mgp, 1);
727 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 728 return status;
729 }
730
731 /* clear confirmation addr */
732 mgp->cmd->data = 0;
733 mb();
734
735 /* send a reload command to the bootstrap MCP, and wait for the
736 * response in the confirmation address. The firmware should
737 * write a -1 there to indicate it is alive and well
738 */
739 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
740 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
741
742 buf[0] = htonl(dma_high); /* confirm addr MSW */
743 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 744 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 745
746 /* FIX: All newest firmware should un-protect the bottom of
747 * the sram before handoff. However, the very first interfaces
748 * do not. Therefore the handoff copy must skip the first 8 bytes
749 */
750 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
751 buf[4] = htonl(size - 8); /* length of code */
752 buf[5] = htonl(8); /* where to copy to */
753 buf[6] = htonl(0); /* where to jump to */
754
e700f9f4 755 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 756
757 myri10ge_pio_copy(submit, &buf, sizeof(buf));
758 mb();
759 msleep(1);
760 mb();
761 i = 0;
d93ca2a4
BG		 762 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
763 msleep(1 << i);
0da34b6d
BG		 764 i++;
765 }
766 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
767 dev_err(&mgp->pdev->dev, "handoff failed\n");
768 return -ENXIO;
769 }
9a71db72 770 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 771 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 772
fa0a90d9 773 return status;
0da34b6d
BG		 774}
775
776static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
777{
778 struct myri10ge_cmd cmd;
779 int status;
780
781 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
782 | (addr[2] << 8) | addr[3]);
783
784 cmd.data1 = ((addr[4] << 8) | (addr[5]));
785
786 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
787 return status;
788}
789
790static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
791{
792 struct myri10ge_cmd cmd;
793 int status, ctl;
794
795 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
796 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
797
798 if (status) {
799 printk(KERN_ERR
800 "myri10ge: %s: Failed to set flow control mode\n",
801 mgp->dev->name);
802 return status;
803 }
804 mgp->pause = pause;
805 return 0;
806}
807
808static void
809myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
810{
811 struct myri10ge_cmd cmd;
812 int status, ctl;
813
814 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
815 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
816 if (status)
817 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
818 mgp->dev->name);
819}
820
0d6ac257 821static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 822{
823 struct myri10ge_cmd cmd;
824 int status;
0da34b6d 825 u32 len;
34fdccea
BG		 826 struct page *dmatest_page;
827 dma_addr_t dmatest_bus;
0d6ac257
BG		 828 char *test = " ";
829
830 dmatest_page = alloc_page(GFP_KERNEL);
831 if (!dmatest_page)
832 return -ENOMEM;
833 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
834 DMA_BIDIRECTIONAL);
835
836 /* Run a small DMA test.
837 * The magic multipliers to the length tell the firmware
838 * to do DMA read, write, or read+write tests. The
839 * results are returned in cmd.data0. The upper 16
840 * bits or the return is the number of transfers completed.
841 * The lower 16 bits is the time in 0.5us ticks that the
842 * transfers took to complete.
843 */
844
b53bef84 845 len = mgp->tx_boundary;
0d6ac257
BG		 846
847 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
848 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
849 cmd.data2 = len * 0x10000;
850 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
851 if (status != 0) {
852 test = "read";
853 goto abort;
854 }
855 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
856 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
857 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
858 cmd.data2 = len * 0x1;
859 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
860 if (status != 0) {
861 test = "write";
862 goto abort;
863 }
864 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
865
866 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
867 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
868 cmd.data2 = len * 0x10001;
869 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
870 if (status != 0) {
871 test = "read/write";
872 goto abort;
873 }
874 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
875 (cmd.data0 & 0xffff);
876
877abort:
878 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
879 put_page(dmatest_page);
880
881 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
882 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
883 test, status);
884
885 return status;
886}
887
888static int myri10ge_reset(struct myri10ge_priv *mgp)
889{
890 struct myri10ge_cmd cmd;
0dcffac1
BG		 891 struct myri10ge_slice_state *ss;
892 int i, status;
0d6ac257 893 size_t bytes;
ead7b940 894#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 895 unsigned long dca_tag_off;
896#endif
0da34b6d
BG		 897
898 /* try to send a reset command to the card to see if it
899 * is alive */
900 memset(&cmd, 0, sizeof(cmd));
901 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
902 if (status != 0) {
903 dev_err(&mgp->pdev->dev, "failed reset\n");
904 return -ENXIO;
905 }
0d6ac257
BG		 906
907 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 908 /*
909 * Use non-ndis mcp_slot (eg, 4 bytes total,
910 * no toeplitz hash value returned. Older firmware will
911 * not understand this command, but will use the correct
912 * sized mcp_slot, so we ignore error returns
913 */
914 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
915 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 916
917 /* Now exchange information about interrupts */
918
0dcffac1 919 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 920 cmd.data0 = (u32) bytes;
921 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 922
923 /*
924 * Even though we already know how many slices are supported
925 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
926 * has magic side effects, and must be called after a reset.
927 * It must be called prior to calling any RSS related cmds,
928 * including assigning an interrupt queue for anything but
929 * slice 0. It must also be called *after*
930 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
931 * the firmware to compute offsets.
932 */
933
934 if (mgp->num_slices > 1) {
935
936 /* ask the maximum number of slices it supports */
937 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
938 &cmd, 0);
939 if (status != 0) {
940 dev_err(&mgp->pdev->dev,
941 "failed to get number of slices\n");
942 }
943
944 /*
945 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
946 * to setting up the interrupt queue DMA
947 */
948
949 cmd.data0 = mgp->num_slices;
950 cmd.data1 = 1; /* use MSI-X */
951 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
952 &cmd, 0);
953 if (status != 0) {
954 dev_err(&mgp->pdev->dev,
955 "failed to set number of slices\n");
956
957 return status;
958 }
959 }
960 for (i = 0; i < mgp->num_slices; i++) {
961 ss = &mgp->ss[i];
962 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
963 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
964 cmd.data2 = i;
965 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
966 &cmd, 0);
967 };
0da34b6d
BG		 968
969 status |=
970 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 971 for (i = 0; i < mgp->num_slices; i++) {
972 ss = &mgp->ss[i];
973 ss->irq_claim =
974 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
975 }
df30a740
BG		 976 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
977 &cmd, 0);
978 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 979
0da34b6d
BG		 980 status |= myri10ge_send_cmd
981 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 982 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 983 if (status != 0) {
984 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
985 return status;
986 }
40f6cff5 987 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 988
ead7b940 989#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 990 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
991 dca_tag_off = cmd.data0;
992 for (i = 0; i < mgp->num_slices; i++) {
993 ss = &mgp->ss[i];
994 if (status == 0) {
995 ss->dca_tag = (__iomem __be32 *)
996 (mgp->sram + dca_tag_off + 4 * i);
997 } else {
998 ss->dca_tag = NULL;
999 }
1000 }
1001#endif /* CONFIG_DCA */
1002
0da34b6d 1003 /* reset mcp/driver shared state back to 0 */
0dcffac1 1004
c58ac5ca 1005 mgp->link_changes = 0;
0dcffac1
BG		 1006 for (i = 0; i < mgp->num_slices; i++) {
1007 ss = &mgp->ss[i];
1008
1009 memset(ss->rx_done.entry, 0, bytes);
1010 ss->tx.req = 0;
1011 ss->tx.done = 0;
1012 ss->tx.pkt_start = 0;
1013 ss->tx.pkt_done = 0;
1014 ss->rx_big.cnt = 0;
1015 ss->rx_small.cnt = 0;
1016 ss->rx_done.idx = 0;
1017 ss->rx_done.cnt = 0;
1018 ss->tx.wake_queue = 0;
1019 ss->tx.stop_queue = 0;
1020 }
1021
0da34b6d 1022 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1023 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1024 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1025 return status;
1026}
1027
ead7b940 1028#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 1029static void
1030myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1031{
1032 ss->cpu = cpu;
1033 ss->cached_dca_tag = tag;
1034 put_be32(htonl(tag), ss->dca_tag);
1035}
1036
1037static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1038{
1039 int cpu = get_cpu();
1040 int tag;
1041
1042 if (cpu != ss->cpu) {
1043 tag = dca_get_tag(cpu);
1044 if (ss->cached_dca_tag != tag)
1045 myri10ge_write_dca(ss, cpu, tag);
1046 }
1047 put_cpu();
1048}
1049
1050static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1051{
1052 int err, i;
1053 struct pci_dev *pdev = mgp->pdev;
1054
1055 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1056 return;
1057 if (!myri10ge_dca) {
1058 dev_err(&pdev->dev, "dca disabled by administrator\n");
1059 return;
1060 }
1061 err = dca_add_requester(&pdev->dev);
1062 if (err) {
330554cb
BG		 1063 if (err != -ENODEV)
1064 dev_err(&pdev->dev,
1065 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1066 return;
1067 }
1068 mgp->dca_enabled = 1;
1069 for (i = 0; i < mgp->num_slices; i++)
1070 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1071}
1072
1073static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1074{
1075 struct pci_dev *pdev = mgp->pdev;
1076 int err;
1077
1078 if (!mgp->dca_enabled)
1079 return;
1080 mgp->dca_enabled = 0;
1081 err = dca_remove_requester(&pdev->dev);
1082}
1083
1084static int myri10ge_notify_dca_device(struct device *dev, void *data)
1085{
1086 struct myri10ge_priv *mgp;
1087 unsigned long event;
1088
1089 mgp = dev_get_drvdata(dev);
1090 event = *(unsigned long *)data;
1091
1092 if (event == DCA_PROVIDER_ADD)
1093 myri10ge_setup_dca(mgp);
1094 else if (event == DCA_PROVIDER_REMOVE)
1095 myri10ge_teardown_dca(mgp);
1096 return 0;
1097}
1098#endif /* CONFIG_DCA */
1099
0da34b6d
BG		 1100static inline void
1101myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1102 struct mcp_kreq_ether_recv *src)
1103{
40f6cff5 1104 __be32 low;
0da34b6d
BG		 1105
1106 low = src->addr_low;
40f6cff5 1107 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 1108 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1109 mb();
1110 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1111 mb();
1112 src->addr_low = low;
40f6cff5 1113 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1114 mb();
1115}
1116
40f6cff5 1117static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1118{
1119 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1120
40f6cff5 1121 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1122 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1123 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1124 skb->csum = hw_csum;
84fa7933 1125 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1126 }
1127}
1128
dd50f336
BG		 1129static inline void
1130myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1131 struct skb_frag_struct *rx_frags, int len, int hlen)
1132{
1133 struct skb_frag_struct *skb_frags;
1134
1135 skb->len = skb->data_len = len;
1136 skb->truesize = len + sizeof(struct sk_buff);
1137 /* attach the page(s) */
1138
1139 skb_frags = skb_shinfo(skb)->frags;
1140 while (len > 0) {
1141 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1142 len -= rx_frags->size;
1143 skb_frags++;
1144 rx_frags++;
1145 skb_shinfo(skb)->nr_frags++;
1146 }
1147
1148 /* pskb_may_pull is not available in irq context, but
1149 * skb_pull() (for ether_pad and eth_type_trans()) requires
1150 * the beginning of the packet in skb_headlen(), move it
1151 * manually */
27d7ff46 1152 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1153 skb_shinfo(skb)->frags[0].page_offset += hlen;
1154 skb_shinfo(skb)->frags[0].size -= hlen;
1155 skb->data_len -= hlen;
1156 skb->tail += hlen;
1157 skb_pull(skb, MXGEFW_PAD);
1158}
1159
1160static void
1161myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1162 int bytes, int watchdog)
1163{
1164 struct page *page;
1165 int idx;
1166
1167 if (unlikely(rx->watchdog_needed && !watchdog))
1168 return;
1169
1170 /* try to refill entire ring */
1171 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1172 idx = rx->fill_cnt & rx->mask;
ae8509b1 1173 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1174 /* we can use part of previous page */
1175 get_page(rx->page);
1176 } else {
1177 /* we need a new page */
1178 page =
1179 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1180 MYRI10GE_ALLOC_ORDER);
1181 if (unlikely(page == NULL)) {
1182 if (rx->fill_cnt - rx->cnt < 16)
1183 rx->watchdog_needed = 1;
1184 return;
1185 }
1186 rx->page = page;
1187 rx->page_offset = 0;
1188 rx->bus = pci_map_page(mgp->pdev, page, 0,
1189 MYRI10GE_ALLOC_SIZE,
1190 PCI_DMA_FROMDEVICE);
1191 }
1192 rx->info[idx].page = rx->page;
1193 rx->info[idx].page_offset = rx->page_offset;
1194 /* note that this is the address of the start of the
1195 * page */
1196 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1197 rx->shadow[idx].addr_low =
1198 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1199 rx->shadow[idx].addr_high =
1200 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1201
1202 /* start next packet on a cacheline boundary */
1203 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1204
1205#if MYRI10GE_ALLOC_SIZE > 4096
1206 /* don't cross a 4KB boundary */
1207 if ((rx->page_offset >> 12) !=
1208 ((rx->page_offset + bytes - 1) >> 12))
1209 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1210#endif
dd50f336
BG		 1211 rx->fill_cnt++;
1212
1213 /* copy 8 descriptors to the firmware at a time */
1214 if ((idx & 7) == 7) {
e454e7e2
BG		 1215 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1216 &rx->shadow[idx - 7]);
dd50f336
BG		 1217 }
1218 }
1219}
1220
1221static inline void
1222myri10ge_unmap_rx_page(struct pci_dev *pdev,
1223 struct myri10ge_rx_buffer_state *info, int bytes)
1224{
1225 /* unmap the recvd page if we're the only or last user of it */
1226 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1227 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1228 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1229 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1230 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1231 }
1232}
1233
1234#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1235 * page into an skb */
1236
1237static inline int
b53bef84 1238myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
52ea6fb3 1239 int bytes, int len, __wsum csum)
dd50f336 1240{
b53bef84 1241 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1242 struct sk_buff *skb;
1243 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1244 int i, idx, hlen, remainder;
1245 struct pci_dev *pdev = mgp->pdev;
1246 struct net_device *dev = mgp->dev;
1247 u8 *va;
1248
1249 len += MXGEFW_PAD;
1250 idx = rx->cnt & rx->mask;
1251 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1252 prefetch(va);
1253 /* Fill skb_frag_struct(s) with data from our receive */
1254 for (i = 0, remainder = len; remainder > 0; i++) {
1255 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1256 rx_frags[i].page = rx->info[idx].page;
1257 rx_frags[i].page_offset = rx->info[idx].page_offset;
1258 if (remainder < MYRI10GE_ALLOC_SIZE)
1259 rx_frags[i].size = remainder;
1260 else
1261 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1262 rx->cnt++;
1263 idx = rx->cnt & rx->mask;
1264 remainder -= MYRI10GE_ALLOC_SIZE;
1265 }
1266
1e6e9342
AG		 1267 if (mgp->csum_flag && myri10ge_lro) {
1268 rx_frags[0].page_offset += MXGEFW_PAD;
1269 rx_frags[0].size -= MXGEFW_PAD;
1270 len -= MXGEFW_PAD;
b53bef84 1271 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1272 /* opaque, will come back in get_frag_header */
0dcffac1 1273 len, len,
b53bef84 1274 (void *)(__force unsigned long)csum, csum);
0dcffac1 1275
1e6e9342
AG		 1276 return 1;
1277 }
1278
dd50f336
BG		 1279 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1280
e636b2ea
BG		 1281 /* allocate an skb to attach the page(s) to. This is done
1282 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1283
1284 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1285 if (unlikely(skb == NULL)) {
1286 mgp->stats.rx_dropped++;
1287 do {
1288 i--;
1289 put_page(rx_frags[i].page);
1290 } while (i != 0);
1291 return 0;
1292 }
1293
1294 /* Attach the pages to the skb, and trim off any padding */
1295 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1296 if (skb_shinfo(skb)->frags[0].size <= 0) {
1297 put_page(skb_shinfo(skb)->frags[0].page);
1298 skb_shinfo(skb)->nr_frags = 0;
1299 }
1300 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1301
1302 if (mgp->csum_flag) {
1303 if ((skb->protocol == htons(ETH_P_IP)) ||
1304 (skb->protocol == htons(ETH_P_IPV6))) {
1305 skb->csum = csum;
1306 skb->ip_summed = CHECKSUM_COMPLETE;
1307 } else
1308 myri10ge_vlan_ip_csum(skb, csum);
1309 }
1310 netif_receive_skb(skb);
1311 dev->last_rx = jiffies;
1312 return 1;
1313}
1314
b53bef84
BG		 1315static inline void
1316myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1317{
b53bef84
BG		 1318 struct pci_dev *pdev = ss->mgp->pdev;
1319 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1320 struct sk_buff *skb;
1321 int idx, len;
0da34b6d
BG		 1322
1323 while (tx->pkt_done != mcp_index) {
1324 idx = tx->done & tx->mask;
1325 skb = tx->info[idx].skb;
1326
1327 /* Mark as free */
1328 tx->info[idx].skb = NULL;
1329 if (tx->info[idx].last) {
1330 tx->pkt_done++;
1331 tx->info[idx].last = 0;
1332 }
1333 tx->done++;
1334 len = pci_unmap_len(&tx->info[idx], len);
1335 pci_unmap_len_set(&tx->info[idx], len, 0);
1336 if (skb) {
b53bef84
BG		 1337 ss->stats.tx_bytes += skb->len;
1338 ss->stats.tx_packets++;
0da34b6d
BG		 1339 dev_kfree_skb_irq(skb);
1340 if (len)
1341 pci_unmap_single(pdev,
1342 pci_unmap_addr(&tx->info[idx],
1343 bus), len,
1344 PCI_DMA_TODEVICE);
1345 } else {
1346 if (len)
1347 pci_unmap_page(pdev,
1348 pci_unmap_addr(&tx->info[idx],
1349 bus), len,
1350 PCI_DMA_TODEVICE);
1351 }
0da34b6d
BG		 1352 }
1353 /* start the queue if we've stopped it */
b53bef84 1354 if (netif_queue_stopped(ss->dev)
0da34b6d 1355 && tx->req - tx->done < (tx->mask >> 1)) {
b53bef84
BG		 1356 tx->wake_queue++;
1357 netif_wake_queue(ss->dev);
0da34b6d
BG		 1358 }
1359}
1360
b53bef84
BG		 1361static inline int
1362myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1363{
b53bef84
BG		 1364 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1365 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1366 unsigned long rx_bytes = 0;
1367 unsigned long rx_packets = 0;
1368 unsigned long rx_ok;
1369
1370 int idx = rx_done->idx;
1371 int cnt = rx_done->cnt;
bea3348e 1372 int work_done = 0;
0da34b6d 1373 u16 length;
40f6cff5 1374 __wsum checksum;
0da34b6d 1375
c956a240 1376 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1377 length = ntohs(rx_done->entry[idx].length);
1378 rx_done->entry[idx].length = 0;
40f6cff5 1379 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1380 if (length <= mgp->small_bytes)
b53bef84 1381 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
52ea6fb3
BG		 1382 mgp->small_bytes,
1383 length, checksum);
0da34b6d 1384 else
b53bef84 1385 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
52ea6fb3
BG		 1386 mgp->big_bytes,
1387 length, checksum);
0da34b6d
BG		 1388 rx_packets += rx_ok;
1389 rx_bytes += rx_ok * (unsigned long)length;
1390 cnt++;
014377a1 1391 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1392 work_done++;
0da34b6d
BG		 1393 }
1394 rx_done->idx = idx;
1395 rx_done->cnt = cnt;
b53bef84
BG		 1396 ss->stats.rx_packets += rx_packets;
1397 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1398
1e6e9342
AG		 1399 if (myri10ge_lro)
1400 lro_flush_all(&rx_done->lro_mgr);
1401
c7dab99b 1402 /* restock receive rings if needed */
b53bef84
BG		 1403 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1404 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1405 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1406 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1407 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1408
bea3348e 1409 return work_done;
0da34b6d
BG		 1410}
1411
1412static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1413{
0dcffac1 1414 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1415
1416 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1417 unsigned link_up = ntohl(stats->link_up);
1418 if (mgp->link_state != link_up) {
1419 mgp->link_state = link_up;
1420
1421 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1422 if (netif_msg_link(mgp))
1423 printk(KERN_INFO
1424 "myri10ge: %s: link up\n",
1425 mgp->dev->name);
0da34b6d 1426 netif_carrier_on(mgp->dev);
c58ac5ca 1427 mgp->link_changes++;
0da34b6d 1428 } else {
c58ac5ca
BG		 1429 if (netif_msg_link(mgp))
1430 printk(KERN_INFO
798a95db
BG		 1431 "myri10ge: %s: link %s\n",
1432 mgp->dev->name,
1433 (link_up == MXGEFW_LINK_MYRINET ?
1434 "mismatch (Myrinet detected)" :
1435 "down"));
0da34b6d 1436 netif_carrier_off(mgp->dev);
c58ac5ca 1437 mgp->link_changes++;
0da34b6d
BG		 1438 }
1439 }
1440 if (mgp->rdma_tags_available !=
b53bef84 1441 ntohl(stats->rdma_tags_available)) {
0da34b6d 1442 mgp->rdma_tags_available =
b53bef84 1443 ntohl(stats->rdma_tags_available);
0da34b6d
BG		 1444 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1445 "%d tags left\n", mgp->dev->name,
1446 mgp->rdma_tags_available);
1447 }
1448 mgp->down_cnt += stats->link_down;
1449 if (stats->link_down)
1450 wake_up(&mgp->down_wq);
1451 }
1452}
1453
bea3348e 1454static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1455{
b53bef84
BG		 1456 struct myri10ge_slice_state *ss =
1457 container_of(napi, struct myri10ge_slice_state, napi);
1458 struct net_device *netdev = ss->mgp->dev;
bea3348e 1459 int work_done;
0da34b6d 1460
ead7b940 1461#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 1462 if (ss->mgp->dca_enabled)
1463 myri10ge_update_dca(ss);
1464#endif
1465
0da34b6d 1466 /* process as many rx events as NAPI will allow */
b53bef84 1467 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1468
4ec24119 1469 if (work_done < budget) {
bea3348e 1470 netif_rx_complete(netdev, napi);
b53bef84 1471 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1472 }
bea3348e 1473 return work_done;
0da34b6d
BG		 1474}
1475
7d12e780 1476static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1477{
b53bef84
BG		 1478 struct myri10ge_slice_state *ss = arg;
1479 struct myri10ge_priv *mgp = ss->mgp;
1480 struct mcp_irq_data *stats = ss->fw_stats;
1481 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1482 u32 send_done_count;
1483 int i;
1484
0dcffac1
BG		 1485 /* an interrupt on a non-zero slice is implicitly valid
1486 * since MSI-X irqs are not shared */
1487 if (ss != mgp->ss) {
1488 netif_rx_schedule(ss->dev, &ss->napi);
1489 return (IRQ_HANDLED);
1490 }
1491
0da34b6d
BG		 1492 /* make sure it is our IRQ, and that the DMA has finished */
1493 if (unlikely(!stats->valid))
1494 return (IRQ_NONE);
1495
1496 /* low bit indicates receives are present, so schedule
1497 * napi poll handler */
1498 if (stats->valid & 1)
b53bef84 1499 netif_rx_schedule(ss->dev, &ss->napi);
0da34b6d 1500
0dcffac1 1501 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1502 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1503 if (!myri10ge_deassert_wait)
1504 stats->valid = 0;
1505 mb();
1506 } else
1507 stats->valid = 0;
1508
1509 /* Wait for IRQ line to go low, if using INTx */
1510 i = 0;
1511 while (1) {
1512 i++;
1513 /* check for transmit completes and receives */
1514 send_done_count = ntohl(stats->send_done_count);
1515 if (send_done_count != tx->pkt_done)
b53bef84 1516 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d
BG		 1517 if (unlikely(i > myri10ge_max_irq_loops)) {
1518 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1519 mgp->dev->name);
1520 stats->valid = 0;
1521 schedule_work(&mgp->watchdog_work);
1522 }
1523 if (likely(stats->valid == 0))
1524 break;
1525 cpu_relax();
1526 barrier();
1527 }
1528
1529 myri10ge_check_statblock(mgp);
1530
b53bef84 1531 put_be32(htonl(3), ss->irq_claim + 1);
0da34b6d
BG		 1532 return (IRQ_HANDLED);
1533}
1534
1535static int
1536myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1537{
c0bf8801
BG		 1538 struct myri10ge_priv *mgp = netdev_priv(netdev);
1539 char *ptr;
1540 int i;
1541
0da34b6d
BG		 1542 cmd->autoneg = AUTONEG_DISABLE;
1543 cmd->speed = SPEED_10000;
1544 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1545
1546 /*
1547 * parse the product code to deterimine the interface type
1548 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1549 * after the 3rd dash in the driver's cached copy of the
1550 * EEPROM's product code string.
1551 */
1552 ptr = mgp->product_code_string;
1553 if (ptr == NULL) {
1554 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
99f5f87e 1555 netdev->name);
c0bf8801
BG		 1556 return 0;
1557 }
1558 for (i = 0; i < 3; i++, ptr++) {
1559 ptr = strchr(ptr, '-');
1560 if (ptr == NULL) {
1561 printk(KERN_ERR "myri10ge: %s: Invalid product "
1562 "code %s\n", netdev->name,
1563 mgp->product_code_string);
1564 return 0;
1565 }
1566 }
1567 if (*ptr == 'R' || *ptr == 'Q') {
1568 /* We've found either an XFP or quad ribbon fiber */
1569 cmd->port = PORT_FIBRE;
1570 }
0da34b6d
BG		 1571 return 0;
1572}
1573
1574static void
1575myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1576{
1577 struct myri10ge_priv *mgp = netdev_priv(netdev);
1578
1579 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1580 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1581 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1582 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1583}
1584
1585static int
1586myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1587{
1588 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1589
0da34b6d
BG		 1590 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1591 return 0;
1592}
1593
1594static int
1595myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1596{
1597 struct myri10ge_priv *mgp = netdev_priv(netdev);
1598
1599 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1600 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1601 return 0;
1602}
1603
1604static void
1605myri10ge_get_pauseparam(struct net_device *netdev,
1606 struct ethtool_pauseparam *pause)
1607{
1608 struct myri10ge_priv *mgp = netdev_priv(netdev);
1609
1610 pause->autoneg = 0;
1611 pause->rx_pause = mgp->pause;
1612 pause->tx_pause = mgp->pause;
1613}
1614
1615static int
1616myri10ge_set_pauseparam(struct net_device *netdev,
1617 struct ethtool_pauseparam *pause)
1618{
1619 struct myri10ge_priv *mgp = netdev_priv(netdev);
1620
1621 if (pause->tx_pause != mgp->pause)
1622 return myri10ge_change_pause(mgp, pause->tx_pause);
1623 if (pause->rx_pause != mgp->pause)
1624 return myri10ge_change_pause(mgp, pause->tx_pause);
1625 if (pause->autoneg != 0)
1626 return -EINVAL;
1627 return 0;
1628}
1629
1630static void
1631myri10ge_get_ringparam(struct net_device *netdev,
1632 struct ethtool_ringparam *ring)
1633{
1634 struct myri10ge_priv *mgp = netdev_priv(netdev);
1635
0dcffac1
BG		 1636 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1637 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1638 ring->rx_jumbo_max_pending = 0;
0dcffac1 1639 ring->tx_max_pending = mgp->ss[0].rx_small.mask + 1;
0da34b6d
BG		 1640 ring->rx_mini_pending = ring->rx_mini_max_pending;
1641 ring->rx_pending = ring->rx_max_pending;
1642 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1643 ring->tx_pending = ring->tx_max_pending;
1644}
1645
1646static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1647{
1648 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1649
0da34b6d
BG		 1650 if (mgp->csum_flag)
1651 return 1;
1652 else
1653 return 0;
1654}
1655
1656static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1657{
1658 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1659
0da34b6d
BG		 1660 if (csum_enabled)
1661 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1662 else
1663 mgp->csum_flag = 0;
1664 return 0;
1665}
1666
4f93fde0
BG		 1667static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1668{
1669 struct myri10ge_priv *mgp = netdev_priv(netdev);
1670 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1671
1672 if (tso_enabled)
1673 netdev->features |= flags;
1674 else
1675 netdev->features &= ~flags;
1676 return 0;
1677}
1678
b53bef84 1679static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1680 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1681 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1682 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1683 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1684 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1685 "tx_heartbeat_errors", "tx_window_errors",
1686 /* device-specific stats */
0dcffac1 1687 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1688 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1689 "serial_number", "watchdog_resets",
ead7b940 1690#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
9a6b3b54 1691 "dca_capable_firmware", "dca_device_present",
981813d8 1692#endif
c58ac5ca 1693 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1694 "dropped_link_error_or_filtered",
1695 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1696 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1697 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1698 "dropped_no_big_buffer"
1699};
1700
1701static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1702 "----------- slice ---------",
1703 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1704 "rx_small_cnt", "rx_big_cnt",
1705 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1706 "LRO flushed",
1e6e9342 1707 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1708};
1709
1710#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1711#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1712#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1713
1714static void
1715myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1716{
0dcffac1
BG		 1717 struct myri10ge_priv *mgp = netdev_priv(netdev);
1718 int i;
1719
0da34b6d
BG		 1720 switch (stringset) {
1721 case ETH_SS_STATS:
b53bef84
BG		 1722 memcpy(data, *myri10ge_gstrings_main_stats,
1723 sizeof(myri10ge_gstrings_main_stats));
1724 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1725 for (i = 0; i < mgp->num_slices; i++) {
1726 memcpy(data, *myri10ge_gstrings_slice_stats,
1727 sizeof(myri10ge_gstrings_slice_stats));
1728 data += sizeof(myri10ge_gstrings_slice_stats);
1729 }
0da34b6d
BG		 1730 break;
1731 }
1732}
1733
b9f2c044 1734static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1735{
0dcffac1
BG		 1736 struct myri10ge_priv *mgp = netdev_priv(netdev);
1737
b9f2c044
JG		 1738 switch (sset) {
1739 case ETH_SS_STATS:
0dcffac1
BG		 1740 return MYRI10GE_MAIN_STATS_LEN +
1741 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1742 default:
1743 return -EOPNOTSUPP;
1744 }
0da34b6d
BG		 1745}
1746
1747static void
1748myri10ge_get_ethtool_stats(struct net_device *netdev,
1749 struct ethtool_stats *stats, u64 * data)
1750{
1751 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1752 struct myri10ge_slice_state *ss;
0dcffac1 1753 int slice;
0da34b6d
BG		 1754 int i;
1755
1756 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1757 data[i] = ((unsigned long *)&mgp->stats)[i];
1758
b53bef84 1759 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1760 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1761 data[i++] = (unsigned int)mgp->pdev->irq;
1762 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1763 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1764 data[i++] = (unsigned int)mgp->read_dma;
1765 data[i++] = (unsigned int)mgp->write_dma;
1766 data[i++] = (unsigned int)mgp->read_write_dma;
1767 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1768 data[i++] = (unsigned int)mgp->watchdog_resets;
ead7b940 1769#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 1770 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1771 data[i++] = (unsigned int)(mgp->dca_enabled);
1772#endif
c58ac5ca 1773 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1774
1775 /* firmware stats are useful only in the first slice */
0dcffac1 1776 ss = &mgp->ss[0];
b53bef84
BG		 1777 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1778 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1779 data[i++] =
b53bef84
BG		 1780 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1781 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1782 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1783 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1784 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1785 data[i++] =
b53bef84
BG		 1786 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1787 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1788 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1789 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1790 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1791
0dcffac1
BG		 1792 for (slice = 0; slice < mgp->num_slices; slice++) {
1793 ss = &mgp->ss[slice];
1794 data[i++] = slice;
1795 data[i++] = (unsigned int)ss->tx.pkt_start;
1796 data[i++] = (unsigned int)ss->tx.pkt_done;
1797 data[i++] = (unsigned int)ss->tx.req;
1798 data[i++] = (unsigned int)ss->tx.done;
1799 data[i++] = (unsigned int)ss->rx_small.cnt;
1800 data[i++] = (unsigned int)ss->rx_big.cnt;
1801 data[i++] = (unsigned int)ss->tx.wake_queue;
1802 data[i++] = (unsigned int)ss->tx.stop_queue;
1803 data[i++] = (unsigned int)ss->tx.linearized;
1804 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1805 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1806 if (ss->rx_done.lro_mgr.stats.flushed)
1807 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1808 ss->rx_done.lro_mgr.stats.flushed;
1809 else
1810 data[i++] = 0;
1811 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1812 }
0da34b6d
BG		 1813}
1814
c58ac5ca
BG		 1815static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1816{
1817 struct myri10ge_priv *mgp = netdev_priv(netdev);
1818 mgp->msg_enable = value;
1819}
1820
1821static u32 myri10ge_get_msglevel(struct net_device *netdev)
1822{
1823 struct myri10ge_priv *mgp = netdev_priv(netdev);
1824 return mgp->msg_enable;
1825}
1826
7282d491 1827static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1828 .get_settings = myri10ge_get_settings,
1829 .get_drvinfo = myri10ge_get_drvinfo,
1830 .get_coalesce = myri10ge_get_coalesce,
1831 .set_coalesce = myri10ge_set_coalesce,
1832 .get_pauseparam = myri10ge_get_pauseparam,
1833 .set_pauseparam = myri10ge_set_pauseparam,
1834 .get_ringparam = myri10ge_get_ringparam,
1835 .get_rx_csum = myri10ge_get_rx_csum,
1836 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1837 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1838 .set_sg = ethtool_op_set_sg,
4f93fde0 1839 .set_tso = myri10ge_set_tso,
6ffdd071 1840 .get_link = ethtool_op_get_link,
0da34b6d 1841 .get_strings = myri10ge_get_strings,
b9f2c044 1842 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1843 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1844 .set_msglevel = myri10ge_set_msglevel,
1845 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1846};
1847
b53bef84 1848static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1849{
b53bef84 1850 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1851 struct myri10ge_cmd cmd;
b53bef84 1852 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1853 int tx_ring_size, rx_ring_size;
1854 int tx_ring_entries, rx_ring_entries;
0dcffac1 1855 int i, slice, status;
0da34b6d
BG		 1856 size_t bytes;
1857
0da34b6d 1858 /* get ring sizes */
0dcffac1
BG		 1859 slice = ss - mgp->ss;
1860 cmd.data0 = slice;
0da34b6d
BG		 1861 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1862 tx_ring_size = cmd.data0;
0dcffac1 1863 cmd.data0 = slice;
0da34b6d 1864 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1865 if (status != 0)
1866 return status;
0da34b6d
BG		 1867 rx_ring_size = cmd.data0;
1868
1869 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1870 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1871 ss->tx.mask = tx_ring_entries - 1;
1872 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1873
355c7265
BG		 1874 status = -ENOMEM;
1875
0da34b6d
BG		 1876 /* allocate the host shadow rings */
1877
1878 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1879 * sizeof(*ss->tx.req_list);
1880 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1881 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1882 goto abort_with_nothing;
1883
1884 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1885 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1886 ALIGN((unsigned long)ss->tx.req_bytes, 8);
0da34b6d 1887
b53bef84
BG		 1888 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1889 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1890 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1891 goto abort_with_tx_req_bytes;
1892
b53bef84
BG		 1893 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1894 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1895 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1896 goto abort_with_rx_small_shadow;
1897
1898 /* allocate the host info rings */
1899
b53bef84
BG		 1900 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1901 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1902 if (ss->tx.info == NULL)
0da34b6d
BG		 1903 goto abort_with_rx_big_shadow;
1904
b53bef84
BG		 1905 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1906 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1907 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1908 goto abort_with_tx_info;
1909
b53bef84
BG		 1910 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1911 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1912 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1913 goto abort_with_rx_small_info;
1914
1915 /* Fill the receive rings */
b53bef84
BG		 1916 ss->rx_big.cnt = 0;
1917 ss->rx_small.cnt = 0;
1918 ss->rx_big.fill_cnt = 0;
1919 ss->rx_small.fill_cnt = 0;
1920 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1921 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1922 ss->rx_small.watchdog_needed = 0;
1923 ss->rx_big.watchdog_needed = 0;
1924 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1925 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1926
b53bef84 1927 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
0dcffac1
BG		 1928 printk(KERN_ERR
1929 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1930 dev->name, slice, ss->rx_small.fill_cnt);
c7dab99b 1931 goto abort_with_rx_small_ring;
0da34b6d
BG		 1932 }
1933
b53bef84
BG		 1934 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1935 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
0dcffac1
BG		 1936 printk(KERN_ERR
1937 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
1938 dev->name, slice, ss->rx_big.fill_cnt);
c7dab99b 1939 goto abort_with_rx_big_ring;
0da34b6d
BG		 1940 }
1941
1942 return 0;
1943
1944abort_with_rx_big_ring:
b53bef84
BG		 1945 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1946 int idx = i & ss->rx_big.mask;
1947 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 1948 mgp->big_bytes);
b53bef84 1949 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 1950 }
1951
1952abort_with_rx_small_ring:
b53bef84
BG		 1953 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1954 int idx = i & ss->rx_small.mask;
1955 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 1956 mgp->small_bytes + MXGEFW_PAD);
b53bef84 1957 put_page(ss->rx_small.info[idx].page);
0da34b6d 1958 }
c7dab99b 1959
b53bef84 1960 kfree(ss->rx_big.info);
0da34b6d
BG		 1961
1962abort_with_rx_small_info:
b53bef84 1963 kfree(ss->rx_small.info);
0da34b6d
BG		 1964
1965abort_with_tx_info:
b53bef84 1966 kfree(ss->tx.info);
0da34b6d
BG		 1967
1968abort_with_rx_big_shadow:
b53bef84 1969 kfree(ss->rx_big.shadow);
0da34b6d
BG		 1970
1971abort_with_rx_small_shadow:
b53bef84 1972 kfree(ss->rx_small.shadow);
0da34b6d
BG		 1973
1974abort_with_tx_req_bytes:
b53bef84
BG		 1975 kfree(ss->tx.req_bytes);
1976 ss->tx.req_bytes = NULL;
1977 ss->tx.req_list = NULL;
0da34b6d
BG		 1978
1979abort_with_nothing:
1980 return status;
1981}
1982
b53bef84 1983static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 1984{
b53bef84 1985 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1986 struct sk_buff *skb;
1987 struct myri10ge_tx_buf *tx;
1988 int i, len, idx;
1989
0dcffac1
BG		 1990 /* If not allocated, skip it */
1991 if (ss->tx.req_list == NULL)
1992 return;
1993
b53bef84
BG		 1994 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1995 idx = i & ss->rx_big.mask;
1996 if (i == ss->rx_big.fill_cnt - 1)
1997 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1998 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 1999 mgp->big_bytes);
b53bef84 2000 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2001 }
2002
b53bef84
BG		 2003 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2004 idx = i & ss->rx_small.mask;
2005 if (i == ss->rx_small.fill_cnt - 1)
2006 ss->rx_small.info[idx].page_offset =
c7dab99b 2007 MYRI10GE_ALLOC_SIZE;
b53bef84 2008 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2009 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2010 put_page(ss->rx_small.info[idx].page);
c7dab99b 2011 }
b53bef84 2012 tx = &ss->tx;
0da34b6d
BG		 2013 while (tx->done != tx->req) {
2014 idx = tx->done & tx->mask;
2015 skb = tx->info[idx].skb;
2016
2017 /* Mark as free */
2018 tx->info[idx].skb = NULL;
2019 tx->done++;
2020 len = pci_unmap_len(&tx->info[idx], len);
2021 pci_unmap_len_set(&tx->info[idx], len, 0);
2022 if (skb) {
b53bef84 2023 ss->stats.tx_dropped++;
0da34b6d
BG		 2024 dev_kfree_skb_any(skb);
2025 if (len)
2026 pci_unmap_single(mgp->pdev,
2027 pci_unmap_addr(&tx->info[idx],
2028 bus), len,
2029 PCI_DMA_TODEVICE);
2030 } else {
2031 if (len)
2032 pci_unmap_page(mgp->pdev,
2033 pci_unmap_addr(&tx->info[idx],
2034 bus), len,
2035 PCI_DMA_TODEVICE);
2036 }
2037 }
b53bef84 2038 kfree(ss->rx_big.info);
0da34b6d 2039
b53bef84 2040 kfree(ss->rx_small.info);
0da34b6d 2041
b53bef84 2042 kfree(ss->tx.info);
0da34b6d 2043
b53bef84 2044 kfree(ss->rx_big.shadow);
0da34b6d 2045
b53bef84 2046 kfree(ss->rx_small.shadow);
0da34b6d 2047
b53bef84
BG		 2048 kfree(ss->tx.req_bytes);
2049 ss->tx.req_bytes = NULL;
2050 ss->tx.req_list = NULL;
0da34b6d
BG		 2051}
2052
df30a740
BG		 2053static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2054{
2055 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2056 struct myri10ge_slice_state *ss;
2057 struct net_device *netdev = mgp->dev;
2058 int i;
df30a740
BG		 2059 int status;
2060
0dcffac1
BG		 2061 mgp->msi_enabled = 0;
2062 mgp->msix_enabled = 0;
2063 status = 0;
df30a740 2064 if (myri10ge_msi) {
0dcffac1
BG		 2065 if (mgp->num_slices > 1) {
2066 status =
2067 pci_enable_msix(pdev, mgp->msix_vectors,
2068 mgp->num_slices);
2069 if (status == 0) {
2070 mgp->msix_enabled = 1;
2071 } else {
2072 dev_err(&pdev->dev,
2073 "Error %d setting up MSI-X\n", status);
2074 return status;
2075 }
2076 }
2077 if (mgp->msix_enabled == 0) {
2078 status = pci_enable_msi(pdev);
2079 if (status != 0) {
2080 dev_err(&pdev->dev,
2081 "Error %d setting up MSI; falling back to xPIC\n",
2082 status);
2083 } else {
2084 mgp->msi_enabled = 1;
2085 }
2086 }
df30a740 2087 }
0dcffac1
BG		 2088 if (mgp->msix_enabled) {
2089 for (i = 0; i < mgp->num_slices; i++) {
2090 ss = &mgp->ss[i];
2091 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2092 "%s:slice-%d", netdev->name, i);
2093 status = request_irq(mgp->msix_vectors[i].vector,
2094 myri10ge_intr, 0, ss->irq_desc,
2095 ss);
2096 if (status != 0) {
2097 dev_err(&pdev->dev,
2098 "slice %d failed to allocate IRQ\n", i);
2099 i--;
2100 while (i >= 0) {
2101 free_irq(mgp->msix_vectors[i].vector,
2102 &mgp->ss[i]);
2103 i--;
2104 }
2105 pci_disable_msix(pdev);
2106 return status;
2107 }
2108 }
2109 } else {
2110 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2111 mgp->dev->name, &mgp->ss[0]);
2112 if (status != 0) {
2113 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2114 if (mgp->msi_enabled)
2115 pci_disable_msi(pdev);
2116 }
df30a740
BG		 2117 }
2118 return status;
2119}
2120
2121static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2122{
2123 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2124 int i;
df30a740 2125
0dcffac1
BG		 2126 if (mgp->msix_enabled) {
2127 for (i = 0; i < mgp->num_slices; i++)
2128 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2129 } else {
2130 free_irq(pdev->irq, &mgp->ss[0]);
2131 }
df30a740
BG		 2132 if (mgp->msi_enabled)
2133 pci_disable_msi(pdev);
0dcffac1
BG		 2134 if (mgp->msix_enabled)
2135 pci_disable_msix(pdev);
df30a740
BG		 2136}
2137
1e6e9342
AG		 2138static int
2139myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2140 void **ip_hdr, void **tcpudp_hdr,
2141 u64 * hdr_flags, void *priv)
2142{
2143 struct ethhdr *eh;
2144 struct vlan_ethhdr *veh;
2145 struct iphdr *iph;
2146 u8 *va = page_address(frag->page) + frag->page_offset;
2147 unsigned long ll_hlen;
66341fff
AV		 2148 /* passed opaque through lro_receive_frags() */
2149 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2150
2151 /* find the mac header, aborting if not IPv4 */
2152
2153 eh = (struct ethhdr *)va;
2154 *mac_hdr = eh;
2155 ll_hlen = ETH_HLEN;
2156 if (eh->h_proto != htons(ETH_P_IP)) {
2157 if (eh->h_proto == htons(ETH_P_8021Q)) {
2158 veh = (struct vlan_ethhdr *)va;
2159 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2160 return -1;
2161
2162 ll_hlen += VLAN_HLEN;
2163
2164 /*
2165 * HW checksum starts ETH_HLEN bytes into
2166 * frame, so we must subtract off the VLAN
2167 * header's checksum before csum can be used
2168 */
2169 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2170 VLAN_HLEN, 0));
2171 } else {
2172 return -1;
2173 }
2174 }
2175 *hdr_flags = LRO_IPV4;
2176
2177 iph = (struct iphdr *)(va + ll_hlen);
2178 *ip_hdr = iph;
2179 if (iph->protocol != IPPROTO_TCP)
2180 return -1;
2181 *hdr_flags |= LRO_TCP;
2182 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2183
2184 /* verify the IP checksum */
2185 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2186 return -1;
2187
2188 /* verify the checksum */
2189 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2190 ntohs(iph->tot_len) - (iph->ihl << 2),
2191 IPPROTO_TCP, csum)))
2192 return -1;
2193
2194 return 0;
2195}
2196
77929732
BG		 2197static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2198{
2199 struct myri10ge_cmd cmd;
2200 struct myri10ge_slice_state *ss;
2201 int status;
2202
2203 ss = &mgp->ss[slice];
2204 cmd.data0 = 0; /* single slice for now */
2205 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
2206 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2207 (mgp->sram + cmd.data0);
2208
2209 cmd.data0 = slice;
2210 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2211 &cmd, 0);
2212 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2213 (mgp->sram + cmd.data0);
2214
2215 cmd.data0 = slice;
2216 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2217 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2218 (mgp->sram + cmd.data0);
2219
77929732
BG		 2220 return status;
2221
2222}
2223
2224static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2225{
2226 struct myri10ge_cmd cmd;
2227 struct myri10ge_slice_state *ss;
2228 int status;
2229
2230 ss = &mgp->ss[slice];
2231 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2232 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2233 cmd.data2 = sizeof(struct mcp_irq_data);
2234 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2235 if (status == -ENOSYS) {
2236 dma_addr_t bus = ss->fw_stats_bus;
2237 if (slice != 0)
2238 return -EINVAL;
2239 bus += offsetof(struct mcp_irq_data, send_done_count);
2240 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2241 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2242 status = myri10ge_send_cmd(mgp,
2243 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2244 &cmd, 0);
2245 /* Firmware cannot support multicast without STATS_DMA_V2 */
2246 mgp->fw_multicast_support = 0;
2247 } else {
2248 mgp->fw_multicast_support = 1;
2249 }
2250 return 0;
2251}
77929732 2252
0da34b6d
BG		 2253static int myri10ge_open(struct net_device *dev)
2254{
0dcffac1 2255 struct myri10ge_slice_state *ss;
b53bef84 2256 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2257 struct myri10ge_cmd cmd;
0dcffac1
BG		 2258 int i, status, big_pow2, slice;
2259 u8 *itable;
1e6e9342 2260 struct net_lro_mgr *lro_mgr;
0da34b6d 2261
0da34b6d
BG		 2262 if (mgp->running != MYRI10GE_ETH_STOPPED)
2263 return -EBUSY;
2264
2265 mgp->running = MYRI10GE_ETH_STARTING;
2266 status = myri10ge_reset(mgp);
2267 if (status != 0) {
2268 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 2269 goto abort_with_nothing;
0da34b6d
BG		 2270 }
2271
0dcffac1
BG		 2272 if (mgp->num_slices > 1) {
2273 cmd.data0 = mgp->num_slices;
2274 cmd.data1 = 1; /* use MSI-X */
2275 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2276 &cmd, 0);
2277 if (status != 0) {
2278 printk(KERN_ERR
2279 "myri10ge: %s: failed to set number of slices\n",
2280 dev->name);
2281 goto abort_with_nothing;
2282 }
2283 /* setup the indirection table */
2284 cmd.data0 = mgp->num_slices;
2285 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2286 &cmd, 0);
2287
2288 status |= myri10ge_send_cmd(mgp,
2289 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2290 &cmd, 0);
2291 if (status != 0) {
2292 printk(KERN_ERR
2293 "myri10ge: %s: failed to setup rss tables\n",
2294 dev->name);
2295 }
2296
2297 /* just enable an identity mapping */
2298 itable = mgp->sram + cmd.data0;
2299 for (i = 0; i < mgp->num_slices; i++)
2300 __raw_writeb(i, &itable[i]);
2301
2302 cmd.data0 = 1;
2303 cmd.data1 = myri10ge_rss_hash;
2304 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2305 &cmd, 0);
2306 if (status != 0) {
2307 printk(KERN_ERR
2308 "myri10ge: %s: failed to enable slices\n",
2309 dev->name);
2310 goto abort_with_nothing;
2311 }
2312 }
2313
df30a740
BG		 2314 status = myri10ge_request_irq(mgp);
2315 if (status != 0)
2316 goto abort_with_nothing;
2317
0da34b6d
BG		 2318 /* decide what small buffer size to use. For good TCP rx
2319 * performance, it is important to not receive 1514 byte
2320 * frames into jumbo buffers, as it confuses the socket buffer
2321 * accounting code, leading to drops and erratic performance.
2322 */
2323
2324 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2325 /* enough for a TCP header */
2326 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2327 ? (128 - MXGEFW_PAD)
2328 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2329 else
de3c4507
BG		 2330 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2331 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2332
2333 /* Override the small buffer size? */
2334 if (myri10ge_small_bytes > 0)
2335 mgp->small_bytes = myri10ge_small_bytes;
2336
0da34b6d
BG		 2337 /* Firmware needs the big buff size as a power of 2. Lie and
2338 * tell him the buffer is larger, because we only use 1
2339 * buffer/pkt, and the mtu will prevent overruns.
2340 */
13348bee 2341 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2342 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2343 while (!is_power_of_2(big_pow2))
c7dab99b 2344 big_pow2++;
13348bee 2345 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2346 } else {
2347 big_pow2 = MYRI10GE_ALLOC_SIZE;
2348 mgp->big_bytes = big_pow2;
2349 }
2350
0dcffac1
BG		 2351 /* setup the per-slice data structures */
2352 for (slice = 0; slice < mgp->num_slices; slice++) {
2353 ss = &mgp->ss[slice];
2354
2355 status = myri10ge_get_txrx(mgp, slice);
2356 if (status != 0) {
2357 printk(KERN_ERR
2358 "myri10ge: %s: failed to get ring sizes or locations\n",
2359 dev->name);
2360 goto abort_with_rings;
2361 }
2362 status = myri10ge_allocate_rings(ss);
2363 if (status != 0)
2364 goto abort_with_rings;
2365 if (slice == 0)
2366 status = myri10ge_set_stats(mgp, slice);
2367 if (status) {
2368 printk(KERN_ERR
2369 "myri10ge: %s: Couldn't set stats DMA\n",
2370 dev->name);
2371 goto abort_with_rings;
2372 }
2373
2374 lro_mgr = &ss->rx_done.lro_mgr;
2375 lro_mgr->dev = dev;
2376 lro_mgr->features = LRO_F_NAPI;
2377 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2378 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2379 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2380 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2381 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2382 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2383 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2384 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2385
2386 /* must happen prior to any irq */
2387 napi_enable(&(ss)->napi);
2388 }
0da34b6d
BG		 2389
2390 /* now give firmware buffers sizes, and MTU */
2391 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2392 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2393 cmd.data0 = mgp->small_bytes;
2394 status |=
2395 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2396 cmd.data0 = big_pow2;
2397 status |=
2398 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2399 if (status) {
2400 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2401 dev->name);
2402 goto abort_with_rings;
2403 }
2404
0dcffac1
BG		 2405 /*
2406 * Set Linux style TSO mode; this is needed only on newer
2407 * firmware versions. Older versions default to Linux
2408 * style TSO
2409 */
2410 cmd.data0 = 0;
2411 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2412 if (status && status != -ENOSYS) {
2413 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
0da34b6d
BG		 2414 dev->name);
2415 goto abort_with_rings;
2416 }
2417
66341fff 2418 mgp->link_state = ~0U;
0da34b6d
BG		 2419 mgp->rdma_tags_available = 15;
2420
0da34b6d
BG		 2421 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2422 if (status) {
2423 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2424 dev->name);
2425 goto abort_with_rings;
2426 }
2427
0da34b6d
BG		 2428 mgp->running = MYRI10GE_ETH_RUNNING;
2429 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2430 add_timer(&mgp->watchdog_timer);
2431 netif_wake_queue(dev);
2432 return 0;
2433
2434abort_with_rings:
0dcffac1
BG		 2435 for (i = 0; i < mgp->num_slices; i++)
2436 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2437
df30a740
BG		 2438 myri10ge_free_irq(mgp);
2439
0da34b6d
BG		 2440abort_with_nothing:
2441 mgp->running = MYRI10GE_ETH_STOPPED;
2442 return -ENOMEM;
2443}
2444
2445static int myri10ge_close(struct net_device *dev)
2446{
b53bef84 2447 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2448 struct myri10ge_cmd cmd;
2449 int status, old_down_cnt;
0dcffac1 2450 int i;
0da34b6d 2451
0da34b6d
BG		 2452 if (mgp->running != MYRI10GE_ETH_RUNNING)
2453 return 0;
2454
0dcffac1 2455 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2456 return 0;
2457
2458 del_timer_sync(&mgp->watchdog_timer);
2459 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2460 for (i = 0; i < mgp->num_slices; i++) {
2461 napi_disable(&mgp->ss[i].napi);
2462 }
0da34b6d
BG		 2463 netif_carrier_off(dev);
2464 netif_stop_queue(dev);
2465 old_down_cnt = mgp->down_cnt;
2466 mb();
2467 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2468 if (status)
2469 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2470 dev->name);
2471
2472 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2473 if (old_down_cnt == mgp->down_cnt)
2474 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2475
2476 netif_tx_disable(dev);
df30a740 2477 myri10ge_free_irq(mgp);
0dcffac1
BG		 2478 for (i = 0; i < mgp->num_slices; i++)
2479 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2480
2481 mgp->running = MYRI10GE_ETH_STOPPED;
2482 return 0;
2483}
2484
2485/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2486 * backwards one at a time and handle ring wraps */
2487
2488static inline void
2489myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2490 struct mcp_kreq_ether_send *src, int cnt)
2491{
2492 int idx, starting_slot;
2493 starting_slot = tx->req;
2494 while (cnt > 1) {
2495 cnt--;
2496 idx = (starting_slot + cnt) & tx->mask;
2497 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2498 mb();
2499 }
2500}
2501
2502/*
2503 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2504 * at most 32 bytes at a time, so as to avoid involving the software
2505 * pio handler in the nic. We re-write the first segment's flags
2506 * to mark them valid only after writing the entire chain.
2507 */
2508
2509static inline void
2510myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2511 int cnt)
2512{
2513 int idx, i;
2514 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2515 struct mcp_kreq_ether_send *srcp;
2516 u8 last_flags;
2517
2518 idx = tx->req & tx->mask;
2519
2520 last_flags = src->flags;
2521 src->flags = 0;
2522 mb();
2523 dst = dstp = &tx->lanai[idx];
2524 srcp = src;
2525
2526 if ((idx + cnt) < tx->mask) {
2527 for (i = 0; i < (cnt - 1); i += 2) {
2528 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2529 mb(); /* force write every 32 bytes */
2530 srcp += 2;
2531 dstp += 2;
2532 }
2533 } else {
2534 /* submit all but the first request, and ensure
2535 * that it is submitted below */
2536 myri10ge_submit_req_backwards(tx, src, cnt);
2537 i = 0;
2538 }
2539 if (i < cnt) {
2540 /* submit the first request */
2541 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2542 mb(); /* barrier before setting valid flag */
2543 }
2544
2545 /* re-write the last 32-bits with the valid flags */
2546 src->flags = last_flags;
40f6cff5 2547 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2548 tx->req += cnt;
2549 mb();
2550}
2551
0da34b6d
BG		 2552/*
2553 * Transmit a packet. We need to split the packet so that a single
b53bef84 2554 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2555 * counting tricky. So rather than try to count segments up front, we
2556 * just give up if there are too few segments to hold a reasonably
2557 * fragmented packet currently available. If we run
2558 * out of segments while preparing a packet for DMA, we just linearize
2559 * it and try again.
2560 */
2561
2562static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2563{
2564 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2565 struct myri10ge_slice_state *ss;
0da34b6d 2566 struct mcp_kreq_ether_send *req;
b53bef84 2567 struct myri10ge_tx_buf *tx;
0da34b6d
BG		 2568 struct skb_frag_struct *frag;
2569 dma_addr_t bus;
40f6cff5
AV		 2570 u32 low;
2571 __be32 high_swapped;
0da34b6d
BG		 2572 unsigned int len;
2573 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2574 u16 pseudo_hdr_offset, cksum_offset;
2575 int cum_len, seglen, boundary, rdma_count;
2576 u8 flags, odd_flag;
2577
b53bef84 2578 /* always transmit through slot 0 */
0dcffac1 2579 ss = mgp->ss;
b53bef84 2580 tx = &ss->tx;
0da34b6d
BG		 2581again:
2582 req = tx->req_list;
2583 avail = tx->mask - 1 - (tx->req - tx->done);
2584
2585 mss = 0;
2586 max_segments = MXGEFW_MAX_SEND_DESC;
2587
917690cd 2588 if (skb_is_gso(skb)) {
7967168c 2589 mss = skb_shinfo(skb)->gso_size;
917690cd 2590 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2591 }
0da34b6d
BG		 2592
2593 if ((unlikely(avail < max_segments))) {
2594 /* we are out of transmit resources */
b53bef84 2595 tx->stop_queue++;
0da34b6d
BG		 2596 netif_stop_queue(dev);
2597 return 1;
2598 }
2599
2600 /* Setup checksum offloading, if needed */
2601 cksum_offset = 0;
2602 pseudo_hdr_offset = 0;
2603 odd_flag = 0;
2604 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2605 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2606 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2607 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2608 /* If the headers are excessively large, then we must
2609 * fall back to a software checksum */
4f93fde0
BG		 2610 if (unlikely(!mss && (cksum_offset > 255 ||
2611 pseudo_hdr_offset > 127))) {
84fa7933 2612 if (skb_checksum_help(skb))
0da34b6d
BG		 2613 goto drop;
2614 cksum_offset = 0;
2615 pseudo_hdr_offset = 0;
2616 } else {
0da34b6d
BG		 2617 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2618 flags |= MXGEFW_FLAGS_CKSUM;
2619 }
2620 }
2621
2622 cum_len = 0;
2623
0da34b6d
BG		 2624 if (mss) { /* TSO */
2625 /* this removes any CKSUM flag from before */
2626 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2627
2628 /* negative cum_len signifies to the
2629 * send loop that we are still in the
2630 * header portion of the TSO packet.
4f93fde0 2631 * TSO header can be at most 1KB long */
ab6a5bb6 2632 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2633
4f93fde0
BG		 2634 /* for IPv6 TSO, the checksum offset stores the
2635 * TCP header length, to save the firmware from
2636 * the need to parse the headers */
2637 if (skb_is_gso_v6(skb)) {
2638 cksum_offset = tcp_hdrlen(skb);
2639 /* Can only handle headers <= max_tso6 long */
2640 if (unlikely(-cum_len > mgp->max_tso6))
2641 return myri10ge_sw_tso(skb, dev);
2642 }
0da34b6d
BG		 2643 /* for TSO, pseudo_hdr_offset holds mss.
2644 * The firmware figures out where to put
2645 * the checksum by parsing the header. */
40f6cff5 2646 pseudo_hdr_offset = mss;
0da34b6d 2647 } else
0da34b6d
BG		 2648 /* Mark small packets, and pad out tiny packets */
2649 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2650 flags |= MXGEFW_FLAGS_SMALL;
2651
2652 /* pad frames to at least ETH_ZLEN bytes */
2653 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2654 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2655 /* The packet is gone, so we must
2656 * return 0 */
b53bef84 2657 ss->stats.tx_dropped += 1;
0da34b6d
BG		 2658 return 0;
2659 }
2660 /* adjust the len to account for the zero pad
2661 * so that the nic can know how long it is */
2662 skb->len = ETH_ZLEN;
2663 }
2664 }
2665
2666 /* map the skb for DMA */
2667 len = skb->len - skb->data_len;
2668 idx = tx->req & tx->mask;
2669 tx->info[idx].skb = skb;
2670 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2671 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2672 pci_unmap_len_set(&tx->info[idx], len, len);
2673
2674 frag_cnt = skb_shinfo(skb)->nr_frags;
2675 frag_idx = 0;
2676 count = 0;
2677 rdma_count = 0;
2678
2679 /* "rdma_count" is the number of RDMAs belonging to the
2680 * current packet BEFORE the current send request. For
2681 * non-TSO packets, this is equal to "count".
2682 * For TSO packets, rdma_count needs to be reset
2683 * to 0 after a segment cut.
2684 *
2685 * The rdma_count field of the send request is
2686 * the number of RDMAs of the packet starting at
2687 * that request. For TSO send requests with one ore more cuts
2688 * in the middle, this is the number of RDMAs starting
2689 * after the last cut in the request. All previous
2690 * segments before the last cut implicitly have 1 RDMA.
2691 *
2692 * Since the number of RDMAs is not known beforehand,
2693 * it must be filled-in retroactively - after each
2694 * segmentation cut or at the end of the entire packet.
2695 */
2696
2697 while (1) {
2698 /* Break the SKB or Fragment up into pieces which
b53bef84 2699 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2700 low = MYRI10GE_LOWPART_TO_U32(bus);
2701 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2702 while (len) {
2703 u8 flags_next;
2704 int cum_len_next;
2705
2706 if (unlikely(count == max_segments))
2707 goto abort_linearize;
2708
b53bef84
BG		 2709 boundary =
2710 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2711 seglen = boundary - low;
2712 if (seglen > len)
2713 seglen = len;
2714 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2715 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2716 if (mss) { /* TSO */
2717 (req - rdma_count)->rdma_count = rdma_count + 1;
2718
2719 if (likely(cum_len >= 0)) { /* payload */
2720 int next_is_first, chop;
2721
2722 chop = (cum_len_next > mss);
2723 cum_len_next = cum_len_next % mss;
2724 next_is_first = (cum_len_next == 0);
2725 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2726 flags_next |= next_is_first *
2727 MXGEFW_FLAGS_FIRST;
2728 rdma_count |= -(chop | next_is_first);
2729 rdma_count += chop & !next_is_first;
2730 } else if (likely(cum_len_next >= 0)) { /* header ends */
2731 int small;
2732
2733 rdma_count = -1;
2734 cum_len_next = 0;
2735 seglen = -cum_len;
2736 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2737 flags_next = MXGEFW_FLAGS_TSO_PLD |
2738 MXGEFW_FLAGS_FIRST |
2739 (small * MXGEFW_FLAGS_SMALL);
2740 }
2741 }
0da34b6d
BG		 2742 req->addr_high = high_swapped;
2743 req->addr_low = htonl(low);
40f6cff5 2744 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2745 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2746 req->rdma_count = 1;
2747 req->length = htons(seglen);
2748 req->cksum_offset = cksum_offset;
2749 req->flags = flags | ((cum_len & 1) * odd_flag);
2750
2751 low += seglen;
2752 len -= seglen;
2753 cum_len = cum_len_next;
2754 flags = flags_next;
2755 req++;
2756 count++;
2757 rdma_count++;
4f93fde0
BG		 2758 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2759 if (unlikely(cksum_offset > seglen))
2760 cksum_offset -= seglen;
2761 else
2762 cksum_offset = 0;
2763 }
0da34b6d
BG		 2764 }
2765 if (frag_idx == frag_cnt)
2766 break;
2767
2768 /* map next fragment for DMA */
2769 idx = (count + tx->req) & tx->mask;
2770 frag = &skb_shinfo(skb)->frags[frag_idx];
2771 frag_idx++;
2772 len = frag->size;
2773 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2774 len, PCI_DMA_TODEVICE);
2775 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2776 pci_unmap_len_set(&tx->info[idx], len, len);
2777 }
2778
2779 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2780 if (mss)
2781 do {
2782 req--;
2783 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2784 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2785 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2786 idx = ((count - 1) + tx->req) & tx->mask;
2787 tx->info[idx].last = 1;
e454e7e2 2788 myri10ge_submit_req(tx, tx->req_list, count);
0da34b6d
BG		 2789 tx->pkt_start++;
2790 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2791 tx->stop_queue++;
0da34b6d
BG		 2792 netif_stop_queue(dev);
2793 }
2794 dev->trans_start = jiffies;
2795 return 0;
2796
2797abort_linearize:
2798 /* Free any DMA resources we've alloced and clear out the skb
2799 * slot so as to not trip up assertions, and to avoid a
2800 * double-free if linearizing fails */
2801
2802 last_idx = (idx + 1) & tx->mask;
2803 idx = tx->req & tx->mask;
2804 tx->info[idx].skb = NULL;
2805 do {
2806 len = pci_unmap_len(&tx->info[idx], len);
2807 if (len) {
2808 if (tx->info[idx].skb != NULL)
2809 pci_unmap_single(mgp->pdev,
2810 pci_unmap_addr(&tx->info[idx],
2811 bus), len,
2812 PCI_DMA_TODEVICE);
2813 else
2814 pci_unmap_page(mgp->pdev,
2815 pci_unmap_addr(&tx->info[idx],
2816 bus), len,
2817 PCI_DMA_TODEVICE);
2818 pci_unmap_len_set(&tx->info[idx], len, 0);
2819 tx->info[idx].skb = NULL;
2820 }
2821 idx = (idx + 1) & tx->mask;
2822 } while (idx != last_idx);
89114afd 2823 if (skb_is_gso(skb)) {
0da34b6d
BG		 2824 printk(KERN_ERR
2825 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2826 mgp->dev->name);
2827 goto drop;
2828 }
2829
bec0e859 2830 if (skb_linearize(skb))
0da34b6d
BG		 2831 goto drop;
2832
b53bef84 2833 tx->linearized++;
0da34b6d
BG		 2834 goto again;
2835
2836drop:
2837 dev_kfree_skb_any(skb);
b53bef84 2838 ss->stats.tx_dropped += 1;
0da34b6d
BG		 2839 return 0;
2840
2841}
2842
4f93fde0
BG		 2843static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2844{
2845 struct sk_buff *segs, *curr;
b53bef84 2846 struct myri10ge_priv *mgp = netdev_priv(dev);
4f93fde0
BG		 2847 int status;
2848
2849 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2850 if (IS_ERR(segs))
4f93fde0
BG		 2851 goto drop;
2852
2853 while (segs) {
2854 curr = segs;
2855 segs = segs->next;
2856 curr->next = NULL;
2857 status = myri10ge_xmit(curr, dev);
2858 if (status != 0) {
2859 dev_kfree_skb_any(curr);
2860 if (segs != NULL) {
2861 curr = segs;
2862 segs = segs->next;
2863 curr->next = NULL;
2864 dev_kfree_skb_any(segs);
2865 }
2866 goto drop;
2867 }
2868 }
2869 dev_kfree_skb_any(skb);
2870 return 0;
2871
2872drop:
2873 dev_kfree_skb_any(skb);
2874 mgp->stats.tx_dropped += 1;
2875 return 0;
2876}
2877
0da34b6d
BG		 2878static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2879{
2880 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1
BG		 2881 struct myri10ge_slice_netstats *slice_stats;
2882 struct net_device_stats *stats = &mgp->stats;
2883 int i;
2884
2885 memset(stats, 0, sizeof(*stats));
2886 for (i = 0; i < mgp->num_slices; i++) {
2887 slice_stats = &mgp->ss[i].stats;
2888 stats->rx_packets += slice_stats->rx_packets;
2889 stats->tx_packets += slice_stats->tx_packets;
2890 stats->rx_bytes += slice_stats->rx_bytes;
2891 stats->tx_bytes += slice_stats->tx_bytes;
2892 stats->rx_dropped += slice_stats->rx_dropped;
2893 stats->tx_dropped += slice_stats->tx_dropped;
2894 }
2895 return stats;
0da34b6d
BG		 2896}
2897
2898static void myri10ge_set_multicast_list(struct net_device *dev)
2899{
b53bef84 2900 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 2901 struct myri10ge_cmd cmd;
85a7ea1b 2902 struct dev_mc_list *mc_list;
6250223e 2903 __be32 data[2] = { 0, 0 };
85a7ea1b 2904 int err;
0795af57 2905 DECLARE_MAC_BUF(mac);
85a7ea1b 2906
0da34b6d
BG		 2907 /* can be called from atomic contexts,
2908 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2909 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2910
2911 /* This firmware is known to not support multicast */
2f76216f 2912 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2913 return;
2914
2915 /* Disable multicast filtering */
2916
2917 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2918 if (err != 0) {
2919 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2920 " error status: %d\n", dev->name, err);
2921 goto abort;
2922 }
2923
2f76216f 2924 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2925 /* request to disable multicast filtering, so quit here */
2926 return;
2927 }
2928
2929 /* Flush the filters */
2930
2931 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2932 &cmd, 1);
2933 if (err != 0) {
2934 printk(KERN_ERR
2935 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2936 ", error status: %d\n", dev->name, err);
2937 goto abort;
2938 }
2939
2940 /* Walk the multicast list, and add each address */
2941 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2942 memcpy(data, &mc_list->dmi_addr, 6);
2943 cmd.data0 = ntohl(data[0]);
2944 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2945 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2946 &cmd, 1);
2947
2948 if (err != 0) {
2949 printk(KERN_ERR "myri10ge: %s: Failed "
2950 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2951 "%d\t", dev->name, err);
0795af57
JP		 2952 printk(KERN_ERR "MAC %s\n",
2953 print_mac(mac, mc_list->dmi_addr));
85a7ea1b
BG		 2954 goto abort;
2955 }
2956 }
2957 /* Enable multicast filtering */
2958 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2959 if (err != 0) {
2960 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2961 "error status: %d\n", dev->name, err);
2962 goto abort;
2963 }
2964
2965 return;
2966
2967abort:
2968 return;
0da34b6d
BG		 2969}
2970
2971static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2972{
2973 struct sockaddr *sa = addr;
2974 struct myri10ge_priv *mgp = netdev_priv(dev);
2975 int status;
2976
2977 if (!is_valid_ether_addr(sa->sa_data))
2978 return -EADDRNOTAVAIL;
2979
2980 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2981 if (status != 0) {
2982 printk(KERN_ERR
2983 "myri10ge: %s: changing mac address failed with %d\n",
2984 dev->name, status);
2985 return status;
2986 }
2987
2988 /* change the dev structure */
2989 memcpy(dev->dev_addr, sa->sa_data, 6);
2990 return 0;
2991}
2992
2993static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2994{
2995 struct myri10ge_priv *mgp = netdev_priv(dev);
2996 int error = 0;
2997
2998 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2999 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3000 dev->name, new_mtu);
3001 return -EINVAL;
3002 }
3003 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3004 dev->name, dev->mtu, new_mtu);
3005 if (mgp->running) {
3006 /* if we change the mtu on an active device, we must
3007 * reset the device so the firmware sees the change */
3008 myri10ge_close(dev);
3009 dev->mtu = new_mtu;
3010 myri10ge_open(dev);
3011 } else
3012 dev->mtu = new_mtu;
3013
3014 return error;
3015}
3016
3017/*
3018 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3019 * Only do it if the bridge is a root port since we don't want to disturb
3020 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3021 */
3022
0da34b6d
BG		 3023static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3024{
3025 struct pci_dev *bridge = mgp->pdev->bus->self;
3026 struct device *dev = &mgp->pdev->dev;
3027 unsigned cap;
3028 unsigned err_cap;
3029 u16 val;
3030 u8 ext_type;
3031 int ret;
3032
3033 if (!myri10ge_ecrc_enable || !bridge)
3034 return;
3035
3036 /* check that the bridge is a root port */
3037 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3038 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3039 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3040 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3041 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3042 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3043
3044 /* Walk the hierarchy up to the root port
3045 * where ECRC has to be enabled */
3046 do {
eca3fd83 3047 prev_bridge = bridge;
0da34b6d 3048 bridge = bridge->bus->self;
eca3fd83 3049 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3050 dev_err(dev,
3051 "Failed to find root port"
3052 " to force ECRC\n");
3053 return;
3054 }
3055 cap =
3056 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3057 pci_read_config_word(bridge,
3058 cap + PCI_CAP_FLAGS, &val);
3059 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3060 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3061
3062 dev_info(dev,
3063 "Forcing ECRC on non-root port %s"
3064 " (enabling on root port %s)\n",
3065 pci_name(old_bridge), pci_name(bridge));
3066 } else {
3067 dev_err(dev,
3068 "Not enabling ECRC on non-root port %s\n",
3069 pci_name(bridge));
3070 return;
3071 }
3072 }
3073
3074 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3075 if (!cap)
3076 return;
3077
3078 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3079 if (ret) {
3080 dev_err(dev, "failed reading ext-conf-space of %s\n",
3081 pci_name(bridge));
3082 dev_err(dev, "\t pci=nommconf in use? "
3083 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3084 return;
3085 }
3086 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3087 return;
3088
3089 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3090 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3091 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3092}
3093
3094/*
3095 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3096 * when the PCI-E Completion packets are aligned on an 8-byte
3097 * boundary. Some PCI-E chip sets always align Completion packets; on
3098 * the ones that do not, the alignment can be enforced by enabling
3099 * ECRC generation (if supported).
3100 *
3101 * When PCI-E Completion packets are not aligned, it is actually more
3102 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3103 *
3104 * If the driver can neither enable ECRC nor verify that it has
3105 * already been enabled, then it must use a firmware image which works
0dcffac1 3106 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3107 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3108 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3109 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3110 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3111 */
3112
5443e9ea 3113static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3114{
5443e9ea
BG		 3115 struct pci_dev *pdev = mgp->pdev;
3116 struct device *dev = &pdev->dev;
302d242c 3117 int status;
0da34b6d 3118
b53bef84 3119 mgp->tx_boundary = 4096;
5443e9ea
BG		 3120 /*
3121 * Verify the max read request size was set to 4KB
3122 * before trying the test with 4KB.
3123 */
302d242c
BG		 3124 status = pcie_get_readrq(pdev);
3125 if (status < 0) {
5443e9ea
BG		 3126 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3127 goto abort;
3128 }
302d242c
BG		 3129 if (status != 4096) {
3130 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3131 mgp->tx_boundary = 2048;
5443e9ea
BG		 3132 }
3133 /*
3134 * load the optimized firmware (which assumes aligned PCIe
3135 * completions) in order to see if it works on this host.
3136 */
3137 mgp->fw_name = myri10ge_fw_aligned;
0dcffac1 3138 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3139 if (status != 0) {
3140 goto abort;
3141 }
3142
3143 /*
3144 * Enable ECRC if possible
3145 */
3146 myri10ge_enable_ecrc(mgp);
3147
3148 /*
3149 * Run a DMA test which watches for unaligned completions and
3150 * aborts on the first one seen.
3151 */
3152
3153 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3154 if (status == 0)
3155 return; /* keep the aligned firmware */
3156
3157 if (status != -E2BIG)
3158 dev_warn(dev, "DMA test failed: %d\n", status);
3159 if (status == -ENOSYS)
3160 dev_warn(dev, "Falling back to ethp! "
3161 "Please install up to date fw\n");
3162abort:
3163 /* fall back to using the unaligned firmware */
b53bef84 3164 mgp->tx_boundary = 2048;
0da34b6d
BG		 3165 mgp->fw_name = myri10ge_fw_unaligned;
3166
5443e9ea
BG		 3167}
3168
3169static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3170{
0da34b6d 3171 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3172 int link_width, exp_cap;
3173 u16 lnk;
3174
3175 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3176 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3177 link_width = (lnk >> 4) & 0x3f;
3178
ce7f9368
BG		 3179 /* Check to see if Link is less than 8 or if the
3180 * upstream bridge is known to provide aligned
3181 * completions */
3182 if (link_width < 8) {
3183 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3184 link_width);
b53bef84 3185 mgp->tx_boundary = 4096;
ce7f9368 3186 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 3187 } else {
3188 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3189 }
3190 } else {
3191 if (myri10ge_force_firmware == 1) {
3192 dev_info(&mgp->pdev->dev,
3193 "Assuming aligned completions (forced)\n");
b53bef84 3194 mgp->tx_boundary = 4096;
0da34b6d
BG		 3195 mgp->fw_name = myri10ge_fw_aligned;
3196 } else {
3197 dev_info(&mgp->pdev->dev,
3198 "Assuming unaligned completions (forced)\n");
b53bef84 3199 mgp->tx_boundary = 2048;
0da34b6d
BG		 3200 mgp->fw_name = myri10ge_fw_unaligned;
3201 }
3202 }
3203 if (myri10ge_fw_name != NULL) {
3204 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3205 myri10ge_fw_name);
3206 mgp->fw_name = myri10ge_fw_name;
3207 }
3208}
3209
0da34b6d 3210#ifdef CONFIG_PM
0da34b6d
BG		 3211static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3212{
3213 struct myri10ge_priv *mgp;
3214 struct net_device *netdev;
3215
3216 mgp = pci_get_drvdata(pdev);
3217 if (mgp == NULL)
3218 return -EINVAL;
3219 netdev = mgp->dev;
3220
3221 netif_device_detach(netdev);
3222 if (netif_running(netdev)) {
3223 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3224 rtnl_lock();
3225 myri10ge_close(netdev);
3226 rtnl_unlock();
3227 }
3228 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3229 pci_save_state(pdev);
0da34b6d 3230 pci_disable_device(pdev);
1a63e846
BG		 3231
3232 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3233}
3234
3235static int myri10ge_resume(struct pci_dev *pdev)
3236{
3237 struct myri10ge_priv *mgp;
3238 struct net_device *netdev;
3239 int status;
3240 u16 vendor;
3241
3242 mgp = pci_get_drvdata(pdev);
3243 if (mgp == NULL)
3244 return -EINVAL;
3245 netdev = mgp->dev;
3246 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3247 msleep(5); /* give card time to respond */
3248 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3249 if (vendor == 0xffff) {
3250 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3251 mgp->dev->name);
3252 return -EIO;
3253 }
83f6e152 3254
1a63e846
BG		 3255 status = pci_restore_state(pdev);
3256 if (status)
3257 return status;
4c2248cc
BG		 3258
3259 status = pci_enable_device(pdev);
1a63e846 3260 if (status) {
4c2248cc 3261 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3262 return status;
4c2248cc
BG		 3263 }
3264
0da34b6d
BG		 3265 pci_set_master(pdev);
3266
0da34b6d 3267 myri10ge_reset(mgp);
013b68bf 3268 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3269
3270 /* Save configuration space to be restored if the
3271 * nic resets due to a parity error */
83f6e152 3272 pci_save_state(pdev);
0da34b6d
BG		 3273
3274 if (netif_running(netdev)) {
3275 rtnl_lock();
df30a740 3276 status = myri10ge_open(netdev);
0da34b6d 3277 rtnl_unlock();
df30a740
BG		 3278 if (status != 0)
3279 goto abort_with_enabled;
3280
0da34b6d
BG		 3281 }
3282 netif_device_attach(netdev);
3283
3284 return 0;
3285
4c2248cc
BG		 3286abort_with_enabled:
3287 pci_disable_device(pdev);
0da34b6d
BG		 3288 return -EIO;
3289
3290}
0da34b6d
BG		 3291#endif /* CONFIG_PM */
3292
3293static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3294{
3295 struct pci_dev *pdev = mgp->pdev;
3296 int vs = mgp->vendor_specific_offset;
3297 u32 reboot;
3298
3299 /*enter read32 mode */
3300 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3301
3302 /*read REBOOT_STATUS (0xfffffff0) */
3303 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3304 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3305 return reboot;
3306}
3307
3308/*
3309 * This watchdog is used to check whether the board has suffered
3310 * from a parity error and needs to be recovered.
3311 */
c4028958 3312static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3313{
c4028958 3314 struct myri10ge_priv *mgp =
6250223e 3315 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3316 struct myri10ge_tx_buf *tx;
0da34b6d
BG		 3317 u32 reboot;
3318 int status;
0dcffac1 3319 int i;
0da34b6d
BG		 3320 u16 cmd, vendor;
3321
3322 mgp->watchdog_resets++;
3323 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3324 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3325 /* Bus master DMA disabled? Check to see
3326 * if the card rebooted due to a parity error
3327 * For now, just report it */
3328 reboot = myri10ge_read_reboot(mgp);
3329 printk(KERN_ERR
f181137f
BG		 3330 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3331 mgp->dev->name, reboot,
3332 myri10ge_reset_recover ? " " : " not");
3333 if (myri10ge_reset_recover == 0)
3334 return;
3335
3336 myri10ge_reset_recover--;
3337
0da34b6d
BG		 3338 /*
3339 * A rebooted nic will come back with config space as
3340 * it was after power was applied to PCIe bus.
3341 * Attempt to restore config space which was saved
3342 * when the driver was loaded, or the last time the
3343 * nic was resumed from power saving mode.
3344 */
83f6e152 3345 pci_restore_state(mgp->pdev);
7adda30c
BG		 3346
3347 /* save state again for accounting reasons */
83f6e152 3348 pci_save_state(mgp->pdev);
7adda30c 3349
0da34b6d
BG		 3350 } else {
3351 /* if we get back -1's from our slot, perhaps somebody
3352 * powered off our card. Don't try to reset it in
3353 * this case */
3354 if (cmd == 0xffff) {
3355 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3356 if (vendor == 0xffff) {
3357 printk(KERN_ERR
3358 "myri10ge: %s: device disappeared!\n",
3359 mgp->dev->name);
3360 return;
3361 }
3362 }
3363 /* Perhaps it is a software error. Try to reset */
3364
3365 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3366 mgp->dev->name);
0dcffac1
BG		 3367 for (i = 0; i < mgp->num_slices; i++) {
3368 tx = &mgp->ss[i].tx;
3369 printk(KERN_INFO
3370 "myri10ge: %s: (%d): %d %d %d %d %d\n",
3371 mgp->dev->name, i, tx->req, tx->done,
3372 tx->pkt_start, tx->pkt_done,
3373 (int)ntohl(mgp->ss[i].fw_stats->
3374 send_done_count));
3375 msleep(2000);
3376 printk(KERN_INFO
3377 "myri10ge: %s: (%d): %d %d %d %d %d\n",
3378 mgp->dev->name, i, tx->req, tx->done,
3379 tx->pkt_start, tx->pkt_done,
3380 (int)ntohl(mgp->ss[i].fw_stats->
3381 send_done_count));
3382 }
0da34b6d
BG		 3383 }
3384 rtnl_lock();
3385 myri10ge_close(mgp->dev);
0dcffac1 3386 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3387 if (status != 0)
3388 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3389 mgp->dev->name);
3390 else
3391 myri10ge_open(mgp->dev);
3392 rtnl_unlock();
3393}
3394
3395/*
3396 * We use our own timer routine rather than relying upon
3397 * netdev->tx_timeout because we have a very large hardware transmit
3398 * queue. Due to the large queue, the netdev->tx_timeout function
3399 * cannot detect a NIC with a parity error in a timely fashion if the
3400 * NIC is lightly loaded.
3401 */
3402static void myri10ge_watchdog_timer(unsigned long arg)
3403{
3404 struct myri10ge_priv *mgp;
b53bef84 3405 struct myri10ge_slice_state *ss;
0dcffac1 3406 int i, reset_needed;
626fda94 3407 u32 rx_pause_cnt;
0da34b6d
BG		 3408
3409 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3410
0dcffac1
BG		 3411 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3412 for (i = 0, reset_needed = 0;
3413 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3414
0dcffac1
BG		 3415 ss = &mgp->ss[i];
3416 if (ss->rx_small.watchdog_needed) {
3417 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3418 mgp->small_bytes + MXGEFW_PAD,
3419 1);
3420 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3421 myri10ge_fill_thresh)
3422 ss->rx_small.watchdog_needed = 0;
3423 }
3424 if (ss->rx_big.watchdog_needed) {
3425 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3426 mgp->big_bytes, 1);
3427 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3428 myri10ge_fill_thresh)
3429 ss->rx_big.watchdog_needed = 0;
3430 }
3431
3432 if (ss->tx.req != ss->tx.done &&
3433 ss->tx.done == ss->watchdog_tx_done &&
3434 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3435 /* nic seems like it might be stuck.. */
3436 if (rx_pause_cnt != mgp->watchdog_pause) {
3437 if (net_ratelimit())
3438 printk(KERN_WARNING "myri10ge %s:"
3439 "TX paused, check link partner\n",
3440 mgp->dev->name);
3441 } else {
3442 reset_needed = 1;
3443 }
626fda94 3444 }
0dcffac1
BG		 3445 ss->watchdog_tx_done = ss->tx.done;
3446 ss->watchdog_tx_req = ss->tx.req;
626fda94 3447 }
626fda94 3448 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3449
3450 if (reset_needed) {
3451 schedule_work(&mgp->watchdog_work);
3452 } else {
3453 /* rearm timer */
3454 mod_timer(&mgp->watchdog_timer,
3455 jiffies + myri10ge_watchdog_timeout * HZ);
3456 }
0da34b6d
BG		 3457}
3458
77929732
BG		 3459static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3460{
3461 struct myri10ge_slice_state *ss;
3462 struct pci_dev *pdev = mgp->pdev;
3463 size_t bytes;
3464 int i;
3465
3466 if (mgp->ss == NULL)
3467 return;
3468
3469 for (i = 0; i < mgp->num_slices; i++) {
3470 ss = &mgp->ss[i];
3471 if (ss->rx_done.entry != NULL) {
3472 bytes = mgp->max_intr_slots *
3473 sizeof(*ss->rx_done.entry);
3474 dma_free_coherent(&pdev->dev, bytes,
3475 ss->rx_done.entry, ss->rx_done.bus);
3476 ss->rx_done.entry = NULL;
3477 }
3478 if (ss->fw_stats != NULL) {
3479 bytes = sizeof(*ss->fw_stats);
3480 dma_free_coherent(&pdev->dev, bytes,
3481 ss->fw_stats, ss->fw_stats_bus);
3482 ss->fw_stats = NULL;
3483 }
3484 }
3485 kfree(mgp->ss);
3486 mgp->ss = NULL;
3487}
3488
3489static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3490{
3491 struct myri10ge_slice_state *ss;
3492 struct pci_dev *pdev = mgp->pdev;
3493 size_t bytes;
3494 int i;
3495
3496 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3497 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3498 if (mgp->ss == NULL) {
3499 return -ENOMEM;
3500 }
3501
3502 for (i = 0; i < mgp->num_slices; i++) {
3503 ss = &mgp->ss[i];
3504 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3505 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3506 &ss->rx_done.bus,
3507 GFP_KERNEL);
3508 if (ss->rx_done.entry == NULL)
3509 goto abort;
3510 memset(ss->rx_done.entry, 0, bytes);
3511 bytes = sizeof(*ss->fw_stats);
3512 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3513 &ss->fw_stats_bus,
3514 GFP_KERNEL);
3515 if (ss->fw_stats == NULL)
3516 goto abort;
3517 ss->mgp = mgp;
3518 ss->dev = mgp->dev;
3519 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3520 myri10ge_napi_weight);
3521 }
3522 return 0;
3523abort:
3524 myri10ge_free_slices(mgp);
3525 return -ENOMEM;
3526}
3527
3528/*
3529 * This function determines the number of slices supported.
3530 * The number slices is the minumum of the number of CPUS,
3531 * the number of MSI-X irqs supported, the number of slices
3532 * supported by the firmware
3533 */
3534static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3535{
3536 struct myri10ge_cmd cmd;
3537 struct pci_dev *pdev = mgp->pdev;
3538 char *old_fw;
3539 int i, status, ncpus, msix_cap;
3540
3541 mgp->num_slices = 1;
3542 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3543 ncpus = num_online_cpus();
3544
3545 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3546 (myri10ge_max_slices == -1 && ncpus < 2))
3547 return;
3548
3549 /* try to load the slice aware rss firmware */
3550 old_fw = mgp->fw_name;
13b2738c
BG		 3551 if (myri10ge_fw_name != NULL) {
3552 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3553 myri10ge_fw_name);
3554 mgp->fw_name = myri10ge_fw_name;
3555 } else if (old_fw == myri10ge_fw_aligned)
77929732
BG		 3556 mgp->fw_name = myri10ge_fw_rss_aligned;
3557 else
3558 mgp->fw_name = myri10ge_fw_rss_unaligned;
3559 status = myri10ge_load_firmware(mgp, 0);
3560 if (status != 0) {
3561 dev_info(&pdev->dev, "Rss firmware not found\n");
3562 return;
3563 }
3564
3565 /* hit the board with a reset to ensure it is alive */
3566 memset(&cmd, 0, sizeof(cmd));
3567 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3568 if (status != 0) {
3569 dev_err(&mgp->pdev->dev, "failed reset\n");
3570 goto abort_with_fw;
3571 return;
3572 }
3573
3574 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3575
3576 /* tell it the size of the interrupt queues */
3577 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3578 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3579 if (status != 0) {
3580 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3581 goto abort_with_fw;
3582 }
3583
3584 /* ask the maximum number of slices it supports */
3585 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3586 if (status != 0)
3587 goto abort_with_fw;
3588 else
3589 mgp->num_slices = cmd.data0;
3590
3591 /* Only allow multiple slices if MSI-X is usable */
3592 if (!myri10ge_msi) {
3593 goto abort_with_fw;
3594 }
3595
3596 /* if the admin did not specify a limit to how many
3597 * slices we should use, cap it automatically to the
3598 * number of CPUs currently online */
3599 if (myri10ge_max_slices == -1)
3600 myri10ge_max_slices = ncpus;
3601
3602 if (mgp->num_slices > myri10ge_max_slices)
3603 mgp->num_slices = myri10ge_max_slices;
3604
3605 /* Now try to allocate as many MSI-X vectors as we have
3606 * slices. We give up on MSI-X if we can only get a single
3607 * vector. */
3608
3609 mgp->msix_vectors = kzalloc(mgp->num_slices *
3610 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3611 if (mgp->msix_vectors == NULL)
3612 goto disable_msix;
3613 for (i = 0; i < mgp->num_slices; i++) {
3614 mgp->msix_vectors[i].entry = i;
3615 }
3616
3617 while (mgp->num_slices > 1) {
3618 /* make sure it is a power of two */
3619 while (!is_power_of_2(mgp->num_slices))
3620 mgp->num_slices--;
3621 if (mgp->num_slices == 1)
3622 goto disable_msix;
3623 status = pci_enable_msix(pdev, mgp->msix_vectors,
3624 mgp->num_slices);
3625 if (status == 0) {
3626 pci_disable_msix(pdev);
3627 return;
3628 }
3629 if (status > 0)
3630 mgp->num_slices = status;
3631 else
3632 goto disable_msix;
3633 }
3634
3635disable_msix:
3636 if (mgp->msix_vectors != NULL) {
3637 kfree(mgp->msix_vectors);
3638 mgp->msix_vectors = NULL;
3639 }
3640
3641abort_with_fw:
3642 mgp->num_slices = 1;
3643 mgp->fw_name = old_fw;
3644 myri10ge_load_firmware(mgp, 0);
3645}
77929732 3646
0da34b6d
BG		 3647static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3648{
3649 struct net_device *netdev;
3650 struct myri10ge_priv *mgp;
3651 struct device *dev = &pdev->dev;
0da34b6d
BG		 3652 int i;
3653 int status = -ENXIO;
0da34b6d 3654 int dac_enabled;
0da34b6d
BG		 3655
3656 netdev = alloc_etherdev(sizeof(*mgp));
3657 if (netdev == NULL) {
3658 dev_err(dev, "Could not allocate ethernet device\n");
3659 return -ENOMEM;
3660 }
3661
b245fb67
MH		 3662 SET_NETDEV_DEV(netdev, &pdev->dev);
3663
0da34b6d 3664 mgp = netdev_priv(netdev);
0da34b6d
BG		 3665 mgp->dev = netdev;
3666 mgp->pdev = pdev;
3667 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3668 mgp->pause = myri10ge_flow_control;
3669 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3670 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 3671 init_waitqueue_head(&mgp->down_wq);
3672
3673 if (pci_enable_device(pdev)) {
3674 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3675 status = -ENODEV;
3676 goto abort_with_netdev;
3677 }
0da34b6d
BG		 3678
3679 /* Find the vendor-specific cap so we can check
3680 * the reboot register later on */
3681 mgp->vendor_specific_offset
3682 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3683
3684 /* Set our max read request to 4KB */
302d242c 3685 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3686 if (status != 0) {
3687 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3688 status);
3689 goto abort_with_netdev;
3690 }
3691
3692 pci_set_master(pdev);
3693 dac_enabled = 1;
3694 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3695 if (status != 0) {
3696 dac_enabled = 0;
3697 dev_err(&pdev->dev,
898eb71c
JP		 3698 "64-bit pci address mask was refused, "
3699 "trying 32-bit\n");
0da34b6d
BG		 3700 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3701 }
3702 if (status != 0) {
3703 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3704 goto abort_with_netdev;
3705 }
77970ea5 3706 (void)pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
b10c0668
BG		 3707 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3708 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 3709 if (mgp->cmd == NULL)
3710 goto abort_with_netdev;
3711
0da34b6d
BG		 3712 mgp->board_span = pci_resource_len(pdev, 0);
3713 mgp->iomem_base = pci_resource_start(pdev, 0);
3714 mgp->mtrr = -1;
276e26c3 3715 mgp->wc_enabled = 0;
0da34b6d
BG		 3716#ifdef CONFIG_MTRR
3717 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3718 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3719 if (mgp->mtrr >= 0)
3720 mgp->wc_enabled = 1;
0da34b6d
BG		 3721#endif
3722 /* Hack. need to get rid of these magic numbers */
3723 mgp->sram_size =
3724 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3725 if (mgp->sram_size > mgp->board_span) {
3726 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3727 mgp->board_span);
c7f80993 3728 goto abort_with_mtrr;
0da34b6d 3729 }
c7f80993 3730 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3731 if (mgp->sram == NULL) {
3732 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3733 mgp->board_span, mgp->iomem_base);
3734 status = -ENXIO;
c7f80993 3735 goto abort_with_mtrr;
0da34b6d
BG		 3736 }
3737 memcpy_fromio(mgp->eeprom_strings,
3738 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3739 MYRI10GE_EEPROM_STRINGS_SIZE);
3740 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3741 status = myri10ge_read_mac_addr(mgp);
3742 if (status)
3743 goto abort_with_ioremap;
3744
3745 for (i = 0; i < ETH_ALEN; i++)
3746 netdev->dev_addr[i] = mgp->mac_addr[i];
3747
5443e9ea
BG		 3748 myri10ge_select_firmware(mgp);
3749
0dcffac1 3750 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3751 if (status != 0) {
3752 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3753 goto abort_with_ioremap;
3754 }
3755 myri10ge_probe_slices(mgp);
3756 status = myri10ge_alloc_slices(mgp);
3757 if (status != 0) {
3758 dev_err(&pdev->dev, "failed to alloc slice state\n");
3759 goto abort_with_firmware;
0da34b6d
BG		 3760 }
3761
3762 status = myri10ge_reset(mgp);
3763 if (status != 0) {
3764 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3765 goto abort_with_slices;
0da34b6d 3766 }
ead7b940 3767#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 3768 myri10ge_setup_dca(mgp);
3769#endif
0da34b6d
BG		 3770 pci_set_drvdata(pdev, mgp);
3771 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3772 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3773 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3774 myri10ge_initial_mtu = 68;
3775 netdev->mtu = myri10ge_initial_mtu;
3776 netdev->open = myri10ge_open;
3777 netdev->stop = myri10ge_close;
3778 netdev->hard_start_xmit = myri10ge_xmit;
3779 netdev->get_stats = myri10ge_get_stats;
3780 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 3781 netdev->change_mtu = myri10ge_change_mtu;
3782 netdev->set_multicast_list = myri10ge_set_multicast_list;
3783 netdev->set_mac_address = myri10ge_set_mac_address;
4f93fde0 3784 netdev->features = mgp->features;
0da34b6d
BG		 3785 if (dac_enabled)
3786 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3787
21d05db1
BG		 3788 /* make sure we can get an irq, and that MSI can be
3789 * setup (if available). Also ensure netdev->irq
3790 * is set to correct value if MSI is enabled */
3791 status = myri10ge_request_irq(mgp);
3792 if (status != 0)
3793 goto abort_with_firmware;
3794 netdev->irq = pdev->irq;
3795 myri10ge_free_irq(mgp);
3796
0da34b6d
BG		 3797 /* Save configuration space to be restored if the
3798 * nic resets due to a parity error */
83f6e152 3799 pci_save_state(pdev);
0da34b6d
BG		 3800
3801 /* Setup the watchdog timer */
3802 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3803 (unsigned long)mgp);
3804
3805 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3806 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3807 status = register_netdev(netdev);
3808 if (status != 0) {
3809 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3810 goto abort_with_state;
0da34b6d 3811 }
0dcffac1
BG		 3812 if (mgp->msix_enabled)
3813 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3814 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3815 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3816 else
3817 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3818 mgp->msi_enabled ? "MSI" : "xPIC",
3819 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3820 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3821
3822 return 0;
3823
7adda30c 3824abort_with_state:
83f6e152 3825 pci_restore_state(pdev);
0da34b6d 3826
0dcffac1
BG		 3827abort_with_slices:
3828 myri10ge_free_slices(mgp);
3829
0da34b6d
BG		 3830abort_with_firmware:
3831 myri10ge_dummy_rdma(mgp, 0);
3832
0da34b6d
BG		 3833abort_with_ioremap:
3834 iounmap(mgp->sram);
3835
c7f80993 3836abort_with_mtrr:
0da34b6d
BG		 3837#ifdef CONFIG_MTRR
3838 if (mgp->mtrr >= 0)
3839 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3840#endif
b10c0668
BG		 3841 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3842 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3843
3844abort_with_netdev:
3845
3846 free_netdev(netdev);
3847 return status;
3848}
3849
3850/*
3851 * myri10ge_remove
3852 *
3853 * Does what is necessary to shutdown one Myrinet device. Called
3854 * once for each Myrinet card by the kernel when a module is
3855 * unloaded.
3856 */
3857static void myri10ge_remove(struct pci_dev *pdev)
3858{
3859 struct myri10ge_priv *mgp;
3860 struct net_device *netdev;
0da34b6d
BG		 3861
3862 mgp = pci_get_drvdata(pdev);
3863 if (mgp == NULL)
3864 return;
3865
3866 flush_scheduled_work();
3867 netdev = mgp->dev;
3868 unregister_netdev(netdev);
0da34b6d 3869
ead7b940 3870#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 3871 myri10ge_teardown_dca(mgp);
3872#endif
0da34b6d
BG		 3873 myri10ge_dummy_rdma(mgp, 0);
3874
7adda30c 3875 /* avoid a memory leak */
83f6e152 3876 pci_restore_state(pdev);
7adda30c 3877
0da34b6d
BG		 3878 iounmap(mgp->sram);
3879
3880#ifdef CONFIG_MTRR
3881 if (mgp->mtrr >= 0)
3882 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3883#endif
0dcffac1
BG		 3884 myri10ge_free_slices(mgp);
3885 if (mgp->msix_vectors != NULL)
3886 kfree(mgp->msix_vectors);
b10c0668
BG		 3887 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3888 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3889
3890 free_netdev(netdev);
3891 pci_set_drvdata(pdev, NULL);
3892}
3893
b10c0668 3894#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3895#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 3896
3897static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3898 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3899 {PCI_DEVICE
3900 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3901 {0},
3902};
3903
3904static struct pci_driver myri10ge_driver = {
3905 .name = "myri10ge",
3906 .probe = myri10ge_probe,
3907 .remove = myri10ge_remove,
3908 .id_table = myri10ge_pci_tbl,
3909#ifdef CONFIG_PM
3910 .suspend = myri10ge_suspend,
3911 .resume = myri10ge_resume,
3912#endif
3913};
3914
ead7b940 3915#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 3916static int
3917myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
3918{
3919 int err = driver_for_each_device(&myri10ge_driver.driver,
3920 NULL, &event,
3921 myri10ge_notify_dca_device);
3922
3923 if (err)
3924 return NOTIFY_BAD;
3925 return NOTIFY_DONE;
3926}
3927
3928static struct notifier_block myri10ge_dca_notifier = {
3929 .notifier_call = myri10ge_notify_dca,
3930 .next = NULL,
3931 .priority = 0,
3932};
3933#endif /* CONFIG_DCA */
3934
0da34b6d
BG		 3935static __init int myri10ge_init_module(void)
3936{
3937 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3938 MYRI10GE_VERSION_STR);
0dcffac1
BG		 3939
3940 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_SRC_PORT ||
3941 myri10ge_rss_hash < MXGEFW_RSS_HASH_TYPE_IPV4) {
3942 printk(KERN_ERR
3943 "%s: Illegal rssh hash type %d, defaulting to source port\n",
3944 myri10ge_driver.name, myri10ge_rss_hash);
3945 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
3946 }
ead7b940 3947#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 3948 dca_register_notify(&myri10ge_dca_notifier);
3949#endif
0dcffac1 3950
0da34b6d
BG		 3951 return pci_register_driver(&myri10ge_driver);
3952}
3953
3954module_init(myri10ge_init_module);
3955
3956static __exit void myri10ge_cleanup_module(void)
3957{
ead7b940 3958#if (defined CONFIG_DCA) || (defined CONFIG_DCA_MODULE)
981813d8
BG		 3959 dca_unregister_notify(&myri10ge_dca_notifier);
3960#endif
0da34b6d
BG		 3961 pci_unregister_driver(&myri10ge_driver);
3962}
3963
3964module_exit(myri10ge_cleanup_module);
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