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myri10ge: increase and fix handoff timeout
[mirror_ubuntu-artful-kernel.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
0da34b6d
BG		 52#include <linux/ip.h>
53#include <linux/inet.h>
54#include <linux/in.h>
55#include <linux/ethtool.h>
56#include <linux/firmware.h>
57#include <linux/delay.h>
58#include <linux/version.h>
59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
e0d7c526 78#define MYRI10GE_VERSION_STR "1.3.2-1.287"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
0da34b6d 105struct myri10ge_rx_buffer_state {
dd50f336
BG		 106 struct page *page;
107 int page_offset;
0da34b6d
BG		 108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110};
111
112struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117};
118
119struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123};
124
125struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 130 struct page *page;
131 dma_addr_t bus;
132 int page_offset;
0da34b6d 133 int cnt;
dd50f336 134 int fill_cnt;
0da34b6d
BG		 135 int alloc_fail;
136 int mask; /* number of rx slots -1 */
dd50f336 137 int watchdog_needed;
0da34b6d
BG		 138};
139
140struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
144 char *req_bytes;
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int boundary; /* boundary transmits cannot cross */
148 int req ____cacheline_aligned; /* transmit slots submitted */
149 int pkt_start; /* packets started */
150 int done ____cacheline_aligned; /* transmit slots completed */
151 int pkt_done; /* packets completed */
152};
153
154struct myri10ge_rx_done {
155 struct mcp_slot *entry;
156 dma_addr_t bus;
157 int cnt;
158 int idx;
1e6e9342
AG		 159 struct net_lro_mgr lro_mgr;
160 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 161};
162
163struct myri10ge_priv {
164 int running; /* running? */
165 int csum_flag; /* rx_csums? */
166 struct myri10ge_tx_buf tx; /* transmit ring */
167 struct myri10ge_rx_buf rx_small;
168 struct myri10ge_rx_buf rx_big;
169 struct myri10ge_rx_done rx_done;
170 int small_bytes;
dd50f336 171 int big_bytes;
0da34b6d 172 struct net_device *dev;
bea3348e 173 struct napi_struct napi;
0da34b6d
BG		 174 struct net_device_stats stats;
175 u8 __iomem *sram;
176 int sram_size;
177 unsigned long board_span;
178 unsigned long iomem_base;
40f6cff5
AV		 179 __be32 __iomem *irq_claim;
180 __be32 __iomem *irq_deassert;
0da34b6d
BG		 181 char *mac_addr_string;
182 struct mcp_cmd_response *cmd;
183 dma_addr_t cmd_bus;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 struct pci_dev *pdev;
187 int msi_enabled;
66341fff 188 u32 link_state;
0da34b6d
BG		 189 unsigned int rdma_tags_available;
190 int intr_coal_delay;
40f6cff5 191 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 192 int mtrr;
276e26c3 193 int wc_enabled;
0da34b6d
BG		 194 int wake_queue;
195 int stop_queue;
196 int down_cnt;
197 wait_queue_head_t down_wq;
198 struct work_struct watchdog_work;
199 struct timer_list watchdog_timer;
200 int watchdog_tx_done;
c54772e7 201 int watchdog_tx_req;
626fda94 202 int watchdog_pause;
0da34b6d
BG		 203 int watchdog_resets;
204 int tx_linearized;
205 int pause;
206 char *fw_name;
207 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
208 char fw_version[128];
9dc6f0e7
BG		 209 int fw_ver_major;
210 int fw_ver_minor;
211 int fw_ver_tiny;
212 int adopted_rx_filter_bug;
0da34b6d
BG		 213 u8 mac_addr[6]; /* eeprom mac address */
214 unsigned long serial_number;
215 int vendor_specific_offset;
85a7ea1b 216 int fw_multicast_support;
4f93fde0
BG		 217 unsigned long features;
218 u32 max_tso6;
0da34b6d
BG		 219 u32 read_dma;
220 u32 write_dma;
221 u32 read_write_dma;
c58ac5ca
BG		 222 u32 link_changes;
223 u32 msg_enable;
0da34b6d
BG		 224};
225
226static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
227static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
228
229static char *myri10ge_fw_name = NULL;
230module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 231MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d
BG		 232
233static int myri10ge_ecrc_enable = 1;
234module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 235MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d
BG		 236
237static int myri10ge_max_intr_slots = 1024;
238module_param(myri10ge_max_intr_slots, int, S_IRUGO);
d1ce3a0f 239MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots");
0da34b6d
BG		 240
241static int myri10ge_small_bytes = -1; /* -1 == auto */
242module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 243MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 244
245static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 246module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 247MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 248
f761fae1 249static int myri10ge_intr_coal_delay = 75;
0da34b6d 250module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 251MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 252
253static int myri10ge_flow_control = 1;
254module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 255MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 256
257static int myri10ge_deassert_wait = 1;
258module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
259MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 260 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 261
262static int myri10ge_force_firmware = 0;
263module_param(myri10ge_force_firmware, int, S_IRUGO);
264MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 265 "Force firmware to assume aligned completions");
0da34b6d 266
0da34b6d
BG		 267static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
268module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 269MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 270
271static int myri10ge_napi_weight = 64;
272module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 273MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 274
275static int myri10ge_watchdog_timeout = 1;
276module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 277MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 278
279static int myri10ge_max_irq_loops = 1048576;
280module_param(myri10ge_max_irq_loops, int, S_IRUGO);
281MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 282 "Set stuck legacy IRQ detection threshold");
0da34b6d 283
c58ac5ca
BG		 284#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
285
286static int myri10ge_debug = -1; /* defaults above */
287module_param(myri10ge_debug, int, 0);
288MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
289
1e6e9342
AG		 290static int myri10ge_lro = 1;
291module_param(myri10ge_lro, int, S_IRUGO);
d1ce3a0f 292MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
1e6e9342
AG		 293
294static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
295module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 296MODULE_PARM_DESC(myri10ge_lro_max_pkts,
297 "Number of LRO packets to be aggregated");
1e6e9342 298
dd50f336
BG		 299static int myri10ge_fill_thresh = 256;
300module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 301MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 302
f181137f
BG		 303static int myri10ge_reset_recover = 1;
304
f761fae1 305static int myri10ge_wcfifo = 0;
6ebc087a 306module_param(myri10ge_wcfifo, int, S_IRUGO);
d1ce3a0f 307MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
6ebc087a 308
0da34b6d
BG		 309#define MYRI10GE_FW_OFFSET 1024*1024
310#define MYRI10GE_HIGHPART_TO_U32(X) \
311(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
312#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
313
314#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
315
2f76216f 316static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 317static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 318
6250223e 319static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 320{
6250223e 321 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 322}
323
0da34b6d
BG		 324static int
325myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
326 struct myri10ge_cmd *data, int atomic)
327{
328 struct mcp_cmd *buf;
329 char buf_bytes[sizeof(*buf) + 8];
330 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 331 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 332 u32 dma_low, dma_high, result, value;
333 int sleep_total = 0;
334
335 /* ensure buf is aligned to 8 bytes */
336 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
337
338 buf->data0 = htonl(data->data0);
339 buf->data1 = htonl(data->data1);
340 buf->data2 = htonl(data->data2);
341 buf->cmd = htonl(cmd);
342 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
343 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
344
345 buf->response_addr.low = htonl(dma_low);
346 buf->response_addr.high = htonl(dma_high);
40f6cff5 347 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 348 mb();
349 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
350
351 /* wait up to 15ms. Longest command is the DMA benchmark,
352 * which is capped at 5ms, but runs from a timeout handler
353 * that runs every 7.8ms. So a 15ms timeout leaves us with
354 * a 2.2ms margin
355 */
356 if (atomic) {
357 /* if atomic is set, do not sleep,
358 * and try to get the completion quickly
359 * (1ms will be enough for those commands) */
360 for (sleep_total = 0;
361 sleep_total < 1000
40f6cff5 362 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 363 sleep_total += 10)
364 udelay(10);
365 } else {
366 /* use msleep for most command */
367 for (sleep_total = 0;
368 sleep_total < 15
40f6cff5 369 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 370 sleep_total++)
371 msleep(1);
372 }
373
374 result = ntohl(response->result);
375 value = ntohl(response->data);
376 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
377 if (result == 0) {
378 data->data0 = value;
379 return 0;
85a7ea1b
BG		 380 } else if (result == MXGEFW_CMD_UNKNOWN) {
381 return -ENOSYS;
5443e9ea
BG		 382 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
383 return -E2BIG;
0da34b6d
BG		 384 } else {
385 dev_err(&mgp->pdev->dev,
386 "command %d failed, result = %d\n",
387 cmd, result);
388 return -ENXIO;
389 }
390 }
391
392 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
393 cmd, result);
394 return -EAGAIN;
395}
396
397/*
398 * The eeprom strings on the lanaiX have the format
399 * SN=x\0
400 * MAC=x:x:x:x:x:x\0
401 * PT:ddd mmm xx xx:xx:xx xx\0
402 * PV:ddd mmm xx xx:xx:xx xx\0
403 */
404static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
405{
406 char *ptr, *limit;
407 int i;
408
409 ptr = mgp->eeprom_strings;
410 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
411
412 while (*ptr != '\0' && ptr < limit) {
413 if (memcmp(ptr, "MAC=", 4) == 0) {
414 ptr += 4;
415 mgp->mac_addr_string = ptr;
416 for (i = 0; i < 6; i++) {
417 if ((ptr + 2) > limit)
418 goto abort;
419 mgp->mac_addr[i] =
420 simple_strtoul(ptr, &ptr, 16);
421 ptr += 1;
422 }
423 }
424 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
425 ptr += 3;
426 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
427 }
428 while (ptr < limit && *ptr++) ;
429 }
430
431 return 0;
432
433abort:
434 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
435 return -ENXIO;
436}
437
438/*
439 * Enable or disable periodic RDMAs from the host to make certain
440 * chipsets resend dropped PCIe messages
441 */
442
443static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
444{
445 char __iomem *submit;
40f6cff5 446 __be32 buf[16];
0da34b6d
BG		 447 u32 dma_low, dma_high;
448 int i;
449
450 /* clear confirmation addr */
451 mgp->cmd->data = 0;
452 mb();
453
454 /* send a rdma command to the PCIe engine, and wait for the
455 * response in the confirmation address. The firmware should
456 * write a -1 there to indicate it is alive and well
457 */
458 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
459 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
460
461 buf[0] = htonl(dma_high); /* confirm addr MSW */
462 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 463 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 464 buf[3] = htonl(dma_high); /* dummy addr MSW */
465 buf[4] = htonl(dma_low); /* dummy addr LSW */
466 buf[5] = htonl(enable); /* enable? */
467
e700f9f4 468 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 469
470 myri10ge_pio_copy(submit, &buf, sizeof(buf));
471 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
472 msleep(1);
473 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
474 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
475 (enable ? "enable" : "disable"));
476}
477
478static int
479myri10ge_validate_firmware(struct myri10ge_priv *mgp,
480 struct mcp_gen_header *hdr)
481{
482 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 483
484 /* check firmware type */
485 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
486 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
487 return -EINVAL;
488 }
489
490 /* save firmware version for ethtool */
491 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
492
9dc6f0e7
BG		 493 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
494 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 495
9dc6f0e7
BG		 496 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
497 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 498 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
499 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
500 MXGEFW_VERSION_MINOR);
501 return -EINVAL;
502 }
503 return 0;
504}
505
506static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
507{
508 unsigned crc, reread_crc;
509 const struct firmware *fw;
510 struct device *dev = &mgp->pdev->dev;
511 struct mcp_gen_header *hdr;
512 size_t hdr_offset;
513 int status;
e454358a 514 unsigned i;
0da34b6d
BG		 515
516 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
517 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
518 mgp->fw_name);
519 status = -EINVAL;
520 goto abort_with_nothing;
521 }
522
523 /* check size */
524
525 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
526 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
527 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
528 status = -EINVAL;
529 goto abort_with_fw;
530 }
531
532 /* check id */
40f6cff5 533 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 534 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
535 dev_err(dev, "Bad firmware file\n");
536 status = -EINVAL;
537 goto abort_with_fw;
538 }
539 hdr = (void *)(fw->data + hdr_offset);
540
541 status = myri10ge_validate_firmware(mgp, hdr);
542 if (status != 0)
543 goto abort_with_fw;
544
545 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 546 for (i = 0; i < fw->size; i += 256) {
547 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
548 fw->data + i,
549 min(256U, (unsigned)(fw->size - i)));
550 mb();
551 readb(mgp->sram);
b10c0668 552 }
0da34b6d
BG		 553 /* corruption checking is good for parity recovery and buggy chipset */
554 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
555 reread_crc = crc32(~0, fw->data, fw->size);
556 if (crc != reread_crc) {
557 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
558 (unsigned)fw->size, reread_crc, crc);
559 status = -EIO;
560 goto abort_with_fw;
561 }
562 *size = (u32) fw->size;
563
564abort_with_fw:
565 release_firmware(fw);
566
567abort_with_nothing:
568 return status;
569}
570
571static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
572{
573 struct mcp_gen_header *hdr;
574 struct device *dev = &mgp->pdev->dev;
575 const size_t bytes = sizeof(struct mcp_gen_header);
576 size_t hdr_offset;
577 int status;
578
579 /* find running firmware header */
66341fff 580 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 581
582 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
583 dev_err(dev, "Running firmware has bad header offset (%d)\n",
584 (int)hdr_offset);
585 return -EIO;
586 }
587
588 /* copy header of running firmware from SRAM to host memory to
589 * validate firmware */
590 hdr = kmalloc(bytes, GFP_KERNEL);
591 if (hdr == NULL) {
592 dev_err(dev, "could not malloc firmware hdr\n");
593 return -ENOMEM;
594 }
595 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
596 status = myri10ge_validate_firmware(mgp, hdr);
597 kfree(hdr);
9dc6f0e7
BG		 598
599 /* check to see if adopted firmware has bug where adopting
600 * it will cause broadcasts to be filtered unless the NIC
601 * is kept in ALLMULTI mode */
602 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
603 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
604 mgp->adopted_rx_filter_bug = 1;
605 dev_warn(dev, "Adopting fw %d.%d.%d: "
606 "working around rx filter bug\n",
607 mgp->fw_ver_major, mgp->fw_ver_minor,
608 mgp->fw_ver_tiny);
609 }
0da34b6d
BG		 610 return status;
611}
612
613static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
614{
615 char __iomem *submit;
40f6cff5 616 __be32 buf[16];
0da34b6d
BG		 617 u32 dma_low, dma_high, size;
618 int status, i;
4f93fde0 619 struct myri10ge_cmd cmd;
0da34b6d 620
b10c0668 621 size = 0;
0da34b6d
BG		 622 status = myri10ge_load_hotplug_firmware(mgp, &size);
623 if (status) {
624 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
625
626 /* Do not attempt to adopt firmware if there
627 * was a bad crc */
628 if (status == -EIO)
629 return status;
630
631 status = myri10ge_adopt_running_firmware(mgp);
632 if (status != 0) {
633 dev_err(&mgp->pdev->dev,
634 "failed to adopt running firmware\n");
635 return status;
636 }
637 dev_info(&mgp->pdev->dev,
638 "Successfully adopted running firmware\n");
639 if (mgp->tx.boundary == 4096) {
640 dev_warn(&mgp->pdev->dev,
641 "Using firmware currently running on NIC"
642 ". For optimal\n");
643 dev_warn(&mgp->pdev->dev,
644 "performance consider loading optimized "
645 "firmware\n");
646 dev_warn(&mgp->pdev->dev, "via hotplug\n");
647 }
648
649 mgp->fw_name = "adopted";
650 mgp->tx.boundary = 2048;
651 return status;
652 }
653
654 /* clear confirmation addr */
655 mgp->cmd->data = 0;
656 mb();
657
658 /* send a reload command to the bootstrap MCP, and wait for the
659 * response in the confirmation address. The firmware should
660 * write a -1 there to indicate it is alive and well
661 */
662 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
663 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
664
665 buf[0] = htonl(dma_high); /* confirm addr MSW */
666 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 667 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 668
669 /* FIX: All newest firmware should un-protect the bottom of
670 * the sram before handoff. However, the very first interfaces
671 * do not. Therefore the handoff copy must skip the first 8 bytes
672 */
673 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
674 buf[4] = htonl(size - 8); /* length of code */
675 buf[5] = htonl(8); /* where to copy to */
676 buf[6] = htonl(0); /* where to jump to */
677
e700f9f4 678 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 679
680 myri10ge_pio_copy(submit, &buf, sizeof(buf));
681 mb();
682 msleep(1);
683 mb();
684 i = 0;
d93ca2a4
BG		 685 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
686 msleep(1 << i);
0da34b6d
BG		 687 i++;
688 }
689 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
690 dev_err(&mgp->pdev->dev, "handoff failed\n");
691 return -ENXIO;
692 }
693 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 694 myri10ge_dummy_rdma(mgp, 1);
0da34b6d 695
4f93fde0
BG		 696 /* probe for IPv6 TSO support */
697 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
698 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
699 &cmd, 0);
700 if (status == 0) {
701 mgp->max_tso6 = cmd.data0;
702 mgp->features |= NETIF_F_TSO6;
703 }
0da34b6d
BG		 704 return 0;
705}
706
707static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
708{
709 struct myri10ge_cmd cmd;
710 int status;
711
712 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
713 | (addr[2] << 8) | addr[3]);
714
715 cmd.data1 = ((addr[4] << 8) | (addr[5]));
716
717 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
718 return status;
719}
720
721static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
722{
723 struct myri10ge_cmd cmd;
724 int status, ctl;
725
726 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
727 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
728
729 if (status) {
730 printk(KERN_ERR
731 "myri10ge: %s: Failed to set flow control mode\n",
732 mgp->dev->name);
733 return status;
734 }
735 mgp->pause = pause;
736 return 0;
737}
738
739static void
740myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
741{
742 struct myri10ge_cmd cmd;
743 int status, ctl;
744
745 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
746 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
747 if (status)
748 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
749 mgp->dev->name);
750}
751
0d6ac257 752static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 753{
754 struct myri10ge_cmd cmd;
755 int status;
0da34b6d 756 u32 len;
34fdccea
BG		 757 struct page *dmatest_page;
758 dma_addr_t dmatest_bus;
0d6ac257
BG		 759 char *test = " ";
760
761 dmatest_page = alloc_page(GFP_KERNEL);
762 if (!dmatest_page)
763 return -ENOMEM;
764 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
765 DMA_BIDIRECTIONAL);
766
767 /* Run a small DMA test.
768 * The magic multipliers to the length tell the firmware
769 * to do DMA read, write, or read+write tests. The
770 * results are returned in cmd.data0. The upper 16
771 * bits or the return is the number of transfers completed.
772 * The lower 16 bits is the time in 0.5us ticks that the
773 * transfers took to complete.
774 */
775
776 len = mgp->tx.boundary;
777
778 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
779 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
780 cmd.data2 = len * 0x10000;
781 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
782 if (status != 0) {
783 test = "read";
784 goto abort;
785 }
786 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
787 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
788 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
789 cmd.data2 = len * 0x1;
790 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
791 if (status != 0) {
792 test = "write";
793 goto abort;
794 }
795 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
796
797 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
798 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
799 cmd.data2 = len * 0x10001;
800 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
801 if (status != 0) {
802 test = "read/write";
803 goto abort;
804 }
805 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
806 (cmd.data0 & 0xffff);
807
808abort:
809 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
810 put_page(dmatest_page);
811
812 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
813 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
814 test, status);
815
816 return status;
817}
818
819static int myri10ge_reset(struct myri10ge_priv *mgp)
820{
821 struct myri10ge_cmd cmd;
822 int status;
823 size_t bytes;
0da34b6d
BG		 824
825 /* try to send a reset command to the card to see if it
826 * is alive */
827 memset(&cmd, 0, sizeof(cmd));
828 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
829 if (status != 0) {
830 dev_err(&mgp->pdev->dev, "failed reset\n");
831 return -ENXIO;
832 }
0d6ac257
BG		 833
834 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0da34b6d
BG		 835
836 /* Now exchange information about interrupts */
837
838 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
839 memset(mgp->rx_done.entry, 0, bytes);
840 cmd.data0 = (u32) bytes;
841 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
842 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
843 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
844 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
845
846 status |=
847 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 848 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 849 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
850 &cmd, 0);
851 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 852
0da34b6d
BG		 853 status |= myri10ge_send_cmd
854 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 855 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 856 if (status != 0) {
857 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
858 return status;
859 }
40f6cff5 860 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 861
0da34b6d
BG		 862 memset(mgp->rx_done.entry, 0, bytes);
863
864 /* reset mcp/driver shared state back to 0 */
865 mgp->tx.req = 0;
866 mgp->tx.done = 0;
867 mgp->tx.pkt_start = 0;
868 mgp->tx.pkt_done = 0;
869 mgp->rx_big.cnt = 0;
870 mgp->rx_small.cnt = 0;
871 mgp->rx_done.idx = 0;
872 mgp->rx_done.cnt = 0;
c58ac5ca 873 mgp->link_changes = 0;
0da34b6d 874 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 875 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 876 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 877 return status;
878}
879
880static inline void
881myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
882 struct mcp_kreq_ether_recv *src)
883{
40f6cff5 884 __be32 low;
0da34b6d
BG		 885
886 low = src->addr_low;
40f6cff5 887 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 888 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
889 mb();
890 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 891 mb();
892 src->addr_low = low;
40f6cff5 893 put_be32(low, &dst->addr_low);
0da34b6d
BG		 894 mb();
895}
896
40f6cff5 897static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 898{
899 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
900
40f6cff5 901 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 902 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
903 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
904 skb->csum = hw_csum;
84fa7933 905 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 906 }
907}
908
dd50f336
BG		 909static inline void
910myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
911 struct skb_frag_struct *rx_frags, int len, int hlen)
912{
913 struct skb_frag_struct *skb_frags;
914
915 skb->len = skb->data_len = len;
916 skb->truesize = len + sizeof(struct sk_buff);
917 /* attach the page(s) */
918
919 skb_frags = skb_shinfo(skb)->frags;
920 while (len > 0) {
921 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
922 len -= rx_frags->size;
923 skb_frags++;
924 rx_frags++;
925 skb_shinfo(skb)->nr_frags++;
926 }
927
928 /* pskb_may_pull is not available in irq context, but
929 * skb_pull() (for ether_pad and eth_type_trans()) requires
930 * the beginning of the packet in skb_headlen(), move it
931 * manually */
27d7ff46 932 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 933 skb_shinfo(skb)->frags[0].page_offset += hlen;
934 skb_shinfo(skb)->frags[0].size -= hlen;
935 skb->data_len -= hlen;
936 skb->tail += hlen;
937 skb_pull(skb, MXGEFW_PAD);
938}
939
940static void
941myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
942 int bytes, int watchdog)
943{
944 struct page *page;
945 int idx;
946
947 if (unlikely(rx->watchdog_needed && !watchdog))
948 return;
949
950 /* try to refill entire ring */
951 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
952 idx = rx->fill_cnt & rx->mask;
ae8509b1 953 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 954 /* we can use part of previous page */
955 get_page(rx->page);
956 } else {
957 /* we need a new page */
958 page =
959 alloc_pages(GFP_ATOMIC | __GFP_COMP,
960 MYRI10GE_ALLOC_ORDER);
961 if (unlikely(page == NULL)) {
962 if (rx->fill_cnt - rx->cnt < 16)
963 rx->watchdog_needed = 1;
964 return;
965 }
966 rx->page = page;
967 rx->page_offset = 0;
968 rx->bus = pci_map_page(mgp->pdev, page, 0,
969 MYRI10GE_ALLOC_SIZE,
970 PCI_DMA_FROMDEVICE);
971 }
972 rx->info[idx].page = rx->page;
973 rx->info[idx].page_offset = rx->page_offset;
974 /* note that this is the address of the start of the
975 * page */
976 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
977 rx->shadow[idx].addr_low =
978 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
979 rx->shadow[idx].addr_high =
980 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
981
982 /* start next packet on a cacheline boundary */
983 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 984
985#if MYRI10GE_ALLOC_SIZE > 4096
986 /* don't cross a 4KB boundary */
987 if ((rx->page_offset >> 12) !=
988 ((rx->page_offset + bytes - 1) >> 12))
989 rx->page_offset = (rx->page_offset + 4096) & ~4095;
990#endif
dd50f336
BG		 991 rx->fill_cnt++;
992
993 /* copy 8 descriptors to the firmware at a time */
994 if ((idx & 7) == 7) {
995 if (rx->wc_fifo == NULL)
996 myri10ge_submit_8rx(&rx->lanai[idx - 7],
997 &rx->shadow[idx - 7]);
998 else {
999 mb();
1000 myri10ge_pio_copy(rx->wc_fifo,
1001 &rx->shadow[idx - 7], 64);
1002 }
1003 }
1004 }
1005}
1006
1007static inline void
1008myri10ge_unmap_rx_page(struct pci_dev *pdev,
1009 struct myri10ge_rx_buffer_state *info, int bytes)
1010{
1011 /* unmap the recvd page if we're the only or last user of it */
1012 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1013 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1014 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1015 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1016 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1017 }
1018}
1019
1020#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1021 * page into an skb */
1022
1023static inline int
52ea6fb3
BG		 1024myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1025 int bytes, int len, __wsum csum)
dd50f336
BG		 1026{
1027 struct sk_buff *skb;
1028 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1029 int i, idx, hlen, remainder;
1030 struct pci_dev *pdev = mgp->pdev;
1031 struct net_device *dev = mgp->dev;
1032 u8 *va;
1033
1034 len += MXGEFW_PAD;
1035 idx = rx->cnt & rx->mask;
1036 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1037 prefetch(va);
1038 /* Fill skb_frag_struct(s) with data from our receive */
1039 for (i = 0, remainder = len; remainder > 0; i++) {
1040 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1041 rx_frags[i].page = rx->info[idx].page;
1042 rx_frags[i].page_offset = rx->info[idx].page_offset;
1043 if (remainder < MYRI10GE_ALLOC_SIZE)
1044 rx_frags[i].size = remainder;
1045 else
1046 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1047 rx->cnt++;
1048 idx = rx->cnt & rx->mask;
1049 remainder -= MYRI10GE_ALLOC_SIZE;
1050 }
1051
1e6e9342
AG		 1052 if (mgp->csum_flag && myri10ge_lro) {
1053 rx_frags[0].page_offset += MXGEFW_PAD;
1054 rx_frags[0].size -= MXGEFW_PAD;
1055 len -= MXGEFW_PAD;
1056 lro_receive_frags(&mgp->rx_done.lro_mgr, rx_frags,
66341fff
AV		 1057 len, len,
1058 /* opaque, will come back in get_frag_header */
1059 (void *)(__force unsigned long)csum,
1060 csum);
1e6e9342
AG		 1061 return 1;
1062 }
1063
dd50f336
BG		 1064 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1065
e636b2ea
BG		 1066 /* allocate an skb to attach the page(s) to. This is done
1067 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1068
1069 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1070 if (unlikely(skb == NULL)) {
1071 mgp->stats.rx_dropped++;
1072 do {
1073 i--;
1074 put_page(rx_frags[i].page);
1075 } while (i != 0);
1076 return 0;
1077 }
1078
1079 /* Attach the pages to the skb, and trim off any padding */
1080 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1081 if (skb_shinfo(skb)->frags[0].size <= 0) {
1082 put_page(skb_shinfo(skb)->frags[0].page);
1083 skb_shinfo(skb)->nr_frags = 0;
1084 }
1085 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1086
1087 if (mgp->csum_flag) {
1088 if ((skb->protocol == htons(ETH_P_IP)) ||
1089 (skb->protocol == htons(ETH_P_IPV6))) {
1090 skb->csum = csum;
1091 skb->ip_summed = CHECKSUM_COMPLETE;
1092 } else
1093 myri10ge_vlan_ip_csum(skb, csum);
1094 }
1095 netif_receive_skb(skb);
1096 dev->last_rx = jiffies;
1097 return 1;
1098}
1099
0da34b6d
BG		 1100static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1101{
1102 struct pci_dev *pdev = mgp->pdev;
1103 struct myri10ge_tx_buf *tx = &mgp->tx;
1104 struct sk_buff *skb;
1105 int idx, len;
0da34b6d
BG		 1106
1107 while (tx->pkt_done != mcp_index) {
1108 idx = tx->done & tx->mask;
1109 skb = tx->info[idx].skb;
1110
1111 /* Mark as free */
1112 tx->info[idx].skb = NULL;
1113 if (tx->info[idx].last) {
1114 tx->pkt_done++;
1115 tx->info[idx].last = 0;
1116 }
1117 tx->done++;
1118 len = pci_unmap_len(&tx->info[idx], len);
1119 pci_unmap_len_set(&tx->info[idx], len, 0);
1120 if (skb) {
1121 mgp->stats.tx_bytes += skb->len;
1122 mgp->stats.tx_packets++;
1123 dev_kfree_skb_irq(skb);
1124 if (len)
1125 pci_unmap_single(pdev,
1126 pci_unmap_addr(&tx->info[idx],
1127 bus), len,
1128 PCI_DMA_TODEVICE);
1129 } else {
1130 if (len)
1131 pci_unmap_page(pdev,
1132 pci_unmap_addr(&tx->info[idx],
1133 bus), len,
1134 PCI_DMA_TODEVICE);
1135 }
0da34b6d
BG		 1136 }
1137 /* start the queue if we've stopped it */
1138 if (netif_queue_stopped(mgp->dev)
1139 && tx->req - tx->done < (tx->mask >> 1)) {
1140 mgp->wake_queue++;
1141 netif_wake_queue(mgp->dev);
1142 }
1143}
1144
bea3348e 1145static inline int myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int budget)
0da34b6d
BG		 1146{
1147 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1148 unsigned long rx_bytes = 0;
1149 unsigned long rx_packets = 0;
1150 unsigned long rx_ok;
1151
1152 int idx = rx_done->idx;
1153 int cnt = rx_done->cnt;
bea3348e 1154 int work_done = 0;
0da34b6d 1155 u16 length;
40f6cff5 1156 __wsum checksum;
0da34b6d 1157
c956a240 1158 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1159 length = ntohs(rx_done->entry[idx].length);
1160 rx_done->entry[idx].length = 0;
40f6cff5 1161 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1162 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1163 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1164 mgp->small_bytes,
1165 length, checksum);
0da34b6d 1166 else
52ea6fb3
BG		 1167 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1168 mgp->big_bytes,
1169 length, checksum);
0da34b6d
BG		 1170 rx_packets += rx_ok;
1171 rx_bytes += rx_ok * (unsigned long)length;
1172 cnt++;
1173 idx = cnt & (myri10ge_max_intr_slots - 1);
c956a240 1174 work_done++;
0da34b6d
BG		 1175 }
1176 rx_done->idx = idx;
1177 rx_done->cnt = cnt;
1178 mgp->stats.rx_packets += rx_packets;
1179 mgp->stats.rx_bytes += rx_bytes;
c7dab99b 1180
1e6e9342
AG		 1181 if (myri10ge_lro)
1182 lro_flush_all(&rx_done->lro_mgr);
1183
c7dab99b
BG		 1184 /* restock receive rings if needed */
1185 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1186 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1187 mgp->small_bytes + MXGEFW_PAD, 0);
1188 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1189 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1190
bea3348e 1191 return work_done;
0da34b6d
BG		 1192}
1193
1194static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1195{
1196 struct mcp_irq_data *stats = mgp->fw_stats;
1197
1198 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1199 unsigned link_up = ntohl(stats->link_up);
1200 if (mgp->link_state != link_up) {
1201 mgp->link_state = link_up;
1202
1203 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1204 if (netif_msg_link(mgp))
1205 printk(KERN_INFO
1206 "myri10ge: %s: link up\n",
1207 mgp->dev->name);
0da34b6d 1208 netif_carrier_on(mgp->dev);
c58ac5ca 1209 mgp->link_changes++;
0da34b6d 1210 } else {
c58ac5ca
BG		 1211 if (netif_msg_link(mgp))
1212 printk(KERN_INFO
798a95db
BG		 1213 "myri10ge: %s: link %s\n",
1214 mgp->dev->name,
1215 (link_up == MXGEFW_LINK_MYRINET ?
1216 "mismatch (Myrinet detected)" :
1217 "down"));
0da34b6d 1218 netif_carrier_off(mgp->dev);
c58ac5ca 1219 mgp->link_changes++;
0da34b6d
BG		 1220 }
1221 }
1222 if (mgp->rdma_tags_available !=
1223 ntohl(mgp->fw_stats->rdma_tags_available)) {
1224 mgp->rdma_tags_available =
1225 ntohl(mgp->fw_stats->rdma_tags_available);
1226 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1227 "%d tags left\n", mgp->dev->name,
1228 mgp->rdma_tags_available);
1229 }
1230 mgp->down_cnt += stats->link_down;
1231 if (stats->link_down)
1232 wake_up(&mgp->down_wq);
1233 }
1234}
1235
bea3348e 1236static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1237{
e636b2ea
BG		 1238 struct myri10ge_priv *mgp =
1239 container_of(napi, struct myri10ge_priv, napi);
bea3348e 1240 struct net_device *netdev = mgp->dev;
bea3348e 1241 int work_done;
0da34b6d
BG		 1242
1243 /* process as many rx events as NAPI will allow */
bea3348e 1244 work_done = myri10ge_clean_rx_done(mgp, budget);
0da34b6d 1245
4ec24119 1246 if (work_done < budget) {
bea3348e 1247 netif_rx_complete(netdev, napi);
40f6cff5 1248 put_be32(htonl(3), mgp->irq_claim);
0da34b6d 1249 }
bea3348e 1250 return work_done;
0da34b6d
BG		 1251}
1252
7d12e780 1253static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1254{
1255 struct myri10ge_priv *mgp = arg;
1256 struct mcp_irq_data *stats = mgp->fw_stats;
1257 struct myri10ge_tx_buf *tx = &mgp->tx;
1258 u32 send_done_count;
1259 int i;
1260
1261 /* make sure it is our IRQ, and that the DMA has finished */
1262 if (unlikely(!stats->valid))
1263 return (IRQ_NONE);
1264
1265 /* low bit indicates receives are present, so schedule
1266 * napi poll handler */
1267 if (stats->valid & 1)
bea3348e 1268 netif_rx_schedule(mgp->dev, &mgp->napi);
0da34b6d
BG		 1269
1270 if (!mgp->msi_enabled) {
40f6cff5 1271 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1272 if (!myri10ge_deassert_wait)
1273 stats->valid = 0;
1274 mb();
1275 } else
1276 stats->valid = 0;
1277
1278 /* Wait for IRQ line to go low, if using INTx */
1279 i = 0;
1280 while (1) {
1281 i++;
1282 /* check for transmit completes and receives */
1283 send_done_count = ntohl(stats->send_done_count);
1284 if (send_done_count != tx->pkt_done)
1285 myri10ge_tx_done(mgp, (int)send_done_count);
1286 if (unlikely(i > myri10ge_max_irq_loops)) {
1287 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1288 mgp->dev->name);
1289 stats->valid = 0;
1290 schedule_work(&mgp->watchdog_work);
1291 }
1292 if (likely(stats->valid == 0))
1293 break;
1294 cpu_relax();
1295 barrier();
1296 }
1297
1298 myri10ge_check_statblock(mgp);
1299
40f6cff5 1300 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1301 return (IRQ_HANDLED);
1302}
1303
1304static int
1305myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1306{
1307 cmd->autoneg = AUTONEG_DISABLE;
1308 cmd->speed = SPEED_10000;
1309 cmd->duplex = DUPLEX_FULL;
1310 return 0;
1311}
1312
1313static void
1314myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1315{
1316 struct myri10ge_priv *mgp = netdev_priv(netdev);
1317
1318 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1319 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1320 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1321 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1322}
1323
1324static int
1325myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1326{
1327 struct myri10ge_priv *mgp = netdev_priv(netdev);
1328 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1329 return 0;
1330}
1331
1332static int
1333myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1334{
1335 struct myri10ge_priv *mgp = netdev_priv(netdev);
1336
1337 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1338 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1339 return 0;
1340}
1341
1342static void
1343myri10ge_get_pauseparam(struct net_device *netdev,
1344 struct ethtool_pauseparam *pause)
1345{
1346 struct myri10ge_priv *mgp = netdev_priv(netdev);
1347
1348 pause->autoneg = 0;
1349 pause->rx_pause = mgp->pause;
1350 pause->tx_pause = mgp->pause;
1351}
1352
1353static int
1354myri10ge_set_pauseparam(struct net_device *netdev,
1355 struct ethtool_pauseparam *pause)
1356{
1357 struct myri10ge_priv *mgp = netdev_priv(netdev);
1358
1359 if (pause->tx_pause != mgp->pause)
1360 return myri10ge_change_pause(mgp, pause->tx_pause);
1361 if (pause->rx_pause != mgp->pause)
1362 return myri10ge_change_pause(mgp, pause->tx_pause);
1363 if (pause->autoneg != 0)
1364 return -EINVAL;
1365 return 0;
1366}
1367
1368static void
1369myri10ge_get_ringparam(struct net_device *netdev,
1370 struct ethtool_ringparam *ring)
1371{
1372 struct myri10ge_priv *mgp = netdev_priv(netdev);
1373
1374 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1375 ring->rx_max_pending = mgp->rx_big.mask + 1;
1376 ring->rx_jumbo_max_pending = 0;
1377 ring->tx_max_pending = mgp->rx_small.mask + 1;
1378 ring->rx_mini_pending = ring->rx_mini_max_pending;
1379 ring->rx_pending = ring->rx_max_pending;
1380 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1381 ring->tx_pending = ring->tx_max_pending;
1382}
1383
1384static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1385{
1386 struct myri10ge_priv *mgp = netdev_priv(netdev);
1387 if (mgp->csum_flag)
1388 return 1;
1389 else
1390 return 0;
1391}
1392
1393static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1394{
1395 struct myri10ge_priv *mgp = netdev_priv(netdev);
1396 if (csum_enabled)
1397 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1398 else
1399 mgp->csum_flag = 0;
1400 return 0;
1401}
1402
4f93fde0
BG		 1403static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1404{
1405 struct myri10ge_priv *mgp = netdev_priv(netdev);
1406 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1407
1408 if (tso_enabled)
1409 netdev->features |= flags;
1410 else
1411 netdev->features &= ~flags;
1412 return 0;
1413}
1414
0da34b6d
BG		 1415static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1416 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1417 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1418 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1419 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1420 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1421 "tx_heartbeat_errors", "tx_window_errors",
1422 /* device-specific stats */
2c1a1088 1423 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1424 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1425 "serial_number", "tx_pkt_start", "tx_pkt_done",
1426 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1427 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1428 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1429 "dropped_link_error_or_filtered",
1430 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1431 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1432 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1e6e9342
AG		 1433 "dropped_no_big_buffer", "LRO aggregated", "LRO flushed",
1434 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1435};
1436
1437#define MYRI10GE_NET_STATS_LEN 21
4c3616cd 1438#define MYRI10GE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_stats)
0da34b6d
BG		 1439
1440static void
1441myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1442{
1443 switch (stringset) {
1444 case ETH_SS_STATS:
1445 memcpy(data, *myri10ge_gstrings_stats,
1446 sizeof(myri10ge_gstrings_stats));
1447 break;
1448 }
1449}
1450
b9f2c044 1451static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1452{
b9f2c044
JG		 1453 switch (sset) {
1454 case ETH_SS_STATS:
1455 return MYRI10GE_STATS_LEN;
1456 default:
1457 return -EOPNOTSUPP;
1458 }
0da34b6d
BG		 1459}
1460
1461static void
1462myri10ge_get_ethtool_stats(struct net_device *netdev,
1463 struct ethtool_stats *stats, u64 * data)
1464{
1465 struct myri10ge_priv *mgp = netdev_priv(netdev);
1466 int i;
1467
1468 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1469 data[i] = ((unsigned long *)&mgp->stats)[i];
1470
2c1a1088 1471 data[i++] = (unsigned int)mgp->tx.boundary;
276e26c3 1472 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1473 data[i++] = (unsigned int)mgp->pdev->irq;
1474 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1475 data[i++] = (unsigned int)mgp->read_dma;
1476 data[i++] = (unsigned int)mgp->write_dma;
1477 data[i++] = (unsigned int)mgp->read_write_dma;
1478 data[i++] = (unsigned int)mgp->serial_number;
1479 data[i++] = (unsigned int)mgp->tx.pkt_start;
1480 data[i++] = (unsigned int)mgp->tx.pkt_done;
1481 data[i++] = (unsigned int)mgp->tx.req;
1482 data[i++] = (unsigned int)mgp->tx.done;
1483 data[i++] = (unsigned int)mgp->rx_small.cnt;
1484 data[i++] = (unsigned int)mgp->rx_big.cnt;
1485 data[i++] = (unsigned int)mgp->wake_queue;
1486 data[i++] = (unsigned int)mgp->stop_queue;
1487 data[i++] = (unsigned int)mgp->watchdog_resets;
1488 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1489 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1490 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1491 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1492 data[i++] =
1493 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
cee505db
BG		 1494 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1495 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1496 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1497 data[i++] =
1498 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
85a7ea1b
BG		 1499 data[i++] =
1500 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1501 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1502 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1503 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1504 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1e6e9342
AG		 1505 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated;
1506 data[i++] = mgp->rx_done.lro_mgr.stats.flushed;
1507 if (mgp->rx_done.lro_mgr.stats.flushed)
1508 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated /
1509 mgp->rx_done.lro_mgr.stats.flushed;
1510 else
1511 data[i++] = 0;
1512 data[i++] = mgp->rx_done.lro_mgr.stats.no_desc;
0da34b6d
BG		 1513}
1514
c58ac5ca
BG		 1515static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1516{
1517 struct myri10ge_priv *mgp = netdev_priv(netdev);
1518 mgp->msg_enable = value;
1519}
1520
1521static u32 myri10ge_get_msglevel(struct net_device *netdev)
1522{
1523 struct myri10ge_priv *mgp = netdev_priv(netdev);
1524 return mgp->msg_enable;
1525}
1526
7282d491 1527static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1528 .get_settings = myri10ge_get_settings,
1529 .get_drvinfo = myri10ge_get_drvinfo,
1530 .get_coalesce = myri10ge_get_coalesce,
1531 .set_coalesce = myri10ge_set_coalesce,
1532 .get_pauseparam = myri10ge_get_pauseparam,
1533 .set_pauseparam = myri10ge_set_pauseparam,
1534 .get_ringparam = myri10ge_get_ringparam,
1535 .get_rx_csum = myri10ge_get_rx_csum,
1536 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1537 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1538 .set_sg = ethtool_op_set_sg,
4f93fde0 1539 .set_tso = myri10ge_set_tso,
6ffdd071 1540 .get_link = ethtool_op_get_link,
0da34b6d 1541 .get_strings = myri10ge_get_strings,
b9f2c044 1542 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1543 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1544 .set_msglevel = myri10ge_set_msglevel,
1545 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1546};
1547
1548static int myri10ge_allocate_rings(struct net_device *dev)
1549{
1550 struct myri10ge_priv *mgp;
1551 struct myri10ge_cmd cmd;
1552 int tx_ring_size, rx_ring_size;
1553 int tx_ring_entries, rx_ring_entries;
1554 int i, status;
1555 size_t bytes;
1556
1557 mgp = netdev_priv(dev);
1558
1559 /* get ring sizes */
1560
1561 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1562 tx_ring_size = cmd.data0;
1563 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1564 if (status != 0)
1565 return status;
0da34b6d
BG		 1566 rx_ring_size = cmd.data0;
1567
1568 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1569 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1570 mgp->tx.mask = tx_ring_entries - 1;
1571 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1572
355c7265
BG		 1573 status = -ENOMEM;
1574
0da34b6d
BG		 1575 /* allocate the host shadow rings */
1576
1577 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1578 * sizeof(*mgp->tx.req_list);
1579 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1580 if (mgp->tx.req_bytes == NULL)
1581 goto abort_with_nothing;
1582
1583 /* ensure req_list entries are aligned to 8 bytes */
1584 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1585 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1586
1587 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1588 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1589 if (mgp->rx_small.shadow == NULL)
1590 goto abort_with_tx_req_bytes;
1591
1592 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1593 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1594 if (mgp->rx_big.shadow == NULL)
1595 goto abort_with_rx_small_shadow;
1596
1597 /* allocate the host info rings */
1598
1599 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1600 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1601 if (mgp->tx.info == NULL)
1602 goto abort_with_rx_big_shadow;
1603
1604 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1605 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1606 if (mgp->rx_small.info == NULL)
1607 goto abort_with_tx_info;
1608
1609 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1610 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1611 if (mgp->rx_big.info == NULL)
1612 goto abort_with_rx_small_info;
1613
1614 /* Fill the receive rings */
c7dab99b
BG		 1615 mgp->rx_big.cnt = 0;
1616 mgp->rx_small.cnt = 0;
1617 mgp->rx_big.fill_cnt = 0;
1618 mgp->rx_small.fill_cnt = 0;
1619 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1620 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1621 mgp->rx_small.watchdog_needed = 0;
1622 mgp->rx_big.watchdog_needed = 0;
1623 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1624 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1625
c7dab99b
BG		 1626 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1627 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1628 dev->name, mgp->rx_small.fill_cnt);
1629 goto abort_with_rx_small_ring;
0da34b6d
BG		 1630 }
1631
c7dab99b
BG		 1632 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1633 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1634 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1635 dev->name, mgp->rx_big.fill_cnt);
1636 goto abort_with_rx_big_ring;
0da34b6d
BG		 1637 }
1638
1639 return 0;
1640
1641abort_with_rx_big_ring:
c7dab99b
BG		 1642 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1643 int idx = i & mgp->rx_big.mask;
1644 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1645 mgp->big_bytes);
1646 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1647 }
1648
1649abort_with_rx_small_ring:
c7dab99b
BG		 1650 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1651 int idx = i & mgp->rx_small.mask;
1652 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1653 mgp->small_bytes + MXGEFW_PAD);
1654 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1655 }
c7dab99b 1656
0da34b6d
BG		 1657 kfree(mgp->rx_big.info);
1658
1659abort_with_rx_small_info:
1660 kfree(mgp->rx_small.info);
1661
1662abort_with_tx_info:
1663 kfree(mgp->tx.info);
1664
1665abort_with_rx_big_shadow:
1666 kfree(mgp->rx_big.shadow);
1667
1668abort_with_rx_small_shadow:
1669 kfree(mgp->rx_small.shadow);
1670
1671abort_with_tx_req_bytes:
1672 kfree(mgp->tx.req_bytes);
1673 mgp->tx.req_bytes = NULL;
1674 mgp->tx.req_list = NULL;
1675
1676abort_with_nothing:
1677 return status;
1678}
1679
1680static void myri10ge_free_rings(struct net_device *dev)
1681{
1682 struct myri10ge_priv *mgp;
1683 struct sk_buff *skb;
1684 struct myri10ge_tx_buf *tx;
1685 int i, len, idx;
1686
1687 mgp = netdev_priv(dev);
1688
c7dab99b
BG		 1689 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1690 idx = i & mgp->rx_big.mask;
1691 if (i == mgp->rx_big.fill_cnt - 1)
1692 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1693 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1694 mgp->big_bytes);
1695 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1696 }
1697
c7dab99b
BG		 1698 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1699 idx = i & mgp->rx_small.mask;
1700 if (i == mgp->rx_small.fill_cnt - 1)
1701 mgp->rx_small.info[idx].page_offset =
1702 MYRI10GE_ALLOC_SIZE;
1703 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1704 mgp->small_bytes + MXGEFW_PAD);
1705 put_page(mgp->rx_small.info[idx].page);
1706 }
0da34b6d
BG		 1707 tx = &mgp->tx;
1708 while (tx->done != tx->req) {
1709 idx = tx->done & tx->mask;
1710 skb = tx->info[idx].skb;
1711
1712 /* Mark as free */
1713 tx->info[idx].skb = NULL;
1714 tx->done++;
1715 len = pci_unmap_len(&tx->info[idx], len);
1716 pci_unmap_len_set(&tx->info[idx], len, 0);
1717 if (skb) {
1718 mgp->stats.tx_dropped++;
1719 dev_kfree_skb_any(skb);
1720 if (len)
1721 pci_unmap_single(mgp->pdev,
1722 pci_unmap_addr(&tx->info[idx],
1723 bus), len,
1724 PCI_DMA_TODEVICE);
1725 } else {
1726 if (len)
1727 pci_unmap_page(mgp->pdev,
1728 pci_unmap_addr(&tx->info[idx],
1729 bus), len,
1730 PCI_DMA_TODEVICE);
1731 }
1732 }
1733 kfree(mgp->rx_big.info);
1734
1735 kfree(mgp->rx_small.info);
1736
1737 kfree(mgp->tx.info);
1738
1739 kfree(mgp->rx_big.shadow);
1740
1741 kfree(mgp->rx_small.shadow);
1742
1743 kfree(mgp->tx.req_bytes);
1744 mgp->tx.req_bytes = NULL;
1745 mgp->tx.req_list = NULL;
1746}
1747
df30a740
BG		 1748static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1749{
1750 struct pci_dev *pdev = mgp->pdev;
1751 int status;
1752
1753 if (myri10ge_msi) {
1754 status = pci_enable_msi(pdev);
1755 if (status != 0)
1756 dev_err(&pdev->dev,
1757 "Error %d setting up MSI; falling back to xPIC\n",
1758 status);
1759 else
1760 mgp->msi_enabled = 1;
1761 } else {
1762 mgp->msi_enabled = 0;
1763 }
1764 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1765 mgp->dev->name, mgp);
1766 if (status != 0) {
1767 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1768 if (mgp->msi_enabled)
1769 pci_disable_msi(pdev);
1770 }
1771 return status;
1772}
1773
1774static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1775{
1776 struct pci_dev *pdev = mgp->pdev;
1777
1778 free_irq(pdev->irq, mgp);
1779 if (mgp->msi_enabled)
1780 pci_disable_msi(pdev);
1781}
1782
1e6e9342
AG		 1783static int
1784myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1785 void **ip_hdr, void **tcpudp_hdr,
1786 u64 * hdr_flags, void *priv)
1787{
1788 struct ethhdr *eh;
1789 struct vlan_ethhdr *veh;
1790 struct iphdr *iph;
1791 u8 *va = page_address(frag->page) + frag->page_offset;
1792 unsigned long ll_hlen;
66341fff
AV		 1793 /* passed opaque through lro_receive_frags() */
1794 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 1795
1796 /* find the mac header, aborting if not IPv4 */
1797
1798 eh = (struct ethhdr *)va;
1799 *mac_hdr = eh;
1800 ll_hlen = ETH_HLEN;
1801 if (eh->h_proto != htons(ETH_P_IP)) {
1802 if (eh->h_proto == htons(ETH_P_8021Q)) {
1803 veh = (struct vlan_ethhdr *)va;
1804 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1805 return -1;
1806
1807 ll_hlen += VLAN_HLEN;
1808
1809 /*
1810 * HW checksum starts ETH_HLEN bytes into
1811 * frame, so we must subtract off the VLAN
1812 * header's checksum before csum can be used
1813 */
1814 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1815 VLAN_HLEN, 0));
1816 } else {
1817 return -1;
1818 }
1819 }
1820 *hdr_flags = LRO_IPV4;
1821
1822 iph = (struct iphdr *)(va + ll_hlen);
1823 *ip_hdr = iph;
1824 if (iph->protocol != IPPROTO_TCP)
1825 return -1;
1826 *hdr_flags |= LRO_TCP;
1827 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1828
1829 /* verify the IP checksum */
1830 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1831 return -1;
1832
1833 /* verify the checksum */
1834 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1835 ntohs(iph->tot_len) - (iph->ihl << 2),
1836 IPPROTO_TCP, csum)))
1837 return -1;
1838
1839 return 0;
1840}
1841
0da34b6d
BG		 1842static int myri10ge_open(struct net_device *dev)
1843{
1844 struct myri10ge_priv *mgp;
1845 struct myri10ge_cmd cmd;
1e6e9342 1846 struct net_lro_mgr *lro_mgr;
0da34b6d
BG		 1847 int status, big_pow2;
1848
1849 mgp = netdev_priv(dev);
1850
1851 if (mgp->running != MYRI10GE_ETH_STOPPED)
1852 return -EBUSY;
1853
1854 mgp->running = MYRI10GE_ETH_STARTING;
1855 status = myri10ge_reset(mgp);
1856 if (status != 0) {
1857 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1858 goto abort_with_nothing;
0da34b6d
BG		 1859 }
1860
df30a740
BG		 1861 status = myri10ge_request_irq(mgp);
1862 if (status != 0)
1863 goto abort_with_nothing;
1864
0da34b6d
BG		 1865 /* decide what small buffer size to use. For good TCP rx
1866 * performance, it is important to not receive 1514 byte
1867 * frames into jumbo buffers, as it confuses the socket buffer
1868 * accounting code, leading to drops and erratic performance.
1869 */
1870
1871 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1872 /* enough for a TCP header */
1873 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1874 ? (128 - MXGEFW_PAD)
1875 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1876 else
de3c4507
BG		 1877 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1878 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1879
1880 /* Override the small buffer size? */
1881 if (myri10ge_small_bytes > 0)
1882 mgp->small_bytes = myri10ge_small_bytes;
1883
0da34b6d
BG		 1884 /* get the lanai pointers to the send and receive rings */
1885
1886 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1887 mgp->tx.lanai =
1888 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1889
1890 status |=
1891 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1892 mgp->rx_small.lanai =
1893 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1894
1895 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1896 mgp->rx_big.lanai =
1897 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1898
1899 if (status != 0) {
1900 printk(KERN_ERR
1901 "myri10ge: %s: failed to get ring sizes or locations\n",
1902 dev->name);
1903 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1904 goto abort_with_irq;
0da34b6d
BG		 1905 }
1906
276e26c3 1907 if (myri10ge_wcfifo && mgp->wc_enabled) {
e700f9f4
BG		 1908 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1909 mgp->rx_small.wc_fifo =
1910 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1911 mgp->rx_big.wc_fifo =
1912 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1913 } else {
1914 mgp->tx.wc_fifo = NULL;
1915 mgp->rx_small.wc_fifo = NULL;
1916 mgp->rx_big.wc_fifo = NULL;
1917 }
1918
0da34b6d
BG		 1919 /* Firmware needs the big buff size as a power of 2. Lie and
1920 * tell him the buffer is larger, because we only use 1
1921 * buffer/pkt, and the mtu will prevent overruns.
1922 */
13348bee 1923 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 1924 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 1925 while (!is_power_of_2(big_pow2))
c7dab99b 1926 big_pow2++;
13348bee 1927 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1928 } else {
1929 big_pow2 = MYRI10GE_ALLOC_SIZE;
1930 mgp->big_bytes = big_pow2;
1931 }
1932
1933 status = myri10ge_allocate_rings(dev);
1934 if (status != 0)
df30a740 1935 goto abort_with_irq;
0da34b6d
BG		 1936
1937 /* now give firmware buffers sizes, and MTU */
1938 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1939 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1940 cmd.data0 = mgp->small_bytes;
1941 status |=
1942 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1943 cmd.data0 = big_pow2;
1944 status |=
1945 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1946 if (status) {
1947 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1948 dev->name);
1949 goto abort_with_rings;
1950 }
1951
1952 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1953 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1954 cmd.data2 = sizeof(struct mcp_irq_data);
1955 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1956 if (status == -ENOSYS) {
1957 dma_addr_t bus = mgp->fw_stats_bus;
1958 bus += offsetof(struct mcp_irq_data, send_done_count);
1959 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1960 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1961 status = myri10ge_send_cmd(mgp,
1962 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1963 &cmd, 0);
1964 /* Firmware cannot support multicast without STATS_DMA_V2 */
1965 mgp->fw_multicast_support = 0;
1966 } else {
1967 mgp->fw_multicast_support = 1;
1968 }
0da34b6d
BG		 1969 if (status) {
1970 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1971 dev->name);
1972 goto abort_with_rings;
1973 }
1974
66341fff 1975 mgp->link_state = ~0U;
0da34b6d
BG		 1976 mgp->rdma_tags_available = 15;
1977
1e6e9342
AG		 1978 lro_mgr = &mgp->rx_done.lro_mgr;
1979 lro_mgr->dev = dev;
1980 lro_mgr->features = LRO_F_NAPI;
1981 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
1982 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
1983 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
1984 lro_mgr->lro_arr = mgp->rx_done.lro_desc;
1985 lro_mgr->get_frag_header = myri10ge_get_frag_header;
1986 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
621544eb 1987 lro_mgr->frag_align_pad = 2;
1e6e9342
AG		 1988 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
1989 lro_mgr->max_aggr = MAX_SKB_FRAGS;
1990
bea3348e 1991 napi_enable(&mgp->napi); /* must happen prior to any irq */
0da34b6d
BG		 1992
1993 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1994 if (status) {
1995 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1996 dev->name);
1997 goto abort_with_rings;
1998 }
1999
2000 mgp->wake_queue = 0;
2001 mgp->stop_queue = 0;
2002 mgp->running = MYRI10GE_ETH_RUNNING;
2003 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2004 add_timer(&mgp->watchdog_timer);
2005 netif_wake_queue(dev);
2006 return 0;
2007
2008abort_with_rings:
2009 myri10ge_free_rings(dev);
2010
df30a740
BG		 2011abort_with_irq:
2012 myri10ge_free_irq(mgp);
2013
0da34b6d
BG		 2014abort_with_nothing:
2015 mgp->running = MYRI10GE_ETH_STOPPED;
2016 return -ENOMEM;
2017}
2018
2019static int myri10ge_close(struct net_device *dev)
2020{
2021 struct myri10ge_priv *mgp;
2022 struct myri10ge_cmd cmd;
2023 int status, old_down_cnt;
2024
2025 mgp = netdev_priv(dev);
2026
2027 if (mgp->running != MYRI10GE_ETH_RUNNING)
2028 return 0;
2029
2030 if (mgp->tx.req_bytes == NULL)
2031 return 0;
2032
2033 del_timer_sync(&mgp->watchdog_timer);
2034 mgp->running = MYRI10GE_ETH_STOPPING;
bea3348e 2035 napi_disable(&mgp->napi);
0da34b6d
BG		 2036 netif_carrier_off(dev);
2037 netif_stop_queue(dev);
2038 old_down_cnt = mgp->down_cnt;
2039 mb();
2040 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2041 if (status)
2042 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2043 dev->name);
2044
2045 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2046 if (old_down_cnt == mgp->down_cnt)
2047 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2048
2049 netif_tx_disable(dev);
df30a740 2050 myri10ge_free_irq(mgp);
0da34b6d
BG		 2051 myri10ge_free_rings(dev);
2052
2053 mgp->running = MYRI10GE_ETH_STOPPED;
2054 return 0;
2055}
2056
2057/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2058 * backwards one at a time and handle ring wraps */
2059
2060static inline void
2061myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2062 struct mcp_kreq_ether_send *src, int cnt)
2063{
2064 int idx, starting_slot;
2065 starting_slot = tx->req;
2066 while (cnt > 1) {
2067 cnt--;
2068 idx = (starting_slot + cnt) & tx->mask;
2069 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2070 mb();
2071 }
2072}
2073
2074/*
2075 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2076 * at most 32 bytes at a time, so as to avoid involving the software
2077 * pio handler in the nic. We re-write the first segment's flags
2078 * to mark them valid only after writing the entire chain.
2079 */
2080
2081static inline void
2082myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2083 int cnt)
2084{
2085 int idx, i;
2086 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2087 struct mcp_kreq_ether_send *srcp;
2088 u8 last_flags;
2089
2090 idx = tx->req & tx->mask;
2091
2092 last_flags = src->flags;
2093 src->flags = 0;
2094 mb();
2095 dst = dstp = &tx->lanai[idx];
2096 srcp = src;
2097
2098 if ((idx + cnt) < tx->mask) {
2099 for (i = 0; i < (cnt - 1); i += 2) {
2100 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2101 mb(); /* force write every 32 bytes */
2102 srcp += 2;
2103 dstp += 2;
2104 }
2105 } else {
2106 /* submit all but the first request, and ensure
2107 * that it is submitted below */
2108 myri10ge_submit_req_backwards(tx, src, cnt);
2109 i = 0;
2110 }
2111 if (i < cnt) {
2112 /* submit the first request */
2113 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2114 mb(); /* barrier before setting valid flag */
2115 }
2116
2117 /* re-write the last 32-bits with the valid flags */
2118 src->flags = last_flags;
40f6cff5 2119 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2120 tx->req += cnt;
2121 mb();
2122}
2123
2124static inline void
2125myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2126 struct mcp_kreq_ether_send *src, int cnt)
2127{
2128 tx->req += cnt;
2129 mb();
2130 while (cnt >= 4) {
2131 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2132 mb();
2133 src += 4;
2134 cnt -= 4;
2135 }
2136 if (cnt > 0) {
2137 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2138 * needs to be so that we don't overrun it */
e700f9f4
BG		 2139 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2140 src, 64);
0da34b6d
BG		 2141 mb();
2142 }
2143}
2144
2145/*
2146 * Transmit a packet. We need to split the packet so that a single
2147 * segment does not cross myri10ge->tx.boundary, so this makes segment
2148 * counting tricky. So rather than try to count segments up front, we
2149 * just give up if there are too few segments to hold a reasonably
2150 * fragmented packet currently available. If we run
2151 * out of segments while preparing a packet for DMA, we just linearize
2152 * it and try again.
2153 */
2154
2155static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2156{
2157 struct myri10ge_priv *mgp = netdev_priv(dev);
2158 struct mcp_kreq_ether_send *req;
2159 struct myri10ge_tx_buf *tx = &mgp->tx;
2160 struct skb_frag_struct *frag;
2161 dma_addr_t bus;
40f6cff5
AV		 2162 u32 low;
2163 __be32 high_swapped;
0da34b6d
BG		 2164 unsigned int len;
2165 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2166 u16 pseudo_hdr_offset, cksum_offset;
2167 int cum_len, seglen, boundary, rdma_count;
2168 u8 flags, odd_flag;
2169
2170again:
2171 req = tx->req_list;
2172 avail = tx->mask - 1 - (tx->req - tx->done);
2173
2174 mss = 0;
2175 max_segments = MXGEFW_MAX_SEND_DESC;
2176
917690cd 2177 if (skb_is_gso(skb)) {
7967168c 2178 mss = skb_shinfo(skb)->gso_size;
917690cd 2179 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2180 }
0da34b6d
BG		 2181
2182 if ((unlikely(avail < max_segments))) {
2183 /* we are out of transmit resources */
2184 mgp->stop_queue++;
2185 netif_stop_queue(dev);
2186 return 1;
2187 }
2188
2189 /* Setup checksum offloading, if needed */
2190 cksum_offset = 0;
2191 pseudo_hdr_offset = 0;
2192 odd_flag = 0;
2193 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2194 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2195 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2196 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2197 /* If the headers are excessively large, then we must
2198 * fall back to a software checksum */
4f93fde0
BG		 2199 if (unlikely(!mss && (cksum_offset > 255 ||
2200 pseudo_hdr_offset > 127))) {
84fa7933 2201 if (skb_checksum_help(skb))
0da34b6d
BG		 2202 goto drop;
2203 cksum_offset = 0;
2204 pseudo_hdr_offset = 0;
2205 } else {
0da34b6d
BG		 2206 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2207 flags |= MXGEFW_FLAGS_CKSUM;
2208 }
2209 }
2210
2211 cum_len = 0;
2212
0da34b6d
BG		 2213 if (mss) { /* TSO */
2214 /* this removes any CKSUM flag from before */
2215 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2216
2217 /* negative cum_len signifies to the
2218 * send loop that we are still in the
2219 * header portion of the TSO packet.
4f93fde0 2220 * TSO header can be at most 1KB long */
ab6a5bb6 2221 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2222
4f93fde0
BG		 2223 /* for IPv6 TSO, the checksum offset stores the
2224 * TCP header length, to save the firmware from
2225 * the need to parse the headers */
2226 if (skb_is_gso_v6(skb)) {
2227 cksum_offset = tcp_hdrlen(skb);
2228 /* Can only handle headers <= max_tso6 long */
2229 if (unlikely(-cum_len > mgp->max_tso6))
2230 return myri10ge_sw_tso(skb, dev);
2231 }
0da34b6d
BG		 2232 /* for TSO, pseudo_hdr_offset holds mss.
2233 * The firmware figures out where to put
2234 * the checksum by parsing the header. */
40f6cff5 2235 pseudo_hdr_offset = mss;
0da34b6d 2236 } else
0da34b6d
BG		 2237 /* Mark small packets, and pad out tiny packets */
2238 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2239 flags |= MXGEFW_FLAGS_SMALL;
2240
2241 /* pad frames to at least ETH_ZLEN bytes */
2242 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2243 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2244 /* The packet is gone, so we must
2245 * return 0 */
2246 mgp->stats.tx_dropped += 1;
2247 return 0;
2248 }
2249 /* adjust the len to account for the zero pad
2250 * so that the nic can know how long it is */
2251 skb->len = ETH_ZLEN;
2252 }
2253 }
2254
2255 /* map the skb for DMA */
2256 len = skb->len - skb->data_len;
2257 idx = tx->req & tx->mask;
2258 tx->info[idx].skb = skb;
2259 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2260 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2261 pci_unmap_len_set(&tx->info[idx], len, len);
2262
2263 frag_cnt = skb_shinfo(skb)->nr_frags;
2264 frag_idx = 0;
2265 count = 0;
2266 rdma_count = 0;
2267
2268 /* "rdma_count" is the number of RDMAs belonging to the
2269 * current packet BEFORE the current send request. For
2270 * non-TSO packets, this is equal to "count".
2271 * For TSO packets, rdma_count needs to be reset
2272 * to 0 after a segment cut.
2273 *
2274 * The rdma_count field of the send request is
2275 * the number of RDMAs of the packet starting at
2276 * that request. For TSO send requests with one ore more cuts
2277 * in the middle, this is the number of RDMAs starting
2278 * after the last cut in the request. All previous
2279 * segments before the last cut implicitly have 1 RDMA.
2280 *
2281 * Since the number of RDMAs is not known beforehand,
2282 * it must be filled-in retroactively - after each
2283 * segmentation cut or at the end of the entire packet.
2284 */
2285
2286 while (1) {
2287 /* Break the SKB or Fragment up into pieces which
2288 * do not cross mgp->tx.boundary */
2289 low = MYRI10GE_LOWPART_TO_U32(bus);
2290 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2291 while (len) {
2292 u8 flags_next;
2293 int cum_len_next;
2294
2295 if (unlikely(count == max_segments))
2296 goto abort_linearize;
2297
2298 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2299 seglen = boundary - low;
2300 if (seglen > len)
2301 seglen = len;
2302 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2303 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2304 if (mss) { /* TSO */
2305 (req - rdma_count)->rdma_count = rdma_count + 1;
2306
2307 if (likely(cum_len >= 0)) { /* payload */
2308 int next_is_first, chop;
2309
2310 chop = (cum_len_next > mss);
2311 cum_len_next = cum_len_next % mss;
2312 next_is_first = (cum_len_next == 0);
2313 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2314 flags_next |= next_is_first *
2315 MXGEFW_FLAGS_FIRST;
2316 rdma_count |= -(chop | next_is_first);
2317 rdma_count += chop & !next_is_first;
2318 } else if (likely(cum_len_next >= 0)) { /* header ends */
2319 int small;
2320
2321 rdma_count = -1;
2322 cum_len_next = 0;
2323 seglen = -cum_len;
2324 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2325 flags_next = MXGEFW_FLAGS_TSO_PLD |
2326 MXGEFW_FLAGS_FIRST |
2327 (small * MXGEFW_FLAGS_SMALL);
2328 }
2329 }
0da34b6d
BG		 2330 req->addr_high = high_swapped;
2331 req->addr_low = htonl(low);
40f6cff5 2332 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2333 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2334 req->rdma_count = 1;
2335 req->length = htons(seglen);
2336 req->cksum_offset = cksum_offset;
2337 req->flags = flags | ((cum_len & 1) * odd_flag);
2338
2339 low += seglen;
2340 len -= seglen;
2341 cum_len = cum_len_next;
2342 flags = flags_next;
2343 req++;
2344 count++;
2345 rdma_count++;
4f93fde0
BG		 2346 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2347 if (unlikely(cksum_offset > seglen))
2348 cksum_offset -= seglen;
2349 else
2350 cksum_offset = 0;
2351 }
0da34b6d
BG		 2352 }
2353 if (frag_idx == frag_cnt)
2354 break;
2355
2356 /* map next fragment for DMA */
2357 idx = (count + tx->req) & tx->mask;
2358 frag = &skb_shinfo(skb)->frags[frag_idx];
2359 frag_idx++;
2360 len = frag->size;
2361 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2362 len, PCI_DMA_TODEVICE);
2363 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2364 pci_unmap_len_set(&tx->info[idx], len, len);
2365 }
2366
2367 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2368 if (mss)
2369 do {
2370 req--;
2371 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2372 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2373 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2374 idx = ((count - 1) + tx->req) & tx->mask;
2375 tx->info[idx].last = 1;
2376 if (tx->wc_fifo == NULL)
2377 myri10ge_submit_req(tx, tx->req_list, count);
2378 else
2379 myri10ge_submit_req_wc(tx, tx->req_list, count);
2380 tx->pkt_start++;
2381 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2382 mgp->stop_queue++;
2383 netif_stop_queue(dev);
2384 }
2385 dev->trans_start = jiffies;
2386 return 0;
2387
2388abort_linearize:
2389 /* Free any DMA resources we've alloced and clear out the skb
2390 * slot so as to not trip up assertions, and to avoid a
2391 * double-free if linearizing fails */
2392
2393 last_idx = (idx + 1) & tx->mask;
2394 idx = tx->req & tx->mask;
2395 tx->info[idx].skb = NULL;
2396 do {
2397 len = pci_unmap_len(&tx->info[idx], len);
2398 if (len) {
2399 if (tx->info[idx].skb != NULL)
2400 pci_unmap_single(mgp->pdev,
2401 pci_unmap_addr(&tx->info[idx],
2402 bus), len,
2403 PCI_DMA_TODEVICE);
2404 else
2405 pci_unmap_page(mgp->pdev,
2406 pci_unmap_addr(&tx->info[idx],
2407 bus), len,
2408 PCI_DMA_TODEVICE);
2409 pci_unmap_len_set(&tx->info[idx], len, 0);
2410 tx->info[idx].skb = NULL;
2411 }
2412 idx = (idx + 1) & tx->mask;
2413 } while (idx != last_idx);
89114afd 2414 if (skb_is_gso(skb)) {
0da34b6d
BG		 2415 printk(KERN_ERR
2416 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2417 mgp->dev->name);
2418 goto drop;
2419 }
2420
bec0e859 2421 if (skb_linearize(skb))
0da34b6d
BG		 2422 goto drop;
2423
2424 mgp->tx_linearized++;
2425 goto again;
2426
2427drop:
2428 dev_kfree_skb_any(skb);
2429 mgp->stats.tx_dropped += 1;
2430 return 0;
2431
2432}
2433
4f93fde0
BG		 2434static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2435{
2436 struct sk_buff *segs, *curr;
2437 struct myri10ge_priv *mgp = dev->priv;
2438 int status;
2439
2440 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2441 if (IS_ERR(segs))
4f93fde0
BG		 2442 goto drop;
2443
2444 while (segs) {
2445 curr = segs;
2446 segs = segs->next;
2447 curr->next = NULL;
2448 status = myri10ge_xmit(curr, dev);
2449 if (status != 0) {
2450 dev_kfree_skb_any(curr);
2451 if (segs != NULL) {
2452 curr = segs;
2453 segs = segs->next;
2454 curr->next = NULL;
2455 dev_kfree_skb_any(segs);
2456 }
2457 goto drop;
2458 }
2459 }
2460 dev_kfree_skb_any(skb);
2461 return 0;
2462
2463drop:
2464 dev_kfree_skb_any(skb);
2465 mgp->stats.tx_dropped += 1;
2466 return 0;
2467}
2468
0da34b6d
BG		 2469static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2470{
2471 struct myri10ge_priv *mgp = netdev_priv(dev);
2472 return &mgp->stats;
2473}
2474
2475static void myri10ge_set_multicast_list(struct net_device *dev)
2476{
85a7ea1b
BG		 2477 struct myri10ge_cmd cmd;
2478 struct myri10ge_priv *mgp;
2479 struct dev_mc_list *mc_list;
6250223e 2480 __be32 data[2] = { 0, 0 };
85a7ea1b 2481 int err;
0795af57 2482 DECLARE_MAC_BUF(mac);
85a7ea1b
BG		 2483
2484 mgp = netdev_priv(dev);
0da34b6d
BG		 2485 /* can be called from atomic contexts,
2486 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2487 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2488
2489 /* This firmware is known to not support multicast */
2f76216f 2490 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2491 return;
2492
2493 /* Disable multicast filtering */
2494
2495 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2496 if (err != 0) {
2497 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2498 " error status: %d\n", dev->name, err);
2499 goto abort;
2500 }
2501
2f76216f 2502 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2503 /* request to disable multicast filtering, so quit here */
2504 return;
2505 }
2506
2507 /* Flush the filters */
2508
2509 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2510 &cmd, 1);
2511 if (err != 0) {
2512 printk(KERN_ERR
2513 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2514 ", error status: %d\n", dev->name, err);
2515 goto abort;
2516 }
2517
2518 /* Walk the multicast list, and add each address */
2519 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2520 memcpy(data, &mc_list->dmi_addr, 6);
2521 cmd.data0 = ntohl(data[0]);
2522 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2523 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2524 &cmd, 1);
2525
2526 if (err != 0) {
2527 printk(KERN_ERR "myri10ge: %s: Failed "
2528 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2529 "%d\t", dev->name, err);
0795af57
JP		 2530 printk(KERN_ERR "MAC %s\n",
2531 print_mac(mac, mc_list->dmi_addr));
85a7ea1b
BG		 2532 goto abort;
2533 }
2534 }
2535 /* Enable multicast filtering */
2536 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2537 if (err != 0) {
2538 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2539 "error status: %d\n", dev->name, err);
2540 goto abort;
2541 }
2542
2543 return;
2544
2545abort:
2546 return;
0da34b6d
BG		 2547}
2548
2549static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2550{
2551 struct sockaddr *sa = addr;
2552 struct myri10ge_priv *mgp = netdev_priv(dev);
2553 int status;
2554
2555 if (!is_valid_ether_addr(sa->sa_data))
2556 return -EADDRNOTAVAIL;
2557
2558 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2559 if (status != 0) {
2560 printk(KERN_ERR
2561 "myri10ge: %s: changing mac address failed with %d\n",
2562 dev->name, status);
2563 return status;
2564 }
2565
2566 /* change the dev structure */
2567 memcpy(dev->dev_addr, sa->sa_data, 6);
2568 return 0;
2569}
2570
2571static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2572{
2573 struct myri10ge_priv *mgp = netdev_priv(dev);
2574 int error = 0;
2575
2576 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2577 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2578 dev->name, new_mtu);
2579 return -EINVAL;
2580 }
2581 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2582 dev->name, dev->mtu, new_mtu);
2583 if (mgp->running) {
2584 /* if we change the mtu on an active device, we must
2585 * reset the device so the firmware sees the change */
2586 myri10ge_close(dev);
2587 dev->mtu = new_mtu;
2588 myri10ge_open(dev);
2589 } else
2590 dev->mtu = new_mtu;
2591
2592 return error;
2593}
2594
2595/*
2596 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2597 * Only do it if the bridge is a root port since we don't want to disturb
2598 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2599 */
2600
0da34b6d
BG		 2601static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2602{
2603 struct pci_dev *bridge = mgp->pdev->bus->self;
2604 struct device *dev = &mgp->pdev->dev;
2605 unsigned cap;
2606 unsigned err_cap;
2607 u16 val;
2608 u8 ext_type;
2609 int ret;
2610
2611 if (!myri10ge_ecrc_enable || !bridge)
2612 return;
2613
2614 /* check that the bridge is a root port */
2615 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2616 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2617 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2618 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2619 if (myri10ge_ecrc_enable > 1) {
2620 struct pci_dev *old_bridge = bridge;
2621
2622 /* Walk the hierarchy up to the root port
2623 * where ECRC has to be enabled */
2624 do {
2625 bridge = bridge->bus->self;
2626 if (!bridge) {
2627 dev_err(dev,
2628 "Failed to find root port"
2629 " to force ECRC\n");
2630 return;
2631 }
2632 cap =
2633 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2634 pci_read_config_word(bridge,
2635 cap + PCI_CAP_FLAGS, &val);
2636 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2637 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2638
2639 dev_info(dev,
2640 "Forcing ECRC on non-root port %s"
2641 " (enabling on root port %s)\n",
2642 pci_name(old_bridge), pci_name(bridge));
2643 } else {
2644 dev_err(dev,
2645 "Not enabling ECRC on non-root port %s\n",
2646 pci_name(bridge));
2647 return;
2648 }
2649 }
2650
2651 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2652 if (!cap)
2653 return;
2654
2655 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2656 if (ret) {
2657 dev_err(dev, "failed reading ext-conf-space of %s\n",
2658 pci_name(bridge));
2659 dev_err(dev, "\t pci=nommconf in use? "
2660 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2661 return;
2662 }
2663 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2664 return;
2665
2666 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2667 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2668 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 2669}
2670
2671/*
2672 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2673 * when the PCI-E Completion packets are aligned on an 8-byte
2674 * boundary. Some PCI-E chip sets always align Completion packets; on
2675 * the ones that do not, the alignment can be enforced by enabling
2676 * ECRC generation (if supported).
2677 *
2678 * When PCI-E Completion packets are not aligned, it is actually more
2679 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2680 *
2681 * If the driver can neither enable ECRC nor verify that it has
2682 * already been enabled, then it must use a firmware image which works
2683 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2684 * should also ensure that it never gives the device a Read-DMA which is
2685 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2686 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2687 * firmware image, and set tx.boundary to 4KB.
2688 */
2689
5443e9ea 2690static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 2691{
5443e9ea
BG		 2692 struct pci_dev *pdev = mgp->pdev;
2693 struct device *dev = &pdev->dev;
302d242c 2694 int status;
0da34b6d 2695
5443e9ea
BG		 2696 mgp->tx.boundary = 4096;
2697 /*
2698 * Verify the max read request size was set to 4KB
2699 * before trying the test with 4KB.
2700 */
302d242c
BG		 2701 status = pcie_get_readrq(pdev);
2702 if (status < 0) {
5443e9ea
BG		 2703 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2704 goto abort;
2705 }
302d242c
BG		 2706 if (status != 4096) {
2707 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
5443e9ea
BG		 2708 mgp->tx.boundary = 2048;
2709 }
2710 /*
2711 * load the optimized firmware (which assumes aligned PCIe
2712 * completions) in order to see if it works on this host.
2713 */
2714 mgp->fw_name = myri10ge_fw_aligned;
2715 status = myri10ge_load_firmware(mgp);
2716 if (status != 0) {
2717 goto abort;
2718 }
2719
2720 /*
2721 * Enable ECRC if possible
2722 */
2723 myri10ge_enable_ecrc(mgp);
2724
2725 /*
2726 * Run a DMA test which watches for unaligned completions and
2727 * aborts on the first one seen.
2728 */
2729
2730 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2731 if (status == 0)
2732 return; /* keep the aligned firmware */
2733
2734 if (status != -E2BIG)
2735 dev_warn(dev, "DMA test failed: %d\n", status);
2736 if (status == -ENOSYS)
2737 dev_warn(dev, "Falling back to ethp! "
2738 "Please install up to date fw\n");
2739abort:
2740 /* fall back to using the unaligned firmware */
0da34b6d
BG		 2741 mgp->tx.boundary = 2048;
2742 mgp->fw_name = myri10ge_fw_unaligned;
2743
5443e9ea
BG		 2744}
2745
2746static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2747{
0da34b6d 2748 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2749 int link_width, exp_cap;
2750 u16 lnk;
2751
2752 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2753 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2754 link_width = (lnk >> 4) & 0x3f;
2755
ce7f9368
BG		 2756 /* Check to see if Link is less than 8 or if the
2757 * upstream bridge is known to provide aligned
2758 * completions */
2759 if (link_width < 8) {
2760 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2761 link_width);
2762 mgp->tx.boundary = 4096;
2763 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 2764 } else {
2765 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 2766 }
2767 } else {
2768 if (myri10ge_force_firmware == 1) {
2769 dev_info(&mgp->pdev->dev,
2770 "Assuming aligned completions (forced)\n");
2771 mgp->tx.boundary = 4096;
2772 mgp->fw_name = myri10ge_fw_aligned;
2773 } else {
2774 dev_info(&mgp->pdev->dev,
2775 "Assuming unaligned completions (forced)\n");
2776 mgp->tx.boundary = 2048;
2777 mgp->fw_name = myri10ge_fw_unaligned;
2778 }
2779 }
2780 if (myri10ge_fw_name != NULL) {
2781 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2782 myri10ge_fw_name);
2783 mgp->fw_name = myri10ge_fw_name;
2784 }
2785}
2786
0da34b6d 2787#ifdef CONFIG_PM
0da34b6d
BG		 2788static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2789{
2790 struct myri10ge_priv *mgp;
2791 struct net_device *netdev;
2792
2793 mgp = pci_get_drvdata(pdev);
2794 if (mgp == NULL)
2795 return -EINVAL;
2796 netdev = mgp->dev;
2797
2798 netif_device_detach(netdev);
2799 if (netif_running(netdev)) {
2800 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2801 rtnl_lock();
2802 myri10ge_close(netdev);
2803 rtnl_unlock();
2804 }
2805 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2806 pci_save_state(pdev);
0da34b6d 2807 pci_disable_device(pdev);
1a63e846
BG		 2808
2809 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2810}
2811
2812static int myri10ge_resume(struct pci_dev *pdev)
2813{
2814 struct myri10ge_priv *mgp;
2815 struct net_device *netdev;
2816 int status;
2817 u16 vendor;
2818
2819 mgp = pci_get_drvdata(pdev);
2820 if (mgp == NULL)
2821 return -EINVAL;
2822 netdev = mgp->dev;
2823 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2824 msleep(5); /* give card time to respond */
2825 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2826 if (vendor == 0xffff) {
2827 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2828 mgp->dev->name);
2829 return -EIO;
2830 }
83f6e152 2831
1a63e846
BG		 2832 status = pci_restore_state(pdev);
2833 if (status)
2834 return status;
4c2248cc
BG		 2835
2836 status = pci_enable_device(pdev);
1a63e846 2837 if (status) {
4c2248cc 2838 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2839 return status;
4c2248cc
BG		 2840 }
2841
0da34b6d
BG		 2842 pci_set_master(pdev);
2843
0da34b6d 2844 myri10ge_reset(mgp);
013b68bf 2845 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2846
2847 /* Save configuration space to be restored if the
2848 * nic resets due to a parity error */
83f6e152 2849 pci_save_state(pdev);
0da34b6d
BG		 2850
2851 if (netif_running(netdev)) {
2852 rtnl_lock();
df30a740 2853 status = myri10ge_open(netdev);
0da34b6d 2854 rtnl_unlock();
df30a740
BG		 2855 if (status != 0)
2856 goto abort_with_enabled;
2857
0da34b6d
BG		 2858 }
2859 netif_device_attach(netdev);
2860
2861 return 0;
2862
4c2248cc
BG		 2863abort_with_enabled:
2864 pci_disable_device(pdev);
0da34b6d
BG		 2865 return -EIO;
2866
2867}
0da34b6d
BG		 2868#endif /* CONFIG_PM */
2869
2870static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2871{
2872 struct pci_dev *pdev = mgp->pdev;
2873 int vs = mgp->vendor_specific_offset;
2874 u32 reboot;
2875
2876 /*enter read32 mode */
2877 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2878
2879 /*read REBOOT_STATUS (0xfffffff0) */
2880 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2881 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2882 return reboot;
2883}
2884
2885/*
2886 * This watchdog is used to check whether the board has suffered
2887 * from a parity error and needs to be recovered.
2888 */
c4028958 2889static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2890{
c4028958 2891 struct myri10ge_priv *mgp =
6250223e 2892 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2893 u32 reboot;
2894 int status;
2895 u16 cmd, vendor;
2896
2897 mgp->watchdog_resets++;
2898 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2899 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2900 /* Bus master DMA disabled? Check to see
2901 * if the card rebooted due to a parity error
2902 * For now, just report it */
2903 reboot = myri10ge_read_reboot(mgp);
2904 printk(KERN_ERR
f181137f
BG		 2905 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2906 mgp->dev->name, reboot,
2907 myri10ge_reset_recover ? " " : " not");
2908 if (myri10ge_reset_recover == 0)
2909 return;
2910
2911 myri10ge_reset_recover--;
2912
0da34b6d
BG		 2913 /*
2914 * A rebooted nic will come back with config space as
2915 * it was after power was applied to PCIe bus.
2916 * Attempt to restore config space which was saved
2917 * when the driver was loaded, or the last time the
2918 * nic was resumed from power saving mode.
2919 */
83f6e152 2920 pci_restore_state(mgp->pdev);
7adda30c
BG		 2921
2922 /* save state again for accounting reasons */
83f6e152 2923 pci_save_state(mgp->pdev);
7adda30c 2924
0da34b6d
BG		 2925 } else {
2926 /* if we get back -1's from our slot, perhaps somebody
2927 * powered off our card. Don't try to reset it in
2928 * this case */
2929 if (cmd == 0xffff) {
2930 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2931 if (vendor == 0xffff) {
2932 printk(KERN_ERR
2933 "myri10ge: %s: device disappeared!\n",
2934 mgp->dev->name);
2935 return;
2936 }
2937 }
2938 /* Perhaps it is a software error. Try to reset */
2939
2940 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2941 mgp->dev->name);
2942 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2943 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2944 mgp->tx.pkt_start, mgp->tx.pkt_done,
2945 (int)ntohl(mgp->fw_stats->send_done_count));
2946 msleep(2000);
2947 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2948 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2949 mgp->tx.pkt_start, mgp->tx.pkt_done,
2950 (int)ntohl(mgp->fw_stats->send_done_count));
2951 }
2952 rtnl_lock();
2953 myri10ge_close(mgp->dev);
2954 status = myri10ge_load_firmware(mgp);
2955 if (status != 0)
2956 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2957 mgp->dev->name);
2958 else
2959 myri10ge_open(mgp->dev);
2960 rtnl_unlock();
2961}
2962
2963/*
2964 * We use our own timer routine rather than relying upon
2965 * netdev->tx_timeout because we have a very large hardware transmit
2966 * queue. Due to the large queue, the netdev->tx_timeout function
2967 * cannot detect a NIC with a parity error in a timely fashion if the
2968 * NIC is lightly loaded.
2969 */
2970static void myri10ge_watchdog_timer(unsigned long arg)
2971{
2972 struct myri10ge_priv *mgp;
626fda94 2973 u32 rx_pause_cnt;
0da34b6d
BG		 2974
2975 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2976
2977 if (mgp->rx_small.watchdog_needed) {
2978 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2979 mgp->small_bytes + MXGEFW_PAD, 1);
2980 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2981 myri10ge_fill_thresh)
2982 mgp->rx_small.watchdog_needed = 0;
2983 }
2984 if (mgp->rx_big.watchdog_needed) {
2985 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2986 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2987 myri10ge_fill_thresh)
2988 mgp->rx_big.watchdog_needed = 0;
2989 }
626fda94 2990 rx_pause_cnt = ntohl(mgp->fw_stats->dropped_pause);
c7dab99b 2991
0da34b6d 2992 if (mgp->tx.req != mgp->tx.done &&
c54772e7 2993 mgp->tx.done == mgp->watchdog_tx_done &&
626fda94 2994 mgp->watchdog_tx_req != mgp->watchdog_tx_done) {
0da34b6d 2995 /* nic seems like it might be stuck.. */
626fda94
BG		 2996 if (rx_pause_cnt != mgp->watchdog_pause) {
2997 if (net_ratelimit())
2998 printk(KERN_WARNING "myri10ge %s:"
2999 "TX paused, check link partner\n",
3000 mgp->dev->name);
3001 } else {
3002 schedule_work(&mgp->watchdog_work);
3003 return;
3004 }
3005 }
3006 /* rearm timer */
3007 mod_timer(&mgp->watchdog_timer,
3008 jiffies + myri10ge_watchdog_timeout * HZ);
0da34b6d 3009 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 3010 mgp->watchdog_tx_req = mgp->tx.req;
626fda94 3011 mgp->watchdog_pause = rx_pause_cnt;
0da34b6d
BG		 3012}
3013
3014static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3015{
3016 struct net_device *netdev;
3017 struct myri10ge_priv *mgp;
3018 struct device *dev = &pdev->dev;
3019 size_t bytes;
3020 int i;
3021 int status = -ENXIO;
0da34b6d 3022 int dac_enabled;
0da34b6d
BG		 3023
3024 netdev = alloc_etherdev(sizeof(*mgp));
3025 if (netdev == NULL) {
3026 dev_err(dev, "Could not allocate ethernet device\n");
3027 return -ENOMEM;
3028 }
3029
b245fb67
MH		 3030 SET_NETDEV_DEV(netdev, &pdev->dev);
3031
0da34b6d 3032 mgp = netdev_priv(netdev);
0da34b6d 3033 mgp->dev = netdev;
e636b2ea 3034 netif_napi_add(netdev, &mgp->napi, myri10ge_poll, myri10ge_napi_weight);
0da34b6d
BG		 3035 mgp->pdev = pdev;
3036 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3037 mgp->pause = myri10ge_flow_control;
3038 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3039 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 3040 init_waitqueue_head(&mgp->down_wq);
3041
3042 if (pci_enable_device(pdev)) {
3043 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3044 status = -ENODEV;
3045 goto abort_with_netdev;
3046 }
0da34b6d
BG		 3047
3048 /* Find the vendor-specific cap so we can check
3049 * the reboot register later on */
3050 mgp->vendor_specific_offset
3051 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3052
3053 /* Set our max read request to 4KB */
302d242c 3054 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3055 if (status != 0) {
3056 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3057 status);
3058 goto abort_with_netdev;
3059 }
3060
3061 pci_set_master(pdev);
3062 dac_enabled = 1;
3063 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3064 if (status != 0) {
3065 dac_enabled = 0;
3066 dev_err(&pdev->dev,
898eb71c
JP		 3067 "64-bit pci address mask was refused, "
3068 "trying 32-bit\n");
0da34b6d
BG		 3069 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3070 }
3071 if (status != 0) {
3072 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3073 goto abort_with_netdev;
3074 }
b10c0668
BG		 3075 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3076 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 3077 if (mgp->cmd == NULL)
3078 goto abort_with_netdev;
3079
b10c0668
BG		 3080 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3081 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 3082 if (mgp->fw_stats == NULL)
3083 goto abort_with_cmd;
3084
3085 mgp->board_span = pci_resource_len(pdev, 0);
3086 mgp->iomem_base = pci_resource_start(pdev, 0);
3087 mgp->mtrr = -1;
276e26c3 3088 mgp->wc_enabled = 0;
0da34b6d
BG		 3089#ifdef CONFIG_MTRR
3090 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3091 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3092 if (mgp->mtrr >= 0)
3093 mgp->wc_enabled = 1;
0da34b6d
BG		 3094#endif
3095 /* Hack. need to get rid of these magic numbers */
3096 mgp->sram_size =
3097 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3098 if (mgp->sram_size > mgp->board_span) {
3099 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3100 mgp->board_span);
3101 goto abort_with_wc;
3102 }
3103 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3104 if (mgp->sram == NULL) {
3105 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3106 mgp->board_span, mgp->iomem_base);
3107 status = -ENXIO;
3108 goto abort_with_wc;
3109 }
3110 memcpy_fromio(mgp->eeprom_strings,
3111 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3112 MYRI10GE_EEPROM_STRINGS_SIZE);
3113 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3114 status = myri10ge_read_mac_addr(mgp);
3115 if (status)
3116 goto abort_with_ioremap;
3117
3118 for (i = 0; i < ETH_ALEN; i++)
3119 netdev->dev_addr[i] = mgp->mac_addr[i];
3120
3121 /* allocate rx done ring */
3122 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3123 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3124 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 3125 if (mgp->rx_done.entry == NULL)
3126 goto abort_with_ioremap;
3127 memset(mgp->rx_done.entry, 0, bytes);
3128
5443e9ea
BG		 3129 myri10ge_select_firmware(mgp);
3130
0da34b6d
BG		 3131 status = myri10ge_load_firmware(mgp);
3132 if (status != 0) {
3133 dev_err(&pdev->dev, "failed to load firmware\n");
3134 goto abort_with_rx_done;
3135 }
3136
3137 status = myri10ge_reset(mgp);
3138 if (status != 0) {
3139 dev_err(&pdev->dev, "failed reset\n");
3140 goto abort_with_firmware;
3141 }
3142
0da34b6d
BG		 3143 pci_set_drvdata(pdev, mgp);
3144 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3145 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3146 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3147 myri10ge_initial_mtu = 68;
3148 netdev->mtu = myri10ge_initial_mtu;
3149 netdev->open = myri10ge_open;
3150 netdev->stop = myri10ge_close;
3151 netdev->hard_start_xmit = myri10ge_xmit;
3152 netdev->get_stats = myri10ge_get_stats;
3153 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 3154 netdev->change_mtu = myri10ge_change_mtu;
3155 netdev->set_multicast_list = myri10ge_set_multicast_list;
3156 netdev->set_mac_address = myri10ge_set_mac_address;
4f93fde0 3157 netdev->features = mgp->features;
0da34b6d
BG		 3158 if (dac_enabled)
3159 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3160
21d05db1
BG		 3161 /* make sure we can get an irq, and that MSI can be
3162 * setup (if available). Also ensure netdev->irq
3163 * is set to correct value if MSI is enabled */
3164 status = myri10ge_request_irq(mgp);
3165 if (status != 0)
3166 goto abort_with_firmware;
3167 netdev->irq = pdev->irq;
3168 myri10ge_free_irq(mgp);
3169
0da34b6d
BG		 3170 /* Save configuration space to be restored if the
3171 * nic resets due to a parity error */
83f6e152 3172 pci_save_state(pdev);
0da34b6d
BG		 3173
3174 /* Setup the watchdog timer */
3175 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3176 (unsigned long)mgp);
3177
3178 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3179 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3180 status = register_netdev(netdev);
3181 if (status != 0) {
3182 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3183 goto abort_with_state;
0da34b6d 3184 }
21d05db1
BG		 3185 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3186 (mgp->msi_enabled ? "MSI" : "xPIC"),
3187 netdev->irq, mgp->tx.boundary, mgp->fw_name,
276e26c3 3188 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3189
3190 return 0;
3191
7adda30c 3192abort_with_state:
83f6e152 3193 pci_restore_state(pdev);
0da34b6d
BG		 3194
3195abort_with_firmware:
3196 myri10ge_dummy_rdma(mgp, 0);
3197
3198abort_with_rx_done:
3199 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3200 dma_free_coherent(&pdev->dev, bytes,
3201 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3202
3203abort_with_ioremap:
3204 iounmap(mgp->sram);
3205
3206abort_with_wc:
3207#ifdef CONFIG_MTRR
3208 if (mgp->mtrr >= 0)
3209 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3210#endif
b10c0668
BG		 3211 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3212 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 3213
3214abort_with_cmd:
b10c0668
BG		 3215 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3216 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3217
3218abort_with_netdev:
3219
3220 free_netdev(netdev);
3221 return status;
3222}
3223
3224/*
3225 * myri10ge_remove
3226 *
3227 * Does what is necessary to shutdown one Myrinet device. Called
3228 * once for each Myrinet card by the kernel when a module is
3229 * unloaded.
3230 */
3231static void myri10ge_remove(struct pci_dev *pdev)
3232{
3233 struct myri10ge_priv *mgp;
3234 struct net_device *netdev;
3235 size_t bytes;
3236
3237 mgp = pci_get_drvdata(pdev);
3238 if (mgp == NULL)
3239 return;
3240
3241 flush_scheduled_work();
3242 netdev = mgp->dev;
3243 unregister_netdev(netdev);
0da34b6d
BG		 3244
3245 myri10ge_dummy_rdma(mgp, 0);
3246
7adda30c 3247 /* avoid a memory leak */
83f6e152 3248 pci_restore_state(pdev);
7adda30c 3249
0da34b6d 3250 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3251 dma_free_coherent(&pdev->dev, bytes,
3252 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3253
3254 iounmap(mgp->sram);
3255
3256#ifdef CONFIG_MTRR
3257 if (mgp->mtrr >= 0)
3258 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3259#endif
b10c0668
BG		 3260 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3261 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3262
b10c0668
BG		 3263 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3264 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3265
3266 free_netdev(netdev);
3267 pci_set_drvdata(pdev, NULL);
3268}
3269
b10c0668 3270#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3271#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 3272
3273static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3274 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3275 {PCI_DEVICE
3276 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3277 {0},
3278};
3279
3280static struct pci_driver myri10ge_driver = {
3281 .name = "myri10ge",
3282 .probe = myri10ge_probe,
3283 .remove = myri10ge_remove,
3284 .id_table = myri10ge_pci_tbl,
3285#ifdef CONFIG_PM
3286 .suspend = myri10ge_suspend,
3287 .resume = myri10ge_resume,
3288#endif
3289};
3290
3291static __init int myri10ge_init_module(void)
3292{
3293 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3294 MYRI10GE_VERSION_STR);
3295 return pci_register_driver(&myri10ge_driver);
3296}
3297
3298module_init(myri10ge_init_module);
3299
3300static __exit void myri10ge_cleanup_module(void)
3301{
3302 pci_unregister_driver(&myri10ge_driver);
3303}
3304
3305module_exit(myri10ge_cleanup_module);
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