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myri10ge: move request_irq to myri10ge_open
[mirror_ubuntu-bionic-kernel.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005, 2006 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
51#include <linux/ip.h>
52#include <linux/inet.h>
53#include <linux/in.h>
54#include <linux/ethtool.h>
55#include <linux/firmware.h>
56#include <linux/delay.h>
57#include <linux/version.h>
58#include <linux/timer.h>
59#include <linux/vmalloc.h>
60#include <linux/crc32.h>
61#include <linux/moduleparam.h>
62#include <linux/io.h>
63#include <net/checksum.h>
64#include <asm/byteorder.h>
65#include <asm/io.h>
0da34b6d
BG		 66#include <asm/processor.h>
67#ifdef CONFIG_MTRR
68#include <asm/mtrr.h>
69#endif
70
71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h"
73
5796df19 74#define MYRI10GE_VERSION_STR "1.1.0"
0da34b6d
BG		 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com");
78MODULE_VERSION(MYRI10GE_VERSION_STR);
79MODULE_LICENSE("Dual BSD/GPL");
80
81#define MYRI10GE_MAX_ETHER_MTU 9014
82
83#define MYRI10GE_ETH_STOPPED 0
84#define MYRI10GE_ETH_STOPPING 1
85#define MYRI10GE_ETH_STARTING 2
86#define MYRI10GE_ETH_RUNNING 3
87#define MYRI10GE_ETH_OPEN_FAILED 4
88
89#define MYRI10GE_EEPROM_STRINGS_SIZE 256
90#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
40f6cff5 92#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 93#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
dd50f336
BG		 95#define MYRI10GE_ALLOC_ORDER 0
96#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
97#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
98
0da34b6d 99struct myri10ge_rx_buffer_state {
dd50f336
BG		 100 struct page *page;
101 int page_offset;
0da34b6d
BG		 102 DECLARE_PCI_UNMAP_ADDR(bus)
103 DECLARE_PCI_UNMAP_LEN(len)
104};
105
106struct myri10ge_tx_buffer_state {
107 struct sk_buff *skb;
108 int last;
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
111};
112
113struct myri10ge_cmd {
114 u32 data0;
115 u32 data1;
116 u32 data2;
117};
118
119struct myri10ge_rx_buf {
120 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
121 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
122 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
123 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 124 struct page *page;
125 dma_addr_t bus;
126 int page_offset;
0da34b6d 127 int cnt;
dd50f336 128 int fill_cnt;
0da34b6d
BG		 129 int alloc_fail;
130 int mask; /* number of rx slots -1 */
dd50f336 131 int watchdog_needed;
0da34b6d
BG		 132};
133
134struct myri10ge_tx_buf {
135 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
136 u8 __iomem *wc_fifo; /* w/c send fifo address */
137 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
138 char *req_bytes;
139 struct myri10ge_tx_buffer_state *info;
140 int mask; /* number of transmit slots -1 */
141 int boundary; /* boundary transmits cannot cross */
142 int req ____cacheline_aligned; /* transmit slots submitted */
143 int pkt_start; /* packets started */
144 int done ____cacheline_aligned; /* transmit slots completed */
145 int pkt_done; /* packets completed */
146};
147
148struct myri10ge_rx_done {
149 struct mcp_slot *entry;
150 dma_addr_t bus;
151 int cnt;
152 int idx;
153};
154
155struct myri10ge_priv {
156 int running; /* running? */
157 int csum_flag; /* rx_csums? */
158 struct myri10ge_tx_buf tx; /* transmit ring */
159 struct myri10ge_rx_buf rx_small;
160 struct myri10ge_rx_buf rx_big;
161 struct myri10ge_rx_done rx_done;
162 int small_bytes;
dd50f336 163 int big_bytes;
0da34b6d
BG		 164 struct net_device *dev;
165 struct net_device_stats stats;
166 u8 __iomem *sram;
167 int sram_size;
168 unsigned long board_span;
169 unsigned long iomem_base;
40f6cff5
AV		 170 __be32 __iomem *irq_claim;
171 __be32 __iomem *irq_deassert;
0da34b6d
BG		 172 char *mac_addr_string;
173 struct mcp_cmd_response *cmd;
174 dma_addr_t cmd_bus;
175 struct mcp_irq_data *fw_stats;
176 dma_addr_t fw_stats_bus;
177 struct pci_dev *pdev;
178 int msi_enabled;
40f6cff5 179 __be32 link_state;
0da34b6d
BG		 180 unsigned int rdma_tags_available;
181 int intr_coal_delay;
40f6cff5 182 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d
BG		 183 int mtrr;
184 int wake_queue;
185 int stop_queue;
186 int down_cnt;
187 wait_queue_head_t down_wq;
188 struct work_struct watchdog_work;
189 struct timer_list watchdog_timer;
190 int watchdog_tx_done;
c54772e7 191 int watchdog_tx_req;
0da34b6d
BG		 192 int watchdog_resets;
193 int tx_linearized;
194 int pause;
195 char *fw_name;
196 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
197 char fw_version[128];
198 u8 mac_addr[6]; /* eeprom mac address */
199 unsigned long serial_number;
200 int vendor_specific_offset;
85a7ea1b 201 int fw_multicast_support;
0da34b6d
BG		 202 u32 devctl;
203 u16 msi_flags;
0da34b6d
BG		 204 u32 read_dma;
205 u32 write_dma;
206 u32 read_write_dma;
c58ac5ca
BG		 207 u32 link_changes;
208 u32 msg_enable;
0da34b6d
BG		 209};
210
211static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
212static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
213
214static char *myri10ge_fw_name = NULL;
215module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
216MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
217
218static int myri10ge_ecrc_enable = 1;
219module_param(myri10ge_ecrc_enable, int, S_IRUGO);
220MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
221
222static int myri10ge_max_intr_slots = 1024;
223module_param(myri10ge_max_intr_slots, int, S_IRUGO);
224MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
225
226static int myri10ge_small_bytes = -1; /* -1 == auto */
227module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
228MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
229
230static int myri10ge_msi = 1; /* enable msi by default */
231module_param(myri10ge_msi, int, S_IRUGO);
232MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
233
234static int myri10ge_intr_coal_delay = 25;
235module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
236MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
237
238static int myri10ge_flow_control = 1;
239module_param(myri10ge_flow_control, int, S_IRUGO);
240MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
241
242static int myri10ge_deassert_wait = 1;
243module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
244MODULE_PARM_DESC(myri10ge_deassert_wait,
245 "Wait when deasserting legacy interrupts\n");
246
247static int myri10ge_force_firmware = 0;
248module_param(myri10ge_force_firmware, int, S_IRUGO);
249MODULE_PARM_DESC(myri10ge_force_firmware,
250 "Force firmware to assume aligned completions\n");
251
0da34b6d
BG		 252static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
253module_param(myri10ge_initial_mtu, int, S_IRUGO);
254MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
255
256static int myri10ge_napi_weight = 64;
257module_param(myri10ge_napi_weight, int, S_IRUGO);
258MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
259
260static int myri10ge_watchdog_timeout = 1;
261module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
262MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
263
264static int myri10ge_max_irq_loops = 1048576;
265module_param(myri10ge_max_irq_loops, int, S_IRUGO);
266MODULE_PARM_DESC(myri10ge_max_irq_loops,
267 "Set stuck legacy IRQ detection threshold\n");
268
c58ac5ca
BG		 269#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
270
271static int myri10ge_debug = -1; /* defaults above */
272module_param(myri10ge_debug, int, 0);
273MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
274
dd50f336
BG		 275static int myri10ge_fill_thresh = 256;
276module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
277MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
278
0da34b6d
BG		 279#define MYRI10GE_FW_OFFSET 1024*1024
280#define MYRI10GE_HIGHPART_TO_U32(X) \
281(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
282#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
283
284#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
285
6250223e 286static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 287{
6250223e 288 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 289}
290
0da34b6d
BG		 291static int
292myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
293 struct myri10ge_cmd *data, int atomic)
294{
295 struct mcp_cmd *buf;
296 char buf_bytes[sizeof(*buf) + 8];
297 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 298 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 299 u32 dma_low, dma_high, result, value;
300 int sleep_total = 0;
301
302 /* ensure buf is aligned to 8 bytes */
303 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
304
305 buf->data0 = htonl(data->data0);
306 buf->data1 = htonl(data->data1);
307 buf->data2 = htonl(data->data2);
308 buf->cmd = htonl(cmd);
309 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
310 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
311
312 buf->response_addr.low = htonl(dma_low);
313 buf->response_addr.high = htonl(dma_high);
40f6cff5 314 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 315 mb();
316 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
317
318 /* wait up to 15ms. Longest command is the DMA benchmark,
319 * which is capped at 5ms, but runs from a timeout handler
320 * that runs every 7.8ms. So a 15ms timeout leaves us with
321 * a 2.2ms margin
322 */
323 if (atomic) {
324 /* if atomic is set, do not sleep,
325 * and try to get the completion quickly
326 * (1ms will be enough for those commands) */
327 for (sleep_total = 0;
328 sleep_total < 1000
40f6cff5 329 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 330 sleep_total += 10)
331 udelay(10);
332 } else {
333 /* use msleep for most command */
334 for (sleep_total = 0;
335 sleep_total < 15
40f6cff5 336 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 337 sleep_total++)
338 msleep(1);
339 }
340
341 result = ntohl(response->result);
342 value = ntohl(response->data);
343 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
344 if (result == 0) {
345 data->data0 = value;
346 return 0;
85a7ea1b
BG		 347 } else if (result == MXGEFW_CMD_UNKNOWN) {
348 return -ENOSYS;
0da34b6d
BG		 349 } else {
350 dev_err(&mgp->pdev->dev,
351 "command %d failed, result = %d\n",
352 cmd, result);
353 return -ENXIO;
354 }
355 }
356
357 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
358 cmd, result);
359 return -EAGAIN;
360}
361
362/*
363 * The eeprom strings on the lanaiX have the format
364 * SN=x\0
365 * MAC=x:x:x:x:x:x\0
366 * PT:ddd mmm xx xx:xx:xx xx\0
367 * PV:ddd mmm xx xx:xx:xx xx\0
368 */
369static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
370{
371 char *ptr, *limit;
372 int i;
373
374 ptr = mgp->eeprom_strings;
375 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
376
377 while (*ptr != '\0' && ptr < limit) {
378 if (memcmp(ptr, "MAC=", 4) == 0) {
379 ptr += 4;
380 mgp->mac_addr_string = ptr;
381 for (i = 0; i < 6; i++) {
382 if ((ptr + 2) > limit)
383 goto abort;
384 mgp->mac_addr[i] =
385 simple_strtoul(ptr, &ptr, 16);
386 ptr += 1;
387 }
388 }
389 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
390 ptr += 3;
391 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
392 }
393 while (ptr < limit && *ptr++) ;
394 }
395
396 return 0;
397
398abort:
399 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
400 return -ENXIO;
401}
402
403/*
404 * Enable or disable periodic RDMAs from the host to make certain
405 * chipsets resend dropped PCIe messages
406 */
407
408static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
409{
410 char __iomem *submit;
40f6cff5 411 __be32 buf[16];
0da34b6d
BG		 412 u32 dma_low, dma_high;
413 int i;
414
415 /* clear confirmation addr */
416 mgp->cmd->data = 0;
417 mb();
418
419 /* send a rdma command to the PCIe engine, and wait for the
420 * response in the confirmation address. The firmware should
421 * write a -1 there to indicate it is alive and well
422 */
423 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
424 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
425
426 buf[0] = htonl(dma_high); /* confirm addr MSW */
427 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 428 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 429 buf[3] = htonl(dma_high); /* dummy addr MSW */
430 buf[4] = htonl(dma_low); /* dummy addr LSW */
431 buf[5] = htonl(enable); /* enable? */
432
e700f9f4 433 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 434
435 myri10ge_pio_copy(submit, &buf, sizeof(buf));
436 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
437 msleep(1);
438 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
439 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
440 (enable ? "enable" : "disable"));
441}
442
443static int
444myri10ge_validate_firmware(struct myri10ge_priv *mgp,
445 struct mcp_gen_header *hdr)
446{
447 struct device *dev = &mgp->pdev->dev;
448 int major, minor;
449
450 /* check firmware type */
451 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
452 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
453 return -EINVAL;
454 }
455
456 /* save firmware version for ethtool */
457 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
458
459 sscanf(mgp->fw_version, "%d.%d", &major, &minor);
460
461 if (!(major == MXGEFW_VERSION_MAJOR && minor == MXGEFW_VERSION_MINOR)) {
462 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
463 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
464 MXGEFW_VERSION_MINOR);
465 return -EINVAL;
466 }
467 return 0;
468}
469
470static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
471{
472 unsigned crc, reread_crc;
473 const struct firmware *fw;
474 struct device *dev = &mgp->pdev->dev;
475 struct mcp_gen_header *hdr;
476 size_t hdr_offset;
477 int status;
e454358a 478 unsigned i;
0da34b6d
BG		 479
480 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
481 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
482 mgp->fw_name);
483 status = -EINVAL;
484 goto abort_with_nothing;
485 }
486
487 /* check size */
488
489 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
490 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
491 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
492 status = -EINVAL;
493 goto abort_with_fw;
494 }
495
496 /* check id */
40f6cff5 497 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 498 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
499 dev_err(dev, "Bad firmware file\n");
500 status = -EINVAL;
501 goto abort_with_fw;
502 }
503 hdr = (void *)(fw->data + hdr_offset);
504
505 status = myri10ge_validate_firmware(mgp, hdr);
506 if (status != 0)
507 goto abort_with_fw;
508
509 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 510 for (i = 0; i < fw->size; i += 256) {
511 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
512 fw->data + i,
513 min(256U, (unsigned)(fw->size - i)));
514 mb();
515 readb(mgp->sram);
b10c0668 516 }
0da34b6d
BG		 517 /* corruption checking is good for parity recovery and buggy chipset */
518 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
519 reread_crc = crc32(~0, fw->data, fw->size);
520 if (crc != reread_crc) {
521 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
522 (unsigned)fw->size, reread_crc, crc);
523 status = -EIO;
524 goto abort_with_fw;
525 }
526 *size = (u32) fw->size;
527
528abort_with_fw:
529 release_firmware(fw);
530
531abort_with_nothing:
532 return status;
533}
534
535static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
536{
537 struct mcp_gen_header *hdr;
538 struct device *dev = &mgp->pdev->dev;
539 const size_t bytes = sizeof(struct mcp_gen_header);
540 size_t hdr_offset;
541 int status;
542
543 /* find running firmware header */
544 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
545
546 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
547 dev_err(dev, "Running firmware has bad header offset (%d)\n",
548 (int)hdr_offset);
549 return -EIO;
550 }
551
552 /* copy header of running firmware from SRAM to host memory to
553 * validate firmware */
554 hdr = kmalloc(bytes, GFP_KERNEL);
555 if (hdr == NULL) {
556 dev_err(dev, "could not malloc firmware hdr\n");
557 return -ENOMEM;
558 }
559 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
560 status = myri10ge_validate_firmware(mgp, hdr);
561 kfree(hdr);
562 return status;
563}
564
565static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
566{
567 char __iomem *submit;
40f6cff5 568 __be32 buf[16];
0da34b6d
BG		 569 u32 dma_low, dma_high, size;
570 int status, i;
571
b10c0668 572 size = 0;
0da34b6d
BG		 573 status = myri10ge_load_hotplug_firmware(mgp, &size);
574 if (status) {
575 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
576
577 /* Do not attempt to adopt firmware if there
578 * was a bad crc */
579 if (status == -EIO)
580 return status;
581
582 status = myri10ge_adopt_running_firmware(mgp);
583 if (status != 0) {
584 dev_err(&mgp->pdev->dev,
585 "failed to adopt running firmware\n");
586 return status;
587 }
588 dev_info(&mgp->pdev->dev,
589 "Successfully adopted running firmware\n");
590 if (mgp->tx.boundary == 4096) {
591 dev_warn(&mgp->pdev->dev,
592 "Using firmware currently running on NIC"
593 ". For optimal\n");
594 dev_warn(&mgp->pdev->dev,
595 "performance consider loading optimized "
596 "firmware\n");
597 dev_warn(&mgp->pdev->dev, "via hotplug\n");
598 }
599
600 mgp->fw_name = "adopted";
601 mgp->tx.boundary = 2048;
602 return status;
603 }
604
605 /* clear confirmation addr */
606 mgp->cmd->data = 0;
607 mb();
608
609 /* send a reload command to the bootstrap MCP, and wait for the
610 * response in the confirmation address. The firmware should
611 * write a -1 there to indicate it is alive and well
612 */
613 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
614 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
615
616 buf[0] = htonl(dma_high); /* confirm addr MSW */
617 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 618 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 619
620 /* FIX: All newest firmware should un-protect the bottom of
621 * the sram before handoff. However, the very first interfaces
622 * do not. Therefore the handoff copy must skip the first 8 bytes
623 */
624 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
625 buf[4] = htonl(size - 8); /* length of code */
626 buf[5] = htonl(8); /* where to copy to */
627 buf[6] = htonl(0); /* where to jump to */
628
e700f9f4 629 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 630
631 myri10ge_pio_copy(submit, &buf, sizeof(buf));
632 mb();
633 msleep(1);
634 mb();
635 i = 0;
636 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
637 msleep(1);
638 i++;
639 }
640 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
641 dev_err(&mgp->pdev->dev, "handoff failed\n");
642 return -ENXIO;
643 }
644 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 645 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 646
647 return 0;
648}
649
650static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
651{
652 struct myri10ge_cmd cmd;
653 int status;
654
655 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
656 | (addr[2] << 8) | addr[3]);
657
658 cmd.data1 = ((addr[4] << 8) | (addr[5]));
659
660 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
661 return status;
662}
663
664static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
665{
666 struct myri10ge_cmd cmd;
667 int status, ctl;
668
669 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
670 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
671
672 if (status) {
673 printk(KERN_ERR
674 "myri10ge: %s: Failed to set flow control mode\n",
675 mgp->dev->name);
676 return status;
677 }
678 mgp->pause = pause;
679 return 0;
680}
681
682static void
683myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
684{
685 struct myri10ge_cmd cmd;
686 int status, ctl;
687
688 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
689 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
690 if (status)
691 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
692 mgp->dev->name);
693}
694
695static int myri10ge_reset(struct myri10ge_priv *mgp)
696{
697 struct myri10ge_cmd cmd;
698 int status;
699 size_t bytes;
700 u32 len;
701
702 /* try to send a reset command to the card to see if it
703 * is alive */
704 memset(&cmd, 0, sizeof(cmd));
705 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
706 if (status != 0) {
707 dev_err(&mgp->pdev->dev, "failed reset\n");
708 return -ENXIO;
709 }
710
711 /* Now exchange information about interrupts */
712
713 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
714 memset(mgp->rx_done.entry, 0, bytes);
715 cmd.data0 = (u32) bytes;
716 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
717 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
718 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
719 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
720
721 status |=
722 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 723 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 724 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
725 &cmd, 0);
726 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 727
0da34b6d
BG		 728 status |= myri10ge_send_cmd
729 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 730 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 731 if (status != 0) {
732 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
733 return status;
734 }
40f6cff5 735 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 736
737 /* Run a small DMA test.
738 * The magic multipliers to the length tell the firmware
739 * to do DMA read, write, or read+write tests. The
740 * results are returned in cmd.data0. The upper 16
741 * bits or the return is the number of transfers completed.
742 * The lower 16 bits is the time in 0.5us ticks that the
743 * transfers took to complete.
744 */
745
746 len = mgp->tx.boundary;
747
748 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
749 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
750 cmd.data2 = len * 0x10000;
751 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
752 if (status == 0)
753 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
754 (cmd.data0 & 0xffff);
755 else
756 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
757 status);
758 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
759 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
760 cmd.data2 = len * 0x1;
761 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
762 if (status == 0)
763 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
764 (cmd.data0 & 0xffff);
765 else
766 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
767 status);
768
769 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
770 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
771 cmd.data2 = len * 0x10001;
772 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
773 if (status == 0)
774 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
775 (cmd.data0 & 0xffff);
776 else
777 dev_warn(&mgp->pdev->dev,
778 "DMA read/write benchmark failed: %d\n", status);
779
780 memset(mgp->rx_done.entry, 0, bytes);
781
782 /* reset mcp/driver shared state back to 0 */
783 mgp->tx.req = 0;
784 mgp->tx.done = 0;
785 mgp->tx.pkt_start = 0;
786 mgp->tx.pkt_done = 0;
787 mgp->rx_big.cnt = 0;
788 mgp->rx_small.cnt = 0;
789 mgp->rx_done.idx = 0;
790 mgp->rx_done.cnt = 0;
c58ac5ca 791 mgp->link_changes = 0;
0da34b6d
BG		 792 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
793 myri10ge_change_promisc(mgp, 0, 0);
794 myri10ge_change_pause(mgp, mgp->pause);
795 return status;
796}
797
798static inline void
799myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
800 struct mcp_kreq_ether_recv *src)
801{
40f6cff5 802 __be32 low;
0da34b6d
BG		 803
804 low = src->addr_low;
40f6cff5 805 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 806 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
807 mb();
808 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 809 mb();
810 src->addr_low = low;
40f6cff5 811 put_be32(low, &dst->addr_low);
0da34b6d
BG		 812 mb();
813}
814
40f6cff5 815static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 816{
817 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
818
40f6cff5 819 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 820 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
821 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
822 skb->csum = hw_csum;
84fa7933 823 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 824 }
825}
826
dd50f336
BG		 827static inline void
828myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
829 struct skb_frag_struct *rx_frags, int len, int hlen)
830{
831 struct skb_frag_struct *skb_frags;
832
833 skb->len = skb->data_len = len;
834 skb->truesize = len + sizeof(struct sk_buff);
835 /* attach the page(s) */
836
837 skb_frags = skb_shinfo(skb)->frags;
838 while (len > 0) {
839 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
840 len -= rx_frags->size;
841 skb_frags++;
842 rx_frags++;
843 skb_shinfo(skb)->nr_frags++;
844 }
845
846 /* pskb_may_pull is not available in irq context, but
847 * skb_pull() (for ether_pad and eth_type_trans()) requires
848 * the beginning of the packet in skb_headlen(), move it
849 * manually */
850 memcpy(skb->data, va, hlen);
851 skb_shinfo(skb)->frags[0].page_offset += hlen;
852 skb_shinfo(skb)->frags[0].size -= hlen;
853 skb->data_len -= hlen;
854 skb->tail += hlen;
855 skb_pull(skb, MXGEFW_PAD);
856}
857
858static void
859myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
860 int bytes, int watchdog)
861{
862 struct page *page;
863 int idx;
864
865 if (unlikely(rx->watchdog_needed && !watchdog))
866 return;
867
868 /* try to refill entire ring */
869 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
870 idx = rx->fill_cnt & rx->mask;
871
872 if ((bytes < MYRI10GE_ALLOC_SIZE / 2) &&
873 (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE)) {
874 /* we can use part of previous page */
875 get_page(rx->page);
876 } else {
877 /* we need a new page */
878 page =
879 alloc_pages(GFP_ATOMIC | __GFP_COMP,
880 MYRI10GE_ALLOC_ORDER);
881 if (unlikely(page == NULL)) {
882 if (rx->fill_cnt - rx->cnt < 16)
883 rx->watchdog_needed = 1;
884 return;
885 }
886 rx->page = page;
887 rx->page_offset = 0;
888 rx->bus = pci_map_page(mgp->pdev, page, 0,
889 MYRI10GE_ALLOC_SIZE,
890 PCI_DMA_FROMDEVICE);
891 }
892 rx->info[idx].page = rx->page;
893 rx->info[idx].page_offset = rx->page_offset;
894 /* note that this is the address of the start of the
895 * page */
896 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
897 rx->shadow[idx].addr_low =
898 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
899 rx->shadow[idx].addr_high =
900 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
901
902 /* start next packet on a cacheline boundary */
903 rx->page_offset += SKB_DATA_ALIGN(bytes);
904 rx->fill_cnt++;
905
906 /* copy 8 descriptors to the firmware at a time */
907 if ((idx & 7) == 7) {
908 if (rx->wc_fifo == NULL)
909 myri10ge_submit_8rx(&rx->lanai[idx - 7],
910 &rx->shadow[idx - 7]);
911 else {
912 mb();
913 myri10ge_pio_copy(rx->wc_fifo,
914 &rx->shadow[idx - 7], 64);
915 }
916 }
917 }
918}
919
920static inline void
921myri10ge_unmap_rx_page(struct pci_dev *pdev,
922 struct myri10ge_rx_buffer_state *info, int bytes)
923{
924 /* unmap the recvd page if we're the only or last user of it */
925 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
926 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
927 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
928 & ~(MYRI10GE_ALLOC_SIZE - 1)),
929 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
930 }
931}
932
933#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
934 * page into an skb */
935
936static inline int
52ea6fb3
BG		 937myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
938 int bytes, int len, __wsum csum)
dd50f336
BG		 939{
940 struct sk_buff *skb;
941 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
942 int i, idx, hlen, remainder;
943 struct pci_dev *pdev = mgp->pdev;
944 struct net_device *dev = mgp->dev;
945 u8 *va;
946
947 len += MXGEFW_PAD;
948 idx = rx->cnt & rx->mask;
949 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
950 prefetch(va);
951 /* Fill skb_frag_struct(s) with data from our receive */
952 for (i = 0, remainder = len; remainder > 0; i++) {
953 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
954 rx_frags[i].page = rx->info[idx].page;
955 rx_frags[i].page_offset = rx->info[idx].page_offset;
956 if (remainder < MYRI10GE_ALLOC_SIZE)
957 rx_frags[i].size = remainder;
958 else
959 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
960 rx->cnt++;
961 idx = rx->cnt & rx->mask;
962 remainder -= MYRI10GE_ALLOC_SIZE;
963 }
964
965 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
966
967 /* allocate an skb to attach the page(s) to. */
968
969 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
970 if (unlikely(skb == NULL)) {
971 mgp->stats.rx_dropped++;
972 do {
973 i--;
974 put_page(rx_frags[i].page);
975 } while (i != 0);
976 return 0;
977 }
978
979 /* Attach the pages to the skb, and trim off any padding */
980 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
981 if (skb_shinfo(skb)->frags[0].size <= 0) {
982 put_page(skb_shinfo(skb)->frags[0].page);
983 skb_shinfo(skb)->nr_frags = 0;
984 }
985 skb->protocol = eth_type_trans(skb, dev);
986 skb->dev = dev;
987
988 if (mgp->csum_flag) {
989 if ((skb->protocol == htons(ETH_P_IP)) ||
990 (skb->protocol == htons(ETH_P_IPV6))) {
991 skb->csum = csum;
992 skb->ip_summed = CHECKSUM_COMPLETE;
993 } else
994 myri10ge_vlan_ip_csum(skb, csum);
995 }
996 netif_receive_skb(skb);
997 dev->last_rx = jiffies;
998 return 1;
999}
1000
0da34b6d
BG		 1001static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1002{
1003 struct pci_dev *pdev = mgp->pdev;
1004 struct myri10ge_tx_buf *tx = &mgp->tx;
1005 struct sk_buff *skb;
1006 int idx, len;
1007 int limit = 0;
1008
1009 while (tx->pkt_done != mcp_index) {
1010 idx = tx->done & tx->mask;
1011 skb = tx->info[idx].skb;
1012
1013 /* Mark as free */
1014 tx->info[idx].skb = NULL;
1015 if (tx->info[idx].last) {
1016 tx->pkt_done++;
1017 tx->info[idx].last = 0;
1018 }
1019 tx->done++;
1020 len = pci_unmap_len(&tx->info[idx], len);
1021 pci_unmap_len_set(&tx->info[idx], len, 0);
1022 if (skb) {
1023 mgp->stats.tx_bytes += skb->len;
1024 mgp->stats.tx_packets++;
1025 dev_kfree_skb_irq(skb);
1026 if (len)
1027 pci_unmap_single(pdev,
1028 pci_unmap_addr(&tx->info[idx],
1029 bus), len,
1030 PCI_DMA_TODEVICE);
1031 } else {
1032 if (len)
1033 pci_unmap_page(pdev,
1034 pci_unmap_addr(&tx->info[idx],
1035 bus), len,
1036 PCI_DMA_TODEVICE);
1037 }
1038
1039 /* limit potential for livelock by only handling
1040 * 2 full tx rings per call */
1041 if (unlikely(++limit > 2 * tx->mask))
1042 break;
1043 }
1044 /* start the queue if we've stopped it */
1045 if (netif_queue_stopped(mgp->dev)
1046 && tx->req - tx->done < (tx->mask >> 1)) {
1047 mgp->wake_queue++;
1048 netif_wake_queue(mgp->dev);
1049 }
1050}
1051
1052static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1053{
1054 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1055 unsigned long rx_bytes = 0;
1056 unsigned long rx_packets = 0;
1057 unsigned long rx_ok;
1058
1059 int idx = rx_done->idx;
1060 int cnt = rx_done->cnt;
1061 u16 length;
40f6cff5 1062 __wsum checksum;
0da34b6d
BG		 1063
1064 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1065 length = ntohs(rx_done->entry[idx].length);
1066 rx_done->entry[idx].length = 0;
40f6cff5 1067 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1068 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1069 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1070 mgp->small_bytes,
1071 length, checksum);
0da34b6d 1072 else
52ea6fb3
BG		 1073 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1074 mgp->big_bytes,
1075 length, checksum);
0da34b6d
BG		 1076 rx_packets += rx_ok;
1077 rx_bytes += rx_ok * (unsigned long)length;
1078 cnt++;
1079 idx = cnt & (myri10ge_max_intr_slots - 1);
1080
1081 /* limit potential for livelock by only handling a
1082 * limited number of frames. */
1083 (*limit)--;
1084 }
1085 rx_done->idx = idx;
1086 rx_done->cnt = cnt;
1087 mgp->stats.rx_packets += rx_packets;
1088 mgp->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1089
1090 /* restock receive rings if needed */
1091 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1092 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1093 mgp->small_bytes + MXGEFW_PAD, 0);
1094 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1095 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1096
0da34b6d
BG		 1097}
1098
1099static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1100{
1101 struct mcp_irq_data *stats = mgp->fw_stats;
1102
1103 if (unlikely(stats->stats_updated)) {
1104 if (mgp->link_state != stats->link_up) {
1105 mgp->link_state = stats->link_up;
1106 if (mgp->link_state) {
c58ac5ca
BG		 1107 if (netif_msg_link(mgp))
1108 printk(KERN_INFO
1109 "myri10ge: %s: link up\n",
1110 mgp->dev->name);
0da34b6d 1111 netif_carrier_on(mgp->dev);
c58ac5ca 1112 mgp->link_changes++;
0da34b6d 1113 } else {
c58ac5ca
BG		 1114 if (netif_msg_link(mgp))
1115 printk(KERN_INFO
1116 "myri10ge: %s: link down\n",
1117 mgp->dev->name);
0da34b6d 1118 netif_carrier_off(mgp->dev);
c58ac5ca 1119 mgp->link_changes++;
0da34b6d
BG		 1120 }
1121 }
1122 if (mgp->rdma_tags_available !=
1123 ntohl(mgp->fw_stats->rdma_tags_available)) {
1124 mgp->rdma_tags_available =
1125 ntohl(mgp->fw_stats->rdma_tags_available);
1126 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1127 "%d tags left\n", mgp->dev->name,
1128 mgp->rdma_tags_available);
1129 }
1130 mgp->down_cnt += stats->link_down;
1131 if (stats->link_down)
1132 wake_up(&mgp->down_wq);
1133 }
1134}
1135
1136static int myri10ge_poll(struct net_device *netdev, int *budget)
1137{
1138 struct myri10ge_priv *mgp = netdev_priv(netdev);
1139 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1140 int limit, orig_limit, work_done;
1141
1142 /* process as many rx events as NAPI will allow */
1143 limit = min(*budget, netdev->quota);
1144 orig_limit = limit;
1145 myri10ge_clean_rx_done(mgp, &limit);
1146 work_done = orig_limit - limit;
1147 *budget -= work_done;
1148 netdev->quota -= work_done;
1149
1150 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1151 netif_rx_complete(netdev);
40f6cff5 1152 put_be32(htonl(3), mgp->irq_claim);
0da34b6d
BG		 1153 return 0;
1154 }
1155 return 1;
1156}
1157
7d12e780 1158static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1159{
1160 struct myri10ge_priv *mgp = arg;
1161 struct mcp_irq_data *stats = mgp->fw_stats;
1162 struct myri10ge_tx_buf *tx = &mgp->tx;
1163 u32 send_done_count;
1164 int i;
1165
1166 /* make sure it is our IRQ, and that the DMA has finished */
1167 if (unlikely(!stats->valid))
1168 return (IRQ_NONE);
1169
1170 /* low bit indicates receives are present, so schedule
1171 * napi poll handler */
1172 if (stats->valid & 1)
1173 netif_rx_schedule(mgp->dev);
1174
1175 if (!mgp->msi_enabled) {
40f6cff5 1176 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1177 if (!myri10ge_deassert_wait)
1178 stats->valid = 0;
1179 mb();
1180 } else
1181 stats->valid = 0;
1182
1183 /* Wait for IRQ line to go low, if using INTx */
1184 i = 0;
1185 while (1) {
1186 i++;
1187 /* check for transmit completes and receives */
1188 send_done_count = ntohl(stats->send_done_count);
1189 if (send_done_count != tx->pkt_done)
1190 myri10ge_tx_done(mgp, (int)send_done_count);
1191 if (unlikely(i > myri10ge_max_irq_loops)) {
1192 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1193 mgp->dev->name);
1194 stats->valid = 0;
1195 schedule_work(&mgp->watchdog_work);
1196 }
1197 if (likely(stats->valid == 0))
1198 break;
1199 cpu_relax();
1200 barrier();
1201 }
1202
1203 myri10ge_check_statblock(mgp);
1204
40f6cff5 1205 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1206 return (IRQ_HANDLED);
1207}
1208
1209static int
1210myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1211{
1212 cmd->autoneg = AUTONEG_DISABLE;
1213 cmd->speed = SPEED_10000;
1214 cmd->duplex = DUPLEX_FULL;
1215 return 0;
1216}
1217
1218static void
1219myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1220{
1221 struct myri10ge_priv *mgp = netdev_priv(netdev);
1222
1223 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1224 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1225 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1226 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1227}
1228
1229static int
1230myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1231{
1232 struct myri10ge_priv *mgp = netdev_priv(netdev);
1233 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1234 return 0;
1235}
1236
1237static int
1238myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1239{
1240 struct myri10ge_priv *mgp = netdev_priv(netdev);
1241
1242 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1243 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1244 return 0;
1245}
1246
1247static void
1248myri10ge_get_pauseparam(struct net_device *netdev,
1249 struct ethtool_pauseparam *pause)
1250{
1251 struct myri10ge_priv *mgp = netdev_priv(netdev);
1252
1253 pause->autoneg = 0;
1254 pause->rx_pause = mgp->pause;
1255 pause->tx_pause = mgp->pause;
1256}
1257
1258static int
1259myri10ge_set_pauseparam(struct net_device *netdev,
1260 struct ethtool_pauseparam *pause)
1261{
1262 struct myri10ge_priv *mgp = netdev_priv(netdev);
1263
1264 if (pause->tx_pause != mgp->pause)
1265 return myri10ge_change_pause(mgp, pause->tx_pause);
1266 if (pause->rx_pause != mgp->pause)
1267 return myri10ge_change_pause(mgp, pause->tx_pause);
1268 if (pause->autoneg != 0)
1269 return -EINVAL;
1270 return 0;
1271}
1272
1273static void
1274myri10ge_get_ringparam(struct net_device *netdev,
1275 struct ethtool_ringparam *ring)
1276{
1277 struct myri10ge_priv *mgp = netdev_priv(netdev);
1278
1279 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1280 ring->rx_max_pending = mgp->rx_big.mask + 1;
1281 ring->rx_jumbo_max_pending = 0;
1282 ring->tx_max_pending = mgp->rx_small.mask + 1;
1283 ring->rx_mini_pending = ring->rx_mini_max_pending;
1284 ring->rx_pending = ring->rx_max_pending;
1285 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1286 ring->tx_pending = ring->tx_max_pending;
1287}
1288
1289static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1290{
1291 struct myri10ge_priv *mgp = netdev_priv(netdev);
1292 if (mgp->csum_flag)
1293 return 1;
1294 else
1295 return 0;
1296}
1297
1298static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1299{
1300 struct myri10ge_priv *mgp = netdev_priv(netdev);
1301 if (csum_enabled)
1302 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1303 else
1304 mgp->csum_flag = 0;
1305 return 0;
1306}
1307
1308static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1309 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1310 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1311 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1312 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1313 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1314 "tx_heartbeat_errors", "tx_window_errors",
1315 /* device-specific stats */
2c1a1088 1316 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1317 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1318 "serial_number", "tx_pkt_start", "tx_pkt_done",
1319 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1320 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1321 "link_changes", "link_up", "dropped_link_overflow",
85a7ea1b 1322 "dropped_link_error_or_filtered", "dropped_multicast_filtered",
0da34b6d
BG		 1323 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1324 "dropped_no_big_buffer"
1325};
1326
1327#define MYRI10GE_NET_STATS_LEN 21
1328#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1329
1330static void
1331myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1332{
1333 switch (stringset) {
1334 case ETH_SS_STATS:
1335 memcpy(data, *myri10ge_gstrings_stats,
1336 sizeof(myri10ge_gstrings_stats));
1337 break;
1338 }
1339}
1340
1341static int myri10ge_get_stats_count(struct net_device *netdev)
1342{
1343 return MYRI10GE_STATS_LEN;
1344}
1345
1346static void
1347myri10ge_get_ethtool_stats(struct net_device *netdev,
1348 struct ethtool_stats *stats, u64 * data)
1349{
1350 struct myri10ge_priv *mgp = netdev_priv(netdev);
1351 int i;
1352
1353 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1354 data[i] = ((unsigned long *)&mgp->stats)[i];
1355
2c1a1088
BG		 1356 data[i++] = (unsigned int)mgp->tx.boundary;
1357 data[i++] = (unsigned int)(mgp->mtrr >= 0);
1358 data[i++] = (unsigned int)mgp->pdev->irq;
1359 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1360 data[i++] = (unsigned int)mgp->read_dma;
1361 data[i++] = (unsigned int)mgp->write_dma;
1362 data[i++] = (unsigned int)mgp->read_write_dma;
1363 data[i++] = (unsigned int)mgp->serial_number;
1364 data[i++] = (unsigned int)mgp->tx.pkt_start;
1365 data[i++] = (unsigned int)mgp->tx.pkt_done;
1366 data[i++] = (unsigned int)mgp->tx.req;
1367 data[i++] = (unsigned int)mgp->tx.done;
1368 data[i++] = (unsigned int)mgp->rx_small.cnt;
1369 data[i++] = (unsigned int)mgp->rx_big.cnt;
1370 data[i++] = (unsigned int)mgp->wake_queue;
1371 data[i++] = (unsigned int)mgp->stop_queue;
1372 data[i++] = (unsigned int)mgp->watchdog_resets;
1373 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1374 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1375 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1376 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1377 data[i++] =
1378 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
85a7ea1b
BG		 1379 data[i++] =
1380 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1381 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1382 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1383 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1384 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1385}
1386
c58ac5ca
BG		 1387static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1388{
1389 struct myri10ge_priv *mgp = netdev_priv(netdev);
1390 mgp->msg_enable = value;
1391}
1392
1393static u32 myri10ge_get_msglevel(struct net_device *netdev)
1394{
1395 struct myri10ge_priv *mgp = netdev_priv(netdev);
1396 return mgp->msg_enable;
1397}
1398
7282d491 1399static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1400 .get_settings = myri10ge_get_settings,
1401 .get_drvinfo = myri10ge_get_drvinfo,
1402 .get_coalesce = myri10ge_get_coalesce,
1403 .set_coalesce = myri10ge_set_coalesce,
1404 .get_pauseparam = myri10ge_get_pauseparam,
1405 .set_pauseparam = myri10ge_set_pauseparam,
1406 .get_ringparam = myri10ge_get_ringparam,
1407 .get_rx_csum = myri10ge_get_rx_csum,
1408 .set_rx_csum = myri10ge_set_rx_csum,
1409 .get_tx_csum = ethtool_op_get_tx_csum,
b10c0668 1410 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d
BG		 1411 .get_sg = ethtool_op_get_sg,
1412 .set_sg = ethtool_op_set_sg,
1413#ifdef NETIF_F_TSO
1414 .get_tso = ethtool_op_get_tso,
1415 .set_tso = ethtool_op_set_tso,
1416#endif
1417 .get_strings = myri10ge_get_strings,
1418 .get_stats_count = myri10ge_get_stats_count,
c58ac5ca
BG		 1419 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1420 .set_msglevel = myri10ge_set_msglevel,
1421 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1422};
1423
1424static int myri10ge_allocate_rings(struct net_device *dev)
1425{
1426 struct myri10ge_priv *mgp;
1427 struct myri10ge_cmd cmd;
1428 int tx_ring_size, rx_ring_size;
1429 int tx_ring_entries, rx_ring_entries;
1430 int i, status;
1431 size_t bytes;
1432
1433 mgp = netdev_priv(dev);
1434
1435 /* get ring sizes */
1436
1437 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1438 tx_ring_size = cmd.data0;
1439 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1440 rx_ring_size = cmd.data0;
1441
1442 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1443 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1444 mgp->tx.mask = tx_ring_entries - 1;
1445 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1446
1447 /* allocate the host shadow rings */
1448
1449 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1450 * sizeof(*mgp->tx.req_list);
1451 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1452 if (mgp->tx.req_bytes == NULL)
1453 goto abort_with_nothing;
1454
1455 /* ensure req_list entries are aligned to 8 bytes */
1456 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1457 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1458
1459 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1460 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1461 if (mgp->rx_small.shadow == NULL)
1462 goto abort_with_tx_req_bytes;
1463
1464 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1465 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1466 if (mgp->rx_big.shadow == NULL)
1467 goto abort_with_rx_small_shadow;
1468
1469 /* allocate the host info rings */
1470
1471 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1472 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1473 if (mgp->tx.info == NULL)
1474 goto abort_with_rx_big_shadow;
1475
1476 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1477 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1478 if (mgp->rx_small.info == NULL)
1479 goto abort_with_tx_info;
1480
1481 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1482 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1483 if (mgp->rx_big.info == NULL)
1484 goto abort_with_rx_small_info;
1485
1486 /* Fill the receive rings */
c7dab99b
BG		 1487 mgp->rx_big.cnt = 0;
1488 mgp->rx_small.cnt = 0;
1489 mgp->rx_big.fill_cnt = 0;
1490 mgp->rx_small.fill_cnt = 0;
1491 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1492 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1493 mgp->rx_small.watchdog_needed = 0;
1494 mgp->rx_big.watchdog_needed = 0;
1495 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1496 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1497
c7dab99b
BG		 1498 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1499 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1500 dev->name, mgp->rx_small.fill_cnt);
1501 goto abort_with_rx_small_ring;
0da34b6d
BG		 1502 }
1503
c7dab99b
BG		 1504 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1505 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1506 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1507 dev->name, mgp->rx_big.fill_cnt);
1508 goto abort_with_rx_big_ring;
0da34b6d
BG		 1509 }
1510
1511 return 0;
1512
1513abort_with_rx_big_ring:
c7dab99b
BG		 1514 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1515 int idx = i & mgp->rx_big.mask;
1516 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1517 mgp->big_bytes);
1518 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1519 }
1520
1521abort_with_rx_small_ring:
c7dab99b
BG		 1522 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1523 int idx = i & mgp->rx_small.mask;
1524 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1525 mgp->small_bytes + MXGEFW_PAD);
1526 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1527 }
c7dab99b 1528
0da34b6d
BG		 1529 kfree(mgp->rx_big.info);
1530
1531abort_with_rx_small_info:
1532 kfree(mgp->rx_small.info);
1533
1534abort_with_tx_info:
1535 kfree(mgp->tx.info);
1536
1537abort_with_rx_big_shadow:
1538 kfree(mgp->rx_big.shadow);
1539
1540abort_with_rx_small_shadow:
1541 kfree(mgp->rx_small.shadow);
1542
1543abort_with_tx_req_bytes:
1544 kfree(mgp->tx.req_bytes);
1545 mgp->tx.req_bytes = NULL;
1546 mgp->tx.req_list = NULL;
1547
1548abort_with_nothing:
1549 return status;
1550}
1551
1552static void myri10ge_free_rings(struct net_device *dev)
1553{
1554 struct myri10ge_priv *mgp;
1555 struct sk_buff *skb;
1556 struct myri10ge_tx_buf *tx;
1557 int i, len, idx;
1558
1559 mgp = netdev_priv(dev);
1560
c7dab99b
BG		 1561 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1562 idx = i & mgp->rx_big.mask;
1563 if (i == mgp->rx_big.fill_cnt - 1)
1564 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1565 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1566 mgp->big_bytes);
1567 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1568 }
1569
c7dab99b
BG		 1570 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1571 idx = i & mgp->rx_small.mask;
1572 if (i == mgp->rx_small.fill_cnt - 1)
1573 mgp->rx_small.info[idx].page_offset =
1574 MYRI10GE_ALLOC_SIZE;
1575 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1576 mgp->small_bytes + MXGEFW_PAD);
1577 put_page(mgp->rx_small.info[idx].page);
1578 }
0da34b6d
BG		 1579 tx = &mgp->tx;
1580 while (tx->done != tx->req) {
1581 idx = tx->done & tx->mask;
1582 skb = tx->info[idx].skb;
1583
1584 /* Mark as free */
1585 tx->info[idx].skb = NULL;
1586 tx->done++;
1587 len = pci_unmap_len(&tx->info[idx], len);
1588 pci_unmap_len_set(&tx->info[idx], len, 0);
1589 if (skb) {
1590 mgp->stats.tx_dropped++;
1591 dev_kfree_skb_any(skb);
1592 if (len)
1593 pci_unmap_single(mgp->pdev,
1594 pci_unmap_addr(&tx->info[idx],
1595 bus), len,
1596 PCI_DMA_TODEVICE);
1597 } else {
1598 if (len)
1599 pci_unmap_page(mgp->pdev,
1600 pci_unmap_addr(&tx->info[idx],
1601 bus), len,
1602 PCI_DMA_TODEVICE);
1603 }
1604 }
1605 kfree(mgp->rx_big.info);
1606
1607 kfree(mgp->rx_small.info);
1608
1609 kfree(mgp->tx.info);
1610
1611 kfree(mgp->rx_big.shadow);
1612
1613 kfree(mgp->rx_small.shadow);
1614
1615 kfree(mgp->tx.req_bytes);
1616 mgp->tx.req_bytes = NULL;
1617 mgp->tx.req_list = NULL;
1618}
1619
df30a740
BG		 1620static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1621{
1622 struct pci_dev *pdev = mgp->pdev;
1623 int status;
1624
1625 if (myri10ge_msi) {
1626 status = pci_enable_msi(pdev);
1627 if (status != 0)
1628 dev_err(&pdev->dev,
1629 "Error %d setting up MSI; falling back to xPIC\n",
1630 status);
1631 else
1632 mgp->msi_enabled = 1;
1633 } else {
1634 mgp->msi_enabled = 0;
1635 }
1636 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1637 mgp->dev->name, mgp);
1638 if (status != 0) {
1639 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1640 if (mgp->msi_enabled)
1641 pci_disable_msi(pdev);
1642 }
1643 return status;
1644}
1645
1646static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1647{
1648 struct pci_dev *pdev = mgp->pdev;
1649
1650 free_irq(pdev->irq, mgp);
1651 if (mgp->msi_enabled)
1652 pci_disable_msi(pdev);
1653}
1654
0da34b6d
BG		 1655static int myri10ge_open(struct net_device *dev)
1656{
1657 struct myri10ge_priv *mgp;
1658 struct myri10ge_cmd cmd;
1659 int status, big_pow2;
1660
1661 mgp = netdev_priv(dev);
1662
1663 if (mgp->running != MYRI10GE_ETH_STOPPED)
1664 return -EBUSY;
1665
1666 mgp->running = MYRI10GE_ETH_STARTING;
1667 status = myri10ge_reset(mgp);
1668 if (status != 0) {
1669 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1670 goto abort_with_nothing;
0da34b6d
BG		 1671 }
1672
df30a740
BG		 1673 status = myri10ge_request_irq(mgp);
1674 if (status != 0)
1675 goto abort_with_nothing;
1676
0da34b6d
BG		 1677 /* decide what small buffer size to use. For good TCP rx
1678 * performance, it is important to not receive 1514 byte
1679 * frames into jumbo buffers, as it confuses the socket buffer
1680 * accounting code, leading to drops and erratic performance.
1681 */
1682
1683 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1684 /* enough for a TCP header */
1685 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1686 ? (128 - MXGEFW_PAD)
1687 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1688 else
de3c4507
BG		 1689 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1690 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1691
1692 /* Override the small buffer size? */
1693 if (myri10ge_small_bytes > 0)
1694 mgp->small_bytes = myri10ge_small_bytes;
1695
0da34b6d
BG		 1696 /* get the lanai pointers to the send and receive rings */
1697
1698 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1699 mgp->tx.lanai =
1700 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1701
1702 status |=
1703 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1704 mgp->rx_small.lanai =
1705 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1706
1707 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1708 mgp->rx_big.lanai =
1709 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1710
1711 if (status != 0) {
1712 printk(KERN_ERR
1713 "myri10ge: %s: failed to get ring sizes or locations\n",
1714 dev->name);
1715 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1716 goto abort_with_irq;
0da34b6d
BG		 1717 }
1718
1719 if (mgp->mtrr >= 0) {
e700f9f4
BG		 1720 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1721 mgp->rx_small.wc_fifo =
1722 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1723 mgp->rx_big.wc_fifo =
1724 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1725 } else {
1726 mgp->tx.wc_fifo = NULL;
1727 mgp->rx_small.wc_fifo = NULL;
1728 mgp->rx_big.wc_fifo = NULL;
1729 }
1730
0da34b6d
BG		 1731 /* Firmware needs the big buff size as a power of 2. Lie and
1732 * tell him the buffer is larger, because we only use 1
1733 * buffer/pkt, and the mtu will prevent overruns.
1734 */
13348bee 1735 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1736 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1737 while ((big_pow2 & (big_pow2 - 1)) != 0)
1738 big_pow2++;
13348bee 1739 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1740 } else {
1741 big_pow2 = MYRI10GE_ALLOC_SIZE;
1742 mgp->big_bytes = big_pow2;
1743 }
1744
1745 status = myri10ge_allocate_rings(dev);
1746 if (status != 0)
df30a740 1747 goto abort_with_irq;
0da34b6d
BG		 1748
1749 /* now give firmware buffers sizes, and MTU */
1750 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1751 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1752 cmd.data0 = mgp->small_bytes;
1753 status |=
1754 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1755 cmd.data0 = big_pow2;
1756 status |=
1757 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1758 if (status) {
1759 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1760 dev->name);
1761 goto abort_with_rings;
1762 }
1763
1764 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1765 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1766 cmd.data2 = sizeof(struct mcp_irq_data);
1767 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1768 if (status == -ENOSYS) {
1769 dma_addr_t bus = mgp->fw_stats_bus;
1770 bus += offsetof(struct mcp_irq_data, send_done_count);
1771 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1772 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1773 status = myri10ge_send_cmd(mgp,
1774 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1775 &cmd, 0);
1776 /* Firmware cannot support multicast without STATS_DMA_V2 */
1777 mgp->fw_multicast_support = 0;
1778 } else {
1779 mgp->fw_multicast_support = 1;
1780 }
0da34b6d
BG		 1781 if (status) {
1782 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1783 dev->name);
1784 goto abort_with_rings;
1785 }
1786
40f6cff5 1787 mgp->link_state = htonl(~0U);
0da34b6d
BG		 1788 mgp->rdma_tags_available = 15;
1789
1790 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1791
1792 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1793 if (status) {
1794 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1795 dev->name);
1796 goto abort_with_rings;
1797 }
1798
1799 mgp->wake_queue = 0;
1800 mgp->stop_queue = 0;
1801 mgp->running = MYRI10GE_ETH_RUNNING;
1802 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1803 add_timer(&mgp->watchdog_timer);
1804 netif_wake_queue(dev);
1805 return 0;
1806
1807abort_with_rings:
1808 myri10ge_free_rings(dev);
1809
df30a740
BG		 1810abort_with_irq:
1811 myri10ge_free_irq(mgp);
1812
0da34b6d
BG		 1813abort_with_nothing:
1814 mgp->running = MYRI10GE_ETH_STOPPED;
1815 return -ENOMEM;
1816}
1817
1818static int myri10ge_close(struct net_device *dev)
1819{
1820 struct myri10ge_priv *mgp;
1821 struct myri10ge_cmd cmd;
1822 int status, old_down_cnt;
1823
1824 mgp = netdev_priv(dev);
1825
1826 if (mgp->running != MYRI10GE_ETH_RUNNING)
1827 return 0;
1828
1829 if (mgp->tx.req_bytes == NULL)
1830 return 0;
1831
1832 del_timer_sync(&mgp->watchdog_timer);
1833 mgp->running = MYRI10GE_ETH_STOPPING;
1834 netif_poll_disable(mgp->dev);
1835 netif_carrier_off(dev);
1836 netif_stop_queue(dev);
1837 old_down_cnt = mgp->down_cnt;
1838 mb();
1839 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1840 if (status)
1841 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1842 dev->name);
1843
1844 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1845 if (old_down_cnt == mgp->down_cnt)
1846 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1847
1848 netif_tx_disable(dev);
df30a740 1849 myri10ge_free_irq(mgp);
0da34b6d
BG		 1850 myri10ge_free_rings(dev);
1851
1852 mgp->running = MYRI10GE_ETH_STOPPED;
1853 return 0;
1854}
1855
1856/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1857 * backwards one at a time and handle ring wraps */
1858
1859static inline void
1860myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1861 struct mcp_kreq_ether_send *src, int cnt)
1862{
1863 int idx, starting_slot;
1864 starting_slot = tx->req;
1865 while (cnt > 1) {
1866 cnt--;
1867 idx = (starting_slot + cnt) & tx->mask;
1868 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1869 mb();
1870 }
1871}
1872
1873/*
1874 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1875 * at most 32 bytes at a time, so as to avoid involving the software
1876 * pio handler in the nic. We re-write the first segment's flags
1877 * to mark them valid only after writing the entire chain.
1878 */
1879
1880static inline void
1881myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1882 int cnt)
1883{
1884 int idx, i;
1885 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1886 struct mcp_kreq_ether_send *srcp;
1887 u8 last_flags;
1888
1889 idx = tx->req & tx->mask;
1890
1891 last_flags = src->flags;
1892 src->flags = 0;
1893 mb();
1894 dst = dstp = &tx->lanai[idx];
1895 srcp = src;
1896
1897 if ((idx + cnt) < tx->mask) {
1898 for (i = 0; i < (cnt - 1); i += 2) {
1899 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1900 mb(); /* force write every 32 bytes */
1901 srcp += 2;
1902 dstp += 2;
1903 }
1904 } else {
1905 /* submit all but the first request, and ensure
1906 * that it is submitted below */
1907 myri10ge_submit_req_backwards(tx, src, cnt);
1908 i = 0;
1909 }
1910 if (i < cnt) {
1911 /* submit the first request */
1912 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1913 mb(); /* barrier before setting valid flag */
1914 }
1915
1916 /* re-write the last 32-bits with the valid flags */
1917 src->flags = last_flags;
40f6cff5 1918 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 1919 tx->req += cnt;
1920 mb();
1921}
1922
1923static inline void
1924myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1925 struct mcp_kreq_ether_send *src, int cnt)
1926{
1927 tx->req += cnt;
1928 mb();
1929 while (cnt >= 4) {
1930 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1931 mb();
1932 src += 4;
1933 cnt -= 4;
1934 }
1935 if (cnt > 0) {
1936 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1937 * needs to be so that we don't overrun it */
e700f9f4
BG		 1938 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1939 src, 64);
0da34b6d
BG		 1940 mb();
1941 }
1942}
1943
1944/*
1945 * Transmit a packet. We need to split the packet so that a single
1946 * segment does not cross myri10ge->tx.boundary, so this makes segment
1947 * counting tricky. So rather than try to count segments up front, we
1948 * just give up if there are too few segments to hold a reasonably
1949 * fragmented packet currently available. If we run
1950 * out of segments while preparing a packet for DMA, we just linearize
1951 * it and try again.
1952 */
1953
1954static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1955{
1956 struct myri10ge_priv *mgp = netdev_priv(dev);
1957 struct mcp_kreq_ether_send *req;
1958 struct myri10ge_tx_buf *tx = &mgp->tx;
1959 struct skb_frag_struct *frag;
1960 dma_addr_t bus;
40f6cff5
AV		 1961 u32 low;
1962 __be32 high_swapped;
0da34b6d
BG		 1963 unsigned int len;
1964 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1965 u16 pseudo_hdr_offset, cksum_offset;
1966 int cum_len, seglen, boundary, rdma_count;
1967 u8 flags, odd_flag;
1968
1969again:
1970 req = tx->req_list;
1971 avail = tx->mask - 1 - (tx->req - tx->done);
1972
1973 mss = 0;
1974 max_segments = MXGEFW_MAX_SEND_DESC;
1975
1976#ifdef NETIF_F_TSO
1977 if (skb->len > (dev->mtu + ETH_HLEN)) {
7967168c 1978 mss = skb_shinfo(skb)->gso_size;
0da34b6d
BG		 1979 if (mss != 0)
1980 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
1981 }
1982#endif /*NETIF_F_TSO */
1983
1984 if ((unlikely(avail < max_segments))) {
1985 /* we are out of transmit resources */
1986 mgp->stop_queue++;
1987 netif_stop_queue(dev);
1988 return 1;
1989 }
1990
1991 /* Setup checksum offloading, if needed */
1992 cksum_offset = 0;
1993 pseudo_hdr_offset = 0;
1994 odd_flag = 0;
1995 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 1996 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0da34b6d 1997 cksum_offset = (skb->h.raw - skb->data);
ff1dcadb 1998 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 1999 /* If the headers are excessively large, then we must
2000 * fall back to a software checksum */
2001 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
84fa7933 2002 if (skb_checksum_help(skb))
0da34b6d
BG		 2003 goto drop;
2004 cksum_offset = 0;
2005 pseudo_hdr_offset = 0;
2006 } else {
0da34b6d
BG		 2007 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2008 flags |= MXGEFW_FLAGS_CKSUM;
2009 }
2010 }
2011
2012 cum_len = 0;
2013
2014#ifdef NETIF_F_TSO
2015 if (mss) { /* TSO */
2016 /* this removes any CKSUM flag from before */
2017 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2018
2019 /* negative cum_len signifies to the
2020 * send loop that we are still in the
2021 * header portion of the TSO packet.
2022 * TSO header must be at most 134 bytes long */
2023 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2024
2025 /* for TSO, pseudo_hdr_offset holds mss.
2026 * The firmware figures out where to put
2027 * the checksum by parsing the header. */
40f6cff5 2028 pseudo_hdr_offset = mss;
0da34b6d
BG		 2029 } else
2030#endif /*NETIF_F_TSO */
2031 /* Mark small packets, and pad out tiny packets */
2032 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2033 flags |= MXGEFW_FLAGS_SMALL;
2034
2035 /* pad frames to at least ETH_ZLEN bytes */
2036 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2037 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2038 /* The packet is gone, so we must
2039 * return 0 */
2040 mgp->stats.tx_dropped += 1;
2041 return 0;
2042 }
2043 /* adjust the len to account for the zero pad
2044 * so that the nic can know how long it is */
2045 skb->len = ETH_ZLEN;
2046 }
2047 }
2048
2049 /* map the skb for DMA */
2050 len = skb->len - skb->data_len;
2051 idx = tx->req & tx->mask;
2052 tx->info[idx].skb = skb;
2053 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2054 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2055 pci_unmap_len_set(&tx->info[idx], len, len);
2056
2057 frag_cnt = skb_shinfo(skb)->nr_frags;
2058 frag_idx = 0;
2059 count = 0;
2060 rdma_count = 0;
2061
2062 /* "rdma_count" is the number of RDMAs belonging to the
2063 * current packet BEFORE the current send request. For
2064 * non-TSO packets, this is equal to "count".
2065 * For TSO packets, rdma_count needs to be reset
2066 * to 0 after a segment cut.
2067 *
2068 * The rdma_count field of the send request is
2069 * the number of RDMAs of the packet starting at
2070 * that request. For TSO send requests with one ore more cuts
2071 * in the middle, this is the number of RDMAs starting
2072 * after the last cut in the request. All previous
2073 * segments before the last cut implicitly have 1 RDMA.
2074 *
2075 * Since the number of RDMAs is not known beforehand,
2076 * it must be filled-in retroactively - after each
2077 * segmentation cut or at the end of the entire packet.
2078 */
2079
2080 while (1) {
2081 /* Break the SKB or Fragment up into pieces which
2082 * do not cross mgp->tx.boundary */
2083 low = MYRI10GE_LOWPART_TO_U32(bus);
2084 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2085 while (len) {
2086 u8 flags_next;
2087 int cum_len_next;
2088
2089 if (unlikely(count == max_segments))
2090 goto abort_linearize;
2091
2092 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2093 seglen = boundary - low;
2094 if (seglen > len)
2095 seglen = len;
2096 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2097 cum_len_next = cum_len + seglen;
2098#ifdef NETIF_F_TSO
2099 if (mss) { /* TSO */
2100 (req - rdma_count)->rdma_count = rdma_count + 1;
2101
2102 if (likely(cum_len >= 0)) { /* payload */
2103 int next_is_first, chop;
2104
2105 chop = (cum_len_next > mss);
2106 cum_len_next = cum_len_next % mss;
2107 next_is_first = (cum_len_next == 0);
2108 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2109 flags_next |= next_is_first *
2110 MXGEFW_FLAGS_FIRST;
2111 rdma_count |= -(chop | next_is_first);
2112 rdma_count += chop & !next_is_first;
2113 } else if (likely(cum_len_next >= 0)) { /* header ends */
2114 int small;
2115
2116 rdma_count = -1;
2117 cum_len_next = 0;
2118 seglen = -cum_len;
2119 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2120 flags_next = MXGEFW_FLAGS_TSO_PLD |
2121 MXGEFW_FLAGS_FIRST |
2122 (small * MXGEFW_FLAGS_SMALL);
2123 }
2124 }
2125#endif /* NETIF_F_TSO */
2126 req->addr_high = high_swapped;
2127 req->addr_low = htonl(low);
40f6cff5 2128 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2129 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2130 req->rdma_count = 1;
2131 req->length = htons(seglen);
2132 req->cksum_offset = cksum_offset;
2133 req->flags = flags | ((cum_len & 1) * odd_flag);
2134
2135 low += seglen;
2136 len -= seglen;
2137 cum_len = cum_len_next;
2138 flags = flags_next;
2139 req++;
2140 count++;
2141 rdma_count++;
2142 if (unlikely(cksum_offset > seglen))
2143 cksum_offset -= seglen;
2144 else
2145 cksum_offset = 0;
2146 }
2147 if (frag_idx == frag_cnt)
2148 break;
2149
2150 /* map next fragment for DMA */
2151 idx = (count + tx->req) & tx->mask;
2152 frag = &skb_shinfo(skb)->frags[frag_idx];
2153 frag_idx++;
2154 len = frag->size;
2155 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2156 len, PCI_DMA_TODEVICE);
2157 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2158 pci_unmap_len_set(&tx->info[idx], len, len);
2159 }
2160
2161 (req - rdma_count)->rdma_count = rdma_count;
2162#ifdef NETIF_F_TSO
2163 if (mss)
2164 do {
2165 req--;
2166 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2167 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2168 MXGEFW_FLAGS_FIRST)));
2169#endif
2170 idx = ((count - 1) + tx->req) & tx->mask;
2171 tx->info[idx].last = 1;
2172 if (tx->wc_fifo == NULL)
2173 myri10ge_submit_req(tx, tx->req_list, count);
2174 else
2175 myri10ge_submit_req_wc(tx, tx->req_list, count);
2176 tx->pkt_start++;
2177 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2178 mgp->stop_queue++;
2179 netif_stop_queue(dev);
2180 }
2181 dev->trans_start = jiffies;
2182 return 0;
2183
2184abort_linearize:
2185 /* Free any DMA resources we've alloced and clear out the skb
2186 * slot so as to not trip up assertions, and to avoid a
2187 * double-free if linearizing fails */
2188
2189 last_idx = (idx + 1) & tx->mask;
2190 idx = tx->req & tx->mask;
2191 tx->info[idx].skb = NULL;
2192 do {
2193 len = pci_unmap_len(&tx->info[idx], len);
2194 if (len) {
2195 if (tx->info[idx].skb != NULL)
2196 pci_unmap_single(mgp->pdev,
2197 pci_unmap_addr(&tx->info[idx],
2198 bus), len,
2199 PCI_DMA_TODEVICE);
2200 else
2201 pci_unmap_page(mgp->pdev,
2202 pci_unmap_addr(&tx->info[idx],
2203 bus), len,
2204 PCI_DMA_TODEVICE);
2205 pci_unmap_len_set(&tx->info[idx], len, 0);
2206 tx->info[idx].skb = NULL;
2207 }
2208 idx = (idx + 1) & tx->mask;
2209 } while (idx != last_idx);
89114afd 2210 if (skb_is_gso(skb)) {
0da34b6d
BG		 2211 printk(KERN_ERR
2212 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2213 mgp->dev->name);
2214 goto drop;
2215 }
2216
bec0e859 2217 if (skb_linearize(skb))
0da34b6d
BG		 2218 goto drop;
2219
2220 mgp->tx_linearized++;
2221 goto again;
2222
2223drop:
2224 dev_kfree_skb_any(skb);
2225 mgp->stats.tx_dropped += 1;
2226 return 0;
2227
2228}
2229
2230static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2231{
2232 struct myri10ge_priv *mgp = netdev_priv(dev);
2233 return &mgp->stats;
2234}
2235
2236static void myri10ge_set_multicast_list(struct net_device *dev)
2237{
85a7ea1b
BG		 2238 struct myri10ge_cmd cmd;
2239 struct myri10ge_priv *mgp;
2240 struct dev_mc_list *mc_list;
6250223e 2241 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 2242 int err;
2243
2244 mgp = netdev_priv(dev);
0da34b6d
BG		 2245 /* can be called from atomic contexts,
2246 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2247 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2248
2249 /* This firmware is known to not support multicast */
2250 if (!mgp->fw_multicast_support)
2251 return;
2252
2253 /* Disable multicast filtering */
2254
2255 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2256 if (err != 0) {
2257 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2258 " error status: %d\n", dev->name, err);
2259 goto abort;
2260 }
2261
2262 if (dev->flags & IFF_ALLMULTI) {
2263 /* request to disable multicast filtering, so quit here */
2264 return;
2265 }
2266
2267 /* Flush the filters */
2268
2269 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2270 &cmd, 1);
2271 if (err != 0) {
2272 printk(KERN_ERR
2273 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2274 ", error status: %d\n", dev->name, err);
2275 goto abort;
2276 }
2277
2278 /* Walk the multicast list, and add each address */
2279 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2280 memcpy(data, &mc_list->dmi_addr, 6);
2281 cmd.data0 = ntohl(data[0]);
2282 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2283 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2284 &cmd, 1);
2285
2286 if (err != 0) {
2287 printk(KERN_ERR "myri10ge: %s: Failed "
2288 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2289 "%d\t", dev->name, err);
2290 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2291 ((unsigned char *)&mc_list->dmi_addr)[0],
2292 ((unsigned char *)&mc_list->dmi_addr)[1],
2293 ((unsigned char *)&mc_list->dmi_addr)[2],
2294 ((unsigned char *)&mc_list->dmi_addr)[3],
2295 ((unsigned char *)&mc_list->dmi_addr)[4],
2296 ((unsigned char *)&mc_list->dmi_addr)[5]
2297 );
2298 goto abort;
2299 }
2300 }
2301 /* Enable multicast filtering */
2302 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2303 if (err != 0) {
2304 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2305 "error status: %d\n", dev->name, err);
2306 goto abort;
2307 }
2308
2309 return;
2310
2311abort:
2312 return;
0da34b6d
BG		 2313}
2314
2315static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2316{
2317 struct sockaddr *sa = addr;
2318 struct myri10ge_priv *mgp = netdev_priv(dev);
2319 int status;
2320
2321 if (!is_valid_ether_addr(sa->sa_data))
2322 return -EADDRNOTAVAIL;
2323
2324 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2325 if (status != 0) {
2326 printk(KERN_ERR
2327 "myri10ge: %s: changing mac address failed with %d\n",
2328 dev->name, status);
2329 return status;
2330 }
2331
2332 /* change the dev structure */
2333 memcpy(dev->dev_addr, sa->sa_data, 6);
2334 return 0;
2335}
2336
2337static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2338{
2339 struct myri10ge_priv *mgp = netdev_priv(dev);
2340 int error = 0;
2341
2342 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2343 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2344 dev->name, new_mtu);
2345 return -EINVAL;
2346 }
2347 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2348 dev->name, dev->mtu, new_mtu);
2349 if (mgp->running) {
2350 /* if we change the mtu on an active device, we must
2351 * reset the device so the firmware sees the change */
2352 myri10ge_close(dev);
2353 dev->mtu = new_mtu;
2354 myri10ge_open(dev);
2355 } else
2356 dev->mtu = new_mtu;
2357
2358 return error;
2359}
2360
2361/*
2362 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2363 * Only do it if the bridge is a root port since we don't want to disturb
2364 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2365 */
2366
0da34b6d
BG		 2367static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2368{
2369 struct pci_dev *bridge = mgp->pdev->bus->self;
2370 struct device *dev = &mgp->pdev->dev;
2371 unsigned cap;
2372 unsigned err_cap;
2373 u16 val;
2374 u8 ext_type;
2375 int ret;
2376
2377 if (!myri10ge_ecrc_enable || !bridge)
2378 return;
2379
2380 /* check that the bridge is a root port */
2381 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2382 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2383 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2384 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2385 if (myri10ge_ecrc_enable > 1) {
2386 struct pci_dev *old_bridge = bridge;
2387
2388 /* Walk the hierarchy up to the root port
2389 * where ECRC has to be enabled */
2390 do {
2391 bridge = bridge->bus->self;
2392 if (!bridge) {
2393 dev_err(dev,
2394 "Failed to find root port"
2395 " to force ECRC\n");
2396 return;
2397 }
2398 cap =
2399 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2400 pci_read_config_word(bridge,
2401 cap + PCI_CAP_FLAGS, &val);
2402 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2403 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2404
2405 dev_info(dev,
2406 "Forcing ECRC on non-root port %s"
2407 " (enabling on root port %s)\n",
2408 pci_name(old_bridge), pci_name(bridge));
2409 } else {
2410 dev_err(dev,
2411 "Not enabling ECRC on non-root port %s\n",
2412 pci_name(bridge));
2413 return;
2414 }
2415 }
2416
2417 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2418 if (!cap)
2419 return;
2420
2421 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2422 if (ret) {
2423 dev_err(dev, "failed reading ext-conf-space of %s\n",
2424 pci_name(bridge));
2425 dev_err(dev, "\t pci=nommconf in use? "
2426 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2427 return;
2428 }
2429 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2430 return;
2431
2432 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2433 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2434 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2435 mgp->tx.boundary = 4096;
2436 mgp->fw_name = myri10ge_fw_aligned;
2437}
2438
2439/*
2440 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2441 * when the PCI-E Completion packets are aligned on an 8-byte
2442 * boundary. Some PCI-E chip sets always align Completion packets; on
2443 * the ones that do not, the alignment can be enforced by enabling
2444 * ECRC generation (if supported).
2445 *
2446 * When PCI-E Completion packets are not aligned, it is actually more
2447 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2448 *
2449 * If the driver can neither enable ECRC nor verify that it has
2450 * already been enabled, then it must use a firmware image which works
2451 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2452 * should also ensure that it never gives the device a Read-DMA which is
2453 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2454 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2455 * firmware image, and set tx.boundary to 4KB.
2456 */
2457
ce7f9368
BG		 2458#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2459#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
0da34b6d
BG		 2460
2461static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2462{
2463 struct pci_dev *bridge = mgp->pdev->bus->self;
2464
2465 mgp->tx.boundary = 2048;
2466 mgp->fw_name = myri10ge_fw_unaligned;
2467
2468 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2469 int link_width, exp_cap;
2470 u16 lnk;
2471
2472 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2473 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2474 link_width = (lnk >> 4) & 0x3f;
2475
0da34b6d
BG		 2476 myri10ge_enable_ecrc(mgp);
2477
ce7f9368
BG		 2478 /* Check to see if Link is less than 8 or if the
2479 * upstream bridge is known to provide aligned
2480 * completions */
2481 if (link_width < 8) {
2482 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2483 link_width);
2484 mgp->tx.boundary = 4096;
2485 mgp->fw_name = myri10ge_fw_aligned;
2486 } else if (bridge &&
2487 /* ServerWorks HT2000/HT1000 */
2488 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2489 && bridge->device ==
2490 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
2491 /* All Intel E5000 PCIE ports */
2492 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2493 && bridge->device >=
2494 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2495 && bridge->device <=
2496 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
0da34b6d
BG		 2497 dev_info(&mgp->pdev->dev,
2498 "Assuming aligned completions (0x%x:0x%x)\n",
2499 bridge->vendor, bridge->device);
2500 mgp->tx.boundary = 4096;
2501 mgp->fw_name = myri10ge_fw_aligned;
2502 }
2503 } else {
2504 if (myri10ge_force_firmware == 1) {
2505 dev_info(&mgp->pdev->dev,
2506 "Assuming aligned completions (forced)\n");
2507 mgp->tx.boundary = 4096;
2508 mgp->fw_name = myri10ge_fw_aligned;
2509 } else {
2510 dev_info(&mgp->pdev->dev,
2511 "Assuming unaligned completions (forced)\n");
2512 mgp->tx.boundary = 2048;
2513 mgp->fw_name = myri10ge_fw_unaligned;
2514 }
2515 }
2516 if (myri10ge_fw_name != NULL) {
2517 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2518 myri10ge_fw_name);
2519 mgp->fw_name = myri10ge_fw_name;
2520 }
2521}
2522
2523static void myri10ge_save_state(struct myri10ge_priv *mgp)
2524{
2525 struct pci_dev *pdev = mgp->pdev;
2526 int cap;
2527
2528 pci_save_state(pdev);
2529 /* now save PCIe and MSI state that Linux will not
2530 * save for us */
2531 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2532 pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &mgp->devctl);
2533 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2534 pci_read_config_word(pdev, cap + PCI_MSI_FLAGS, &mgp->msi_flags);
2535}
2536
2537static void myri10ge_restore_state(struct myri10ge_priv *mgp)
2538{
2539 struct pci_dev *pdev = mgp->pdev;
2540 int cap;
2541
2542 /* restore PCIe and MSI state that linux will not */
2543 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2544 pci_write_config_dword(pdev, cap + PCI_CAP_ID_EXP, mgp->devctl);
2545 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2546 pci_write_config_word(pdev, cap + PCI_MSI_FLAGS, mgp->msi_flags);
2547
2548 pci_restore_state(pdev);
2549}
2550
2551#ifdef CONFIG_PM
2552
2553static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2554{
2555 struct myri10ge_priv *mgp;
2556 struct net_device *netdev;
2557
2558 mgp = pci_get_drvdata(pdev);
2559 if (mgp == NULL)
2560 return -EINVAL;
2561 netdev = mgp->dev;
2562
2563 netif_device_detach(netdev);
2564 if (netif_running(netdev)) {
2565 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2566 rtnl_lock();
2567 myri10ge_close(netdev);
2568 rtnl_unlock();
2569 }
2570 myri10ge_dummy_rdma(mgp, 0);
0da34b6d
BG		 2571 myri10ge_save_state(mgp);
2572 pci_disable_device(pdev);
2573 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2574 return 0;
2575}
2576
2577static int myri10ge_resume(struct pci_dev *pdev)
2578{
2579 struct myri10ge_priv *mgp;
2580 struct net_device *netdev;
2581 int status;
2582 u16 vendor;
2583
2584 mgp = pci_get_drvdata(pdev);
2585 if (mgp == NULL)
2586 return -EINVAL;
2587 netdev = mgp->dev;
2588 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2589 msleep(5); /* give card time to respond */
2590 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2591 if (vendor == 0xffff) {
2592 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2593 mgp->dev->name);
2594 return -EIO;
2595 }
2596 myri10ge_restore_state(mgp);
4c2248cc
BG		 2597
2598 status = pci_enable_device(pdev);
2599 if (status < 0) {
2600 dev_err(&pdev->dev, "failed to enable device\n");
2601 return -EIO;
2602 }
2603
0da34b6d
BG		 2604 pci_set_master(pdev);
2605
0da34b6d 2606 myri10ge_reset(mgp);
013b68bf 2607 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2608
2609 /* Save configuration space to be restored if the
2610 * nic resets due to a parity error */
2611 myri10ge_save_state(mgp);
2612
2613 if (netif_running(netdev)) {
2614 rtnl_lock();
df30a740 2615 status = myri10ge_open(netdev);
0da34b6d 2616 rtnl_unlock();
df30a740
BG		 2617 if (status != 0)
2618 goto abort_with_enabled;
2619
0da34b6d
BG		 2620 }
2621 netif_device_attach(netdev);
2622
2623 return 0;
2624
4c2248cc
BG		 2625abort_with_enabled:
2626 pci_disable_device(pdev);
0da34b6d
BG		 2627 return -EIO;
2628
2629}
2630
2631#endif /* CONFIG_PM */
2632
2633static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2634{
2635 struct pci_dev *pdev = mgp->pdev;
2636 int vs = mgp->vendor_specific_offset;
2637 u32 reboot;
2638
2639 /*enter read32 mode */
2640 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2641
2642 /*read REBOOT_STATUS (0xfffffff0) */
2643 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2644 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2645 return reboot;
2646}
2647
2648/*
2649 * This watchdog is used to check whether the board has suffered
2650 * from a parity error and needs to be recovered.
2651 */
c4028958 2652static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2653{
c4028958 2654 struct myri10ge_priv *mgp =
6250223e 2655 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2656 u32 reboot;
2657 int status;
2658 u16 cmd, vendor;
2659
2660 mgp->watchdog_resets++;
2661 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2662 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2663 /* Bus master DMA disabled? Check to see
2664 * if the card rebooted due to a parity error
2665 * For now, just report it */
2666 reboot = myri10ge_read_reboot(mgp);
2667 printk(KERN_ERR
2668 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2669 mgp->dev->name, reboot);
2670 /*
2671 * A rebooted nic will come back with config space as
2672 * it was after power was applied to PCIe bus.
2673 * Attempt to restore config space which was saved
2674 * when the driver was loaded, or the last time the
2675 * nic was resumed from power saving mode.
2676 */
2677 myri10ge_restore_state(mgp);
7adda30c
BG		 2678
2679 /* save state again for accounting reasons */
2680 myri10ge_save_state(mgp);
2681
0da34b6d
BG		 2682 } else {
2683 /* if we get back -1's from our slot, perhaps somebody
2684 * powered off our card. Don't try to reset it in
2685 * this case */
2686 if (cmd == 0xffff) {
2687 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2688 if (vendor == 0xffff) {
2689 printk(KERN_ERR
2690 "myri10ge: %s: device disappeared!\n",
2691 mgp->dev->name);
2692 return;
2693 }
2694 }
2695 /* Perhaps it is a software error. Try to reset */
2696
2697 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2698 mgp->dev->name);
2699 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2700 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2701 mgp->tx.pkt_start, mgp->tx.pkt_done,
2702 (int)ntohl(mgp->fw_stats->send_done_count));
2703 msleep(2000);
2704 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2705 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2706 mgp->tx.pkt_start, mgp->tx.pkt_done,
2707 (int)ntohl(mgp->fw_stats->send_done_count));
2708 }
2709 rtnl_lock();
2710 myri10ge_close(mgp->dev);
2711 status = myri10ge_load_firmware(mgp);
2712 if (status != 0)
2713 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2714 mgp->dev->name);
2715 else
2716 myri10ge_open(mgp->dev);
2717 rtnl_unlock();
2718}
2719
2720/*
2721 * We use our own timer routine rather than relying upon
2722 * netdev->tx_timeout because we have a very large hardware transmit
2723 * queue. Due to the large queue, the netdev->tx_timeout function
2724 * cannot detect a NIC with a parity error in a timely fashion if the
2725 * NIC is lightly loaded.
2726 */
2727static void myri10ge_watchdog_timer(unsigned long arg)
2728{
2729 struct myri10ge_priv *mgp;
2730
2731 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2732
2733 if (mgp->rx_small.watchdog_needed) {
2734 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2735 mgp->small_bytes + MXGEFW_PAD, 1);
2736 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2737 myri10ge_fill_thresh)
2738 mgp->rx_small.watchdog_needed = 0;
2739 }
2740 if (mgp->rx_big.watchdog_needed) {
2741 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2742 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2743 myri10ge_fill_thresh)
2744 mgp->rx_big.watchdog_needed = 0;
2745 }
2746
0da34b6d 2747 if (mgp->tx.req != mgp->tx.done &&
c54772e7
BG		 2748 mgp->tx.done == mgp->watchdog_tx_done &&
2749 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
0da34b6d
BG		 2750 /* nic seems like it might be stuck.. */
2751 schedule_work(&mgp->watchdog_work);
2752 else
2753 /* rearm timer */
2754 mod_timer(&mgp->watchdog_timer,
2755 jiffies + myri10ge_watchdog_timeout * HZ);
2756
2757 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 2758 mgp->watchdog_tx_req = mgp->tx.req;
0da34b6d
BG		 2759}
2760
2761static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2762{
2763 struct net_device *netdev;
2764 struct myri10ge_priv *mgp;
2765 struct device *dev = &pdev->dev;
2766 size_t bytes;
2767 int i;
2768 int status = -ENXIO;
2769 int cap;
2770 int dac_enabled;
2771 u16 val;
2772
2773 netdev = alloc_etherdev(sizeof(*mgp));
2774 if (netdev == NULL) {
2775 dev_err(dev, "Could not allocate ethernet device\n");
2776 return -ENOMEM;
2777 }
2778
2779 mgp = netdev_priv(netdev);
2780 memset(mgp, 0, sizeof(*mgp));
2781 mgp->dev = netdev;
2782 mgp->pdev = pdev;
2783 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2784 mgp->pause = myri10ge_flow_control;
2785 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 2786 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 2787 init_waitqueue_head(&mgp->down_wq);
2788
2789 if (pci_enable_device(pdev)) {
2790 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2791 status = -ENODEV;
2792 goto abort_with_netdev;
2793 }
2794 myri10ge_select_firmware(mgp);
2795
2796 /* Find the vendor-specific cap so we can check
2797 * the reboot register later on */
2798 mgp->vendor_specific_offset
2799 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2800
2801 /* Set our max read request to 4KB */
2802 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2803 if (cap < 64) {
2804 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2805 goto abort_with_netdev;
2806 }
2807 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2808 if (status != 0) {
2809 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2810 status);
2811 goto abort_with_netdev;
2812 }
2813 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2814 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2815 if (status != 0) {
2816 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2817 status);
2818 goto abort_with_netdev;
2819 }
2820
2821 pci_set_master(pdev);
2822 dac_enabled = 1;
2823 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2824 if (status != 0) {
2825 dac_enabled = 0;
2826 dev_err(&pdev->dev,
2827 "64-bit pci address mask was refused, trying 32-bit");
2828 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2829 }
2830 if (status != 0) {
2831 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2832 goto abort_with_netdev;
2833 }
b10c0668
BG		 2834 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2835 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 2836 if (mgp->cmd == NULL)
2837 goto abort_with_netdev;
2838
b10c0668
BG		 2839 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2840 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 2841 if (mgp->fw_stats == NULL)
2842 goto abort_with_cmd;
2843
2844 mgp->board_span = pci_resource_len(pdev, 0);
2845 mgp->iomem_base = pci_resource_start(pdev, 0);
2846 mgp->mtrr = -1;
2847#ifdef CONFIG_MTRR
2848 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2849 MTRR_TYPE_WRCOMB, 1);
2850#endif
2851 /* Hack. need to get rid of these magic numbers */
2852 mgp->sram_size =
2853 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2854 if (mgp->sram_size > mgp->board_span) {
2855 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2856 mgp->board_span);
2857 goto abort_with_wc;
2858 }
2859 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2860 if (mgp->sram == NULL) {
2861 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2862 mgp->board_span, mgp->iomem_base);
2863 status = -ENXIO;
2864 goto abort_with_wc;
2865 }
2866 memcpy_fromio(mgp->eeprom_strings,
2867 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2868 MYRI10GE_EEPROM_STRINGS_SIZE);
2869 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2870 status = myri10ge_read_mac_addr(mgp);
2871 if (status)
2872 goto abort_with_ioremap;
2873
2874 for (i = 0; i < ETH_ALEN; i++)
2875 netdev->dev_addr[i] = mgp->mac_addr[i];
2876
2877 /* allocate rx done ring */
2878 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2879 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2880 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 2881 if (mgp->rx_done.entry == NULL)
2882 goto abort_with_ioremap;
2883 memset(mgp->rx_done.entry, 0, bytes);
2884
2885 status = myri10ge_load_firmware(mgp);
2886 if (status != 0) {
2887 dev_err(&pdev->dev, "failed to load firmware\n");
2888 goto abort_with_rx_done;
2889 }
2890
2891 status = myri10ge_reset(mgp);
2892 if (status != 0) {
2893 dev_err(&pdev->dev, "failed reset\n");
2894 goto abort_with_firmware;
2895 }
2896
0da34b6d
BG		 2897 pci_set_drvdata(pdev, mgp);
2898 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2899 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2900 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2901 myri10ge_initial_mtu = 68;
2902 netdev->mtu = myri10ge_initial_mtu;
2903 netdev->open = myri10ge_open;
2904 netdev->stop = myri10ge_close;
2905 netdev->hard_start_xmit = myri10ge_xmit;
2906 netdev->get_stats = myri10ge_get_stats;
2907 netdev->base_addr = mgp->iomem_base;
2908 netdev->irq = pdev->irq;
2909 netdev->change_mtu = myri10ge_change_mtu;
2910 netdev->set_multicast_list = myri10ge_set_multicast_list;
2911 netdev->set_mac_address = myri10ge_set_mac_address;
2912 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2913 if (dac_enabled)
2914 netdev->features |= NETIF_F_HIGHDMA;
2915 netdev->poll = myri10ge_poll;
2916 netdev->weight = myri10ge_napi_weight;
2917
2918 /* Save configuration space to be restored if the
2919 * nic resets due to a parity error */
2920 myri10ge_save_state(mgp);
0da34b6d
BG		 2921
2922 /* Setup the watchdog timer */
2923 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2924 (unsigned long)mgp);
2925
2926 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 2927 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 2928 status = register_netdev(netdev);
2929 if (status != 0) {
2930 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 2931 goto abort_with_state;
0da34b6d 2932 }
df30a740 2933 dev_info(dev, "%d, tx bndry %d, fw %s, WC %s\n",
d6020787
BG		 2934 pdev->irq, mgp->tx.boundary, mgp->fw_name,
2935 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
0da34b6d
BG		 2936
2937 return 0;
2938
7adda30c
BG		 2939abort_with_state:
2940 myri10ge_restore_state(mgp);
0da34b6d
BG		 2941
2942abort_with_firmware:
2943 myri10ge_dummy_rdma(mgp, 0);
2944
2945abort_with_rx_done:
2946 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2947 dma_free_coherent(&pdev->dev, bytes,
2948 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 2949
2950abort_with_ioremap:
2951 iounmap(mgp->sram);
2952
2953abort_with_wc:
2954#ifdef CONFIG_MTRR
2955 if (mgp->mtrr >= 0)
2956 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2957#endif
b10c0668
BG		 2958 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2959 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 2960
2961abort_with_cmd:
b10c0668
BG		 2962 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2963 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 2964
2965abort_with_netdev:
2966
2967 free_netdev(netdev);
2968 return status;
2969}
2970
2971/*
2972 * myri10ge_remove
2973 *
2974 * Does what is necessary to shutdown one Myrinet device. Called
2975 * once for each Myrinet card by the kernel when a module is
2976 * unloaded.
2977 */
2978static void myri10ge_remove(struct pci_dev *pdev)
2979{
2980 struct myri10ge_priv *mgp;
2981 struct net_device *netdev;
2982 size_t bytes;
2983
2984 mgp = pci_get_drvdata(pdev);
2985 if (mgp == NULL)
2986 return;
2987
2988 flush_scheduled_work();
2989 netdev = mgp->dev;
2990 unregister_netdev(netdev);
0da34b6d
BG		 2991
2992 myri10ge_dummy_rdma(mgp, 0);
2993
7adda30c
BG		 2994 /* avoid a memory leak */
2995 myri10ge_restore_state(mgp);
2996
0da34b6d 2997 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2998 dma_free_coherent(&pdev->dev, bytes,
2999 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3000
3001 iounmap(mgp->sram);
3002
3003#ifdef CONFIG_MTRR
3004 if (mgp->mtrr >= 0)
3005 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3006#endif
b10c0668
BG		 3007 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3008 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3009
b10c0668
BG		 3010 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3011 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3012
3013 free_netdev(netdev);
3014 pci_set_drvdata(pdev, NULL);
3015}
3016
b10c0668 3017#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
0da34b6d
BG		 3018
3019static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3020 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
0da34b6d
BG		 3021 {0},
3022};
3023
3024static struct pci_driver myri10ge_driver = {
3025 .name = "myri10ge",
3026 .probe = myri10ge_probe,
3027 .remove = myri10ge_remove,
3028 .id_table = myri10ge_pci_tbl,
3029#ifdef CONFIG_PM
3030 .suspend = myri10ge_suspend,
3031 .resume = myri10ge_resume,
3032#endif
3033};
3034
3035static __init int myri10ge_init_module(void)
3036{
3037 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3038 MYRI10GE_VERSION_STR);
3039 return pci_register_driver(&myri10ge_driver);
3040}
3041
3042module_init(myri10ge_init_module);
3043
3044static __exit void myri10ge_cleanup_module(void)
3045{
3046 pci_unregister_driver(&myri10ge_driver);
3047}
3048
3049module_exit(myri10ge_cleanup_module);
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