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myri10ge: cleanup retrieving of firmware capabilities
[mirror_ubuntu-bionic-kernel.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
0da34b6d
BG		 52#include <linux/ip.h>
53#include <linux/inet.h>
54#include <linux/in.h>
55#include <linux/ethtool.h>
56#include <linux/firmware.h>
57#include <linux/delay.h>
58#include <linux/version.h>
59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
e0d7c526 78#define MYRI10GE_VERSION_STR "1.3.2-1.287"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
0da34b6d 105struct myri10ge_rx_buffer_state {
dd50f336
BG		 106 struct page *page;
107 int page_offset;
0da34b6d
BG		 108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110};
111
112struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117};
118
119struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123};
124
125struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 130 struct page *page;
131 dma_addr_t bus;
132 int page_offset;
0da34b6d 133 int cnt;
dd50f336 134 int fill_cnt;
0da34b6d
BG		 135 int alloc_fail;
136 int mask; /* number of rx slots -1 */
dd50f336 137 int watchdog_needed;
0da34b6d
BG		 138};
139
140struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
144 char *req_bytes;
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 147 int req ____cacheline_aligned; /* transmit slots submitted */
148 int pkt_start; /* packets started */
b53bef84
BG		 149 int stop_queue;
150 int linearized;
0da34b6d
BG		 151 int done ____cacheline_aligned; /* transmit slots completed */
152 int pkt_done; /* packets completed */
b53bef84 153 int wake_queue;
0da34b6d
BG		 154};
155
156struct myri10ge_rx_done {
157 struct mcp_slot *entry;
158 dma_addr_t bus;
159 int cnt;
160 int idx;
1e6e9342
AG		 161 struct net_lro_mgr lro_mgr;
162 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 163};
164
b53bef84
BG		 165struct myri10ge_slice_netstats {
166 unsigned long rx_packets;
167 unsigned long tx_packets;
168 unsigned long rx_bytes;
169 unsigned long tx_bytes;
170 unsigned long rx_dropped;
171 unsigned long tx_dropped;
172};
173
174struct myri10ge_slice_state {
0da34b6d
BG		 175 struct myri10ge_tx_buf tx; /* transmit ring */
176 struct myri10ge_rx_buf rx_small;
177 struct myri10ge_rx_buf rx_big;
178 struct myri10ge_rx_done rx_done;
b53bef84
BG		 179 struct net_device *dev;
180 struct napi_struct napi;
181 struct myri10ge_priv *mgp;
182 struct myri10ge_slice_netstats stats;
183 __be32 __iomem *irq_claim;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 int watchdog_tx_done;
187 int watchdog_tx_req;
188};
189
190struct myri10ge_priv {
191 struct myri10ge_slice_state ss;
192 int tx_boundary; /* boundary transmits cannot cross */
193 int running; /* running? */
194 int csum_flag; /* rx_csums? */
0da34b6d 195 int small_bytes;
dd50f336 196 int big_bytes;
fa0a90d9 197 int max_intr_slots;
0da34b6d
BG		 198 struct net_device *dev;
199 struct net_device_stats stats;
b53bef84 200 spinlock_t stats_lock;
0da34b6d
BG		 201 u8 __iomem *sram;
202 int sram_size;
203 unsigned long board_span;
204 unsigned long iomem_base;
40f6cff5 205 __be32 __iomem *irq_deassert;
0da34b6d
BG		 206 char *mac_addr_string;
207 struct mcp_cmd_response *cmd;
208 dma_addr_t cmd_bus;
0da34b6d
BG		 209 struct pci_dev *pdev;
210 int msi_enabled;
66341fff 211 u32 link_state;
0da34b6d
BG		 212 unsigned int rdma_tags_available;
213 int intr_coal_delay;
40f6cff5 214 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 215 int mtrr;
276e26c3 216 int wc_enabled;
0da34b6d
BG		 217 int down_cnt;
218 wait_queue_head_t down_wq;
219 struct work_struct watchdog_work;
220 struct timer_list watchdog_timer;
0da34b6d 221 int watchdog_resets;
b53bef84 222 int watchdog_pause;
0da34b6d
BG		 223 int pause;
224 char *fw_name;
225 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 226 char *product_code_string;
0da34b6d 227 char fw_version[128];
9dc6f0e7
BG		 228 int fw_ver_major;
229 int fw_ver_minor;
230 int fw_ver_tiny;
231 int adopted_rx_filter_bug;
0da34b6d
BG		 232 u8 mac_addr[6]; /* eeprom mac address */
233 unsigned long serial_number;
234 int vendor_specific_offset;
85a7ea1b 235 int fw_multicast_support;
4f93fde0
BG		 236 unsigned long features;
237 u32 max_tso6;
0da34b6d
BG		 238 u32 read_dma;
239 u32 write_dma;
240 u32 read_write_dma;
c58ac5ca
BG		 241 u32 link_changes;
242 u32 msg_enable;
0da34b6d
BG		 243};
244
245static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
246static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
247
248static char *myri10ge_fw_name = NULL;
249module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 250MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d
BG		 251
252static int myri10ge_ecrc_enable = 1;
253module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 254MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d
BG		 255
256static int myri10ge_max_intr_slots = 1024;
257module_param(myri10ge_max_intr_slots, int, S_IRUGO);
d1ce3a0f 258MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots");
0da34b6d
BG		 259
260static int myri10ge_small_bytes = -1; /* -1 == auto */
261module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 262MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 263
264static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 265module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 266MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 267
f761fae1 268static int myri10ge_intr_coal_delay = 75;
0da34b6d 269module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 270MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 271
272static int myri10ge_flow_control = 1;
273module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 274MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 275
276static int myri10ge_deassert_wait = 1;
277module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
278MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 279 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 280
281static int myri10ge_force_firmware = 0;
282module_param(myri10ge_force_firmware, int, S_IRUGO);
283MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 284 "Force firmware to assume aligned completions");
0da34b6d 285
0da34b6d
BG		 286static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
287module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 288MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 289
290static int myri10ge_napi_weight = 64;
291module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 292MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 293
294static int myri10ge_watchdog_timeout = 1;
295module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 296MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 297
298static int myri10ge_max_irq_loops = 1048576;
299module_param(myri10ge_max_irq_loops, int, S_IRUGO);
300MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 301 "Set stuck legacy IRQ detection threshold");
0da34b6d 302
c58ac5ca
BG		 303#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
304
305static int myri10ge_debug = -1; /* defaults above */
306module_param(myri10ge_debug, int, 0);
307MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
308
1e6e9342
AG		 309static int myri10ge_lro = 1;
310module_param(myri10ge_lro, int, S_IRUGO);
d1ce3a0f 311MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
1e6e9342
AG		 312
313static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
314module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 315MODULE_PARM_DESC(myri10ge_lro_max_pkts,
316 "Number of LRO packets to be aggregated");
1e6e9342 317
dd50f336
BG		 318static int myri10ge_fill_thresh = 256;
319module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 320MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 321
f181137f
BG		 322static int myri10ge_reset_recover = 1;
323
f761fae1 324static int myri10ge_wcfifo = 0;
6ebc087a 325module_param(myri10ge_wcfifo, int, S_IRUGO);
d1ce3a0f 326MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
6ebc087a 327
0da34b6d
BG		 328#define MYRI10GE_FW_OFFSET 1024*1024
329#define MYRI10GE_HIGHPART_TO_U32(X) \
330(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
331#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
332
333#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
334
2f76216f 335static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 336static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 337
6250223e 338static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 339{
6250223e 340 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 341}
342
0da34b6d
BG		 343static int
344myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
345 struct myri10ge_cmd *data, int atomic)
346{
347 struct mcp_cmd *buf;
348 char buf_bytes[sizeof(*buf) + 8];
349 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 350 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 351 u32 dma_low, dma_high, result, value;
352 int sleep_total = 0;
353
354 /* ensure buf is aligned to 8 bytes */
355 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
356
357 buf->data0 = htonl(data->data0);
358 buf->data1 = htonl(data->data1);
359 buf->data2 = htonl(data->data2);
360 buf->cmd = htonl(cmd);
361 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
362 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
363
364 buf->response_addr.low = htonl(dma_low);
365 buf->response_addr.high = htonl(dma_high);
40f6cff5 366 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 367 mb();
368 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
369
370 /* wait up to 15ms. Longest command is the DMA benchmark,
371 * which is capped at 5ms, but runs from a timeout handler
372 * that runs every 7.8ms. So a 15ms timeout leaves us with
373 * a 2.2ms margin
374 */
375 if (atomic) {
376 /* if atomic is set, do not sleep,
377 * and try to get the completion quickly
378 * (1ms will be enough for those commands) */
379 for (sleep_total = 0;
380 sleep_total < 1000
40f6cff5 381 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 382 sleep_total += 10) {
0da34b6d 383 udelay(10);
bd2db0cf
BG		 384 mb();
385 }
0da34b6d
BG		 386 } else {
387 /* use msleep for most command */
388 for (sleep_total = 0;
389 sleep_total < 15
40f6cff5 390 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 391 sleep_total++)
392 msleep(1);
393 }
394
395 result = ntohl(response->result);
396 value = ntohl(response->data);
397 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
398 if (result == 0) {
399 data->data0 = value;
400 return 0;
85a7ea1b
BG		 401 } else if (result == MXGEFW_CMD_UNKNOWN) {
402 return -ENOSYS;
5443e9ea
BG		 403 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
404 return -E2BIG;
0da34b6d
BG		 405 } else {
406 dev_err(&mgp->pdev->dev,
407 "command %d failed, result = %d\n",
408 cmd, result);
409 return -ENXIO;
410 }
411 }
412
413 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
414 cmd, result);
415 return -EAGAIN;
416}
417
418/*
419 * The eeprom strings on the lanaiX have the format
420 * SN=x\0
421 * MAC=x:x:x:x:x:x\0
422 * PT:ddd mmm xx xx:xx:xx xx\0
423 * PV:ddd mmm xx xx:xx:xx xx\0
424 */
425static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
426{
427 char *ptr, *limit;
428 int i;
429
430 ptr = mgp->eeprom_strings;
431 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
432
433 while (*ptr != '\0' && ptr < limit) {
434 if (memcmp(ptr, "MAC=", 4) == 0) {
435 ptr += 4;
436 mgp->mac_addr_string = ptr;
437 for (i = 0; i < 6; i++) {
438 if ((ptr + 2) > limit)
439 goto abort;
440 mgp->mac_addr[i] =
441 simple_strtoul(ptr, &ptr, 16);
442 ptr += 1;
443 }
444 }
c0bf8801
BG		 445 if (memcmp(ptr, "PC=", 3) == 0) {
446 ptr += 3;
447 mgp->product_code_string = ptr;
448 }
0da34b6d
BG		 449 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
450 ptr += 3;
451 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
452 }
453 while (ptr < limit && *ptr++) ;
454 }
455
456 return 0;
457
458abort:
459 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
460 return -ENXIO;
461}
462
463/*
464 * Enable or disable periodic RDMAs from the host to make certain
465 * chipsets resend dropped PCIe messages
466 */
467
468static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
469{
470 char __iomem *submit;
f8fd57c1 471 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 472 u32 dma_low, dma_high;
473 int i;
474
475 /* clear confirmation addr */
476 mgp->cmd->data = 0;
477 mb();
478
479 /* send a rdma command to the PCIe engine, and wait for the
480 * response in the confirmation address. The firmware should
481 * write a -1 there to indicate it is alive and well
482 */
483 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
484 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
485
486 buf[0] = htonl(dma_high); /* confirm addr MSW */
487 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 488 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 489 buf[3] = htonl(dma_high); /* dummy addr MSW */
490 buf[4] = htonl(dma_low); /* dummy addr LSW */
491 buf[5] = htonl(enable); /* enable? */
492
e700f9f4 493 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 494
495 myri10ge_pio_copy(submit, &buf, sizeof(buf));
496 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
497 msleep(1);
498 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
499 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
500 (enable ? "enable" : "disable"));
501}
502
503static int
504myri10ge_validate_firmware(struct myri10ge_priv *mgp,
505 struct mcp_gen_header *hdr)
506{
507 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 508
509 /* check firmware type */
510 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
511 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
512 return -EINVAL;
513 }
514
515 /* save firmware version for ethtool */
516 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
517
9dc6f0e7
BG		 518 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
519 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 520
9dc6f0e7
BG		 521 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
522 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 523 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
524 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
525 MXGEFW_VERSION_MINOR);
526 return -EINVAL;
527 }
528 return 0;
529}
530
531static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
532{
533 unsigned crc, reread_crc;
534 const struct firmware *fw;
535 struct device *dev = &mgp->pdev->dev;
536 struct mcp_gen_header *hdr;
537 size_t hdr_offset;
538 int status;
e454358a 539 unsigned i;
0da34b6d
BG		 540
541 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
542 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
543 mgp->fw_name);
544 status = -EINVAL;
545 goto abort_with_nothing;
546 }
547
548 /* check size */
549
550 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
551 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
552 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
553 status = -EINVAL;
554 goto abort_with_fw;
555 }
556
557 /* check id */
40f6cff5 558 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 559 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
560 dev_err(dev, "Bad firmware file\n");
561 status = -EINVAL;
562 goto abort_with_fw;
563 }
564 hdr = (void *)(fw->data + hdr_offset);
565
566 status = myri10ge_validate_firmware(mgp, hdr);
567 if (status != 0)
568 goto abort_with_fw;
569
570 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 571 for (i = 0; i < fw->size; i += 256) {
572 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
573 fw->data + i,
574 min(256U, (unsigned)(fw->size - i)));
575 mb();
576 readb(mgp->sram);
b10c0668 577 }
0da34b6d
BG		 578 /* corruption checking is good for parity recovery and buggy chipset */
579 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
580 reread_crc = crc32(~0, fw->data, fw->size);
581 if (crc != reread_crc) {
582 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
583 (unsigned)fw->size, reread_crc, crc);
584 status = -EIO;
585 goto abort_with_fw;
586 }
587 *size = (u32) fw->size;
588
589abort_with_fw:
590 release_firmware(fw);
591
592abort_with_nothing:
593 return status;
594}
595
596static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
597{
598 struct mcp_gen_header *hdr;
599 struct device *dev = &mgp->pdev->dev;
600 const size_t bytes = sizeof(struct mcp_gen_header);
601 size_t hdr_offset;
602 int status;
603
604 /* find running firmware header */
66341fff 605 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 606
607 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
608 dev_err(dev, "Running firmware has bad header offset (%d)\n",
609 (int)hdr_offset);
610 return -EIO;
611 }
612
613 /* copy header of running firmware from SRAM to host memory to
614 * validate firmware */
615 hdr = kmalloc(bytes, GFP_KERNEL);
616 if (hdr == NULL) {
617 dev_err(dev, "could not malloc firmware hdr\n");
618 return -ENOMEM;
619 }
620 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
621 status = myri10ge_validate_firmware(mgp, hdr);
622 kfree(hdr);
9dc6f0e7
BG		 623
624 /* check to see if adopted firmware has bug where adopting
625 * it will cause broadcasts to be filtered unless the NIC
626 * is kept in ALLMULTI mode */
627 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
628 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
629 mgp->adopted_rx_filter_bug = 1;
630 dev_warn(dev, "Adopting fw %d.%d.%d: "
631 "working around rx filter bug\n",
632 mgp->fw_ver_major, mgp->fw_ver_minor,
633 mgp->fw_ver_tiny);
634 }
0da34b6d
BG		 635 return status;
636}
637
fa0a90d9
BG		 638int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
639{
640 struct myri10ge_cmd cmd;
641 int status;
642
643 /* probe for IPv6 TSO support */
644 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
645 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
646 &cmd, 0);
647 if (status == 0) {
648 mgp->max_tso6 = cmd.data0;
649 mgp->features |= NETIF_F_TSO6;
650 }
651
652 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
653 if (status != 0) {
654 dev_err(&mgp->pdev->dev,
655 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
656 return -ENXIO;
657 }
658
659 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
660
661 return 0;
662}
663
0da34b6d
BG		 664static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
665{
666 char __iomem *submit;
f8fd57c1 667 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 668 u32 dma_low, dma_high, size;
669 int status, i;
670
b10c0668 671 size = 0;
0da34b6d
BG		 672 status = myri10ge_load_hotplug_firmware(mgp, &size);
673 if (status) {
674 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
675
676 /* Do not attempt to adopt firmware if there
677 * was a bad crc */
678 if (status == -EIO)
679 return status;
680
681 status = myri10ge_adopt_running_firmware(mgp);
682 if (status != 0) {
683 dev_err(&mgp->pdev->dev,
684 "failed to adopt running firmware\n");
685 return status;
686 }
687 dev_info(&mgp->pdev->dev,
688 "Successfully adopted running firmware\n");
b53bef84 689 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 690 dev_warn(&mgp->pdev->dev,
691 "Using firmware currently running on NIC"
692 ". For optimal\n");
693 dev_warn(&mgp->pdev->dev,
694 "performance consider loading optimized "
695 "firmware\n");
696 dev_warn(&mgp->pdev->dev, "via hotplug\n");
697 }
698
699 mgp->fw_name = "adopted";
b53bef84 700 mgp->tx_boundary = 2048;
fa0a90d9
BG		 701 myri10ge_dummy_rdma(mgp, 1);
702 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 703 return status;
704 }
705
706 /* clear confirmation addr */
707 mgp->cmd->data = 0;
708 mb();
709
710 /* send a reload command to the bootstrap MCP, and wait for the
711 * response in the confirmation address. The firmware should
712 * write a -1 there to indicate it is alive and well
713 */
714 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
715 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
716
717 buf[0] = htonl(dma_high); /* confirm addr MSW */
718 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 719 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 720
721 /* FIX: All newest firmware should un-protect the bottom of
722 * the sram before handoff. However, the very first interfaces
723 * do not. Therefore the handoff copy must skip the first 8 bytes
724 */
725 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
726 buf[4] = htonl(size - 8); /* length of code */
727 buf[5] = htonl(8); /* where to copy to */
728 buf[6] = htonl(0); /* where to jump to */
729
e700f9f4 730 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 731
732 myri10ge_pio_copy(submit, &buf, sizeof(buf));
733 mb();
734 msleep(1);
735 mb();
736 i = 0;
d93ca2a4
BG		 737 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
738 msleep(1 << i);
0da34b6d
BG		 739 i++;
740 }
741 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
742 dev_err(&mgp->pdev->dev, "handoff failed\n");
743 return -ENXIO;
744 }
9a71db72 745 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 746 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 747
fa0a90d9 748 return status;
0da34b6d
BG		 749}
750
751static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
752{
753 struct myri10ge_cmd cmd;
754 int status;
755
756 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
757 | (addr[2] << 8) | addr[3]);
758
759 cmd.data1 = ((addr[4] << 8) | (addr[5]));
760
761 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
762 return status;
763}
764
765static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
766{
767 struct myri10ge_cmd cmd;
768 int status, ctl;
769
770 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
771 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
772
773 if (status) {
774 printk(KERN_ERR
775 "myri10ge: %s: Failed to set flow control mode\n",
776 mgp->dev->name);
777 return status;
778 }
779 mgp->pause = pause;
780 return 0;
781}
782
783static void
784myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
785{
786 struct myri10ge_cmd cmd;
787 int status, ctl;
788
789 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
790 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
791 if (status)
792 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
793 mgp->dev->name);
794}
795
0d6ac257 796static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 797{
798 struct myri10ge_cmd cmd;
799 int status;
0da34b6d 800 u32 len;
34fdccea
BG		 801 struct page *dmatest_page;
802 dma_addr_t dmatest_bus;
0d6ac257
BG		 803 char *test = " ";
804
805 dmatest_page = alloc_page(GFP_KERNEL);
806 if (!dmatest_page)
807 return -ENOMEM;
808 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
809 DMA_BIDIRECTIONAL);
810
811 /* Run a small DMA test.
812 * The magic multipliers to the length tell the firmware
813 * to do DMA read, write, or read+write tests. The
814 * results are returned in cmd.data0. The upper 16
815 * bits or the return is the number of transfers completed.
816 * The lower 16 bits is the time in 0.5us ticks that the
817 * transfers took to complete.
818 */
819
b53bef84 820 len = mgp->tx_boundary;
0d6ac257
BG		 821
822 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
823 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
824 cmd.data2 = len * 0x10000;
825 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
826 if (status != 0) {
827 test = "read";
828 goto abort;
829 }
830 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
831 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
832 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
833 cmd.data2 = len * 0x1;
834 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
835 if (status != 0) {
836 test = "write";
837 goto abort;
838 }
839 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
840
841 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
842 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
843 cmd.data2 = len * 0x10001;
844 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
845 if (status != 0) {
846 test = "read/write";
847 goto abort;
848 }
849 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
850 (cmd.data0 & 0xffff);
851
852abort:
853 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
854 put_page(dmatest_page);
855
856 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
857 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
858 test, status);
859
860 return status;
861}
862
863static int myri10ge_reset(struct myri10ge_priv *mgp)
864{
865 struct myri10ge_cmd cmd;
866 int status;
867 size_t bytes;
0da34b6d
BG		 868
869 /* try to send a reset command to the card to see if it
870 * is alive */
871 memset(&cmd, 0, sizeof(cmd));
872 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
873 if (status != 0) {
874 dev_err(&mgp->pdev->dev, "failed reset\n");
875 return -ENXIO;
876 }
0d6ac257
BG		 877
878 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0da34b6d
BG		 879
880 /* Now exchange information about interrupts */
881
b53bef84
BG		 882 bytes = myri10ge_max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
883 memset(mgp->ss.rx_done.entry, 0, bytes);
0da34b6d
BG		 884 cmd.data0 = (u32) bytes;
885 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
b53bef84
BG		 886 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->ss.rx_done.bus);
887 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->ss.rx_done.bus);
0da34b6d
BG		 888 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
889
890 status |=
891 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
b53bef84 892 mgp->ss.irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 893 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
894 &cmd, 0);
895 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 896
0da34b6d
BG		 897 status |= myri10ge_send_cmd
898 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 899 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 900 if (status != 0) {
901 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
902 return status;
903 }
40f6cff5 904 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 905
b53bef84 906 memset(mgp->ss.rx_done.entry, 0, bytes);
0da34b6d
BG		 907
908 /* reset mcp/driver shared state back to 0 */
b53bef84
BG		 909 mgp->ss.tx.req = 0;
910 mgp->ss.tx.done = 0;
911 mgp->ss.tx.pkt_start = 0;
912 mgp->ss.tx.pkt_done = 0;
913 mgp->ss.rx_big.cnt = 0;
914 mgp->ss.rx_small.cnt = 0;
915 mgp->ss.rx_done.idx = 0;
916 mgp->ss.rx_done.cnt = 0;
c58ac5ca 917 mgp->link_changes = 0;
0da34b6d 918 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 919 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 920 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 921 return status;
922}
923
924static inline void
925myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
926 struct mcp_kreq_ether_recv *src)
927{
40f6cff5 928 __be32 low;
0da34b6d
BG		 929
930 low = src->addr_low;
40f6cff5 931 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 932 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
933 mb();
934 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 935 mb();
936 src->addr_low = low;
40f6cff5 937 put_be32(low, &dst->addr_low);
0da34b6d
BG		 938 mb();
939}
940
40f6cff5 941static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 942{
943 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
944
40f6cff5 945 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 946 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
947 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
948 skb->csum = hw_csum;
84fa7933 949 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 950 }
951}
952
dd50f336
BG		 953static inline void
954myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
955 struct skb_frag_struct *rx_frags, int len, int hlen)
956{
957 struct skb_frag_struct *skb_frags;
958
959 skb->len = skb->data_len = len;
960 skb->truesize = len + sizeof(struct sk_buff);
961 /* attach the page(s) */
962
963 skb_frags = skb_shinfo(skb)->frags;
964 while (len > 0) {
965 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
966 len -= rx_frags->size;
967 skb_frags++;
968 rx_frags++;
969 skb_shinfo(skb)->nr_frags++;
970 }
971
972 /* pskb_may_pull is not available in irq context, but
973 * skb_pull() (for ether_pad and eth_type_trans()) requires
974 * the beginning of the packet in skb_headlen(), move it
975 * manually */
27d7ff46 976 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 977 skb_shinfo(skb)->frags[0].page_offset += hlen;
978 skb_shinfo(skb)->frags[0].size -= hlen;
979 skb->data_len -= hlen;
980 skb->tail += hlen;
981 skb_pull(skb, MXGEFW_PAD);
982}
983
984static void
985myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
986 int bytes, int watchdog)
987{
988 struct page *page;
989 int idx;
990
991 if (unlikely(rx->watchdog_needed && !watchdog))
992 return;
993
994 /* try to refill entire ring */
995 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
996 idx = rx->fill_cnt & rx->mask;
ae8509b1 997 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 998 /* we can use part of previous page */
999 get_page(rx->page);
1000 } else {
1001 /* we need a new page */
1002 page =
1003 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1004 MYRI10GE_ALLOC_ORDER);
1005 if (unlikely(page == NULL)) {
1006 if (rx->fill_cnt - rx->cnt < 16)
1007 rx->watchdog_needed = 1;
1008 return;
1009 }
1010 rx->page = page;
1011 rx->page_offset = 0;
1012 rx->bus = pci_map_page(mgp->pdev, page, 0,
1013 MYRI10GE_ALLOC_SIZE,
1014 PCI_DMA_FROMDEVICE);
1015 }
1016 rx->info[idx].page = rx->page;
1017 rx->info[idx].page_offset = rx->page_offset;
1018 /* note that this is the address of the start of the
1019 * page */
1020 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1021 rx->shadow[idx].addr_low =
1022 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1023 rx->shadow[idx].addr_high =
1024 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1025
1026 /* start next packet on a cacheline boundary */
1027 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1028
1029#if MYRI10GE_ALLOC_SIZE > 4096
1030 /* don't cross a 4KB boundary */
1031 if ((rx->page_offset >> 12) !=
1032 ((rx->page_offset + bytes - 1) >> 12))
1033 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1034#endif
dd50f336
BG		 1035 rx->fill_cnt++;
1036
1037 /* copy 8 descriptors to the firmware at a time */
1038 if ((idx & 7) == 7) {
1039 if (rx->wc_fifo == NULL)
1040 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1041 &rx->shadow[idx - 7]);
1042 else {
1043 mb();
1044 myri10ge_pio_copy(rx->wc_fifo,
1045 &rx->shadow[idx - 7], 64);
1046 }
1047 }
1048 }
1049}
1050
1051static inline void
1052myri10ge_unmap_rx_page(struct pci_dev *pdev,
1053 struct myri10ge_rx_buffer_state *info, int bytes)
1054{
1055 /* unmap the recvd page if we're the only or last user of it */
1056 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1057 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1058 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1059 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1060 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1061 }
1062}
1063
1064#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1065 * page into an skb */
1066
1067static inline int
b53bef84 1068myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
52ea6fb3 1069 int bytes, int len, __wsum csum)
dd50f336 1070{
b53bef84 1071 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1072 struct sk_buff *skb;
1073 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1074 int i, idx, hlen, remainder;
1075 struct pci_dev *pdev = mgp->pdev;
1076 struct net_device *dev = mgp->dev;
1077 u8 *va;
1078
1079 len += MXGEFW_PAD;
1080 idx = rx->cnt & rx->mask;
1081 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1082 prefetch(va);
1083 /* Fill skb_frag_struct(s) with data from our receive */
1084 for (i = 0, remainder = len; remainder > 0; i++) {
1085 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1086 rx_frags[i].page = rx->info[idx].page;
1087 rx_frags[i].page_offset = rx->info[idx].page_offset;
1088 if (remainder < MYRI10GE_ALLOC_SIZE)
1089 rx_frags[i].size = remainder;
1090 else
1091 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1092 rx->cnt++;
1093 idx = rx->cnt & rx->mask;
1094 remainder -= MYRI10GE_ALLOC_SIZE;
1095 }
1096
1e6e9342
AG		 1097 if (mgp->csum_flag && myri10ge_lro) {
1098 rx_frags[0].page_offset += MXGEFW_PAD;
1099 rx_frags[0].size -= MXGEFW_PAD;
1100 len -= MXGEFW_PAD;
b53bef84 1101 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
66341fff 1102 len, len,
b53bef84
BG		 1103 /* opaque, will come back in get_frag_header */
1104 (void *)(__force unsigned long)csum, csum);
1e6e9342
AG		 1105 return 1;
1106 }
1107
dd50f336
BG		 1108 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1109
e636b2ea
BG		 1110 /* allocate an skb to attach the page(s) to. This is done
1111 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1112
1113 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1114 if (unlikely(skb == NULL)) {
1115 mgp->stats.rx_dropped++;
1116 do {
1117 i--;
1118 put_page(rx_frags[i].page);
1119 } while (i != 0);
1120 return 0;
1121 }
1122
1123 /* Attach the pages to the skb, and trim off any padding */
1124 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1125 if (skb_shinfo(skb)->frags[0].size <= 0) {
1126 put_page(skb_shinfo(skb)->frags[0].page);
1127 skb_shinfo(skb)->nr_frags = 0;
1128 }
1129 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1130
1131 if (mgp->csum_flag) {
1132 if ((skb->protocol == htons(ETH_P_IP)) ||
1133 (skb->protocol == htons(ETH_P_IPV6))) {
1134 skb->csum = csum;
1135 skb->ip_summed = CHECKSUM_COMPLETE;
1136 } else
1137 myri10ge_vlan_ip_csum(skb, csum);
1138 }
1139 netif_receive_skb(skb);
1140 dev->last_rx = jiffies;
1141 return 1;
1142}
1143
b53bef84
BG		 1144static inline void
1145myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1146{
b53bef84
BG		 1147 struct pci_dev *pdev = ss->mgp->pdev;
1148 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1149 struct sk_buff *skb;
1150 int idx, len;
0da34b6d
BG		 1151
1152 while (tx->pkt_done != mcp_index) {
1153 idx = tx->done & tx->mask;
1154 skb = tx->info[idx].skb;
1155
1156 /* Mark as free */
1157 tx->info[idx].skb = NULL;
1158 if (tx->info[idx].last) {
1159 tx->pkt_done++;
1160 tx->info[idx].last = 0;
1161 }
1162 tx->done++;
1163 len = pci_unmap_len(&tx->info[idx], len);
1164 pci_unmap_len_set(&tx->info[idx], len, 0);
1165 if (skb) {
b53bef84
BG		 1166 ss->stats.tx_bytes += skb->len;
1167 ss->stats.tx_packets++;
0da34b6d
BG		 1168 dev_kfree_skb_irq(skb);
1169 if (len)
1170 pci_unmap_single(pdev,
1171 pci_unmap_addr(&tx->info[idx],
1172 bus), len,
1173 PCI_DMA_TODEVICE);
1174 } else {
1175 if (len)
1176 pci_unmap_page(pdev,
1177 pci_unmap_addr(&tx->info[idx],
1178 bus), len,
1179 PCI_DMA_TODEVICE);
1180 }
0da34b6d
BG		 1181 }
1182 /* start the queue if we've stopped it */
b53bef84 1183 if (netif_queue_stopped(ss->dev)
0da34b6d 1184 && tx->req - tx->done < (tx->mask >> 1)) {
b53bef84
BG		 1185 tx->wake_queue++;
1186 netif_wake_queue(ss->dev);
0da34b6d
BG		 1187 }
1188}
1189
b53bef84
BG		 1190static inline int
1191myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1192{
b53bef84
BG		 1193 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1194 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1195 unsigned long rx_bytes = 0;
1196 unsigned long rx_packets = 0;
1197 unsigned long rx_ok;
1198
1199 int idx = rx_done->idx;
1200 int cnt = rx_done->cnt;
bea3348e 1201 int work_done = 0;
0da34b6d 1202 u16 length;
40f6cff5 1203 __wsum checksum;
0da34b6d 1204
c956a240 1205 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1206 length = ntohs(rx_done->entry[idx].length);
1207 rx_done->entry[idx].length = 0;
40f6cff5 1208 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1209 if (length <= mgp->small_bytes)
b53bef84 1210 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
52ea6fb3
BG		 1211 mgp->small_bytes,
1212 length, checksum);
0da34b6d 1213 else
b53bef84 1214 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
52ea6fb3
BG		 1215 mgp->big_bytes,
1216 length, checksum);
0da34b6d
BG		 1217 rx_packets += rx_ok;
1218 rx_bytes += rx_ok * (unsigned long)length;
1219 cnt++;
1220 idx = cnt & (myri10ge_max_intr_slots - 1);
c956a240 1221 work_done++;
0da34b6d
BG		 1222 }
1223 rx_done->idx = idx;
1224 rx_done->cnt = cnt;
b53bef84
BG		 1225 ss->stats.rx_packets += rx_packets;
1226 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1227
1e6e9342
AG		 1228 if (myri10ge_lro)
1229 lro_flush_all(&rx_done->lro_mgr);
1230
c7dab99b 1231 /* restock receive rings if needed */
b53bef84
BG		 1232 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1233 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1234 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1235 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1236 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1237
bea3348e 1238 return work_done;
0da34b6d
BG		 1239}
1240
1241static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1242{
b53bef84 1243 struct mcp_irq_data *stats = mgp->ss.fw_stats;
0da34b6d
BG		 1244
1245 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1246 unsigned link_up = ntohl(stats->link_up);
1247 if (mgp->link_state != link_up) {
1248 mgp->link_state = link_up;
1249
1250 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1251 if (netif_msg_link(mgp))
1252 printk(KERN_INFO
1253 "myri10ge: %s: link up\n",
1254 mgp->dev->name);
0da34b6d 1255 netif_carrier_on(mgp->dev);
c58ac5ca 1256 mgp->link_changes++;
0da34b6d 1257 } else {
c58ac5ca
BG		 1258 if (netif_msg_link(mgp))
1259 printk(KERN_INFO
798a95db
BG		 1260 "myri10ge: %s: link %s\n",
1261 mgp->dev->name,
1262 (link_up == MXGEFW_LINK_MYRINET ?
1263 "mismatch (Myrinet detected)" :
1264 "down"));
0da34b6d 1265 netif_carrier_off(mgp->dev);
c58ac5ca 1266 mgp->link_changes++;
0da34b6d
BG		 1267 }
1268 }
1269 if (mgp->rdma_tags_available !=
b53bef84 1270 ntohl(stats->rdma_tags_available)) {
0da34b6d 1271 mgp->rdma_tags_available =
b53bef84 1272 ntohl(stats->rdma_tags_available);
0da34b6d
BG		 1273 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1274 "%d tags left\n", mgp->dev->name,
1275 mgp->rdma_tags_available);
1276 }
1277 mgp->down_cnt += stats->link_down;
1278 if (stats->link_down)
1279 wake_up(&mgp->down_wq);
1280 }
1281}
1282
bea3348e 1283static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1284{
b53bef84
BG		 1285 struct myri10ge_slice_state *ss =
1286 container_of(napi, struct myri10ge_slice_state, napi);
1287 struct net_device *netdev = ss->mgp->dev;
bea3348e 1288 int work_done;
0da34b6d
BG		 1289
1290 /* process as many rx events as NAPI will allow */
b53bef84 1291 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1292
4ec24119 1293 if (work_done < budget) {
bea3348e 1294 netif_rx_complete(netdev, napi);
b53bef84 1295 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1296 }
bea3348e 1297 return work_done;
0da34b6d
BG		 1298}
1299
7d12e780 1300static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1301{
b53bef84
BG		 1302 struct myri10ge_slice_state *ss = arg;
1303 struct myri10ge_priv *mgp = ss->mgp;
1304 struct mcp_irq_data *stats = ss->fw_stats;
1305 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1306 u32 send_done_count;
1307 int i;
1308
1309 /* make sure it is our IRQ, and that the DMA has finished */
1310 if (unlikely(!stats->valid))
1311 return (IRQ_NONE);
1312
1313 /* low bit indicates receives are present, so schedule
1314 * napi poll handler */
1315 if (stats->valid & 1)
b53bef84 1316 netif_rx_schedule(ss->dev, &ss->napi);
0da34b6d
BG		 1317
1318 if (!mgp->msi_enabled) {
40f6cff5 1319 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1320 if (!myri10ge_deassert_wait)
1321 stats->valid = 0;
1322 mb();
1323 } else
1324 stats->valid = 0;
1325
1326 /* Wait for IRQ line to go low, if using INTx */
1327 i = 0;
1328 while (1) {
1329 i++;
1330 /* check for transmit completes and receives */
1331 send_done_count = ntohl(stats->send_done_count);
1332 if (send_done_count != tx->pkt_done)
b53bef84 1333 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d
BG		 1334 if (unlikely(i > myri10ge_max_irq_loops)) {
1335 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1336 mgp->dev->name);
1337 stats->valid = 0;
1338 schedule_work(&mgp->watchdog_work);
1339 }
1340 if (likely(stats->valid == 0))
1341 break;
1342 cpu_relax();
1343 barrier();
1344 }
1345
1346 myri10ge_check_statblock(mgp);
1347
b53bef84 1348 put_be32(htonl(3), ss->irq_claim + 1);
0da34b6d
BG		 1349 return (IRQ_HANDLED);
1350}
1351
1352static int
1353myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1354{
c0bf8801
BG		 1355 struct myri10ge_priv *mgp = netdev_priv(netdev);
1356 char *ptr;
1357 int i;
1358
0da34b6d
BG		 1359 cmd->autoneg = AUTONEG_DISABLE;
1360 cmd->speed = SPEED_10000;
1361 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1362
1363 /*
1364 * parse the product code to deterimine the interface type
1365 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1366 * after the 3rd dash in the driver's cached copy of the
1367 * EEPROM's product code string.
1368 */
1369 ptr = mgp->product_code_string;
1370 if (ptr == NULL) {
1371 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
99f5f87e 1372 netdev->name);
c0bf8801
BG		 1373 return 0;
1374 }
1375 for (i = 0; i < 3; i++, ptr++) {
1376 ptr = strchr(ptr, '-');
1377 if (ptr == NULL) {
1378 printk(KERN_ERR "myri10ge: %s: Invalid product "
1379 "code %s\n", netdev->name,
1380 mgp->product_code_string);
1381 return 0;
1382 }
1383 }
1384 if (*ptr == 'R' || *ptr == 'Q') {
1385 /* We've found either an XFP or quad ribbon fiber */
1386 cmd->port = PORT_FIBRE;
1387 }
0da34b6d
BG		 1388 return 0;
1389}
1390
1391static void
1392myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1393{
1394 struct myri10ge_priv *mgp = netdev_priv(netdev);
1395
1396 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1397 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1398 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1399 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1400}
1401
1402static int
1403myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1404{
1405 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1406
0da34b6d
BG		 1407 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1408 return 0;
1409}
1410
1411static int
1412myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1413{
1414 struct myri10ge_priv *mgp = netdev_priv(netdev);
1415
1416 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1417 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1418 return 0;
1419}
1420
1421static void
1422myri10ge_get_pauseparam(struct net_device *netdev,
1423 struct ethtool_pauseparam *pause)
1424{
1425 struct myri10ge_priv *mgp = netdev_priv(netdev);
1426
1427 pause->autoneg = 0;
1428 pause->rx_pause = mgp->pause;
1429 pause->tx_pause = mgp->pause;
1430}
1431
1432static int
1433myri10ge_set_pauseparam(struct net_device *netdev,
1434 struct ethtool_pauseparam *pause)
1435{
1436 struct myri10ge_priv *mgp = netdev_priv(netdev);
1437
1438 if (pause->tx_pause != mgp->pause)
1439 return myri10ge_change_pause(mgp, pause->tx_pause);
1440 if (pause->rx_pause != mgp->pause)
1441 return myri10ge_change_pause(mgp, pause->tx_pause);
1442 if (pause->autoneg != 0)
1443 return -EINVAL;
1444 return 0;
1445}
1446
1447static void
1448myri10ge_get_ringparam(struct net_device *netdev,
1449 struct ethtool_ringparam *ring)
1450{
1451 struct myri10ge_priv *mgp = netdev_priv(netdev);
1452
b53bef84
BG		 1453 ring->rx_mini_max_pending = mgp->ss.rx_small.mask + 1;
1454 ring->rx_max_pending = mgp->ss.rx_big.mask + 1;
0da34b6d 1455 ring->rx_jumbo_max_pending = 0;
b53bef84 1456 ring->tx_max_pending = mgp->ss.rx_small.mask + 1;
0da34b6d
BG		 1457 ring->rx_mini_pending = ring->rx_mini_max_pending;
1458 ring->rx_pending = ring->rx_max_pending;
1459 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1460 ring->tx_pending = ring->tx_max_pending;
1461}
1462
1463static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1464{
1465 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1466
0da34b6d
BG		 1467 if (mgp->csum_flag)
1468 return 1;
1469 else
1470 return 0;
1471}
1472
1473static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1474{
1475 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1476
0da34b6d
BG		 1477 if (csum_enabled)
1478 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1479 else
1480 mgp->csum_flag = 0;
1481 return 0;
1482}
1483
4f93fde0
BG		 1484static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1485{
1486 struct myri10ge_priv *mgp = netdev_priv(netdev);
1487 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1488
1489 if (tso_enabled)
1490 netdev->features |= flags;
1491 else
1492 netdev->features &= ~flags;
1493 return 0;
1494}
1495
b53bef84 1496static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1497 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1498 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1499 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1500 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1501 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1502 "tx_heartbeat_errors", "tx_window_errors",
1503 /* device-specific stats */
2c1a1088 1504 "tx_boundary", "WC", "irq", "MSI",
0da34b6d 1505 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1506 "serial_number", "watchdog_resets",
c58ac5ca 1507 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1508 "dropped_link_error_or_filtered",
1509 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1510 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1511 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1512 "dropped_no_big_buffer"
1513};
1514
1515static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1516 "----------- slice ---------",
1517 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1518 "rx_small_cnt", "rx_big_cnt",
1519 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1520 "LRO flushed",
1e6e9342 1521 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1522};
1523
1524#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1525#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1526#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1527
1528static void
1529myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1530{
1531 switch (stringset) {
1532 case ETH_SS_STATS:
b53bef84
BG		 1533 memcpy(data, *myri10ge_gstrings_main_stats,
1534 sizeof(myri10ge_gstrings_main_stats));
1535 data += sizeof(myri10ge_gstrings_main_stats);
1536 memcpy(data, *myri10ge_gstrings_slice_stats,
1537 sizeof(myri10ge_gstrings_slice_stats));
1538 data += sizeof(myri10ge_gstrings_slice_stats);
0da34b6d
BG		 1539 break;
1540 }
1541}
1542
b9f2c044 1543static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1544{
b9f2c044
JG		 1545 switch (sset) {
1546 case ETH_SS_STATS:
b53bef84 1547 return MYRI10GE_MAIN_STATS_LEN + MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1548 default:
1549 return -EOPNOTSUPP;
1550 }
0da34b6d
BG		 1551}
1552
1553static void
1554myri10ge_get_ethtool_stats(struct net_device *netdev,
1555 struct ethtool_stats *stats, u64 * data)
1556{
1557 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1558 struct myri10ge_slice_state *ss;
0da34b6d
BG		 1559 int i;
1560
1561 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1562 data[i] = ((unsigned long *)&mgp->stats)[i];
1563
b53bef84 1564 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1565 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1566 data[i++] = (unsigned int)mgp->pdev->irq;
1567 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1568 data[i++] = (unsigned int)mgp->read_dma;
1569 data[i++] = (unsigned int)mgp->write_dma;
1570 data[i++] = (unsigned int)mgp->read_write_dma;
1571 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1572 data[i++] = (unsigned int)mgp->watchdog_resets;
c58ac5ca 1573 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1574
1575 /* firmware stats are useful only in the first slice */
1576 ss = &mgp->ss;
1577 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1578 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1579 data[i++] =
b53bef84
BG		 1580 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1581 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1582 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1583 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1584 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1585 data[i++] =
b53bef84
BG		 1586 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1587 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1588 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1589 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1590 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1591
1592 data[i++] = 0;
1593 data[i++] = (unsigned int)ss->tx.pkt_start;
1594 data[i++] = (unsigned int)ss->tx.pkt_done;
1595 data[i++] = (unsigned int)ss->tx.req;
1596 data[i++] = (unsigned int)ss->tx.done;
1597 data[i++] = (unsigned int)ss->rx_small.cnt;
1598 data[i++] = (unsigned int)ss->rx_big.cnt;
1599 data[i++] = (unsigned int)ss->tx.wake_queue;
1600 data[i++] = (unsigned int)ss->tx.stop_queue;
1601 data[i++] = (unsigned int)ss->tx.linearized;
1602 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1603 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1604 if (ss->rx_done.lro_mgr.stats.flushed)
1605 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1606 ss->rx_done.lro_mgr.stats.flushed;
1e6e9342
AG		 1607 else
1608 data[i++] = 0;
b53bef84 1609 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
0da34b6d
BG		 1610}
1611
c58ac5ca
BG		 1612static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1613{
1614 struct myri10ge_priv *mgp = netdev_priv(netdev);
1615 mgp->msg_enable = value;
1616}
1617
1618static u32 myri10ge_get_msglevel(struct net_device *netdev)
1619{
1620 struct myri10ge_priv *mgp = netdev_priv(netdev);
1621 return mgp->msg_enable;
1622}
1623
7282d491 1624static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1625 .get_settings = myri10ge_get_settings,
1626 .get_drvinfo = myri10ge_get_drvinfo,
1627 .get_coalesce = myri10ge_get_coalesce,
1628 .set_coalesce = myri10ge_set_coalesce,
1629 .get_pauseparam = myri10ge_get_pauseparam,
1630 .set_pauseparam = myri10ge_set_pauseparam,
1631 .get_ringparam = myri10ge_get_ringparam,
1632 .get_rx_csum = myri10ge_get_rx_csum,
1633 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1634 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1635 .set_sg = ethtool_op_set_sg,
4f93fde0 1636 .set_tso = myri10ge_set_tso,
6ffdd071 1637 .get_link = ethtool_op_get_link,
0da34b6d 1638 .get_strings = myri10ge_get_strings,
b9f2c044 1639 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1640 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1641 .set_msglevel = myri10ge_set_msglevel,
1642 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1643};
1644
b53bef84 1645static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1646{
b53bef84 1647 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1648 struct myri10ge_cmd cmd;
b53bef84 1649 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1650 int tx_ring_size, rx_ring_size;
1651 int tx_ring_entries, rx_ring_entries;
1652 int i, status;
1653 size_t bytes;
1654
0da34b6d 1655 /* get ring sizes */
0da34b6d
BG		 1656 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1657 tx_ring_size = cmd.data0;
1658 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1659 if (status != 0)
1660 return status;
0da34b6d
BG		 1661 rx_ring_size = cmd.data0;
1662
1663 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1664 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1665 ss->tx.mask = tx_ring_entries - 1;
1666 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1667
355c7265
BG		 1668 status = -ENOMEM;
1669
0da34b6d
BG		 1670 /* allocate the host shadow rings */
1671
1672 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1673 * sizeof(*ss->tx.req_list);
1674 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1675 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1676 goto abort_with_nothing;
1677
1678 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1679 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1680 ALIGN((unsigned long)ss->tx.req_bytes, 8);
0da34b6d 1681
b53bef84
BG		 1682 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1683 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1684 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1685 goto abort_with_tx_req_bytes;
1686
b53bef84
BG		 1687 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1688 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1689 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1690 goto abort_with_rx_small_shadow;
1691
1692 /* allocate the host info rings */
1693
b53bef84
BG		 1694 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1695 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1696 if (ss->tx.info == NULL)
0da34b6d
BG		 1697 goto abort_with_rx_big_shadow;
1698
b53bef84
BG		 1699 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1700 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1701 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1702 goto abort_with_tx_info;
1703
b53bef84
BG		 1704 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1705 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1706 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1707 goto abort_with_rx_small_info;
1708
1709 /* Fill the receive rings */
b53bef84
BG		 1710 ss->rx_big.cnt = 0;
1711 ss->rx_small.cnt = 0;
1712 ss->rx_big.fill_cnt = 0;
1713 ss->rx_small.fill_cnt = 0;
1714 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1715 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1716 ss->rx_small.watchdog_needed = 0;
1717 ss->rx_big.watchdog_needed = 0;
1718 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1719 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1720
b53bef84 1721 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
c7dab99b 1722 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
b53bef84 1723 dev->name, ss->rx_small.fill_cnt);
c7dab99b 1724 goto abort_with_rx_small_ring;
0da34b6d
BG		 1725 }
1726
b53bef84
BG		 1727 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1728 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
c7dab99b 1729 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
b53bef84 1730 dev->name, ss->rx_big.fill_cnt);
c7dab99b 1731 goto abort_with_rx_big_ring;
0da34b6d
BG		 1732 }
1733
1734 return 0;
1735
1736abort_with_rx_big_ring:
b53bef84
BG		 1737 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1738 int idx = i & ss->rx_big.mask;
1739 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 1740 mgp->big_bytes);
b53bef84 1741 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 1742 }
1743
1744abort_with_rx_small_ring:
b53bef84
BG		 1745 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1746 int idx = i & ss->rx_small.mask;
1747 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 1748 mgp->small_bytes + MXGEFW_PAD);
b53bef84 1749 put_page(ss->rx_small.info[idx].page);
0da34b6d 1750 }
c7dab99b 1751
b53bef84 1752 kfree(ss->rx_big.info);
0da34b6d
BG		 1753
1754abort_with_rx_small_info:
b53bef84 1755 kfree(ss->rx_small.info);
0da34b6d
BG		 1756
1757abort_with_tx_info:
b53bef84 1758 kfree(ss->tx.info);
0da34b6d
BG		 1759
1760abort_with_rx_big_shadow:
b53bef84 1761 kfree(ss->rx_big.shadow);
0da34b6d
BG		 1762
1763abort_with_rx_small_shadow:
b53bef84 1764 kfree(ss->rx_small.shadow);
0da34b6d
BG		 1765
1766abort_with_tx_req_bytes:
b53bef84
BG		 1767 kfree(ss->tx.req_bytes);
1768 ss->tx.req_bytes = NULL;
1769 ss->tx.req_list = NULL;
0da34b6d
BG		 1770
1771abort_with_nothing:
1772 return status;
1773}
1774
b53bef84 1775static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 1776{
b53bef84 1777 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1778 struct sk_buff *skb;
1779 struct myri10ge_tx_buf *tx;
1780 int i, len, idx;
1781
b53bef84
BG		 1782 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1783 idx = i & ss->rx_big.mask;
1784 if (i == ss->rx_big.fill_cnt - 1)
1785 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1786 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 1787 mgp->big_bytes);
b53bef84 1788 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 1789 }
1790
b53bef84
BG		 1791 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1792 idx = i & ss->rx_small.mask;
1793 if (i == ss->rx_small.fill_cnt - 1)
1794 ss->rx_small.info[idx].page_offset =
c7dab99b 1795 MYRI10GE_ALLOC_SIZE;
b53bef84 1796 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 1797 mgp->small_bytes + MXGEFW_PAD);
b53bef84 1798 put_page(ss->rx_small.info[idx].page);
c7dab99b 1799 }
b53bef84 1800 tx = &ss->tx;
0da34b6d
BG		 1801 while (tx->done != tx->req) {
1802 idx = tx->done & tx->mask;
1803 skb = tx->info[idx].skb;
1804
1805 /* Mark as free */
1806 tx->info[idx].skb = NULL;
1807 tx->done++;
1808 len = pci_unmap_len(&tx->info[idx], len);
1809 pci_unmap_len_set(&tx->info[idx], len, 0);
1810 if (skb) {
b53bef84 1811 ss->stats.tx_dropped++;
0da34b6d
BG		 1812 dev_kfree_skb_any(skb);
1813 if (len)
1814 pci_unmap_single(mgp->pdev,
1815 pci_unmap_addr(&tx->info[idx],
1816 bus), len,
1817 PCI_DMA_TODEVICE);
1818 } else {
1819 if (len)
1820 pci_unmap_page(mgp->pdev,
1821 pci_unmap_addr(&tx->info[idx],
1822 bus), len,
1823 PCI_DMA_TODEVICE);
1824 }
1825 }
b53bef84 1826 kfree(ss->rx_big.info);
0da34b6d 1827
b53bef84 1828 kfree(ss->rx_small.info);
0da34b6d 1829
b53bef84 1830 kfree(ss->tx.info);
0da34b6d 1831
b53bef84 1832 kfree(ss->rx_big.shadow);
0da34b6d 1833
b53bef84 1834 kfree(ss->rx_small.shadow);
0da34b6d 1835
b53bef84
BG		 1836 kfree(ss->tx.req_bytes);
1837 ss->tx.req_bytes = NULL;
1838 ss->tx.req_list = NULL;
0da34b6d
BG		 1839}
1840
df30a740
BG		 1841static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1842{
1843 struct pci_dev *pdev = mgp->pdev;
1844 int status;
1845
1846 if (myri10ge_msi) {
1847 status = pci_enable_msi(pdev);
1848 if (status != 0)
1849 dev_err(&pdev->dev,
1850 "Error %d setting up MSI; falling back to xPIC\n",
1851 status);
1852 else
1853 mgp->msi_enabled = 1;
1854 } else {
1855 mgp->msi_enabled = 0;
1856 }
1857 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1858 mgp->dev->name, mgp);
1859 if (status != 0) {
1860 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1861 if (mgp->msi_enabled)
1862 pci_disable_msi(pdev);
1863 }
1864 return status;
1865}
1866
1867static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1868{
1869 struct pci_dev *pdev = mgp->pdev;
1870
1871 free_irq(pdev->irq, mgp);
1872 if (mgp->msi_enabled)
1873 pci_disable_msi(pdev);
1874}
1875
1e6e9342
AG		 1876static int
1877myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1878 void **ip_hdr, void **tcpudp_hdr,
1879 u64 * hdr_flags, void *priv)
1880{
1881 struct ethhdr *eh;
1882 struct vlan_ethhdr *veh;
1883 struct iphdr *iph;
1884 u8 *va = page_address(frag->page) + frag->page_offset;
1885 unsigned long ll_hlen;
66341fff
AV		 1886 /* passed opaque through lro_receive_frags() */
1887 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 1888
1889 /* find the mac header, aborting if not IPv4 */
1890
1891 eh = (struct ethhdr *)va;
1892 *mac_hdr = eh;
1893 ll_hlen = ETH_HLEN;
1894 if (eh->h_proto != htons(ETH_P_IP)) {
1895 if (eh->h_proto == htons(ETH_P_8021Q)) {
1896 veh = (struct vlan_ethhdr *)va;
1897 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1898 return -1;
1899
1900 ll_hlen += VLAN_HLEN;
1901
1902 /*
1903 * HW checksum starts ETH_HLEN bytes into
1904 * frame, so we must subtract off the VLAN
1905 * header's checksum before csum can be used
1906 */
1907 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1908 VLAN_HLEN, 0));
1909 } else {
1910 return -1;
1911 }
1912 }
1913 *hdr_flags = LRO_IPV4;
1914
1915 iph = (struct iphdr *)(va + ll_hlen);
1916 *ip_hdr = iph;
1917 if (iph->protocol != IPPROTO_TCP)
1918 return -1;
1919 *hdr_flags |= LRO_TCP;
1920 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1921
1922 /* verify the IP checksum */
1923 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1924 return -1;
1925
1926 /* verify the checksum */
1927 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1928 ntohs(iph->tot_len) - (iph->ihl << 2),
1929 IPPROTO_TCP, csum)))
1930 return -1;
1931
1932 return 0;
1933}
1934
0da34b6d
BG		 1935static int myri10ge_open(struct net_device *dev)
1936{
b53bef84 1937 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 1938 struct myri10ge_cmd cmd;
1e6e9342 1939 struct net_lro_mgr *lro_mgr;
0da34b6d
BG		 1940 int status, big_pow2;
1941
0da34b6d
BG		 1942 if (mgp->running != MYRI10GE_ETH_STOPPED)
1943 return -EBUSY;
1944
1945 mgp->running = MYRI10GE_ETH_STARTING;
1946 status = myri10ge_reset(mgp);
1947 if (status != 0) {
1948 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1949 goto abort_with_nothing;
0da34b6d
BG		 1950 }
1951
df30a740
BG		 1952 status = myri10ge_request_irq(mgp);
1953 if (status != 0)
1954 goto abort_with_nothing;
1955
0da34b6d
BG		 1956 /* decide what small buffer size to use. For good TCP rx
1957 * performance, it is important to not receive 1514 byte
1958 * frames into jumbo buffers, as it confuses the socket buffer
1959 * accounting code, leading to drops and erratic performance.
1960 */
1961
1962 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1963 /* enough for a TCP header */
1964 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1965 ? (128 - MXGEFW_PAD)
1966 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1967 else
de3c4507
BG		 1968 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1969 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1970
1971 /* Override the small buffer size? */
1972 if (myri10ge_small_bytes > 0)
1973 mgp->small_bytes = myri10ge_small_bytes;
1974
0da34b6d
BG		 1975 /* get the lanai pointers to the send and receive rings */
1976
1977 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
b53bef84 1978 mgp->ss.tx.lanai =
0da34b6d
BG		 1979 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1980
1981 status |=
1982 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
b53bef84 1983 mgp->ss.rx_small.lanai =
0da34b6d
BG		 1984 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1985
1986 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
b53bef84 1987 mgp->ss.rx_big.lanai =
0da34b6d
BG		 1988 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1989
1990 if (status != 0) {
1991 printk(KERN_ERR
1992 "myri10ge: %s: failed to get ring sizes or locations\n",
1993 dev->name);
1994 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1995 goto abort_with_irq;
0da34b6d
BG		 1996 }
1997
276e26c3 1998 if (myri10ge_wcfifo && mgp->wc_enabled) {
b53bef84
BG		 1999 mgp->ss.tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
2000 mgp->ss.rx_small.wc_fifo =
e700f9f4 2001 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
b53bef84 2002 mgp->ss.rx_big.wc_fifo =
e700f9f4 2003 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d 2004 } else {
b53bef84
BG		 2005 mgp->ss.tx.wc_fifo = NULL;
2006 mgp->ss.rx_small.wc_fifo = NULL;
2007 mgp->ss.rx_big.wc_fifo = NULL;
0da34b6d
BG		 2008 }
2009
0da34b6d
BG		 2010 /* Firmware needs the big buff size as a power of 2. Lie and
2011 * tell him the buffer is larger, because we only use 1
2012 * buffer/pkt, and the mtu will prevent overruns.
2013 */
13348bee 2014 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2015 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2016 while (!is_power_of_2(big_pow2))
c7dab99b 2017 big_pow2++;
13348bee 2018 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2019 } else {
2020 big_pow2 = MYRI10GE_ALLOC_SIZE;
2021 mgp->big_bytes = big_pow2;
2022 }
2023
b53bef84 2024 status = myri10ge_allocate_rings(&mgp->ss);
c7dab99b 2025 if (status != 0)
df30a740 2026 goto abort_with_irq;
0da34b6d
BG		 2027
2028 /* now give firmware buffers sizes, and MTU */
2029 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2030 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2031 cmd.data0 = mgp->small_bytes;
2032 status |=
2033 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2034 cmd.data0 = big_pow2;
2035 status |=
2036 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2037 if (status) {
2038 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2039 dev->name);
2040 goto abort_with_rings;
2041 }
2042
b53bef84
BG		 2043 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->ss.fw_stats_bus);
2044 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->ss.fw_stats_bus);
85a7ea1b
BG		 2045 cmd.data2 = sizeof(struct mcp_irq_data);
2046 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2047 if (status == -ENOSYS) {
b53bef84 2048 dma_addr_t bus = mgp->ss.fw_stats_bus;
85a7ea1b
BG		 2049 bus += offsetof(struct mcp_irq_data, send_done_count);
2050 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2051 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2052 status = myri10ge_send_cmd(mgp,
2053 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2054 &cmd, 0);
2055 /* Firmware cannot support multicast without STATS_DMA_V2 */
2056 mgp->fw_multicast_support = 0;
2057 } else {
2058 mgp->fw_multicast_support = 1;
2059 }
0da34b6d
BG		 2060 if (status) {
2061 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
2062 dev->name);
2063 goto abort_with_rings;
2064 }
2065
66341fff 2066 mgp->link_state = ~0U;
0da34b6d
BG		 2067 mgp->rdma_tags_available = 15;
2068
b53bef84 2069 lro_mgr = &mgp->ss.rx_done.lro_mgr;
1e6e9342
AG		 2070 lro_mgr->dev = dev;
2071 lro_mgr->features = LRO_F_NAPI;
2072 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2073 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2074 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
b53bef84 2075 lro_mgr->lro_arr = mgp->ss.rx_done.lro_desc;
1e6e9342
AG		 2076 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2077 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
621544eb 2078 lro_mgr->frag_align_pad = 2;
1e6e9342
AG		 2079 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2080 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2081
b53bef84 2082 napi_enable(&mgp->ss.napi); /* must happen prior to any irq */
0da34b6d
BG		 2083
2084 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2085 if (status) {
2086 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2087 dev->name);
2088 goto abort_with_rings;
2089 }
2090
b53bef84
BG		 2091 mgp->ss.tx.wake_queue = 0;
2092 mgp->ss.tx.stop_queue = 0;
0da34b6d
BG		 2093 mgp->running = MYRI10GE_ETH_RUNNING;
2094 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2095 add_timer(&mgp->watchdog_timer);
2096 netif_wake_queue(dev);
2097 return 0;
2098
2099abort_with_rings:
b53bef84 2100 myri10ge_free_rings(&mgp->ss);
0da34b6d 2101
df30a740
BG		 2102abort_with_irq:
2103 myri10ge_free_irq(mgp);
2104
0da34b6d
BG		 2105abort_with_nothing:
2106 mgp->running = MYRI10GE_ETH_STOPPED;
2107 return -ENOMEM;
2108}
2109
2110static int myri10ge_close(struct net_device *dev)
2111{
b53bef84 2112 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2113 struct myri10ge_cmd cmd;
2114 int status, old_down_cnt;
2115
0da34b6d
BG		 2116 if (mgp->running != MYRI10GE_ETH_RUNNING)
2117 return 0;
2118
b53bef84 2119 if (mgp->ss.tx.req_bytes == NULL)
0da34b6d
BG		 2120 return 0;
2121
2122 del_timer_sync(&mgp->watchdog_timer);
2123 mgp->running = MYRI10GE_ETH_STOPPING;
b53bef84 2124 napi_disable(&mgp->ss.napi);
0da34b6d
BG		 2125 netif_carrier_off(dev);
2126 netif_stop_queue(dev);
2127 old_down_cnt = mgp->down_cnt;
2128 mb();
2129 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2130 if (status)
2131 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2132 dev->name);
2133
2134 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2135 if (old_down_cnt == mgp->down_cnt)
2136 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2137
2138 netif_tx_disable(dev);
df30a740 2139 myri10ge_free_irq(mgp);
b53bef84 2140 myri10ge_free_rings(&mgp->ss);
0da34b6d
BG		 2141
2142 mgp->running = MYRI10GE_ETH_STOPPED;
2143 return 0;
2144}
2145
2146/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2147 * backwards one at a time and handle ring wraps */
2148
2149static inline void
2150myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2151 struct mcp_kreq_ether_send *src, int cnt)
2152{
2153 int idx, starting_slot;
2154 starting_slot = tx->req;
2155 while (cnt > 1) {
2156 cnt--;
2157 idx = (starting_slot + cnt) & tx->mask;
2158 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2159 mb();
2160 }
2161}
2162
2163/*
2164 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2165 * at most 32 bytes at a time, so as to avoid involving the software
2166 * pio handler in the nic. We re-write the first segment's flags
2167 * to mark them valid only after writing the entire chain.
2168 */
2169
2170static inline void
2171myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2172 int cnt)
2173{
2174 int idx, i;
2175 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2176 struct mcp_kreq_ether_send *srcp;
2177 u8 last_flags;
2178
2179 idx = tx->req & tx->mask;
2180
2181 last_flags = src->flags;
2182 src->flags = 0;
2183 mb();
2184 dst = dstp = &tx->lanai[idx];
2185 srcp = src;
2186
2187 if ((idx + cnt) < tx->mask) {
2188 for (i = 0; i < (cnt - 1); i += 2) {
2189 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2190 mb(); /* force write every 32 bytes */
2191 srcp += 2;
2192 dstp += 2;
2193 }
2194 } else {
2195 /* submit all but the first request, and ensure
2196 * that it is submitted below */
2197 myri10ge_submit_req_backwards(tx, src, cnt);
2198 i = 0;
2199 }
2200 if (i < cnt) {
2201 /* submit the first request */
2202 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2203 mb(); /* barrier before setting valid flag */
2204 }
2205
2206 /* re-write the last 32-bits with the valid flags */
2207 src->flags = last_flags;
40f6cff5 2208 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2209 tx->req += cnt;
2210 mb();
2211}
2212
2213static inline void
2214myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2215 struct mcp_kreq_ether_send *src, int cnt)
2216{
2217 tx->req += cnt;
2218 mb();
2219 while (cnt >= 4) {
2220 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2221 mb();
2222 src += 4;
2223 cnt -= 4;
2224 }
2225 if (cnt > 0) {
2226 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2227 * needs to be so that we don't overrun it */
e700f9f4
BG		 2228 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2229 src, 64);
0da34b6d
BG		 2230 mb();
2231 }
2232}
2233
2234/*
2235 * Transmit a packet. We need to split the packet so that a single
b53bef84 2236 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2237 * counting tricky. So rather than try to count segments up front, we
2238 * just give up if there are too few segments to hold a reasonably
2239 * fragmented packet currently available. If we run
2240 * out of segments while preparing a packet for DMA, we just linearize
2241 * it and try again.
2242 */
2243
2244static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2245{
2246 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2247 struct myri10ge_slice_state *ss;
0da34b6d 2248 struct mcp_kreq_ether_send *req;
b53bef84 2249 struct myri10ge_tx_buf *tx;
0da34b6d
BG		 2250 struct skb_frag_struct *frag;
2251 dma_addr_t bus;
40f6cff5
AV		 2252 u32 low;
2253 __be32 high_swapped;
0da34b6d
BG		 2254 unsigned int len;
2255 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2256 u16 pseudo_hdr_offset, cksum_offset;
2257 int cum_len, seglen, boundary, rdma_count;
2258 u8 flags, odd_flag;
2259
b53bef84
BG		 2260 /* always transmit through slot 0 */
2261 ss = &mgp->ss;
2262 tx = &ss->tx;
0da34b6d
BG		 2263again:
2264 req = tx->req_list;
2265 avail = tx->mask - 1 - (tx->req - tx->done);
2266
2267 mss = 0;
2268 max_segments = MXGEFW_MAX_SEND_DESC;
2269
917690cd 2270 if (skb_is_gso(skb)) {
7967168c 2271 mss = skb_shinfo(skb)->gso_size;
917690cd 2272 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2273 }
0da34b6d
BG		 2274
2275 if ((unlikely(avail < max_segments))) {
2276 /* we are out of transmit resources */
b53bef84 2277 tx->stop_queue++;
0da34b6d
BG		 2278 netif_stop_queue(dev);
2279 return 1;
2280 }
2281
2282 /* Setup checksum offloading, if needed */
2283 cksum_offset = 0;
2284 pseudo_hdr_offset = 0;
2285 odd_flag = 0;
2286 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2287 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2288 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2289 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2290 /* If the headers are excessively large, then we must
2291 * fall back to a software checksum */
4f93fde0
BG		 2292 if (unlikely(!mss && (cksum_offset > 255 ||
2293 pseudo_hdr_offset > 127))) {
84fa7933 2294 if (skb_checksum_help(skb))
0da34b6d
BG		 2295 goto drop;
2296 cksum_offset = 0;
2297 pseudo_hdr_offset = 0;
2298 } else {
0da34b6d
BG		 2299 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2300 flags |= MXGEFW_FLAGS_CKSUM;
2301 }
2302 }
2303
2304 cum_len = 0;
2305
0da34b6d
BG		 2306 if (mss) { /* TSO */
2307 /* this removes any CKSUM flag from before */
2308 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2309
2310 /* negative cum_len signifies to the
2311 * send loop that we are still in the
2312 * header portion of the TSO packet.
4f93fde0 2313 * TSO header can be at most 1KB long */
ab6a5bb6 2314 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2315
4f93fde0
BG		 2316 /* for IPv6 TSO, the checksum offset stores the
2317 * TCP header length, to save the firmware from
2318 * the need to parse the headers */
2319 if (skb_is_gso_v6(skb)) {
2320 cksum_offset = tcp_hdrlen(skb);
2321 /* Can only handle headers <= max_tso6 long */
2322 if (unlikely(-cum_len > mgp->max_tso6))
2323 return myri10ge_sw_tso(skb, dev);
2324 }
0da34b6d
BG		 2325 /* for TSO, pseudo_hdr_offset holds mss.
2326 * The firmware figures out where to put
2327 * the checksum by parsing the header. */
40f6cff5 2328 pseudo_hdr_offset = mss;
0da34b6d 2329 } else
0da34b6d
BG		 2330 /* Mark small packets, and pad out tiny packets */
2331 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2332 flags |= MXGEFW_FLAGS_SMALL;
2333
2334 /* pad frames to at least ETH_ZLEN bytes */
2335 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2336 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2337 /* The packet is gone, so we must
2338 * return 0 */
b53bef84 2339 ss->stats.tx_dropped += 1;
0da34b6d
BG		 2340 return 0;
2341 }
2342 /* adjust the len to account for the zero pad
2343 * so that the nic can know how long it is */
2344 skb->len = ETH_ZLEN;
2345 }
2346 }
2347
2348 /* map the skb for DMA */
2349 len = skb->len - skb->data_len;
2350 idx = tx->req & tx->mask;
2351 tx->info[idx].skb = skb;
2352 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2353 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2354 pci_unmap_len_set(&tx->info[idx], len, len);
2355
2356 frag_cnt = skb_shinfo(skb)->nr_frags;
2357 frag_idx = 0;
2358 count = 0;
2359 rdma_count = 0;
2360
2361 /* "rdma_count" is the number of RDMAs belonging to the
2362 * current packet BEFORE the current send request. For
2363 * non-TSO packets, this is equal to "count".
2364 * For TSO packets, rdma_count needs to be reset
2365 * to 0 after a segment cut.
2366 *
2367 * The rdma_count field of the send request is
2368 * the number of RDMAs of the packet starting at
2369 * that request. For TSO send requests with one ore more cuts
2370 * in the middle, this is the number of RDMAs starting
2371 * after the last cut in the request. All previous
2372 * segments before the last cut implicitly have 1 RDMA.
2373 *
2374 * Since the number of RDMAs is not known beforehand,
2375 * it must be filled-in retroactively - after each
2376 * segmentation cut or at the end of the entire packet.
2377 */
2378
2379 while (1) {
2380 /* Break the SKB or Fragment up into pieces which
b53bef84 2381 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2382 low = MYRI10GE_LOWPART_TO_U32(bus);
2383 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2384 while (len) {
2385 u8 flags_next;
2386 int cum_len_next;
2387
2388 if (unlikely(count == max_segments))
2389 goto abort_linearize;
2390
b53bef84
BG		 2391 boundary =
2392 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2393 seglen = boundary - low;
2394 if (seglen > len)
2395 seglen = len;
2396 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2397 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2398 if (mss) { /* TSO */
2399 (req - rdma_count)->rdma_count = rdma_count + 1;
2400
2401 if (likely(cum_len >= 0)) { /* payload */
2402 int next_is_first, chop;
2403
2404 chop = (cum_len_next > mss);
2405 cum_len_next = cum_len_next % mss;
2406 next_is_first = (cum_len_next == 0);
2407 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2408 flags_next |= next_is_first *
2409 MXGEFW_FLAGS_FIRST;
2410 rdma_count |= -(chop | next_is_first);
2411 rdma_count += chop & !next_is_first;
2412 } else if (likely(cum_len_next >= 0)) { /* header ends */
2413 int small;
2414
2415 rdma_count = -1;
2416 cum_len_next = 0;
2417 seglen = -cum_len;
2418 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2419 flags_next = MXGEFW_FLAGS_TSO_PLD |
2420 MXGEFW_FLAGS_FIRST |
2421 (small * MXGEFW_FLAGS_SMALL);
2422 }
2423 }
0da34b6d
BG		 2424 req->addr_high = high_swapped;
2425 req->addr_low = htonl(low);
40f6cff5 2426 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2427 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2428 req->rdma_count = 1;
2429 req->length = htons(seglen);
2430 req->cksum_offset = cksum_offset;
2431 req->flags = flags | ((cum_len & 1) * odd_flag);
2432
2433 low += seglen;
2434 len -= seglen;
2435 cum_len = cum_len_next;
2436 flags = flags_next;
2437 req++;
2438 count++;
2439 rdma_count++;
4f93fde0
BG		 2440 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2441 if (unlikely(cksum_offset > seglen))
2442 cksum_offset -= seglen;
2443 else
2444 cksum_offset = 0;
2445 }
0da34b6d
BG		 2446 }
2447 if (frag_idx == frag_cnt)
2448 break;
2449
2450 /* map next fragment for DMA */
2451 idx = (count + tx->req) & tx->mask;
2452 frag = &skb_shinfo(skb)->frags[frag_idx];
2453 frag_idx++;
2454 len = frag->size;
2455 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2456 len, PCI_DMA_TODEVICE);
2457 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2458 pci_unmap_len_set(&tx->info[idx], len, len);
2459 }
2460
2461 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2462 if (mss)
2463 do {
2464 req--;
2465 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2466 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2467 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2468 idx = ((count - 1) + tx->req) & tx->mask;
2469 tx->info[idx].last = 1;
2470 if (tx->wc_fifo == NULL)
2471 myri10ge_submit_req(tx, tx->req_list, count);
2472 else
2473 myri10ge_submit_req_wc(tx, tx->req_list, count);
2474 tx->pkt_start++;
2475 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2476 tx->stop_queue++;
0da34b6d
BG		 2477 netif_stop_queue(dev);
2478 }
2479 dev->trans_start = jiffies;
2480 return 0;
2481
2482abort_linearize:
2483 /* Free any DMA resources we've alloced and clear out the skb
2484 * slot so as to not trip up assertions, and to avoid a
2485 * double-free if linearizing fails */
2486
2487 last_idx = (idx + 1) & tx->mask;
2488 idx = tx->req & tx->mask;
2489 tx->info[idx].skb = NULL;
2490 do {
2491 len = pci_unmap_len(&tx->info[idx], len);
2492 if (len) {
2493 if (tx->info[idx].skb != NULL)
2494 pci_unmap_single(mgp->pdev,
2495 pci_unmap_addr(&tx->info[idx],
2496 bus), len,
2497 PCI_DMA_TODEVICE);
2498 else
2499 pci_unmap_page(mgp->pdev,
2500 pci_unmap_addr(&tx->info[idx],
2501 bus), len,
2502 PCI_DMA_TODEVICE);
2503 pci_unmap_len_set(&tx->info[idx], len, 0);
2504 tx->info[idx].skb = NULL;
2505 }
2506 idx = (idx + 1) & tx->mask;
2507 } while (idx != last_idx);
89114afd 2508 if (skb_is_gso(skb)) {
0da34b6d
BG		 2509 printk(KERN_ERR
2510 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2511 mgp->dev->name);
2512 goto drop;
2513 }
2514
bec0e859 2515 if (skb_linearize(skb))
0da34b6d
BG		 2516 goto drop;
2517
b53bef84 2518 tx->linearized++;
0da34b6d
BG		 2519 goto again;
2520
2521drop:
2522 dev_kfree_skb_any(skb);
b53bef84 2523 ss->stats.tx_dropped += 1;
0da34b6d
BG		 2524 return 0;
2525
2526}
2527
4f93fde0
BG		 2528static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2529{
2530 struct sk_buff *segs, *curr;
b53bef84 2531 struct myri10ge_priv *mgp = netdev_priv(dev);
4f93fde0
BG		 2532 int status;
2533
2534 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2535 if (IS_ERR(segs))
4f93fde0
BG		 2536 goto drop;
2537
2538 while (segs) {
2539 curr = segs;
2540 segs = segs->next;
2541 curr->next = NULL;
2542 status = myri10ge_xmit(curr, dev);
2543 if (status != 0) {
2544 dev_kfree_skb_any(curr);
2545 if (segs != NULL) {
2546 curr = segs;
2547 segs = segs->next;
2548 curr->next = NULL;
2549 dev_kfree_skb_any(segs);
2550 }
2551 goto drop;
2552 }
2553 }
2554 dev_kfree_skb_any(skb);
2555 return 0;
2556
2557drop:
2558 dev_kfree_skb_any(skb);
2559 mgp->stats.tx_dropped += 1;
2560 return 0;
2561}
2562
0da34b6d
BG		 2563static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2564{
2565 struct myri10ge_priv *mgp = netdev_priv(dev);
2566 return &mgp->stats;
2567}
2568
2569static void myri10ge_set_multicast_list(struct net_device *dev)
2570{
b53bef84 2571 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 2572 struct myri10ge_cmd cmd;
85a7ea1b 2573 struct dev_mc_list *mc_list;
6250223e 2574 __be32 data[2] = { 0, 0 };
85a7ea1b 2575 int err;
0795af57 2576 DECLARE_MAC_BUF(mac);
85a7ea1b 2577
0da34b6d
BG		 2578 /* can be called from atomic contexts,
2579 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2580 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2581
2582 /* This firmware is known to not support multicast */
2f76216f 2583 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2584 return;
2585
2586 /* Disable multicast filtering */
2587
2588 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2589 if (err != 0) {
2590 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2591 " error status: %d\n", dev->name, err);
2592 goto abort;
2593 }
2594
2f76216f 2595 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2596 /* request to disable multicast filtering, so quit here */
2597 return;
2598 }
2599
2600 /* Flush the filters */
2601
2602 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2603 &cmd, 1);
2604 if (err != 0) {
2605 printk(KERN_ERR
2606 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2607 ", error status: %d\n", dev->name, err);
2608 goto abort;
2609 }
2610
2611 /* Walk the multicast list, and add each address */
2612 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2613 memcpy(data, &mc_list->dmi_addr, 6);
2614 cmd.data0 = ntohl(data[0]);
2615 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2616 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2617 &cmd, 1);
2618
2619 if (err != 0) {
2620 printk(KERN_ERR "myri10ge: %s: Failed "
2621 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2622 "%d\t", dev->name, err);
0795af57
JP		 2623 printk(KERN_ERR "MAC %s\n",
2624 print_mac(mac, mc_list->dmi_addr));
85a7ea1b
BG		 2625 goto abort;
2626 }
2627 }
2628 /* Enable multicast filtering */
2629 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2630 if (err != 0) {
2631 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2632 "error status: %d\n", dev->name, err);
2633 goto abort;
2634 }
2635
2636 return;
2637
2638abort:
2639 return;
0da34b6d
BG		 2640}
2641
2642static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2643{
2644 struct sockaddr *sa = addr;
2645 struct myri10ge_priv *mgp = netdev_priv(dev);
2646 int status;
2647
2648 if (!is_valid_ether_addr(sa->sa_data))
2649 return -EADDRNOTAVAIL;
2650
2651 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2652 if (status != 0) {
2653 printk(KERN_ERR
2654 "myri10ge: %s: changing mac address failed with %d\n",
2655 dev->name, status);
2656 return status;
2657 }
2658
2659 /* change the dev structure */
2660 memcpy(dev->dev_addr, sa->sa_data, 6);
2661 return 0;
2662}
2663
2664static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2665{
2666 struct myri10ge_priv *mgp = netdev_priv(dev);
2667 int error = 0;
2668
2669 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2670 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2671 dev->name, new_mtu);
2672 return -EINVAL;
2673 }
2674 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2675 dev->name, dev->mtu, new_mtu);
2676 if (mgp->running) {
2677 /* if we change the mtu on an active device, we must
2678 * reset the device so the firmware sees the change */
2679 myri10ge_close(dev);
2680 dev->mtu = new_mtu;
2681 myri10ge_open(dev);
2682 } else
2683 dev->mtu = new_mtu;
2684
2685 return error;
2686}
2687
2688/*
2689 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2690 * Only do it if the bridge is a root port since we don't want to disturb
2691 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2692 */
2693
0da34b6d
BG		 2694static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2695{
2696 struct pci_dev *bridge = mgp->pdev->bus->self;
2697 struct device *dev = &mgp->pdev->dev;
2698 unsigned cap;
2699 unsigned err_cap;
2700 u16 val;
2701 u8 ext_type;
2702 int ret;
2703
2704 if (!myri10ge_ecrc_enable || !bridge)
2705 return;
2706
2707 /* check that the bridge is a root port */
2708 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2709 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2710 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2711 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2712 if (myri10ge_ecrc_enable > 1) {
eca3fd83 2713 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 2714
2715 /* Walk the hierarchy up to the root port
2716 * where ECRC has to be enabled */
2717 do {
eca3fd83 2718 prev_bridge = bridge;
0da34b6d 2719 bridge = bridge->bus->self;
eca3fd83 2720 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 2721 dev_err(dev,
2722 "Failed to find root port"
2723 " to force ECRC\n");
2724 return;
2725 }
2726 cap =
2727 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2728 pci_read_config_word(bridge,
2729 cap + PCI_CAP_FLAGS, &val);
2730 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2731 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2732
2733 dev_info(dev,
2734 "Forcing ECRC on non-root port %s"
2735 " (enabling on root port %s)\n",
2736 pci_name(old_bridge), pci_name(bridge));
2737 } else {
2738 dev_err(dev,
2739 "Not enabling ECRC on non-root port %s\n",
2740 pci_name(bridge));
2741 return;
2742 }
2743 }
2744
2745 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2746 if (!cap)
2747 return;
2748
2749 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2750 if (ret) {
2751 dev_err(dev, "failed reading ext-conf-space of %s\n",
2752 pci_name(bridge));
2753 dev_err(dev, "\t pci=nommconf in use? "
2754 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2755 return;
2756 }
2757 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2758 return;
2759
2760 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2761 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2762 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 2763}
2764
2765/*
2766 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2767 * when the PCI-E Completion packets are aligned on an 8-byte
2768 * boundary. Some PCI-E chip sets always align Completion packets; on
2769 * the ones that do not, the alignment can be enforced by enabling
2770 * ECRC generation (if supported).
2771 *
2772 * When PCI-E Completion packets are not aligned, it is actually more
2773 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2774 *
2775 * If the driver can neither enable ECRC nor verify that it has
2776 * already been enabled, then it must use a firmware image which works
2777 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2778 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 2779 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0da34b6d 2780 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
b53bef84 2781 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 2782 */
2783
5443e9ea 2784static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 2785{
5443e9ea
BG		 2786 struct pci_dev *pdev = mgp->pdev;
2787 struct device *dev = &pdev->dev;
302d242c 2788 int status;
0da34b6d 2789
b53bef84 2790 mgp->tx_boundary = 4096;
5443e9ea
BG		 2791 /*
2792 * Verify the max read request size was set to 4KB
2793 * before trying the test with 4KB.
2794 */
302d242c
BG		 2795 status = pcie_get_readrq(pdev);
2796 if (status < 0) {
5443e9ea
BG		 2797 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2798 goto abort;
2799 }
302d242c
BG		 2800 if (status != 4096) {
2801 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 2802 mgp->tx_boundary = 2048;
5443e9ea
BG		 2803 }
2804 /*
2805 * load the optimized firmware (which assumes aligned PCIe
2806 * completions) in order to see if it works on this host.
2807 */
2808 mgp->fw_name = myri10ge_fw_aligned;
2809 status = myri10ge_load_firmware(mgp);
2810 if (status != 0) {
2811 goto abort;
2812 }
2813
2814 /*
2815 * Enable ECRC if possible
2816 */
2817 myri10ge_enable_ecrc(mgp);
2818
2819 /*
2820 * Run a DMA test which watches for unaligned completions and
2821 * aborts on the first one seen.
2822 */
2823
2824 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2825 if (status == 0)
2826 return; /* keep the aligned firmware */
2827
2828 if (status != -E2BIG)
2829 dev_warn(dev, "DMA test failed: %d\n", status);
2830 if (status == -ENOSYS)
2831 dev_warn(dev, "Falling back to ethp! "
2832 "Please install up to date fw\n");
2833abort:
2834 /* fall back to using the unaligned firmware */
b53bef84 2835 mgp->tx_boundary = 2048;
0da34b6d
BG		 2836 mgp->fw_name = myri10ge_fw_unaligned;
2837
5443e9ea
BG		 2838}
2839
2840static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2841{
0da34b6d 2842 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2843 int link_width, exp_cap;
2844 u16 lnk;
2845
2846 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2847 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2848 link_width = (lnk >> 4) & 0x3f;
2849
ce7f9368
BG		 2850 /* Check to see if Link is less than 8 or if the
2851 * upstream bridge is known to provide aligned
2852 * completions */
2853 if (link_width < 8) {
2854 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2855 link_width);
b53bef84 2856 mgp->tx_boundary = 4096;
ce7f9368 2857 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 2858 } else {
2859 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 2860 }
2861 } else {
2862 if (myri10ge_force_firmware == 1) {
2863 dev_info(&mgp->pdev->dev,
2864 "Assuming aligned completions (forced)\n");
b53bef84 2865 mgp->tx_boundary = 4096;
0da34b6d
BG		 2866 mgp->fw_name = myri10ge_fw_aligned;
2867 } else {
2868 dev_info(&mgp->pdev->dev,
2869 "Assuming unaligned completions (forced)\n");
b53bef84 2870 mgp->tx_boundary = 2048;
0da34b6d
BG		 2871 mgp->fw_name = myri10ge_fw_unaligned;
2872 }
2873 }
2874 if (myri10ge_fw_name != NULL) {
2875 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2876 myri10ge_fw_name);
2877 mgp->fw_name = myri10ge_fw_name;
2878 }
2879}
2880
0da34b6d 2881#ifdef CONFIG_PM
0da34b6d
BG		 2882static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2883{
2884 struct myri10ge_priv *mgp;
2885 struct net_device *netdev;
2886
2887 mgp = pci_get_drvdata(pdev);
2888 if (mgp == NULL)
2889 return -EINVAL;
2890 netdev = mgp->dev;
2891
2892 netif_device_detach(netdev);
2893 if (netif_running(netdev)) {
2894 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2895 rtnl_lock();
2896 myri10ge_close(netdev);
2897 rtnl_unlock();
2898 }
2899 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2900 pci_save_state(pdev);
0da34b6d 2901 pci_disable_device(pdev);
1a63e846
BG		 2902
2903 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2904}
2905
2906static int myri10ge_resume(struct pci_dev *pdev)
2907{
2908 struct myri10ge_priv *mgp;
2909 struct net_device *netdev;
2910 int status;
2911 u16 vendor;
2912
2913 mgp = pci_get_drvdata(pdev);
2914 if (mgp == NULL)
2915 return -EINVAL;
2916 netdev = mgp->dev;
2917 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2918 msleep(5); /* give card time to respond */
2919 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2920 if (vendor == 0xffff) {
2921 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2922 mgp->dev->name);
2923 return -EIO;
2924 }
83f6e152 2925
1a63e846
BG		 2926 status = pci_restore_state(pdev);
2927 if (status)
2928 return status;
4c2248cc
BG		 2929
2930 status = pci_enable_device(pdev);
1a63e846 2931 if (status) {
4c2248cc 2932 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2933 return status;
4c2248cc
BG		 2934 }
2935
0da34b6d
BG		 2936 pci_set_master(pdev);
2937
0da34b6d 2938 myri10ge_reset(mgp);
013b68bf 2939 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2940
2941 /* Save configuration space to be restored if the
2942 * nic resets due to a parity error */
83f6e152 2943 pci_save_state(pdev);
0da34b6d
BG		 2944
2945 if (netif_running(netdev)) {
2946 rtnl_lock();
df30a740 2947 status = myri10ge_open(netdev);
0da34b6d 2948 rtnl_unlock();
df30a740
BG		 2949 if (status != 0)
2950 goto abort_with_enabled;
2951
0da34b6d
BG		 2952 }
2953 netif_device_attach(netdev);
2954
2955 return 0;
2956
4c2248cc
BG		 2957abort_with_enabled:
2958 pci_disable_device(pdev);
0da34b6d
BG		 2959 return -EIO;
2960
2961}
0da34b6d
BG		 2962#endif /* CONFIG_PM */
2963
2964static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2965{
2966 struct pci_dev *pdev = mgp->pdev;
2967 int vs = mgp->vendor_specific_offset;
2968 u32 reboot;
2969
2970 /*enter read32 mode */
2971 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2972
2973 /*read REBOOT_STATUS (0xfffffff0) */
2974 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2975 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2976 return reboot;
2977}
2978
2979/*
2980 * This watchdog is used to check whether the board has suffered
2981 * from a parity error and needs to be recovered.
2982 */
c4028958 2983static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2984{
c4028958 2985 struct myri10ge_priv *mgp =
6250223e 2986 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 2987 struct myri10ge_tx_buf *tx;
0da34b6d
BG		 2988 u32 reboot;
2989 int status;
2990 u16 cmd, vendor;
2991
2992 mgp->watchdog_resets++;
2993 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2994 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2995 /* Bus master DMA disabled? Check to see
2996 * if the card rebooted due to a parity error
2997 * For now, just report it */
2998 reboot = myri10ge_read_reboot(mgp);
2999 printk(KERN_ERR
f181137f
BG		 3000 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3001 mgp->dev->name, reboot,
3002 myri10ge_reset_recover ? " " : " not");
3003 if (myri10ge_reset_recover == 0)
3004 return;
3005
3006 myri10ge_reset_recover--;
3007
0da34b6d
BG		 3008 /*
3009 * A rebooted nic will come back with config space as
3010 * it was after power was applied to PCIe bus.
3011 * Attempt to restore config space which was saved
3012 * when the driver was loaded, or the last time the
3013 * nic was resumed from power saving mode.
3014 */
83f6e152 3015 pci_restore_state(mgp->pdev);
7adda30c
BG		 3016
3017 /* save state again for accounting reasons */
83f6e152 3018 pci_save_state(mgp->pdev);
7adda30c 3019
0da34b6d
BG		 3020 } else {
3021 /* if we get back -1's from our slot, perhaps somebody
3022 * powered off our card. Don't try to reset it in
3023 * this case */
3024 if (cmd == 0xffff) {
3025 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3026 if (vendor == 0xffff) {
3027 printk(KERN_ERR
3028 "myri10ge: %s: device disappeared!\n",
3029 mgp->dev->name);
3030 return;
3031 }
3032 }
3033 /* Perhaps it is a software error. Try to reset */
3034
3035 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3036 mgp->dev->name);
b53bef84 3037 tx = &mgp->ss.tx;
0da34b6d 3038 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
b53bef84
BG		 3039 mgp->dev->name, tx->req, tx->done,
3040 tx->pkt_start, tx->pkt_done,
3041 (int)ntohl(mgp->ss.fw_stats->send_done_count));
0da34b6d
BG		 3042 msleep(2000);
3043 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
b53bef84
BG		 3044 mgp->dev->name, tx->req, tx->done,
3045 tx->pkt_start, tx->pkt_done,
3046 (int)ntohl(mgp->ss.fw_stats->send_done_count));
0da34b6d
BG		 3047 }
3048 rtnl_lock();
3049 myri10ge_close(mgp->dev);
3050 status = myri10ge_load_firmware(mgp);
3051 if (status != 0)
3052 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3053 mgp->dev->name);
3054 else
3055 myri10ge_open(mgp->dev);
3056 rtnl_unlock();
3057}
3058
3059/*
3060 * We use our own timer routine rather than relying upon
3061 * netdev->tx_timeout because we have a very large hardware transmit
3062 * queue. Due to the large queue, the netdev->tx_timeout function
3063 * cannot detect a NIC with a parity error in a timely fashion if the
3064 * NIC is lightly loaded.
3065 */
3066static void myri10ge_watchdog_timer(unsigned long arg)
3067{
3068 struct myri10ge_priv *mgp;
b53bef84 3069 struct myri10ge_slice_state *ss;
626fda94 3070 u32 rx_pause_cnt;
0da34b6d
BG		 3071
3072 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3073
b53bef84
BG		 3074 rx_pause_cnt = ntohl(mgp->ss.fw_stats->dropped_pause);
3075
3076 ss = &mgp->ss;
3077 if (ss->rx_small.watchdog_needed) {
3078 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 3079 mgp->small_bytes + MXGEFW_PAD, 1);
b53bef84 3080 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
c7dab99b 3081 myri10ge_fill_thresh)
b53bef84 3082 ss->rx_small.watchdog_needed = 0;
c7dab99b 3083 }
b53bef84
BG		 3084 if (ss->rx_big.watchdog_needed) {
3085 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 1);
3086 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
c7dab99b 3087 myri10ge_fill_thresh)
b53bef84 3088 ss->rx_big.watchdog_needed = 0;
c7dab99b
BG		 3089 }
3090
b53bef84
BG		 3091 if (ss->tx.req != ss->tx.done &&
3092 ss->tx.done == ss->watchdog_tx_done &&
3093 ss->watchdog_tx_req != ss->watchdog_tx_done) {
0da34b6d 3094 /* nic seems like it might be stuck.. */
626fda94
BG		 3095 if (rx_pause_cnt != mgp->watchdog_pause) {
3096 if (net_ratelimit())
3097 printk(KERN_WARNING "myri10ge %s:"
3098 "TX paused, check link partner\n",
3099 mgp->dev->name);
3100 } else {
3101 schedule_work(&mgp->watchdog_work);
3102 return;
3103 }
3104 }
3105 /* rearm timer */
3106 mod_timer(&mgp->watchdog_timer,
3107 jiffies + myri10ge_watchdog_timeout * HZ);
b53bef84
BG		 3108 ss->watchdog_tx_done = ss->tx.done;
3109 ss->watchdog_tx_req = ss->tx.req;
626fda94 3110 mgp->watchdog_pause = rx_pause_cnt;
0da34b6d
BG		 3111}
3112
3113static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3114{
3115 struct net_device *netdev;
3116 struct myri10ge_priv *mgp;
3117 struct device *dev = &pdev->dev;
3118 size_t bytes;
3119 int i;
3120 int status = -ENXIO;
0da34b6d 3121 int dac_enabled;
0da34b6d
BG		 3122
3123 netdev = alloc_etherdev(sizeof(*mgp));
3124 if (netdev == NULL) {
3125 dev_err(dev, "Could not allocate ethernet device\n");
3126 return -ENOMEM;
3127 }
3128
b245fb67
MH		 3129 SET_NETDEV_DEV(netdev, &pdev->dev);
3130
0da34b6d 3131 mgp = netdev_priv(netdev);
0da34b6d 3132 mgp->dev = netdev;
b53bef84 3133 netif_napi_add(netdev, &mgp->ss.napi, myri10ge_poll, myri10ge_napi_weight);
0da34b6d
BG		 3134 mgp->pdev = pdev;
3135 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3136 mgp->pause = myri10ge_flow_control;
3137 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3138 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 3139 init_waitqueue_head(&mgp->down_wq);
3140
3141 if (pci_enable_device(pdev)) {
3142 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3143 status = -ENODEV;
3144 goto abort_with_netdev;
3145 }
0da34b6d
BG		 3146
3147 /* Find the vendor-specific cap so we can check
3148 * the reboot register later on */
3149 mgp->vendor_specific_offset
3150 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3151
3152 /* Set our max read request to 4KB */
302d242c 3153 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3154 if (status != 0) {
3155 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3156 status);
3157 goto abort_with_netdev;
3158 }
3159
3160 pci_set_master(pdev);
3161 dac_enabled = 1;
3162 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3163 if (status != 0) {
3164 dac_enabled = 0;
3165 dev_err(&pdev->dev,
898eb71c
JP		 3166 "64-bit pci address mask was refused, "
3167 "trying 32-bit\n");
0da34b6d
BG		 3168 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3169 }
3170 if (status != 0) {
3171 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3172 goto abort_with_netdev;
3173 }
b10c0668
BG		 3174 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3175 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 3176 if (mgp->cmd == NULL)
3177 goto abort_with_netdev;
3178
b53bef84
BG		 3179 mgp->ss.fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3180 &mgp->ss.fw_stats_bus, GFP_KERNEL);
3181 if (mgp->ss.fw_stats == NULL)
0da34b6d
BG		 3182 goto abort_with_cmd;
3183
3184 mgp->board_span = pci_resource_len(pdev, 0);
3185 mgp->iomem_base = pci_resource_start(pdev, 0);
3186 mgp->mtrr = -1;
276e26c3 3187 mgp->wc_enabled = 0;
0da34b6d
BG		 3188#ifdef CONFIG_MTRR
3189 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3190 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3191 if (mgp->mtrr >= 0)
3192 mgp->wc_enabled = 1;
0da34b6d
BG		 3193#endif
3194 /* Hack. need to get rid of these magic numbers */
3195 mgp->sram_size =
3196 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3197 if (mgp->sram_size > mgp->board_span) {
3198 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3199 mgp->board_span);
3200 goto abort_with_wc;
3201 }
3202 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3203 if (mgp->sram == NULL) {
3204 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3205 mgp->board_span, mgp->iomem_base);
3206 status = -ENXIO;
3207 goto abort_with_wc;
3208 }
3209 memcpy_fromio(mgp->eeprom_strings,
3210 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3211 MYRI10GE_EEPROM_STRINGS_SIZE);
3212 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3213 status = myri10ge_read_mac_addr(mgp);
3214 if (status)
3215 goto abort_with_ioremap;
3216
3217 for (i = 0; i < ETH_ALEN; i++)
3218 netdev->dev_addr[i] = mgp->mac_addr[i];
3219
3220 /* allocate rx done ring */
b53bef84
BG		 3221 bytes = myri10ge_max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3222 mgp->ss.rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3223 &mgp->ss.rx_done.bus, GFP_KERNEL);
3224 if (mgp->ss.rx_done.entry == NULL)
0da34b6d 3225 goto abort_with_ioremap;
b53bef84 3226 memset(mgp->ss.rx_done.entry, 0, bytes);
0da34b6d 3227
5443e9ea
BG		 3228 myri10ge_select_firmware(mgp);
3229
0da34b6d
BG		 3230 status = myri10ge_load_firmware(mgp);
3231 if (status != 0) {
3232 dev_err(&pdev->dev, "failed to load firmware\n");
3233 goto abort_with_rx_done;
3234 }
3235
3236 status = myri10ge_reset(mgp);
3237 if (status != 0) {
3238 dev_err(&pdev->dev, "failed reset\n");
3239 goto abort_with_firmware;
3240 }
3241
0da34b6d
BG		 3242 pci_set_drvdata(pdev, mgp);
3243 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3244 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3245 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3246 myri10ge_initial_mtu = 68;
3247 netdev->mtu = myri10ge_initial_mtu;
3248 netdev->open = myri10ge_open;
3249 netdev->stop = myri10ge_close;
3250 netdev->hard_start_xmit = myri10ge_xmit;
3251 netdev->get_stats = myri10ge_get_stats;
3252 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 3253 netdev->change_mtu = myri10ge_change_mtu;
3254 netdev->set_multicast_list = myri10ge_set_multicast_list;
3255 netdev->set_mac_address = myri10ge_set_mac_address;
4f93fde0 3256 netdev->features = mgp->features;
0da34b6d
BG		 3257 if (dac_enabled)
3258 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3259
21d05db1
BG		 3260 /* make sure we can get an irq, and that MSI can be
3261 * setup (if available). Also ensure netdev->irq
3262 * is set to correct value if MSI is enabled */
3263 status = myri10ge_request_irq(mgp);
3264 if (status != 0)
3265 goto abort_with_firmware;
3266 netdev->irq = pdev->irq;
3267 myri10ge_free_irq(mgp);
3268
0da34b6d
BG		 3269 /* Save configuration space to be restored if the
3270 * nic resets due to a parity error */
83f6e152 3271 pci_save_state(pdev);
0da34b6d
BG		 3272
3273 /* Setup the watchdog timer */
3274 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3275 (unsigned long)mgp);
3276
3277 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3278 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3279 status = register_netdev(netdev);
3280 if (status != 0) {
3281 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3282 goto abort_with_state;
0da34b6d 3283 }
21d05db1
BG		 3284 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3285 (mgp->msi_enabled ? "MSI" : "xPIC"),
b53bef84 3286 netdev->irq, mgp->tx_boundary, mgp->fw_name,
276e26c3 3287 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3288
3289 return 0;
3290
7adda30c 3291abort_with_state:
83f6e152 3292 pci_restore_state(pdev);
0da34b6d
BG		 3293
3294abort_with_firmware:
3295 myri10ge_dummy_rdma(mgp, 0);
3296
3297abort_with_rx_done:
b53bef84 3298 bytes = myri10ge_max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
b10c0668 3299 dma_free_coherent(&pdev->dev, bytes,
b53bef84 3300 mgp->ss.rx_done.entry, mgp->ss.rx_done.bus);
0da34b6d
BG		 3301
3302abort_with_ioremap:
3303 iounmap(mgp->sram);
3304
3305abort_with_wc:
3306#ifdef CONFIG_MTRR
3307 if (mgp->mtrr >= 0)
3308 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3309#endif
b53bef84
BG		 3310 dma_free_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3311 mgp->ss.fw_stats, mgp->ss.fw_stats_bus);
0da34b6d
BG		 3312
3313abort_with_cmd:
b10c0668
BG		 3314 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3315 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3316
3317abort_with_netdev:
3318
3319 free_netdev(netdev);
3320 return status;
3321}
3322
3323/*
3324 * myri10ge_remove
3325 *
3326 * Does what is necessary to shutdown one Myrinet device. Called
3327 * once for each Myrinet card by the kernel when a module is
3328 * unloaded.
3329 */
3330static void myri10ge_remove(struct pci_dev *pdev)
3331{
3332 struct myri10ge_priv *mgp;
3333 struct net_device *netdev;
3334 size_t bytes;
3335
3336 mgp = pci_get_drvdata(pdev);
3337 if (mgp == NULL)
3338 return;
3339
3340 flush_scheduled_work();
3341 netdev = mgp->dev;
3342 unregister_netdev(netdev);
0da34b6d
BG		 3343
3344 myri10ge_dummy_rdma(mgp, 0);
3345
7adda30c 3346 /* avoid a memory leak */
83f6e152 3347 pci_restore_state(pdev);
7adda30c 3348
b53bef84 3349 bytes = myri10ge_max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
b10c0668 3350 dma_free_coherent(&pdev->dev, bytes,
b53bef84 3351 mgp->ss.rx_done.entry, mgp->ss.rx_done.bus);
0da34b6d
BG		 3352
3353 iounmap(mgp->sram);
3354
3355#ifdef CONFIG_MTRR
3356 if (mgp->mtrr >= 0)
3357 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3358#endif
b53bef84
BG		 3359 dma_free_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3360 mgp->ss.fw_stats, mgp->ss.fw_stats_bus);
0da34b6d 3361
b10c0668
BG		 3362 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3363 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3364
3365 free_netdev(netdev);
3366 pci_set_drvdata(pdev, NULL);
3367}
3368
b10c0668 3369#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3370#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 3371
3372static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3373 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3374 {PCI_DEVICE
3375 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3376 {0},
3377};
3378
3379static struct pci_driver myri10ge_driver = {
3380 .name = "myri10ge",
3381 .probe = myri10ge_probe,
3382 .remove = myri10ge_remove,
3383 .id_table = myri10ge_pci_tbl,
3384#ifdef CONFIG_PM
3385 .suspend = myri10ge_suspend,
3386 .resume = myri10ge_resume,
3387#endif
3388};
3389
3390static __init int myri10ge_init_module(void)
3391{
3392 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3393 MYRI10GE_VERSION_STR);
3394 return pci_register_driver(&myri10ge_driver);
3395}
3396
3397module_init(myri10ge_init_module);
3398
3399static __exit void myri10ge_cleanup_module(void)
3400{
3401 pci_unregister_driver(&myri10ge_driver);
3402}
3403
3404module_exit(myri10ge_cleanup_module);
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