]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/natsemi.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ehea: fix port_napi_disable/enable
[mirror_ubuntu-jammy-kernel.git] / drivers / net / natsemi.c
CommitLineData
1da177e4
LT		 1/* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
2/*
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
b27a16b7 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
1da177e4
LT		 7
8 This software may be used and distributed according to the terms of
9 the GNU General Public License (GPL), incorporated herein by reference.
10 Drivers based on or derived from this code fall under the GPL and must
11 retain the authorship, copyright and license notice. This file is not
12 a complete program and may only be used when the entire operating
13 system is licensed under the GPL. License for under other terms may be
14 available. Contact the original author for details.
15
16 The original author may be reached as becker@scyld.com, or at
17 Scyld Computing Corporation
18 410 Severn Ave., Suite 210
19 Annapolis MD 21403
20
21 Support information and updates available at
22 http://www.scyld.com/network/netsemi.html
03a8c661 23 [link no longer provides useful info -jgarzik]
1da177e4
LT		 24
25
1da177e4
LT		 26 TODO:
27 * big endian support with CFG:BEM instead of cpu_to_le32
1da177e4
LT		 28*/
29
1da177e4
LT		 30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/string.h>
33#include <linux/timer.h>
34#include <linux/errno.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/etherdevice.h>
41#include <linux/skbuff.h>
42#include <linux/init.h>
43#include <linux/spinlock.h>
44#include <linux/ethtool.h>
45#include <linux/delay.h>
46#include <linux/rtnetlink.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/bitops.h>
b27a16b7 50#include <linux/prefetch.h>
1da177e4
LT		 51#include <asm/processor.h> /* Processor type for cache alignment. */
52#include <asm/io.h>
53#include <asm/irq.h>
54#include <asm/uaccess.h>
55
56#define DRV_NAME "natsemi"
d5b20697
AG		 57#define DRV_VERSION "2.1"
58#define DRV_RELDATE "Sept 11, 2006"
1da177e4
LT		 59
60#define RX_OFFSET 2
61
62/* Updated to recommendations in pci-skeleton v2.03. */
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67#define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
68 NETIF_MSG_LINK | \
69 NETIF_MSG_WOL | \
70 NETIF_MSG_RX_ERR | \
71 NETIF_MSG_TX_ERR)
72static int debug = -1;
73
1da177e4
LT		 74static int mtu;
75
76/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
77 This chip uses a 512 element hash table based on the Ethernet CRC. */
f71e1309 78static const int multicast_filter_limit = 100;
1da177e4
LT		 79
80/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
81 Setting to > 1518 effectively disables this feature. */
82static int rx_copybreak;
83
1a147809
MB		 84static int dspcfg_workaround = 1;
85
1da177e4
LT		 86/* Used to pass the media type, etc.
87 Both 'options[]' and 'full_duplex[]' should exist for driver
88 interoperability.
89 The media type is usually passed in 'options[]'.
90*/
91#define MAX_UNITS 8 /* More are supported, limit only on options */
92static int options[MAX_UNITS];
93static int full_duplex[MAX_UNITS];
94
95/* Operational parameters that are set at compile time. */
96
97/* Keep the ring sizes a power of two for compile efficiency.
98 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
99 Making the Tx ring too large decreases the effectiveness of channel
100 bonding and packet priority.
101 There are no ill effects from too-large receive rings. */
102#define TX_RING_SIZE 16
103#define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
104#define RX_RING_SIZE 32
105
106/* Operational parameters that usually are not changed. */
107/* Time in jiffies before concluding the transmitter is hung. */
108#define TX_TIMEOUT (2*HZ)
109
110#define NATSEMI_HW_TIMEOUT 400
f2cade13 111#define NATSEMI_TIMER_FREQ 5*HZ
1da177e4
LT		 112#define NATSEMI_PG0_NREGS 64
113#define NATSEMI_RFDR_NREGS 8
114#define NATSEMI_PG1_NREGS 4
115#define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
116 NATSEMI_PG1_NREGS)
117#define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
118#define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
1da177e4
LT		 119
120/* Buffer sizes:
121 * The nic writes 32-bit values, even if the upper bytes of
122 * a 32-bit value are beyond the end of the buffer.
123 */
124#define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
125#define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
126#define NATSEMI_LONGPKT 1518 /* limit for normal packets */
127#define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
128
129/* These identify the driver base version and may not be removed. */
e19360f2 130static const char version[] __devinitdata =
1da177e4
LT		 131 KERN_INFO DRV_NAME " dp8381x driver, version "
132 DRV_VERSION ", " DRV_RELDATE "\n"
133 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
1da177e4
LT		 134 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
135
136MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
137MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
138MODULE_LICENSE("GPL");
139
1da177e4
LT		 140module_param(mtu, int, 0);
141module_param(debug, int, 0);
142module_param(rx_copybreak, int, 0);
1a147809 143module_param(dspcfg_workaround, int, 1);
1da177e4
LT		 144module_param_array(options, int, NULL, 0);
145module_param_array(full_duplex, int, NULL, 0);
1da177e4
LT		 146MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
147MODULE_PARM_DESC(debug, "DP8381x default debug level");
6aa20a22 148MODULE_PARM_DESC(rx_copybreak,
1da177e4 149 "DP8381x copy breakpoint for copy-only-tiny-frames");
1a147809 150MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround");
6aa20a22 151MODULE_PARM_DESC(options,
1da177e4
LT		 152 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
153MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
154
155/*
156 Theory of Operation
157
158I. Board Compatibility
159
160This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
161It also works with other chips in in the DP83810 series.
162
163II. Board-specific settings
164
165This driver requires the PCI interrupt line to be valid.
166It honors the EEPROM-set values.
167
168III. Driver operation
169
170IIIa. Ring buffers
171
172This driver uses two statically allocated fixed-size descriptor lists
173formed into rings by a branch from the final descriptor to the beginning of
174the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
175The NatSemi design uses a 'next descriptor' pointer that the driver forms
176into a list.
177
178IIIb/c. Transmit/Receive Structure
179
180This driver uses a zero-copy receive and transmit scheme.
181The driver allocates full frame size skbuffs for the Rx ring buffers at
182open() time and passes the skb->data field to the chip as receive data
183buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
184a fresh skbuff is allocated and the frame is copied to the new skbuff.
185When the incoming frame is larger, the skbuff is passed directly up the
186protocol stack. Buffers consumed this way are replaced by newly allocated
187skbuffs in a later phase of receives.
188
189The RX_COPYBREAK value is chosen to trade-off the memory wasted by
190using a full-sized skbuff for small frames vs. the copying costs of larger
191frames. New boards are typically used in generously configured machines
192and the underfilled buffers have negligible impact compared to the benefit of
193a single allocation size, so the default value of zero results in never
194copying packets. When copying is done, the cost is usually mitigated by using
195a combined copy/checksum routine. Copying also preloads the cache, which is
196most useful with small frames.
197
198A subtle aspect of the operation is that unaligned buffers are not permitted
199by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
200longword aligned for further processing. On copies frames are put into the
201skbuff at an offset of "+2", 16-byte aligning the IP header.
202
203IIId. Synchronization
204
205Most operations are synchronized on the np->lock irq spinlock, except the
206performance critical codepaths:
207
208The rx process only runs in the interrupt handler. Access from outside
209the interrupt handler is only permitted after disable_irq().
210
932ff279 211The rx process usually runs under the netif_tx_lock. If np->intr_tx_reap
1da177e4
LT		 212is set, then access is permitted under spin_lock_irq(&np->lock).
213
214Thus configuration functions that want to access everything must call
215 disable_irq(dev->irq);
932ff279 216 netif_tx_lock_bh(dev);
1da177e4
LT		 217 spin_lock_irq(&np->lock);
218
219IV. Notes
220
221NatSemi PCI network controllers are very uncommon.
222
223IVb. References
224
225http://www.scyld.com/expert/100mbps.html
226http://www.scyld.com/expert/NWay.html
227Datasheet is available from:
228http://www.national.com/pf/DP/DP83815.html
229
230IVc. Errata
231
232None characterised.
233*/
234
235
236
1da177e4
LT		 237/*
238 * Support for fibre connections on Am79C874:
239 * This phy needs a special setup when connected to a fibre cable.
240 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
241 */
242#define PHYID_AM79C874 0x0022561b
243
a2b524b2
JG		 244enum {
245 MII_MCTRL = 0x15, /* mode control register */
246 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
247 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
248};
1da177e4 249
6aab4447
MB		 250enum {
251 NATSEMI_FLAG_IGNORE_PHY = 0x1,
252};
6aa20a22 253
1da177e4 254/* array of board data directly indexed by pci_tbl[x].driver_data */
f71e1309 255static const struct {
1da177e4
LT		 256 const char *name;
257 unsigned long flags;
a2b524b2 258 unsigned int eeprom_size;
1da177e4 259} natsemi_pci_info[] __devinitdata = {
6aab4447 260 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
a2b524b2 261 { "NatSemi DP8381[56]", 0, 24 },
1da177e4
LT		 262};
263
a2b524b2 264static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
6aab4447 265 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
36c843d5 266 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
a2b524b2 267 { } /* terminate list */
1da177e4
LT		 268};
269MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
270
271/* Offsets to the device registers.
272 Unlike software-only systems, device drivers interact with complex hardware.
273 It's not useful to define symbolic names for every register bit in the
274 device.
275*/
276enum register_offsets {
277 ChipCmd = 0x00,
278 ChipConfig = 0x04,
279 EECtrl = 0x08,
280 PCIBusCfg = 0x0C,
281 IntrStatus = 0x10,
282 IntrMask = 0x14,
283 IntrEnable = 0x18,
284 IntrHoldoff = 0x1C, /* DP83816 only */
285 TxRingPtr = 0x20,
286 TxConfig = 0x24,
287 RxRingPtr = 0x30,
288 RxConfig = 0x34,
289 ClkRun = 0x3C,
290 WOLCmd = 0x40,
291 PauseCmd = 0x44,
292 RxFilterAddr = 0x48,
293 RxFilterData = 0x4C,
294 BootRomAddr = 0x50,
295 BootRomData = 0x54,
296 SiliconRev = 0x58,
297 StatsCtrl = 0x5C,
298 StatsData = 0x60,
299 RxPktErrs = 0x60,
300 RxMissed = 0x68,
301 RxCRCErrs = 0x64,
302 BasicControl = 0x80,
303 BasicStatus = 0x84,
304 AnegAdv = 0x90,
305 AnegPeer = 0x94,
306 PhyStatus = 0xC0,
307 MIntrCtrl = 0xC4,
308 MIntrStatus = 0xC8,
309 PhyCtrl = 0xE4,
310
311 /* These are from the spec, around page 78... on a separate table.
312 * The meaning of these registers depend on the value of PGSEL. */
313 PGSEL = 0xCC,
314 PMDCSR = 0xE4,
315 TSTDAT = 0xFC,
316 DSPCFG = 0xF4,
317 SDCFG = 0xF8
318};
319/* the values for the 'magic' registers above (PGSEL=1) */
320#define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
321#define TSTDAT_VAL 0x0
322#define DSPCFG_VAL 0x5040
323#define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
324#define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
325#define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
326#define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
327
328/* misc PCI space registers */
329enum pci_register_offsets {
330 PCIPM = 0x44,
331};
332
333enum ChipCmd_bits {
334 ChipReset = 0x100,
335 RxReset = 0x20,
336 TxReset = 0x10,
337 RxOff = 0x08,
338 RxOn = 0x04,
339 TxOff = 0x02,
340 TxOn = 0x01,
341};
342
343enum ChipConfig_bits {
344 CfgPhyDis = 0x200,
345 CfgPhyRst = 0x400,
346 CfgExtPhy = 0x1000,
347 CfgAnegEnable = 0x2000,
348 CfgAneg100 = 0x4000,
349 CfgAnegFull = 0x8000,
350 CfgAnegDone = 0x8000000,
351 CfgFullDuplex = 0x20000000,
352 CfgSpeed100 = 0x40000000,
353 CfgLink = 0x80000000,
354};
355
356enum EECtrl_bits {
357 EE_ShiftClk = 0x04,
358 EE_DataIn = 0x01,
359 EE_ChipSelect = 0x08,
360 EE_DataOut = 0x02,
361 MII_Data = 0x10,
362 MII_Write = 0x20,
363 MII_ShiftClk = 0x40,
364};
365
366enum PCIBusCfg_bits {
367 EepromReload = 0x4,
368};
369
370/* Bits in the interrupt status/mask registers. */
371enum IntrStatus_bits {
372 IntrRxDone = 0x0001,
373 IntrRxIntr = 0x0002,
374 IntrRxErr = 0x0004,
375 IntrRxEarly = 0x0008,
376 IntrRxIdle = 0x0010,
377 IntrRxOverrun = 0x0020,
378 IntrTxDone = 0x0040,
379 IntrTxIntr = 0x0080,
380 IntrTxErr = 0x0100,
381 IntrTxIdle = 0x0200,
382 IntrTxUnderrun = 0x0400,
383 StatsMax = 0x0800,
384 SWInt = 0x1000,
385 WOLPkt = 0x2000,
386 LinkChange = 0x4000,
387 IntrHighBits = 0x8000,
388 RxStatusFIFOOver = 0x10000,
389 IntrPCIErr = 0xf00000,
390 RxResetDone = 0x1000000,
391 TxResetDone = 0x2000000,
392 IntrAbnormalSummary = 0xCD20,
393};
394
395/*
396 * Default Interrupts:
397 * Rx OK, Rx Packet Error, Rx Overrun,
398 * Tx OK, Tx Packet Error, Tx Underrun,
399 * MIB Service, Phy Interrupt, High Bits,
400 * Rx Status FIFO overrun,
401 * Received Target Abort, Received Master Abort,
402 * Signalled System Error, Received Parity Error
403 */
404#define DEFAULT_INTR 0x00f1cd65
405
406enum TxConfig_bits {
407 TxDrthMask = 0x3f,
408 TxFlthMask = 0x3f00,
409 TxMxdmaMask = 0x700000,
410 TxMxdma_512 = 0x0,
411 TxMxdma_4 = 0x100000,
412 TxMxdma_8 = 0x200000,
413 TxMxdma_16 = 0x300000,
414 TxMxdma_32 = 0x400000,
415 TxMxdma_64 = 0x500000,
416 TxMxdma_128 = 0x600000,
417 TxMxdma_256 = 0x700000,
418 TxCollRetry = 0x800000,
419 TxAutoPad = 0x10000000,
420 TxMacLoop = 0x20000000,
421 TxHeartIgn = 0x40000000,
422 TxCarrierIgn = 0x80000000
423};
424
6aa20a22 425/*
1da177e4
LT		 426 * Tx Configuration:
427 * - 256 byte DMA burst length
428 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
429 * - 64 bytes initial drain threshold (i.e. begin actual transmission
430 * when 64 byte are in the fifo)
431 * - on tx underruns, increase drain threshold by 64.
432 * - at most use a drain threshold of 1472 bytes: The sum of the fill
433 * threshold and the drain threshold must be less than 2016 bytes.
434 *
435 */
436#define TX_FLTH_VAL ((512/32) << 8)
437#define TX_DRTH_VAL_START (64/32)
438#define TX_DRTH_VAL_INC 2
439#define TX_DRTH_VAL_LIMIT (1472/32)
440
441enum RxConfig_bits {
442 RxDrthMask = 0x3e,
443 RxMxdmaMask = 0x700000,
444 RxMxdma_512 = 0x0,
445 RxMxdma_4 = 0x100000,
446 RxMxdma_8 = 0x200000,
447 RxMxdma_16 = 0x300000,
448 RxMxdma_32 = 0x400000,
449 RxMxdma_64 = 0x500000,
450 RxMxdma_128 = 0x600000,
451 RxMxdma_256 = 0x700000,
452 RxAcceptLong = 0x8000000,
453 RxAcceptTx = 0x10000000,
454 RxAcceptRunt = 0x40000000,
455 RxAcceptErr = 0x80000000
456};
457#define RX_DRTH_VAL (128/8)
458
459enum ClkRun_bits {
460 PMEEnable = 0x100,
461 PMEStatus = 0x8000,
462};
463
464enum WolCmd_bits {
465 WakePhy = 0x1,
466 WakeUnicast = 0x2,
467 WakeMulticast = 0x4,
468 WakeBroadcast = 0x8,
469 WakeArp = 0x10,
470 WakePMatch0 = 0x20,
471 WakePMatch1 = 0x40,
472 WakePMatch2 = 0x80,
473 WakePMatch3 = 0x100,
474 WakeMagic = 0x200,
475 WakeMagicSecure = 0x400,
476 SecureHack = 0x100000,
477 WokePhy = 0x400000,
478 WokeUnicast = 0x800000,
479 WokeMulticast = 0x1000000,
480 WokeBroadcast = 0x2000000,
481 WokeArp = 0x4000000,
482 WokePMatch0 = 0x8000000,
483 WokePMatch1 = 0x10000000,
484 WokePMatch2 = 0x20000000,
485 WokePMatch3 = 0x40000000,
486 WokeMagic = 0x80000000,
487 WakeOptsSummary = 0x7ff
488};
489
490enum RxFilterAddr_bits {
491 RFCRAddressMask = 0x3ff,
492 AcceptMulticast = 0x00200000,
493 AcceptMyPhys = 0x08000000,
494 AcceptAllPhys = 0x10000000,
495 AcceptAllMulticast = 0x20000000,
496 AcceptBroadcast = 0x40000000,
497 RxFilterEnable = 0x80000000
498};
499
500enum StatsCtrl_bits {
501 StatsWarn = 0x1,
502 StatsFreeze = 0x2,
503 StatsClear = 0x4,
504 StatsStrobe = 0x8,
505};
506
507enum MIntrCtrl_bits {
508 MICRIntEn = 0x2,
509};
510
511enum PhyCtrl_bits {
512 PhyAddrMask = 0x1f,
513};
514
515#define PHY_ADDR_NONE 32
516#define PHY_ADDR_INTERNAL 1
517
518/* values we might find in the silicon revision register */
519#define SRR_DP83815_C 0x0302
520#define SRR_DP83815_D 0x0403
521#define SRR_DP83816_A4 0x0504
522#define SRR_DP83816_A5 0x0505
523
524/* The Rx and Tx buffer descriptors. */
525/* Note that using only 32 bit fields simplifies conversion to big-endian
526 architectures. */
527struct netdev_desc {
528 u32 next_desc;
529 s32 cmd_status;
530 u32 addr;
531 u32 software_use;
532};
533
534/* Bits in network_desc.status */
535enum desc_status_bits {
536 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
537 DescNoCRC=0x10000000, DescPktOK=0x08000000,
538 DescSizeMask=0xfff,
539
540 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
541 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
542 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
543 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
544
545 DescRxAbort=0x04000000, DescRxOver=0x02000000,
546 DescRxDest=0x01800000, DescRxLong=0x00400000,
547 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
548 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
549 DescRxLoop=0x00020000, DesRxColl=0x00010000,
550};
551
552struct netdev_private {
553 /* Descriptor rings first for alignment */
554 dma_addr_t ring_dma;
555 struct netdev_desc *rx_ring;
556 struct netdev_desc *tx_ring;
557 /* The addresses of receive-in-place skbuffs */
558 struct sk_buff *rx_skbuff[RX_RING_SIZE];
559 dma_addr_t rx_dma[RX_RING_SIZE];
560 /* address of a sent-in-place packet/buffer, for later free() */
561 struct sk_buff *tx_skbuff[TX_RING_SIZE];
562 dma_addr_t tx_dma[TX_RING_SIZE];
bea3348e
SH		 563 struct net_device *dev;
564 struct napi_struct napi;
1da177e4
LT		 565 struct net_device_stats stats;
566 /* Media monitoring timer */
567 struct timer_list timer;
568 /* Frequently used values: keep some adjacent for cache effect */
569 struct pci_dev *pci_dev;
570 struct netdev_desc *rx_head_desc;
571 /* Producer/consumer ring indices */
572 unsigned int cur_rx, dirty_rx;
573 unsigned int cur_tx, dirty_tx;
574 /* Based on MTU+slack. */
575 unsigned int rx_buf_sz;
576 int oom;
b27a16b7
MB		 577 /* Interrupt status */
578 u32 intr_status;
1da177e4
LT		 579 /* Do not touch the nic registers */
580 int hands_off;
68c90166
MB		 581 /* Don't pay attention to the reported link state. */
582 int ignore_phy;
1da177e4
LT		 583 /* external phy that is used: only valid if dev->if_port != PORT_TP */
584 int mii;
585 int phy_addr_external;
586 unsigned int full_duplex;
587 /* Rx filter */
588 u32 cur_rx_mode;
589 u32 rx_filter[16];
590 /* FIFO and PCI burst thresholds */
591 u32 tx_config, rx_config;
592 /* original contents of ClkRun register */
593 u32 SavedClkRun;
594 /* silicon revision */
595 u32 srr;
596 /* expected DSPCFG value */
597 u16 dspcfg;
1a147809 598 int dspcfg_workaround;
1da177e4
LT		 599 /* parms saved in ethtool format */
600 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
601 u8 duplex; /* Duplex, half or full */
602 u8 autoneg; /* Autonegotiation enabled */
603 /* MII transceiver section */
604 u16 advertising;
605 unsigned int iosize;
606 spinlock_t lock;
607 u32 msg_enable;
a8b4cf42
MB		 608 /* EEPROM data */
609 int eeprom_size;
1da177e4
LT		 610};
611
612static void move_int_phy(struct net_device *dev, int addr);
613static int eeprom_read(void __iomem *ioaddr, int location);
614static int mdio_read(struct net_device *dev, int reg);
615static void mdio_write(struct net_device *dev, int reg, u16 data);
616static void init_phy_fixup(struct net_device *dev);
617static int miiport_read(struct net_device *dev, int phy_id, int reg);
618static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
619static int find_mii(struct net_device *dev);
620static void natsemi_reset(struct net_device *dev);
621static void natsemi_reload_eeprom(struct net_device *dev);
622static void natsemi_stop_rxtx(struct net_device *dev);
623static int netdev_open(struct net_device *dev);
624static void do_cable_magic(struct net_device *dev);
625static void undo_cable_magic(struct net_device *dev);
626static void check_link(struct net_device *dev);
627static void netdev_timer(unsigned long data);
628static void dump_ring(struct net_device *dev);
629static void tx_timeout(struct net_device *dev);
630static int alloc_ring(struct net_device *dev);
631static void refill_rx(struct net_device *dev);
632static void init_ring(struct net_device *dev);
633static void drain_tx(struct net_device *dev);
634static void drain_ring(struct net_device *dev);
635static void free_ring(struct net_device *dev);
636static void reinit_ring(struct net_device *dev);
637static void init_registers(struct net_device *dev);
638static int start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 639static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4 640static void netdev_error(struct net_device *dev, int intr_status);
bea3348e 641static int natsemi_poll(struct napi_struct *napi, int budget);
b27a16b7 642static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
1da177e4
LT		 643static void netdev_tx_done(struct net_device *dev);
644static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
645#ifdef CONFIG_NET_POLL_CONTROLLER
646static void natsemi_poll_controller(struct net_device *dev);
647#endif
648static void __set_rx_mode(struct net_device *dev);
649static void set_rx_mode(struct net_device *dev);
650static void __get_stats(struct net_device *dev);
651static struct net_device_stats *get_stats(struct net_device *dev);
652static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
653static int netdev_set_wol(struct net_device *dev, u32 newval);
654static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
655static int netdev_set_sopass(struct net_device *dev, u8 *newval);
656static int netdev_get_sopass(struct net_device *dev, u8 *data);
657static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
658static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
659static void enable_wol_mode(struct net_device *dev, int enable_intr);
660static int netdev_close(struct net_device *dev);
661static int netdev_get_regs(struct net_device *dev, u8 *buf);
662static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
7282d491 663static const struct ethtool_ops ethtool_ops;
1da177e4 664
1a147809
MB		 665#define NATSEMI_ATTR(_name) \
666static ssize_t natsemi_show_##_name(struct device *dev, \
667 struct device_attribute *attr, char *buf); \
668 static ssize_t natsemi_set_##_name(struct device *dev, \
669 struct device_attribute *attr, \
670 const char *buf, size_t count); \
671 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name)
672
673#define NATSEMI_CREATE_FILE(_dev, _name) \
674 device_create_file(&_dev->dev, &dev_attr_##_name)
675#define NATSEMI_REMOVE_FILE(_dev, _name) \
f6c42865 676 device_remove_file(&_dev->dev, &dev_attr_##_name)
1a147809
MB		 677
678NATSEMI_ATTR(dspcfg_workaround);
679
680static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
681 struct device_attribute *attr,
682 char *buf)
683{
684 struct netdev_private *np = netdev_priv(to_net_dev(dev));
685
686 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off");
687}
688
689static ssize_t natsemi_set_dspcfg_workaround(struct device *dev,
690 struct device_attribute *attr,
691 const char *buf, size_t count)
692{
693 struct netdev_private *np = netdev_priv(to_net_dev(dev));
694 int new_setting;
d41f2d17 695 unsigned long flags;
1a147809
MB		 696
697 /* Find out the new setting */
698 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
699 new_setting = 1;
700 else if (!strncmp("off", buf, count - 1)
701 || !strncmp("0", buf, count - 1))
702 new_setting = 0;
703 else
704 return count;
705
706 spin_lock_irqsave(&np->lock, flags);
707
708 np->dspcfg_workaround = new_setting;
709
710 spin_unlock_irqrestore(&np->lock, flags);
711
712 return count;
713}
714
1da177e4
LT		 715static inline void __iomem *ns_ioaddr(struct net_device *dev)
716{
717 return (void __iomem *) dev->base_addr;
718}
719
b27a16b7
MB		 720static inline void natsemi_irq_enable(struct net_device *dev)
721{
722 writel(1, ns_ioaddr(dev) + IntrEnable);
723 readl(ns_ioaddr(dev) + IntrEnable);
724}
725
726static inline void natsemi_irq_disable(struct net_device *dev)
727{
728 writel(0, ns_ioaddr(dev) + IntrEnable);
729 readl(ns_ioaddr(dev) + IntrEnable);
730}
731
1da177e4
LT		 732static void move_int_phy(struct net_device *dev, int addr)
733{
734 struct netdev_private *np = netdev_priv(dev);
735 void __iomem *ioaddr = ns_ioaddr(dev);
736 int target = 31;
737
6aa20a22 738 /*
1da177e4
LT		 739 * The internal phy is visible on the external mii bus. Therefore we must
740 * move it away before we can send commands to an external phy.
741 * There are two addresses we must avoid:
742 * - the address on the external phy that is used for transmission.
743 * - the address that we want to access. User space can access phys
744 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
745 * phy that is used for transmission.
746 */
747
748 if (target == addr)
749 target--;
750 if (target == np->phy_addr_external)
751 target--;
752 writew(target, ioaddr + PhyCtrl);
753 readw(ioaddr + PhyCtrl);
754 udelay(1);
755}
756
5a40f09b
JG		 757static void __devinit natsemi_init_media (struct net_device *dev)
758{
759 struct netdev_private *np = netdev_priv(dev);
760 u32 tmp;
761
68c90166
MB		 762 if (np->ignore_phy)
763 netif_carrier_on(dev);
764 else
765 netif_carrier_off(dev);
5a40f09b
JG		 766
767 /* get the initial settings from hardware */
768 tmp = mdio_read(dev, MII_BMCR);
769 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
770 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
771 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
772 np->advertising= mdio_read(dev, MII_ADVERTISE);
773
774 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
775 && netif_msg_probe(np)) {
776 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
777 "10%s %s duplex.\n",
778 pci_name(np->pci_dev),
779 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
780 "enabled, advertise" : "disabled, force",
781 (np->advertising &
782 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
783 "0" : "",
784 (np->advertising &
785 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
786 "full" : "half");
787 }
788 if (netif_msg_probe(np))
789 printk(KERN_INFO
790 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
791 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
792 np->advertising);
793
794}
795
1da177e4
LT		 796static int __devinit natsemi_probe1 (struct pci_dev *pdev,
797 const struct pci_device_id *ent)
798{
799 struct net_device *dev;
800 struct netdev_private *np;
801 int i, option, irq, chip_idx = ent->driver_data;
802 static int find_cnt = -1;
803 unsigned long iostart, iosize;
804 void __iomem *ioaddr;
805 const int pcibar = 1; /* PCI base address register */
806 int prev_eedata;
807 u32 tmp;
0795af57 808 DECLARE_MAC_BUF(mac);
1da177e4
LT		 809
810/* when built into the kernel, we only print version if device is found */
811#ifndef MODULE
812 static int printed_version;
813 if (!printed_version++)
814 printk(version);
815#endif
816
817 i = pci_enable_device(pdev);
818 if (i) return i;
819
820 /* natsemi has a non-standard PM control register
821 * in PCI config space. Some boards apparently need
822 * to be brought to D0 in this manner.
823 */
824 pci_read_config_dword(pdev, PCIPM, &tmp);
825 if (tmp & PCI_PM_CTRL_STATE_MASK) {
826 /* D0 state, disable PME assertion */
827 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
828 pci_write_config_dword(pdev, PCIPM, newtmp);
829 }
830
831 find_cnt++;
832 iostart = pci_resource_start(pdev, pcibar);
833 iosize = pci_resource_len(pdev, pcibar);
834 irq = pdev->irq;
835
a2b524b2 836 pci_set_master(pdev);
1da177e4
LT		 837
838 dev = alloc_etherdev(sizeof (struct netdev_private));
839 if (!dev)
840 return -ENOMEM;
1da177e4
LT		 841 SET_NETDEV_DEV(dev, &pdev->dev);
842
843 i = pci_request_regions(pdev, DRV_NAME);
844 if (i)
845 goto err_pci_request_regions;
846
847 ioaddr = ioremap(iostart, iosize);
848 if (!ioaddr) {
849 i = -ENOMEM;
850 goto err_ioremap;
851 }
852
853 /* Work around the dropped serial bit. */
854 prev_eedata = eeprom_read(ioaddr, 6);
855 for (i = 0; i < 3; i++) {
856 int eedata = eeprom_read(ioaddr, i + 7);
857 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
858 dev->dev_addr[i*2+1] = eedata >> 7;
859 prev_eedata = eedata;
860 }
861
862 dev->base_addr = (unsigned long __force) ioaddr;
863 dev->irq = irq;
864
865 np = netdev_priv(dev);
bea3348e 866 netif_napi_add(dev, &np->napi, natsemi_poll, 64);
1da177e4
LT		 867
868 np->pci_dev = pdev;
869 pci_set_drvdata(pdev, dev);
870 np->iosize = iosize;
871 spin_lock_init(&np->lock);
872 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
873 np->hands_off = 0;
b27a16b7 874 np->intr_status = 0;
a2b524b2 875 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
6aab4447
MB		 876 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
877 np->ignore_phy = 1;
878 else
879 np->ignore_phy = 0;
1a147809 880 np->dspcfg_workaround = dspcfg_workaround;
1da177e4
LT		 881
882 /* Initial port:
68c90166 883 * - If configured to ignore the PHY set up for external.
1da177e4
LT		 884 * - If the nic was configured to use an external phy and if find_mii
885 * finds a phy: use external port, first phy that replies.
886 * - Otherwise: internal port.
887 * Note that the phy address for the internal phy doesn't matter:
888 * The address would be used to access a phy over the mii bus, but
889 * the internal phy is accessed through mapped registers.
890 */
68c90166 891 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
1da177e4
LT		 892 dev->if_port = PORT_MII;
893 else
894 dev->if_port = PORT_TP;
895 /* Reset the chip to erase previous misconfiguration. */
896 natsemi_reload_eeprom(dev);
897 natsemi_reset(dev);
898
899 if (dev->if_port != PORT_TP) {
900 np->phy_addr_external = find_mii(dev);
68c90166
MB		 901 /* If we're ignoring the PHY it doesn't matter if we can't
902 * find one. */
903 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
1da177e4
LT		 904 dev->if_port = PORT_TP;
905 np->phy_addr_external = PHY_ADDR_INTERNAL;
906 }
907 } else {
908 np->phy_addr_external = PHY_ADDR_INTERNAL;
909 }
910
911 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
912 if (dev->mem_start)
913 option = dev->mem_start;
914
915 /* The lower four bits are the media type. */
916 if (option) {
917 if (option & 0x200)
918 np->full_duplex = 1;
919 if (option & 15)
920 printk(KERN_INFO
921 "natsemi %s: ignoring user supplied media type %d",
922 pci_name(np->pci_dev), option & 15);
923 }
924 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
925 np->full_duplex = 1;
926
927 /* The chip-specific entries in the device structure. */
928 dev->open = &netdev_open;
929 dev->hard_start_xmit = &start_tx;
930 dev->stop = &netdev_close;
931 dev->get_stats = &get_stats;
932 dev->set_multicast_list = &set_rx_mode;
933 dev->change_mtu = &natsemi_change_mtu;
934 dev->do_ioctl = &netdev_ioctl;
935 dev->tx_timeout = &tx_timeout;
936 dev->watchdog_timeo = TX_TIMEOUT;
b27a16b7 937
1da177e4
LT		 938#ifdef CONFIG_NET_POLL_CONTROLLER
939 dev->poll_controller = &natsemi_poll_controller;
940#endif
941 SET_ETHTOOL_OPS(dev, &ethtool_ops);
942
943 if (mtu)
944 dev->mtu = mtu;
945
5a40f09b 946 natsemi_init_media(dev);
1da177e4
LT		 947
948 /* save the silicon revision for later querying */
949 np->srr = readl(ioaddr + SiliconRev);
950 if (netif_msg_hw(np))
951 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
952 pci_name(np->pci_dev), np->srr);
953
954 i = register_netdev(dev);
955 if (i)
956 goto err_register_netdev;
957
1a147809
MB		 958 if (NATSEMI_CREATE_FILE(pdev, dspcfg_workaround))
959 goto err_create_file;
960
1da177e4 961 if (netif_msg_drv(np)) {
0795af57
JP		 962 printk(KERN_INFO "natsemi %s: %s at %#08lx "
963 "(%s), %s, IRQ %d",
964 dev->name, natsemi_pci_info[chip_idx].name, iostart,
965 pci_name(np->pci_dev), print_mac(mac, dev->dev_addr), irq);
1da177e4
LT		 966 if (dev->if_port == PORT_TP)
967 printk(", port TP.\n");
68c90166
MB		 968 else if (np->ignore_phy)
969 printk(", port MII, ignoring PHY\n");
1da177e4
LT		 970 else
971 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
972 }
973 return 0;
974
1a147809
MB		 975 err_create_file:
976 unregister_netdev(dev);
977
1da177e4
LT		 978 err_register_netdev:
979 iounmap(ioaddr);
980
981 err_ioremap:
982 pci_release_regions(pdev);
983 pci_set_drvdata(pdev, NULL);
984
985 err_pci_request_regions:
986 free_netdev(dev);
987 return i;
988}
989
990
991/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
992 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
993
994/* Delay between EEPROM clock transitions.
995 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
996 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
997 made udelay() unreliable.
998 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
405bbe9f 999 deprecated.
1da177e4
LT		 1000*/
1001#define eeprom_delay(ee_addr) readl(ee_addr)
1002
1003#define EE_Write0 (EE_ChipSelect)
1004#define EE_Write1 (EE_ChipSelect | EE_DataIn)
1005
1006/* The EEPROM commands include the alway-set leading bit. */
1007enum EEPROM_Cmds {
1008 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1009};
1010
1011static int eeprom_read(void __iomem *addr, int location)
1012{
1013 int i;
1014 int retval = 0;
1015 void __iomem *ee_addr = addr + EECtrl;
1016 int read_cmd = location | EE_ReadCmd;
1017
1018 writel(EE_Write0, ee_addr);
1019
1020 /* Shift the read command bits out. */
1021 for (i = 10; i >= 0; i--) {
1022 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1023 writel(dataval, ee_addr);
1024 eeprom_delay(ee_addr);
1025 writel(dataval | EE_ShiftClk, ee_addr);
1026 eeprom_delay(ee_addr);
1027 }
1028 writel(EE_ChipSelect, ee_addr);
1029 eeprom_delay(ee_addr);
1030
1031 for (i = 0; i < 16; i++) {
1032 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1033 eeprom_delay(ee_addr);
1034 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1035 writel(EE_ChipSelect, ee_addr);
1036 eeprom_delay(ee_addr);
1037 }
1038
1039 /* Terminate the EEPROM access. */
1040 writel(EE_Write0, ee_addr);
1041 writel(0, ee_addr);
1042 return retval;
1043}
1044
1045/* MII transceiver control section.
1046 * The 83815 series has an internal transceiver, and we present the
1047 * internal management registers as if they were MII connected.
1048 * External Phy registers are referenced through the MII interface.
1049 */
1050
1051/* clock transitions >= 20ns (25MHz)
1052 * One readl should be good to PCI @ 100MHz
1053 */
1054#define mii_delay(ioaddr) readl(ioaddr + EECtrl)
1055
1056static int mii_getbit (struct net_device *dev)
1057{
1058 int data;
1059 void __iomem *ioaddr = ns_ioaddr(dev);
1060
1061 writel(MII_ShiftClk, ioaddr + EECtrl);
1062 data = readl(ioaddr + EECtrl);
1063 writel(0, ioaddr + EECtrl);
1064 mii_delay(ioaddr);
1065 return (data & MII_Data)? 1 : 0;
1066}
1067
1068static void mii_send_bits (struct net_device *dev, u32 data, int len)
1069{
1070 u32 i;
1071 void __iomem *ioaddr = ns_ioaddr(dev);
1072
1073 for (i = (1 << (len-1)); i; i >>= 1)
1074 {
1075 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1076 writel(mdio_val, ioaddr + EECtrl);
1077 mii_delay(ioaddr);
1078 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
1079 mii_delay(ioaddr);
1080 }
1081 writel(0, ioaddr + EECtrl);
1082 mii_delay(ioaddr);
1083}
1084
1085static int miiport_read(struct net_device *dev, int phy_id, int reg)
1086{
1087 u32 cmd;
1088 int i;
1089 u32 retval = 0;
1090
1091 /* Ensure sync */
1092 mii_send_bits (dev, 0xffffffff, 32);
1093 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1094 /* ST,OP = 0110'b for read operation */
1095 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1096 mii_send_bits (dev, cmd, 14);
1097 /* Turnaround */
1098 if (mii_getbit (dev))
1099 return 0;
1100 /* Read data */
1101 for (i = 0; i < 16; i++) {
1102 retval <<= 1;
1103 retval |= mii_getbit (dev);
1104 }
1105 /* End cycle */
1106 mii_getbit (dev);
1107 return retval;
1108}
1109
1110static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1111{
1112 u32 cmd;
1113
1114 /* Ensure sync */
1115 mii_send_bits (dev, 0xffffffff, 32);
1116 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1117 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1118 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1119 mii_send_bits (dev, cmd, 32);
1120 /* End cycle */
1121 mii_getbit (dev);
1122}
1123
1124static int mdio_read(struct net_device *dev, int reg)
1125{
1126 struct netdev_private *np = netdev_priv(dev);
1127 void __iomem *ioaddr = ns_ioaddr(dev);
1128
1129 /* The 83815 series has two ports:
1130 * - an internal transceiver
1131 * - an external mii bus
1132 */
1133 if (dev->if_port == PORT_TP)
1134 return readw(ioaddr+BasicControl+(reg<<2));
1135 else
1136 return miiport_read(dev, np->phy_addr_external, reg);
1137}
1138
1139static void mdio_write(struct net_device *dev, int reg, u16 data)
1140{
1141 struct netdev_private *np = netdev_priv(dev);
1142 void __iomem *ioaddr = ns_ioaddr(dev);
1143
1144 /* The 83815 series has an internal transceiver; handle separately */
1145 if (dev->if_port == PORT_TP)
1146 writew(data, ioaddr+BasicControl+(reg<<2));
1147 else
1148 miiport_write(dev, np->phy_addr_external, reg, data);
1149}
1150
1151static void init_phy_fixup(struct net_device *dev)
1152{
1153 struct netdev_private *np = netdev_priv(dev);
1154 void __iomem *ioaddr = ns_ioaddr(dev);
1155 int i;
1156 u32 cfg;
1157 u16 tmp;
1158
1159 /* restore stuff lost when power was out */
1160 tmp = mdio_read(dev, MII_BMCR);
1161 if (np->autoneg == AUTONEG_ENABLE) {
1162 /* renegotiate if something changed */
1163 if ((tmp & BMCR_ANENABLE) == 0
1164 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1165 {
1166 /* turn on autonegotiation and force negotiation */
1167 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1168 mdio_write(dev, MII_ADVERTISE, np->advertising);
1169 }
1170 } else {
1171 /* turn off auto negotiation, set speed and duplexity */
1172 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1173 if (np->speed == SPEED_100)
1174 tmp |= BMCR_SPEED100;
1175 if (np->duplex == DUPLEX_FULL)
1176 tmp |= BMCR_FULLDPLX;
6aa20a22 1177 /*
1da177e4
LT		 1178 * Note: there is no good way to inform the link partner
1179 * that our capabilities changed. The user has to unplug
1180 * and replug the network cable after some changes, e.g.
1181 * after switching from 10HD, autoneg off to 100 HD,
1182 * autoneg off.
1183 */
1184 }
1185 mdio_write(dev, MII_BMCR, tmp);
1186 readl(ioaddr + ChipConfig);
1187 udelay(1);
1188
1189 /* find out what phy this is */
1190 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1191 + mdio_read(dev, MII_PHYSID2);
1192
1193 /* handle external phys here */
1194 switch (np->mii) {
1195 case PHYID_AM79C874:
1196 /* phy specific configuration for fibre/tp operation */
1197 tmp = mdio_read(dev, MII_MCTRL);
1198 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1199 if (dev->if_port == PORT_FIBRE)
1200 tmp |= MII_FX_SEL;
1201 else
1202 tmp |= MII_EN_SCRM;
1203 mdio_write(dev, MII_MCTRL, tmp);
1204 break;
1205 default:
1206 break;
1207 }
1208 cfg = readl(ioaddr + ChipConfig);
1209 if (cfg & CfgExtPhy)
1210 return;
1211
1212 /* On page 78 of the spec, they recommend some settings for "optimum
1213 performance" to be done in sequence. These settings optimize some
1214 of the 100Mbit autodetection circuitry. They say we only want to
1215 do this for rev C of the chip, but engineers at NSC (Bradley
1216 Kennedy) recommends always setting them. If you don't, you get
1217 errors on some autonegotiations that make the device unusable.
1218
1219 It seems that the DSP needs a few usec to reinitialize after
1220 the start of the phy. Just retry writing these values until they
1221 stick.
1222 */
1223 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1224
1225 int dspcfg;
1226 writew(1, ioaddr + PGSEL);
1227 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1228 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1229 np->dspcfg = (np->srr <= SRR_DP83815_C)?
1230 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
1231 writew(np->dspcfg, ioaddr + DSPCFG);
1232 writew(SDCFG_VAL, ioaddr + SDCFG);
1233 writew(0, ioaddr + PGSEL);
1234 readl(ioaddr + ChipConfig);
1235 udelay(10);
1236
1237 writew(1, ioaddr + PGSEL);
1238 dspcfg = readw(ioaddr + DSPCFG);
1239 writew(0, ioaddr + PGSEL);
1240 if (np->dspcfg == dspcfg)
1241 break;
1242 }
1243
1244 if (netif_msg_link(np)) {
1245 if (i==NATSEMI_HW_TIMEOUT) {
1246 printk(KERN_INFO
1247 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1248 dev->name, i*10);
1249 } else {
1250 printk(KERN_INFO
1251 "%s: DSPCFG accepted after %d usec.\n",
1252 dev->name, i*10);
1253 }
1254 }
1255 /*
1256 * Enable PHY Specific event based interrupts. Link state change
1257 * and Auto-Negotiation Completion are among the affected.
1258 * Read the intr status to clear it (needed for wake events).
1259 */
1260 readw(ioaddr + MIntrStatus);
1261 writew(MICRIntEn, ioaddr + MIntrCtrl);
1262}
1263
1264static int switch_port_external(struct net_device *dev)
1265{
1266 struct netdev_private *np = netdev_priv(dev);
1267 void __iomem *ioaddr = ns_ioaddr(dev);
1268 u32 cfg;
1269
1270 cfg = readl(ioaddr + ChipConfig);
1271 if (cfg & CfgExtPhy)
1272 return 0;
1273
1274 if (netif_msg_link(np)) {
1275 printk(KERN_INFO "%s: switching to external transceiver.\n",
1276 dev->name);
1277 }
1278
1279 /* 1) switch back to external phy */
1280 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
1281 readl(ioaddr + ChipConfig);
1282 udelay(1);
1283
1284 /* 2) reset the external phy: */
1285 /* resetting the external PHY has been known to cause a hub supplying
1286 * power over Ethernet to kill the power. We don't want to kill
1287 * power to this computer, so we avoid resetting the phy.
1288 */
1289
1290 /* 3) reinit the phy fixup, it got lost during power down. */
1291 move_int_phy(dev, np->phy_addr_external);
1292 init_phy_fixup(dev);
1293
1294 return 1;
1295}
1296
1297static int switch_port_internal(struct net_device *dev)
1298{
1299 struct netdev_private *np = netdev_priv(dev);
1300 void __iomem *ioaddr = ns_ioaddr(dev);
1301 int i;
1302 u32 cfg;
1303 u16 bmcr;
1304
1305 cfg = readl(ioaddr + ChipConfig);
1306 if (!(cfg &CfgExtPhy))
1307 return 0;
1308
1309 if (netif_msg_link(np)) {
1310 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1311 dev->name);
1312 }
1313 /* 1) switch back to internal phy: */
1314 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1315 writel(cfg, ioaddr + ChipConfig);
1316 readl(ioaddr + ChipConfig);
1317 udelay(1);
6aa20a22 1318
1da177e4
LT		 1319 /* 2) reset the internal phy: */
1320 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1321 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
1322 readl(ioaddr + ChipConfig);
1323 udelay(10);
1324 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1325 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
1326 if (!(bmcr & BMCR_RESET))
1327 break;
1328 udelay(10);
1329 }
1330 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1331 printk(KERN_INFO
1332 "%s: phy reset did not complete in %d usec.\n",
1333 dev->name, i*10);
1334 }
1335 /* 3) reinit the phy fixup, it got lost during power down. */
1336 init_phy_fixup(dev);
1337
1338 return 1;
1339}
1340
1341/* Scan for a PHY on the external mii bus.
1342 * There are two tricky points:
1343 * - Do not scan while the internal phy is enabled. The internal phy will
1344 * crash: e.g. reads from the DSPCFG register will return odd values and
1345 * the nasty random phy reset code will reset the nic every few seconds.
1346 * - The internal phy must be moved around, an external phy could
1347 * have the same address as the internal phy.
1348 */
1349static int find_mii(struct net_device *dev)
1350{
1351 struct netdev_private *np = netdev_priv(dev);
1352 int tmp;
1353 int i;
1354 int did_switch;
1355
1356 /* Switch to external phy */
1357 did_switch = switch_port_external(dev);
6aa20a22 1358
1da177e4
LT		 1359 /* Scan the possible phy addresses:
1360 *
1361 * PHY address 0 means that the phy is in isolate mode. Not yet
1362 * supported due to lack of test hardware. User space should
1363 * handle it through ethtool.
1364 */
1365 for (i = 1; i <= 31; i++) {
1366 move_int_phy(dev, i);
1367 tmp = miiport_read(dev, i, MII_BMSR);
1368 if (tmp != 0xffff && tmp != 0x0000) {
1369 /* found something! */
1370 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1371 + mdio_read(dev, MII_PHYSID2);
1372 if (netif_msg_probe(np)) {
1373 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1374 pci_name(np->pci_dev), np->mii, i);
1375 }
1376 break;
1377 }
1378 }
1379 /* And switch back to internal phy: */
1380 if (did_switch)
1381 switch_port_internal(dev);
1382 return i;
1383}
1384
1385/* CFG bits [13:16] [18:23] */
1386#define CFG_RESET_SAVE 0xfde000
1387/* WCSR bits [0:4] [9:10] */
1388#define WCSR_RESET_SAVE 0x61f
1389/* RFCR bits [20] [22] [27:31] */
1390#define RFCR_RESET_SAVE 0xf8500000;
1391
1392static void natsemi_reset(struct net_device *dev)
1393{
1394 int i;
1395 u32 cfg;
1396 u32 wcsr;
1397 u32 rfcr;
1398 u16 pmatch[3];
1399 u16 sopass[3];
1400 struct netdev_private *np = netdev_priv(dev);
1401 void __iomem *ioaddr = ns_ioaddr(dev);
1402
1403 /*
1404 * Resetting the chip causes some registers to be lost.
1405 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1406 * we save the state that would have been loaded from EEPROM
1407 * on a normal power-up (see the spec EEPROM map). This assumes
1408 * whoever calls this will follow up with init_registers() eventually.
1409 */
1410
1411 /* CFG */
1412 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
1413 /* WCSR */
1414 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
1415 /* RFCR */
1416 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
1417 /* PMATCH */
1418 for (i = 0; i < 3; i++) {
1419 writel(i*2, ioaddr + RxFilterAddr);
1420 pmatch[i] = readw(ioaddr + RxFilterData);
1421 }
1422 /* SOPAS */
1423 for (i = 0; i < 3; i++) {
1424 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1425 sopass[i] = readw(ioaddr + RxFilterData);
1426 }
1427
1428 /* now whack the chip */
1429 writel(ChipReset, ioaddr + ChipCmd);
1430 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1431 if (!(readl(ioaddr + ChipCmd) & ChipReset))
1432 break;
1433 udelay(5);
1434 }
1435 if (i==NATSEMI_HW_TIMEOUT) {
1436 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1437 dev->name, i*5);
1438 } else if (netif_msg_hw(np)) {
1439 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1440 dev->name, i*5);
1441 }
1442
1443 /* restore CFG */
1444 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
1445 /* turn on external phy if it was selected */
1446 if (dev->if_port == PORT_TP)
1447 cfg &= ~(CfgExtPhy | CfgPhyDis);
1448 else
1449 cfg |= (CfgExtPhy | CfgPhyDis);
1450 writel(cfg, ioaddr + ChipConfig);
1451 /* restore WCSR */
1452 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
1453 writel(wcsr, ioaddr + WOLCmd);
1454 /* read RFCR */
1455 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1456 /* restore PMATCH */
1457 for (i = 0; i < 3; i++) {
1458 writel(i*2, ioaddr + RxFilterAddr);
1459 writew(pmatch[i], ioaddr + RxFilterData);
1460 }
1461 for (i = 0; i < 3; i++) {
1462 writel(0xa+(i*2), ioaddr + RxFilterAddr);
1463 writew(sopass[i], ioaddr + RxFilterData);
1464 }
1465 /* restore RFCR */
1466 writel(rfcr, ioaddr + RxFilterAddr);
1467}
1468
e72fd96e
MB		 1469static void reset_rx(struct net_device *dev)
1470{
1471 int i;
1472 struct netdev_private *np = netdev_priv(dev);
1473 void __iomem *ioaddr = ns_ioaddr(dev);
1474
1475 np->intr_status &= ~RxResetDone;
1476
1477 writel(RxReset, ioaddr + ChipCmd);
1478
1479 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1480 np->intr_status |= readl(ioaddr + IntrStatus);
1481 if (np->intr_status & RxResetDone)
1482 break;
1483 udelay(15);
1484 }
1485 if (i==NATSEMI_HW_TIMEOUT) {
1486 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
1487 dev->name, i*15);
1488 } else if (netif_msg_hw(np)) {
1489 printk(KERN_WARNING "%s: RX reset took %d usec.\n",
1490 dev->name, i*15);
1491 }
1492}
1493
1da177e4
LT		 1494static void natsemi_reload_eeprom(struct net_device *dev)
1495{
1496 struct netdev_private *np = netdev_priv(dev);
1497 void __iomem *ioaddr = ns_ioaddr(dev);
1498 int i;
1499
1500 writel(EepromReload, ioaddr + PCIBusCfg);
1501 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1502 udelay(50);
1503 if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
1504 break;
1505 }
1506 if (i==NATSEMI_HW_TIMEOUT) {
1507 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1508 pci_name(np->pci_dev), i*50);
1509 } else if (netif_msg_hw(np)) {
1510 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1511 pci_name(np->pci_dev), i*50);
1512 }
1513}
1514
1515static void natsemi_stop_rxtx(struct net_device *dev)
1516{
1517 void __iomem * ioaddr = ns_ioaddr(dev);
1518 struct netdev_private *np = netdev_priv(dev);
1519 int i;
1520
1521 writel(RxOff | TxOff, ioaddr + ChipCmd);
1522 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1523 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1524 break;
1525 udelay(5);
1526 }
1527 if (i==NATSEMI_HW_TIMEOUT) {
1528 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1529 dev->name, i*5);
1530 } else if (netif_msg_hw(np)) {
1531 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1532 dev->name, i*5);
1533 }
1534}
1535
1536static int netdev_open(struct net_device *dev)
1537{
1538 struct netdev_private *np = netdev_priv(dev);
1539 void __iomem * ioaddr = ns_ioaddr(dev);
1540 int i;
1541
1542 /* Reset the chip, just in case. */
1543 natsemi_reset(dev);
1544
1fb9df5d 1545 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1546 if (i) return i;
1547
1548 if (netif_msg_ifup(np))
1549 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1550 dev->name, dev->irq);
1551 i = alloc_ring(dev);
1552 if (i < 0) {
1553 free_irq(dev->irq, dev);
1554 return i;
1555 }
bea3348e
SH		 1556 napi_enable(&np->napi);
1557
1da177e4
LT		 1558 init_ring(dev);
1559 spin_lock_irq(&np->lock);
1560 init_registers(dev);
1561 /* now set the MAC address according to dev->dev_addr */
1562 for (i = 0; i < 3; i++) {
1563 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1564
1565 writel(i*2, ioaddr + RxFilterAddr);
1566 writew(mac, ioaddr + RxFilterData);
1567 }
1568 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1569 spin_unlock_irq(&np->lock);
1570
1571 netif_start_queue(dev);
1572
1573 if (netif_msg_ifup(np))
1574 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1575 dev->name, (int)readl(ioaddr + ChipCmd));
1576
1577 /* Set the timer to check for link beat. */
1578 init_timer(&np->timer);
0e5d5442 1579 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ);
1da177e4
LT		 1580 np->timer.data = (unsigned long)dev;
1581 np->timer.function = &netdev_timer; /* timer handler */
1582 add_timer(&np->timer);
1583
1584 return 0;
1585}
1586
1587static void do_cable_magic(struct net_device *dev)
1588{
1589 struct netdev_private *np = netdev_priv(dev);
1590 void __iomem *ioaddr = ns_ioaddr(dev);
1591
1592 if (dev->if_port != PORT_TP)
1593 return;
1594
1595 if (np->srr >= SRR_DP83816_A5)
1596 return;
1597
1598 /*
1599 * 100 MBit links with short cables can trip an issue with the chip.
1600 * The problem manifests as lots of CRC errors and/or flickering
1601 * activity LED while idle. This process is based on instructions
1602 * from engineers at National.
1603 */
1604 if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
1605 u16 data;
1606
1607 writew(1, ioaddr + PGSEL);
1608 /*
1609 * coefficient visibility should already be enabled via
1610 * DSPCFG | 0x1000
1611 */
1612 data = readw(ioaddr + TSTDAT) & 0xff;
1613 /*
1614 * the value must be negative, and within certain values
1615 * (these values all come from National)
1616 */
1617 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
ddfce6bb 1618 np = netdev_priv(dev);
1da177e4
LT		 1619
1620 /* the bug has been triggered - fix the coefficient */
1621 writew(TSTDAT_FIXED, ioaddr + TSTDAT);
1622 /* lock the value */
1623 data = readw(ioaddr + DSPCFG);
1624 np->dspcfg = data | DSPCFG_LOCK;
1625 writew(np->dspcfg, ioaddr + DSPCFG);
1626 }
1627 writew(0, ioaddr + PGSEL);
1628 }
1629}
1630
1631static void undo_cable_magic(struct net_device *dev)
1632{
1633 u16 data;
1634 struct netdev_private *np = netdev_priv(dev);
1635 void __iomem * ioaddr = ns_ioaddr(dev);
1636
1637 if (dev->if_port != PORT_TP)
1638 return;
1639
1640 if (np->srr >= SRR_DP83816_A5)
1641 return;
1642
1643 writew(1, ioaddr + PGSEL);
1644 /* make sure the lock bit is clear */
1645 data = readw(ioaddr + DSPCFG);
1646 np->dspcfg = data & ~DSPCFG_LOCK;
1647 writew(np->dspcfg, ioaddr + DSPCFG);
1648 writew(0, ioaddr + PGSEL);
1649}
1650
1651static void check_link(struct net_device *dev)
1652{
1653 struct netdev_private *np = netdev_priv(dev);
1654 void __iomem * ioaddr = ns_ioaddr(dev);
68c90166 1655 int duplex = np->duplex;
1da177e4 1656 u16 bmsr;
6aa20a22 1657
68c90166
MB		 1658 /* If we are ignoring the PHY then don't try reading it. */
1659 if (np->ignore_phy)
1660 goto propagate_state;
1661
1da177e4
LT		 1662 /* The link status field is latched: it remains low after a temporary
1663 * link failure until it's read. We need the current link status,
1664 * thus read twice.
1665 */
1666 mdio_read(dev, MII_BMSR);
1667 bmsr = mdio_read(dev, MII_BMSR);
1668
1669 if (!(bmsr & BMSR_LSTATUS)) {
1670 if (netif_carrier_ok(dev)) {
1671 if (netif_msg_link(np))
1672 printk(KERN_NOTICE "%s: link down.\n",
68c90166 1673 dev->name);
1da177e4
LT		 1674 netif_carrier_off(dev);
1675 undo_cable_magic(dev);
1676 }
1677 return;
1678 }
1679 if (!netif_carrier_ok(dev)) {
1680 if (netif_msg_link(np))
1681 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1682 netif_carrier_on(dev);
1683 do_cable_magic(dev);
1684 }
1685
1686 duplex = np->full_duplex;
1687 if (!duplex) {
1688 if (bmsr & BMSR_ANEGCOMPLETE) {
1689 int tmp = mii_nway_result(
1690 np->advertising & mdio_read(dev, MII_LPA));
1691 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1692 duplex = 1;
1693 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1694 duplex = 1;
1695 }
1696
68c90166 1697propagate_state:
1da177e4
LT		 1698 /* if duplex is set then bit 28 must be set, too */
1699 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1700 if (netif_msg_link(np))
1701 printk(KERN_INFO
1702 "%s: Setting %s-duplex based on negotiated "
1703 "link capability.\n", dev->name,
1704 duplex ? "full" : "half");
1705 if (duplex) {
1706 np->rx_config |= RxAcceptTx;
1707 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1708 } else {
1709 np->rx_config &= ~RxAcceptTx;
1710 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1711 }
1712 writel(np->tx_config, ioaddr + TxConfig);
1713 writel(np->rx_config, ioaddr + RxConfig);
1714 }
1715}
1716
1717static void init_registers(struct net_device *dev)
1718{
1719 struct netdev_private *np = netdev_priv(dev);
1720 void __iomem * ioaddr = ns_ioaddr(dev);
1721
1722 init_phy_fixup(dev);
1723
1724 /* clear any interrupts that are pending, such as wake events */
1725 readl(ioaddr + IntrStatus);
1726
1727 writel(np->ring_dma, ioaddr + RxRingPtr);
1728 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1729 ioaddr + TxRingPtr);
1730
1731 /* Initialize other registers.
1732 * Configure the PCI bus bursts and FIFO thresholds.
1733 * Configure for standard, in-spec Ethernet.
1734 * Start with half-duplex. check_link will update
1735 * to the correct settings.
1736 */
1737
1738 /* DRTH: 2: start tx if 64 bytes are in the fifo
1739 * FLTH: 0x10: refill with next packet if 512 bytes are free
1740 * MXDMA: 0: up to 256 byte bursts.
1741 * MXDMA must be <= FLTH
1742 * ECRETRY=1
1743 * ATP=1
1744 */
1745 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1746 TX_FLTH_VAL | TX_DRTH_VAL_START;
1747 writel(np->tx_config, ioaddr + TxConfig);
1748
1749 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1750 * MXDMA 0: up to 256 byte bursts
1751 */
1752 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1753 /* if receive ring now has bigger buffers than normal, enable jumbo */
1754 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1755 np->rx_config |= RxAcceptLong;
1756
1757 writel(np->rx_config, ioaddr + RxConfig);
1758
1759 /* Disable PME:
1760 * The PME bit is initialized from the EEPROM contents.
1761 * PCI cards probably have PME disabled, but motherboard
1762 * implementations may have PME set to enable WakeOnLan.
1763 * With PME set the chip will scan incoming packets but
1764 * nothing will be written to memory. */
1765 np->SavedClkRun = readl(ioaddr + ClkRun);
1766 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1767 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1768 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1769 dev->name, readl(ioaddr + WOLCmd));
1770 }
1771
1772 check_link(dev);
1773 __set_rx_mode(dev);
1774
1775 /* Enable interrupts by setting the interrupt mask. */
1776 writel(DEFAULT_INTR, ioaddr + IntrMask);
14fdd90e 1777 natsemi_irq_enable(dev);
1da177e4
LT		 1778
1779 writel(RxOn | TxOn, ioaddr + ChipCmd);
1780 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1781}
1782
1783/*
1784 * netdev_timer:
1785 * Purpose:
1786 * 1) check for link changes. Usually they are handled by the MII interrupt
1787 * but it doesn't hurt to check twice.
1788 * 2) check for sudden death of the NIC:
1789 * It seems that a reference set for this chip went out with incorrect info,
1790 * and there exist boards that aren't quite right. An unexpected voltage
1791 * drop can cause the PHY to get itself in a weird state (basically reset).
1a147809
MB		 1792 * NOTE: this only seems to affect revC chips. The user can disable
1793 * this check via dspcfg_workaround sysfs option.
1da177e4
LT		 1794 * 3) check of death of the RX path due to OOM
1795 */
1796static void netdev_timer(unsigned long data)
1797{
1798 struct net_device *dev = (struct net_device *)data;
1799 struct netdev_private *np = netdev_priv(dev);
1800 void __iomem * ioaddr = ns_ioaddr(dev);
f2cade13 1801 int next_tick = NATSEMI_TIMER_FREQ;
1da177e4
LT		 1802
1803 if (netif_msg_timer(np)) {
1804 /* DO NOT read the IntrStatus register,
1805 * a read clears any pending interrupts.
1806 */
1807 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1808 dev->name);
1809 }
1810
1811 if (dev->if_port == PORT_TP) {
1812 u16 dspcfg;
1813
1814 spin_lock_irq(&np->lock);
1815 /* check for a nasty random phy-reset - use dspcfg as a flag */
1816 writew(1, ioaddr+PGSEL);
1817 dspcfg = readw(ioaddr+DSPCFG);
1818 writew(0, ioaddr+PGSEL);
1a147809 1819 if (np->dspcfg_workaround && dspcfg != np->dspcfg) {
1da177e4
LT		 1820 if (!netif_queue_stopped(dev)) {
1821 spin_unlock_irq(&np->lock);
d0ed4864 1822 if (netif_msg_drv(np))
1da177e4
LT		 1823 printk(KERN_NOTICE "%s: possible phy reset: "
1824 "re-initializing\n", dev->name);
1825 disable_irq(dev->irq);
1826 spin_lock_irq(&np->lock);
1827 natsemi_stop_rxtx(dev);
1828 dump_ring(dev);
1829 reinit_ring(dev);
1830 init_registers(dev);
1831 spin_unlock_irq(&np->lock);
1832 enable_irq(dev->irq);
1833 } else {
1834 /* hurry back */
1835 next_tick = HZ;
1836 spin_unlock_irq(&np->lock);
1837 }
1838 } else {
1839 /* init_registers() calls check_link() for the above case */
1840 check_link(dev);
1841 spin_unlock_irq(&np->lock);
1842 }
1843 } else {
1844 spin_lock_irq(&np->lock);
1845 check_link(dev);
1846 spin_unlock_irq(&np->lock);
1847 }
1848 if (np->oom) {
1849 disable_irq(dev->irq);
1850 np->oom = 0;
1851 refill_rx(dev);
1852 enable_irq(dev->irq);
1853 if (!np->oom) {
1854 writel(RxOn, ioaddr + ChipCmd);
1855 } else {
1856 next_tick = 1;
1857 }
1858 }
0e5d5442
MB		 1859
1860 if (next_tick > 1)
1861 mod_timer(&np->timer, round_jiffies(jiffies + next_tick));
1862 else
1863 mod_timer(&np->timer, jiffies + next_tick);
1da177e4
LT		 1864}
1865
1866static void dump_ring(struct net_device *dev)
1867{
1868 struct netdev_private *np = netdev_priv(dev);
1869
1870 if (netif_msg_pktdata(np)) {
1871 int i;
1872 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1873 for (i = 0; i < TX_RING_SIZE; i++) {
1874 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1875 i, np->tx_ring[i].next_desc,
1876 np->tx_ring[i].cmd_status,
1877 np->tx_ring[i].addr);
1878 }
1879 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1880 for (i = 0; i < RX_RING_SIZE; i++) {
1881 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1882 i, np->rx_ring[i].next_desc,
1883 np->rx_ring[i].cmd_status,
1884 np->rx_ring[i].addr);
1885 }
1886 }
1887}
1888
1889static void tx_timeout(struct net_device *dev)
1890{
1891 struct netdev_private *np = netdev_priv(dev);
1892 void __iomem * ioaddr = ns_ioaddr(dev);
1893
1894 disable_irq(dev->irq);
1895 spin_lock_irq(&np->lock);
1896 if (!np->hands_off) {
1897 if (netif_msg_tx_err(np))
1898 printk(KERN_WARNING
1899 "%s: Transmit timed out, status %#08x,"
1900 " resetting...\n",
1901 dev->name, readl(ioaddr + IntrStatus));
1902 dump_ring(dev);
1903
1904 natsemi_reset(dev);
1905 reinit_ring(dev);
1906 init_registers(dev);
1907 } else {
1908 printk(KERN_WARNING
1909 "%s: tx_timeout while in hands_off state?\n",
1910 dev->name);
1911 }
1912 spin_unlock_irq(&np->lock);
1913 enable_irq(dev->irq);
1914
1915 dev->trans_start = jiffies;
1916 np->stats.tx_errors++;
1917 netif_wake_queue(dev);
1918}
1919
1920static int alloc_ring(struct net_device *dev)
1921{
1922 struct netdev_private *np = netdev_priv(dev);
1923 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1924 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1925 &np->ring_dma);
1926 if (!np->rx_ring)
1927 return -ENOMEM;
1928 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1929 return 0;
1930}
1931
1932static void refill_rx(struct net_device *dev)
1933{
1934 struct netdev_private *np = netdev_priv(dev);
1935
1936 /* Refill the Rx ring buffers. */
1937 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1938 struct sk_buff *skb;
1939 int entry = np->dirty_rx % RX_RING_SIZE;
1940 if (np->rx_skbuff[entry] == NULL) {
1941 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1942 skb = dev_alloc_skb(buflen);
1943 np->rx_skbuff[entry] = skb;
1944 if (skb == NULL)
1945 break; /* Better luck next round. */
1946 skb->dev = dev; /* Mark as being used by this device. */
1947 np->rx_dma[entry] = pci_map_single(np->pci_dev,
689be439 1948 skb->data, buflen, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1949 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1950 }
1951 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1952 }
1953 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1954 if (netif_msg_rx_err(np))
1955 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1956 np->oom = 1;
1957 }
1958}
1959
1960static void set_bufsize(struct net_device *dev)
1961{
1962 struct netdev_private *np = netdev_priv(dev);
1963 if (dev->mtu <= ETH_DATA_LEN)
1964 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1965 else
1966 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1967}
1968
1969/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1970static void init_ring(struct net_device *dev)
1971{
1972 struct netdev_private *np = netdev_priv(dev);
1973 int i;
1974
1975 /* 1) TX ring */
1976 np->dirty_tx = np->cur_tx = 0;
1977 for (i = 0; i < TX_RING_SIZE; i++) {
1978 np->tx_skbuff[i] = NULL;
1979 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1980 +sizeof(struct netdev_desc)
1981 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1982 np->tx_ring[i].cmd_status = 0;
1983 }
1984
1985 /* 2) RX ring */
1986 np->dirty_rx = 0;
1987 np->cur_rx = RX_RING_SIZE;
1988 np->oom = 0;
1989 set_bufsize(dev);
1990
1991 np->rx_head_desc = &np->rx_ring[0];
1992
1993 /* Please be carefull before changing this loop - at least gcc-2.95.1
1994 * miscompiles it otherwise.
1995 */
1996 /* Initialize all Rx descriptors. */
1997 for (i = 0; i < RX_RING_SIZE; i++) {
1998 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1999 +sizeof(struct netdev_desc)
2000 *((i+1)%RX_RING_SIZE));
2001 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2002 np->rx_skbuff[i] = NULL;
2003 }
2004 refill_rx(dev);
2005 dump_ring(dev);
2006}
2007
2008static void drain_tx(struct net_device *dev)
2009{
2010 struct netdev_private *np = netdev_priv(dev);
2011 int i;
2012
2013 for (i = 0; i < TX_RING_SIZE; i++) {
2014 if (np->tx_skbuff[i]) {
2015 pci_unmap_single(np->pci_dev,
2016 np->tx_dma[i], np->tx_skbuff[i]->len,
2017 PCI_DMA_TODEVICE);
2018 dev_kfree_skb(np->tx_skbuff[i]);
2019 np->stats.tx_dropped++;
2020 }
2021 np->tx_skbuff[i] = NULL;
2022 }
2023}
2024
2025static void drain_rx(struct net_device *dev)
2026{
2027 struct netdev_private *np = netdev_priv(dev);
2028 unsigned int buflen = np->rx_buf_sz;
2029 int i;
2030
2031 /* Free all the skbuffs in the Rx queue. */
2032 for (i = 0; i < RX_RING_SIZE; i++) {
2033 np->rx_ring[i].cmd_status = 0;
2034 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
2035 if (np->rx_skbuff[i]) {
2036 pci_unmap_single(np->pci_dev,
2037 np->rx_dma[i], buflen,
2038 PCI_DMA_FROMDEVICE);
2039 dev_kfree_skb(np->rx_skbuff[i]);
2040 }
2041 np->rx_skbuff[i] = NULL;
2042 }
2043}
2044
2045static void drain_ring(struct net_device *dev)
2046{
2047 drain_rx(dev);
2048 drain_tx(dev);
2049}
2050
2051static void free_ring(struct net_device *dev)
2052{
2053 struct netdev_private *np = netdev_priv(dev);
2054 pci_free_consistent(np->pci_dev,
2055 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2056 np->rx_ring, np->ring_dma);
2057}
2058
2059static void reinit_rx(struct net_device *dev)
2060{
2061 struct netdev_private *np = netdev_priv(dev);
2062 int i;
2063
2064 /* RX Ring */
2065 np->dirty_rx = 0;
2066 np->cur_rx = RX_RING_SIZE;
2067 np->rx_head_desc = &np->rx_ring[0];
2068 /* Initialize all Rx descriptors. */
2069 for (i = 0; i < RX_RING_SIZE; i++)
2070 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2071
2072 refill_rx(dev);
2073}
2074
2075static void reinit_ring(struct net_device *dev)
2076{
2077 struct netdev_private *np = netdev_priv(dev);
2078 int i;
2079
2080 /* drain TX ring */
2081 drain_tx(dev);
2082 np->dirty_tx = np->cur_tx = 0;
2083 for (i=0;i<TX_RING_SIZE;i++)
2084 np->tx_ring[i].cmd_status = 0;
2085
2086 reinit_rx(dev);
2087}
2088
2089static int start_tx(struct sk_buff *skb, struct net_device *dev)
2090{
2091 struct netdev_private *np = netdev_priv(dev);
2092 void __iomem * ioaddr = ns_ioaddr(dev);
2093 unsigned entry;
6006f7f5 2094 unsigned long flags;
1da177e4
LT		 2095
2096 /* Note: Ordering is important here, set the field with the
2097 "ownership" bit last, and only then increment cur_tx. */
2098
2099 /* Calculate the next Tx descriptor entry. */
2100 entry = np->cur_tx % TX_RING_SIZE;
2101
2102 np->tx_skbuff[entry] = skb;
2103 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2104 skb->data,skb->len, PCI_DMA_TODEVICE);
2105
2106 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2107
6006f7f5 2108 spin_lock_irqsave(&np->lock, flags);
1da177e4
LT		 2109
2110 if (!np->hands_off) {
2111 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2112 /* StrongARM: Explicitly cache flush np->tx_ring and
2113 * skb->data,skb->len. */
2114 wmb();
2115 np->cur_tx++;
2116 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2117 netdev_tx_done(dev);
2118 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2119 netif_stop_queue(dev);
2120 }
2121 /* Wake the potentially-idle transmit channel. */
2122 writel(TxOn, ioaddr + ChipCmd);
2123 } else {
2124 dev_kfree_skb_irq(skb);
2125 np->stats.tx_dropped++;
2126 }
6006f7f5 2127 spin_unlock_irqrestore(&np->lock, flags);
1da177e4
LT		 2128
2129 dev->trans_start = jiffies;
2130
2131 if (netif_msg_tx_queued(np)) {
2132 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2133 dev->name, np->cur_tx, entry);
2134 }
2135 return 0;
2136}
2137
2138static void netdev_tx_done(struct net_device *dev)
2139{
2140 struct netdev_private *np = netdev_priv(dev);
2141
2142 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2143 int entry = np->dirty_tx % TX_RING_SIZE;
2144 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2145 break;
2146 if (netif_msg_tx_done(np))
2147 printk(KERN_DEBUG
2148 "%s: tx frame #%d finished, status %#08x.\n",
2149 dev->name, np->dirty_tx,
2150 le32_to_cpu(np->tx_ring[entry].cmd_status));
2151 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2152 np->stats.tx_packets++;
2153 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2154 } else { /* Various Tx errors */
2155 int tx_status =
2156 le32_to_cpu(np->tx_ring[entry].cmd_status);
2157 if (tx_status & (DescTxAbort|DescTxExcColl))
2158 np->stats.tx_aborted_errors++;
2159 if (tx_status & DescTxFIFO)
2160 np->stats.tx_fifo_errors++;
2161 if (tx_status & DescTxCarrier)
2162 np->stats.tx_carrier_errors++;
2163 if (tx_status & DescTxOOWCol)
2164 np->stats.tx_window_errors++;
2165 np->stats.tx_errors++;
2166 }
2167 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2168 np->tx_skbuff[entry]->len,
2169 PCI_DMA_TODEVICE);
2170 /* Free the original skb. */
2171 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2172 np->tx_skbuff[entry] = NULL;
2173 }
2174 if (netif_queue_stopped(dev)
2175 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2176 /* The ring is no longer full, wake queue. */
2177 netif_wake_queue(dev);
2178 }
2179}
2180
b27a16b7
MB		 2181/* The interrupt handler doesn't actually handle interrupts itself, it
2182 * schedules a NAPI poll if there is anything to do. */
7d12e780 2183static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 2184{
2185 struct net_device *dev = dev_instance;
2186 struct netdev_private *np = netdev_priv(dev);
2187 void __iomem * ioaddr = ns_ioaddr(dev);
1da177e4 2188
069f8256
MB		 2189 /* Reading IntrStatus automatically acknowledges so don't do
2190 * that while interrupts are disabled, (for example, while a
2191 * poll is scheduled). */
2192 if (np->hands_off || !readl(ioaddr + IntrEnable))
1da177e4 2193 return IRQ_NONE;
6aa20a22 2194
b27a16b7 2195 np->intr_status = readl(ioaddr + IntrStatus);
1da177e4 2196
069f8256
MB		 2197 if (!np->intr_status)
2198 return IRQ_NONE;
2199
b27a16b7
MB		 2200 if (netif_msg_intr(np))
2201 printk(KERN_DEBUG
2202 "%s: Interrupt, status %#08x, mask %#08x.\n",
2203 dev->name, np->intr_status,
2204 readl(ioaddr + IntrMask));
1da177e4 2205
b27a16b7
MB		 2206 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
2207
bea3348e 2208 if (netif_rx_schedule_prep(dev, &np->napi)) {
b27a16b7
MB		 2209 /* Disable interrupts and register for poll */
2210 natsemi_irq_disable(dev);
bea3348e 2211 __netif_rx_schedule(dev, &np->napi);
069f8256
MB		 2212 } else
2213 printk(KERN_WARNING
2214 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
2215 dev->name, np->intr_status,
2216 readl(ioaddr + IntrMask));
2217
b27a16b7
MB		 2218 return IRQ_HANDLED;
2219}
2220
2221/* This is the NAPI poll routine. As well as the standard RX handling
2222 * it also handles all other interrupts that the chip might raise.
2223 */
bea3348e 2224static int natsemi_poll(struct napi_struct *napi, int budget)
b27a16b7 2225{
bea3348e
SH		 2226 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
2227 struct net_device *dev = np->dev;
b27a16b7 2228 void __iomem * ioaddr = ns_ioaddr(dev);
b27a16b7
MB		 2229 int work_done = 0;
2230
2231 do {
069f8256
MB		 2232 if (netif_msg_intr(np))
2233 printk(KERN_DEBUG
2234 "%s: Poll, status %#08x, mask %#08x.\n",
2235 dev->name, np->intr_status,
2236 readl(ioaddr + IntrMask));
2237
d2a90036
MB		 2238 /* netdev_rx() may read IntrStatus again if the RX state
2239 * machine falls over so do it first. */
2240 if (np->intr_status &
2241 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2242 IntrRxErr | IntrRxOverrun)) {
bea3348e 2243 netdev_rx(dev, &work_done, budget);
d2a90036
MB		 2244 }
2245
b27a16b7
MB		 2246 if (np->intr_status &
2247 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
1da177e4
LT		 2248 spin_lock(&np->lock);
2249 netdev_tx_done(dev);
2250 spin_unlock(&np->lock);
2251 }
2252
2253 /* Abnormal error summary/uncommon events handlers. */
b27a16b7
MB		 2254 if (np->intr_status & IntrAbnormalSummary)
2255 netdev_error(dev, np->intr_status);
6aa20a22 2256
bea3348e
SH		 2257 if (work_done >= budget)
2258 return work_done;
b27a16b7
MB		 2259
2260 np->intr_status = readl(ioaddr + IntrStatus);
2261 } while (np->intr_status);
1da177e4 2262
bea3348e 2263 netif_rx_complete(dev, napi);
b27a16b7
MB		 2264
2265 /* Reenable interrupts providing nothing is trying to shut
2266 * the chip down. */
2267 spin_lock(&np->lock);
2268 if (!np->hands_off && netif_running(dev))
2269 natsemi_irq_enable(dev);
2270 spin_unlock(&np->lock);
2271
bea3348e 2272 return work_done;
1da177e4
LT		 2273}
2274
2275/* This routine is logically part of the interrupt handler, but separated
2276 for clarity and better register allocation. */
b27a16b7 2277static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
1da177e4
LT		 2278{
2279 struct netdev_private *np = netdev_priv(dev);
2280 int entry = np->cur_rx % RX_RING_SIZE;
2281 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2282 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2283 unsigned int buflen = np->rx_buf_sz;
2284 void __iomem * ioaddr = ns_ioaddr(dev);
2285
2286 /* If the driver owns the next entry it's a new packet. Send it up. */
2287 while (desc_status < 0) { /* e.g. & DescOwn */
2288 int pkt_len;
2289 if (netif_msg_rx_status(np))
2290 printk(KERN_DEBUG
2291 " netdev_rx() entry %d status was %#08x.\n",
2292 entry, desc_status);
2293 if (--boguscnt < 0)
2294 break;
b27a16b7
MB		 2295
2296 if (*work_done >= work_to_do)
2297 break;
2298
2299 (*work_done)++;
2300
1da177e4
LT		 2301 pkt_len = (desc_status & DescSizeMask) - 4;
2302 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2303 if (desc_status & DescMore) {
6006f7f5
SS		 2304 unsigned long flags;
2305
1da177e4
LT		 2306 if (netif_msg_rx_err(np))
2307 printk(KERN_WARNING
2308 "%s: Oversized(?) Ethernet "
2309 "frame spanned multiple "
2310 "buffers, entry %#08x "
2311 "status %#08x.\n", dev->name,
2312 np->cur_rx, desc_status);
2313 np->stats.rx_length_errors++;
e72fd96e
MB		 2314
2315 /* The RX state machine has probably
2316 * locked up beneath us. Follow the
2317 * reset procedure documented in
2318 * AN-1287. */
2319
6006f7f5 2320 spin_lock_irqsave(&np->lock, flags);
e72fd96e
MB		 2321 reset_rx(dev);
2322 reinit_rx(dev);
2323 writel(np->ring_dma, ioaddr + RxRingPtr);
2324 check_link(dev);
6006f7f5 2325 spin_unlock_irqrestore(&np->lock, flags);
e72fd96e
MB		 2326
2327 /* We'll enable RX on exit from this
2328 * function. */
2329 break;
2330
1da177e4
LT		 2331 } else {
2332 /* There was an error. */
2333 np->stats.rx_errors++;
2334 if (desc_status & (DescRxAbort|DescRxOver))
2335 np->stats.rx_over_errors++;
2336 if (desc_status & (DescRxLong|DescRxRunt))
2337 np->stats.rx_length_errors++;
2338 if (desc_status & (DescRxInvalid|DescRxAlign))
2339 np->stats.rx_frame_errors++;
2340 if (desc_status & DescRxCRC)
2341 np->stats.rx_crc_errors++;
2342 }
2343 } else if (pkt_len > np->rx_buf_sz) {
2344 /* if this is the tail of a double buffer
2345 * packet, we've already counted the error
2346 * on the first part. Ignore the second half.
2347 */
2348 } else {
2349 struct sk_buff *skb;
2350 /* Omit CRC size. */
2351 /* Check if the packet is long enough to accept
2352 * without copying to a minimally-sized skbuff. */
2353 if (pkt_len < rx_copybreak
2354 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
1da177e4
LT		 2355 /* 16 byte align the IP header */
2356 skb_reserve(skb, RX_OFFSET);
2357 pci_dma_sync_single_for_cpu(np->pci_dev,
2358 np->rx_dma[entry],
2359 buflen,
2360 PCI_DMA_FROMDEVICE);
8c7b7faa
DM		 2361 skb_copy_to_linear_data(skb,
2362 np->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT		 2363 skb_put(skb, pkt_len);
2364 pci_dma_sync_single_for_device(np->pci_dev,
2365 np->rx_dma[entry],
2366 buflen,
2367 PCI_DMA_FROMDEVICE);
2368 } else {
2369 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2370 buflen, PCI_DMA_FROMDEVICE);
2371 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2372 np->rx_skbuff[entry] = NULL;
2373 }
2374 skb->protocol = eth_type_trans(skb, dev);
b27a16b7 2375 netif_receive_skb(skb);
1da177e4
LT		 2376 dev->last_rx = jiffies;
2377 np->stats.rx_packets++;
2378 np->stats.rx_bytes += pkt_len;
2379 }
2380 entry = (++np->cur_rx) % RX_RING_SIZE;
2381 np->rx_head_desc = &np->rx_ring[entry];
2382 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2383 }
2384 refill_rx(dev);
2385
2386 /* Restart Rx engine if stopped. */
2387 if (np->oom)
2388 mod_timer(&np->timer, jiffies + 1);
2389 else
2390 writel(RxOn, ioaddr + ChipCmd);
2391}
2392
2393static void netdev_error(struct net_device *dev, int intr_status)
2394{
2395 struct netdev_private *np = netdev_priv(dev);
2396 void __iomem * ioaddr = ns_ioaddr(dev);
2397
2398 spin_lock(&np->lock);
2399 if (intr_status & LinkChange) {
2400 u16 lpa = mdio_read(dev, MII_LPA);
2401 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2402 && netif_msg_link(np)) {
2403 printk(KERN_INFO
2404 "%s: Autonegotiation advertising"
2405 " %#04x partner %#04x.\n", dev->name,
2406 np->advertising, lpa);
2407 }
2408
2409 /* read MII int status to clear the flag */
2410 readw(ioaddr + MIntrStatus);
2411 check_link(dev);
2412 }
2413 if (intr_status & StatsMax) {
2414 __get_stats(dev);
2415 }
2416 if (intr_status & IntrTxUnderrun) {
2417 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2418 np->tx_config += TX_DRTH_VAL_INC;
2419 if (netif_msg_tx_err(np))
2420 printk(KERN_NOTICE
2421 "%s: increased tx threshold, txcfg %#08x.\n",
2422 dev->name, np->tx_config);
2423 } else {
2424 if (netif_msg_tx_err(np))
2425 printk(KERN_NOTICE
2426 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2427 dev->name, np->tx_config);
2428 }
2429 writel(np->tx_config, ioaddr + TxConfig);
2430 }
2431 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2432 int wol_status = readl(ioaddr + WOLCmd);
2433 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2434 dev->name, wol_status);
2435 }
2436 if (intr_status & RxStatusFIFOOver) {
2437 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2438 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2439 dev->name);
2440 }
2441 np->stats.rx_fifo_errors++;
c76720cf 2442 np->stats.rx_errors++;
1da177e4
LT		 2443 }
2444 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2445 if (intr_status & IntrPCIErr) {
2446 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2447 intr_status & IntrPCIErr);
2448 np->stats.tx_fifo_errors++;
c76720cf 2449 np->stats.tx_errors++;
1da177e4 2450 np->stats.rx_fifo_errors++;
c76720cf 2451 np->stats.rx_errors++;
1da177e4
LT		 2452 }
2453 spin_unlock(&np->lock);
2454}
2455
2456static void __get_stats(struct net_device *dev)
2457{
2458 void __iomem * ioaddr = ns_ioaddr(dev);
2459 struct netdev_private *np = netdev_priv(dev);
2460
2461 /* The chip only need report frame silently dropped. */
2462 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2463 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2464}
2465
2466static struct net_device_stats *get_stats(struct net_device *dev)
2467{
2468 struct netdev_private *np = netdev_priv(dev);
2469
2470 /* The chip only need report frame silently dropped. */
2471 spin_lock_irq(&np->lock);
2472 if (netif_running(dev) && !np->hands_off)
2473 __get_stats(dev);
2474 spin_unlock_irq(&np->lock);
2475
2476 return &np->stats;
2477}
2478
2479#ifdef CONFIG_NET_POLL_CONTROLLER
2480static void natsemi_poll_controller(struct net_device *dev)
2481{
2482 disable_irq(dev->irq);
069f8256 2483 intr_handler(dev->irq, dev);
1da177e4
LT		 2484 enable_irq(dev->irq);
2485}
2486#endif
2487
2488#define HASH_TABLE 0x200
2489static void __set_rx_mode(struct net_device *dev)
2490{
2491 void __iomem * ioaddr = ns_ioaddr(dev);
2492 struct netdev_private *np = netdev_priv(dev);
2493 u8 mc_filter[64]; /* Multicast hash filter */
2494 u32 rx_mode;
2495
2496 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 2497 rx_mode = RxFilterEnable | AcceptBroadcast
2498 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2499 } else if ((dev->mc_count > multicast_filter_limit)
2500 || (dev->flags & IFF_ALLMULTI)) {
2501 rx_mode = RxFilterEnable | AcceptBroadcast
2502 | AcceptAllMulticast | AcceptMyPhys;
2503 } else {
2504 struct dev_mc_list *mclist;
2505 int i;
2506 memset(mc_filter, 0, sizeof(mc_filter));
2507 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2508 i++, mclist = mclist->next) {
ddfce6bb
SH		 2509 int b = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2510 mc_filter[b/8] |= (1 << (b & 0x07));
1da177e4
LT		 2511 }
2512 rx_mode = RxFilterEnable | AcceptBroadcast
2513 | AcceptMulticast | AcceptMyPhys;
2514 for (i = 0; i < 64; i += 2) {
760f86d7
HX		 2515 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2516 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2517 ioaddr + RxFilterData);
1da177e4
LT		 2518 }
2519 }
2520 writel(rx_mode, ioaddr + RxFilterAddr);
2521 np->cur_rx_mode = rx_mode;
2522}
2523
2524static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2525{
2526 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2527 return -EINVAL;
2528
2529 dev->mtu = new_mtu;
2530
2531 /* synchronized against open : rtnl_lock() held by caller */
2532 if (netif_running(dev)) {
2533 struct netdev_private *np = netdev_priv(dev);
2534 void __iomem * ioaddr = ns_ioaddr(dev);
2535
2536 disable_irq(dev->irq);
2537 spin_lock(&np->lock);
2538 /* stop engines */
2539 natsemi_stop_rxtx(dev);
2540 /* drain rx queue */
2541 drain_rx(dev);
2542 /* change buffers */
2543 set_bufsize(dev);
2544 reinit_rx(dev);
2545 writel(np->ring_dma, ioaddr + RxRingPtr);
2546 /* restart engines */
2547 writel(RxOn | TxOn, ioaddr + ChipCmd);
2548 spin_unlock(&np->lock);
2549 enable_irq(dev->irq);
2550 }
2551 return 0;
2552}
2553
2554static void set_rx_mode(struct net_device *dev)
2555{
2556 struct netdev_private *np = netdev_priv(dev);
2557 spin_lock_irq(&np->lock);
2558 if (!np->hands_off)
2559 __set_rx_mode(dev);
2560 spin_unlock_irq(&np->lock);
2561}
2562
2563static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2564{
2565 struct netdev_private *np = netdev_priv(dev);
2566 strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2567 strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2568 strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
2569}
2570
2571static int get_regs_len(struct net_device *dev)
2572{
2573 return NATSEMI_REGS_SIZE;
2574}
2575
2576static int get_eeprom_len(struct net_device *dev)
2577{
a8b4cf42
MB		 2578 struct netdev_private *np = netdev_priv(dev);
2579 return np->eeprom_size;
1da177e4
LT		 2580}
2581
2582static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2583{
2584 struct netdev_private *np = netdev_priv(dev);
2585 spin_lock_irq(&np->lock);
2586 netdev_get_ecmd(dev, ecmd);
2587 spin_unlock_irq(&np->lock);
2588 return 0;
2589}
2590
2591static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2592{
2593 struct netdev_private *np = netdev_priv(dev);
2594 int res;
2595 spin_lock_irq(&np->lock);
2596 res = netdev_set_ecmd(dev, ecmd);
2597 spin_unlock_irq(&np->lock);
2598 return res;
2599}
2600
2601static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2602{
2603 struct netdev_private *np = netdev_priv(dev);
2604 spin_lock_irq(&np->lock);
2605 netdev_get_wol(dev, &wol->supported, &wol->wolopts);
2606 netdev_get_sopass(dev, wol->sopass);
2607 spin_unlock_irq(&np->lock);
2608}
2609
2610static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2611{
2612 struct netdev_private *np = netdev_priv(dev);
2613 int res;
2614 spin_lock_irq(&np->lock);
2615 netdev_set_wol(dev, wol->wolopts);
2616 res = netdev_set_sopass(dev, wol->sopass);
2617 spin_unlock_irq(&np->lock);
2618 return res;
2619}
2620
2621static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2622{
2623 struct netdev_private *np = netdev_priv(dev);
2624 regs->version = NATSEMI_REGS_VER;
2625 spin_lock_irq(&np->lock);
2626 netdev_get_regs(dev, buf);
2627 spin_unlock_irq(&np->lock);
2628}
2629
2630static u32 get_msglevel(struct net_device *dev)
2631{
2632 struct netdev_private *np = netdev_priv(dev);
2633 return np->msg_enable;
2634}
2635
2636static void set_msglevel(struct net_device *dev, u32 val)
2637{
2638 struct netdev_private *np = netdev_priv(dev);
2639 np->msg_enable = val;
2640}
2641
2642static int nway_reset(struct net_device *dev)
2643{
2644 int tmp;
2645 int r = -EINVAL;
2646 /* if autoneg is off, it's an error */
2647 tmp = mdio_read(dev, MII_BMCR);
2648 if (tmp & BMCR_ANENABLE) {
2649 tmp |= (BMCR_ANRESTART);
2650 mdio_write(dev, MII_BMCR, tmp);
2651 r = 0;
2652 }
2653 return r;
2654}
2655
2656static u32 get_link(struct net_device *dev)
2657{
2658 /* LSTATUS is latched low until a read - so read twice */
2659 mdio_read(dev, MII_BMSR);
2660 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2661}
2662
2663static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2664{
2665 struct netdev_private *np = netdev_priv(dev);
a8b4cf42 2666 u8 *eebuf;
1da177e4
LT		 2667 int res;
2668
a8b4cf42
MB		 2669 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
2670 if (!eebuf)
2671 return -ENOMEM;
2672
1da177e4
LT		 2673 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2674 spin_lock_irq(&np->lock);
2675 res = netdev_get_eeprom(dev, eebuf);
2676 spin_unlock_irq(&np->lock);
2677 if (!res)
2678 memcpy(data, eebuf+eeprom->offset, eeprom->len);
a8b4cf42 2679 kfree(eebuf);
1da177e4
LT		 2680 return res;
2681}
2682
7282d491 2683static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 2684 .get_drvinfo = get_drvinfo,
2685 .get_regs_len = get_regs_len,
2686 .get_eeprom_len = get_eeprom_len,
2687 .get_settings = get_settings,
2688 .set_settings = set_settings,
2689 .get_wol = get_wol,
2690 .set_wol = set_wol,
2691 .get_regs = get_regs,
2692 .get_msglevel = get_msglevel,
2693 .set_msglevel = set_msglevel,
2694 .nway_reset = nway_reset,
2695 .get_link = get_link,
2696 .get_eeprom = get_eeprom,
2697};
2698
2699static int netdev_set_wol(struct net_device *dev, u32 newval)
2700{
2701 struct netdev_private *np = netdev_priv(dev);
2702 void __iomem * ioaddr = ns_ioaddr(dev);
2703 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
2704
2705 /* translate to bitmasks this chip understands */
2706 if (newval & WAKE_PHY)
2707 data |= WakePhy;
2708 if (newval & WAKE_UCAST)
2709 data |= WakeUnicast;
2710 if (newval & WAKE_MCAST)
2711 data |= WakeMulticast;
2712 if (newval & WAKE_BCAST)
2713 data |= WakeBroadcast;
2714 if (newval & WAKE_ARP)
2715 data |= WakeArp;
2716 if (newval & WAKE_MAGIC)
2717 data |= WakeMagic;
2718 if (np->srr >= SRR_DP83815_D) {
2719 if (newval & WAKE_MAGICSECURE) {
2720 data |= WakeMagicSecure;
2721 }
2722 }
2723
2724 writel(data, ioaddr + WOLCmd);
2725
2726 return 0;
2727}
2728
2729static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2730{
2731 struct netdev_private *np = netdev_priv(dev);
2732 void __iomem * ioaddr = ns_ioaddr(dev);
2733 u32 regval = readl(ioaddr + WOLCmd);
2734
2735 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2736 | WAKE_ARP | WAKE_MAGIC);
2737
2738 if (np->srr >= SRR_DP83815_D) {
2739 /* SOPASS works on revD and higher */
2740 *supported |= WAKE_MAGICSECURE;
2741 }
2742 *cur = 0;
2743
2744 /* translate from chip bitmasks */
2745 if (regval & WakePhy)
2746 *cur |= WAKE_PHY;
2747 if (regval & WakeUnicast)
2748 *cur |= WAKE_UCAST;
2749 if (regval & WakeMulticast)
2750 *cur |= WAKE_MCAST;
2751 if (regval & WakeBroadcast)
2752 *cur |= WAKE_BCAST;
2753 if (regval & WakeArp)
2754 *cur |= WAKE_ARP;
2755 if (regval & WakeMagic)
2756 *cur |= WAKE_MAGIC;
2757 if (regval & WakeMagicSecure) {
2758 /* this can be on in revC, but it's broken */
2759 *cur |= WAKE_MAGICSECURE;
2760 }
2761
2762 return 0;
2763}
2764
2765static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2766{
2767 struct netdev_private *np = netdev_priv(dev);
2768 void __iomem * ioaddr = ns_ioaddr(dev);
2769 u16 *sval = (u16 *)newval;
2770 u32 addr;
2771
2772 if (np->srr < SRR_DP83815_D) {
2773 return 0;
2774 }
2775
2776 /* enable writing to these registers by disabling the RX filter */
2777 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2778 addr &= ~RxFilterEnable;
2779 writel(addr, ioaddr + RxFilterAddr);
2780
2781 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2782 writel(addr | 0xa, ioaddr + RxFilterAddr);
2783 writew(sval[0], ioaddr + RxFilterData);
2784
2785 writel(addr | 0xc, ioaddr + RxFilterAddr);
2786 writew(sval[1], ioaddr + RxFilterData);
2787
2788 writel(addr | 0xe, ioaddr + RxFilterAddr);
2789 writew(sval[2], ioaddr + RxFilterData);
2790
2791 /* re-enable the RX filter */
2792 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
2793
2794 return 0;
2795}
2796
2797static int netdev_get_sopass(struct net_device *dev, u8 *data)
2798{
2799 struct netdev_private *np = netdev_priv(dev);
2800 void __iomem * ioaddr = ns_ioaddr(dev);
2801 u16 *sval = (u16 *)data;
2802 u32 addr;
2803
2804 if (np->srr < SRR_DP83815_D) {
2805 sval[0] = sval[1] = sval[2] = 0;
2806 return 0;
2807 }
2808
2809 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2810 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
2811
2812 writel(addr | 0xa, ioaddr + RxFilterAddr);
2813 sval[0] = readw(ioaddr + RxFilterData);
2814
2815 writel(addr | 0xc, ioaddr + RxFilterAddr);
2816 sval[1] = readw(ioaddr + RxFilterData);
2817
2818 writel(addr | 0xe, ioaddr + RxFilterAddr);
2819 sval[2] = readw(ioaddr + RxFilterData);
2820
2821 writel(addr, ioaddr + RxFilterAddr);
2822
2823 return 0;
2824}
2825
2826static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2827{
2828 struct netdev_private *np = netdev_priv(dev);
2829 u32 tmp;
2830
2831 ecmd->port = dev->if_port;
2832 ecmd->speed = np->speed;
2833 ecmd->duplex = np->duplex;
2834 ecmd->autoneg = np->autoneg;
2835 ecmd->advertising = 0;
2836 if (np->advertising & ADVERTISE_10HALF)
2837 ecmd->advertising |= ADVERTISED_10baseT_Half;
2838 if (np->advertising & ADVERTISE_10FULL)
2839 ecmd->advertising |= ADVERTISED_10baseT_Full;
2840 if (np->advertising & ADVERTISE_100HALF)
2841 ecmd->advertising |= ADVERTISED_100baseT_Half;
2842 if (np->advertising & ADVERTISE_100FULL)
2843 ecmd->advertising |= ADVERTISED_100baseT_Full;
2844 ecmd->supported = (SUPPORTED_Autoneg |
2845 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2846 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2847 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2848 ecmd->phy_address = np->phy_addr_external;
2849 /*
2850 * We intentionally report the phy address of the external
2851 * phy, even if the internal phy is used. This is necessary
2852 * to work around a deficiency of the ethtool interface:
2853 * It's only possible to query the settings of the active
6aa20a22 2854 * port. Therefore
1da177e4
LT		 2855 * # ethtool -s ethX port mii
2856 * actually sends an ioctl to switch to port mii with the
2857 * settings that are used for the current active port.
2858 * If we would report a different phy address in this
2859 * command, then
2860 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2861 * would unintentionally change the phy address.
2862 *
2863 * Fortunately the phy address doesn't matter with the
2864 * internal phy...
2865 */
2866
2867 /* set information based on active port type */
2868 switch (ecmd->port) {
2869 default:
2870 case PORT_TP:
2871 ecmd->advertising |= ADVERTISED_TP;
2872 ecmd->transceiver = XCVR_INTERNAL;
2873 break;
2874 case PORT_MII:
2875 ecmd->advertising |= ADVERTISED_MII;
2876 ecmd->transceiver = XCVR_EXTERNAL;
2877 break;
2878 case PORT_FIBRE:
2879 ecmd->advertising |= ADVERTISED_FIBRE;
2880 ecmd->transceiver = XCVR_EXTERNAL;
2881 break;
2882 }
2883
2884 /* if autonegotiation is on, try to return the active speed/duplex */
2885 if (ecmd->autoneg == AUTONEG_ENABLE) {
2886 ecmd->advertising |= ADVERTISED_Autoneg;
2887 tmp = mii_nway_result(
2888 np->advertising & mdio_read(dev, MII_LPA));
2889 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2890 ecmd->speed = SPEED_100;
2891 else
2892 ecmd->speed = SPEED_10;
2893 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2894 ecmd->duplex = DUPLEX_FULL;
2895 else
2896 ecmd->duplex = DUPLEX_HALF;
2897 }
2898
2899 /* ignore maxtxpkt, maxrxpkt for now */
2900
2901 return 0;
2902}
2903
2904static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2905{
2906 struct netdev_private *np = netdev_priv(dev);
2907
2908 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2909 return -EINVAL;
2910 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2911 return -EINVAL;
2912 if (ecmd->autoneg == AUTONEG_ENABLE) {
2913 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2914 ADVERTISED_10baseT_Full |
2915 ADVERTISED_100baseT_Half |
2916 ADVERTISED_100baseT_Full)) == 0) {
2917 return -EINVAL;
2918 }
2919 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2920 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2921 return -EINVAL;
2922 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2923 return -EINVAL;
2924 } else {
2925 return -EINVAL;
2926 }
2927
68c90166
MB		 2928 /*
2929 * If we're ignoring the PHY then autoneg and the internal
2930 * transciever are really not going to work so don't let the
2931 * user select them.
2932 */
2933 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
2934 ecmd->port == PORT_TP))
2935 return -EINVAL;
2936
1da177e4
LT		 2937 /*
2938 * maxtxpkt, maxrxpkt: ignored for now.
2939 *
2940 * transceiver:
2941 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2942 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2943 * selects based on ecmd->port.
2944 *
2945 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2946 * phys that are connected to the mii bus. It's used to apply fibre
2947 * specific updates.
2948 */
2949
2950 /* WHEW! now lets bang some bits */
2951
2952 /* save the parms */
2953 dev->if_port = ecmd->port;
2954 np->autoneg = ecmd->autoneg;
2955 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2956 if (np->autoneg == AUTONEG_ENABLE) {
2957 /* advertise only what has been requested */
2958 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2959 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2960 np->advertising |= ADVERTISE_10HALF;
2961 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2962 np->advertising |= ADVERTISE_10FULL;
2963 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2964 np->advertising |= ADVERTISE_100HALF;
2965 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2966 np->advertising |= ADVERTISE_100FULL;
2967 } else {
2968 np->speed = ecmd->speed;
2969 np->duplex = ecmd->duplex;
2970 /* user overriding the initial full duplex parm? */
2971 if (np->duplex == DUPLEX_HALF)
2972 np->full_duplex = 0;
2973 }
2974
2975 /* get the right phy enabled */
2976 if (ecmd->port == PORT_TP)
2977 switch_port_internal(dev);
2978 else
2979 switch_port_external(dev);
2980
2981 /* set parms and see how this affected our link status */
2982 init_phy_fixup(dev);
2983 check_link(dev);
2984 return 0;
2985}
2986
2987static int netdev_get_regs(struct net_device *dev, u8 *buf)
2988{
2989 int i;
2990 int j;
2991 u32 rfcr;
2992 u32 *rbuf = (u32 *)buf;
2993 void __iomem * ioaddr = ns_ioaddr(dev);
2994
2995 /* read non-mii page 0 of registers */
2996 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2997 rbuf[i] = readl(ioaddr + i*4);
2998 }
2999
3000 /* read current mii registers */
3001 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
3002 rbuf[i] = mdio_read(dev, i & 0x1f);
3003
3004 /* read only the 'magic' registers from page 1 */
3005 writew(1, ioaddr + PGSEL);
3006 rbuf[i++] = readw(ioaddr + PMDCSR);
3007 rbuf[i++] = readw(ioaddr + TSTDAT);
3008 rbuf[i++] = readw(ioaddr + DSPCFG);
3009 rbuf[i++] = readw(ioaddr + SDCFG);
3010 writew(0, ioaddr + PGSEL);
3011
3012 /* read RFCR indexed registers */
3013 rfcr = readl(ioaddr + RxFilterAddr);
3014 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
3015 writel(j*2, ioaddr + RxFilterAddr);
3016 rbuf[i++] = readw(ioaddr + RxFilterData);
3017 }
3018 writel(rfcr, ioaddr + RxFilterAddr);
3019
3020 /* the interrupt status is clear-on-read - see if we missed any */
3021 if (rbuf[4] & rbuf[5]) {
3022 printk(KERN_WARNING
3023 "%s: shoot, we dropped an interrupt (%#08x)\n",
3024 dev->name, rbuf[4] & rbuf[5]);
3025 }
3026
3027 return 0;
3028}
3029
3030#define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
3031 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
3032 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
3033 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
3034 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
3035 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
3036 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
3037 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
3038
3039static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
3040{
3041 int i;
3042 u16 *ebuf = (u16 *)buf;
3043 void __iomem * ioaddr = ns_ioaddr(dev);
a8b4cf42 3044 struct netdev_private *np = netdev_priv(dev);
1da177e4
LT		 3045
3046 /* eeprom_read reads 16 bits, and indexes by 16 bits */
a8b4cf42 3047 for (i = 0; i < np->eeprom_size/2; i++) {
1da177e4
LT		 3048 ebuf[i] = eeprom_read(ioaddr, i);
3049 /* The EEPROM itself stores data bit-swapped, but eeprom_read
3050 * reads it back "sanely". So we swap it back here in order to
3051 * present it to userland as it is stored. */
3052 ebuf[i] = SWAP_BITS(ebuf[i]);
3053 }
3054 return 0;
3055}
3056
3057static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3058{
3059 struct mii_ioctl_data *data = if_mii(rq);
3060 struct netdev_private *np = netdev_priv(dev);
3061
3062 switch(cmd) {
3063 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
3064 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
3065 data->phy_id = np->phy_addr_external;
3066 /* Fall Through */
3067
3068 case SIOCGMIIREG: /* Read MII PHY register. */
3069 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
3070 /* The phy_id is not enough to uniquely identify
3071 * the intended target. Therefore the command is sent to
3072 * the given mii on the current port.
3073 */
3074 if (dev->if_port == PORT_TP) {
3075 if ((data->phy_id & 0x1f) == np->phy_addr_external)
3076 data->val_out = mdio_read(dev,
3077 data->reg_num & 0x1f);
3078 else
3079 data->val_out = 0;
3080 } else {
3081 move_int_phy(dev, data->phy_id & 0x1f);
3082 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
3083 data->reg_num & 0x1f);
3084 }
3085 return 0;
3086
3087 case SIOCSMIIREG: /* Write MII PHY register. */
3088 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
3089 if (!capable(CAP_NET_ADMIN))
3090 return -EPERM;
3091 if (dev->if_port == PORT_TP) {
3092 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3093 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3094 np->advertising = data->val_in;
3095 mdio_write(dev, data->reg_num & 0x1f,
3096 data->val_in);
3097 }
3098 } else {
3099 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3100 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3101 np->advertising = data->val_in;
3102 }
3103 move_int_phy(dev, data->phy_id & 0x1f);
3104 miiport_write(dev, data->phy_id & 0x1f,
3105 data->reg_num & 0x1f,
3106 data->val_in);
3107 }
3108 return 0;
3109 default:
3110 return -EOPNOTSUPP;
3111 }
3112}
3113
3114static void enable_wol_mode(struct net_device *dev, int enable_intr)
3115{
3116 void __iomem * ioaddr = ns_ioaddr(dev);
3117 struct netdev_private *np = netdev_priv(dev);
3118
3119 if (netif_msg_wol(np))
3120 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3121 dev->name);
3122
3123 /* For WOL we must restart the rx process in silent mode.
3124 * Write NULL to the RxRingPtr. Only possible if
3125 * rx process is stopped
3126 */
3127 writel(0, ioaddr + RxRingPtr);
3128
3129 /* read WoL status to clear */
3130 readl(ioaddr + WOLCmd);
3131
3132 /* PME on, clear status */
3133 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3134
3135 /* and restart the rx process */
3136 writel(RxOn, ioaddr + ChipCmd);
3137
3138 if (enable_intr) {
3139 /* enable the WOL interrupt.
3140 * Could be used to send a netlink message.
3141 */
3142 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
14fdd90e 3143 natsemi_irq_enable(dev);
1da177e4
LT		 3144 }
3145}
3146
3147static int netdev_close(struct net_device *dev)
3148{
3149 void __iomem * ioaddr = ns_ioaddr(dev);
3150 struct netdev_private *np = netdev_priv(dev);
3151
3152 if (netif_msg_ifdown(np))
3153 printk(KERN_DEBUG
3154 "%s: Shutting down ethercard, status was %#04x.\n",
3155 dev->name, (int)readl(ioaddr + ChipCmd));
3156 if (netif_msg_pktdata(np))
3157 printk(KERN_DEBUG
3158 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3159 dev->name, np->cur_tx, np->dirty_tx,
3160 np->cur_rx, np->dirty_rx);
3161
bea3348e
SH		 3162 napi_disable(&np->napi);
3163
1da177e4
LT		 3164 /*
3165 * FIXME: what if someone tries to close a device
3166 * that is suspended?
3167 * Should we reenable the nic to switch to
3168 * the final WOL settings?
3169 */
3170
3171 del_timer_sync(&np->timer);
3172 disable_irq(dev->irq);
3173 spin_lock_irq(&np->lock);
b27a16b7 3174 natsemi_irq_disable(dev);
1da177e4
LT		 3175 np->hands_off = 1;
3176 spin_unlock_irq(&np->lock);
3177 enable_irq(dev->irq);
3178
3179 free_irq(dev->irq, dev);
3180
3181 /* Interrupt disabled, interrupt handler released,
3182 * queue stopped, timer deleted, rtnl_lock held
3183 * All async codepaths that access the driver are disabled.
3184 */
3185 spin_lock_irq(&np->lock);
3186 np->hands_off = 0;
3187 readl(ioaddr + IntrMask);
3188 readw(ioaddr + MIntrStatus);
3189
3190 /* Freeze Stats */
3191 writel(StatsFreeze, ioaddr + StatsCtrl);
3192
3193 /* Stop the chip's Tx and Rx processes. */
3194 natsemi_stop_rxtx(dev);
3195
3196 __get_stats(dev);
3197 spin_unlock_irq(&np->lock);
3198
3199 /* clear the carrier last - an interrupt could reenable it otherwise */
3200 netif_carrier_off(dev);
3201 netif_stop_queue(dev);
3202
3203 dump_ring(dev);
3204 drain_ring(dev);
3205 free_ring(dev);
3206
3207 {
3208 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3209 if (wol) {
3210 /* restart the NIC in WOL mode.
3211 * The nic must be stopped for this.
3212 */
3213 enable_wol_mode(dev, 0);
3214 } else {
3215 /* Restore PME enable bit unmolested */
3216 writel(np->SavedClkRun, ioaddr + ClkRun);
3217 }
3218 }
3219 return 0;
3220}
3221
3222
3223static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3224{
3225 struct net_device *dev = pci_get_drvdata(pdev);
3226 void __iomem * ioaddr = ns_ioaddr(dev);
3227
1a147809 3228 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround);
1da177e4
LT		 3229 unregister_netdev (dev);
3230 pci_release_regions (pdev);
3231 iounmap(ioaddr);
3232 free_netdev (dev);
3233 pci_set_drvdata(pdev, NULL);
3234}
3235
3236#ifdef CONFIG_PM
3237
3238/*
3239 * The ns83815 chip doesn't have explicit RxStop bits.
3240 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3241 * of the nic, thus this function must be very careful:
3242 *
3243 * suspend/resume synchronization:
3244 * entry points:
3245 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3246 * start_tx, tx_timeout
3247 *
3248 * No function accesses the hardware without checking np->hands_off.
3249 * the check occurs under spin_lock_irq(&np->lock);
3250 * exceptions:
3251 * * netdev_ioctl: noncritical access.
3252 * * netdev_open: cannot happen due to the device_detach
3253 * * netdev_close: doesn't hurt.
3254 * * netdev_timer: timer stopped by natsemi_suspend.
3255 * * intr_handler: doesn't acquire the spinlock. suspend calls
3256 * disable_irq() to enforce synchronization.
b27a16b7
MB		 3257 * * natsemi_poll: checks before reenabling interrupts. suspend
3258 * sets hands_off, disables interrupts and then waits with
bea3348e 3259 * napi_disable().
1da177e4
LT		 3260 *
3261 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3262 */
3263
3264static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
3265{
3266 struct net_device *dev = pci_get_drvdata (pdev);
3267 struct netdev_private *np = netdev_priv(dev);
3268 void __iomem * ioaddr = ns_ioaddr(dev);
3269
3270 rtnl_lock();
3271 if (netif_running (dev)) {
3272 del_timer_sync(&np->timer);
3273
3274 disable_irq(dev->irq);
3275 spin_lock_irq(&np->lock);
3276
14fdd90e 3277 natsemi_irq_disable(dev);
1da177e4
LT		 3278 np->hands_off = 1;
3279 natsemi_stop_rxtx(dev);
3280 netif_stop_queue(dev);
3281
3282 spin_unlock_irq(&np->lock);
3283 enable_irq(dev->irq);
3284
bea3348e 3285 napi_disable(&np->napi);
b27a16b7 3286
1da177e4
LT		 3287 /* Update the error counts. */
3288 __get_stats(dev);
3289
3290 /* pci_power_off(pdev, -1); */
3291 drain_ring(dev);
3292 {
3293 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3294 /* Restore PME enable bit */
3295 if (wol) {
3296 /* restart the NIC in WOL mode.
3297 * The nic must be stopped for this.
3298 * FIXME: use the WOL interrupt
3299 */
3300 enable_wol_mode(dev, 0);
3301 } else {
3302 /* Restore PME enable bit unmolested */
3303 writel(np->SavedClkRun, ioaddr + ClkRun);
3304 }
3305 }
3306 }
3307 netif_device_detach(dev);
3308 rtnl_unlock();
3309 return 0;
3310}
3311
3312
3313static int natsemi_resume (struct pci_dev *pdev)
3314{
3315 struct net_device *dev = pci_get_drvdata (pdev);
3316 struct netdev_private *np = netdev_priv(dev);
a8a935da 3317 int ret = 0;
1da177e4
LT		 3318
3319 rtnl_lock();
3320 if (netif_device_present(dev))
3321 goto out;
3322 if (netif_running(dev)) {
3323 BUG_ON(!np->hands_off);
a8a935da
MB		 3324 ret = pci_enable_device(pdev);
3325 if (ret < 0) {
3326 dev_err(&pdev->dev,
3327 "pci_enable_device() failed: %d\n", ret);
3328 goto out;
3329 }
1da177e4
LT		 3330 /* pci_power_on(pdev); */
3331
bea3348e
SH		 3332 napi_enable(&np->napi);
3333
1da177e4
LT		 3334 natsemi_reset(dev);
3335 init_ring(dev);
3336 disable_irq(dev->irq);
3337 spin_lock_irq(&np->lock);
3338 np->hands_off = 0;
3339 init_registers(dev);
3340 netif_device_attach(dev);
3341 spin_unlock_irq(&np->lock);
3342 enable_irq(dev->irq);
3343
0e5d5442 3344 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ));
1da177e4
LT		 3345 }
3346 netif_device_attach(dev);
3347out:
3348 rtnl_unlock();
a8a935da 3349 return ret;
1da177e4
LT		 3350}
3351
3352#endif /* CONFIG_PM */
3353
3354static struct pci_driver natsemi_driver = {
3355 .name = DRV_NAME,
3356 .id_table = natsemi_pci_tbl,
3357 .probe = natsemi_probe1,
3358 .remove = __devexit_p(natsemi_remove1),
3359#ifdef CONFIG_PM
3360 .suspend = natsemi_suspend,
3361 .resume = natsemi_resume,
3362#endif
3363};
3364
3365static int __init natsemi_init_mod (void)
3366{
3367/* when a module, this is printed whether or not devices are found in probe */
3368#ifdef MODULE
3369 printk(version);
3370#endif
3371
29917620 3372 return pci_register_driver(&natsemi_driver);
1da177e4
LT		 3373}
3374
3375static void __exit natsemi_exit_mod (void)
3376{
3377 pci_unregister_driver (&natsemi_driver);
3378}
3379
3380module_init(natsemi_init_mod);
3381module_exit(natsemi_exit_mod);
3382
Ubuntu Jammy Linux kernel mirror