]>
Commit | Line | Data |
---|---|---|
3d396eb1 | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
3d396eb1 | 3 | * All rights reserved. |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
5d242f1c DP |
25 | * NetXen Inc, |
26 | * 18922 Forge Drive | |
27 | * Cupertino, CA 95014-0701 | |
28 | * | |
3d396eb1 AK |
29 | */ |
30 | ||
31 | #ifndef _NETXEN_NIC_H_ | |
32 | #define _NETXEN_NIC_H_ | |
33 | ||
3d396eb1 AK |
34 | #include <linux/module.h> |
35 | #include <linux/kernel.h> | |
36 | #include <linux/types.h> | |
37 | #include <linux/compiler.h> | |
38 | #include <linux/slab.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/ioport.h> | |
42 | #include <linux/pci.h> | |
43 | #include <linux/netdevice.h> | |
44 | #include <linux/etherdevice.h> | |
45 | #include <linux/ip.h> | |
46 | #include <linux/in.h> | |
47 | #include <linux/tcp.h> | |
48 | #include <linux/skbuff.h> | |
3d396eb1 AK |
49 | |
50 | #include <linux/ethtool.h> | |
51 | #include <linux/mii.h> | |
52 | #include <linux/interrupt.h> | |
53 | #include <linux/timer.h> | |
54 | ||
55 | #include <linux/mm.h> | |
56 | #include <linux/mman.h> | |
42555892 | 57 | #include <linux/vmalloc.h> |
3d396eb1 AK |
58 | |
59 | #include <asm/system.h> | |
60 | #include <asm/io.h> | |
61 | #include <asm/byteorder.h> | |
62 | #include <asm/uaccess.h> | |
63 | #include <asm/pgtable.h> | |
64 | ||
65 | #include "netxen_nic_hw.h" | |
66 | ||
58735567 DP |
67 | #define _NETXEN_NIC_LINUX_MAJOR 4 |
68 | #define _NETXEN_NIC_LINUX_MINOR 0 | |
11d89d63 DP |
69 | #define _NETXEN_NIC_LINUX_SUBVERSION 11 |
70 | #define NETXEN_NIC_LINUX_VERSIONID "4.0.11" | |
58735567 DP |
71 | |
72 | #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c)) | |
27d2ab54 | 73 | |
0d04761d MT |
74 | #define NETXEN_NUM_FLASH_SECTORS (64) |
75 | #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024) | |
76 | #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \ | |
77 | * NETXEN_FLASH_SECTOR_SIZE) | |
3d396eb1 | 78 | |
0c25cfe1 LCMT |
79 | #define PHAN_VENDOR_ID 0x4040 |
80 | ||
3d396eb1 AK |
81 | #define RCV_DESC_RINGSIZE \ |
82 | (sizeof(struct rcv_desc) * adapter->max_rx_desc_count) | |
83 | #define STATUS_DESC_RINGSIZE \ | |
84 | (sizeof(struct status_desc)* adapter->max_rx_desc_count) | |
ed25ffa1 AK |
85 | #define LRO_DESC_RINGSIZE \ |
86 | (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count) | |
3d396eb1 AK |
87 | #define TX_RINGSIZE \ |
88 | (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count) | |
89 | #define RCV_BUFFSIZE \ | |
48bfd1e0 | 90 | (sizeof(struct netxen_rx_buffer) * rds_ring->max_rx_desc_count) |
ba53e6b4 | 91 | #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) |
3d396eb1 | 92 | |
ed25ffa1 AK |
93 | #define NETXEN_NETDEV_STATUS 0x1 |
94 | #define NETXEN_RCV_PRODUCER_OFFSET 0 | |
95 | #define NETXEN_RCV_PEG_DB_ID 2 | |
96 | #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 | |
27d2ab54 | 97 | #define FLASH_SUCCESS 0 |
3d396eb1 AK |
98 | |
99 | #define ADDR_IN_WINDOW1(off) \ | |
100 | ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 | |
101 | ||
4790654c JG |
102 | /* |
103 | * normalize a 64MB crb address to 32MB PCI window | |
3d396eb1 AK |
104 | * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 |
105 | */ | |
80922fbc AK |
106 | #define NETXEN_CRB_NORMAL(reg) \ |
107 | ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) | |
cb8011ad | 108 | |
3d396eb1 | 109 | #define NETXEN_CRB_NORMALIZE(adapter, reg) \ |
cb8011ad AK |
110 | pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) |
111 | ||
ed25ffa1 AK |
112 | #define DB_NORMALIZE(adapter, off) \ |
113 | (adapter->ahw.db_base + (off)) | |
114 | ||
115 | #define NX_P2_C0 0x24 | |
116 | #define NX_P2_C1 0x25 | |
e4c93c81 DP |
117 | #define NX_P3_A0 0x30 |
118 | #define NX_P3_A2 0x30 | |
119 | #define NX_P3_B0 0x40 | |
120 | #define NX_P3_B1 0x41 | |
121 | ||
122 | #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1) | |
123 | #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0) | |
ed25ffa1 | 124 | |
cb8011ad | 125 | #define FIRST_PAGE_GROUP_START 0 |
ed25ffa1 | 126 | #define FIRST_PAGE_GROUP_END 0x100000 |
cb8011ad | 127 | |
78403a92 MT |
128 | #define SECOND_PAGE_GROUP_START 0x6000000 |
129 | #define SECOND_PAGE_GROUP_END 0x68BC000 | |
cb8011ad AK |
130 | |
131 | #define THIRD_PAGE_GROUP_START 0x70E4000 | |
132 | #define THIRD_PAGE_GROUP_END 0x8000000 | |
133 | ||
134 | #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START | |
135 | #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START | |
136 | #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START | |
3d396eb1 | 137 | |
e4c93c81 DP |
138 | #define P2_MAX_MTU (8000) |
139 | #define P3_MAX_MTU (9600) | |
140 | #define NX_ETHERMTU 1500 | |
141 | #define NX_MAX_ETHERHDR 32 /* This contains some padding */ | |
142 | ||
143 | #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU) | |
144 | #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU) | |
145 | #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU) | |
d9e651bc | 146 | #define NX_CT_DEFAULT_RX_BUF_LEN 2048 |
e4c93c81 | 147 | |
ed25ffa1 | 148 | #define MAX_RX_BUFFER_LENGTH 1760 |
bd56c6b1 | 149 | #define MAX_RX_JUMBO_BUFFER_LENGTH 8062 |
32ec8033 | 150 | #define MAX_RX_LRO_BUFFER_LENGTH (8062) |
ed25ffa1 | 151 | #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2) |
3d396eb1 | 152 | #define RX_JUMBO_DMA_MAP_LEN \ |
ed25ffa1 AK |
153 | (MAX_RX_JUMBO_BUFFER_LENGTH - 2) |
154 | #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2) | |
3d396eb1 AK |
155 | |
156 | /* | |
157 | * Maximum number of ring contexts | |
158 | */ | |
159 | #define MAX_RING_CTX 1 | |
160 | ||
161 | /* Opcodes to be used with the commands */ | |
e4c93c81 DP |
162 | #define TX_ETHER_PKT 0x01 |
163 | #define TX_TCP_PKT 0x02 | |
164 | #define TX_UDP_PKT 0x03 | |
165 | #define TX_IP_PKT 0x04 | |
166 | #define TX_TCP_LSO 0x05 | |
167 | #define TX_TCP_LSO6 0x06 | |
168 | #define TX_IPSEC 0x07 | |
169 | #define TX_IPSEC_CMD 0x0a | |
170 | #define TX_TCPV6_PKT 0x0b | |
171 | #define TX_UDPV6_PKT 0x0c | |
3d396eb1 AK |
172 | |
173 | /* The following opcodes are for internal consumption. */ | |
174 | #define NETXEN_CONTROL_OP 0x10 | |
175 | #define PEGNET_REQUEST 0x11 | |
176 | ||
177 | #define MAX_NUM_CARDS 4 | |
178 | ||
179 | #define MAX_BUFFERS_PER_CMD 32 | |
180 | ||
181 | /* | |
182 | * Following are the states of the Phantom. Phantom will set them and | |
183 | * Host will read to check if the fields are correct. | |
184 | */ | |
185 | #define PHAN_INITIALIZE_START 0xff00 | |
186 | #define PHAN_INITIALIZE_FAILED 0xffff | |
187 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
188 | ||
189 | /* Host writes the following to notify that it has done the init-handshake */ | |
190 | #define PHAN_INITIALIZE_ACK 0xf00f | |
191 | ||
ed25ffa1 | 192 | #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */ |
3d396eb1 AK |
193 | |
194 | /* descriptor types */ | |
195 | #define RCV_DESC_NORMAL 0x01 | |
196 | #define RCV_DESC_JUMBO 0x02 | |
ed25ffa1 | 197 | #define RCV_DESC_LRO 0x04 |
3d396eb1 AK |
198 | #define RCV_DESC_NORMAL_CTXID 0 |
199 | #define RCV_DESC_JUMBO_CTXID 1 | |
ed25ffa1 | 200 | #define RCV_DESC_LRO_CTXID 2 |
3d396eb1 AK |
201 | |
202 | #define RCV_DESC_TYPE(ID) \ | |
ed25ffa1 AK |
203 | ((ID == RCV_DESC_JUMBO_CTXID) \ |
204 | ? RCV_DESC_JUMBO \ | |
205 | : ((ID == RCV_DESC_LRO_CTXID) \ | |
206 | ? RCV_DESC_LRO : \ | |
207 | (RCV_DESC_NORMAL))) | |
3d396eb1 | 208 | |
ba53e6b4 | 209 | #define MAX_CMD_DESCRIPTORS 4096 |
bd56c6b1 | 210 | #define MAX_RCV_DESCRIPTORS 16384 |
32ec8033 DP |
211 | #define MAX_CMD_DESCRIPTORS_HOST 1024 |
212 | #define MAX_RCV_DESCRIPTORS_1G 2048 | |
213 | #define MAX_RCV_DESCRIPTORS_10G 4096 | |
e125646a | 214 | #define MAX_JUMBO_RCV_DESCRIPTORS 1024 |
32ec8033 | 215 | #define MAX_LRO_RCV_DESCRIPTORS 8 |
3d396eb1 AK |
216 | #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS |
217 | #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS | |
218 | #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS | |
219 | #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS | |
3d396eb1 | 220 | #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8) |
ed25ffa1 AK |
221 | #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \ |
222 | MAX_LRO_RCV_DESCRIPTORS) | |
3d396eb1 AK |
223 | #define MIN_TX_COUNT 4096 |
224 | #define MIN_RX_COUNT 4096 | |
ed25ffa1 AK |
225 | #define NETXEN_CTX_SIGNATURE 0xdee0 |
226 | #define NETXEN_RCV_PRODUCER(ringid) (ringid) | |
3d396eb1 AK |
227 | #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */ |
228 | ||
229 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
230 | #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 | |
231 | ||
232 | #define get_next_index(index, length) \ | |
233 | (((index) + 1) & ((length) - 1)) | |
234 | ||
235 | #define get_index_range(index,length,count) \ | |
236 | (((index) + (count)) & ((length) - 1)) | |
237 | ||
ed25ffa1 | 238 | #define MPORT_SINGLE_FUNCTION_MODE 0x1111 |
3176ff3e | 239 | #define MPORT_MULTI_FUNCTION_MODE 0x2222 |
ed25ffa1 | 240 | |
3176ff3e | 241 | #include "netxen_nic_phan_reg.h" |
ed25ffa1 AK |
242 | |
243 | /* | |
244 | * NetXen host-peg signal message structure | |
245 | * | |
246 | * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx | |
247 | * Bit 2 : priv_id => must be 1 | |
248 | * Bit 3-17 : count => for doorbell | |
249 | * Bit 18-27 : ctx_id => Context id | |
250 | * Bit 28-31 : opcode | |
251 | */ | |
252 | ||
253 | typedef u32 netxen_ctx_msg; | |
254 | ||
ed25ffa1 | 255 | #define netxen_set_msg_peg_id(config_word, val) \ |
a608ab9c | 256 | ((config_word) &= ~3, (config_word) |= val & 3) |
ed25ffa1 | 257 | #define netxen_set_msg_privid(config_word) \ |
a608ab9c | 258 | ((config_word) |= 1 << 2) |
ed25ffa1 | 259 | #define netxen_set_msg_count(config_word, val) \ |
a608ab9c | 260 | ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) |
ed25ffa1 | 261 | #define netxen_set_msg_ctxid(config_word, val) \ |
a608ab9c | 262 | ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) |
ed25ffa1 | 263 | #define netxen_set_msg_opcode(config_word, val) \ |
82581174 | 264 | ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) |
ed25ffa1 AK |
265 | |
266 | struct netxen_rcv_context { | |
a608ab9c AV |
267 | __le64 rcv_ring_addr; |
268 | __le32 rcv_ring_size; | |
269 | __le32 rsrvd; | |
ed25ffa1 AK |
270 | }; |
271 | ||
272 | struct netxen_ring_ctx { | |
273 | ||
274 | /* one command ring */ | |
a608ab9c AV |
275 | __le64 cmd_consumer_offset; |
276 | __le64 cmd_ring_addr; | |
277 | __le32 cmd_ring_size; | |
278 | __le32 rsrvd; | |
ed25ffa1 AK |
279 | |
280 | /* three receive rings */ | |
281 | struct netxen_rcv_context rcv_ctx[3]; | |
282 | ||
283 | /* one status ring */ | |
a608ab9c AV |
284 | __le64 sts_ring_addr; |
285 | __le32 sts_ring_size; | |
ed25ffa1 | 286 | |
a608ab9c | 287 | __le32 ctx_id; |
ed25ffa1 AK |
288 | } __attribute__ ((aligned(64))); |
289 | ||
3d396eb1 AK |
290 | /* |
291 | * Following data structures describe the descriptors that will be used. | |
292 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
293 | * we are doing LSO (above the 1500 size packet) only. | |
294 | */ | |
295 | ||
296 | /* | |
297 | * The size of reference handle been changed to 16 bits to pass the MSS fields | |
298 | * for the LSO packet | |
299 | */ | |
300 | ||
301 | #define FLAGS_CHECKSUM_ENABLED 0x01 | |
302 | #define FLAGS_LSO_ENABLED 0x02 | |
303 | #define FLAGS_IPSEC_SA_ADD 0x04 | |
304 | #define FLAGS_IPSEC_SA_DELETE 0x08 | |
305 | #define FLAGS_VLAN_TAGGED 0x10 | |
306 | ||
ed25ffa1 AK |
307 | #define netxen_set_cmd_desc_port(cmd_desc, var) \ |
308 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
6c80b18d | 309 | #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \ |
48bfd1e0 | 310 | ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) |
3d396eb1 | 311 | |
391587c3 DP |
312 | #define netxen_set_tx_port(_desc, _port) \ |
313 | (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0) | |
314 | ||
315 | #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \ | |
316 | (_desc)->flags_opcode = \ | |
317 | cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)) | |
318 | ||
319 | #define netxen_set_tx_frags_len(_desc, _frags, _len) \ | |
320 | (_desc)->num_of_buffers_total_length = \ | |
321 | cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)) | |
3d396eb1 AK |
322 | |
323 | struct cmd_desc_type0 { | |
ed25ffa1 AK |
324 | u8 tcp_hdr_offset; /* For LSO only */ |
325 | u8 ip_hdr_offset; /* For LSO only */ | |
326 | /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */ | |
a608ab9c | 327 | __le16 flags_opcode; |
ed25ffa1 AK |
328 | /* Bit pattern: 0-7 total number of segments, |
329 | 8-31 Total size of the packet */ | |
a608ab9c | 330 | __le32 num_of_buffers_total_length; |
3d396eb1 AK |
331 | union { |
332 | struct { | |
a608ab9c AV |
333 | __le32 addr_low_part2; |
334 | __le32 addr_high_part2; | |
3d396eb1 | 335 | }; |
a608ab9c | 336 | __le64 addr_buffer2; |
3d396eb1 AK |
337 | }; |
338 | ||
a608ab9c AV |
339 | __le16 reference_handle; /* changed to u16 to add mss */ |
340 | __le16 mss; /* passed by NDIS_PACKET for LSO */ | |
3d396eb1 AK |
341 | /* Bit pattern 0-3 port, 0-3 ctx id */ |
342 | u8 port_ctxid; | |
343 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
a608ab9c | 344 | __le16 conn_id; /* IPSec offoad only */ |
3d396eb1 AK |
345 | |
346 | union { | |
347 | struct { | |
a608ab9c AV |
348 | __le32 addr_low_part3; |
349 | __le32 addr_high_part3; | |
3d396eb1 | 350 | }; |
a608ab9c | 351 | __le64 addr_buffer3; |
3d396eb1 | 352 | }; |
3d396eb1 AK |
353 | union { |
354 | struct { | |
a608ab9c AV |
355 | __le32 addr_low_part1; |
356 | __le32 addr_high_part1; | |
3d396eb1 | 357 | }; |
a608ab9c | 358 | __le64 addr_buffer1; |
3d396eb1 AK |
359 | }; |
360 | ||
a608ab9c AV |
361 | __le16 buffer1_length; |
362 | __le16 buffer2_length; | |
363 | __le16 buffer3_length; | |
364 | __le16 buffer4_length; | |
3d396eb1 AK |
365 | |
366 | union { | |
367 | struct { | |
a608ab9c AV |
368 | __le32 addr_low_part4; |
369 | __le32 addr_high_part4; | |
3d396eb1 | 370 | }; |
a608ab9c | 371 | __le64 addr_buffer4; |
3d396eb1 AK |
372 | }; |
373 | ||
a608ab9c | 374 | __le64 unused; |
ed25ffa1 | 375 | |
3d396eb1 AK |
376 | } __attribute__ ((aligned(64))); |
377 | ||
378 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
379 | struct rcv_desc { | |
a608ab9c AV |
380 | __le16 reference_handle; |
381 | __le16 reserved; | |
382 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
383 | __le64 addr_buffer; | |
3d396eb1 AK |
384 | }; |
385 | ||
386 | /* opcode field in status_desc */ | |
d9e651bc DP |
387 | #define NETXEN_NIC_RXPKT_DESC 0x04 |
388 | #define NETXEN_OLD_RXPKT_DESC 0x3f | |
3d396eb1 AK |
389 | |
390 | /* for status field in status_desc */ | |
391 | #define STATUS_NEED_CKSUM (1) | |
392 | #define STATUS_CKSUM_OK (2) | |
393 | ||
394 | /* owner bits of status_desc */ | |
0ddc110c DP |
395 | #define STATUS_OWNER_HOST (0x1ULL << 56) |
396 | #define STATUS_OWNER_PHANTOM (0x2ULL << 56) | |
3d396eb1 AK |
397 | |
398 | /* Note: sizeof(status_desc) should always be a mutliple of 2 */ | |
ed25ffa1 AK |
399 | |
400 | #define netxen_get_sts_desc_lro_cnt(status_desc) \ | |
401 | ((status_desc)->lro & 0x7F) | |
402 | #define netxen_get_sts_desc_lro_last_frag(status_desc) \ | |
403 | (((status_desc)->lro & 0x80) >> 7) | |
404 | ||
5dc16268 DP |
405 | #define netxen_get_sts_port(sts_data) \ |
406 | ((sts_data) & 0x0F) | |
407 | #define netxen_get_sts_status(sts_data) \ | |
408 | (((sts_data) >> 4) & 0x0F) | |
409 | #define netxen_get_sts_type(sts_data) \ | |
410 | (((sts_data) >> 8) & 0x0F) | |
411 | #define netxen_get_sts_totallength(sts_data) \ | |
412 | (((sts_data) >> 12) & 0xFFFF) | |
413 | #define netxen_get_sts_refhandle(sts_data) \ | |
414 | (((sts_data) >> 28) & 0xFFFF) | |
415 | #define netxen_get_sts_prot(sts_data) \ | |
416 | (((sts_data) >> 44) & 0x0F) | |
d9e651bc DP |
417 | #define netxen_get_sts_pkt_offset(sts_data) \ |
418 | (((sts_data) >> 48) & 0x1F) | |
5dc16268 DP |
419 | #define netxen_get_sts_opcode(sts_data) \ |
420 | (((sts_data) >> 58) & 0x03F) | |
421 | ||
3d396eb1 | 422 | struct status_desc { |
ed25ffa1 | 423 | /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length |
d9e651bc | 424 | 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset |
ed25ffa1 AK |
425 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode |
426 | */ | |
a608ab9c | 427 | __le64 status_desc_data; |
d9e651bc DP |
428 | union { |
429 | struct { | |
430 | __le32 hash_value; | |
431 | u8 hash_type; | |
432 | u8 msg_type; | |
433 | u8 unused; | |
434 | union { | |
435 | /* Bit pattern: 0-6 lro_count indicates frag | |
436 | * sequence, 7 last_frag indicates last frag | |
437 | */ | |
438 | u8 lro; | |
439 | ||
440 | /* chained buffers */ | |
441 | u8 nr_frags; | |
442 | }; | |
443 | }; | |
444 | struct { | |
445 | __le16 frag_handles[4]; | |
446 | }; | |
447 | }; | |
6c80b18d | 448 | } __attribute__ ((aligned(16))); |
3d396eb1 AK |
449 | |
450 | enum { | |
451 | NETXEN_RCV_PEG_0 = 0, | |
452 | NETXEN_RCV_PEG_1 | |
453 | }; | |
454 | /* The version of the main data structure */ | |
455 | #define NETXEN_BDINFO_VERSION 1 | |
456 | ||
457 | /* Magic number to let user know flash is programmed */ | |
458 | #define NETXEN_BDINFO_MAGIC 0x12345678 | |
459 | ||
460 | /* Max number of Gig ports on a Phantom board */ | |
461 | #define NETXEN_MAX_PORTS 4 | |
462 | ||
463 | typedef enum { | |
464 | NETXEN_BRDTYPE_P1_BD = 0x0000, | |
465 | NETXEN_BRDTYPE_P1_SB = 0x0001, | |
466 | NETXEN_BRDTYPE_P1_SMAX = 0x0002, | |
467 | NETXEN_BRDTYPE_P1_SOCK = 0x0003, | |
468 | ||
469 | NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008, | |
470 | NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009, | |
471 | NETXEN_BRDTYPE_P2_SB35_4G = 0x000a, | |
472 | NETXEN_BRDTYPE_P2_SB31_10G = 0x000b, | |
473 | NETXEN_BRDTYPE_P2_SB31_2G = 0x000c, | |
474 | ||
475 | NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d, | |
476 | NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e, | |
e4c93c81 DP |
477 | NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f, |
478 | ||
479 | NETXEN_BRDTYPE_P3_REF_QG = 0x0021, | |
480 | NETXEN_BRDTYPE_P3_HMEZ = 0x0022, | |
481 | NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023, | |
482 | NETXEN_BRDTYPE_P3_4_GB = 0x0024, | |
483 | NETXEN_BRDTYPE_P3_IMEZ = 0x0025, | |
484 | NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026, | |
485 | NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027, | |
486 | NETXEN_BRDTYPE_P3_XG_LOM = 0x0028, | |
487 | NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029, | |
a70f9393 DP |
488 | NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a, |
489 | NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b, | |
e4c93c81 | 490 | NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031, |
c7860a2a DP |
491 | NETXEN_BRDTYPE_P3_10G_XFP = 0x0032, |
492 | NETXEN_BRDTYPE_P3_10G_TP = 0x0080 | |
e4c93c81 | 493 | |
3d396eb1 AK |
494 | } netxen_brdtype_t; |
495 | ||
496 | typedef enum { | |
497 | NETXEN_BRDMFG_INVENTEC = 1 | |
498 | } netxen_brdmfg; | |
499 | ||
500 | typedef enum { | |
501 | MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */ | |
502 | MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */ | |
503 | MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */ | |
504 | MEM_ORG_256Mbx4 = 0x3, | |
505 | MEM_ORG_256Mbx8 = 0x4, | |
506 | MEM_ORG_256Mbx16 = 0x5, | |
507 | MEM_ORG_512Mbx4 = 0x6, | |
508 | MEM_ORG_512Mbx8 = 0x7, | |
509 | MEM_ORG_512Mbx16 = 0x8, | |
510 | MEM_ORG_1Gbx4 = 0x9, | |
511 | MEM_ORG_1Gbx8 = 0xa, | |
512 | MEM_ORG_1Gbx16 = 0xb, | |
513 | MEM_ORG_2Gbx4 = 0xc, | |
514 | MEM_ORG_2Gbx8 = 0xd, | |
515 | MEM_ORG_2Gbx16 = 0xe, | |
516 | MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */ | |
517 | MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */ | |
518 | } netxen_mn_mem_org_t; | |
519 | ||
520 | typedef enum { | |
521 | MEM_ORG_512Kx36 = 0x0, | |
522 | MEM_ORG_1Mx36 = 0x1, | |
523 | MEM_ORG_2Mx36 = 0x2 | |
524 | } netxen_sn_mem_org_t; | |
525 | ||
526 | typedef enum { | |
527 | MEM_DEPTH_4MB = 0x1, | |
528 | MEM_DEPTH_8MB = 0x2, | |
529 | MEM_DEPTH_16MB = 0x3, | |
530 | MEM_DEPTH_32MB = 0x4, | |
531 | MEM_DEPTH_64MB = 0x5, | |
532 | MEM_DEPTH_128MB = 0x6, | |
533 | MEM_DEPTH_256MB = 0x7, | |
534 | MEM_DEPTH_512MB = 0x8, | |
535 | MEM_DEPTH_1GB = 0x9, | |
536 | MEM_DEPTH_2GB = 0xa, | |
537 | MEM_DEPTH_4GB = 0xb, | |
538 | MEM_DEPTH_8GB = 0xc, | |
539 | MEM_DEPTH_16GB = 0xd, | |
540 | MEM_DEPTH_32GB = 0xe | |
541 | } netxen_mem_depth_t; | |
542 | ||
543 | struct netxen_board_info { | |
544 | u32 header_version; | |
545 | ||
546 | u32 board_mfg; | |
547 | u32 board_type; | |
548 | u32 board_num; | |
549 | u32 chip_id; | |
550 | u32 chip_minor; | |
551 | u32 chip_major; | |
552 | u32 chip_pkg; | |
553 | u32 chip_lot; | |
554 | ||
555 | u32 port_mask; /* available niu ports */ | |
556 | u32 peg_mask; /* available pegs */ | |
557 | u32 icache_ok; /* can we run with icache? */ | |
558 | u32 dcache_ok; /* can we run with dcache? */ | |
559 | u32 casper_ok; | |
560 | ||
561 | u32 mac_addr_lo_0; | |
562 | u32 mac_addr_lo_1; | |
563 | u32 mac_addr_lo_2; | |
564 | u32 mac_addr_lo_3; | |
565 | ||
566 | /* MN-related config */ | |
567 | u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */ | |
568 | u32 mn_sync_shift_cclk; | |
569 | u32 mn_sync_shift_mclk; | |
570 | u32 mn_wb_en; | |
571 | u32 mn_crystal_freq; /* in MHz */ | |
572 | u32 mn_speed; /* in MHz */ | |
573 | u32 mn_org; | |
574 | u32 mn_depth; | |
575 | u32 mn_ranks_0; /* ranks per slot */ | |
576 | u32 mn_ranks_1; /* ranks per slot */ | |
577 | u32 mn_rd_latency_0; | |
578 | u32 mn_rd_latency_1; | |
579 | u32 mn_rd_latency_2; | |
580 | u32 mn_rd_latency_3; | |
581 | u32 mn_rd_latency_4; | |
582 | u32 mn_rd_latency_5; | |
583 | u32 mn_rd_latency_6; | |
584 | u32 mn_rd_latency_7; | |
585 | u32 mn_rd_latency_8; | |
586 | u32 mn_dll_val[18]; | |
587 | u32 mn_mode_reg; /* MIU DDR Mode Register */ | |
588 | u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */ | |
589 | u32 mn_timing_0; /* MIU Memory Control Timing Rgister */ | |
590 | u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */ | |
591 | u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */ | |
592 | ||
593 | /* SN-related config */ | |
594 | u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */ | |
595 | u32 sn_pt_mode; /* pass through mode */ | |
596 | u32 sn_ecc_en; | |
597 | u32 sn_wb_en; | |
598 | u32 sn_crystal_freq; | |
599 | u32 sn_speed; | |
600 | u32 sn_org; | |
601 | u32 sn_depth; | |
602 | u32 sn_dll_tap; | |
603 | u32 sn_rd_latency; | |
604 | ||
605 | u32 mac_addr_hi_0; | |
606 | u32 mac_addr_hi_1; | |
607 | u32 mac_addr_hi_2; | |
608 | u32 mac_addr_hi_3; | |
609 | ||
610 | u32 magic; /* indicates flash has been initialized */ | |
611 | ||
612 | u32 mn_rdimm; | |
613 | u32 mn_dll_override; | |
614 | ||
615 | }; | |
616 | ||
617 | #define FLASH_NUM_PORTS (4) | |
618 | ||
619 | struct netxen_flash_mac_addr { | |
620 | u32 flash_addr[32]; | |
621 | }; | |
622 | ||
623 | struct netxen_user_old_info { | |
624 | u8 flash_md5[16]; | |
625 | u8 crbinit_md5[16]; | |
626 | u8 brdcfg_md5[16]; | |
627 | /* bootloader */ | |
628 | u32 bootld_version; | |
629 | u32 bootld_size; | |
630 | u8 bootld_md5[16]; | |
631 | /* image */ | |
632 | u32 image_version; | |
633 | u32 image_size; | |
634 | u8 image_md5[16]; | |
635 | /* primary image status */ | |
636 | u32 primary_status; | |
637 | u32 secondary_present; | |
638 | ||
639 | /* MAC address , 4 ports */ | |
640 | struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS]; | |
641 | }; | |
642 | #define FLASH_NUM_MAC_PER_PORT 32 | |
643 | struct netxen_user_info { | |
644 | u8 flash_md5[16 * 64]; | |
645 | /* bootloader */ | |
646 | u32 bootld_version; | |
647 | u32 bootld_size; | |
648 | /* image */ | |
649 | u32 image_version; | |
650 | u32 image_size; | |
651 | /* primary image status */ | |
652 | u32 primary_status; | |
653 | u32 secondary_present; | |
654 | ||
655 | /* MAC address , 4 ports, 32 address per port */ | |
656 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
657 | u32 sub_sys_id; | |
658 | u8 serial_num[32]; | |
659 | ||
660 | /* Any user defined data */ | |
661 | }; | |
662 | ||
663 | /* | |
664 | * Flash Layout - new format. | |
665 | */ | |
666 | struct netxen_new_user_info { | |
667 | u8 flash_md5[16 * 64]; | |
668 | /* bootloader */ | |
669 | u32 bootld_version; | |
670 | u32 bootld_size; | |
671 | /* image */ | |
672 | u32 image_version; | |
673 | u32 image_size; | |
674 | /* primary image status */ | |
675 | u32 primary_status; | |
676 | u32 secondary_present; | |
677 | ||
678 | /* MAC address , 4 ports, 32 address per port */ | |
679 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
680 | u32 sub_sys_id; | |
681 | u8 serial_num[32]; | |
682 | ||
683 | /* Any user defined data */ | |
684 | }; | |
685 | ||
686 | #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6 | |
687 | #define SECONDARY_IMAGE_ABSENT 0xffffffff | |
688 | #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a | |
689 | #define PRIMARY_IMAGE_BAD 0xffffffff | |
690 | ||
691 | /* Flash memory map */ | |
692 | typedef enum { | |
0d04761d MT |
693 | NETXEN_CRBINIT_START = 0, /* Crbinit section */ |
694 | NETXEN_BRDCFG_START = 0x4000, /* board config */ | |
695 | NETXEN_INITCODE_START = 0x6000, /* pegtune code */ | |
696 | NETXEN_BOOTLD_START = 0x10000, /* bootld */ | |
697 | NETXEN_IMAGE_START = 0x43000, /* compressed image */ | |
698 | NETXEN_SECONDARY_START = 0x200000, /* backup images */ | |
699 | NETXEN_PXE_START = 0x3E0000, /* user defined region */ | |
700 | NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */ | |
701 | NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */ | |
3d396eb1 AK |
702 | } netxen_flash_map_t; |
703 | ||
ba599d4f DP |
704 | #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408) |
705 | #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c) | |
706 | #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c) | |
707 | #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128) | |
708 | #define NX_FW_MIN_SIZE (0x3fffff) | |
709 | #define NX_P2_MN_ROMIMAGE "nxromimg.bin" | |
710 | #define NX_P3_CT_ROMIMAGE "nx3fwct.bin" | |
711 | #define NX_P3_MN_ROMIMAGE "nx3fwmn.bin" | |
712 | ||
0d04761d MT |
713 | #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */ |
714 | ||
715 | #define NETXEN_FLASH_START (NETXEN_CRBINIT_START) | |
716 | #define NETXEN_INIT_SECTOR (0) | |
717 | #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START) | |
718 | #define NETXEN_FLASH_CRBINIT_SIZE (0x4000) | |
719 | #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info)) | |
720 | #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32)) | |
721 | #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START) | |
722 | #define NETXEN_NUM_PRIMARY_SECTORS (0x20) | |
723 | #define NETXEN_NUM_CONFIG_SECTORS (1) | |
ed25ffa1 AK |
724 | #define PFX "NetXen: " |
725 | extern char netxen_nic_driver_name[]; | |
3d396eb1 AK |
726 | |
727 | /* Note: Make sure to not call this before adapter->port is valid */ | |
728 | #if !defined(NETXEN_DEBUG) | |
729 | #define DPRINTK(klevel, fmt, args...) do { \ | |
730 | } while (0) | |
731 | #else | |
732 | #define DPRINTK(klevel, fmt, args...) do { \ | |
b39d66a8 | 733 | printk(KERN_##klevel PFX "%s: %s: " fmt, __func__,\ |
3176ff3e MT |
734 | (adapter != NULL && adapter->netdev != NULL) ? \ |
735 | adapter->netdev->name : NULL, \ | |
3d396eb1 AK |
736 | ## args); } while(0) |
737 | #endif | |
738 | ||
739 | /* Number of status descriptors to handle per interrupt */ | |
740 | #define MAX_STATUS_HANDLE (128) | |
741 | ||
742 | /* | |
743 | * netxen_skb_frag{} is to contain mapping info for each SG list. This | |
744 | * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. | |
745 | */ | |
746 | struct netxen_skb_frag { | |
747 | u64 dma; | |
391587c3 | 748 | ulong length; |
3d396eb1 AK |
749 | }; |
750 | ||
6c80b18d MT |
751 | #define _netxen_set_bits(config_word, start, bits, val) {\ |
752 | unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\ | |
753 | unsigned long long __tvalue = (val); \ | |
754 | (config_word) &= ~__tmask; \ | |
755 | (config_word) |= (((__tvalue) << (start)) & __tmask); \ | |
756 | } | |
4790654c | 757 | |
6c80b18d MT |
758 | #define _netxen_clear_bits(config_word, start, bits) {\ |
759 | unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \ | |
760 | (config_word) &= ~__tmask; \ | |
4790654c | 761 | } |
6c80b18d | 762 | |
3d396eb1 AK |
763 | /* Following defines are for the state of the buffers */ |
764 | #define NETXEN_BUFFER_FREE 0 | |
765 | #define NETXEN_BUFFER_BUSY 1 | |
766 | ||
767 | /* | |
768 | * There will be one netxen_buffer per skb packet. These will be | |
769 | * used to save the dma info for pci_unmap_page() | |
770 | */ | |
771 | struct netxen_cmd_buffer { | |
772 | struct sk_buff *skb; | |
773 | struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; | |
391587c3 | 774 | u32 frag_count; |
3d396eb1 AK |
775 | }; |
776 | ||
777 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
778 | struct netxen_rx_buffer { | |
d9e651bc | 779 | struct list_head list; |
3d396eb1 AK |
780 | struct sk_buff *skb; |
781 | u64 dma; | |
782 | u16 ref_handle; | |
783 | u16 state; | |
ed25ffa1 AK |
784 | u32 lro_expected_frags; |
785 | u32 lro_current_frags; | |
786 | u32 lro_length; | |
3d396eb1 AK |
787 | }; |
788 | ||
789 | /* Board types */ | |
790 | #define NETXEN_NIC_GBE 0x01 | |
791 | #define NETXEN_NIC_XGBE 0x02 | |
792 | ||
793 | /* | |
794 | * One hardware_context{} per adapter | |
795 | * contains interrupt info as well shared hardware info. | |
796 | */ | |
797 | struct netxen_hardware_context { | |
cb8011ad AK |
798 | void __iomem *pci_base0; |
799 | void __iomem *pci_base1; | |
800 | void __iomem *pci_base2; | |
6c80b18d MT |
801 | unsigned long first_page_group_end; |
802 | unsigned long first_page_group_start; | |
ed25ffa1 AK |
803 | void __iomem *db_base; |
804 | unsigned long db_len; | |
3ce06a32 DP |
805 | unsigned long pci_len0; |
806 | ||
2956640d | 807 | u8 cut_through; |
3ce06a32 DP |
808 | int qdr_sn_window; |
809 | int ddr_mn_window; | |
810 | unsigned long mn_win_crb; | |
811 | unsigned long ms_win_crb; | |
cb8011ad | 812 | |
3d396eb1 AK |
813 | u8 revision_id; |
814 | u16 board_type; | |
3d396eb1 | 815 | struct netxen_board_info boardcfg; |
a97342f9 | 816 | u32 linkup; |
3d396eb1 AK |
817 | /* Address of cmd ring in Phantom */ |
818 | struct cmd_desc_type0 *cmd_desc_head; | |
819 | dma_addr_t cmd_desc_phys_addr; | |
820 | struct netxen_adapter *adapter; | |
13ba9c77 | 821 | int pci_func; |
3d396eb1 AK |
822 | }; |
823 | ||
ed25ffa1 AK |
824 | #define RCV_RING_LRO RCV_DESC_LRO |
825 | ||
3d396eb1 AK |
826 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ |
827 | #define ETHERNET_FCS_SIZE 4 | |
828 | ||
829 | struct netxen_adapter_stats { | |
3176ff3e MT |
830 | u64 rcvdbadskb; |
831 | u64 xmitcalled; | |
832 | u64 xmitedframes; | |
833 | u64 xmitfinished; | |
834 | u64 badskblen; | |
835 | u64 nocmddescriptor; | |
836 | u64 polled; | |
d1847a72 | 837 | u64 rxdropped; |
3176ff3e | 838 | u64 txdropped; |
3176ff3e MT |
839 | u64 csummed; |
840 | u64 no_rcv; | |
841 | u64 rxbytes; | |
842 | u64 txbytes; | |
843 | u64 ints; | |
3d396eb1 AK |
844 | }; |
845 | ||
846 | /* | |
847 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
848 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
849 | */ | |
48bfd1e0 | 850 | struct nx_host_rds_ring { |
3d396eb1 AK |
851 | u32 flags; |
852 | u32 producer; | |
3d396eb1 | 853 | dma_addr_t phys_addr; |
7830b22c | 854 | u32 crb_rcv_producer; /* reg offset */ |
3d396eb1 AK |
855 | struct rcv_desc *desc_head; /* address of rx ring in Phantom */ |
856 | u32 max_rx_desc_count; | |
857 | u32 dma_size; | |
858 | u32 skb_size; | |
859 | struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */ | |
d9e651bc | 860 | struct list_head free_list; |
3d396eb1 AK |
861 | }; |
862 | ||
863 | /* | |
864 | * Receive context. There is one such structure per instance of the | |
865 | * receive processing. Any state information that is relevant to | |
866 | * the receive, and is must be in this structure. The global data may be | |
867 | * present elsewhere. | |
868 | */ | |
869 | struct netxen_recv_context { | |
48bfd1e0 DP |
870 | u32 state; |
871 | u16 context_id; | |
872 | u16 virt_port; | |
873 | ||
874 | struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS]; | |
3d396eb1 | 875 | u32 status_rx_consumer; |
7830b22c | 876 | u32 crb_sts_consumer; /* reg offset */ |
3d396eb1 AK |
877 | dma_addr_t rcv_status_desc_phys_addr; |
878 | struct status_desc *rcv_status_desc_head; | |
879 | }; | |
880 | ||
48bfd1e0 DP |
881 | /* New HW context creation */ |
882 | ||
883 | #define NX_OS_CRB_RETRY_COUNT 4000 | |
884 | #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \ | |
885 | (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) | |
886 | ||
887 | #define NX_CDRP_CLEAR 0x00000000 | |
888 | #define NX_CDRP_CMD_BIT 0x80000000 | |
889 | ||
890 | /* | |
891 | * All responses must have the NX_CDRP_CMD_BIT cleared | |
892 | * in the crb NX_CDRP_CRB_OFFSET. | |
893 | */ | |
894 | #define NX_CDRP_FORM_RSP(rsp) (rsp) | |
895 | #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0) | |
896 | ||
897 | #define NX_CDRP_RSP_OK 0x00000001 | |
898 | #define NX_CDRP_RSP_FAIL 0x00000002 | |
899 | #define NX_CDRP_RSP_TIMEOUT 0x00000003 | |
900 | ||
901 | /* | |
902 | * All commands must have the NX_CDRP_CMD_BIT set in | |
903 | * the crb NX_CDRP_CRB_OFFSET. | |
904 | */ | |
905 | #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd)) | |
906 | #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0) | |
907 | ||
908 | #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 | |
909 | #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 | |
910 | #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 | |
911 | #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 | |
912 | #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 | |
913 | #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 | |
914 | #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007 | |
915 | #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008 | |
916 | #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009 | |
917 | #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a | |
918 | #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e | |
919 | #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f | |
920 | #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010 | |
921 | #define NX_CDRP_CMD_SET_MTU 0x00000012 | |
922 | #define NX_CDRP_CMD_MAX 0x00000013 | |
923 | ||
924 | #define NX_RCODE_SUCCESS 0 | |
925 | #define NX_RCODE_NO_HOST_MEM 1 | |
926 | #define NX_RCODE_NO_HOST_RESOURCE 2 | |
927 | #define NX_RCODE_NO_CARD_CRB 3 | |
928 | #define NX_RCODE_NO_CARD_MEM 4 | |
929 | #define NX_RCODE_NO_CARD_RESOURCE 5 | |
930 | #define NX_RCODE_INVALID_ARGS 6 | |
931 | #define NX_RCODE_INVALID_ACTION 7 | |
932 | #define NX_RCODE_INVALID_STATE 8 | |
933 | #define NX_RCODE_NOT_SUPPORTED 9 | |
934 | #define NX_RCODE_NOT_PERMITTED 10 | |
935 | #define NX_RCODE_NOT_READY 11 | |
936 | #define NX_RCODE_DOES_NOT_EXIST 12 | |
937 | #define NX_RCODE_ALREADY_EXISTS 13 | |
938 | #define NX_RCODE_BAD_SIGNATURE 14 | |
939 | #define NX_RCODE_CMD_NOT_IMPL 15 | |
940 | #define NX_RCODE_CMD_INVALID 16 | |
941 | #define NX_RCODE_TIMEOUT 17 | |
942 | #define NX_RCODE_CMD_FAILED 18 | |
943 | #define NX_RCODE_MAX_EXCEEDED 19 | |
944 | #define NX_RCODE_MAX 20 | |
945 | ||
946 | #define NX_DESTROY_CTX_RESET 0 | |
947 | #define NX_DESTROY_CTX_D3_RESET 1 | |
948 | #define NX_DESTROY_CTX_MAX 2 | |
949 | ||
950 | /* | |
951 | * Capabilities | |
952 | */ | |
953 | #define NX_CAP_BIT(class, bit) (1 << bit) | |
954 | #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0) | |
955 | #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1) | |
956 | #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2) | |
957 | #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3) | |
958 | #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4) | |
959 | #define NX_CAP0_LRO NX_CAP_BIT(0, 5) | |
960 | #define NX_CAP0_LSO NX_CAP_BIT(0, 6) | |
961 | #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7) | |
962 | #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8) | |
963 | ||
964 | /* | |
965 | * Context state | |
966 | */ | |
967 | #define NX_HOST_CTX_STATE_FREED 0 | |
968 | #define NX_HOST_CTX_STATE_ALLOCATED 1 | |
969 | #define NX_HOST_CTX_STATE_ACTIVE 2 | |
970 | #define NX_HOST_CTX_STATE_DISABLED 3 | |
971 | #define NX_HOST_CTX_STATE_QUIESCED 4 | |
972 | #define NX_HOST_CTX_STATE_MAX 5 | |
973 | ||
974 | /* | |
975 | * Rx context | |
976 | */ | |
977 | ||
978 | typedef struct { | |
2edbb454 DP |
979 | __le64 host_phys_addr; /* Ring base addr */ |
980 | __le32 ring_size; /* Ring entries */ | |
981 | __le16 msi_index; | |
982 | __le16 rsvd; /* Padding */ | |
48bfd1e0 DP |
983 | } nx_hostrq_sds_ring_t; |
984 | ||
985 | typedef struct { | |
2edbb454 DP |
986 | __le64 host_phys_addr; /* Ring base addr */ |
987 | __le64 buff_size; /* Packet buffer size */ | |
988 | __le32 ring_size; /* Ring entries */ | |
989 | __le32 ring_kind; /* Class of ring */ | |
48bfd1e0 DP |
990 | } nx_hostrq_rds_ring_t; |
991 | ||
992 | typedef struct { | |
2edbb454 DP |
993 | __le64 host_rsp_dma_addr; /* Response dma'd here */ |
994 | __le32 capabilities[4]; /* Flag bit vector */ | |
995 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
996 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
48bfd1e0 | 997 | /* These ring offsets are relative to data[0] below */ |
2edbb454 DP |
998 | __le32 rds_ring_offset; /* Offset to RDS config */ |
999 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
1000 | __le16 num_rds_rings; /* Count of RDS rings */ | |
1001 | __le16 num_sds_rings; /* Count of SDS rings */ | |
1002 | __le16 rsvd1; /* Padding */ | |
1003 | __le16 rsvd2; /* Padding */ | |
48bfd1e0 DP |
1004 | u8 reserved[128]; /* reserve space for future expansion*/ |
1005 | /* MUST BE 64-bit aligned. | |
1006 | The following is packed: | |
1007 | - N hostrq_rds_rings | |
1008 | - N hostrq_sds_rings */ | |
1009 | char data[0]; | |
1010 | } nx_hostrq_rx_ctx_t; | |
1011 | ||
1012 | typedef struct { | |
2edbb454 DP |
1013 | __le32 host_producer_crb; /* Crb to use */ |
1014 | __le32 rsvd1; /* Padding */ | |
48bfd1e0 DP |
1015 | } nx_cardrsp_rds_ring_t; |
1016 | ||
1017 | typedef struct { | |
2edbb454 DP |
1018 | __le32 host_consumer_crb; /* Crb to use */ |
1019 | __le32 interrupt_crb; /* Crb to use */ | |
48bfd1e0 DP |
1020 | } nx_cardrsp_sds_ring_t; |
1021 | ||
1022 | typedef struct { | |
1023 | /* These ring offsets are relative to data[0] below */ | |
2edbb454 DP |
1024 | __le32 rds_ring_offset; /* Offset to RDS config */ |
1025 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
1026 | __le32 host_ctx_state; /* Starting State */ | |
1027 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
1028 | __le16 num_rds_rings; /* Count of RDS rings */ | |
1029 | __le16 num_sds_rings; /* Count of SDS rings */ | |
1030 | __le16 context_id; /* Handle for context */ | |
48bfd1e0 DP |
1031 | u8 phys_port; /* Physical id of port */ |
1032 | u8 virt_port; /* Virtual/Logical id of port */ | |
1033 | u8 reserved[128]; /* save space for future expansion */ | |
1034 | /* MUST BE 64-bit aligned. | |
1035 | The following is packed: | |
1036 | - N cardrsp_rds_rings | |
1037 | - N cardrs_sds_rings */ | |
1038 | char data[0]; | |
1039 | } nx_cardrsp_rx_ctx_t; | |
1040 | ||
1041 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
1042 | (sizeof(HOSTRQ_RX) + \ | |
1043 | (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \ | |
1044 | (sds_rings)*(sizeof(nx_hostrq_sds_ring_t))) | |
1045 | ||
1046 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
1047 | (sizeof(CARDRSP_RX) + \ | |
1048 | (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \ | |
1049 | (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t))) | |
1050 | ||
1051 | /* | |
1052 | * Tx context | |
1053 | */ | |
1054 | ||
1055 | typedef struct { | |
2edbb454 DP |
1056 | __le64 host_phys_addr; /* Ring base addr */ |
1057 | __le32 ring_size; /* Ring entries */ | |
1058 | __le32 rsvd; /* Padding */ | |
48bfd1e0 DP |
1059 | } nx_hostrq_cds_ring_t; |
1060 | ||
1061 | typedef struct { | |
2edbb454 DP |
1062 | __le64 host_rsp_dma_addr; /* Response dma'd here */ |
1063 | __le64 cmd_cons_dma_addr; /* */ | |
1064 | __le64 dummy_dma_addr; /* */ | |
1065 | __le32 capabilities[4]; /* Flag bit vector */ | |
1066 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
1067 | __le32 rsvd1; /* Padding */ | |
1068 | __le16 rsvd2; /* Padding */ | |
1069 | __le16 interrupt_ctl; | |
1070 | __le16 msi_index; | |
1071 | __le16 rsvd3; /* Padding */ | |
48bfd1e0 DP |
1072 | nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */ |
1073 | u8 reserved[128]; /* future expansion */ | |
1074 | } nx_hostrq_tx_ctx_t; | |
1075 | ||
1076 | typedef struct { | |
2edbb454 DP |
1077 | __le32 host_producer_crb; /* Crb to use */ |
1078 | __le32 interrupt_crb; /* Crb to use */ | |
48bfd1e0 DP |
1079 | } nx_cardrsp_cds_ring_t; |
1080 | ||
1081 | typedef struct { | |
2edbb454 DP |
1082 | __le32 host_ctx_state; /* Starting state */ |
1083 | __le16 context_id; /* Handle for context */ | |
48bfd1e0 DP |
1084 | u8 phys_port; /* Physical id of port */ |
1085 | u8 virt_port; /* Virtual/Logical id of port */ | |
1086 | nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */ | |
1087 | u8 reserved[128]; /* future expansion */ | |
1088 | } nx_cardrsp_tx_ctx_t; | |
1089 | ||
1090 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
1091 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
1092 | ||
1093 | /* CRB */ | |
1094 | ||
1095 | #define NX_HOST_RDS_CRB_MODE_UNIQUE 0 | |
1096 | #define NX_HOST_RDS_CRB_MODE_SHARED 1 | |
1097 | #define NX_HOST_RDS_CRB_MODE_CUSTOM 2 | |
1098 | #define NX_HOST_RDS_CRB_MODE_MAX 3 | |
1099 | ||
1100 | #define NX_HOST_INT_CRB_MODE_UNIQUE 0 | |
1101 | #define NX_HOST_INT_CRB_MODE_SHARED 1 | |
1102 | #define NX_HOST_INT_CRB_MODE_NORX 2 | |
1103 | #define NX_HOST_INT_CRB_MODE_NOTX 3 | |
1104 | #define NX_HOST_INT_CRB_MODE_NORXTX 4 | |
1105 | ||
1106 | ||
1107 | /* MAC */ | |
1108 | ||
1109 | #define MC_COUNT_P2 16 | |
1110 | #define MC_COUNT_P3 38 | |
1111 | ||
1112 | #define NETXEN_MAC_NOOP 0 | |
1113 | #define NETXEN_MAC_ADD 1 | |
1114 | #define NETXEN_MAC_DEL 2 | |
1115 | ||
1116 | typedef struct nx_mac_list_s { | |
1117 | struct nx_mac_list_s *next; | |
1118 | uint8_t mac_addr[MAX_ADDR_LEN]; | |
1119 | } nx_mac_list_t; | |
1120 | ||
cd1f8160 DP |
1121 | /* |
1122 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
1123 | * adjusted based on configured MTU. | |
1124 | */ | |
1125 | #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3 | |
1126 | #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256 | |
1127 | #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64 | |
1128 | #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4 | |
1129 | ||
1130 | #define NETXEN_NIC_INTR_DEFAULT 0x04 | |
1131 | ||
1132 | typedef union { | |
1133 | struct { | |
1134 | uint16_t rx_packets; | |
1135 | uint16_t rx_time_us; | |
1136 | uint16_t tx_packets; | |
1137 | uint16_t tx_time_us; | |
1138 | } data; | |
1139 | uint64_t word; | |
1140 | } nx_nic_intr_coalesce_data_t; | |
1141 | ||
1142 | typedef struct { | |
1143 | uint16_t stats_time_us; | |
1144 | uint16_t rate_sample_time; | |
1145 | uint16_t flags; | |
1146 | uint16_t rsvd_1; | |
1147 | uint32_t low_threshold; | |
1148 | uint32_t high_threshold; | |
1149 | nx_nic_intr_coalesce_data_t normal; | |
1150 | nx_nic_intr_coalesce_data_t low; | |
1151 | nx_nic_intr_coalesce_data_t high; | |
1152 | nx_nic_intr_coalesce_data_t irq; | |
1153 | } nx_nic_intr_coalesce_t; | |
1154 | ||
9ad27643 DP |
1155 | #define NX_HOST_REQUEST 0x13 |
1156 | #define NX_NIC_REQUEST 0x14 | |
1157 | ||
1158 | #define NX_MAC_EVENT 0x1 | |
1159 | ||
1160 | enum { | |
1161 | NX_NIC_H2C_OPCODE_START = 0, | |
1162 | NX_NIC_H2C_OPCODE_CONFIG_RSS, | |
1163 | NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL, | |
1164 | NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE, | |
1165 | NX_NIC_H2C_OPCODE_CONFIG_LED, | |
1166 | NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS, | |
1167 | NX_NIC_H2C_OPCODE_CONFIG_L2_MAC, | |
1168 | NX_NIC_H2C_OPCODE_LRO_REQUEST, | |
1169 | NX_NIC_H2C_OPCODE_GET_SNMP_STATS, | |
1170 | NX_NIC_H2C_OPCODE_PROXY_START_REQUEST, | |
1171 | NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST, | |
1172 | NX_NIC_H2C_OPCODE_PROXY_SET_MTU, | |
1173 | NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE, | |
1174 | NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST, | |
1175 | NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST, | |
1176 | NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST, | |
1177 | NX_NIC_H2C_OPCODE_GET_NET_STATS, | |
1178 | NX_NIC_H2C_OPCODE_LAST | |
1179 | }; | |
1180 | ||
1181 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
1182 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
1183 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
1184 | ||
48bfd1e0 | 1185 | typedef struct { |
2edbb454 DP |
1186 | __le64 qhdr; |
1187 | __le64 req_hdr; | |
1188 | __le64 words[6]; | |
c9fc891f | 1189 | } nx_nic_req_t; |
48bfd1e0 DP |
1190 | |
1191 | typedef struct { | |
1192 | u8 op; | |
1193 | u8 tag; | |
1194 | u8 mac_addr[6]; | |
1195 | } nx_mac_req_t; | |
1196 | ||
c9fc891f | 1197 | #define MAX_PENDING_DESC_BLOCK_SIZE 64 |
48bfd1e0 | 1198 | |
2956640d DP |
1199 | #define NETXEN_NIC_MSI_ENABLED 0x02 |
1200 | #define NETXEN_NIC_MSIX_ENABLED 0x04 | |
1201 | #define NETXEN_IS_MSI_FAMILY(adapter) \ | |
1202 | ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED)) | |
1203 | ||
b3df68f8 | 1204 | #define MSIX_ENTRIES_PER_ADAPTER 1 |
2956640d DP |
1205 | #define NETXEN_MSIX_TBL_SPACE 8192 |
1206 | #define NETXEN_PCI_REG_MSIX_TBL 0x44 | |
1207 | ||
1208 | #define NETXEN_DB_MAPSIZE_BYTES 0x1000 | |
ed25ffa1 | 1209 | |
cd1f8160 DP |
1210 | #define NETXEN_NETDEV_WEIGHT 120 |
1211 | #define NETXEN_ADAPTER_UP_MAGIC 777 | |
1212 | #define NETXEN_NIC_PEG_TUNE 0 | |
1213 | ||
ed25ffa1 AK |
1214 | struct netxen_dummy_dma { |
1215 | void *addr; | |
1216 | dma_addr_t phys_addr; | |
1217 | }; | |
3d396eb1 | 1218 | |
3d396eb1 AK |
1219 | struct netxen_adapter { |
1220 | struct netxen_hardware_context ahw; | |
4790654c | 1221 | |
3176ff3e MT |
1222 | struct net_device *netdev; |
1223 | struct pci_dev *pdev; | |
2956640d | 1224 | int pci_using_dac; |
bea3348e | 1225 | struct napi_struct napi; |
6c80b18d | 1226 | struct net_device_stats net_stats; |
3176ff3e MT |
1227 | int mtu; |
1228 | int portnum; | |
3276fbad | 1229 | u8 physical_port; |
48bfd1e0 | 1230 | u16 tx_context_id; |
3176ff3e | 1231 | |
623621b0 DP |
1232 | uint8_t mc_enabled; |
1233 | uint8_t max_mc_count; | |
c9fc891f | 1234 | nx_mac_list_t *mac_list; |
623621b0 | 1235 | |
2956640d | 1236 | struct netxen_legacy_intr_set legacy_intr; |
48bfd1e0 | 1237 | u32 crb_intr_mask; |
2956640d | 1238 | |
3d396eb1 | 1239 | struct work_struct watchdog_task; |
3d396eb1 | 1240 | struct timer_list watchdog_timer; |
3176ff3e | 1241 | struct work_struct tx_timeout_task; |
3d396eb1 AK |
1242 | |
1243 | u32 curr_window; | |
3ce06a32 DP |
1244 | u32 crb_win; |
1245 | rwlock_t adapter_lock; | |
2956640d | 1246 | |
3d396eb1 | 1247 | u32 cmd_producer; |
f305f789 | 1248 | __le32 *cmd_consumer; |
3d396eb1 | 1249 | u32 last_cmd_consumer; |
7830b22c DP |
1250 | u32 crb_addr_cmd_producer; |
1251 | u32 crb_addr_cmd_consumer; | |
ba53e6b4 | 1252 | |
3d396eb1 AK |
1253 | u32 max_tx_desc_count; |
1254 | u32 max_rx_desc_count; | |
1255 | u32 max_jumbo_rx_desc_count; | |
ed25ffa1 | 1256 | u32 max_lro_rx_desc_count; |
3d396eb1 | 1257 | |
48bfd1e0 DP |
1258 | int max_rds_rings; |
1259 | ||
3d396eb1 AK |
1260 | u32 flags; |
1261 | u32 irq; | |
1262 | int driver_mismatch; | |
cb8011ad | 1263 | u32 temp; |
3d396eb1 | 1264 | |
2956640d DP |
1265 | u32 fw_major; |
1266 | ||
1267 | u8 msix_supported; | |
1268 | u8 max_possible_rss_rings; | |
1269 | struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; | |
1270 | ||
3d396eb1 | 1271 | struct netxen_adapter_stats stats; |
4790654c | 1272 | |
3176ff3e MT |
1273 | u16 link_speed; |
1274 | u16 link_duplex; | |
1275 | u16 state; | |
1276 | u16 link_autoneg; | |
200eef20 | 1277 | int rx_csum; |
3176ff3e | 1278 | int status; |
3d396eb1 AK |
1279 | |
1280 | struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */ | |
1281 | ||
1282 | /* | |
1283 | * Receive instances. These can be either one per port, | |
1284 | * or one per peg, etc. | |
1285 | */ | |
1286 | struct netxen_recv_context recv_ctx[MAX_RCV_CTX]; | |
1287 | ||
1288 | int is_up; | |
ed25ffa1 | 1289 | struct netxen_dummy_dma dummy_dma; |
cd1f8160 | 1290 | nx_nic_intr_coalesce_t coal; |
ed25ffa1 AK |
1291 | |
1292 | /* Context interface shared between card and host */ | |
1293 | struct netxen_ring_ctx *ctx_desc; | |
ed25ffa1 | 1294 | dma_addr_t ctx_desc_phys_addr; |
2d1a3bbd | 1295 | int intr_scheme; |
443be796 | 1296 | int msi_mode; |
13ba9c77 MT |
1297 | int (*enable_phy_interrupts) (struct netxen_adapter *); |
1298 | int (*disable_phy_interrupts) (struct netxen_adapter *); | |
3176ff3e MT |
1299 | int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t); |
1300 | int (*set_mtu) (struct netxen_adapter *, int); | |
9ad27643 | 1301 | int (*set_promisc) (struct netxen_adapter *, u32); |
13ba9c77 MT |
1302 | int (*phy_read) (struct netxen_adapter *, long reg, u32 *); |
1303 | int (*phy_write) (struct netxen_adapter *, long reg, u32 val); | |
80922fbc | 1304 | int (*init_port) (struct netxen_adapter *, int); |
3176ff3e | 1305 | int (*stop_port) (struct netxen_adapter *); |
3ce06a32 DP |
1306 | |
1307 | int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int); | |
1308 | int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int); | |
1309 | int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int); | |
1310 | int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int); | |
1311 | int (*pci_write_immediate)(struct netxen_adapter *, u64, u32); | |
1312 | u32 (*pci_read_immediate)(struct netxen_adapter *, u64); | |
1313 | void (*pci_write_normalize)(struct netxen_adapter *, u64, u32); | |
1314 | u32 (*pci_read_normalize)(struct netxen_adapter *, u64); | |
1315 | unsigned long (*pci_set_window)(struct netxen_adapter *, | |
1316 | unsigned long long); | |
3d396eb1 AK |
1317 | }; /* netxen_adapter structure */ |
1318 | ||
96acb6eb DP |
1319 | /* |
1320 | * NetXen dma watchdog control structure | |
1321 | * | |
1322 | * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive | |
1323 | * Bit 1 : disable_request => 1 req disable dma watchdog | |
1324 | * Bit 2 : enable_request => 1 req enable dma watchdog | |
1325 | * Bit 3-31 : unused | |
1326 | */ | |
1327 | ||
1328 | #define netxen_set_dma_watchdog_disable_req(config_word) \ | |
1329 | _netxen_set_bits(config_word, 1, 1, 1) | |
1330 | #define netxen_set_dma_watchdog_enable_req(config_word) \ | |
1331 | _netxen_set_bits(config_word, 2, 1, 1) | |
1332 | #define netxen_get_dma_watchdog_enabled(config_word) \ | |
1333 | ((config_word) & 0x1) | |
1334 | #define netxen_get_dma_watchdog_disabled(config_word) \ | |
1335 | (((config_word) >> 1) & 0x1) | |
1336 | ||
3d396eb1 AK |
1337 | /* Max number of xmit producer threads that can run simultaneously */ |
1338 | #define MAX_XMIT_PRODUCERS 16 | |
1339 | ||
cb8011ad AK |
1340 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
1341 | ((adapter)->ahw.pci_base0 + (off)) | |
1342 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | |
1343 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) | |
1344 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ | |
1345 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) | |
1346 | ||
1347 | static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter, | |
1348 | unsigned long off) | |
1349 | { | |
1350 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
1351 | return (adapter->ahw.pci_base0 + off); | |
1352 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
1353 | (off >= SECOND_PAGE_GROUP_START)) { | |
1354 | return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START); | |
1355 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
1356 | (off >= THIRD_PAGE_GROUP_START)) { | |
1357 | return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START); | |
1358 | } | |
1359 | return NULL; | |
1360 | } | |
1361 | ||
1362 | static inline void __iomem *pci_base(struct netxen_adapter *adapter, | |
1363 | unsigned long off) | |
1364 | { | |
1365 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
1366 | return adapter->ahw.pci_base0; | |
1367 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
1368 | (off >= SECOND_PAGE_GROUP_START)) { | |
1369 | return adapter->ahw.pci_base1; | |
1370 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
1371 | (off >= THIRD_PAGE_GROUP_START)) { | |
1372 | return adapter->ahw.pci_base2; | |
1373 | } | |
1374 | return NULL; | |
1375 | } | |
1376 | ||
13ba9c77 MT |
1377 | int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter); |
1378 | int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter); | |
1379 | int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter); | |
1380 | int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter); | |
13ba9c77 | 1381 | int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg, |
a608ab9c | 1382 | __u32 * readval); |
13ba9c77 | 1383 | int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, |
a608ab9c | 1384 | long reg, __u32 val); |
3d396eb1 AK |
1385 | |
1386 | /* Functions available from netxen_nic_hw.c */ | |
3176ff3e MT |
1387 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); |
1388 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); | |
3d396eb1 AK |
1389 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); |
1390 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); | |
1391 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); | |
3ce06a32 DP |
1392 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value); |
1393 | void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value); | |
1394 | void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value); | |
3d396eb1 AK |
1395 | |
1396 | int netxen_nic_get_board_info(struct netxen_adapter *adapter); | |
3ce06a32 DP |
1397 | |
1398 | int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, | |
1399 | ulong off, void *data, int len); | |
1400 | int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, | |
1401 | ulong off, void *data, int len); | |
1402 | int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, | |
1403 | u64 off, void *data, int size); | |
1404 | int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, | |
1405 | u64 off, void *data, int size); | |
1406 | int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter, | |
1407 | u64 off, u32 data); | |
1408 | u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off); | |
1409 | void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter, | |
1410 | u64 off, u32 data); | |
1411 | u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off); | |
1412 | unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, | |
1413 | unsigned long long addr); | |
1414 | void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, | |
1415 | u32 wndw); | |
1416 | ||
1417 | int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, | |
1418 | ulong off, void *data, int len); | |
1419 | int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, | |
1420 | ulong off, void *data, int len); | |
1421 | int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, | |
1422 | u64 off, void *data, int size); | |
1423 | int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, | |
1424 | u64 off, void *data, int size); | |
3d396eb1 AK |
1425 | void netxen_crb_writelit_adapter(struct netxen_adapter *adapter, |
1426 | unsigned long off, int data); | |
3ce06a32 DP |
1427 | int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, |
1428 | u64 off, u32 data); | |
1429 | u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off); | |
1430 | void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter, | |
1431 | u64 off, u32 data); | |
1432 | u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off); | |
1433 | unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |
1434 | unsigned long long addr); | |
3d396eb1 AK |
1435 | |
1436 | /* Functions from netxen_nic_init.c */ | |
ed25ffa1 AK |
1437 | void netxen_free_adapter_offload(struct netxen_adapter *adapter); |
1438 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter); | |
96acb6eb | 1439 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); |
2956640d | 1440 | int netxen_receive_peg_ready(struct netxen_adapter *adapter); |
96acb6eb | 1441 | int netxen_load_firmware(struct netxen_adapter *adapter); |
3d396eb1 | 1442 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); |
2956640d | 1443 | |
3d396eb1 | 1444 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); |
4790654c | 1445 | int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 | 1446 | u8 *bytes, size_t size); |
4790654c | 1447 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
1448 | u8 *bytes, size_t size); |
1449 | int netxen_flash_unlock(struct netxen_adapter *adapter); | |
1450 | int netxen_backup_crbinit(struct netxen_adapter *adapter); | |
1451 | int netxen_flash_erase_secondary(struct netxen_adapter *adapter); | |
1452 | int netxen_flash_erase_primary(struct netxen_adapter *adapter); | |
e45d9ab4 | 1453 | void netxen_halt_pegs(struct netxen_adapter *adapter); |
27d2ab54 | 1454 | |
cb8011ad | 1455 | int netxen_rom_se(struct netxen_adapter *adapter, int addr); |
3d396eb1 | 1456 | |
2956640d DP |
1457 | int netxen_alloc_sw_resources(struct netxen_adapter *adapter); |
1458 | void netxen_free_sw_resources(struct netxen_adapter *adapter); | |
1459 | ||
1460 | int netxen_alloc_hw_resources(struct netxen_adapter *adapter); | |
1461 | void netxen_free_hw_resources(struct netxen_adapter *adapter); | |
1462 | ||
1463 | void netxen_release_rx_buffers(struct netxen_adapter *adapter); | |
1464 | void netxen_release_tx_buffers(struct netxen_adapter *adapter); | |
1465 | ||
3d396eb1 AK |
1466 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); |
1467 | int netxen_init_firmware(struct netxen_adapter *adapter); | |
3d396eb1 | 1468 | void netxen_nic_clear_stats(struct netxen_adapter *adapter); |
6d5aefb8 | 1469 | void netxen_watchdog_task(struct work_struct *work); |
3d396eb1 AK |
1470 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, |
1471 | u32 ringid); | |
05aaa02d | 1472 | int netxen_process_cmd_ring(struct netxen_adapter *adapter); |
3d396eb1 | 1473 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max); |
c9fc891f DP |
1474 | void netxen_p2_nic_set_multi(struct net_device *netdev); |
1475 | void netxen_p3_nic_set_multi(struct net_device *netdev); | |
06e9d9f9 | 1476 | void netxen_p3_free_mac_list(struct netxen_adapter *adapter); |
9ad27643 | 1477 | int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32); |
cd1f8160 | 1478 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter); |
48bfd1e0 | 1479 | |
9ad27643 | 1480 | int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu); |
3d396eb1 | 1481 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); |
48bfd1e0 | 1482 | |
3d396eb1 AK |
1483 | int netxen_nic_set_mac(struct net_device *netdev, void *p); |
1484 | struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); | |
1485 | ||
c9fc891f DP |
1486 | void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, |
1487 | uint32_t crb_producer); | |
cb8011ad AK |
1488 | |
1489 | /* | |
1490 | * NetXen Board information | |
1491 | */ | |
1492 | ||
e4c93c81 | 1493 | #define NETXEN_MAX_SHORT_NAME 32 |
71bd7877 | 1494 | struct netxen_brdinfo { |
cb8011ad AK |
1495 | netxen_brdtype_t brdtype; /* type of board */ |
1496 | long ports; /* max no of physical ports */ | |
1497 | char short_name[NETXEN_MAX_SHORT_NAME]; | |
71bd7877 | 1498 | }; |
cb8011ad | 1499 | |
71bd7877 | 1500 | static const struct netxen_brdinfo netxen_boards[] = { |
cb8011ad AK |
1501 | {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, |
1502 | {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, | |
1503 | {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, | |
1504 | {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, | |
1505 | {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, | |
1506 | {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, | |
e4c93c81 DP |
1507 | {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "}, |
1508 | {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"}, | |
1509 | {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"}, | |
1510 | {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"}, | |
1511 | {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"}, | |
1512 | {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"}, | |
1513 | {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"}, | |
1514 | {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"}, | |
a70f9393 DP |
1515 | {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"}, |
1516 | {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"}, | |
1517 | {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"}, | |
e4c93c81 DP |
1518 | {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"}, |
1519 | {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"} | |
cb8011ad AK |
1520 | }; |
1521 | ||
ff8ac609 | 1522 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards) |
cb8011ad | 1523 | |
cb8011ad AK |
1524 | static inline void get_brd_name_by_type(u32 type, char *name) |
1525 | { | |
1526 | int i, found = 0; | |
1527 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1528 | if (netxen_boards[i].brdtype == type) { | |
1529 | strcpy(name, netxen_boards[i].short_name); | |
1530 | found = 1; | |
1531 | break; | |
1532 | } | |
1533 | ||
3d396eb1 | 1534 | } |
cb8011ad AK |
1535 | if (!found) |
1536 | name = "Unknown"; | |
3d396eb1 AK |
1537 | } |
1538 | ||
96acb6eb DP |
1539 | static inline int |
1540 | dma_watchdog_shutdown_request(struct netxen_adapter *adapter) | |
1541 | { | |
1542 | u32 ctrl; | |
1543 | ||
1544 | /* check if already inactive */ | |
3ce06a32 | 1545 | if (adapter->hw_read_wx(adapter, |
96acb6eb DP |
1546 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) |
1547 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1548 | ||
1549 | if (netxen_get_dma_watchdog_enabled(ctrl) == 0) | |
1550 | return 1; | |
1551 | ||
1552 | /* Send the disable request */ | |
1553 | netxen_set_dma_watchdog_disable_req(ctrl); | |
1554 | netxen_crb_writelit_adapter(adapter, | |
1555 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); | |
1556 | ||
1557 | return 0; | |
1558 | } | |
1559 | ||
1560 | static inline int | |
1561 | dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter) | |
1562 | { | |
1563 | u32 ctrl; | |
1564 | ||
3ce06a32 | 1565 | if (adapter->hw_read_wx(adapter, |
96acb6eb DP |
1566 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) |
1567 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1568 | ||
ceded32f | 1569 | return (netxen_get_dma_watchdog_enabled(ctrl) == 0); |
96acb6eb DP |
1570 | } |
1571 | ||
1572 | static inline int | |
1573 | dma_watchdog_wakeup(struct netxen_adapter *adapter) | |
1574 | { | |
1575 | u32 ctrl; | |
1576 | ||
3ce06a32 | 1577 | if (adapter->hw_read_wx(adapter, |
96acb6eb DP |
1578 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) |
1579 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1580 | ||
1581 | if (netxen_get_dma_watchdog_enabled(ctrl)) | |
1582 | return 1; | |
1583 | ||
1584 | /* send the wakeup request */ | |
1585 | netxen_set_dma_watchdog_enable_req(ctrl); | |
1586 | ||
1587 | netxen_crb_writelit_adapter(adapter, | |
1588 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); | |
1589 | ||
1590 | return 0; | |
1591 | } | |
1592 | ||
1593 | ||
3d396eb1 | 1594 | int netxen_is_flash_supported(struct netxen_adapter *adapter); |
9dc28efe DP |
1595 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
1596 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); | |
3d396eb1 AK |
1597 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
1598 | extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, | |
1599 | int *valp); | |
1600 | ||
1601 | extern struct ethtool_ops netxen_nic_ethtool_ops; | |
1602 | ||
1603 | #endif /* __NETXEN_NIC_H_ */ |