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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | */ | |
29 | ||
30 | #ifndef _NETXEN_NIC_H_ | |
31 | #define _NETXEN_NIC_H_ | |
32 | ||
3d396eb1 AK |
33 | #include <linux/module.h> |
34 | #include <linux/kernel.h> | |
35 | #include <linux/types.h> | |
36 | #include <linux/compiler.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/ioport.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/etherdevice.h> | |
44 | #include <linux/ip.h> | |
45 | #include <linux/in.h> | |
46 | #include <linux/tcp.h> | |
47 | #include <linux/skbuff.h> | |
48 | #include <linux/version.h> | |
49 | ||
50 | #include <linux/ethtool.h> | |
51 | #include <linux/mii.h> | |
52 | #include <linux/interrupt.h> | |
53 | #include <linux/timer.h> | |
54 | ||
55 | #include <linux/mm.h> | |
56 | #include <linux/mman.h> | |
57 | ||
58 | #include <asm/system.h> | |
59 | #include <asm/io.h> | |
60 | #include <asm/byteorder.h> | |
61 | #include <asm/uaccess.h> | |
62 | #include <asm/pgtable.h> | |
63 | ||
64 | #include "netxen_nic_hw.h" | |
65 | ||
ed25ffa1 | 66 | #define _NETXEN_NIC_LINUX_MAJOR 3 |
3d396eb1 | 67 | #define _NETXEN_NIC_LINUX_MINOR 3 |
90f8b1d2 | 68 | #define _NETXEN_NIC_LINUX_SUBVERSION 3 |
27d2ab54 AK |
69 | #define NETXEN_NIC_LINUX_VERSIONID "3.3.3" |
70 | ||
71 | #define NUM_FLASH_SECTORS (64) | |
72 | #define FLASH_SECTOR_SIZE (64 * 1024) | |
73 | #define FLASH_TOTAL_SIZE (NUM_FLASH_SECTORS * FLASH_SECTOR_SIZE) | |
3d396eb1 | 74 | |
0c25cfe1 LCMT |
75 | #define PHAN_VENDOR_ID 0x4040 |
76 | ||
3d396eb1 AK |
77 | #define RCV_DESC_RINGSIZE \ |
78 | (sizeof(struct rcv_desc) * adapter->max_rx_desc_count) | |
79 | #define STATUS_DESC_RINGSIZE \ | |
80 | (sizeof(struct status_desc)* adapter->max_rx_desc_count) | |
ed25ffa1 AK |
81 | #define LRO_DESC_RINGSIZE \ |
82 | (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count) | |
3d396eb1 AK |
83 | #define TX_RINGSIZE \ |
84 | (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count) | |
85 | #define RCV_BUFFSIZE \ | |
86 | (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count) | |
0c25cfe1 | 87 | #define find_diff_among(a,b,range) ((a)<=(b)?((b)-(a)):((b)+(range)-(a))) |
3d396eb1 | 88 | |
ed25ffa1 AK |
89 | #define NETXEN_NETDEV_STATUS 0x1 |
90 | #define NETXEN_RCV_PRODUCER_OFFSET 0 | |
91 | #define NETXEN_RCV_PEG_DB_ID 2 | |
92 | #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 | |
27d2ab54 | 93 | #define FLASH_SUCCESS 0 |
3d396eb1 AK |
94 | |
95 | #define ADDR_IN_WINDOW1(off) \ | |
96 | ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 | |
ed25ffa1 AK |
97 | /* |
98 | * In netxen_nic_down(), we must wait for any pending callback requests into | |
99 | * netxen_watchdog_task() to complete; eg otherwise the watchdog_timer could be | |
100 | * reenabled right after it is deleted in netxen_nic_down(). FLUSH_SCHEDULED_WORK() | |
101 | * does this synchronization. | |
102 | * | |
103 | * Normally, schedule_work()/flush_scheduled_work() could have worked, but | |
104 | * netxen_nic_close() is invoked with kernel rtnl lock held. netif_carrier_off() | |
105 | * call in netxen_nic_close() triggers a schedule_work(&linkwatch_work), and a | |
106 | * subsequent call to flush_scheduled_work() in netxen_nic_down() would cause | |
107 | * linkwatch_event() to be executed which also attempts to acquire the rtnl | |
108 | * lock thus causing a deadlock. | |
109 | */ | |
110 | ||
111 | #define SCHEDULE_WORK(tp) queue_work(netxen_workq, tp) | |
112 | #define FLUSH_SCHEDULED_WORK() flush_workqueue(netxen_workq) | |
113 | extern struct workqueue_struct *netxen_workq; | |
3d396eb1 AK |
114 | |
115 | /* | |
116 | * normalize a 64MB crb address to 32MB PCI window | |
117 | * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 | |
118 | */ | |
80922fbc AK |
119 | #define NETXEN_CRB_NORMAL(reg) \ |
120 | ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) | |
cb8011ad | 121 | |
3d396eb1 | 122 | #define NETXEN_CRB_NORMALIZE(adapter, reg) \ |
cb8011ad AK |
123 | pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) |
124 | ||
ed25ffa1 AK |
125 | #define DB_NORMALIZE(adapter, off) \ |
126 | (adapter->ahw.db_base + (off)) | |
127 | ||
128 | #define NX_P2_C0 0x24 | |
129 | #define NX_P2_C1 0x25 | |
130 | ||
cb8011ad | 131 | #define FIRST_PAGE_GROUP_START 0 |
ed25ffa1 | 132 | #define FIRST_PAGE_GROUP_END 0x100000 |
cb8011ad AK |
133 | |
134 | #define SECOND_PAGE_GROUP_START 0x4000000 | |
135 | #define SECOND_PAGE_GROUP_END 0x66BC000 | |
136 | ||
137 | #define THIRD_PAGE_GROUP_START 0x70E4000 | |
138 | #define THIRD_PAGE_GROUP_END 0x8000000 | |
139 | ||
140 | #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START | |
141 | #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START | |
142 | #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START | |
3d396eb1 | 143 | |
ed25ffa1 | 144 | #define MAX_RX_BUFFER_LENGTH 1760 |
bd56c6b1 | 145 | #define MAX_RX_JUMBO_BUFFER_LENGTH 8062 |
ed25ffa1 AK |
146 | #define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512) |
147 | #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2) | |
3d396eb1 | 148 | #define RX_JUMBO_DMA_MAP_LEN \ |
ed25ffa1 AK |
149 | (MAX_RX_JUMBO_BUFFER_LENGTH - 2) |
150 | #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2) | |
3d396eb1 AK |
151 | #define NETXEN_ROM_ROUNDUP 0x80000000ULL |
152 | ||
153 | /* | |
154 | * Maximum number of ring contexts | |
155 | */ | |
156 | #define MAX_RING_CTX 1 | |
157 | ||
158 | /* Opcodes to be used with the commands */ | |
159 | enum { | |
160 | TX_ETHER_PKT = 0x01, | |
161 | /* The following opcodes are for IP checksum */ | |
162 | TX_TCP_PKT, | |
163 | TX_UDP_PKT, | |
164 | TX_IP_PKT, | |
165 | TX_TCP_LSO, | |
166 | TX_IPSEC, | |
167 | TX_IPSEC_CMD | |
168 | }; | |
169 | ||
170 | /* The following opcodes are for internal consumption. */ | |
171 | #define NETXEN_CONTROL_OP 0x10 | |
172 | #define PEGNET_REQUEST 0x11 | |
173 | ||
174 | #define MAX_NUM_CARDS 4 | |
175 | ||
176 | #define MAX_BUFFERS_PER_CMD 32 | |
177 | ||
178 | /* | |
179 | * Following are the states of the Phantom. Phantom will set them and | |
180 | * Host will read to check if the fields are correct. | |
181 | */ | |
182 | #define PHAN_INITIALIZE_START 0xff00 | |
183 | #define PHAN_INITIALIZE_FAILED 0xffff | |
184 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
185 | ||
186 | /* Host writes the following to notify that it has done the init-handshake */ | |
187 | #define PHAN_INITIALIZE_ACK 0xf00f | |
188 | ||
ed25ffa1 | 189 | #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */ |
3d396eb1 AK |
190 | |
191 | /* descriptor types */ | |
192 | #define RCV_DESC_NORMAL 0x01 | |
193 | #define RCV_DESC_JUMBO 0x02 | |
ed25ffa1 | 194 | #define RCV_DESC_LRO 0x04 |
3d396eb1 AK |
195 | #define RCV_DESC_NORMAL_CTXID 0 |
196 | #define RCV_DESC_JUMBO_CTXID 1 | |
ed25ffa1 | 197 | #define RCV_DESC_LRO_CTXID 2 |
3d396eb1 AK |
198 | |
199 | #define RCV_DESC_TYPE(ID) \ | |
ed25ffa1 AK |
200 | ((ID == RCV_DESC_JUMBO_CTXID) \ |
201 | ? RCV_DESC_JUMBO \ | |
202 | : ((ID == RCV_DESC_LRO_CTXID) \ | |
203 | ? RCV_DESC_LRO : \ | |
204 | (RCV_DESC_NORMAL))) | |
3d396eb1 AK |
205 | |
206 | #define MAX_CMD_DESCRIPTORS 1024 | |
bd56c6b1 AK |
207 | #define MAX_RCV_DESCRIPTORS 16384 |
208 | #define MAX_JUMBO_RCV_DESCRIPTORS 1024 | |
209 | #define MAX_LRO_RCV_DESCRIPTORS 64 | |
3d396eb1 AK |
210 | #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS |
211 | #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS | |
212 | #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS | |
213 | #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS | |
3d396eb1 | 214 | #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8) |
ed25ffa1 AK |
215 | #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \ |
216 | MAX_LRO_RCV_DESCRIPTORS) | |
3d396eb1 AK |
217 | #define MIN_TX_COUNT 4096 |
218 | #define MIN_RX_COUNT 4096 | |
ed25ffa1 AK |
219 | #define NETXEN_CTX_SIGNATURE 0xdee0 |
220 | #define NETXEN_RCV_PRODUCER(ringid) (ringid) | |
3d396eb1 AK |
221 | #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */ |
222 | ||
223 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
224 | #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 | |
225 | ||
226 | #define get_next_index(index, length) \ | |
227 | (((index) + 1) & ((length) - 1)) | |
228 | ||
229 | #define get_index_range(index,length,count) \ | |
230 | (((index) + (count)) & ((length) - 1)) | |
231 | ||
ed25ffa1 AK |
232 | #define MPORT_SINGLE_FUNCTION_MODE 0x1111 |
233 | ||
234 | extern unsigned long long netxen_dma_mask; | |
235 | ||
236 | /* | |
237 | * NetXen host-peg signal message structure | |
238 | * | |
239 | * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx | |
240 | * Bit 2 : priv_id => must be 1 | |
241 | * Bit 3-17 : count => for doorbell | |
242 | * Bit 18-27 : ctx_id => Context id | |
243 | * Bit 28-31 : opcode | |
244 | */ | |
245 | ||
246 | typedef u32 netxen_ctx_msg; | |
247 | ||
ed25ffa1 | 248 | #define netxen_set_msg_peg_id(config_word, val) \ |
a608ab9c | 249 | ((config_word) &= ~3, (config_word) |= val & 3) |
ed25ffa1 | 250 | #define netxen_set_msg_privid(config_word) \ |
a608ab9c | 251 | ((config_word) |= 1 << 2) |
ed25ffa1 | 252 | #define netxen_set_msg_count(config_word, val) \ |
a608ab9c | 253 | ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) |
ed25ffa1 | 254 | #define netxen_set_msg_ctxid(config_word, val) \ |
a608ab9c | 255 | ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) |
ed25ffa1 | 256 | #define netxen_set_msg_opcode(config_word, val) \ |
82581174 | 257 | ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) |
ed25ffa1 AK |
258 | |
259 | struct netxen_rcv_context { | |
a608ab9c AV |
260 | __le64 rcv_ring_addr; |
261 | __le32 rcv_ring_size; | |
262 | __le32 rsrvd; | |
ed25ffa1 AK |
263 | }; |
264 | ||
265 | struct netxen_ring_ctx { | |
266 | ||
267 | /* one command ring */ | |
a608ab9c AV |
268 | __le64 cmd_consumer_offset; |
269 | __le64 cmd_ring_addr; | |
270 | __le32 cmd_ring_size; | |
271 | __le32 rsrvd; | |
ed25ffa1 AK |
272 | |
273 | /* three receive rings */ | |
274 | struct netxen_rcv_context rcv_ctx[3]; | |
275 | ||
276 | /* one status ring */ | |
a608ab9c AV |
277 | __le64 sts_ring_addr; |
278 | __le32 sts_ring_size; | |
ed25ffa1 | 279 | |
a608ab9c | 280 | __le32 ctx_id; |
ed25ffa1 AK |
281 | } __attribute__ ((aligned(64))); |
282 | ||
3d396eb1 AK |
283 | /* |
284 | * Following data structures describe the descriptors that will be used. | |
285 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
286 | * we are doing LSO (above the 1500 size packet) only. | |
287 | */ | |
288 | ||
289 | /* | |
290 | * The size of reference handle been changed to 16 bits to pass the MSS fields | |
291 | * for the LSO packet | |
292 | */ | |
293 | ||
294 | #define FLAGS_CHECKSUM_ENABLED 0x01 | |
295 | #define FLAGS_LSO_ENABLED 0x02 | |
296 | #define FLAGS_IPSEC_SA_ADD 0x04 | |
297 | #define FLAGS_IPSEC_SA_DELETE 0x08 | |
298 | #define FLAGS_VLAN_TAGGED 0x10 | |
299 | ||
ed25ffa1 AK |
300 | #define netxen_set_cmd_desc_port(cmd_desc, var) \ |
301 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
3d396eb1 | 302 | |
ed25ffa1 | 303 | #define netxen_set_cmd_desc_flags(cmd_desc, val) \ |
a608ab9c AV |
304 | ((cmd_desc)->flags_opcode &= ~cpu_to_le16(0x7f), \ |
305 | (cmd_desc)->flags_opcode |= cpu_to_le16((val) & 0x7f)) | |
ed25ffa1 | 306 | #define netxen_set_cmd_desc_opcode(cmd_desc, val) \ |
a608ab9c | 307 | ((cmd_desc)->flags_opcode &= ~cpu_to_le16(0x3f<<7), \ |
82581174 | 308 | (cmd_desc)->flags_opcode |= cpu_to_le16(((val & 0x3f)<<7))) |
ed25ffa1 AK |
309 | |
310 | #define netxen_set_cmd_desc_num_of_buff(cmd_desc, val) \ | |
a608ab9c AV |
311 | ((cmd_desc)->num_of_buffers_total_length &= ~cpu_to_le32(0xff), \ |
312 | (cmd_desc)->num_of_buffers_total_length |= cpu_to_le32((val) & 0xff)) | |
ed25ffa1 | 313 | #define netxen_set_cmd_desc_totallength(cmd_desc, val) \ |
82581174 AK |
314 | ((cmd_desc)->num_of_buffers_total_length &= ~cpu_to_le32(0xffffff00), \ |
315 | (cmd_desc)->num_of_buffers_total_length |= cpu_to_le32(val << 8)) | |
ed25ffa1 AK |
316 | |
317 | #define netxen_get_cmd_desc_opcode(cmd_desc) \ | |
a608ab9c | 318 | ((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003F) |
ed25ffa1 | 319 | #define netxen_get_cmd_desc_totallength(cmd_desc) \ |
a608ab9c | 320 | (le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8) |
3d396eb1 AK |
321 | |
322 | struct cmd_desc_type0 { | |
ed25ffa1 AK |
323 | u8 tcp_hdr_offset; /* For LSO only */ |
324 | u8 ip_hdr_offset; /* For LSO only */ | |
325 | /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */ | |
a608ab9c | 326 | __le16 flags_opcode; |
ed25ffa1 AK |
327 | /* Bit pattern: 0-7 total number of segments, |
328 | 8-31 Total size of the packet */ | |
a608ab9c | 329 | __le32 num_of_buffers_total_length; |
3d396eb1 AK |
330 | union { |
331 | struct { | |
a608ab9c AV |
332 | __le32 addr_low_part2; |
333 | __le32 addr_high_part2; | |
3d396eb1 | 334 | }; |
a608ab9c | 335 | __le64 addr_buffer2; |
3d396eb1 AK |
336 | }; |
337 | ||
a608ab9c AV |
338 | __le16 reference_handle; /* changed to u16 to add mss */ |
339 | __le16 mss; /* passed by NDIS_PACKET for LSO */ | |
3d396eb1 AK |
340 | /* Bit pattern 0-3 port, 0-3 ctx id */ |
341 | u8 port_ctxid; | |
342 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
a608ab9c | 343 | __le16 conn_id; /* IPSec offoad only */ |
3d396eb1 AK |
344 | |
345 | union { | |
346 | struct { | |
a608ab9c AV |
347 | __le32 addr_low_part3; |
348 | __le32 addr_high_part3; | |
3d396eb1 | 349 | }; |
a608ab9c | 350 | __le64 addr_buffer3; |
3d396eb1 | 351 | }; |
3d396eb1 AK |
352 | union { |
353 | struct { | |
a608ab9c AV |
354 | __le32 addr_low_part1; |
355 | __le32 addr_high_part1; | |
3d396eb1 | 356 | }; |
a608ab9c | 357 | __le64 addr_buffer1; |
3d396eb1 AK |
358 | }; |
359 | ||
a608ab9c AV |
360 | __le16 buffer1_length; |
361 | __le16 buffer2_length; | |
362 | __le16 buffer3_length; | |
363 | __le16 buffer4_length; | |
3d396eb1 AK |
364 | |
365 | union { | |
366 | struct { | |
a608ab9c AV |
367 | __le32 addr_low_part4; |
368 | __le32 addr_high_part4; | |
3d396eb1 | 369 | }; |
a608ab9c | 370 | __le64 addr_buffer4; |
3d396eb1 AK |
371 | }; |
372 | ||
a608ab9c | 373 | __le64 unused; |
ed25ffa1 | 374 | |
3d396eb1 AK |
375 | } __attribute__ ((aligned(64))); |
376 | ||
377 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
378 | struct rcv_desc { | |
a608ab9c AV |
379 | __le16 reference_handle; |
380 | __le16 reserved; | |
381 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
382 | __le64 addr_buffer; | |
3d396eb1 AK |
383 | }; |
384 | ||
385 | /* opcode field in status_desc */ | |
386 | #define RCV_NIC_PKT (0xA) | |
387 | #define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12) | |
388 | ||
389 | /* for status field in status_desc */ | |
390 | #define STATUS_NEED_CKSUM (1) | |
391 | #define STATUS_CKSUM_OK (2) | |
392 | ||
393 | /* owner bits of status_desc */ | |
394 | #define STATUS_OWNER_HOST (0x1) | |
395 | #define STATUS_OWNER_PHANTOM (0x2) | |
396 | ||
397 | #define NETXEN_PROT_IP (1) | |
398 | #define NETXEN_PROT_UNKNOWN (0) | |
399 | ||
400 | /* Note: sizeof(status_desc) should always be a mutliple of 2 */ | |
ed25ffa1 AK |
401 | |
402 | #define netxen_get_sts_desc_lro_cnt(status_desc) \ | |
403 | ((status_desc)->lro & 0x7F) | |
404 | #define netxen_get_sts_desc_lro_last_frag(status_desc) \ | |
405 | (((status_desc)->lro & 0x80) >> 7) | |
406 | ||
407 | #define netxen_get_sts_port(status_desc) \ | |
a608ab9c | 408 | (le64_to_cpu((status_desc)->status_desc_data) & 0x0F) |
ed25ffa1 | 409 | #define netxen_get_sts_status(status_desc) \ |
a608ab9c | 410 | ((le64_to_cpu((status_desc)->status_desc_data) >> 4) & 0x0F) |
ed25ffa1 | 411 | #define netxen_get_sts_type(status_desc) \ |
a608ab9c | 412 | ((le64_to_cpu((status_desc)->status_desc_data) >> 8) & 0x0F) |
ed25ffa1 | 413 | #define netxen_get_sts_totallength(status_desc) \ |
a608ab9c | 414 | ((le64_to_cpu((status_desc)->status_desc_data) >> 12) & 0xFFFF) |
ed25ffa1 | 415 | #define netxen_get_sts_refhandle(status_desc) \ |
a608ab9c | 416 | ((le64_to_cpu((status_desc)->status_desc_data) >> 28) & 0xFFFF) |
ed25ffa1 | 417 | #define netxen_get_sts_prot(status_desc) \ |
a608ab9c | 418 | ((le64_to_cpu((status_desc)->status_desc_data) >> 44) & 0x0F) |
ed25ffa1 | 419 | #define netxen_get_sts_owner(status_desc) \ |
a608ab9c | 420 | ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03) |
ed25ffa1 | 421 | #define netxen_get_sts_opcode(status_desc) \ |
a608ab9c | 422 | ((le64_to_cpu((status_desc)->status_desc_data) >> 58) & 0x03F) |
ed25ffa1 AK |
423 | |
424 | #define netxen_clear_sts_owner(status_desc) \ | |
425 | ((status_desc)->status_desc_data &= \ | |
a608ab9c | 426 | ~cpu_to_le64(((unsigned long long)3) << 56 )) |
ed25ffa1 AK |
427 | #define netxen_set_sts_owner(status_desc, val) \ |
428 | ((status_desc)->status_desc_data |= \ | |
a608ab9c | 429 | cpu_to_le64(((unsigned long long)((val) & 0x3)) << 56 )) |
3d396eb1 AK |
430 | |
431 | struct status_desc { | |
ed25ffa1 AK |
432 | /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length |
433 | 28-43 reference_handle, 44-47 protocol, 48-52 unused | |
434 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode | |
435 | */ | |
a608ab9c AV |
436 | __le64 status_desc_data; |
437 | __le32 hash_value; | |
ed25ffa1 AK |
438 | u8 hash_type; |
439 | u8 msg_type; | |
440 | u8 unused; | |
441 | /* Bit pattern: 0-6 lro_count indicates frag sequence, | |
442 | 7 last_frag indicates last frag */ | |
443 | u8 lro; | |
3d396eb1 AK |
444 | } __attribute__ ((aligned(8))); |
445 | ||
446 | enum { | |
447 | NETXEN_RCV_PEG_0 = 0, | |
448 | NETXEN_RCV_PEG_1 | |
449 | }; | |
450 | /* The version of the main data structure */ | |
451 | #define NETXEN_BDINFO_VERSION 1 | |
452 | ||
453 | /* Magic number to let user know flash is programmed */ | |
454 | #define NETXEN_BDINFO_MAGIC 0x12345678 | |
455 | ||
456 | /* Max number of Gig ports on a Phantom board */ | |
457 | #define NETXEN_MAX_PORTS 4 | |
458 | ||
459 | typedef enum { | |
460 | NETXEN_BRDTYPE_P1_BD = 0x0000, | |
461 | NETXEN_BRDTYPE_P1_SB = 0x0001, | |
462 | NETXEN_BRDTYPE_P1_SMAX = 0x0002, | |
463 | NETXEN_BRDTYPE_P1_SOCK = 0x0003, | |
464 | ||
465 | NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008, | |
466 | NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009, | |
467 | NETXEN_BRDTYPE_P2_SB35_4G = 0x000a, | |
468 | NETXEN_BRDTYPE_P2_SB31_10G = 0x000b, | |
469 | NETXEN_BRDTYPE_P2_SB31_2G = 0x000c, | |
470 | ||
471 | NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d, | |
472 | NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e, | |
473 | NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f | |
474 | } netxen_brdtype_t; | |
475 | ||
476 | typedef enum { | |
477 | NETXEN_BRDMFG_INVENTEC = 1 | |
478 | } netxen_brdmfg; | |
479 | ||
480 | typedef enum { | |
481 | MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */ | |
482 | MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */ | |
483 | MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */ | |
484 | MEM_ORG_256Mbx4 = 0x3, | |
485 | MEM_ORG_256Mbx8 = 0x4, | |
486 | MEM_ORG_256Mbx16 = 0x5, | |
487 | MEM_ORG_512Mbx4 = 0x6, | |
488 | MEM_ORG_512Mbx8 = 0x7, | |
489 | MEM_ORG_512Mbx16 = 0x8, | |
490 | MEM_ORG_1Gbx4 = 0x9, | |
491 | MEM_ORG_1Gbx8 = 0xa, | |
492 | MEM_ORG_1Gbx16 = 0xb, | |
493 | MEM_ORG_2Gbx4 = 0xc, | |
494 | MEM_ORG_2Gbx8 = 0xd, | |
495 | MEM_ORG_2Gbx16 = 0xe, | |
496 | MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */ | |
497 | MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */ | |
498 | } netxen_mn_mem_org_t; | |
499 | ||
500 | typedef enum { | |
501 | MEM_ORG_512Kx36 = 0x0, | |
502 | MEM_ORG_1Mx36 = 0x1, | |
503 | MEM_ORG_2Mx36 = 0x2 | |
504 | } netxen_sn_mem_org_t; | |
505 | ||
506 | typedef enum { | |
507 | MEM_DEPTH_4MB = 0x1, | |
508 | MEM_DEPTH_8MB = 0x2, | |
509 | MEM_DEPTH_16MB = 0x3, | |
510 | MEM_DEPTH_32MB = 0x4, | |
511 | MEM_DEPTH_64MB = 0x5, | |
512 | MEM_DEPTH_128MB = 0x6, | |
513 | MEM_DEPTH_256MB = 0x7, | |
514 | MEM_DEPTH_512MB = 0x8, | |
515 | MEM_DEPTH_1GB = 0x9, | |
516 | MEM_DEPTH_2GB = 0xa, | |
517 | MEM_DEPTH_4GB = 0xb, | |
518 | MEM_DEPTH_8GB = 0xc, | |
519 | MEM_DEPTH_16GB = 0xd, | |
520 | MEM_DEPTH_32GB = 0xe | |
521 | } netxen_mem_depth_t; | |
522 | ||
523 | struct netxen_board_info { | |
524 | u32 header_version; | |
525 | ||
526 | u32 board_mfg; | |
527 | u32 board_type; | |
528 | u32 board_num; | |
529 | u32 chip_id; | |
530 | u32 chip_minor; | |
531 | u32 chip_major; | |
532 | u32 chip_pkg; | |
533 | u32 chip_lot; | |
534 | ||
535 | u32 port_mask; /* available niu ports */ | |
536 | u32 peg_mask; /* available pegs */ | |
537 | u32 icache_ok; /* can we run with icache? */ | |
538 | u32 dcache_ok; /* can we run with dcache? */ | |
539 | u32 casper_ok; | |
540 | ||
541 | u32 mac_addr_lo_0; | |
542 | u32 mac_addr_lo_1; | |
543 | u32 mac_addr_lo_2; | |
544 | u32 mac_addr_lo_3; | |
545 | ||
546 | /* MN-related config */ | |
547 | u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */ | |
548 | u32 mn_sync_shift_cclk; | |
549 | u32 mn_sync_shift_mclk; | |
550 | u32 mn_wb_en; | |
551 | u32 mn_crystal_freq; /* in MHz */ | |
552 | u32 mn_speed; /* in MHz */ | |
553 | u32 mn_org; | |
554 | u32 mn_depth; | |
555 | u32 mn_ranks_0; /* ranks per slot */ | |
556 | u32 mn_ranks_1; /* ranks per slot */ | |
557 | u32 mn_rd_latency_0; | |
558 | u32 mn_rd_latency_1; | |
559 | u32 mn_rd_latency_2; | |
560 | u32 mn_rd_latency_3; | |
561 | u32 mn_rd_latency_4; | |
562 | u32 mn_rd_latency_5; | |
563 | u32 mn_rd_latency_6; | |
564 | u32 mn_rd_latency_7; | |
565 | u32 mn_rd_latency_8; | |
566 | u32 mn_dll_val[18]; | |
567 | u32 mn_mode_reg; /* MIU DDR Mode Register */ | |
568 | u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */ | |
569 | u32 mn_timing_0; /* MIU Memory Control Timing Rgister */ | |
570 | u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */ | |
571 | u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */ | |
572 | ||
573 | /* SN-related config */ | |
574 | u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */ | |
575 | u32 sn_pt_mode; /* pass through mode */ | |
576 | u32 sn_ecc_en; | |
577 | u32 sn_wb_en; | |
578 | u32 sn_crystal_freq; | |
579 | u32 sn_speed; | |
580 | u32 sn_org; | |
581 | u32 sn_depth; | |
582 | u32 sn_dll_tap; | |
583 | u32 sn_rd_latency; | |
584 | ||
585 | u32 mac_addr_hi_0; | |
586 | u32 mac_addr_hi_1; | |
587 | u32 mac_addr_hi_2; | |
588 | u32 mac_addr_hi_3; | |
589 | ||
590 | u32 magic; /* indicates flash has been initialized */ | |
591 | ||
592 | u32 mn_rdimm; | |
593 | u32 mn_dll_override; | |
594 | ||
595 | }; | |
596 | ||
597 | #define FLASH_NUM_PORTS (4) | |
598 | ||
599 | struct netxen_flash_mac_addr { | |
600 | u32 flash_addr[32]; | |
601 | }; | |
602 | ||
603 | struct netxen_user_old_info { | |
604 | u8 flash_md5[16]; | |
605 | u8 crbinit_md5[16]; | |
606 | u8 brdcfg_md5[16]; | |
607 | /* bootloader */ | |
608 | u32 bootld_version; | |
609 | u32 bootld_size; | |
610 | u8 bootld_md5[16]; | |
611 | /* image */ | |
612 | u32 image_version; | |
613 | u32 image_size; | |
614 | u8 image_md5[16]; | |
615 | /* primary image status */ | |
616 | u32 primary_status; | |
617 | u32 secondary_present; | |
618 | ||
619 | /* MAC address , 4 ports */ | |
620 | struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS]; | |
621 | }; | |
622 | #define FLASH_NUM_MAC_PER_PORT 32 | |
623 | struct netxen_user_info { | |
624 | u8 flash_md5[16 * 64]; | |
625 | /* bootloader */ | |
626 | u32 bootld_version; | |
627 | u32 bootld_size; | |
628 | /* image */ | |
629 | u32 image_version; | |
630 | u32 image_size; | |
631 | /* primary image status */ | |
632 | u32 primary_status; | |
633 | u32 secondary_present; | |
634 | ||
635 | /* MAC address , 4 ports, 32 address per port */ | |
636 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
637 | u32 sub_sys_id; | |
638 | u8 serial_num[32]; | |
639 | ||
640 | /* Any user defined data */ | |
641 | }; | |
642 | ||
643 | /* | |
644 | * Flash Layout - new format. | |
645 | */ | |
646 | struct netxen_new_user_info { | |
647 | u8 flash_md5[16 * 64]; | |
648 | /* bootloader */ | |
649 | u32 bootld_version; | |
650 | u32 bootld_size; | |
651 | /* image */ | |
652 | u32 image_version; | |
653 | u32 image_size; | |
654 | /* primary image status */ | |
655 | u32 primary_status; | |
656 | u32 secondary_present; | |
657 | ||
658 | /* MAC address , 4 ports, 32 address per port */ | |
659 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
660 | u32 sub_sys_id; | |
661 | u8 serial_num[32]; | |
662 | ||
663 | /* Any user defined data */ | |
664 | }; | |
665 | ||
666 | #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6 | |
667 | #define SECONDARY_IMAGE_ABSENT 0xffffffff | |
668 | #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a | |
669 | #define PRIMARY_IMAGE_BAD 0xffffffff | |
670 | ||
671 | /* Flash memory map */ | |
672 | typedef enum { | |
673 | CRBINIT_START = 0, /* Crbinit section */ | |
674 | BRDCFG_START = 0x4000, /* board config */ | |
675 | INITCODE_START = 0x6000, /* pegtune code */ | |
676 | BOOTLD_START = 0x10000, /* bootld */ | |
677 | IMAGE_START = 0x43000, /* compressed image */ | |
678 | SECONDARY_START = 0x200000, /* backup images */ | |
679 | PXE_START = 0x3E0000, /* user defined region */ | |
680 | USER_START = 0x3E8000, /* User defined region for new boards */ | |
681 | FIXED_START = 0x3F0000 /* backup of crbinit */ | |
682 | } netxen_flash_map_t; | |
683 | ||
684 | #define USER_START_OLD PXE_START /* for backward compatibility */ | |
685 | ||
686 | #define FLASH_START (CRBINIT_START) | |
687 | #define INIT_SECTOR (0) | |
688 | #define PRIMARY_START (BOOTLD_START) | |
689 | #define FLASH_CRBINIT_SIZE (0x4000) | |
690 | #define FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info)) | |
80922fbc | 691 | #define FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32)) |
3d396eb1 AK |
692 | #define FLASH_SECONDARY_SIZE (USER_START-SECONDARY_START) |
693 | #define NUM_PRIMARY_SECTORS (0x20) | |
694 | #define NUM_CONFIG_SECTORS (1) | |
ed25ffa1 AK |
695 | #define PFX "NetXen: " |
696 | extern char netxen_nic_driver_name[]; | |
3d396eb1 AK |
697 | |
698 | /* Note: Make sure to not call this before adapter->port is valid */ | |
699 | #if !defined(NETXEN_DEBUG) | |
700 | #define DPRINTK(klevel, fmt, args...) do { \ | |
701 | } while (0) | |
702 | #else | |
703 | #define DPRINTK(klevel, fmt, args...) do { \ | |
704 | printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\ | |
80922fbc | 705 | (adapter != NULL && \ |
3d396eb1 AK |
706 | adapter->port[0] != NULL && \ |
707 | adapter->port[0]->netdev != NULL) ? \ | |
708 | adapter->port[0]->netdev->name : NULL, \ | |
709 | ## args); } while(0) | |
710 | #endif | |
711 | ||
712 | /* Number of status descriptors to handle per interrupt */ | |
713 | #define MAX_STATUS_HANDLE (128) | |
714 | ||
715 | /* | |
716 | * netxen_skb_frag{} is to contain mapping info for each SG list. This | |
717 | * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. | |
718 | */ | |
719 | struct netxen_skb_frag { | |
720 | u64 dma; | |
721 | u32 length; | |
722 | }; | |
723 | ||
724 | /* Following defines are for the state of the buffers */ | |
725 | #define NETXEN_BUFFER_FREE 0 | |
726 | #define NETXEN_BUFFER_BUSY 1 | |
727 | ||
728 | /* | |
729 | * There will be one netxen_buffer per skb packet. These will be | |
730 | * used to save the dma info for pci_unmap_page() | |
731 | */ | |
732 | struct netxen_cmd_buffer { | |
733 | struct sk_buff *skb; | |
734 | struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; | |
735 | u32 total_length; | |
736 | u32 mss; | |
737 | u16 port; | |
738 | u8 cmd; | |
739 | u8 frag_count; | |
740 | unsigned long time_stamp; | |
741 | u32 state; | |
3d396eb1 AK |
742 | }; |
743 | ||
744 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
745 | struct netxen_rx_buffer { | |
746 | struct sk_buff *skb; | |
747 | u64 dma; | |
748 | u16 ref_handle; | |
749 | u16 state; | |
ed25ffa1 AK |
750 | u32 lro_expected_frags; |
751 | u32 lro_current_frags; | |
752 | u32 lro_length; | |
3d396eb1 AK |
753 | }; |
754 | ||
755 | /* Board types */ | |
756 | #define NETXEN_NIC_GBE 0x01 | |
757 | #define NETXEN_NIC_XGBE 0x02 | |
758 | ||
759 | /* | |
760 | * One hardware_context{} per adapter | |
761 | * contains interrupt info as well shared hardware info. | |
762 | */ | |
763 | struct netxen_hardware_context { | |
764 | struct pci_dev *pdev; | |
cb8011ad AK |
765 | void __iomem *pci_base0; |
766 | void __iomem *pci_base1; | |
767 | void __iomem *pci_base2; | |
ed25ffa1 AK |
768 | void __iomem *db_base; |
769 | unsigned long db_len; | |
cb8011ad | 770 | |
3d396eb1 AK |
771 | u8 revision_id; |
772 | u16 board_type; | |
773 | u16 max_ports; | |
774 | struct netxen_board_info boardcfg; | |
775 | u32 xg_linkup; | |
cb8011ad | 776 | u32 qg_linksup; |
3d396eb1 AK |
777 | /* Address of cmd ring in Phantom */ |
778 | struct cmd_desc_type0 *cmd_desc_head; | |
cb8011ad | 779 | struct pci_dev *cmd_desc_pdev; |
3d396eb1 AK |
780 | dma_addr_t cmd_desc_phys_addr; |
781 | struct netxen_adapter *adapter; | |
782 | }; | |
783 | ||
ed25ffa1 AK |
784 | #define RCV_RING_LRO RCV_DESC_LRO |
785 | ||
3d396eb1 AK |
786 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ |
787 | #define ETHERNET_FCS_SIZE 4 | |
788 | ||
789 | struct netxen_adapter_stats { | |
790 | u64 ints; | |
791 | u64 hostints; | |
792 | u64 otherints; | |
793 | u64 process_rcv; | |
794 | u64 process_xmit; | |
795 | u64 noxmitdone; | |
796 | u64 xmitcsummed; | |
797 | u64 post_called; | |
798 | u64 posted; | |
799 | u64 lastposted; | |
800 | u64 goodskbposts; | |
801 | }; | |
802 | ||
803 | /* | |
804 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
805 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
806 | */ | |
807 | struct netxen_rcv_desc_ctx { | |
808 | u32 flags; | |
809 | u32 producer; | |
810 | u32 rcv_pending; /* Num of bufs posted in phantom */ | |
811 | u32 rcv_free; /* Num of bufs in free list */ | |
812 | dma_addr_t phys_addr; | |
cb8011ad | 813 | struct pci_dev *phys_pdev; |
3d396eb1 AK |
814 | struct rcv_desc *desc_head; /* address of rx ring in Phantom */ |
815 | u32 max_rx_desc_count; | |
816 | u32 dma_size; | |
817 | u32 skb_size; | |
818 | struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */ | |
819 | int begin_alloc; | |
820 | }; | |
821 | ||
822 | /* | |
823 | * Receive context. There is one such structure per instance of the | |
824 | * receive processing. Any state information that is relevant to | |
825 | * the receive, and is must be in this structure. The global data may be | |
826 | * present elsewhere. | |
827 | */ | |
828 | struct netxen_recv_context { | |
829 | struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS]; | |
830 | u32 status_rx_producer; | |
831 | u32 status_rx_consumer; | |
832 | dma_addr_t rcv_status_desc_phys_addr; | |
cb8011ad | 833 | struct pci_dev *rcv_status_desc_pdev; |
3d396eb1 AK |
834 | struct status_desc *rcv_status_desc_head; |
835 | }; | |
836 | ||
837 | #define NETXEN_NIC_MSI_ENABLED 0x02 | |
ed25ffa1 AK |
838 | #define NETXEN_DMA_MASK 0xfffffffe |
839 | #define NETXEN_DB_MAPSIZE_BYTES 0x1000 | |
840 | ||
841 | struct netxen_dummy_dma { | |
842 | void *addr; | |
843 | dma_addr_t phys_addr; | |
844 | }; | |
3d396eb1 | 845 | |
3d396eb1 AK |
846 | struct netxen_adapter { |
847 | struct netxen_hardware_context ahw; | |
848 | int port_count; /* Number of configured ports */ | |
849 | int active_ports; /* Number of open ports */ | |
850 | struct netxen_port *port[NETXEN_MAX_PORTS]; /* ptr to each port */ | |
851 | spinlock_t tx_lock; | |
852 | spinlock_t lock; | |
853 | struct work_struct watchdog_task; | |
3d396eb1 AK |
854 | struct timer_list watchdog_timer; |
855 | ||
856 | u32 curr_window; | |
857 | ||
858 | u32 cmd_producer; | |
ed25ffa1 | 859 | u32 *cmd_consumer; |
3d396eb1 AK |
860 | |
861 | u32 last_cmd_consumer; | |
862 | u32 max_tx_desc_count; | |
863 | u32 max_rx_desc_count; | |
864 | u32 max_jumbo_rx_desc_count; | |
ed25ffa1 | 865 | u32 max_lro_rx_desc_count; |
3d396eb1 AK |
866 | /* Num of instances active on cmd buffer ring */ |
867 | u32 proc_cmd_buf_counter; | |
868 | ||
869 | u32 num_threads, total_threads; /*Use to keep track of xmit threads */ | |
870 | ||
871 | u32 flags; | |
872 | u32 irq; | |
873 | int driver_mismatch; | |
cb8011ad | 874 | u32 temp; |
3d396eb1 AK |
875 | |
876 | struct netxen_adapter_stats stats; | |
877 | ||
878 | struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */ | |
879 | ||
880 | /* | |
881 | * Receive instances. These can be either one per port, | |
882 | * or one per peg, etc. | |
883 | */ | |
884 | struct netxen_recv_context recv_ctx[MAX_RCV_CTX]; | |
885 | ||
886 | int is_up; | |
ed25ffa1 AK |
887 | struct netxen_dummy_dma dummy_dma; |
888 | ||
889 | /* Context interface shared between card and host */ | |
890 | struct netxen_ring_ctx *ctx_desc; | |
891 | struct pci_dev *ctx_desc_pdev; | |
892 | dma_addr_t ctx_desc_phys_addr; | |
80922fbc AK |
893 | int (*enable_phy_interrupts) (struct netxen_adapter *, int); |
894 | int (*disable_phy_interrupts) (struct netxen_adapter *, int); | |
895 | void (*handle_phy_intr) (struct netxen_adapter *); | |
896 | int (*macaddr_set) (struct netxen_port *, netxen_ethernet_macaddr_t); | |
897 | int (*set_mtu) (struct netxen_port *, int); | |
898 | int (*set_promisc) (struct netxen_adapter *, int, | |
899 | netxen_niu_prom_mode_t); | |
900 | int (*unset_promisc) (struct netxen_adapter *, int, | |
901 | netxen_niu_prom_mode_t); | |
902 | int (*phy_read) (struct netxen_adapter *, long phy, long reg, u32 *); | |
903 | int (*phy_write) (struct netxen_adapter *, long phy, long reg, u32 val); | |
904 | int (*init_port) (struct netxen_adapter *, int); | |
905 | void (*init_niu) (struct netxen_adapter *); | |
906 | int (*stop_port) (struct netxen_adapter *, int); | |
3d396eb1 AK |
907 | }; /* netxen_adapter structure */ |
908 | ||
909 | /* Max number of xmit producer threads that can run simultaneously */ | |
910 | #define MAX_XMIT_PRODUCERS 16 | |
911 | ||
912 | struct netxen_port_stats { | |
913 | u64 rcvdbadskb; | |
914 | u64 xmitcalled; | |
915 | u64 xmitedframes; | |
916 | u64 xmitfinished; | |
917 | u64 badskblen; | |
918 | u64 nocmddescriptor; | |
919 | u64 polled; | |
920 | u64 uphappy; | |
921 | u64 updropped; | |
922 | u64 uplcong; | |
923 | u64 uphcong; | |
924 | u64 upmcong; | |
925 | u64 updunno; | |
926 | u64 skbfreed; | |
927 | u64 txdropped; | |
928 | u64 txnullskb; | |
929 | u64 csummed; | |
930 | u64 no_rcv; | |
931 | u64 rxbytes; | |
932 | u64 txbytes; | |
933 | }; | |
934 | ||
935 | struct netxen_port { | |
936 | struct netxen_adapter *adapter; | |
937 | ||
938 | u16 portnum; /* GBE port number */ | |
939 | u16 link_speed; | |
940 | u16 link_duplex; | |
941 | u16 link_autoneg; | |
942 | ||
943 | int flags; | |
944 | ||
945 | struct net_device *netdev; | |
946 | struct pci_dev *pdev; | |
947 | struct net_device_stats net_stats; | |
948 | struct netxen_port_stats stats; | |
6c586644 | 949 | struct work_struct tx_timeout_task; |
3d396eb1 AK |
950 | }; |
951 | ||
cb8011ad AK |
952 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
953 | ((adapter)->ahw.pci_base0 + (off)) | |
954 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | |
955 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) | |
956 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ | |
957 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) | |
958 | ||
959 | static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter, | |
960 | unsigned long off) | |
961 | { | |
962 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
963 | return (adapter->ahw.pci_base0 + off); | |
964 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
965 | (off >= SECOND_PAGE_GROUP_START)) { | |
966 | return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START); | |
967 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
968 | (off >= THIRD_PAGE_GROUP_START)) { | |
969 | return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START); | |
970 | } | |
971 | return NULL; | |
972 | } | |
973 | ||
974 | static inline void __iomem *pci_base(struct netxen_adapter *adapter, | |
975 | unsigned long off) | |
976 | { | |
977 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
978 | return adapter->ahw.pci_base0; | |
979 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
980 | (off >= SECOND_PAGE_GROUP_START)) { | |
981 | return adapter->ahw.pci_base1; | |
982 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
983 | (off >= THIRD_PAGE_GROUP_START)) { | |
984 | return adapter->ahw.pci_base2; | |
985 | } | |
986 | return NULL; | |
987 | } | |
988 | ||
3d396eb1 AK |
989 | int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter, |
990 | int port); | |
991 | int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter, | |
992 | int port); | |
993 | int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter, | |
994 | int port); | |
995 | int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter, | |
996 | int port); | |
997 | int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter, | |
998 | int port); | |
999 | int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter, | |
1000 | int port); | |
1001 | void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter); | |
1002 | void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter); | |
1003 | void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, int port, | |
1004 | long enable); | |
1005 | void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, int port, | |
1006 | long enable); | |
1007 | int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy, long reg, | |
a608ab9c | 1008 | __u32 * readval); |
3d396eb1 | 1009 | int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long phy, |
a608ab9c | 1010 | long reg, __u32 val); |
3d396eb1 AK |
1011 | |
1012 | /* Functions available from netxen_nic_hw.c */ | |
3d396eb1 AK |
1013 | int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu); |
1014 | int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu); | |
1015 | void netxen_nic_init_niu_gb(struct netxen_adapter *adapter); | |
1016 | void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw); | |
1017 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); | |
1018 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); | |
1019 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); | |
1020 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value); | |
1021 | ||
1022 | int netxen_nic_get_board_info(struct netxen_adapter *adapter); | |
1023 | int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
1024 | int len); | |
1025 | int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
1026 | int len); | |
1027 | void netxen_crb_writelit_adapter(struct netxen_adapter *adapter, | |
1028 | unsigned long off, int data); | |
1029 | ||
1030 | /* Functions from netxen_nic_init.c */ | |
ed25ffa1 AK |
1031 | void netxen_free_adapter_offload(struct netxen_adapter *adapter); |
1032 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter); | |
cb8011ad | 1033 | void netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); |
3d396eb1 AK |
1034 | void netxen_load_firmware(struct netxen_adapter *adapter); |
1035 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); | |
1036 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); | |
27d2ab54 AK |
1037 | int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
1038 | u8 *bytes, size_t size); | |
1039 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, | |
1040 | u8 *bytes, size_t size); | |
1041 | int netxen_flash_unlock(struct netxen_adapter *adapter); | |
1042 | int netxen_backup_crbinit(struct netxen_adapter *adapter); | |
1043 | int netxen_flash_erase_secondary(struct netxen_adapter *adapter); | |
1044 | int netxen_flash_erase_primary(struct netxen_adapter *adapter); | |
e45d9ab4 | 1045 | void netxen_halt_pegs(struct netxen_adapter *adapter); |
27d2ab54 | 1046 | |
cb8011ad AK |
1047 | int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data); |
1048 | int netxen_rom_se(struct netxen_adapter *adapter, int addr); | |
1049 | int netxen_do_rom_se(struct netxen_adapter *adapter, int addr); | |
3d396eb1 AK |
1050 | |
1051 | /* Functions from netxen_nic_isr.c */ | |
1052 | void netxen_nic_isr_other(struct netxen_adapter *adapter); | |
1053 | void netxen_indicate_link_status(struct netxen_adapter *adapter, u32 port, | |
1054 | u32 link); | |
1055 | void netxen_handle_port_int(struct netxen_adapter *adapter, u32 port, | |
1056 | u32 enable); | |
1057 | void netxen_nic_stop_all_ports(struct netxen_adapter *adapter); | |
1058 | void netxen_initialize_adapter_sw(struct netxen_adapter *adapter); | |
1059 | void netxen_initialize_adapter_hw(struct netxen_adapter *adapter); | |
cb8011ad AK |
1060 | void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr, |
1061 | struct pci_dev **used_dev); | |
3d396eb1 AK |
1062 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); |
1063 | int netxen_init_firmware(struct netxen_adapter *adapter); | |
1064 | void netxen_free_hw_resources(struct netxen_adapter *adapter); | |
1065 | void netxen_tso_check(struct netxen_adapter *adapter, | |
1066 | struct cmd_desc_type0 *desc, struct sk_buff *skb); | |
1067 | int netxen_nic_hw_resources(struct netxen_adapter *adapter); | |
1068 | void netxen_nic_clear_stats(struct netxen_adapter *adapter); | |
3d396eb1 AK |
1069 | int netxen_nic_rx_has_work(struct netxen_adapter *adapter); |
1070 | int netxen_nic_tx_has_work(struct netxen_adapter *adapter); | |
6d5aefb8 | 1071 | void netxen_watchdog_task(struct work_struct *work); |
3d396eb1 AK |
1072 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, |
1073 | u32 ringid); | |
ed25ffa1 AK |
1074 | void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, u32 ctx, |
1075 | u32 ringid); | |
1076 | int netxen_process_cmd_ring(unsigned long data); | |
3d396eb1 AK |
1077 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max); |
1078 | void netxen_nic_set_multi(struct net_device *netdev); | |
1079 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); | |
1080 | int netxen_nic_set_mac(struct net_device *netdev, void *p); | |
1081 | struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); | |
1082 | ||
1083 | static inline void netxen_nic_disable_int(struct netxen_adapter *adapter) | |
1084 | { | |
1085 | /* | |
1086 | * ISR_INT_MASK: Can be read from window 0 or 1. | |
1087 | */ | |
71bd7877 | 1088 | writel(0x7ff, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)); |
cb8011ad | 1089 | |
3d396eb1 AK |
1090 | } |
1091 | ||
1092 | static inline void netxen_nic_enable_int(struct netxen_adapter *adapter) | |
1093 | { | |
1094 | u32 mask; | |
1095 | ||
1096 | switch (adapter->ahw.board_type) { | |
1097 | case NETXEN_NIC_GBE: | |
1098 | mask = 0x77b; | |
1099 | break; | |
1100 | case NETXEN_NIC_XGBE: | |
1101 | mask = 0x77f; | |
1102 | break; | |
1103 | default: | |
1104 | mask = 0x7ff; | |
1105 | break; | |
1106 | } | |
1107 | ||
71bd7877 | 1108 | writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)); |
3d396eb1 AK |
1109 | |
1110 | if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) { | |
1111 | mask = 0xbff; | |
71bd7877 AK |
1112 | writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, |
1113 | ISR_INT_TARGET_MASK)); | |
cb8011ad AK |
1114 | } |
1115 | } | |
1116 | ||
1117 | /* | |
1118 | * NetXen Board information | |
1119 | */ | |
1120 | ||
1121 | #define NETXEN_MAX_SHORT_NAME 16 | |
71bd7877 | 1122 | struct netxen_brdinfo { |
cb8011ad AK |
1123 | netxen_brdtype_t brdtype; /* type of board */ |
1124 | long ports; /* max no of physical ports */ | |
1125 | char short_name[NETXEN_MAX_SHORT_NAME]; | |
71bd7877 | 1126 | }; |
cb8011ad | 1127 | |
71bd7877 | 1128 | static const struct netxen_brdinfo netxen_boards[] = { |
cb8011ad AK |
1129 | {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, |
1130 | {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, | |
1131 | {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, | |
1132 | {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, | |
1133 | {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, | |
1134 | {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, | |
1135 | }; | |
1136 | ||
71bd7877 | 1137 | #define NUM_SUPPORTED_BOARDS (sizeof(netxen_boards)/sizeof(struct netxen_brdinfo)) |
cb8011ad AK |
1138 | |
1139 | static inline void get_brd_port_by_type(u32 type, int *ports) | |
1140 | { | |
1141 | int i, found = 0; | |
1142 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1143 | if (netxen_boards[i].brdtype == type) { | |
1144 | *ports = netxen_boards[i].ports; | |
1145 | found = 1; | |
1146 | break; | |
1147 | } | |
1148 | } | |
1149 | if (!found) | |
1150 | *ports = 0; | |
1151 | } | |
1152 | ||
1153 | static inline void get_brd_name_by_type(u32 type, char *name) | |
1154 | { | |
1155 | int i, found = 0; | |
1156 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1157 | if (netxen_boards[i].brdtype == type) { | |
1158 | strcpy(name, netxen_boards[i].short_name); | |
1159 | found = 1; | |
1160 | break; | |
1161 | } | |
1162 | ||
3d396eb1 | 1163 | } |
cb8011ad AK |
1164 | if (!found) |
1165 | name = "Unknown"; | |
3d396eb1 AK |
1166 | } |
1167 | ||
1168 | int netxen_is_flash_supported(struct netxen_adapter *adapter); | |
1169 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[]); | |
3d396eb1 AK |
1170 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
1171 | extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, | |
1172 | int *valp); | |
1173 | ||
1174 | extern struct ethtool_ops netxen_nic_ethtool_ops; | |
1175 | ||
1176 | #endif /* __NETXEN_NIC_H_ */ |