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3d396eb1 | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
3d396eb1 | 3 | * All rights reserved. |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
5d242f1c DP |
25 | * NetXen Inc, |
26 | * 18922 Forge Drive | |
27 | * Cupertino, CA 95014-0701 | |
28 | * | |
3d396eb1 AK |
29 | */ |
30 | ||
31 | #ifndef _NETXEN_NIC_H_ | |
32 | #define _NETXEN_NIC_H_ | |
33 | ||
3d396eb1 AK |
34 | #include <linux/module.h> |
35 | #include <linux/kernel.h> | |
36 | #include <linux/types.h> | |
3d396eb1 AK |
37 | #include <linux/ioport.h> |
38 | #include <linux/pci.h> | |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/etherdevice.h> | |
41 | #include <linux/ip.h> | |
42 | #include <linux/in.h> | |
43 | #include <linux/tcp.h> | |
44 | #include <linux/skbuff.h> | |
f7185c71 | 45 | #include <linux/firmware.h> |
3d396eb1 AK |
46 | |
47 | #include <linux/ethtool.h> | |
48 | #include <linux/mii.h> | |
3d396eb1 AK |
49 | #include <linux/timer.h> |
50 | ||
42555892 | 51 | #include <linux/vmalloc.h> |
3d396eb1 | 52 | |
3d396eb1 AK |
53 | #include <asm/io.h> |
54 | #include <asm/byteorder.h> | |
3d396eb1 | 55 | |
7d6fd5e7 | 56 | #include "netxen_nic_hdr.h" |
3d396eb1 AK |
57 | #include "netxen_nic_hw.h" |
58 | ||
58735567 DP |
59 | #define _NETXEN_NIC_LINUX_MAJOR 4 |
60 | #define _NETXEN_NIC_LINUX_MINOR 0 | |
c685bfc6 DP |
61 | #define _NETXEN_NIC_LINUX_SUBVERSION 41 |
62 | #define NETXEN_NIC_LINUX_VERSIONID "4.0.41" | |
58735567 | 63 | |
98e31bb0 DP |
64 | #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) |
65 | #define _major(v) (((v) >> 24) & 0xff) | |
66 | #define _minor(v) (((v) >> 16) & 0xff) | |
67 | #define _build(v) ((v) & 0xffff) | |
68 | ||
69 | /* version in image has weird encoding: | |
70 | * 7:0 - major | |
71 | * 15:8 - minor | |
72 | * 31:16 - build (little endian) | |
73 | */ | |
74 | #define NETXEN_DECODE_VERSION(v) \ | |
75 | NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
27d2ab54 | 76 | |
0d04761d MT |
77 | #define NETXEN_NUM_FLASH_SECTORS (64) |
78 | #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024) | |
79 | #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \ | |
80 | * NETXEN_FLASH_SECTOR_SIZE) | |
3d396eb1 | 81 | |
0c25cfe1 LCMT |
82 | #define PHAN_VENDOR_ID 0x4040 |
83 | ||
d8b100c5 DP |
84 | #define RCV_DESC_RINGSIZE(rds_ring) \ |
85 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
86 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
438627c7 | 87 | (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc) |
d8b100c5 DP |
88 | #define STATUS_DESC_RINGSIZE(sds_ring) \ |
89 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
d877f1e3 DP |
90 | #define TX_BUFF_RINGSIZE(tx_ring) \ |
91 | (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc) | |
92 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
93 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
d8b100c5 | 94 | |
ba53e6b4 | 95 | #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) |
3d396eb1 | 96 | |
ed25ffa1 AK |
97 | #define NETXEN_RCV_PRODUCER_OFFSET 0 |
98 | #define NETXEN_RCV_PEG_DB_ID 2 | |
99 | #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 | |
27d2ab54 | 100 | #define FLASH_SUCCESS 0 |
3d396eb1 AK |
101 | |
102 | #define ADDR_IN_WINDOW1(off) \ | |
103 | ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 | |
104 | ||
4790654c JG |
105 | /* |
106 | * normalize a 64MB crb address to 32MB PCI window | |
3d396eb1 AK |
107 | * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 |
108 | */ | |
80922fbc AK |
109 | #define NETXEN_CRB_NORMAL(reg) \ |
110 | ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) | |
cb8011ad | 111 | |
3d396eb1 | 112 | #define NETXEN_CRB_NORMALIZE(adapter, reg) \ |
cb8011ad AK |
113 | pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) |
114 | ||
ed25ffa1 AK |
115 | #define DB_NORMALIZE(adapter, off) \ |
116 | (adapter->ahw.db_base + (off)) | |
117 | ||
118 | #define NX_P2_C0 0x24 | |
119 | #define NX_P2_C1 0x25 | |
e4c93c81 DP |
120 | #define NX_P3_A0 0x30 |
121 | #define NX_P3_A2 0x30 | |
122 | #define NX_P3_B0 0x40 | |
123 | #define NX_P3_B1 0x41 | |
e98e3350 | 124 | #define NX_P3_B2 0x42 |
e4c93c81 DP |
125 | |
126 | #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1) | |
127 | #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0) | |
ed25ffa1 | 128 | |
cb8011ad | 129 | #define FIRST_PAGE_GROUP_START 0 |
ed25ffa1 | 130 | #define FIRST_PAGE_GROUP_END 0x100000 |
cb8011ad | 131 | |
78403a92 MT |
132 | #define SECOND_PAGE_GROUP_START 0x6000000 |
133 | #define SECOND_PAGE_GROUP_END 0x68BC000 | |
cb8011ad AK |
134 | |
135 | #define THIRD_PAGE_GROUP_START 0x70E4000 | |
136 | #define THIRD_PAGE_GROUP_END 0x8000000 | |
137 | ||
138 | #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START | |
139 | #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START | |
140 | #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START | |
3d396eb1 | 141 | |
e4c93c81 DP |
142 | #define P2_MAX_MTU (8000) |
143 | #define P3_MAX_MTU (9600) | |
144 | #define NX_ETHERMTU 1500 | |
145 | #define NX_MAX_ETHERHDR 32 /* This contains some padding */ | |
146 | ||
9b08beba DP |
147 | #define NX_P2_RX_BUF_MAX_LEN 1760 |
148 | #define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU) | |
e4c93c81 DP |
149 | #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU) |
150 | #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU) | |
d9e651bc | 151 | #define NX_CT_DEFAULT_RX_BUF_LEN 2048 |
bc75e5bf | 152 | #define NX_LRO_BUFFER_EXTRA 2048 |
e4c93c81 | 153 | |
9b08beba | 154 | #define NX_RX_LRO_BUFFER_LENGTH (8060) |
3d396eb1 AK |
155 | |
156 | /* | |
157 | * Maximum number of ring contexts | |
158 | */ | |
159 | #define MAX_RING_CTX 1 | |
160 | ||
161 | /* Opcodes to be used with the commands */ | |
e4c93c81 DP |
162 | #define TX_ETHER_PKT 0x01 |
163 | #define TX_TCP_PKT 0x02 | |
164 | #define TX_UDP_PKT 0x03 | |
165 | #define TX_IP_PKT 0x04 | |
166 | #define TX_TCP_LSO 0x05 | |
167 | #define TX_TCP_LSO6 0x06 | |
168 | #define TX_IPSEC 0x07 | |
169 | #define TX_IPSEC_CMD 0x0a | |
170 | #define TX_TCPV6_PKT 0x0b | |
171 | #define TX_UDPV6_PKT 0x0c | |
3d396eb1 AK |
172 | |
173 | /* The following opcodes are for internal consumption. */ | |
174 | #define NETXEN_CONTROL_OP 0x10 | |
175 | #define PEGNET_REQUEST 0x11 | |
176 | ||
177 | #define MAX_NUM_CARDS 4 | |
178 | ||
179 | #define MAX_BUFFERS_PER_CMD 32 | |
cb2107be | 180 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4) |
3d396eb1 AK |
181 | |
182 | /* | |
183 | * Following are the states of the Phantom. Phantom will set them and | |
184 | * Host will read to check if the fields are correct. | |
185 | */ | |
186 | #define PHAN_INITIALIZE_START 0xff00 | |
187 | #define PHAN_INITIALIZE_FAILED 0xffff | |
188 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
189 | ||
190 | /* Host writes the following to notify that it has done the init-handshake */ | |
191 | #define PHAN_INITIALIZE_ACK 0xf00f | |
192 | ||
d8b100c5 DP |
193 | #define NUM_RCV_DESC_RINGS 3 |
194 | #define NUM_STS_DESC_RINGS 4 | |
3d396eb1 | 195 | |
438627c7 DP |
196 | #define RCV_RING_NORMAL 0 |
197 | #define RCV_RING_JUMBO 1 | |
198 | #define RCV_RING_LRO 2 | |
3d396eb1 | 199 | |
24767ab1 DP |
200 | #define MIN_CMD_DESCRIPTORS 64 |
201 | #define MIN_RCV_DESCRIPTORS 64 | |
202 | #define MIN_JUMBO_DESCRIPTORS 32 | |
203 | ||
204 | #define MAX_CMD_DESCRIPTORS 1024 | |
205 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
206 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
207 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 | |
208 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
32ec8033 | 209 | #define MAX_LRO_RCV_DESCRIPTORS 8 |
24767ab1 DP |
210 | |
211 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
212 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
213 | ||
ed25ffa1 | 214 | #define NETXEN_CTX_SIGNATURE 0xdee0 |
f6d21f44 DP |
215 | #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0 |
216 | #define NETXEN_CTX_RESET 0xbad0 | |
cf981ffb | 217 | #define NETXEN_CTX_D3_RESET 0xacc0 |
ed25ffa1 | 218 | #define NETXEN_RCV_PRODUCER(ringid) (ringid) |
3d396eb1 AK |
219 | |
220 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
221 | #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 | |
222 | ||
223 | #define get_next_index(index, length) \ | |
224 | (((index) + 1) & ((length) - 1)) | |
225 | ||
226 | #define get_index_range(index,length,count) \ | |
227 | (((index) + (count)) & ((length) - 1)) | |
228 | ||
ed25ffa1 | 229 | #define MPORT_SINGLE_FUNCTION_MODE 0x1111 |
3176ff3e | 230 | #define MPORT_MULTI_FUNCTION_MODE 0x2222 |
ed25ffa1 | 231 | |
ed25ffa1 AK |
232 | /* |
233 | * NetXen host-peg signal message structure | |
234 | * | |
235 | * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx | |
236 | * Bit 2 : priv_id => must be 1 | |
237 | * Bit 3-17 : count => for doorbell | |
238 | * Bit 18-27 : ctx_id => Context id | |
239 | * Bit 28-31 : opcode | |
240 | */ | |
241 | ||
242 | typedef u32 netxen_ctx_msg; | |
243 | ||
ed25ffa1 | 244 | #define netxen_set_msg_peg_id(config_word, val) \ |
a608ab9c | 245 | ((config_word) &= ~3, (config_word) |= val & 3) |
ed25ffa1 | 246 | #define netxen_set_msg_privid(config_word) \ |
a608ab9c | 247 | ((config_word) |= 1 << 2) |
ed25ffa1 | 248 | #define netxen_set_msg_count(config_word, val) \ |
a608ab9c | 249 | ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) |
ed25ffa1 | 250 | #define netxen_set_msg_ctxid(config_word, val) \ |
a608ab9c | 251 | ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) |
ed25ffa1 | 252 | #define netxen_set_msg_opcode(config_word, val) \ |
82581174 | 253 | ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) |
ed25ffa1 | 254 | |
f6d21f44 DP |
255 | struct netxen_rcv_ring { |
256 | __le64 addr; | |
257 | __le32 size; | |
a608ab9c | 258 | __le32 rsrvd; |
ed25ffa1 AK |
259 | }; |
260 | ||
f6d21f44 DP |
261 | struct netxen_sts_ring { |
262 | __le64 addr; | |
263 | __le32 size; | |
264 | __le16 msi_index; | |
265 | __le16 rsvd; | |
266 | } ; | |
267 | ||
ed25ffa1 AK |
268 | struct netxen_ring_ctx { |
269 | ||
270 | /* one command ring */ | |
a608ab9c AV |
271 | __le64 cmd_consumer_offset; |
272 | __le64 cmd_ring_addr; | |
273 | __le32 cmd_ring_size; | |
274 | __le32 rsrvd; | |
ed25ffa1 AK |
275 | |
276 | /* three receive rings */ | |
f6d21f44 | 277 | struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS]; |
ed25ffa1 | 278 | |
a608ab9c AV |
279 | __le64 sts_ring_addr; |
280 | __le32 sts_ring_size; | |
ed25ffa1 | 281 | |
a608ab9c | 282 | __le32 ctx_id; |
f6d21f44 DP |
283 | |
284 | __le64 rsrvd_2[3]; | |
285 | __le32 sts_ring_count; | |
286 | __le32 rsrvd_3; | |
287 | struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS]; | |
288 | ||
ed25ffa1 AK |
289 | } __attribute__ ((aligned(64))); |
290 | ||
3d396eb1 AK |
291 | /* |
292 | * Following data structures describe the descriptors that will be used. | |
293 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
294 | * we are doing LSO (above the 1500 size packet) only. | |
295 | */ | |
296 | ||
297 | /* | |
298 | * The size of reference handle been changed to 16 bits to pass the MSS fields | |
299 | * for the LSO packet | |
300 | */ | |
301 | ||
302 | #define FLAGS_CHECKSUM_ENABLED 0x01 | |
303 | #define FLAGS_LSO_ENABLED 0x02 | |
304 | #define FLAGS_IPSEC_SA_ADD 0x04 | |
305 | #define FLAGS_IPSEC_SA_DELETE 0x08 | |
306 | #define FLAGS_VLAN_TAGGED 0x10 | |
028afe71 DP |
307 | #define FLAGS_VLAN_OOB 0x40 |
308 | ||
309 | #define netxen_set_tx_vlan_tci(cmd_desc, v) \ | |
310 | (cmd_desc)->vlan_TCI = cpu_to_le16(v); | |
3d396eb1 | 311 | |
ed25ffa1 AK |
312 | #define netxen_set_cmd_desc_port(cmd_desc, var) \ |
313 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
6c80b18d | 314 | #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \ |
48bfd1e0 | 315 | ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) |
3d396eb1 | 316 | |
391587c3 DP |
317 | #define netxen_set_tx_port(_desc, _port) \ |
318 | (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0) | |
319 | ||
320 | #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \ | |
321 | (_desc)->flags_opcode = \ | |
322 | cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)) | |
323 | ||
324 | #define netxen_set_tx_frags_len(_desc, _frags, _len) \ | |
1bcfd790 | 325 | (_desc)->nfrags__length = \ |
391587c3 | 326 | cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)) |
3d396eb1 AK |
327 | |
328 | struct cmd_desc_type0 { | |
ed25ffa1 AK |
329 | u8 tcp_hdr_offset; /* For LSO only */ |
330 | u8 ip_hdr_offset; /* For LSO only */ | |
1bcfd790 DP |
331 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ |
332 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
333 | ||
334 | __le64 addr_buffer2; | |
335 | ||
336 | __le16 reference_handle; | |
337 | __le16 mss; | |
338 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
3d396eb1 | 339 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ |
a608ab9c | 340 | __le16 conn_id; /* IPSec offoad only */ |
3d396eb1 | 341 | |
1bcfd790 DP |
342 | __le64 addr_buffer3; |
343 | __le64 addr_buffer1; | |
3d396eb1 | 344 | |
d32cc3d2 | 345 | __le16 buffer_length[4]; |
3d396eb1 | 346 | |
1bcfd790 | 347 | __le64 addr_buffer4; |
3d396eb1 | 348 | |
028afe71 DP |
349 | __le16 vlan_TCI; |
350 | __le16 reserved; | |
351 | __le32 reserved2; | |
ed25ffa1 | 352 | |
3d396eb1 AK |
353 | } __attribute__ ((aligned(64))); |
354 | ||
355 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
356 | struct rcv_desc { | |
a608ab9c AV |
357 | __le16 reference_handle; |
358 | __le16 reserved; | |
359 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
360 | __le64 addr_buffer; | |
3d396eb1 AK |
361 | }; |
362 | ||
363 | /* opcode field in status_desc */ | |
6598b169 | 364 | #define NETXEN_NIC_SYN_OFFLOAD 0x03 |
d9e651bc DP |
365 | #define NETXEN_NIC_RXPKT_DESC 0x04 |
366 | #define NETXEN_OLD_RXPKT_DESC 0x3f | |
3bf26ce3 | 367 | #define NETXEN_NIC_RESPONSE_DESC 0x05 |
c1c00ab8 | 368 | #define NETXEN_NIC_LRO_DESC 0x12 |
3d396eb1 AK |
369 | |
370 | /* for status field in status_desc */ | |
371 | #define STATUS_NEED_CKSUM (1) | |
372 | #define STATUS_CKSUM_OK (2) | |
373 | ||
374 | /* owner bits of status_desc */ | |
0ddc110c DP |
375 | #define STATUS_OWNER_HOST (0x1ULL << 56) |
376 | #define STATUS_OWNER_PHANTOM (0x2ULL << 56) | |
3d396eb1 | 377 | |
3bf26ce3 DP |
378 | /* Status descriptor: |
379 | 0-3 port, 4-7 status, 8-11 type, 12-27 total_length | |
380 | 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset | |
381 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode | |
382 | */ | |
5dc16268 DP |
383 | #define netxen_get_sts_port(sts_data) \ |
384 | ((sts_data) & 0x0F) | |
385 | #define netxen_get_sts_status(sts_data) \ | |
386 | (((sts_data) >> 4) & 0x0F) | |
387 | #define netxen_get_sts_type(sts_data) \ | |
388 | (((sts_data) >> 8) & 0x0F) | |
389 | #define netxen_get_sts_totallength(sts_data) \ | |
390 | (((sts_data) >> 12) & 0xFFFF) | |
391 | #define netxen_get_sts_refhandle(sts_data) \ | |
392 | (((sts_data) >> 28) & 0xFFFF) | |
393 | #define netxen_get_sts_prot(sts_data) \ | |
394 | (((sts_data) >> 44) & 0x0F) | |
d9e651bc DP |
395 | #define netxen_get_sts_pkt_offset(sts_data) \ |
396 | (((sts_data) >> 48) & 0x1F) | |
3bf26ce3 DP |
397 | #define netxen_get_sts_desc_cnt(sts_data) \ |
398 | (((sts_data) >> 53) & 0x7) | |
5dc16268 DP |
399 | #define netxen_get_sts_opcode(sts_data) \ |
400 | (((sts_data) >> 58) & 0x03F) | |
401 | ||
c1c00ab8 DP |
402 | #define netxen_get_lro_sts_refhandle(sts_data) \ |
403 | ((sts_data) & 0x0FFFF) | |
404 | #define netxen_get_lro_sts_length(sts_data) \ | |
405 | (((sts_data) >> 16) & 0x0FFFF) | |
406 | #define netxen_get_lro_sts_l2_hdr_offset(sts_data) \ | |
407 | (((sts_data) >> 32) & 0x0FF) | |
408 | #define netxen_get_lro_sts_l4_hdr_offset(sts_data) \ | |
409 | (((sts_data) >> 40) & 0x0FF) | |
410 | #define netxen_get_lro_sts_timestamp(sts_data) \ | |
411 | (((sts_data) >> 48) & 0x1) | |
412 | #define netxen_get_lro_sts_type(sts_data) \ | |
413 | (((sts_data) >> 49) & 0x7) | |
414 | #define netxen_get_lro_sts_push_flag(sts_data) \ | |
415 | (((sts_data) >> 52) & 0x1) | |
416 | #define netxen_get_lro_sts_seq_number(sts_data) \ | |
417 | ((sts_data) & 0x0FFFFFFFF) | |
418 | ||
419 | ||
3d396eb1 | 420 | struct status_desc { |
3bf26ce3 | 421 | __le64 status_desc_data[2]; |
6c80b18d | 422 | } __attribute__ ((aligned(16))); |
3d396eb1 | 423 | |
3d396eb1 AK |
424 | /* The version of the main data structure */ |
425 | #define NETXEN_BDINFO_VERSION 1 | |
426 | ||
427 | /* Magic number to let user know flash is programmed */ | |
428 | #define NETXEN_BDINFO_MAGIC 0x12345678 | |
429 | ||
430 | /* Max number of Gig ports on a Phantom board */ | |
431 | #define NETXEN_MAX_PORTS 4 | |
432 | ||
e98e3350 DP |
433 | #define NETXEN_BRDTYPE_P1_BD 0x0000 |
434 | #define NETXEN_BRDTYPE_P1_SB 0x0001 | |
435 | #define NETXEN_BRDTYPE_P1_SMAX 0x0002 | |
436 | #define NETXEN_BRDTYPE_P1_SOCK 0x0003 | |
437 | ||
438 | #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008 | |
439 | #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009 | |
440 | #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a | |
441 | #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b | |
442 | #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c | |
443 | ||
444 | #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d | |
445 | #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e | |
446 | #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f | |
447 | ||
448 | #define NETXEN_BRDTYPE_P3_REF_QG 0x0021 | |
449 | #define NETXEN_BRDTYPE_P3_HMEZ 0x0022 | |
450 | #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023 | |
451 | #define NETXEN_BRDTYPE_P3_4_GB 0x0024 | |
452 | #define NETXEN_BRDTYPE_P3_IMEZ 0x0025 | |
453 | #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026 | |
454 | #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027 | |
455 | #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028 | |
456 | #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029 | |
457 | #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a | |
458 | #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b | |
459 | #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031 | |
460 | #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032 | |
461 | #define NETXEN_BRDTYPE_P3_10G_TP 0x0080 | |
3d396eb1 | 462 | |
3d396eb1 | 463 | /* Flash memory map */ |
e98e3350 DP |
464 | #define NETXEN_CRBINIT_START 0 /* crbinit section */ |
465 | #define NETXEN_BRDCFG_START 0x4000 /* board config */ | |
466 | #define NETXEN_INITCODE_START 0x6000 /* pegtune code */ | |
467 | #define NETXEN_BOOTLD_START 0x10000 /* bootld */ | |
468 | #define NETXEN_IMAGE_START 0x43000 /* compressed image */ | |
469 | #define NETXEN_SECONDARY_START 0x200000 /* backup images */ | |
470 | #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */ | |
471 | #define NETXEN_USER_START 0x3E8000 /* Firmare info */ | |
472 | #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */ | |
06db58c0 | 473 | #define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */ |
3d396eb1 | 474 | |
06db58c0 | 475 | #define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START) |
ba599d4f DP |
476 | #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408) |
477 | #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c) | |
06db58c0 DP |
478 | #define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418) |
479 | #define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c) | |
ba599d4f | 480 | #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c) |
06db58c0 DP |
481 | |
482 | #define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START) | |
483 | #define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8) | |
ba599d4f | 484 | #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128) |
06db58c0 | 485 | |
ba599d4f | 486 | #define NX_FW_MIN_SIZE (0x3fffff) |
bd257ed9 DP |
487 | #define NX_P2_MN_ROMIMAGE 0 |
488 | #define NX_P3_CT_ROMIMAGE 1 | |
489 | #define NX_P3_MN_ROMIMAGE 2 | |
67c38fc6 | 490 | #define NX_FLASH_ROMIMAGE 3 |
ba599d4f | 491 | |
ed25ffa1 | 492 | extern char netxen_nic_driver_name[]; |
3d396eb1 | 493 | |
3d396eb1 | 494 | /* Number of status descriptors to handle per interrupt */ |
d8b100c5 | 495 | #define MAX_STATUS_HANDLE (64) |
3d396eb1 AK |
496 | |
497 | /* | |
498 | * netxen_skb_frag{} is to contain mapping info for each SG list. This | |
499 | * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. | |
500 | */ | |
501 | struct netxen_skb_frag { | |
502 | u64 dma; | |
d877f1e3 | 503 | u64 length; |
3d396eb1 AK |
504 | }; |
505 | ||
7d6fd5e7 DP |
506 | struct netxen_recv_crb { |
507 | u32 crb_rcv_producer[NUM_RCV_DESC_RINGS]; | |
508 | u32 crb_sts_consumer[NUM_STS_DESC_RINGS]; | |
509 | u32 sw_int_mask[NUM_STS_DESC_RINGS]; | |
510 | }; | |
6c80b18d | 511 | |
3d396eb1 AK |
512 | /* Following defines are for the state of the buffers */ |
513 | #define NETXEN_BUFFER_FREE 0 | |
514 | #define NETXEN_BUFFER_BUSY 1 | |
515 | ||
516 | /* | |
517 | * There will be one netxen_buffer per skb packet. These will be | |
518 | * used to save the dma info for pci_unmap_page() | |
519 | */ | |
520 | struct netxen_cmd_buffer { | |
521 | struct sk_buff *skb; | |
522 | struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; | |
391587c3 | 523 | u32 frag_count; |
3d396eb1 AK |
524 | }; |
525 | ||
526 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
527 | struct netxen_rx_buffer { | |
d9e651bc | 528 | struct list_head list; |
3d396eb1 AK |
529 | struct sk_buff *skb; |
530 | u64 dma; | |
531 | u16 ref_handle; | |
532 | u16 state; | |
533 | }; | |
534 | ||
535 | /* Board types */ | |
536 | #define NETXEN_NIC_GBE 0x01 | |
537 | #define NETXEN_NIC_XGBE 0x02 | |
538 | ||
539 | /* | |
540 | * One hardware_context{} per adapter | |
541 | * contains interrupt info as well shared hardware info. | |
542 | */ | |
543 | struct netxen_hardware_context { | |
cb8011ad AK |
544 | void __iomem *pci_base0; |
545 | void __iomem *pci_base1; | |
546 | void __iomem *pci_base2; | |
ed25ffa1 AK |
547 | void __iomem *db_base; |
548 | unsigned long db_len; | |
3ce06a32 DP |
549 | unsigned long pci_len0; |
550 | ||
551 | int qdr_sn_window; | |
552 | int ddr_mn_window; | |
553 | unsigned long mn_win_crb; | |
554 | unsigned long ms_win_crb; | |
cb8011ad | 555 | |
1e2d0059 | 556 | u8 cut_through; |
3d396eb1 | 557 | u8 revision_id; |
1b1f7898 DP |
558 | u8 pci_func; |
559 | u8 linkup; | |
1e2d0059 | 560 | u16 port_type; |
1b1f7898 | 561 | u16 board_type; |
3d396eb1 AK |
562 | }; |
563 | ||
564 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ | |
565 | #define ETHERNET_FCS_SIZE 4 | |
566 | ||
567 | struct netxen_adapter_stats { | |
3176ff3e | 568 | u64 xmitcalled; |
3176ff3e | 569 | u64 xmitfinished; |
d1847a72 | 570 | u64 rxdropped; |
3176ff3e | 571 | u64 txdropped; |
3176ff3e | 572 | u64 csummed; |
1bb482f8 NK |
573 | u64 rx_pkts; |
574 | u64 lro_pkts; | |
3176ff3e MT |
575 | u64 rxbytes; |
576 | u64 txbytes; | |
3d396eb1 AK |
577 | }; |
578 | ||
579 | /* | |
580 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
581 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
582 | */ | |
48bfd1e0 | 583 | struct nx_host_rds_ring { |
3d396eb1 | 584 | u32 producer; |
d8b100c5 | 585 | u32 crb_rcv_producer; |
438627c7 DP |
586 | u32 num_desc; |
587 | u32 dma_size; | |
588 | u32 skb_size; | |
589 | u32 flags; | |
d8b100c5 DP |
590 | struct rcv_desc *desc_head; |
591 | struct netxen_rx_buffer *rx_buf_arr; | |
592 | struct list_head free_list; | |
593 | spinlock_t lock; | |
438627c7 | 594 | dma_addr_t phys_addr; |
3d396eb1 AK |
595 | }; |
596 | ||
d8b100c5 DP |
597 | struct nx_host_sds_ring { |
598 | u32 consumer; | |
599 | u32 crb_sts_consumer; | |
600 | u32 crb_intr_mask; | |
601 | u32 num_desc; | |
602 | ||
603 | struct status_desc *desc_head; | |
604 | struct netxen_adapter *adapter; | |
605 | struct napi_struct napi; | |
606 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
607 | ||
d8b100c5 DP |
608 | int irq; |
609 | ||
610 | dma_addr_t phys_addr; | |
611 | char name[IFNAMSIZ+4]; | |
612 | }; | |
613 | ||
d877f1e3 DP |
614 | struct nx_host_tx_ring { |
615 | u32 producer; | |
616 | __le32 *hw_consumer; | |
617 | u32 sw_consumer; | |
618 | u32 crb_cmd_producer; | |
619 | u32 crb_cmd_consumer; | |
620 | u32 num_desc; | |
621 | ||
b2af9cb0 DP |
622 | struct netdev_queue *txq; |
623 | ||
d877f1e3 DP |
624 | struct netxen_cmd_buffer *cmd_buf_arr; |
625 | struct cmd_desc_type0 *desc_head; | |
626 | dma_addr_t phys_addr; | |
627 | }; | |
628 | ||
3d396eb1 AK |
629 | /* |
630 | * Receive context. There is one such structure per instance of the | |
631 | * receive processing. Any state information that is relevant to | |
632 | * the receive, and is must be in this structure. The global data may be | |
633 | * present elsewhere. | |
634 | */ | |
635 | struct netxen_recv_context { | |
48bfd1e0 DP |
636 | u32 state; |
637 | u16 context_id; | |
638 | u16 virt_port; | |
639 | ||
4ea528a1 | 640 | struct nx_host_rds_ring *rds_rings; |
71dcddbd | 641 | struct nx_host_sds_ring *sds_rings; |
4ea528a1 DP |
642 | |
643 | struct netxen_ring_ctx *hwctx; | |
644 | dma_addr_t phys_addr; | |
3d396eb1 AK |
645 | }; |
646 | ||
48bfd1e0 DP |
647 | /* New HW context creation */ |
648 | ||
649 | #define NX_OS_CRB_RETRY_COUNT 4000 | |
650 | #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \ | |
651 | (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) | |
652 | ||
653 | #define NX_CDRP_CLEAR 0x00000000 | |
654 | #define NX_CDRP_CMD_BIT 0x80000000 | |
655 | ||
656 | /* | |
657 | * All responses must have the NX_CDRP_CMD_BIT cleared | |
658 | * in the crb NX_CDRP_CRB_OFFSET. | |
659 | */ | |
660 | #define NX_CDRP_FORM_RSP(rsp) (rsp) | |
661 | #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0) | |
662 | ||
663 | #define NX_CDRP_RSP_OK 0x00000001 | |
664 | #define NX_CDRP_RSP_FAIL 0x00000002 | |
665 | #define NX_CDRP_RSP_TIMEOUT 0x00000003 | |
666 | ||
667 | /* | |
668 | * All commands must have the NX_CDRP_CMD_BIT set in | |
669 | * the crb NX_CDRP_CRB_OFFSET. | |
670 | */ | |
671 | #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd)) | |
672 | #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0) | |
673 | ||
674 | #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 | |
675 | #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 | |
676 | #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 | |
677 | #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 | |
678 | #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 | |
679 | #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 | |
680 | #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007 | |
681 | #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008 | |
682 | #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009 | |
683 | #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a | |
684 | #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e | |
685 | #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f | |
686 | #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010 | |
687 | #define NX_CDRP_CMD_SET_MTU 0x00000012 | |
3ad4467c DP |
688 | #define NX_CDRP_CMD_READ_PHY 0x00000013 |
689 | #define NX_CDRP_CMD_WRITE_PHY 0x00000014 | |
690 | #define NX_CDRP_CMD_READ_HW_REG 0x00000015 | |
691 | #define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016 | |
692 | #define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017 | |
693 | #define NX_CDRP_CMD_READ_MAX_MTU 0x00000018 | |
694 | #define NX_CDRP_CMD_READ_MAX_LRO 0x00000019 | |
695 | #define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a | |
696 | #define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b | |
697 | #define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c | |
698 | #define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d | |
699 | #define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e | |
700 | #define NX_CDRP_CMD_MAX 0x0000001f | |
48bfd1e0 DP |
701 | |
702 | #define NX_RCODE_SUCCESS 0 | |
703 | #define NX_RCODE_NO_HOST_MEM 1 | |
704 | #define NX_RCODE_NO_HOST_RESOURCE 2 | |
705 | #define NX_RCODE_NO_CARD_CRB 3 | |
706 | #define NX_RCODE_NO_CARD_MEM 4 | |
707 | #define NX_RCODE_NO_CARD_RESOURCE 5 | |
708 | #define NX_RCODE_INVALID_ARGS 6 | |
709 | #define NX_RCODE_INVALID_ACTION 7 | |
710 | #define NX_RCODE_INVALID_STATE 8 | |
711 | #define NX_RCODE_NOT_SUPPORTED 9 | |
712 | #define NX_RCODE_NOT_PERMITTED 10 | |
713 | #define NX_RCODE_NOT_READY 11 | |
714 | #define NX_RCODE_DOES_NOT_EXIST 12 | |
715 | #define NX_RCODE_ALREADY_EXISTS 13 | |
716 | #define NX_RCODE_BAD_SIGNATURE 14 | |
717 | #define NX_RCODE_CMD_NOT_IMPL 15 | |
718 | #define NX_RCODE_CMD_INVALID 16 | |
719 | #define NX_RCODE_TIMEOUT 17 | |
720 | #define NX_RCODE_CMD_FAILED 18 | |
721 | #define NX_RCODE_MAX_EXCEEDED 19 | |
722 | #define NX_RCODE_MAX 20 | |
723 | ||
724 | #define NX_DESTROY_CTX_RESET 0 | |
725 | #define NX_DESTROY_CTX_D3_RESET 1 | |
726 | #define NX_DESTROY_CTX_MAX 2 | |
727 | ||
728 | /* | |
729 | * Capabilities | |
730 | */ | |
731 | #define NX_CAP_BIT(class, bit) (1 << bit) | |
732 | #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0) | |
733 | #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1) | |
734 | #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2) | |
735 | #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3) | |
736 | #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4) | |
737 | #define NX_CAP0_LRO NX_CAP_BIT(0, 5) | |
738 | #define NX_CAP0_LSO NX_CAP_BIT(0, 6) | |
739 | #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7) | |
740 | #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8) | |
c1c00ab8 | 741 | #define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10) |
48bfd1e0 DP |
742 | |
743 | /* | |
744 | * Context state | |
745 | */ | |
746 | #define NX_HOST_CTX_STATE_FREED 0 | |
747 | #define NX_HOST_CTX_STATE_ALLOCATED 1 | |
748 | #define NX_HOST_CTX_STATE_ACTIVE 2 | |
749 | #define NX_HOST_CTX_STATE_DISABLED 3 | |
750 | #define NX_HOST_CTX_STATE_QUIESCED 4 | |
751 | #define NX_HOST_CTX_STATE_MAX 5 | |
752 | ||
753 | /* | |
754 | * Rx context | |
755 | */ | |
756 | ||
757 | typedef struct { | |
2edbb454 DP |
758 | __le64 host_phys_addr; /* Ring base addr */ |
759 | __le32 ring_size; /* Ring entries */ | |
760 | __le16 msi_index; | |
761 | __le16 rsvd; /* Padding */ | |
48bfd1e0 DP |
762 | } nx_hostrq_sds_ring_t; |
763 | ||
764 | typedef struct { | |
2edbb454 DP |
765 | __le64 host_phys_addr; /* Ring base addr */ |
766 | __le64 buff_size; /* Packet buffer size */ | |
767 | __le32 ring_size; /* Ring entries */ | |
768 | __le32 ring_kind; /* Class of ring */ | |
48bfd1e0 DP |
769 | } nx_hostrq_rds_ring_t; |
770 | ||
771 | typedef struct { | |
2edbb454 DP |
772 | __le64 host_rsp_dma_addr; /* Response dma'd here */ |
773 | __le32 capabilities[4]; /* Flag bit vector */ | |
774 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
775 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
48bfd1e0 | 776 | /* These ring offsets are relative to data[0] below */ |
2edbb454 DP |
777 | __le32 rds_ring_offset; /* Offset to RDS config */ |
778 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
779 | __le16 num_rds_rings; /* Count of RDS rings */ | |
780 | __le16 num_sds_rings; /* Count of SDS rings */ | |
781 | __le16 rsvd1; /* Padding */ | |
782 | __le16 rsvd2; /* Padding */ | |
48bfd1e0 DP |
783 | u8 reserved[128]; /* reserve space for future expansion*/ |
784 | /* MUST BE 64-bit aligned. | |
785 | The following is packed: | |
786 | - N hostrq_rds_rings | |
787 | - N hostrq_sds_rings */ | |
788 | char data[0]; | |
789 | } nx_hostrq_rx_ctx_t; | |
790 | ||
791 | typedef struct { | |
2edbb454 DP |
792 | __le32 host_producer_crb; /* Crb to use */ |
793 | __le32 rsvd1; /* Padding */ | |
48bfd1e0 DP |
794 | } nx_cardrsp_rds_ring_t; |
795 | ||
796 | typedef struct { | |
2edbb454 DP |
797 | __le32 host_consumer_crb; /* Crb to use */ |
798 | __le32 interrupt_crb; /* Crb to use */ | |
48bfd1e0 DP |
799 | } nx_cardrsp_sds_ring_t; |
800 | ||
801 | typedef struct { | |
802 | /* These ring offsets are relative to data[0] below */ | |
2edbb454 DP |
803 | __le32 rds_ring_offset; /* Offset to RDS config */ |
804 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
805 | __le32 host_ctx_state; /* Starting State */ | |
806 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
807 | __le16 num_rds_rings; /* Count of RDS rings */ | |
808 | __le16 num_sds_rings; /* Count of SDS rings */ | |
809 | __le16 context_id; /* Handle for context */ | |
48bfd1e0 DP |
810 | u8 phys_port; /* Physical id of port */ |
811 | u8 virt_port; /* Virtual/Logical id of port */ | |
812 | u8 reserved[128]; /* save space for future expansion */ | |
813 | /* MUST BE 64-bit aligned. | |
814 | The following is packed: | |
815 | - N cardrsp_rds_rings | |
816 | - N cardrs_sds_rings */ | |
817 | char data[0]; | |
818 | } nx_cardrsp_rx_ctx_t; | |
819 | ||
820 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
821 | (sizeof(HOSTRQ_RX) + \ | |
822 | (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \ | |
823 | (sds_rings)*(sizeof(nx_hostrq_sds_ring_t))) | |
824 | ||
825 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
826 | (sizeof(CARDRSP_RX) + \ | |
827 | (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \ | |
828 | (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t))) | |
829 | ||
830 | /* | |
831 | * Tx context | |
832 | */ | |
833 | ||
834 | typedef struct { | |
2edbb454 DP |
835 | __le64 host_phys_addr; /* Ring base addr */ |
836 | __le32 ring_size; /* Ring entries */ | |
837 | __le32 rsvd; /* Padding */ | |
48bfd1e0 DP |
838 | } nx_hostrq_cds_ring_t; |
839 | ||
840 | typedef struct { | |
2edbb454 DP |
841 | __le64 host_rsp_dma_addr; /* Response dma'd here */ |
842 | __le64 cmd_cons_dma_addr; /* */ | |
843 | __le64 dummy_dma_addr; /* */ | |
844 | __le32 capabilities[4]; /* Flag bit vector */ | |
845 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
846 | __le32 rsvd1; /* Padding */ | |
847 | __le16 rsvd2; /* Padding */ | |
848 | __le16 interrupt_ctl; | |
849 | __le16 msi_index; | |
850 | __le16 rsvd3; /* Padding */ | |
48bfd1e0 DP |
851 | nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */ |
852 | u8 reserved[128]; /* future expansion */ | |
853 | } nx_hostrq_tx_ctx_t; | |
854 | ||
855 | typedef struct { | |
2edbb454 DP |
856 | __le32 host_producer_crb; /* Crb to use */ |
857 | __le32 interrupt_crb; /* Crb to use */ | |
48bfd1e0 DP |
858 | } nx_cardrsp_cds_ring_t; |
859 | ||
860 | typedef struct { | |
2edbb454 DP |
861 | __le32 host_ctx_state; /* Starting state */ |
862 | __le16 context_id; /* Handle for context */ | |
48bfd1e0 DP |
863 | u8 phys_port; /* Physical id of port */ |
864 | u8 virt_port; /* Virtual/Logical id of port */ | |
865 | nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */ | |
866 | u8 reserved[128]; /* future expansion */ | |
867 | } nx_cardrsp_tx_ctx_t; | |
868 | ||
869 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
870 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
871 | ||
872 | /* CRB */ | |
873 | ||
874 | #define NX_HOST_RDS_CRB_MODE_UNIQUE 0 | |
875 | #define NX_HOST_RDS_CRB_MODE_SHARED 1 | |
876 | #define NX_HOST_RDS_CRB_MODE_CUSTOM 2 | |
877 | #define NX_HOST_RDS_CRB_MODE_MAX 3 | |
878 | ||
879 | #define NX_HOST_INT_CRB_MODE_UNIQUE 0 | |
880 | #define NX_HOST_INT_CRB_MODE_SHARED 1 | |
881 | #define NX_HOST_INT_CRB_MODE_NORX 2 | |
882 | #define NX_HOST_INT_CRB_MODE_NOTX 3 | |
883 | #define NX_HOST_INT_CRB_MODE_NORXTX 4 | |
884 | ||
885 | ||
886 | /* MAC */ | |
887 | ||
888 | #define MC_COUNT_P2 16 | |
889 | #define MC_COUNT_P3 38 | |
890 | ||
891 | #define NETXEN_MAC_NOOP 0 | |
892 | #define NETXEN_MAC_ADD 1 | |
893 | #define NETXEN_MAC_DEL 2 | |
894 | ||
895 | typedef struct nx_mac_list_s { | |
5cf4d323 DP |
896 | struct list_head list; |
897 | uint8_t mac_addr[ETH_ALEN+2]; | |
48bfd1e0 DP |
898 | } nx_mac_list_t; |
899 | ||
cd1f8160 DP |
900 | /* |
901 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
902 | * adjusted based on configured MTU. | |
903 | */ | |
904 | #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3 | |
905 | #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256 | |
906 | #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64 | |
907 | #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4 | |
908 | ||
909 | #define NETXEN_NIC_INTR_DEFAULT 0x04 | |
910 | ||
911 | typedef union { | |
912 | struct { | |
913 | uint16_t rx_packets; | |
914 | uint16_t rx_time_us; | |
915 | uint16_t tx_packets; | |
916 | uint16_t tx_time_us; | |
917 | } data; | |
918 | uint64_t word; | |
919 | } nx_nic_intr_coalesce_data_t; | |
920 | ||
921 | typedef struct { | |
922 | uint16_t stats_time_us; | |
923 | uint16_t rate_sample_time; | |
924 | uint16_t flags; | |
925 | uint16_t rsvd_1; | |
926 | uint32_t low_threshold; | |
927 | uint32_t high_threshold; | |
928 | nx_nic_intr_coalesce_data_t normal; | |
929 | nx_nic_intr_coalesce_data_t low; | |
930 | nx_nic_intr_coalesce_data_t high; | |
931 | nx_nic_intr_coalesce_data_t irq; | |
932 | } nx_nic_intr_coalesce_t; | |
933 | ||
9ad27643 DP |
934 | #define NX_HOST_REQUEST 0x13 |
935 | #define NX_NIC_REQUEST 0x14 | |
936 | ||
937 | #define NX_MAC_EVENT 0x1 | |
938 | ||
6598b169 DP |
939 | #define NX_IP_UP 2 |
940 | #define NX_IP_DOWN 3 | |
941 | ||
e98e3350 DP |
942 | /* |
943 | * Driver --> Firmware | |
944 | */ | |
945 | #define NX_NIC_H2C_OPCODE_START 0 | |
946 | #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1 | |
947 | #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2 | |
948 | #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3 | |
949 | #define NX_NIC_H2C_OPCODE_CONFIG_LED 4 | |
950 | #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5 | |
951 | #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6 | |
952 | #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7 | |
953 | #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8 | |
954 | #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9 | |
955 | #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10 | |
956 | #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11 | |
957 | #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12 | |
958 | #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13 | |
959 | #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14 | |
960 | #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15 | |
961 | #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16 | |
962 | #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17 | |
963 | #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18 | |
964 | #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19 | |
965 | #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20 | |
966 | #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21 | |
967 | #define NX_NIC_C2C_OPCODE 22 | |
fa3ce355 | 968 | #define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23 |
1bb482f8 NK |
969 | #define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24 |
970 | #define NX_NIC_H2C_OPCODE_LAST 25 | |
e98e3350 DP |
971 | |
972 | /* | |
973 | * Firmware --> Driver | |
974 | */ | |
975 | ||
976 | #define NX_NIC_C2H_OPCODE_START 128 | |
977 | #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129 | |
978 | #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130 | |
979 | #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131 | |
980 | #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132 | |
981 | #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133 | |
982 | #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134 | |
983 | #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135 | |
984 | #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136 | |
985 | #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137 | |
986 | #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138 | |
987 | #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139 | |
988 | #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140 | |
989 | #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 | |
990 | #define NX_NIC_C2H_OPCODE_LAST 142 | |
9ad27643 DP |
991 | |
992 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
993 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
994 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
995 | ||
1bb482f8 NK |
996 | #define NX_NIC_LRO_REQUEST_FIRST 0 |
997 | #define NX_NIC_LRO_REQUEST_ADD_FLOW 1 | |
998 | #define NX_NIC_LRO_REQUEST_DELETE_FLOW 2 | |
999 | #define NX_NIC_LRO_REQUEST_TIMER 3 | |
1000 | #define NX_NIC_LRO_REQUEST_CLEANUP 4 | |
1001 | #define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5 | |
1002 | #define NX_TOE_LRO_REQUEST_ADD_FLOW 6 | |
1003 | #define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7 | |
1004 | #define NX_TOE_LRO_REQUEST_DELETE_FLOW 8 | |
1005 | #define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9 | |
1006 | #define NX_TOE_LRO_REQUEST_TIMER 10 | |
1007 | #define NX_NIC_LRO_REQUEST_LAST 11 | |
1008 | ||
3bf26ce3 DP |
1009 | #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5) |
1010 | #define NX_FW_CAPABILITY_SWITCHING (1 << 6) | |
028afe71 DP |
1011 | #define NX_FW_CAPABILITY_PEXQ (1 << 7) |
1012 | #define NX_FW_CAPABILITY_BDG (1 << 8) | |
1013 | #define NX_FW_CAPABILITY_FVLANTX (1 << 9) | |
c1c00ab8 | 1014 | #define NX_FW_CAPABILITY_HW_LRO (1 << 10) |
3bf26ce3 DP |
1015 | |
1016 | /* module types */ | |
1017 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
1018 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
1019 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
1020 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
1021 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
1022 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
1023 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
1024 | #define LINKEVENT_MODULE_TWINAX 8 | |
1025 | ||
1026 | #define LINKSPEED_10GBPS 10000 | |
1027 | #define LINKSPEED_1GBPS 1000 | |
1028 | #define LINKSPEED_100MBPS 100 | |
1029 | #define LINKSPEED_10MBPS 10 | |
1030 | ||
1031 | #define LINKSPEED_ENCODED_10MBPS 0 | |
1032 | #define LINKSPEED_ENCODED_100MBPS 1 | |
1033 | #define LINKSPEED_ENCODED_1GBPS 2 | |
1034 | ||
1035 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
1036 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
1037 | ||
1038 | #define LINKEVENT_HALF_DUPLEX 0 | |
1039 | #define LINKEVENT_FULL_DUPLEX 1 | |
1040 | ||
1041 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
1042 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
1043 | ||
1044 | /* firmware response header: | |
1045 | * 63:58 - message type | |
1046 | * 57:56 - owner | |
1047 | * 55:53 - desc count | |
1048 | * 52:48 - reserved | |
1049 | * 47:40 - completion id | |
1050 | * 39:32 - opcode | |
1051 | * 31:16 - error code | |
1052 | * 15:00 - reserved | |
1053 | */ | |
1054 | #define netxen_get_nic_msgtype(msg_hdr) \ | |
1055 | ((msg_hdr >> 58) & 0x3F) | |
1056 | #define netxen_get_nic_msg_compid(msg_hdr) \ | |
1057 | ((msg_hdr >> 40) & 0xFF) | |
1058 | #define netxen_get_nic_msg_opcode(msg_hdr) \ | |
1059 | ((msg_hdr >> 32) & 0xFF) | |
1060 | #define netxen_get_nic_msg_errcode(msg_hdr) \ | |
1061 | ((msg_hdr >> 16) & 0xFFFF) | |
1062 | ||
1063 | typedef struct { | |
1064 | union { | |
1065 | struct { | |
1066 | u64 hdr; | |
1067 | u64 body[7]; | |
1068 | }; | |
1069 | u64 words[8]; | |
1070 | }; | |
1071 | } nx_fw_msg_t; | |
1072 | ||
48bfd1e0 | 1073 | typedef struct { |
2edbb454 DP |
1074 | __le64 qhdr; |
1075 | __le64 req_hdr; | |
1076 | __le64 words[6]; | |
c9fc891f | 1077 | } nx_nic_req_t; |
48bfd1e0 DP |
1078 | |
1079 | typedef struct { | |
1080 | u8 op; | |
1081 | u8 tag; | |
1082 | u8 mac_addr[6]; | |
1083 | } nx_mac_req_t; | |
1084 | ||
c9fc891f | 1085 | #define MAX_PENDING_DESC_BLOCK_SIZE 64 |
48bfd1e0 | 1086 | |
2956640d DP |
1087 | #define NETXEN_NIC_MSI_ENABLED 0x02 |
1088 | #define NETXEN_NIC_MSIX_ENABLED 0x04 | |
1bb482f8 | 1089 | #define NETXEN_NIC_LRO_ENABLED 0x08 |
fa3ce355 | 1090 | #define NETXEN_NIC_BRIDGE_ENABLED 0X10 |
2956640d DP |
1091 | #define NETXEN_IS_MSI_FAMILY(adapter) \ |
1092 | ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED)) | |
1093 | ||
d8b100c5 | 1094 | #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS |
2956640d DP |
1095 | #define NETXEN_MSIX_TBL_SPACE 8192 |
1096 | #define NETXEN_PCI_REG_MSIX_TBL 0x44 | |
1097 | ||
1098 | #define NETXEN_DB_MAPSIZE_BYTES 0x1000 | |
ed25ffa1 | 1099 | |
d8b100c5 | 1100 | #define NETXEN_NETDEV_WEIGHT 128 |
cd1f8160 DP |
1101 | #define NETXEN_ADAPTER_UP_MAGIC 777 |
1102 | #define NETXEN_NIC_PEG_TUNE 0 | |
1103 | ||
ed25ffa1 AK |
1104 | struct netxen_dummy_dma { |
1105 | void *addr; | |
1106 | dma_addr_t phys_addr; | |
1107 | }; | |
3d396eb1 | 1108 | |
3d396eb1 AK |
1109 | struct netxen_adapter { |
1110 | struct netxen_hardware_context ahw; | |
4790654c | 1111 | |
3176ff3e MT |
1112 | struct net_device *netdev; |
1113 | struct pci_dev *pdev; | |
5cf4d323 | 1114 | struct list_head mac_list; |
623621b0 | 1115 | |
3d396eb1 | 1116 | u32 curr_window; |
3ce06a32 DP |
1117 | u32 crb_win; |
1118 | rwlock_t adapter_lock; | |
2956640d | 1119 | |
1b1f7898 | 1120 | spinlock_t tx_clean_lock; |
ba53e6b4 | 1121 | |
71dcddbd DP |
1122 | u16 num_txd; |
1123 | u16 num_rxd; | |
1124 | u16 num_jumbo_rxd; | |
1125 | u16 num_lro_rxd; | |
3d396eb1 | 1126 | |
1b1f7898 DP |
1127 | u8 max_rds_rings; |
1128 | u8 max_sds_rings; | |
1129 | u8 driver_mismatch; | |
1130 | u8 msix_supported; | |
1131 | u8 rx_csum; | |
1132 | u8 pci_using_dac; | |
1133 | u8 portnum; | |
1134 | u8 physical_port; | |
1135 | ||
1136 | u8 mc_enabled; | |
1137 | u8 max_mc_count; | |
f6d21f44 | 1138 | u8 rss_supported; |
e424fa9d | 1139 | u8 link_changed; |
3bf26ce3 DP |
1140 | u32 resv3; |
1141 | ||
1142 | u8 has_link_events; | |
67c38fc6 | 1143 | u8 fw_type; |
1b1f7898 DP |
1144 | u16 tx_context_id; |
1145 | u16 mtu; | |
1146 | u16 is_up; | |
3bf26ce3 | 1147 | |
1b1f7898 DP |
1148 | u16 link_speed; |
1149 | u16 link_duplex; | |
1150 | u16 link_autoneg; | |
3bf26ce3 | 1151 | u16 module_type; |
48bfd1e0 | 1152 | |
3bf26ce3 | 1153 | u32 capabilities; |
3d396eb1 AK |
1154 | u32 flags; |
1155 | u32 irq; | |
cb8011ad | 1156 | u32 temp; |
2956640d | 1157 | |
7a2469ce DP |
1158 | u32 msi_tgt_status; |
1159 | u32 resv4; | |
1160 | ||
3d396eb1 | 1161 | struct netxen_adapter_stats stats; |
4790654c | 1162 | |
becf46a0 | 1163 | struct netxen_recv_context recv_ctx; |
4ea528a1 | 1164 | struct nx_host_tx_ring *tx_ring; |
3d396eb1 | 1165 | |
3d0a3cc9 | 1166 | int (*macaddr_set) (struct netxen_adapter *, u8 *); |
3176ff3e | 1167 | int (*set_mtu) (struct netxen_adapter *, int); |
9ad27643 | 1168 | int (*set_promisc) (struct netxen_adapter *, u32); |
3d0a3cc9 | 1169 | void (*set_multi) (struct net_device *); |
3ad4467c DP |
1170 | int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *); |
1171 | int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val); | |
80922fbc | 1172 | int (*init_port) (struct netxen_adapter *, int); |
3176ff3e | 1173 | int (*stop_port) (struct netxen_adapter *); |
3ce06a32 | 1174 | |
1fbe6323 DP |
1175 | u32 (*hw_read_wx)(struct netxen_adapter *, ulong); |
1176 | int (*hw_write_wx)(struct netxen_adapter *, ulong, u32); | |
3ce06a32 DP |
1177 | int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int); |
1178 | int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int); | |
1179 | int (*pci_write_immediate)(struct netxen_adapter *, u64, u32); | |
1180 | u32 (*pci_read_immediate)(struct netxen_adapter *, u64); | |
3ce06a32 DP |
1181 | unsigned long (*pci_set_window)(struct netxen_adapter *, |
1182 | unsigned long long); | |
1b1f7898 DP |
1183 | |
1184 | struct netxen_legacy_intr_set legacy_intr; | |
1185 | ||
1186 | struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; | |
1187 | ||
1188 | struct netxen_dummy_dma dummy_dma; | |
1189 | ||
1190 | struct work_struct watchdog_task; | |
1191 | struct timer_list watchdog_timer; | |
1192 | struct work_struct tx_timeout_task; | |
1193 | ||
1194 | struct net_device_stats net_stats; | |
1195 | ||
1196 | nx_nic_intr_coalesce_t coal; | |
f7185c71 | 1197 | |
4f96b988 | 1198 | u32 resv5; |
f7185c71 DP |
1199 | u32 fw_version; |
1200 | const struct firmware *fw; | |
1b1f7898 | 1201 | }; |
3d396eb1 | 1202 | |
7d6fd5e7 | 1203 | int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port); |
7d6fd5e7 DP |
1204 | int netxen_niu_disable_xg_port(struct netxen_adapter *adapter); |
1205 | ||
3ad4467c DP |
1206 | int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val); |
1207 | int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val); | |
3d396eb1 AK |
1208 | |
1209 | /* Functions available from netxen_nic_hw.c */ | |
3176ff3e MT |
1210 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); |
1211 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); | |
f98a9f69 | 1212 | |
3d0a3cc9 DP |
1213 | int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr); |
1214 | int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr); | |
1215 | ||
f98a9f69 DP |
1216 | #define NXRD32(adapter, off) \ |
1217 | (adapter->hw_read_wx(adapter, off)) | |
1218 | #define NXWR32(adapter, off, val) \ | |
1219 | (adapter->hw_write_wx(adapter, off, val)) | |
3d396eb1 | 1220 | |
c9517e58 DP |
1221 | int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32); |
1222 | void netxen_pcie_sem_unlock(struct netxen_adapter *, int); | |
1223 | ||
1224 | #define netxen_rom_lock(a) \ | |
1225 | netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID) | |
1226 | #define netxen_rom_unlock(a) \ | |
1227 | netxen_pcie_sem_unlock((a), 2) | |
1228 | #define netxen_phy_lock(a) \ | |
1229 | netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID) | |
1230 | #define netxen_phy_unlock(a) \ | |
1231 | netxen_pcie_sem_unlock((a), 3) | |
1232 | #define netxen_api_lock(a) \ | |
1233 | netxen_pcie_sem_lock((a), 5, 0) | |
1234 | #define netxen_api_unlock(a) \ | |
1235 | netxen_pcie_sem_unlock((a), 5) | |
1236 | #define netxen_sw_lock(a) \ | |
1237 | netxen_pcie_sem_lock((a), 6, 0) | |
1238 | #define netxen_sw_unlock(a) \ | |
1239 | netxen_pcie_sem_unlock((a), 6) | |
1240 | #define crb_win_lock(a) \ | |
1241 | netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID) | |
1242 | #define crb_win_unlock(a) \ | |
1243 | netxen_pcie_sem_unlock((a), 7) | |
1244 | ||
3d396eb1 | 1245 | int netxen_nic_get_board_info(struct netxen_adapter *adapter); |
1e2d0059 | 1246 | void netxen_nic_get_firmware_info(struct netxen_adapter *adapter); |
0b72e659 | 1247 | int netxen_nic_wol_supported(struct netxen_adapter *adapter); |
3ce06a32 | 1248 | |
1fbe6323 | 1249 | u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off); |
3ce06a32 | 1250 | int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, |
1fbe6323 | 1251 | ulong off, u32 data); |
3ce06a32 DP |
1252 | int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, |
1253 | u64 off, void *data, int size); | |
1254 | int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, | |
1255 | u64 off, void *data, int size); | |
1256 | int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter, | |
1257 | u64 off, u32 data); | |
1258 | u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off); | |
1259 | void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter, | |
1260 | u64 off, u32 data); | |
1261 | u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off); | |
1262 | unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, | |
1263 | unsigned long long addr); | |
1264 | void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, | |
1265 | u32 wndw); | |
1266 | ||
1fbe6323 | 1267 | u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off); |
3ce06a32 | 1268 | int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, |
1fbe6323 | 1269 | ulong off, u32 data); |
3ce06a32 DP |
1270 | int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, |
1271 | u64 off, void *data, int size); | |
1272 | int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, | |
1273 | u64 off, void *data, int size); | |
3ce06a32 DP |
1274 | int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, |
1275 | u64 off, u32 data); | |
1276 | u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off); | |
1277 | void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter, | |
1278 | u64 off, u32 data); | |
1279 | u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off); | |
1280 | unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |
1281 | unsigned long long addr); | |
3d396eb1 AK |
1282 | |
1283 | /* Functions from netxen_nic_init.c */ | |
83ac51fa DP |
1284 | int netxen_init_dummy_dma(struct netxen_adapter *adapter); |
1285 | void netxen_free_dummy_dma(struct netxen_adapter *adapter); | |
1286 | ||
96acb6eb DP |
1287 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); |
1288 | int netxen_load_firmware(struct netxen_adapter *adapter); | |
67c38fc6 | 1289 | int netxen_need_fw_reset(struct netxen_adapter *adapter); |
f7185c71 DP |
1290 | void netxen_request_firmware(struct netxen_adapter *adapter); |
1291 | void netxen_release_firmware(struct netxen_adapter *adapter); | |
3d396eb1 | 1292 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); |
2956640d | 1293 | |
3d396eb1 | 1294 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); |
4790654c | 1295 | int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 | 1296 | u8 *bytes, size_t size); |
4790654c | 1297 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
1298 | u8 *bytes, size_t size); |
1299 | int netxen_flash_unlock(struct netxen_adapter *adapter); | |
1300 | int netxen_backup_crbinit(struct netxen_adapter *adapter); | |
1301 | int netxen_flash_erase_secondary(struct netxen_adapter *adapter); | |
1302 | int netxen_flash_erase_primary(struct netxen_adapter *adapter); | |
e45d9ab4 | 1303 | void netxen_halt_pegs(struct netxen_adapter *adapter); |
27d2ab54 | 1304 | |
cb8011ad | 1305 | int netxen_rom_se(struct netxen_adapter *adapter, int addr); |
3d396eb1 | 1306 | |
2956640d DP |
1307 | int netxen_alloc_sw_resources(struct netxen_adapter *adapter); |
1308 | void netxen_free_sw_resources(struct netxen_adapter *adapter); | |
1309 | ||
1310 | int netxen_alloc_hw_resources(struct netxen_adapter *adapter); | |
1311 | void netxen_free_hw_resources(struct netxen_adapter *adapter); | |
1312 | ||
1313 | void netxen_release_rx_buffers(struct netxen_adapter *adapter); | |
1314 | void netxen_release_tx_buffers(struct netxen_adapter *adapter); | |
1315 | ||
3d396eb1 AK |
1316 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); |
1317 | int netxen_init_firmware(struct netxen_adapter *adapter); | |
3d396eb1 | 1318 | void netxen_nic_clear_stats(struct netxen_adapter *adapter); |
6d5aefb8 | 1319 | void netxen_watchdog_task(struct work_struct *work); |
d8b100c5 DP |
1320 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, |
1321 | struct nx_host_rds_ring *rds_ring); | |
05aaa02d | 1322 | int netxen_process_cmd_ring(struct netxen_adapter *adapter); |
d8b100c5 | 1323 | int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max); |
c9fc891f DP |
1324 | void netxen_p2_nic_set_multi(struct net_device *netdev); |
1325 | void netxen_p3_nic_set_multi(struct net_device *netdev); | |
06e9d9f9 | 1326 | void netxen_p3_free_mac_list(struct netxen_adapter *adapter); |
3ad4467c | 1327 | int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode); |
9ad27643 | 1328 | int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32); |
cd1f8160 | 1329 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter); |
d8b100c5 | 1330 | int netxen_config_rss(struct netxen_adapter *adapter, int enable); |
6598b169 | 1331 | int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd); |
3bf26ce3 DP |
1332 | int netxen_linkevent_request(struct netxen_adapter *adapter, int enable); |
1333 | void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup); | |
48bfd1e0 | 1334 | |
9ad27643 | 1335 | int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu); |
3d396eb1 | 1336 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); |
1bb482f8 | 1337 | int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable); |
fa3ce355 | 1338 | int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable); |
1bb482f8 | 1339 | int netxen_send_lro_cleanup(struct netxen_adapter *adapter); |
48bfd1e0 | 1340 | |
3d396eb1 AK |
1341 | int netxen_nic_set_mac(struct net_device *netdev, void *p); |
1342 | struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); | |
1343 | ||
c9fc891f | 1344 | void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, |
cb2107be | 1345 | struct nx_host_tx_ring *tx_ring); |
cb8011ad | 1346 | |
7042cd8f AKS |
1347 | /* Functions from netxen_nic_main.c */ |
1348 | int netxen_nic_reset_context(struct netxen_adapter *); | |
1349 | ||
cb8011ad AK |
1350 | /* |
1351 | * NetXen Board information | |
1352 | */ | |
1353 | ||
e4c93c81 | 1354 | #define NETXEN_MAX_SHORT_NAME 32 |
71bd7877 | 1355 | struct netxen_brdinfo { |
e98e3350 | 1356 | int brdtype; /* type of board */ |
cb8011ad AK |
1357 | long ports; /* max no of physical ports */ |
1358 | char short_name[NETXEN_MAX_SHORT_NAME]; | |
71bd7877 | 1359 | }; |
cb8011ad | 1360 | |
71bd7877 | 1361 | static const struct netxen_brdinfo netxen_boards[] = { |
cb8011ad AK |
1362 | {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, |
1363 | {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, | |
1364 | {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, | |
1365 | {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, | |
1366 | {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, | |
1367 | {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, | |
e4c93c81 DP |
1368 | {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "}, |
1369 | {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"}, | |
1370 | {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"}, | |
1371 | {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"}, | |
1372 | {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"}, | |
1373 | {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"}, | |
1374 | {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"}, | |
1375 | {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"}, | |
a70f9393 DP |
1376 | {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"}, |
1377 | {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"}, | |
1378 | {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"}, | |
e4c93c81 DP |
1379 | {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"}, |
1380 | {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"} | |
cb8011ad AK |
1381 | }; |
1382 | ||
ff8ac609 | 1383 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards) |
cb8011ad | 1384 | |
cb8011ad AK |
1385 | static inline void get_brd_name_by_type(u32 type, char *name) |
1386 | { | |
1387 | int i, found = 0; | |
1388 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1389 | if (netxen_boards[i].brdtype == type) { | |
1390 | strcpy(name, netxen_boards[i].short_name); | |
1391 | found = 1; | |
1392 | break; | |
1393 | } | |
1394 | ||
3d396eb1 | 1395 | } |
cb8011ad AK |
1396 | if (!found) |
1397 | name = "Unknown"; | |
3d396eb1 AK |
1398 | } |
1399 | ||
cb2107be DP |
1400 | static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring) |
1401 | { | |
1402 | smp_mb(); | |
1403 | return find_diff_among(tx_ring->producer, | |
1404 | tx_ring->sw_consumer, tx_ring->num_desc); | |
1405 | ||
1406 | } | |
1407 | ||
9dc28efe DP |
1408 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
1409 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); | |
3d396eb1 AK |
1410 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
1411 | extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, | |
1412 | int *valp); | |
1413 | ||
0fc0b732 | 1414 | extern const struct ethtool_ops netxen_nic_ethtool_ops; |
3d396eb1 AK |
1415 | |
1416 | #endif /* __NETXEN_NIC_H_ */ |