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3d396eb1 | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
3d396eb1 | 3 | * All rights reserved. |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
5d242f1c DP |
25 | * NetXen Inc, |
26 | * 18922 Forge Drive | |
27 | * Cupertino, CA 95014-0701 | |
28 | * | |
3d396eb1 AK |
29 | */ |
30 | ||
31 | #ifndef _NETXEN_NIC_H_ | |
32 | #define _NETXEN_NIC_H_ | |
33 | ||
3d396eb1 AK |
34 | #include <linux/module.h> |
35 | #include <linux/kernel.h> | |
36 | #include <linux/types.h> | |
3d396eb1 AK |
37 | #include <linux/ioport.h> |
38 | #include <linux/pci.h> | |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/etherdevice.h> | |
41 | #include <linux/ip.h> | |
42 | #include <linux/in.h> | |
43 | #include <linux/tcp.h> | |
44 | #include <linux/skbuff.h> | |
3d396eb1 AK |
45 | |
46 | #include <linux/ethtool.h> | |
47 | #include <linux/mii.h> | |
3d396eb1 AK |
48 | #include <linux/timer.h> |
49 | ||
42555892 | 50 | #include <linux/vmalloc.h> |
3d396eb1 | 51 | |
3d396eb1 AK |
52 | #include <asm/io.h> |
53 | #include <asm/byteorder.h> | |
3d396eb1 AK |
54 | |
55 | #include "netxen_nic_hw.h" | |
56 | ||
58735567 DP |
57 | #define _NETXEN_NIC_LINUX_MAJOR 4 |
58 | #define _NETXEN_NIC_LINUX_MINOR 0 | |
ff4fbd43 DP |
59 | #define _NETXEN_NIC_LINUX_SUBVERSION 30 |
60 | #define NETXEN_NIC_LINUX_VERSIONID "4.0.30" | |
58735567 DP |
61 | |
62 | #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c)) | |
27d2ab54 | 63 | |
0d04761d MT |
64 | #define NETXEN_NUM_FLASH_SECTORS (64) |
65 | #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024) | |
66 | #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \ | |
67 | * NETXEN_FLASH_SECTOR_SIZE) | |
3d396eb1 | 68 | |
0c25cfe1 LCMT |
69 | #define PHAN_VENDOR_ID 0x4040 |
70 | ||
d8b100c5 DP |
71 | #define RCV_DESC_RINGSIZE(rds_ring) \ |
72 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
73 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
438627c7 | 74 | (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc) |
d8b100c5 DP |
75 | #define STATUS_DESC_RINGSIZE(sds_ring) \ |
76 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
77 | #define TX_BUFF_RINGSIZE(adapter) \ | |
78 | (sizeof(struct netxen_cmd_buffer) * adapter->num_txd) | |
79 | #define TX_DESC_RINGSIZE(adapter) \ | |
80 | (sizeof(struct cmd_desc_type0) * adapter->num_txd) | |
81 | ||
ba53e6b4 | 82 | #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) |
3d396eb1 | 83 | |
ed25ffa1 AK |
84 | #define NETXEN_RCV_PRODUCER_OFFSET 0 |
85 | #define NETXEN_RCV_PEG_DB_ID 2 | |
86 | #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 | |
27d2ab54 | 87 | #define FLASH_SUCCESS 0 |
3d396eb1 AK |
88 | |
89 | #define ADDR_IN_WINDOW1(off) \ | |
90 | ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 | |
91 | ||
4790654c JG |
92 | /* |
93 | * normalize a 64MB crb address to 32MB PCI window | |
3d396eb1 AK |
94 | * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 |
95 | */ | |
80922fbc AK |
96 | #define NETXEN_CRB_NORMAL(reg) \ |
97 | ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) | |
cb8011ad | 98 | |
3d396eb1 | 99 | #define NETXEN_CRB_NORMALIZE(adapter, reg) \ |
cb8011ad AK |
100 | pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) |
101 | ||
ed25ffa1 AK |
102 | #define DB_NORMALIZE(adapter, off) \ |
103 | (adapter->ahw.db_base + (off)) | |
104 | ||
105 | #define NX_P2_C0 0x24 | |
106 | #define NX_P2_C1 0x25 | |
e4c93c81 DP |
107 | #define NX_P3_A0 0x30 |
108 | #define NX_P3_A2 0x30 | |
109 | #define NX_P3_B0 0x40 | |
110 | #define NX_P3_B1 0x41 | |
e98e3350 | 111 | #define NX_P3_B2 0x42 |
e4c93c81 DP |
112 | |
113 | #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1) | |
114 | #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0) | |
ed25ffa1 | 115 | |
cb8011ad | 116 | #define FIRST_PAGE_GROUP_START 0 |
ed25ffa1 | 117 | #define FIRST_PAGE_GROUP_END 0x100000 |
cb8011ad | 118 | |
78403a92 MT |
119 | #define SECOND_PAGE_GROUP_START 0x6000000 |
120 | #define SECOND_PAGE_GROUP_END 0x68BC000 | |
cb8011ad AK |
121 | |
122 | #define THIRD_PAGE_GROUP_START 0x70E4000 | |
123 | #define THIRD_PAGE_GROUP_END 0x8000000 | |
124 | ||
125 | #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START | |
126 | #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START | |
127 | #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START | |
3d396eb1 | 128 | |
e4c93c81 DP |
129 | #define P2_MAX_MTU (8000) |
130 | #define P3_MAX_MTU (9600) | |
131 | #define NX_ETHERMTU 1500 | |
132 | #define NX_MAX_ETHERHDR 32 /* This contains some padding */ | |
133 | ||
134 | #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU) | |
135 | #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU) | |
136 | #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU) | |
d9e651bc | 137 | #define NX_CT_DEFAULT_RX_BUF_LEN 2048 |
e4c93c81 | 138 | |
ed25ffa1 | 139 | #define MAX_RX_BUFFER_LENGTH 1760 |
bd56c6b1 | 140 | #define MAX_RX_JUMBO_BUFFER_LENGTH 8062 |
32ec8033 | 141 | #define MAX_RX_LRO_BUFFER_LENGTH (8062) |
ed25ffa1 | 142 | #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2) |
3d396eb1 | 143 | #define RX_JUMBO_DMA_MAP_LEN \ |
ed25ffa1 AK |
144 | (MAX_RX_JUMBO_BUFFER_LENGTH - 2) |
145 | #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2) | |
3d396eb1 AK |
146 | |
147 | /* | |
148 | * Maximum number of ring contexts | |
149 | */ | |
150 | #define MAX_RING_CTX 1 | |
151 | ||
152 | /* Opcodes to be used with the commands */ | |
e4c93c81 DP |
153 | #define TX_ETHER_PKT 0x01 |
154 | #define TX_TCP_PKT 0x02 | |
155 | #define TX_UDP_PKT 0x03 | |
156 | #define TX_IP_PKT 0x04 | |
157 | #define TX_TCP_LSO 0x05 | |
158 | #define TX_TCP_LSO6 0x06 | |
159 | #define TX_IPSEC 0x07 | |
160 | #define TX_IPSEC_CMD 0x0a | |
161 | #define TX_TCPV6_PKT 0x0b | |
162 | #define TX_UDPV6_PKT 0x0c | |
3d396eb1 AK |
163 | |
164 | /* The following opcodes are for internal consumption. */ | |
165 | #define NETXEN_CONTROL_OP 0x10 | |
166 | #define PEGNET_REQUEST 0x11 | |
167 | ||
168 | #define MAX_NUM_CARDS 4 | |
169 | ||
170 | #define MAX_BUFFERS_PER_CMD 32 | |
171 | ||
172 | /* | |
173 | * Following are the states of the Phantom. Phantom will set them and | |
174 | * Host will read to check if the fields are correct. | |
175 | */ | |
176 | #define PHAN_INITIALIZE_START 0xff00 | |
177 | #define PHAN_INITIALIZE_FAILED 0xffff | |
178 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
179 | ||
180 | /* Host writes the following to notify that it has done the init-handshake */ | |
181 | #define PHAN_INITIALIZE_ACK 0xf00f | |
182 | ||
d8b100c5 DP |
183 | #define NUM_RCV_DESC_RINGS 3 |
184 | #define NUM_STS_DESC_RINGS 4 | |
3d396eb1 | 185 | |
438627c7 DP |
186 | #define RCV_RING_NORMAL 0 |
187 | #define RCV_RING_JUMBO 1 | |
188 | #define RCV_RING_LRO 2 | |
3d396eb1 | 189 | |
ba53e6b4 | 190 | #define MAX_CMD_DESCRIPTORS 4096 |
bd56c6b1 | 191 | #define MAX_RCV_DESCRIPTORS 16384 |
32ec8033 DP |
192 | #define MAX_CMD_DESCRIPTORS_HOST 1024 |
193 | #define MAX_RCV_DESCRIPTORS_1G 2048 | |
194 | #define MAX_RCV_DESCRIPTORS_10G 4096 | |
e125646a | 195 | #define MAX_JUMBO_RCV_DESCRIPTORS 1024 |
32ec8033 | 196 | #define MAX_LRO_RCV_DESCRIPTORS 8 |
ed25ffa1 AK |
197 | #define NETXEN_CTX_SIGNATURE 0xdee0 |
198 | #define NETXEN_RCV_PRODUCER(ringid) (ringid) | |
3d396eb1 AK |
199 | |
200 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
201 | #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 | |
202 | ||
203 | #define get_next_index(index, length) \ | |
204 | (((index) + 1) & ((length) - 1)) | |
205 | ||
206 | #define get_index_range(index,length,count) \ | |
207 | (((index) + (count)) & ((length) - 1)) | |
208 | ||
ed25ffa1 | 209 | #define MPORT_SINGLE_FUNCTION_MODE 0x1111 |
3176ff3e | 210 | #define MPORT_MULTI_FUNCTION_MODE 0x2222 |
ed25ffa1 | 211 | |
3176ff3e | 212 | #include "netxen_nic_phan_reg.h" |
ed25ffa1 AK |
213 | |
214 | /* | |
215 | * NetXen host-peg signal message structure | |
216 | * | |
217 | * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx | |
218 | * Bit 2 : priv_id => must be 1 | |
219 | * Bit 3-17 : count => for doorbell | |
220 | * Bit 18-27 : ctx_id => Context id | |
221 | * Bit 28-31 : opcode | |
222 | */ | |
223 | ||
224 | typedef u32 netxen_ctx_msg; | |
225 | ||
ed25ffa1 | 226 | #define netxen_set_msg_peg_id(config_word, val) \ |
a608ab9c | 227 | ((config_word) &= ~3, (config_word) |= val & 3) |
ed25ffa1 | 228 | #define netxen_set_msg_privid(config_word) \ |
a608ab9c | 229 | ((config_word) |= 1 << 2) |
ed25ffa1 | 230 | #define netxen_set_msg_count(config_word, val) \ |
a608ab9c | 231 | ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) |
ed25ffa1 | 232 | #define netxen_set_msg_ctxid(config_word, val) \ |
a608ab9c | 233 | ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) |
ed25ffa1 | 234 | #define netxen_set_msg_opcode(config_word, val) \ |
82581174 | 235 | ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) |
ed25ffa1 AK |
236 | |
237 | struct netxen_rcv_context { | |
a608ab9c AV |
238 | __le64 rcv_ring_addr; |
239 | __le32 rcv_ring_size; | |
240 | __le32 rsrvd; | |
ed25ffa1 AK |
241 | }; |
242 | ||
243 | struct netxen_ring_ctx { | |
244 | ||
245 | /* one command ring */ | |
a608ab9c AV |
246 | __le64 cmd_consumer_offset; |
247 | __le64 cmd_ring_addr; | |
248 | __le32 cmd_ring_size; | |
249 | __le32 rsrvd; | |
ed25ffa1 AK |
250 | |
251 | /* three receive rings */ | |
252 | struct netxen_rcv_context rcv_ctx[3]; | |
253 | ||
254 | /* one status ring */ | |
a608ab9c AV |
255 | __le64 sts_ring_addr; |
256 | __le32 sts_ring_size; | |
ed25ffa1 | 257 | |
a608ab9c | 258 | __le32 ctx_id; |
ed25ffa1 AK |
259 | } __attribute__ ((aligned(64))); |
260 | ||
3d396eb1 AK |
261 | /* |
262 | * Following data structures describe the descriptors that will be used. | |
263 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
264 | * we are doing LSO (above the 1500 size packet) only. | |
265 | */ | |
266 | ||
267 | /* | |
268 | * The size of reference handle been changed to 16 bits to pass the MSS fields | |
269 | * for the LSO packet | |
270 | */ | |
271 | ||
272 | #define FLAGS_CHECKSUM_ENABLED 0x01 | |
273 | #define FLAGS_LSO_ENABLED 0x02 | |
274 | #define FLAGS_IPSEC_SA_ADD 0x04 | |
275 | #define FLAGS_IPSEC_SA_DELETE 0x08 | |
276 | #define FLAGS_VLAN_TAGGED 0x10 | |
277 | ||
ed25ffa1 AK |
278 | #define netxen_set_cmd_desc_port(cmd_desc, var) \ |
279 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
6c80b18d | 280 | #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \ |
48bfd1e0 | 281 | ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) |
3d396eb1 | 282 | |
391587c3 DP |
283 | #define netxen_set_tx_port(_desc, _port) \ |
284 | (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0) | |
285 | ||
286 | #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \ | |
287 | (_desc)->flags_opcode = \ | |
288 | cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)) | |
289 | ||
290 | #define netxen_set_tx_frags_len(_desc, _frags, _len) \ | |
291 | (_desc)->num_of_buffers_total_length = \ | |
292 | cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)) | |
3d396eb1 AK |
293 | |
294 | struct cmd_desc_type0 { | |
ed25ffa1 AK |
295 | u8 tcp_hdr_offset; /* For LSO only */ |
296 | u8 ip_hdr_offset; /* For LSO only */ | |
297 | /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */ | |
a608ab9c | 298 | __le16 flags_opcode; |
ed25ffa1 AK |
299 | /* Bit pattern: 0-7 total number of segments, |
300 | 8-31 Total size of the packet */ | |
a608ab9c | 301 | __le32 num_of_buffers_total_length; |
3d396eb1 AK |
302 | union { |
303 | struct { | |
a608ab9c AV |
304 | __le32 addr_low_part2; |
305 | __le32 addr_high_part2; | |
3d396eb1 | 306 | }; |
a608ab9c | 307 | __le64 addr_buffer2; |
3d396eb1 AK |
308 | }; |
309 | ||
a608ab9c AV |
310 | __le16 reference_handle; /* changed to u16 to add mss */ |
311 | __le16 mss; /* passed by NDIS_PACKET for LSO */ | |
3d396eb1 AK |
312 | /* Bit pattern 0-3 port, 0-3 ctx id */ |
313 | u8 port_ctxid; | |
314 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
a608ab9c | 315 | __le16 conn_id; /* IPSec offoad only */ |
3d396eb1 AK |
316 | |
317 | union { | |
318 | struct { | |
a608ab9c AV |
319 | __le32 addr_low_part3; |
320 | __le32 addr_high_part3; | |
3d396eb1 | 321 | }; |
a608ab9c | 322 | __le64 addr_buffer3; |
3d396eb1 | 323 | }; |
3d396eb1 AK |
324 | union { |
325 | struct { | |
a608ab9c AV |
326 | __le32 addr_low_part1; |
327 | __le32 addr_high_part1; | |
3d396eb1 | 328 | }; |
a608ab9c | 329 | __le64 addr_buffer1; |
3d396eb1 AK |
330 | }; |
331 | ||
d32cc3d2 | 332 | __le16 buffer_length[4]; |
3d396eb1 AK |
333 | |
334 | union { | |
335 | struct { | |
a608ab9c AV |
336 | __le32 addr_low_part4; |
337 | __le32 addr_high_part4; | |
3d396eb1 | 338 | }; |
a608ab9c | 339 | __le64 addr_buffer4; |
3d396eb1 AK |
340 | }; |
341 | ||
a608ab9c | 342 | __le64 unused; |
ed25ffa1 | 343 | |
3d396eb1 AK |
344 | } __attribute__ ((aligned(64))); |
345 | ||
346 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
347 | struct rcv_desc { | |
a608ab9c AV |
348 | __le16 reference_handle; |
349 | __le16 reserved; | |
350 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
351 | __le64 addr_buffer; | |
3d396eb1 AK |
352 | }; |
353 | ||
354 | /* opcode field in status_desc */ | |
d9e651bc DP |
355 | #define NETXEN_NIC_RXPKT_DESC 0x04 |
356 | #define NETXEN_OLD_RXPKT_DESC 0x3f | |
3d396eb1 AK |
357 | |
358 | /* for status field in status_desc */ | |
359 | #define STATUS_NEED_CKSUM (1) | |
360 | #define STATUS_CKSUM_OK (2) | |
361 | ||
362 | /* owner bits of status_desc */ | |
0ddc110c DP |
363 | #define STATUS_OWNER_HOST (0x1ULL << 56) |
364 | #define STATUS_OWNER_PHANTOM (0x2ULL << 56) | |
3d396eb1 AK |
365 | |
366 | /* Note: sizeof(status_desc) should always be a mutliple of 2 */ | |
ed25ffa1 | 367 | |
5dc16268 DP |
368 | #define netxen_get_sts_port(sts_data) \ |
369 | ((sts_data) & 0x0F) | |
370 | #define netxen_get_sts_status(sts_data) \ | |
371 | (((sts_data) >> 4) & 0x0F) | |
372 | #define netxen_get_sts_type(sts_data) \ | |
373 | (((sts_data) >> 8) & 0x0F) | |
374 | #define netxen_get_sts_totallength(sts_data) \ | |
375 | (((sts_data) >> 12) & 0xFFFF) | |
376 | #define netxen_get_sts_refhandle(sts_data) \ | |
377 | (((sts_data) >> 28) & 0xFFFF) | |
378 | #define netxen_get_sts_prot(sts_data) \ | |
379 | (((sts_data) >> 44) & 0x0F) | |
d9e651bc DP |
380 | #define netxen_get_sts_pkt_offset(sts_data) \ |
381 | (((sts_data) >> 48) & 0x1F) | |
5dc16268 DP |
382 | #define netxen_get_sts_opcode(sts_data) \ |
383 | (((sts_data) >> 58) & 0x03F) | |
384 | ||
3d396eb1 | 385 | struct status_desc { |
ed25ffa1 | 386 | /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length |
d9e651bc | 387 | 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset |
ed25ffa1 AK |
388 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode |
389 | */ | |
a608ab9c | 390 | __le64 status_desc_data; |
d9e651bc DP |
391 | union { |
392 | struct { | |
393 | __le32 hash_value; | |
394 | u8 hash_type; | |
395 | u8 msg_type; | |
396 | u8 unused; | |
397 | union { | |
398 | /* Bit pattern: 0-6 lro_count indicates frag | |
399 | * sequence, 7 last_frag indicates last frag | |
400 | */ | |
401 | u8 lro; | |
402 | ||
403 | /* chained buffers */ | |
404 | u8 nr_frags; | |
405 | }; | |
406 | }; | |
407 | struct { | |
408 | __le16 frag_handles[4]; | |
409 | }; | |
410 | }; | |
6c80b18d | 411 | } __attribute__ ((aligned(16))); |
3d396eb1 | 412 | |
3d396eb1 AK |
413 | /* The version of the main data structure */ |
414 | #define NETXEN_BDINFO_VERSION 1 | |
415 | ||
416 | /* Magic number to let user know flash is programmed */ | |
417 | #define NETXEN_BDINFO_MAGIC 0x12345678 | |
418 | ||
419 | /* Max number of Gig ports on a Phantom board */ | |
420 | #define NETXEN_MAX_PORTS 4 | |
421 | ||
e98e3350 DP |
422 | #define NETXEN_BRDTYPE_P1_BD 0x0000 |
423 | #define NETXEN_BRDTYPE_P1_SB 0x0001 | |
424 | #define NETXEN_BRDTYPE_P1_SMAX 0x0002 | |
425 | #define NETXEN_BRDTYPE_P1_SOCK 0x0003 | |
426 | ||
427 | #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008 | |
428 | #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009 | |
429 | #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a | |
430 | #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b | |
431 | #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c | |
432 | ||
433 | #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d | |
434 | #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e | |
435 | #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f | |
436 | ||
437 | #define NETXEN_BRDTYPE_P3_REF_QG 0x0021 | |
438 | #define NETXEN_BRDTYPE_P3_HMEZ 0x0022 | |
439 | #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023 | |
440 | #define NETXEN_BRDTYPE_P3_4_GB 0x0024 | |
441 | #define NETXEN_BRDTYPE_P3_IMEZ 0x0025 | |
442 | #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026 | |
443 | #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027 | |
444 | #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028 | |
445 | #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029 | |
446 | #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a | |
447 | #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b | |
448 | #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031 | |
449 | #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032 | |
450 | #define NETXEN_BRDTYPE_P3_10G_TP 0x0080 | |
3d396eb1 AK |
451 | |
452 | struct netxen_board_info { | |
453 | u32 header_version; | |
454 | ||
455 | u32 board_mfg; | |
456 | u32 board_type; | |
457 | u32 board_num; | |
458 | u32 chip_id; | |
459 | u32 chip_minor; | |
460 | u32 chip_major; | |
461 | u32 chip_pkg; | |
462 | u32 chip_lot; | |
463 | ||
464 | u32 port_mask; /* available niu ports */ | |
465 | u32 peg_mask; /* available pegs */ | |
466 | u32 icache_ok; /* can we run with icache? */ | |
467 | u32 dcache_ok; /* can we run with dcache? */ | |
468 | u32 casper_ok; | |
469 | ||
470 | u32 mac_addr_lo_0; | |
471 | u32 mac_addr_lo_1; | |
472 | u32 mac_addr_lo_2; | |
473 | u32 mac_addr_lo_3; | |
474 | ||
475 | /* MN-related config */ | |
476 | u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */ | |
477 | u32 mn_sync_shift_cclk; | |
478 | u32 mn_sync_shift_mclk; | |
479 | u32 mn_wb_en; | |
480 | u32 mn_crystal_freq; /* in MHz */ | |
481 | u32 mn_speed; /* in MHz */ | |
482 | u32 mn_org; | |
483 | u32 mn_depth; | |
484 | u32 mn_ranks_0; /* ranks per slot */ | |
485 | u32 mn_ranks_1; /* ranks per slot */ | |
486 | u32 mn_rd_latency_0; | |
487 | u32 mn_rd_latency_1; | |
488 | u32 mn_rd_latency_2; | |
489 | u32 mn_rd_latency_3; | |
490 | u32 mn_rd_latency_4; | |
491 | u32 mn_rd_latency_5; | |
492 | u32 mn_rd_latency_6; | |
493 | u32 mn_rd_latency_7; | |
494 | u32 mn_rd_latency_8; | |
495 | u32 mn_dll_val[18]; | |
496 | u32 mn_mode_reg; /* MIU DDR Mode Register */ | |
497 | u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */ | |
498 | u32 mn_timing_0; /* MIU Memory Control Timing Rgister */ | |
499 | u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */ | |
500 | u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */ | |
501 | ||
502 | /* SN-related config */ | |
503 | u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */ | |
504 | u32 sn_pt_mode; /* pass through mode */ | |
505 | u32 sn_ecc_en; | |
506 | u32 sn_wb_en; | |
507 | u32 sn_crystal_freq; | |
508 | u32 sn_speed; | |
509 | u32 sn_org; | |
510 | u32 sn_depth; | |
511 | u32 sn_dll_tap; | |
512 | u32 sn_rd_latency; | |
513 | ||
514 | u32 mac_addr_hi_0; | |
515 | u32 mac_addr_hi_1; | |
516 | u32 mac_addr_hi_2; | |
517 | u32 mac_addr_hi_3; | |
518 | ||
519 | u32 magic; /* indicates flash has been initialized */ | |
520 | ||
521 | u32 mn_rdimm; | |
522 | u32 mn_dll_override; | |
523 | ||
524 | }; | |
525 | ||
526 | #define FLASH_NUM_PORTS (4) | |
527 | ||
528 | struct netxen_flash_mac_addr { | |
529 | u32 flash_addr[32]; | |
530 | }; | |
531 | ||
532 | struct netxen_user_old_info { | |
533 | u8 flash_md5[16]; | |
534 | u8 crbinit_md5[16]; | |
535 | u8 brdcfg_md5[16]; | |
536 | /* bootloader */ | |
537 | u32 bootld_version; | |
538 | u32 bootld_size; | |
539 | u8 bootld_md5[16]; | |
540 | /* image */ | |
541 | u32 image_version; | |
542 | u32 image_size; | |
543 | u8 image_md5[16]; | |
544 | /* primary image status */ | |
545 | u32 primary_status; | |
546 | u32 secondary_present; | |
547 | ||
548 | /* MAC address , 4 ports */ | |
549 | struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS]; | |
550 | }; | |
551 | #define FLASH_NUM_MAC_PER_PORT 32 | |
552 | struct netxen_user_info { | |
553 | u8 flash_md5[16 * 64]; | |
554 | /* bootloader */ | |
555 | u32 bootld_version; | |
556 | u32 bootld_size; | |
557 | /* image */ | |
558 | u32 image_version; | |
559 | u32 image_size; | |
560 | /* primary image status */ | |
561 | u32 primary_status; | |
562 | u32 secondary_present; | |
563 | ||
564 | /* MAC address , 4 ports, 32 address per port */ | |
565 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
566 | u32 sub_sys_id; | |
567 | u8 serial_num[32]; | |
568 | ||
569 | /* Any user defined data */ | |
570 | }; | |
571 | ||
572 | /* | |
573 | * Flash Layout - new format. | |
574 | */ | |
575 | struct netxen_new_user_info { | |
576 | u8 flash_md5[16 * 64]; | |
577 | /* bootloader */ | |
578 | u32 bootld_version; | |
579 | u32 bootld_size; | |
580 | /* image */ | |
581 | u32 image_version; | |
582 | u32 image_size; | |
583 | /* primary image status */ | |
584 | u32 primary_status; | |
585 | u32 secondary_present; | |
586 | ||
587 | /* MAC address , 4 ports, 32 address per port */ | |
588 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
589 | u32 sub_sys_id; | |
590 | u8 serial_num[32]; | |
591 | ||
592 | /* Any user defined data */ | |
593 | }; | |
594 | ||
595 | #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6 | |
596 | #define SECONDARY_IMAGE_ABSENT 0xffffffff | |
597 | #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a | |
598 | #define PRIMARY_IMAGE_BAD 0xffffffff | |
599 | ||
600 | /* Flash memory map */ | |
e98e3350 DP |
601 | #define NETXEN_CRBINIT_START 0 /* crbinit section */ |
602 | #define NETXEN_BRDCFG_START 0x4000 /* board config */ | |
603 | #define NETXEN_INITCODE_START 0x6000 /* pegtune code */ | |
604 | #define NETXEN_BOOTLD_START 0x10000 /* bootld */ | |
605 | #define NETXEN_IMAGE_START 0x43000 /* compressed image */ | |
606 | #define NETXEN_SECONDARY_START 0x200000 /* backup images */ | |
607 | #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */ | |
608 | #define NETXEN_USER_START 0x3E8000 /* Firmare info */ | |
609 | #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */ | |
3d396eb1 | 610 | |
ba599d4f DP |
611 | #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408) |
612 | #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c) | |
613 | #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c) | |
614 | #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128) | |
615 | #define NX_FW_MIN_SIZE (0x3fffff) | |
bd257ed9 DP |
616 | #define NX_P2_MN_ROMIMAGE 0 |
617 | #define NX_P3_CT_ROMIMAGE 1 | |
618 | #define NX_P3_MN_ROMIMAGE 2 | |
ba599d4f | 619 | |
0d04761d MT |
620 | #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */ |
621 | ||
622 | #define NETXEN_FLASH_START (NETXEN_CRBINIT_START) | |
623 | #define NETXEN_INIT_SECTOR (0) | |
624 | #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START) | |
625 | #define NETXEN_FLASH_CRBINIT_SIZE (0x4000) | |
626 | #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info)) | |
627 | #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32)) | |
628 | #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START) | |
629 | #define NETXEN_NUM_PRIMARY_SECTORS (0x20) | |
630 | #define NETXEN_NUM_CONFIG_SECTORS (1) | |
ed25ffa1 | 631 | extern char netxen_nic_driver_name[]; |
3d396eb1 | 632 | |
3d396eb1 | 633 | /* Number of status descriptors to handle per interrupt */ |
d8b100c5 | 634 | #define MAX_STATUS_HANDLE (64) |
3d396eb1 AK |
635 | |
636 | /* | |
637 | * netxen_skb_frag{} is to contain mapping info for each SG list. This | |
638 | * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. | |
639 | */ | |
640 | struct netxen_skb_frag { | |
641 | u64 dma; | |
391587c3 | 642 | ulong length; |
3d396eb1 AK |
643 | }; |
644 | ||
6c80b18d MT |
645 | #define _netxen_set_bits(config_word, start, bits, val) {\ |
646 | unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\ | |
647 | unsigned long long __tvalue = (val); \ | |
648 | (config_word) &= ~__tmask; \ | |
649 | (config_word) |= (((__tvalue) << (start)) & __tmask); \ | |
650 | } | |
4790654c | 651 | |
6c80b18d MT |
652 | #define _netxen_clear_bits(config_word, start, bits) {\ |
653 | unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \ | |
654 | (config_word) &= ~__tmask; \ | |
4790654c | 655 | } |
6c80b18d | 656 | |
3d396eb1 AK |
657 | /* Following defines are for the state of the buffers */ |
658 | #define NETXEN_BUFFER_FREE 0 | |
659 | #define NETXEN_BUFFER_BUSY 1 | |
660 | ||
661 | /* | |
662 | * There will be one netxen_buffer per skb packet. These will be | |
663 | * used to save the dma info for pci_unmap_page() | |
664 | */ | |
665 | struct netxen_cmd_buffer { | |
666 | struct sk_buff *skb; | |
667 | struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; | |
391587c3 | 668 | u32 frag_count; |
3d396eb1 AK |
669 | }; |
670 | ||
671 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
672 | struct netxen_rx_buffer { | |
d9e651bc | 673 | struct list_head list; |
3d396eb1 AK |
674 | struct sk_buff *skb; |
675 | u64 dma; | |
676 | u16 ref_handle; | |
677 | u16 state; | |
678 | }; | |
679 | ||
680 | /* Board types */ | |
681 | #define NETXEN_NIC_GBE 0x01 | |
682 | #define NETXEN_NIC_XGBE 0x02 | |
683 | ||
684 | /* | |
685 | * One hardware_context{} per adapter | |
686 | * contains interrupt info as well shared hardware info. | |
687 | */ | |
688 | struct netxen_hardware_context { | |
cb8011ad AK |
689 | void __iomem *pci_base0; |
690 | void __iomem *pci_base1; | |
691 | void __iomem *pci_base2; | |
ed25ffa1 AK |
692 | void __iomem *db_base; |
693 | unsigned long db_len; | |
3ce06a32 DP |
694 | unsigned long pci_len0; |
695 | ||
696 | int qdr_sn_window; | |
697 | int ddr_mn_window; | |
698 | unsigned long mn_win_crb; | |
699 | unsigned long ms_win_crb; | |
cb8011ad | 700 | |
1e2d0059 | 701 | u8 cut_through; |
3d396eb1 | 702 | u8 revision_id; |
1e2d0059 DP |
703 | u16 port_type; |
704 | int board_type; | |
a97342f9 | 705 | u32 linkup; |
3d396eb1 AK |
706 | /* Address of cmd ring in Phantom */ |
707 | struct cmd_desc_type0 *cmd_desc_head; | |
708 | dma_addr_t cmd_desc_phys_addr; | |
709 | struct netxen_adapter *adapter; | |
13ba9c77 | 710 | int pci_func; |
3d396eb1 AK |
711 | }; |
712 | ||
713 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ | |
714 | #define ETHERNET_FCS_SIZE 4 | |
715 | ||
716 | struct netxen_adapter_stats { | |
3176ff3e | 717 | u64 xmitcalled; |
3176ff3e | 718 | u64 xmitfinished; |
d1847a72 | 719 | u64 rxdropped; |
3176ff3e | 720 | u64 txdropped; |
3176ff3e MT |
721 | u64 csummed; |
722 | u64 no_rcv; | |
723 | u64 rxbytes; | |
724 | u64 txbytes; | |
3d396eb1 AK |
725 | }; |
726 | ||
727 | /* | |
728 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
729 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
730 | */ | |
48bfd1e0 | 731 | struct nx_host_rds_ring { |
3d396eb1 | 732 | u32 producer; |
d8b100c5 | 733 | u32 crb_rcv_producer; |
438627c7 DP |
734 | u32 num_desc; |
735 | u32 dma_size; | |
736 | u32 skb_size; | |
737 | u32 flags; | |
d8b100c5 DP |
738 | struct rcv_desc *desc_head; |
739 | struct netxen_rx_buffer *rx_buf_arr; | |
740 | struct list_head free_list; | |
741 | spinlock_t lock; | |
438627c7 | 742 | dma_addr_t phys_addr; |
3d396eb1 AK |
743 | }; |
744 | ||
d8b100c5 DP |
745 | struct nx_host_sds_ring { |
746 | u32 consumer; | |
747 | u32 crb_sts_consumer; | |
748 | u32 crb_intr_mask; | |
749 | u32 num_desc; | |
750 | ||
751 | struct status_desc *desc_head; | |
752 | struct netxen_adapter *adapter; | |
753 | struct napi_struct napi; | |
754 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
755 | ||
756 | u16 clean_tx; | |
757 | u16 post_rxd; | |
758 | int irq; | |
759 | ||
760 | dma_addr_t phys_addr; | |
761 | char name[IFNAMSIZ+4]; | |
762 | }; | |
763 | ||
3d396eb1 AK |
764 | /* |
765 | * Receive context. There is one such structure per instance of the | |
766 | * receive processing. Any state information that is relevant to | |
767 | * the receive, and is must be in this structure. The global data may be | |
768 | * present elsewhere. | |
769 | */ | |
770 | struct netxen_recv_context { | |
48bfd1e0 DP |
771 | u32 state; |
772 | u16 context_id; | |
773 | u16 virt_port; | |
774 | ||
775 | struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS]; | |
d8b100c5 | 776 | struct nx_host_sds_ring sds_rings[NUM_STS_DESC_RINGS]; |
3d396eb1 AK |
777 | }; |
778 | ||
48bfd1e0 DP |
779 | /* New HW context creation */ |
780 | ||
781 | #define NX_OS_CRB_RETRY_COUNT 4000 | |
782 | #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \ | |
783 | (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) | |
784 | ||
785 | #define NX_CDRP_CLEAR 0x00000000 | |
786 | #define NX_CDRP_CMD_BIT 0x80000000 | |
787 | ||
788 | /* | |
789 | * All responses must have the NX_CDRP_CMD_BIT cleared | |
790 | * in the crb NX_CDRP_CRB_OFFSET. | |
791 | */ | |
792 | #define NX_CDRP_FORM_RSP(rsp) (rsp) | |
793 | #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0) | |
794 | ||
795 | #define NX_CDRP_RSP_OK 0x00000001 | |
796 | #define NX_CDRP_RSP_FAIL 0x00000002 | |
797 | #define NX_CDRP_RSP_TIMEOUT 0x00000003 | |
798 | ||
799 | /* | |
800 | * All commands must have the NX_CDRP_CMD_BIT set in | |
801 | * the crb NX_CDRP_CRB_OFFSET. | |
802 | */ | |
803 | #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd)) | |
804 | #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0) | |
805 | ||
806 | #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 | |
807 | #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 | |
808 | #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 | |
809 | #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 | |
810 | #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 | |
811 | #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 | |
812 | #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007 | |
813 | #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008 | |
814 | #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009 | |
815 | #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a | |
816 | #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e | |
817 | #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f | |
818 | #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010 | |
819 | #define NX_CDRP_CMD_SET_MTU 0x00000012 | |
820 | #define NX_CDRP_CMD_MAX 0x00000013 | |
821 | ||
822 | #define NX_RCODE_SUCCESS 0 | |
823 | #define NX_RCODE_NO_HOST_MEM 1 | |
824 | #define NX_RCODE_NO_HOST_RESOURCE 2 | |
825 | #define NX_RCODE_NO_CARD_CRB 3 | |
826 | #define NX_RCODE_NO_CARD_MEM 4 | |
827 | #define NX_RCODE_NO_CARD_RESOURCE 5 | |
828 | #define NX_RCODE_INVALID_ARGS 6 | |
829 | #define NX_RCODE_INVALID_ACTION 7 | |
830 | #define NX_RCODE_INVALID_STATE 8 | |
831 | #define NX_RCODE_NOT_SUPPORTED 9 | |
832 | #define NX_RCODE_NOT_PERMITTED 10 | |
833 | #define NX_RCODE_NOT_READY 11 | |
834 | #define NX_RCODE_DOES_NOT_EXIST 12 | |
835 | #define NX_RCODE_ALREADY_EXISTS 13 | |
836 | #define NX_RCODE_BAD_SIGNATURE 14 | |
837 | #define NX_RCODE_CMD_NOT_IMPL 15 | |
838 | #define NX_RCODE_CMD_INVALID 16 | |
839 | #define NX_RCODE_TIMEOUT 17 | |
840 | #define NX_RCODE_CMD_FAILED 18 | |
841 | #define NX_RCODE_MAX_EXCEEDED 19 | |
842 | #define NX_RCODE_MAX 20 | |
843 | ||
844 | #define NX_DESTROY_CTX_RESET 0 | |
845 | #define NX_DESTROY_CTX_D3_RESET 1 | |
846 | #define NX_DESTROY_CTX_MAX 2 | |
847 | ||
848 | /* | |
849 | * Capabilities | |
850 | */ | |
851 | #define NX_CAP_BIT(class, bit) (1 << bit) | |
852 | #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0) | |
853 | #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1) | |
854 | #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2) | |
855 | #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3) | |
856 | #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4) | |
857 | #define NX_CAP0_LRO NX_CAP_BIT(0, 5) | |
858 | #define NX_CAP0_LSO NX_CAP_BIT(0, 6) | |
859 | #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7) | |
860 | #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8) | |
861 | ||
862 | /* | |
863 | * Context state | |
864 | */ | |
865 | #define NX_HOST_CTX_STATE_FREED 0 | |
866 | #define NX_HOST_CTX_STATE_ALLOCATED 1 | |
867 | #define NX_HOST_CTX_STATE_ACTIVE 2 | |
868 | #define NX_HOST_CTX_STATE_DISABLED 3 | |
869 | #define NX_HOST_CTX_STATE_QUIESCED 4 | |
870 | #define NX_HOST_CTX_STATE_MAX 5 | |
871 | ||
872 | /* | |
873 | * Rx context | |
874 | */ | |
875 | ||
876 | typedef struct { | |
2edbb454 DP |
877 | __le64 host_phys_addr; /* Ring base addr */ |
878 | __le32 ring_size; /* Ring entries */ | |
879 | __le16 msi_index; | |
880 | __le16 rsvd; /* Padding */ | |
48bfd1e0 DP |
881 | } nx_hostrq_sds_ring_t; |
882 | ||
883 | typedef struct { | |
2edbb454 DP |
884 | __le64 host_phys_addr; /* Ring base addr */ |
885 | __le64 buff_size; /* Packet buffer size */ | |
886 | __le32 ring_size; /* Ring entries */ | |
887 | __le32 ring_kind; /* Class of ring */ | |
48bfd1e0 DP |
888 | } nx_hostrq_rds_ring_t; |
889 | ||
890 | typedef struct { | |
2edbb454 DP |
891 | __le64 host_rsp_dma_addr; /* Response dma'd here */ |
892 | __le32 capabilities[4]; /* Flag bit vector */ | |
893 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
894 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
48bfd1e0 | 895 | /* These ring offsets are relative to data[0] below */ |
2edbb454 DP |
896 | __le32 rds_ring_offset; /* Offset to RDS config */ |
897 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
898 | __le16 num_rds_rings; /* Count of RDS rings */ | |
899 | __le16 num_sds_rings; /* Count of SDS rings */ | |
900 | __le16 rsvd1; /* Padding */ | |
901 | __le16 rsvd2; /* Padding */ | |
48bfd1e0 DP |
902 | u8 reserved[128]; /* reserve space for future expansion*/ |
903 | /* MUST BE 64-bit aligned. | |
904 | The following is packed: | |
905 | - N hostrq_rds_rings | |
906 | - N hostrq_sds_rings */ | |
907 | char data[0]; | |
908 | } nx_hostrq_rx_ctx_t; | |
909 | ||
910 | typedef struct { | |
2edbb454 DP |
911 | __le32 host_producer_crb; /* Crb to use */ |
912 | __le32 rsvd1; /* Padding */ | |
48bfd1e0 DP |
913 | } nx_cardrsp_rds_ring_t; |
914 | ||
915 | typedef struct { | |
2edbb454 DP |
916 | __le32 host_consumer_crb; /* Crb to use */ |
917 | __le32 interrupt_crb; /* Crb to use */ | |
48bfd1e0 DP |
918 | } nx_cardrsp_sds_ring_t; |
919 | ||
920 | typedef struct { | |
921 | /* These ring offsets are relative to data[0] below */ | |
2edbb454 DP |
922 | __le32 rds_ring_offset; /* Offset to RDS config */ |
923 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
924 | __le32 host_ctx_state; /* Starting State */ | |
925 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
926 | __le16 num_rds_rings; /* Count of RDS rings */ | |
927 | __le16 num_sds_rings; /* Count of SDS rings */ | |
928 | __le16 context_id; /* Handle for context */ | |
48bfd1e0 DP |
929 | u8 phys_port; /* Physical id of port */ |
930 | u8 virt_port; /* Virtual/Logical id of port */ | |
931 | u8 reserved[128]; /* save space for future expansion */ | |
932 | /* MUST BE 64-bit aligned. | |
933 | The following is packed: | |
934 | - N cardrsp_rds_rings | |
935 | - N cardrs_sds_rings */ | |
936 | char data[0]; | |
937 | } nx_cardrsp_rx_ctx_t; | |
938 | ||
939 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
940 | (sizeof(HOSTRQ_RX) + \ | |
941 | (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \ | |
942 | (sds_rings)*(sizeof(nx_hostrq_sds_ring_t))) | |
943 | ||
944 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
945 | (sizeof(CARDRSP_RX) + \ | |
946 | (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \ | |
947 | (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t))) | |
948 | ||
949 | /* | |
950 | * Tx context | |
951 | */ | |
952 | ||
953 | typedef struct { | |
2edbb454 DP |
954 | __le64 host_phys_addr; /* Ring base addr */ |
955 | __le32 ring_size; /* Ring entries */ | |
956 | __le32 rsvd; /* Padding */ | |
48bfd1e0 DP |
957 | } nx_hostrq_cds_ring_t; |
958 | ||
959 | typedef struct { | |
2edbb454 DP |
960 | __le64 host_rsp_dma_addr; /* Response dma'd here */ |
961 | __le64 cmd_cons_dma_addr; /* */ | |
962 | __le64 dummy_dma_addr; /* */ | |
963 | __le32 capabilities[4]; /* Flag bit vector */ | |
964 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
965 | __le32 rsvd1; /* Padding */ | |
966 | __le16 rsvd2; /* Padding */ | |
967 | __le16 interrupt_ctl; | |
968 | __le16 msi_index; | |
969 | __le16 rsvd3; /* Padding */ | |
48bfd1e0 DP |
970 | nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */ |
971 | u8 reserved[128]; /* future expansion */ | |
972 | } nx_hostrq_tx_ctx_t; | |
973 | ||
974 | typedef struct { | |
2edbb454 DP |
975 | __le32 host_producer_crb; /* Crb to use */ |
976 | __le32 interrupt_crb; /* Crb to use */ | |
48bfd1e0 DP |
977 | } nx_cardrsp_cds_ring_t; |
978 | ||
979 | typedef struct { | |
2edbb454 DP |
980 | __le32 host_ctx_state; /* Starting state */ |
981 | __le16 context_id; /* Handle for context */ | |
48bfd1e0 DP |
982 | u8 phys_port; /* Physical id of port */ |
983 | u8 virt_port; /* Virtual/Logical id of port */ | |
984 | nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */ | |
985 | u8 reserved[128]; /* future expansion */ | |
986 | } nx_cardrsp_tx_ctx_t; | |
987 | ||
988 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
989 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
990 | ||
991 | /* CRB */ | |
992 | ||
993 | #define NX_HOST_RDS_CRB_MODE_UNIQUE 0 | |
994 | #define NX_HOST_RDS_CRB_MODE_SHARED 1 | |
995 | #define NX_HOST_RDS_CRB_MODE_CUSTOM 2 | |
996 | #define NX_HOST_RDS_CRB_MODE_MAX 3 | |
997 | ||
998 | #define NX_HOST_INT_CRB_MODE_UNIQUE 0 | |
999 | #define NX_HOST_INT_CRB_MODE_SHARED 1 | |
1000 | #define NX_HOST_INT_CRB_MODE_NORX 2 | |
1001 | #define NX_HOST_INT_CRB_MODE_NOTX 3 | |
1002 | #define NX_HOST_INT_CRB_MODE_NORXTX 4 | |
1003 | ||
1004 | ||
1005 | /* MAC */ | |
1006 | ||
1007 | #define MC_COUNT_P2 16 | |
1008 | #define MC_COUNT_P3 38 | |
1009 | ||
1010 | #define NETXEN_MAC_NOOP 0 | |
1011 | #define NETXEN_MAC_ADD 1 | |
1012 | #define NETXEN_MAC_DEL 2 | |
1013 | ||
1014 | typedef struct nx_mac_list_s { | |
1015 | struct nx_mac_list_s *next; | |
1016 | uint8_t mac_addr[MAX_ADDR_LEN]; | |
1017 | } nx_mac_list_t; | |
1018 | ||
cd1f8160 DP |
1019 | /* |
1020 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
1021 | * adjusted based on configured MTU. | |
1022 | */ | |
1023 | #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3 | |
1024 | #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256 | |
1025 | #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64 | |
1026 | #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4 | |
1027 | ||
1028 | #define NETXEN_NIC_INTR_DEFAULT 0x04 | |
1029 | ||
1030 | typedef union { | |
1031 | struct { | |
1032 | uint16_t rx_packets; | |
1033 | uint16_t rx_time_us; | |
1034 | uint16_t tx_packets; | |
1035 | uint16_t tx_time_us; | |
1036 | } data; | |
1037 | uint64_t word; | |
1038 | } nx_nic_intr_coalesce_data_t; | |
1039 | ||
1040 | typedef struct { | |
1041 | uint16_t stats_time_us; | |
1042 | uint16_t rate_sample_time; | |
1043 | uint16_t flags; | |
1044 | uint16_t rsvd_1; | |
1045 | uint32_t low_threshold; | |
1046 | uint32_t high_threshold; | |
1047 | nx_nic_intr_coalesce_data_t normal; | |
1048 | nx_nic_intr_coalesce_data_t low; | |
1049 | nx_nic_intr_coalesce_data_t high; | |
1050 | nx_nic_intr_coalesce_data_t irq; | |
1051 | } nx_nic_intr_coalesce_t; | |
1052 | ||
9ad27643 DP |
1053 | #define NX_HOST_REQUEST 0x13 |
1054 | #define NX_NIC_REQUEST 0x14 | |
1055 | ||
1056 | #define NX_MAC_EVENT 0x1 | |
1057 | ||
e98e3350 DP |
1058 | /* |
1059 | * Driver --> Firmware | |
1060 | */ | |
1061 | #define NX_NIC_H2C_OPCODE_START 0 | |
1062 | #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1 | |
1063 | #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2 | |
1064 | #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3 | |
1065 | #define NX_NIC_H2C_OPCODE_CONFIG_LED 4 | |
1066 | #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5 | |
1067 | #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6 | |
1068 | #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7 | |
1069 | #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8 | |
1070 | #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9 | |
1071 | #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10 | |
1072 | #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11 | |
1073 | #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12 | |
1074 | #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13 | |
1075 | #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14 | |
1076 | #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15 | |
1077 | #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16 | |
1078 | #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17 | |
1079 | #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18 | |
1080 | #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19 | |
1081 | #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20 | |
1082 | #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21 | |
1083 | #define NX_NIC_C2C_OPCODE 22 | |
1084 | #define NX_NIC_H2C_OPCODE_LAST 23 | |
1085 | ||
1086 | /* | |
1087 | * Firmware --> Driver | |
1088 | */ | |
1089 | ||
1090 | #define NX_NIC_C2H_OPCODE_START 128 | |
1091 | #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129 | |
1092 | #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130 | |
1093 | #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131 | |
1094 | #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132 | |
1095 | #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133 | |
1096 | #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134 | |
1097 | #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135 | |
1098 | #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136 | |
1099 | #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137 | |
1100 | #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138 | |
1101 | #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139 | |
1102 | #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140 | |
1103 | #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 | |
1104 | #define NX_NIC_C2H_OPCODE_LAST 142 | |
9ad27643 DP |
1105 | |
1106 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
1107 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
1108 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
1109 | ||
48bfd1e0 | 1110 | typedef struct { |
2edbb454 DP |
1111 | __le64 qhdr; |
1112 | __le64 req_hdr; | |
1113 | __le64 words[6]; | |
c9fc891f | 1114 | } nx_nic_req_t; |
48bfd1e0 DP |
1115 | |
1116 | typedef struct { | |
1117 | u8 op; | |
1118 | u8 tag; | |
1119 | u8 mac_addr[6]; | |
1120 | } nx_mac_req_t; | |
1121 | ||
c9fc891f | 1122 | #define MAX_PENDING_DESC_BLOCK_SIZE 64 |
48bfd1e0 | 1123 | |
2956640d DP |
1124 | #define NETXEN_NIC_MSI_ENABLED 0x02 |
1125 | #define NETXEN_NIC_MSIX_ENABLED 0x04 | |
1126 | #define NETXEN_IS_MSI_FAMILY(adapter) \ | |
1127 | ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED)) | |
1128 | ||
d8b100c5 | 1129 | #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS |
2956640d DP |
1130 | #define NETXEN_MSIX_TBL_SPACE 8192 |
1131 | #define NETXEN_PCI_REG_MSIX_TBL 0x44 | |
1132 | ||
1133 | #define NETXEN_DB_MAPSIZE_BYTES 0x1000 | |
ed25ffa1 | 1134 | |
d8b100c5 | 1135 | #define NETXEN_NETDEV_WEIGHT 128 |
cd1f8160 DP |
1136 | #define NETXEN_ADAPTER_UP_MAGIC 777 |
1137 | #define NETXEN_NIC_PEG_TUNE 0 | |
1138 | ||
ed25ffa1 AK |
1139 | struct netxen_dummy_dma { |
1140 | void *addr; | |
1141 | dma_addr_t phys_addr; | |
1142 | }; | |
3d396eb1 | 1143 | |
3d396eb1 AK |
1144 | struct netxen_adapter { |
1145 | struct netxen_hardware_context ahw; | |
4790654c | 1146 | |
3176ff3e MT |
1147 | struct net_device *netdev; |
1148 | struct pci_dev *pdev; | |
2956640d | 1149 | int pci_using_dac; |
6c80b18d | 1150 | struct net_device_stats net_stats; |
3176ff3e MT |
1151 | int mtu; |
1152 | int portnum; | |
3276fbad | 1153 | u8 physical_port; |
48bfd1e0 | 1154 | u16 tx_context_id; |
3176ff3e | 1155 | |
623621b0 DP |
1156 | uint8_t mc_enabled; |
1157 | uint8_t max_mc_count; | |
c9fc891f | 1158 | nx_mac_list_t *mac_list; |
623621b0 | 1159 | |
2956640d DP |
1160 | struct netxen_legacy_intr_set legacy_intr; |
1161 | ||
3d396eb1 | 1162 | struct work_struct watchdog_task; |
3d396eb1 | 1163 | struct timer_list watchdog_timer; |
3176ff3e | 1164 | struct work_struct tx_timeout_task; |
3d396eb1 AK |
1165 | |
1166 | u32 curr_window; | |
3ce06a32 DP |
1167 | u32 crb_win; |
1168 | rwlock_t adapter_lock; | |
2956640d | 1169 | |
3d396eb1 | 1170 | u32 cmd_producer; |
f305f789 | 1171 | __le32 *cmd_consumer; |
3d396eb1 | 1172 | u32 last_cmd_consumer; |
7830b22c DP |
1173 | u32 crb_addr_cmd_producer; |
1174 | u32 crb_addr_cmd_consumer; | |
d8b100c5 | 1175 | spinlock_t tx_clean_lock; |
ba53e6b4 | 1176 | |
438627c7 DP |
1177 | u32 num_txd; |
1178 | u32 num_rxd; | |
1179 | u32 num_jumbo_rxd; | |
1180 | u32 num_lro_rxd; | |
3d396eb1 | 1181 | |
48bfd1e0 | 1182 | int max_rds_rings; |
d8b100c5 | 1183 | int max_sds_rings; |
48bfd1e0 | 1184 | |
3d396eb1 AK |
1185 | u32 flags; |
1186 | u32 irq; | |
1187 | int driver_mismatch; | |
cb8011ad | 1188 | u32 temp; |
3d396eb1 | 1189 | |
2956640d | 1190 | u32 fw_major; |
1e2d0059 | 1191 | u32 fw_version; |
2956640d | 1192 | |
d8b100c5 | 1193 | int msix_supported; |
2956640d DP |
1194 | struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; |
1195 | ||
3d396eb1 | 1196 | struct netxen_adapter_stats stats; |
4790654c | 1197 | |
3176ff3e MT |
1198 | u16 link_speed; |
1199 | u16 link_duplex; | |
1200 | u16 state; | |
1201 | u16 link_autoneg; | |
200eef20 | 1202 | int rx_csum; |
3d396eb1 AK |
1203 | |
1204 | struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */ | |
1205 | ||
1206 | /* | |
1207 | * Receive instances. These can be either one per port, | |
1208 | * or one per peg, etc. | |
1209 | */ | |
becf46a0 | 1210 | struct netxen_recv_context recv_ctx; |
3d396eb1 AK |
1211 | |
1212 | int is_up; | |
ed25ffa1 | 1213 | struct netxen_dummy_dma dummy_dma; |
cd1f8160 | 1214 | nx_nic_intr_coalesce_t coal; |
ed25ffa1 AK |
1215 | |
1216 | /* Context interface shared between card and host */ | |
1217 | struct netxen_ring_ctx *ctx_desc; | |
ed25ffa1 | 1218 | dma_addr_t ctx_desc_phys_addr; |
2d1a3bbd | 1219 | int intr_scheme; |
443be796 | 1220 | int msi_mode; |
13ba9c77 MT |
1221 | int (*enable_phy_interrupts) (struct netxen_adapter *); |
1222 | int (*disable_phy_interrupts) (struct netxen_adapter *); | |
3176ff3e MT |
1223 | int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t); |
1224 | int (*set_mtu) (struct netxen_adapter *, int); | |
9ad27643 | 1225 | int (*set_promisc) (struct netxen_adapter *, u32); |
13ba9c77 MT |
1226 | int (*phy_read) (struct netxen_adapter *, long reg, u32 *); |
1227 | int (*phy_write) (struct netxen_adapter *, long reg, u32 val); | |
80922fbc | 1228 | int (*init_port) (struct netxen_adapter *, int); |
3176ff3e | 1229 | int (*stop_port) (struct netxen_adapter *); |
3ce06a32 DP |
1230 | |
1231 | int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int); | |
1232 | int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int); | |
1233 | int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int); | |
1234 | int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int); | |
1235 | int (*pci_write_immediate)(struct netxen_adapter *, u64, u32); | |
1236 | u32 (*pci_read_immediate)(struct netxen_adapter *, u64); | |
1237 | void (*pci_write_normalize)(struct netxen_adapter *, u64, u32); | |
1238 | u32 (*pci_read_normalize)(struct netxen_adapter *, u64); | |
1239 | unsigned long (*pci_set_window)(struct netxen_adapter *, | |
1240 | unsigned long long); | |
3d396eb1 AK |
1241 | }; /* netxen_adapter structure */ |
1242 | ||
96acb6eb DP |
1243 | /* |
1244 | * NetXen dma watchdog control structure | |
1245 | * | |
1246 | * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive | |
1247 | * Bit 1 : disable_request => 1 req disable dma watchdog | |
1248 | * Bit 2 : enable_request => 1 req enable dma watchdog | |
1249 | * Bit 3-31 : unused | |
1250 | */ | |
1251 | ||
1252 | #define netxen_set_dma_watchdog_disable_req(config_word) \ | |
1253 | _netxen_set_bits(config_word, 1, 1, 1) | |
1254 | #define netxen_set_dma_watchdog_enable_req(config_word) \ | |
1255 | _netxen_set_bits(config_word, 2, 1, 1) | |
1256 | #define netxen_get_dma_watchdog_enabled(config_word) \ | |
1257 | ((config_word) & 0x1) | |
1258 | #define netxen_get_dma_watchdog_disabled(config_word) \ | |
1259 | (((config_word) >> 1) & 0x1) | |
1260 | ||
3d396eb1 AK |
1261 | /* Max number of xmit producer threads that can run simultaneously */ |
1262 | #define MAX_XMIT_PRODUCERS 16 | |
1263 | ||
cb8011ad AK |
1264 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
1265 | ((adapter)->ahw.pci_base0 + (off)) | |
1266 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | |
1267 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) | |
1268 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ | |
1269 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) | |
1270 | ||
1271 | static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter, | |
1272 | unsigned long off) | |
1273 | { | |
1274 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
1275 | return (adapter->ahw.pci_base0 + off); | |
1276 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
1277 | (off >= SECOND_PAGE_GROUP_START)) { | |
1278 | return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START); | |
1279 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
1280 | (off >= THIRD_PAGE_GROUP_START)) { | |
1281 | return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START); | |
1282 | } | |
1283 | return NULL; | |
1284 | } | |
1285 | ||
1286 | static inline void __iomem *pci_base(struct netxen_adapter *adapter, | |
1287 | unsigned long off) | |
1288 | { | |
1289 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
1290 | return adapter->ahw.pci_base0; | |
1291 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
1292 | (off >= SECOND_PAGE_GROUP_START)) { | |
1293 | return adapter->ahw.pci_base1; | |
1294 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
1295 | (off >= THIRD_PAGE_GROUP_START)) { | |
1296 | return adapter->ahw.pci_base2; | |
1297 | } | |
1298 | return NULL; | |
1299 | } | |
1300 | ||
13ba9c77 MT |
1301 | int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter); |
1302 | int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter); | |
1303 | int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter); | |
1304 | int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter); | |
13ba9c77 | 1305 | int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg, |
a608ab9c | 1306 | __u32 * readval); |
13ba9c77 | 1307 | int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, |
a608ab9c | 1308 | long reg, __u32 val); |
3d396eb1 AK |
1309 | |
1310 | /* Functions available from netxen_nic_hw.c */ | |
3176ff3e MT |
1311 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); |
1312 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); | |
3d396eb1 AK |
1313 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); |
1314 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); | |
1315 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); | |
3ce06a32 DP |
1316 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value); |
1317 | void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value); | |
1318 | void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value); | |
3d396eb1 AK |
1319 | |
1320 | int netxen_nic_get_board_info(struct netxen_adapter *adapter); | |
1e2d0059 | 1321 | void netxen_nic_get_firmware_info(struct netxen_adapter *adapter); |
0b72e659 | 1322 | int netxen_nic_wol_supported(struct netxen_adapter *adapter); |
3ce06a32 DP |
1323 | |
1324 | int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, | |
1325 | ulong off, void *data, int len); | |
1326 | int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, | |
1327 | ulong off, void *data, int len); | |
1328 | int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, | |
1329 | u64 off, void *data, int size); | |
1330 | int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, | |
1331 | u64 off, void *data, int size); | |
1332 | int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter, | |
1333 | u64 off, u32 data); | |
1334 | u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off); | |
1335 | void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter, | |
1336 | u64 off, u32 data); | |
1337 | u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off); | |
1338 | unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, | |
1339 | unsigned long long addr); | |
1340 | void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, | |
1341 | u32 wndw); | |
1342 | ||
1343 | int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, | |
1344 | ulong off, void *data, int len); | |
1345 | int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, | |
1346 | ulong off, void *data, int len); | |
1347 | int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, | |
1348 | u64 off, void *data, int size); | |
1349 | int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, | |
1350 | u64 off, void *data, int size); | |
3d396eb1 AK |
1351 | void netxen_crb_writelit_adapter(struct netxen_adapter *adapter, |
1352 | unsigned long off, int data); | |
3ce06a32 DP |
1353 | int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, |
1354 | u64 off, u32 data); | |
1355 | u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off); | |
1356 | void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter, | |
1357 | u64 off, u32 data); | |
1358 | u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off); | |
1359 | unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |
1360 | unsigned long long addr); | |
3d396eb1 AK |
1361 | |
1362 | /* Functions from netxen_nic_init.c */ | |
ed25ffa1 AK |
1363 | void netxen_free_adapter_offload(struct netxen_adapter *adapter); |
1364 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter); | |
96acb6eb | 1365 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); |
2956640d | 1366 | int netxen_receive_peg_ready(struct netxen_adapter *adapter); |
96acb6eb | 1367 | int netxen_load_firmware(struct netxen_adapter *adapter); |
3d396eb1 | 1368 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); |
2956640d | 1369 | |
3d396eb1 | 1370 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); |
4790654c | 1371 | int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 | 1372 | u8 *bytes, size_t size); |
4790654c | 1373 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
1374 | u8 *bytes, size_t size); |
1375 | int netxen_flash_unlock(struct netxen_adapter *adapter); | |
1376 | int netxen_backup_crbinit(struct netxen_adapter *adapter); | |
1377 | int netxen_flash_erase_secondary(struct netxen_adapter *adapter); | |
1378 | int netxen_flash_erase_primary(struct netxen_adapter *adapter); | |
e45d9ab4 | 1379 | void netxen_halt_pegs(struct netxen_adapter *adapter); |
27d2ab54 | 1380 | |
cb8011ad | 1381 | int netxen_rom_se(struct netxen_adapter *adapter, int addr); |
3d396eb1 | 1382 | |
2956640d DP |
1383 | int netxen_alloc_sw_resources(struct netxen_adapter *adapter); |
1384 | void netxen_free_sw_resources(struct netxen_adapter *adapter); | |
1385 | ||
1386 | int netxen_alloc_hw_resources(struct netxen_adapter *adapter); | |
1387 | void netxen_free_hw_resources(struct netxen_adapter *adapter); | |
1388 | ||
1389 | void netxen_release_rx_buffers(struct netxen_adapter *adapter); | |
1390 | void netxen_release_tx_buffers(struct netxen_adapter *adapter); | |
1391 | ||
3d396eb1 AK |
1392 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); |
1393 | int netxen_init_firmware(struct netxen_adapter *adapter); | |
3d396eb1 | 1394 | void netxen_nic_clear_stats(struct netxen_adapter *adapter); |
6d5aefb8 | 1395 | void netxen_watchdog_task(struct work_struct *work); |
d8b100c5 DP |
1396 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, |
1397 | struct nx_host_rds_ring *rds_ring); | |
05aaa02d | 1398 | int netxen_process_cmd_ring(struct netxen_adapter *adapter); |
d8b100c5 | 1399 | int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max); |
c9fc891f DP |
1400 | void netxen_p2_nic_set_multi(struct net_device *netdev); |
1401 | void netxen_p3_nic_set_multi(struct net_device *netdev); | |
06e9d9f9 | 1402 | void netxen_p3_free_mac_list(struct netxen_adapter *adapter); |
9ad27643 | 1403 | int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32); |
cd1f8160 | 1404 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter); |
d8b100c5 | 1405 | int netxen_config_rss(struct netxen_adapter *adapter, int enable); |
48bfd1e0 | 1406 | |
9ad27643 | 1407 | int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu); |
3d396eb1 | 1408 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); |
48bfd1e0 | 1409 | |
3d396eb1 AK |
1410 | int netxen_nic_set_mac(struct net_device *netdev, void *p); |
1411 | struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); | |
1412 | ||
c9fc891f DP |
1413 | void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, |
1414 | uint32_t crb_producer); | |
cb8011ad AK |
1415 | |
1416 | /* | |
1417 | * NetXen Board information | |
1418 | */ | |
1419 | ||
e4c93c81 | 1420 | #define NETXEN_MAX_SHORT_NAME 32 |
71bd7877 | 1421 | struct netxen_brdinfo { |
e98e3350 | 1422 | int brdtype; /* type of board */ |
cb8011ad AK |
1423 | long ports; /* max no of physical ports */ |
1424 | char short_name[NETXEN_MAX_SHORT_NAME]; | |
71bd7877 | 1425 | }; |
cb8011ad | 1426 | |
71bd7877 | 1427 | static const struct netxen_brdinfo netxen_boards[] = { |
cb8011ad AK |
1428 | {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, |
1429 | {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, | |
1430 | {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, | |
1431 | {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, | |
1432 | {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, | |
1433 | {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, | |
e4c93c81 DP |
1434 | {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "}, |
1435 | {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"}, | |
1436 | {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"}, | |
1437 | {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"}, | |
1438 | {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"}, | |
1439 | {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"}, | |
1440 | {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"}, | |
1441 | {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"}, | |
a70f9393 DP |
1442 | {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"}, |
1443 | {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"}, | |
1444 | {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"}, | |
e4c93c81 DP |
1445 | {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"}, |
1446 | {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"} | |
cb8011ad AK |
1447 | }; |
1448 | ||
ff8ac609 | 1449 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards) |
cb8011ad | 1450 | |
cb8011ad AK |
1451 | static inline void get_brd_name_by_type(u32 type, char *name) |
1452 | { | |
1453 | int i, found = 0; | |
1454 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1455 | if (netxen_boards[i].brdtype == type) { | |
1456 | strcpy(name, netxen_boards[i].short_name); | |
1457 | found = 1; | |
1458 | break; | |
1459 | } | |
1460 | ||
3d396eb1 | 1461 | } |
cb8011ad AK |
1462 | if (!found) |
1463 | name = "Unknown"; | |
3d396eb1 AK |
1464 | } |
1465 | ||
96acb6eb DP |
1466 | static inline int |
1467 | dma_watchdog_shutdown_request(struct netxen_adapter *adapter) | |
1468 | { | |
1469 | u32 ctrl; | |
1470 | ||
1471 | /* check if already inactive */ | |
3ce06a32 | 1472 | if (adapter->hw_read_wx(adapter, |
96acb6eb DP |
1473 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) |
1474 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1475 | ||
1476 | if (netxen_get_dma_watchdog_enabled(ctrl) == 0) | |
1477 | return 1; | |
1478 | ||
1479 | /* Send the disable request */ | |
1480 | netxen_set_dma_watchdog_disable_req(ctrl); | |
1481 | netxen_crb_writelit_adapter(adapter, | |
1482 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); | |
1483 | ||
1484 | return 0; | |
1485 | } | |
1486 | ||
1487 | static inline int | |
1488 | dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter) | |
1489 | { | |
1490 | u32 ctrl; | |
1491 | ||
3ce06a32 | 1492 | if (adapter->hw_read_wx(adapter, |
96acb6eb DP |
1493 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) |
1494 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1495 | ||
ceded32f | 1496 | return (netxen_get_dma_watchdog_enabled(ctrl) == 0); |
96acb6eb DP |
1497 | } |
1498 | ||
1499 | static inline int | |
1500 | dma_watchdog_wakeup(struct netxen_adapter *adapter) | |
1501 | { | |
1502 | u32 ctrl; | |
1503 | ||
3ce06a32 | 1504 | if (adapter->hw_read_wx(adapter, |
96acb6eb DP |
1505 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) |
1506 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1507 | ||
1508 | if (netxen_get_dma_watchdog_enabled(ctrl)) | |
1509 | return 1; | |
1510 | ||
1511 | /* send the wakeup request */ | |
1512 | netxen_set_dma_watchdog_enable_req(ctrl); | |
1513 | ||
1514 | netxen_crb_writelit_adapter(adapter, | |
1515 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); | |
1516 | ||
1517 | return 0; | |
1518 | } | |
1519 | ||
1520 | ||
9dc28efe DP |
1521 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
1522 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); | |
3d396eb1 AK |
1523 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
1524 | extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, | |
1525 | int *valp); | |
1526 | ||
1527 | extern struct ethtool_ops netxen_nic_ethtool_ops; | |
1528 | ||
1529 | #endif /* __NETXEN_NIC_H_ */ |