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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | */ | |
29 | ||
30 | #ifndef _NETXEN_NIC_H_ | |
31 | #define _NETXEN_NIC_H_ | |
32 | ||
3d396eb1 AK |
33 | #include <linux/module.h> |
34 | #include <linux/kernel.h> | |
35 | #include <linux/types.h> | |
36 | #include <linux/compiler.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/ioport.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/etherdevice.h> | |
44 | #include <linux/ip.h> | |
45 | #include <linux/in.h> | |
46 | #include <linux/tcp.h> | |
47 | #include <linux/skbuff.h> | |
48 | #include <linux/version.h> | |
49 | ||
50 | #include <linux/ethtool.h> | |
51 | #include <linux/mii.h> | |
52 | #include <linux/interrupt.h> | |
53 | #include <linux/timer.h> | |
54 | ||
55 | #include <linux/mm.h> | |
56 | #include <linux/mman.h> | |
57 | ||
58 | #include <asm/system.h> | |
59 | #include <asm/io.h> | |
60 | #include <asm/byteorder.h> | |
61 | #include <asm/uaccess.h> | |
62 | #include <asm/pgtable.h> | |
63 | ||
64 | #include "netxen_nic_hw.h" | |
65 | ||
ed25ffa1 | 66 | #define _NETXEN_NIC_LINUX_MAJOR 3 |
6d1495f2 | 67 | #define _NETXEN_NIC_LINUX_MINOR 4 |
001a731e | 68 | #define _NETXEN_NIC_LINUX_SUBVERSION 18 |
69 | #define NETXEN_NIC_LINUX_VERSIONID "3.4.18" | |
27d2ab54 | 70 | |
0d04761d MT |
71 | #define NETXEN_NUM_FLASH_SECTORS (64) |
72 | #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024) | |
73 | #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \ | |
74 | * NETXEN_FLASH_SECTOR_SIZE) | |
3d396eb1 | 75 | |
0c25cfe1 LCMT |
76 | #define PHAN_VENDOR_ID 0x4040 |
77 | ||
3d396eb1 AK |
78 | #define RCV_DESC_RINGSIZE \ |
79 | (sizeof(struct rcv_desc) * adapter->max_rx_desc_count) | |
80 | #define STATUS_DESC_RINGSIZE \ | |
81 | (sizeof(struct status_desc)* adapter->max_rx_desc_count) | |
ed25ffa1 AK |
82 | #define LRO_DESC_RINGSIZE \ |
83 | (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count) | |
3d396eb1 AK |
84 | #define TX_RINGSIZE \ |
85 | (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count) | |
86 | #define RCV_BUFFSIZE \ | |
87 | (sizeof(struct netxen_rx_buffer) * rcv_desc->max_rx_desc_count) | |
ba53e6b4 | 88 | #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) |
3d396eb1 | 89 | |
ed25ffa1 AK |
90 | #define NETXEN_NETDEV_STATUS 0x1 |
91 | #define NETXEN_RCV_PRODUCER_OFFSET 0 | |
92 | #define NETXEN_RCV_PEG_DB_ID 2 | |
93 | #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 | |
27d2ab54 | 94 | #define FLASH_SUCCESS 0 |
3d396eb1 AK |
95 | |
96 | #define ADDR_IN_WINDOW1(off) \ | |
97 | ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 | |
98 | ||
4790654c JG |
99 | /* |
100 | * normalize a 64MB crb address to 32MB PCI window | |
3d396eb1 AK |
101 | * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 |
102 | */ | |
80922fbc AK |
103 | #define NETXEN_CRB_NORMAL(reg) \ |
104 | ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) | |
cb8011ad | 105 | |
3d396eb1 | 106 | #define NETXEN_CRB_NORMALIZE(adapter, reg) \ |
cb8011ad AK |
107 | pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) |
108 | ||
ed25ffa1 AK |
109 | #define DB_NORMALIZE(adapter, off) \ |
110 | (adapter->ahw.db_base + (off)) | |
111 | ||
112 | #define NX_P2_C0 0x24 | |
113 | #define NX_P2_C1 0x25 | |
114 | ||
cb8011ad | 115 | #define FIRST_PAGE_GROUP_START 0 |
ed25ffa1 | 116 | #define FIRST_PAGE_GROUP_END 0x100000 |
cb8011ad | 117 | |
78403a92 MT |
118 | #define SECOND_PAGE_GROUP_START 0x6000000 |
119 | #define SECOND_PAGE_GROUP_END 0x68BC000 | |
cb8011ad AK |
120 | |
121 | #define THIRD_PAGE_GROUP_START 0x70E4000 | |
122 | #define THIRD_PAGE_GROUP_END 0x8000000 | |
123 | ||
124 | #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START | |
125 | #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START | |
126 | #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START | |
3d396eb1 | 127 | |
ed25ffa1 | 128 | #define MAX_RX_BUFFER_LENGTH 1760 |
bd56c6b1 | 129 | #define MAX_RX_JUMBO_BUFFER_LENGTH 8062 |
ed25ffa1 AK |
130 | #define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512) |
131 | #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2) | |
3d396eb1 | 132 | #define RX_JUMBO_DMA_MAP_LEN \ |
ed25ffa1 AK |
133 | (MAX_RX_JUMBO_BUFFER_LENGTH - 2) |
134 | #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2) | |
3d396eb1 AK |
135 | #define NETXEN_ROM_ROUNDUP 0x80000000ULL |
136 | ||
137 | /* | |
138 | * Maximum number of ring contexts | |
139 | */ | |
140 | #define MAX_RING_CTX 1 | |
141 | ||
142 | /* Opcodes to be used with the commands */ | |
143 | enum { | |
144 | TX_ETHER_PKT = 0x01, | |
145 | /* The following opcodes are for IP checksum */ | |
146 | TX_TCP_PKT, | |
147 | TX_UDP_PKT, | |
148 | TX_IP_PKT, | |
149 | TX_TCP_LSO, | |
150 | TX_IPSEC, | |
151 | TX_IPSEC_CMD | |
152 | }; | |
153 | ||
154 | /* The following opcodes are for internal consumption. */ | |
155 | #define NETXEN_CONTROL_OP 0x10 | |
156 | #define PEGNET_REQUEST 0x11 | |
157 | ||
158 | #define MAX_NUM_CARDS 4 | |
159 | ||
160 | #define MAX_BUFFERS_PER_CMD 32 | |
161 | ||
162 | /* | |
163 | * Following are the states of the Phantom. Phantom will set them and | |
164 | * Host will read to check if the fields are correct. | |
165 | */ | |
166 | #define PHAN_INITIALIZE_START 0xff00 | |
167 | #define PHAN_INITIALIZE_FAILED 0xffff | |
168 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
169 | ||
170 | /* Host writes the following to notify that it has done the init-handshake */ | |
171 | #define PHAN_INITIALIZE_ACK 0xf00f | |
172 | ||
ed25ffa1 | 173 | #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */ |
3d396eb1 AK |
174 | |
175 | /* descriptor types */ | |
176 | #define RCV_DESC_NORMAL 0x01 | |
177 | #define RCV_DESC_JUMBO 0x02 | |
ed25ffa1 | 178 | #define RCV_DESC_LRO 0x04 |
3d396eb1 AK |
179 | #define RCV_DESC_NORMAL_CTXID 0 |
180 | #define RCV_DESC_JUMBO_CTXID 1 | |
ed25ffa1 | 181 | #define RCV_DESC_LRO_CTXID 2 |
3d396eb1 AK |
182 | |
183 | #define RCV_DESC_TYPE(ID) \ | |
ed25ffa1 AK |
184 | ((ID == RCV_DESC_JUMBO_CTXID) \ |
185 | ? RCV_DESC_JUMBO \ | |
186 | : ((ID == RCV_DESC_LRO_CTXID) \ | |
187 | ? RCV_DESC_LRO : \ | |
188 | (RCV_DESC_NORMAL))) | |
3d396eb1 | 189 | |
ba53e6b4 | 190 | #define MAX_CMD_DESCRIPTORS 4096 |
bd56c6b1 | 191 | #define MAX_RCV_DESCRIPTORS 16384 |
6c80b18d | 192 | #define MAX_CMD_DESCRIPTORS_HOST (MAX_CMD_DESCRIPTORS / 4) |
13ba9c77 | 193 | #define MAX_RCV_DESCRIPTORS_1G (MAX_RCV_DESCRIPTORS / 4) |
bd56c6b1 AK |
194 | #define MAX_JUMBO_RCV_DESCRIPTORS 1024 |
195 | #define MAX_LRO_RCV_DESCRIPTORS 64 | |
3d396eb1 AK |
196 | #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS |
197 | #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS | |
198 | #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS | |
199 | #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS | |
3d396eb1 | 200 | #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8) |
ed25ffa1 AK |
201 | #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \ |
202 | MAX_LRO_RCV_DESCRIPTORS) | |
3d396eb1 AK |
203 | #define MIN_TX_COUNT 4096 |
204 | #define MIN_RX_COUNT 4096 | |
ed25ffa1 AK |
205 | #define NETXEN_CTX_SIGNATURE 0xdee0 |
206 | #define NETXEN_RCV_PRODUCER(ringid) (ringid) | |
3d396eb1 AK |
207 | #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */ |
208 | ||
209 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
210 | #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 | |
211 | ||
212 | #define get_next_index(index, length) \ | |
213 | (((index) + 1) & ((length) - 1)) | |
214 | ||
215 | #define get_index_range(index,length,count) \ | |
216 | (((index) + (count)) & ((length) - 1)) | |
217 | ||
ed25ffa1 | 218 | #define MPORT_SINGLE_FUNCTION_MODE 0x1111 |
3176ff3e | 219 | #define MPORT_MULTI_FUNCTION_MODE 0x2222 |
ed25ffa1 | 220 | |
3176ff3e | 221 | #include "netxen_nic_phan_reg.h" |
ed25ffa1 | 222 | extern unsigned long long netxen_dma_mask; |
b58ecad8 | 223 | extern unsigned long last_schedule_time; |
ed25ffa1 AK |
224 | |
225 | /* | |
226 | * NetXen host-peg signal message structure | |
227 | * | |
228 | * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx | |
229 | * Bit 2 : priv_id => must be 1 | |
230 | * Bit 3-17 : count => for doorbell | |
231 | * Bit 18-27 : ctx_id => Context id | |
232 | * Bit 28-31 : opcode | |
233 | */ | |
234 | ||
235 | typedef u32 netxen_ctx_msg; | |
236 | ||
ed25ffa1 | 237 | #define netxen_set_msg_peg_id(config_word, val) \ |
a608ab9c | 238 | ((config_word) &= ~3, (config_word) |= val & 3) |
ed25ffa1 | 239 | #define netxen_set_msg_privid(config_word) \ |
a608ab9c | 240 | ((config_word) |= 1 << 2) |
ed25ffa1 | 241 | #define netxen_set_msg_count(config_word, val) \ |
a608ab9c | 242 | ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) |
ed25ffa1 | 243 | #define netxen_set_msg_ctxid(config_word, val) \ |
a608ab9c | 244 | ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) |
ed25ffa1 | 245 | #define netxen_set_msg_opcode(config_word, val) \ |
82581174 | 246 | ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) |
ed25ffa1 AK |
247 | |
248 | struct netxen_rcv_context { | |
a608ab9c AV |
249 | __le64 rcv_ring_addr; |
250 | __le32 rcv_ring_size; | |
251 | __le32 rsrvd; | |
ed25ffa1 AK |
252 | }; |
253 | ||
254 | struct netxen_ring_ctx { | |
255 | ||
256 | /* one command ring */ | |
a608ab9c AV |
257 | __le64 cmd_consumer_offset; |
258 | __le64 cmd_ring_addr; | |
259 | __le32 cmd_ring_size; | |
260 | __le32 rsrvd; | |
ed25ffa1 AK |
261 | |
262 | /* three receive rings */ | |
263 | struct netxen_rcv_context rcv_ctx[3]; | |
264 | ||
265 | /* one status ring */ | |
a608ab9c AV |
266 | __le64 sts_ring_addr; |
267 | __le32 sts_ring_size; | |
ed25ffa1 | 268 | |
a608ab9c | 269 | __le32 ctx_id; |
ed25ffa1 AK |
270 | } __attribute__ ((aligned(64))); |
271 | ||
3d396eb1 AK |
272 | /* |
273 | * Following data structures describe the descriptors that will be used. | |
274 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
275 | * we are doing LSO (above the 1500 size packet) only. | |
276 | */ | |
277 | ||
278 | /* | |
279 | * The size of reference handle been changed to 16 bits to pass the MSS fields | |
280 | * for the LSO packet | |
281 | */ | |
282 | ||
283 | #define FLAGS_CHECKSUM_ENABLED 0x01 | |
284 | #define FLAGS_LSO_ENABLED 0x02 | |
285 | #define FLAGS_IPSEC_SA_ADD 0x04 | |
286 | #define FLAGS_IPSEC_SA_DELETE 0x08 | |
287 | #define FLAGS_VLAN_TAGGED 0x10 | |
288 | ||
ed25ffa1 AK |
289 | #define netxen_set_cmd_desc_port(cmd_desc, var) \ |
290 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
6c80b18d MT |
291 | #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \ |
292 | ((cmd_desc)->port_ctxid |= ((var) & 0xF0)) | |
3d396eb1 | 293 | |
ed25ffa1 | 294 | #define netxen_set_cmd_desc_flags(cmd_desc, val) \ |
5dc16268 DP |
295 | (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \ |
296 | ~cpu_to_le16(0x7f)) | cpu_to_le16((val) & 0x7f) | |
ed25ffa1 | 297 | #define netxen_set_cmd_desc_opcode(cmd_desc, val) \ |
5dc16268 DP |
298 | (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \ |
299 | ~cpu_to_le16((u16)0x3f << 7)) | cpu_to_le16(((val) & 0x3f) << 7) | |
ed25ffa1 AK |
300 | |
301 | #define netxen_set_cmd_desc_num_of_buff(cmd_desc, val) \ | |
5dc16268 DP |
302 | (cmd_desc)->num_of_buffers_total_length = \ |
303 | ((cmd_desc)->num_of_buffers_total_length & \ | |
304 | ~cpu_to_le32(0xff)) | cpu_to_le32((val) & 0xff) | |
ed25ffa1 | 305 | #define netxen_set_cmd_desc_totallength(cmd_desc, val) \ |
5dc16268 DP |
306 | (cmd_desc)->num_of_buffers_total_length = \ |
307 | ((cmd_desc)->num_of_buffers_total_length & \ | |
308 | ~cpu_to_le32((u32)0xffffff << 8)) | \ | |
309 | cpu_to_le32(((val) & 0xffffff) << 8) | |
ed25ffa1 AK |
310 | |
311 | #define netxen_get_cmd_desc_opcode(cmd_desc) \ | |
5dc16268 | 312 | ((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003f) |
ed25ffa1 | 313 | #define netxen_get_cmd_desc_totallength(cmd_desc) \ |
5dc16268 | 314 | ((le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8) & 0xffffff) |
3d396eb1 AK |
315 | |
316 | struct cmd_desc_type0 { | |
ed25ffa1 AK |
317 | u8 tcp_hdr_offset; /* For LSO only */ |
318 | u8 ip_hdr_offset; /* For LSO only */ | |
319 | /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */ | |
a608ab9c | 320 | __le16 flags_opcode; |
ed25ffa1 AK |
321 | /* Bit pattern: 0-7 total number of segments, |
322 | 8-31 Total size of the packet */ | |
a608ab9c | 323 | __le32 num_of_buffers_total_length; |
3d396eb1 AK |
324 | union { |
325 | struct { | |
a608ab9c AV |
326 | __le32 addr_low_part2; |
327 | __le32 addr_high_part2; | |
3d396eb1 | 328 | }; |
a608ab9c | 329 | __le64 addr_buffer2; |
3d396eb1 AK |
330 | }; |
331 | ||
a608ab9c AV |
332 | __le16 reference_handle; /* changed to u16 to add mss */ |
333 | __le16 mss; /* passed by NDIS_PACKET for LSO */ | |
3d396eb1 AK |
334 | /* Bit pattern 0-3 port, 0-3 ctx id */ |
335 | u8 port_ctxid; | |
336 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
a608ab9c | 337 | __le16 conn_id; /* IPSec offoad only */ |
3d396eb1 AK |
338 | |
339 | union { | |
340 | struct { | |
a608ab9c AV |
341 | __le32 addr_low_part3; |
342 | __le32 addr_high_part3; | |
3d396eb1 | 343 | }; |
a608ab9c | 344 | __le64 addr_buffer3; |
3d396eb1 | 345 | }; |
3d396eb1 AK |
346 | union { |
347 | struct { | |
a608ab9c AV |
348 | __le32 addr_low_part1; |
349 | __le32 addr_high_part1; | |
3d396eb1 | 350 | }; |
a608ab9c | 351 | __le64 addr_buffer1; |
3d396eb1 AK |
352 | }; |
353 | ||
a608ab9c AV |
354 | __le16 buffer1_length; |
355 | __le16 buffer2_length; | |
356 | __le16 buffer3_length; | |
357 | __le16 buffer4_length; | |
3d396eb1 AK |
358 | |
359 | union { | |
360 | struct { | |
a608ab9c AV |
361 | __le32 addr_low_part4; |
362 | __le32 addr_high_part4; | |
3d396eb1 | 363 | }; |
a608ab9c | 364 | __le64 addr_buffer4; |
3d396eb1 AK |
365 | }; |
366 | ||
a608ab9c | 367 | __le64 unused; |
ed25ffa1 | 368 | |
3d396eb1 AK |
369 | } __attribute__ ((aligned(64))); |
370 | ||
371 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
372 | struct rcv_desc { | |
a608ab9c AV |
373 | __le16 reference_handle; |
374 | __le16 reserved; | |
375 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
376 | __le64 addr_buffer; | |
3d396eb1 AK |
377 | }; |
378 | ||
379 | /* opcode field in status_desc */ | |
380 | #define RCV_NIC_PKT (0xA) | |
381 | #define STATUS_NIC_PKT ((RCV_NIC_PKT) << 12) | |
382 | ||
383 | /* for status field in status_desc */ | |
384 | #define STATUS_NEED_CKSUM (1) | |
385 | #define STATUS_CKSUM_OK (2) | |
386 | ||
387 | /* owner bits of status_desc */ | |
388 | #define STATUS_OWNER_HOST (0x1) | |
389 | #define STATUS_OWNER_PHANTOM (0x2) | |
390 | ||
391 | #define NETXEN_PROT_IP (1) | |
392 | #define NETXEN_PROT_UNKNOWN (0) | |
393 | ||
394 | /* Note: sizeof(status_desc) should always be a mutliple of 2 */ | |
ed25ffa1 AK |
395 | |
396 | #define netxen_get_sts_desc_lro_cnt(status_desc) \ | |
397 | ((status_desc)->lro & 0x7F) | |
398 | #define netxen_get_sts_desc_lro_last_frag(status_desc) \ | |
399 | (((status_desc)->lro & 0x80) >> 7) | |
400 | ||
5dc16268 DP |
401 | #define netxen_get_sts_port(sts_data) \ |
402 | ((sts_data) & 0x0F) | |
403 | #define netxen_get_sts_status(sts_data) \ | |
404 | (((sts_data) >> 4) & 0x0F) | |
405 | #define netxen_get_sts_type(sts_data) \ | |
406 | (((sts_data) >> 8) & 0x0F) | |
407 | #define netxen_get_sts_totallength(sts_data) \ | |
408 | (((sts_data) >> 12) & 0xFFFF) | |
409 | #define netxen_get_sts_refhandle(sts_data) \ | |
410 | (((sts_data) >> 28) & 0xFFFF) | |
411 | #define netxen_get_sts_prot(sts_data) \ | |
412 | (((sts_data) >> 44) & 0x0F) | |
413 | #define netxen_get_sts_opcode(sts_data) \ | |
414 | (((sts_data) >> 58) & 0x03F) | |
415 | ||
ed25ffa1 | 416 | #define netxen_get_sts_owner(status_desc) \ |
a608ab9c | 417 | ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03) |
5dc16268 DP |
418 | #define netxen_set_sts_owner(status_desc, val) { \ |
419 | (status_desc)->status_desc_data = \ | |
420 | ((status_desc)->status_desc_data & \ | |
421 | ~cpu_to_le64(0x3ULL << 56)) | \ | |
422 | cpu_to_le64((u64)((val) & 0x3) << 56); \ | |
423 | } | |
3d396eb1 AK |
424 | |
425 | struct status_desc { | |
ed25ffa1 AK |
426 | /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length |
427 | 28-43 reference_handle, 44-47 protocol, 48-52 unused | |
428 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode | |
429 | */ | |
a608ab9c AV |
430 | __le64 status_desc_data; |
431 | __le32 hash_value; | |
ed25ffa1 AK |
432 | u8 hash_type; |
433 | u8 msg_type; | |
434 | u8 unused; | |
435 | /* Bit pattern: 0-6 lro_count indicates frag sequence, | |
436 | 7 last_frag indicates last frag */ | |
437 | u8 lro; | |
6c80b18d | 438 | } __attribute__ ((aligned(16))); |
3d396eb1 AK |
439 | |
440 | enum { | |
441 | NETXEN_RCV_PEG_0 = 0, | |
442 | NETXEN_RCV_PEG_1 | |
443 | }; | |
444 | /* The version of the main data structure */ | |
445 | #define NETXEN_BDINFO_VERSION 1 | |
446 | ||
447 | /* Magic number to let user know flash is programmed */ | |
448 | #define NETXEN_BDINFO_MAGIC 0x12345678 | |
449 | ||
450 | /* Max number of Gig ports on a Phantom board */ | |
451 | #define NETXEN_MAX_PORTS 4 | |
452 | ||
453 | typedef enum { | |
454 | NETXEN_BRDTYPE_P1_BD = 0x0000, | |
455 | NETXEN_BRDTYPE_P1_SB = 0x0001, | |
456 | NETXEN_BRDTYPE_P1_SMAX = 0x0002, | |
457 | NETXEN_BRDTYPE_P1_SOCK = 0x0003, | |
458 | ||
459 | NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008, | |
460 | NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009, | |
461 | NETXEN_BRDTYPE_P2_SB35_4G = 0x000a, | |
462 | NETXEN_BRDTYPE_P2_SB31_10G = 0x000b, | |
463 | NETXEN_BRDTYPE_P2_SB31_2G = 0x000c, | |
464 | ||
465 | NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d, | |
466 | NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e, | |
467 | NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f | |
468 | } netxen_brdtype_t; | |
469 | ||
470 | typedef enum { | |
471 | NETXEN_BRDMFG_INVENTEC = 1 | |
472 | } netxen_brdmfg; | |
473 | ||
474 | typedef enum { | |
475 | MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */ | |
476 | MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */ | |
477 | MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */ | |
478 | MEM_ORG_256Mbx4 = 0x3, | |
479 | MEM_ORG_256Mbx8 = 0x4, | |
480 | MEM_ORG_256Mbx16 = 0x5, | |
481 | MEM_ORG_512Mbx4 = 0x6, | |
482 | MEM_ORG_512Mbx8 = 0x7, | |
483 | MEM_ORG_512Mbx16 = 0x8, | |
484 | MEM_ORG_1Gbx4 = 0x9, | |
485 | MEM_ORG_1Gbx8 = 0xa, | |
486 | MEM_ORG_1Gbx16 = 0xb, | |
487 | MEM_ORG_2Gbx4 = 0xc, | |
488 | MEM_ORG_2Gbx8 = 0xd, | |
489 | MEM_ORG_2Gbx16 = 0xe, | |
490 | MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */ | |
491 | MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */ | |
492 | } netxen_mn_mem_org_t; | |
493 | ||
494 | typedef enum { | |
495 | MEM_ORG_512Kx36 = 0x0, | |
496 | MEM_ORG_1Mx36 = 0x1, | |
497 | MEM_ORG_2Mx36 = 0x2 | |
498 | } netxen_sn_mem_org_t; | |
499 | ||
500 | typedef enum { | |
501 | MEM_DEPTH_4MB = 0x1, | |
502 | MEM_DEPTH_8MB = 0x2, | |
503 | MEM_DEPTH_16MB = 0x3, | |
504 | MEM_DEPTH_32MB = 0x4, | |
505 | MEM_DEPTH_64MB = 0x5, | |
506 | MEM_DEPTH_128MB = 0x6, | |
507 | MEM_DEPTH_256MB = 0x7, | |
508 | MEM_DEPTH_512MB = 0x8, | |
509 | MEM_DEPTH_1GB = 0x9, | |
510 | MEM_DEPTH_2GB = 0xa, | |
511 | MEM_DEPTH_4GB = 0xb, | |
512 | MEM_DEPTH_8GB = 0xc, | |
513 | MEM_DEPTH_16GB = 0xd, | |
514 | MEM_DEPTH_32GB = 0xe | |
515 | } netxen_mem_depth_t; | |
516 | ||
517 | struct netxen_board_info { | |
518 | u32 header_version; | |
519 | ||
520 | u32 board_mfg; | |
521 | u32 board_type; | |
522 | u32 board_num; | |
523 | u32 chip_id; | |
524 | u32 chip_minor; | |
525 | u32 chip_major; | |
526 | u32 chip_pkg; | |
527 | u32 chip_lot; | |
528 | ||
529 | u32 port_mask; /* available niu ports */ | |
530 | u32 peg_mask; /* available pegs */ | |
531 | u32 icache_ok; /* can we run with icache? */ | |
532 | u32 dcache_ok; /* can we run with dcache? */ | |
533 | u32 casper_ok; | |
534 | ||
535 | u32 mac_addr_lo_0; | |
536 | u32 mac_addr_lo_1; | |
537 | u32 mac_addr_lo_2; | |
538 | u32 mac_addr_lo_3; | |
539 | ||
540 | /* MN-related config */ | |
541 | u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */ | |
542 | u32 mn_sync_shift_cclk; | |
543 | u32 mn_sync_shift_mclk; | |
544 | u32 mn_wb_en; | |
545 | u32 mn_crystal_freq; /* in MHz */ | |
546 | u32 mn_speed; /* in MHz */ | |
547 | u32 mn_org; | |
548 | u32 mn_depth; | |
549 | u32 mn_ranks_0; /* ranks per slot */ | |
550 | u32 mn_ranks_1; /* ranks per slot */ | |
551 | u32 mn_rd_latency_0; | |
552 | u32 mn_rd_latency_1; | |
553 | u32 mn_rd_latency_2; | |
554 | u32 mn_rd_latency_3; | |
555 | u32 mn_rd_latency_4; | |
556 | u32 mn_rd_latency_5; | |
557 | u32 mn_rd_latency_6; | |
558 | u32 mn_rd_latency_7; | |
559 | u32 mn_rd_latency_8; | |
560 | u32 mn_dll_val[18]; | |
561 | u32 mn_mode_reg; /* MIU DDR Mode Register */ | |
562 | u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */ | |
563 | u32 mn_timing_0; /* MIU Memory Control Timing Rgister */ | |
564 | u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */ | |
565 | u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */ | |
566 | ||
567 | /* SN-related config */ | |
568 | u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */ | |
569 | u32 sn_pt_mode; /* pass through mode */ | |
570 | u32 sn_ecc_en; | |
571 | u32 sn_wb_en; | |
572 | u32 sn_crystal_freq; | |
573 | u32 sn_speed; | |
574 | u32 sn_org; | |
575 | u32 sn_depth; | |
576 | u32 sn_dll_tap; | |
577 | u32 sn_rd_latency; | |
578 | ||
579 | u32 mac_addr_hi_0; | |
580 | u32 mac_addr_hi_1; | |
581 | u32 mac_addr_hi_2; | |
582 | u32 mac_addr_hi_3; | |
583 | ||
584 | u32 magic; /* indicates flash has been initialized */ | |
585 | ||
586 | u32 mn_rdimm; | |
587 | u32 mn_dll_override; | |
588 | ||
589 | }; | |
590 | ||
591 | #define FLASH_NUM_PORTS (4) | |
592 | ||
593 | struct netxen_flash_mac_addr { | |
594 | u32 flash_addr[32]; | |
595 | }; | |
596 | ||
597 | struct netxen_user_old_info { | |
598 | u8 flash_md5[16]; | |
599 | u8 crbinit_md5[16]; | |
600 | u8 brdcfg_md5[16]; | |
601 | /* bootloader */ | |
602 | u32 bootld_version; | |
603 | u32 bootld_size; | |
604 | u8 bootld_md5[16]; | |
605 | /* image */ | |
606 | u32 image_version; | |
607 | u32 image_size; | |
608 | u8 image_md5[16]; | |
609 | /* primary image status */ | |
610 | u32 primary_status; | |
611 | u32 secondary_present; | |
612 | ||
613 | /* MAC address , 4 ports */ | |
614 | struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS]; | |
615 | }; | |
616 | #define FLASH_NUM_MAC_PER_PORT 32 | |
617 | struct netxen_user_info { | |
618 | u8 flash_md5[16 * 64]; | |
619 | /* bootloader */ | |
620 | u32 bootld_version; | |
621 | u32 bootld_size; | |
622 | /* image */ | |
623 | u32 image_version; | |
624 | u32 image_size; | |
625 | /* primary image status */ | |
626 | u32 primary_status; | |
627 | u32 secondary_present; | |
628 | ||
629 | /* MAC address , 4 ports, 32 address per port */ | |
630 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
631 | u32 sub_sys_id; | |
632 | u8 serial_num[32]; | |
633 | ||
634 | /* Any user defined data */ | |
635 | }; | |
636 | ||
637 | /* | |
638 | * Flash Layout - new format. | |
639 | */ | |
640 | struct netxen_new_user_info { | |
641 | u8 flash_md5[16 * 64]; | |
642 | /* bootloader */ | |
643 | u32 bootld_version; | |
644 | u32 bootld_size; | |
645 | /* image */ | |
646 | u32 image_version; | |
647 | u32 image_size; | |
648 | /* primary image status */ | |
649 | u32 primary_status; | |
650 | u32 secondary_present; | |
651 | ||
652 | /* MAC address , 4 ports, 32 address per port */ | |
653 | u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; | |
654 | u32 sub_sys_id; | |
655 | u8 serial_num[32]; | |
656 | ||
657 | /* Any user defined data */ | |
658 | }; | |
659 | ||
660 | #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6 | |
661 | #define SECONDARY_IMAGE_ABSENT 0xffffffff | |
662 | #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a | |
663 | #define PRIMARY_IMAGE_BAD 0xffffffff | |
664 | ||
665 | /* Flash memory map */ | |
666 | typedef enum { | |
0d04761d MT |
667 | NETXEN_CRBINIT_START = 0, /* Crbinit section */ |
668 | NETXEN_BRDCFG_START = 0x4000, /* board config */ | |
669 | NETXEN_INITCODE_START = 0x6000, /* pegtune code */ | |
670 | NETXEN_BOOTLD_START = 0x10000, /* bootld */ | |
671 | NETXEN_IMAGE_START = 0x43000, /* compressed image */ | |
672 | NETXEN_SECONDARY_START = 0x200000, /* backup images */ | |
673 | NETXEN_PXE_START = 0x3E0000, /* user defined region */ | |
674 | NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */ | |
675 | NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */ | |
3d396eb1 AK |
676 | } netxen_flash_map_t; |
677 | ||
0d04761d MT |
678 | #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */ |
679 | ||
680 | #define NETXEN_FLASH_START (NETXEN_CRBINIT_START) | |
681 | #define NETXEN_INIT_SECTOR (0) | |
682 | #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START) | |
683 | #define NETXEN_FLASH_CRBINIT_SIZE (0x4000) | |
684 | #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info)) | |
685 | #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32)) | |
686 | #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START) | |
687 | #define NETXEN_NUM_PRIMARY_SECTORS (0x20) | |
688 | #define NETXEN_NUM_CONFIG_SECTORS (1) | |
ed25ffa1 AK |
689 | #define PFX "NetXen: " |
690 | extern char netxen_nic_driver_name[]; | |
3d396eb1 AK |
691 | |
692 | /* Note: Make sure to not call this before adapter->port is valid */ | |
693 | #if !defined(NETXEN_DEBUG) | |
694 | #define DPRINTK(klevel, fmt, args...) do { \ | |
695 | } while (0) | |
696 | #else | |
697 | #define DPRINTK(klevel, fmt, args...) do { \ | |
698 | printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\ | |
3176ff3e MT |
699 | (adapter != NULL && adapter->netdev != NULL) ? \ |
700 | adapter->netdev->name : NULL, \ | |
3d396eb1 AK |
701 | ## args); } while(0) |
702 | #endif | |
703 | ||
704 | /* Number of status descriptors to handle per interrupt */ | |
705 | #define MAX_STATUS_HANDLE (128) | |
706 | ||
707 | /* | |
708 | * netxen_skb_frag{} is to contain mapping info for each SG list. This | |
709 | * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. | |
710 | */ | |
711 | struct netxen_skb_frag { | |
712 | u64 dma; | |
713 | u32 length; | |
714 | }; | |
715 | ||
6c80b18d MT |
716 | #define _netxen_set_bits(config_word, start, bits, val) {\ |
717 | unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\ | |
718 | unsigned long long __tvalue = (val); \ | |
719 | (config_word) &= ~__tmask; \ | |
720 | (config_word) |= (((__tvalue) << (start)) & __tmask); \ | |
721 | } | |
4790654c | 722 | |
6c80b18d MT |
723 | #define _netxen_clear_bits(config_word, start, bits) {\ |
724 | unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \ | |
725 | (config_word) &= ~__tmask; \ | |
4790654c | 726 | } |
6c80b18d | 727 | |
3d396eb1 AK |
728 | /* Following defines are for the state of the buffers */ |
729 | #define NETXEN_BUFFER_FREE 0 | |
730 | #define NETXEN_BUFFER_BUSY 1 | |
731 | ||
732 | /* | |
733 | * There will be one netxen_buffer per skb packet. These will be | |
734 | * used to save the dma info for pci_unmap_page() | |
735 | */ | |
736 | struct netxen_cmd_buffer { | |
737 | struct sk_buff *skb; | |
738 | struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; | |
739 | u32 total_length; | |
740 | u32 mss; | |
741 | u16 port; | |
742 | u8 cmd; | |
743 | u8 frag_count; | |
744 | unsigned long time_stamp; | |
745 | u32 state; | |
3d396eb1 AK |
746 | }; |
747 | ||
748 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
749 | struct netxen_rx_buffer { | |
750 | struct sk_buff *skb; | |
751 | u64 dma; | |
752 | u16 ref_handle; | |
753 | u16 state; | |
ed25ffa1 AK |
754 | u32 lro_expected_frags; |
755 | u32 lro_current_frags; | |
756 | u32 lro_length; | |
3d396eb1 AK |
757 | }; |
758 | ||
759 | /* Board types */ | |
760 | #define NETXEN_NIC_GBE 0x01 | |
761 | #define NETXEN_NIC_XGBE 0x02 | |
762 | ||
763 | /* | |
764 | * One hardware_context{} per adapter | |
765 | * contains interrupt info as well shared hardware info. | |
766 | */ | |
767 | struct netxen_hardware_context { | |
768 | struct pci_dev *pdev; | |
cb8011ad AK |
769 | void __iomem *pci_base0; |
770 | void __iomem *pci_base1; | |
771 | void __iomem *pci_base2; | |
6c80b18d MT |
772 | unsigned long first_page_group_end; |
773 | unsigned long first_page_group_start; | |
ed25ffa1 AK |
774 | void __iomem *db_base; |
775 | unsigned long db_len; | |
cb8011ad | 776 | |
3d396eb1 AK |
777 | u8 revision_id; |
778 | u16 board_type; | |
3d396eb1 AK |
779 | struct netxen_board_info boardcfg; |
780 | u32 xg_linkup; | |
cb8011ad | 781 | u32 qg_linksup; |
3d396eb1 AK |
782 | /* Address of cmd ring in Phantom */ |
783 | struct cmd_desc_type0 *cmd_desc_head; | |
cb8011ad | 784 | struct pci_dev *cmd_desc_pdev; |
3d396eb1 AK |
785 | dma_addr_t cmd_desc_phys_addr; |
786 | struct netxen_adapter *adapter; | |
13ba9c77 | 787 | int pci_func; |
3d396eb1 AK |
788 | }; |
789 | ||
ed25ffa1 AK |
790 | #define RCV_RING_LRO RCV_DESC_LRO |
791 | ||
3d396eb1 AK |
792 | #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ |
793 | #define ETHERNET_FCS_SIZE 4 | |
794 | ||
795 | struct netxen_adapter_stats { | |
3176ff3e MT |
796 | u64 rcvdbadskb; |
797 | u64 xmitcalled; | |
798 | u64 xmitedframes; | |
799 | u64 xmitfinished; | |
800 | u64 badskblen; | |
801 | u64 nocmddescriptor; | |
802 | u64 polled; | |
d1847a72 | 803 | u64 rxdropped; |
3176ff3e | 804 | u64 txdropped; |
3176ff3e MT |
805 | u64 csummed; |
806 | u64 no_rcv; | |
807 | u64 rxbytes; | |
808 | u64 txbytes; | |
809 | u64 ints; | |
3d396eb1 AK |
810 | }; |
811 | ||
812 | /* | |
813 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
814 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
815 | */ | |
816 | struct netxen_rcv_desc_ctx { | |
817 | u32 flags; | |
818 | u32 producer; | |
819 | u32 rcv_pending; /* Num of bufs posted in phantom */ | |
3d396eb1 | 820 | dma_addr_t phys_addr; |
cb8011ad | 821 | struct pci_dev *phys_pdev; |
3d396eb1 AK |
822 | struct rcv_desc *desc_head; /* address of rx ring in Phantom */ |
823 | u32 max_rx_desc_count; | |
824 | u32 dma_size; | |
825 | u32 skb_size; | |
826 | struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */ | |
827 | int begin_alloc; | |
828 | }; | |
829 | ||
830 | /* | |
831 | * Receive context. There is one such structure per instance of the | |
832 | * receive processing. Any state information that is relevant to | |
833 | * the receive, and is must be in this structure. The global data may be | |
834 | * present elsewhere. | |
835 | */ | |
836 | struct netxen_recv_context { | |
837 | struct netxen_rcv_desc_ctx rcv_desc[NUM_RCV_DESC_RINGS]; | |
838 | u32 status_rx_producer; | |
839 | u32 status_rx_consumer; | |
840 | dma_addr_t rcv_status_desc_phys_addr; | |
cb8011ad | 841 | struct pci_dev *rcv_status_desc_pdev; |
3d396eb1 AK |
842 | struct status_desc *rcv_status_desc_head; |
843 | }; | |
844 | ||
845 | #define NETXEN_NIC_MSI_ENABLED 0x02 | |
ed25ffa1 AK |
846 | #define NETXEN_DMA_MASK 0xfffffffe |
847 | #define NETXEN_DB_MAPSIZE_BYTES 0x1000 | |
848 | ||
849 | struct netxen_dummy_dma { | |
850 | void *addr; | |
851 | dma_addr_t phys_addr; | |
852 | }; | |
3d396eb1 | 853 | |
3d396eb1 AK |
854 | struct netxen_adapter { |
855 | struct netxen_hardware_context ahw; | |
4790654c | 856 | |
3176ff3e MT |
857 | struct netxen_adapter *master; |
858 | struct net_device *netdev; | |
859 | struct pci_dev *pdev; | |
bea3348e | 860 | struct napi_struct napi; |
6c80b18d | 861 | struct net_device_stats net_stats; |
3176ff3e MT |
862 | unsigned char mac_addr[ETH_ALEN]; |
863 | int mtu; | |
864 | int portnum; | |
3276fbad | 865 | u8 physical_port; |
3176ff3e | 866 | |
3d396eb1 | 867 | struct work_struct watchdog_task; |
3d396eb1 | 868 | struct timer_list watchdog_timer; |
3176ff3e | 869 | struct work_struct tx_timeout_task; |
3d396eb1 AK |
870 | |
871 | u32 curr_window; | |
872 | ||
873 | u32 cmd_producer; | |
f305f789 | 874 | __le32 *cmd_consumer; |
3d396eb1 | 875 | u32 last_cmd_consumer; |
ba53e6b4 | 876 | |
3d396eb1 AK |
877 | u32 max_tx_desc_count; |
878 | u32 max_rx_desc_count; | |
879 | u32 max_jumbo_rx_desc_count; | |
ed25ffa1 | 880 | u32 max_lro_rx_desc_count; |
3d396eb1 AK |
881 | |
882 | u32 flags; | |
883 | u32 irq; | |
884 | int driver_mismatch; | |
cb8011ad | 885 | u32 temp; |
3d396eb1 AK |
886 | |
887 | struct netxen_adapter_stats stats; | |
4790654c | 888 | |
3176ff3e MT |
889 | u16 portno; |
890 | u16 link_speed; | |
891 | u16 link_duplex; | |
892 | u16 state; | |
893 | u16 link_autoneg; | |
200eef20 | 894 | int rx_csum; |
3176ff3e MT |
895 | int status; |
896 | spinlock_t stats_lock; | |
3d396eb1 AK |
897 | |
898 | struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */ | |
899 | ||
900 | /* | |
901 | * Receive instances. These can be either one per port, | |
902 | * or one per peg, etc. | |
903 | */ | |
904 | struct netxen_recv_context recv_ctx[MAX_RCV_CTX]; | |
905 | ||
906 | int is_up; | |
ed25ffa1 AK |
907 | struct netxen_dummy_dma dummy_dma; |
908 | ||
909 | /* Context interface shared between card and host */ | |
910 | struct netxen_ring_ctx *ctx_desc; | |
911 | struct pci_dev *ctx_desc_pdev; | |
912 | dma_addr_t ctx_desc_phys_addr; | |
2d1a3bbd | 913 | int intr_scheme; |
443be796 | 914 | int msi_mode; |
13ba9c77 MT |
915 | int (*enable_phy_interrupts) (struct netxen_adapter *); |
916 | int (*disable_phy_interrupts) (struct netxen_adapter *); | |
80922fbc | 917 | void (*handle_phy_intr) (struct netxen_adapter *); |
3176ff3e MT |
918 | int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t); |
919 | int (*set_mtu) (struct netxen_adapter *, int); | |
920 | int (*set_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t); | |
921 | int (*unset_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t); | |
13ba9c77 MT |
922 | int (*phy_read) (struct netxen_adapter *, long reg, u32 *); |
923 | int (*phy_write) (struct netxen_adapter *, long reg, u32 val); | |
80922fbc AK |
924 | int (*init_port) (struct netxen_adapter *, int); |
925 | void (*init_niu) (struct netxen_adapter *); | |
3176ff3e | 926 | int (*stop_port) (struct netxen_adapter *); |
3d396eb1 AK |
927 | }; /* netxen_adapter structure */ |
928 | ||
96acb6eb DP |
929 | /* |
930 | * NetXen dma watchdog control structure | |
931 | * | |
932 | * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive | |
933 | * Bit 1 : disable_request => 1 req disable dma watchdog | |
934 | * Bit 2 : enable_request => 1 req enable dma watchdog | |
935 | * Bit 3-31 : unused | |
936 | */ | |
937 | ||
938 | #define netxen_set_dma_watchdog_disable_req(config_word) \ | |
939 | _netxen_set_bits(config_word, 1, 1, 1) | |
940 | #define netxen_set_dma_watchdog_enable_req(config_word) \ | |
941 | _netxen_set_bits(config_word, 2, 1, 1) | |
942 | #define netxen_get_dma_watchdog_enabled(config_word) \ | |
943 | ((config_word) & 0x1) | |
944 | #define netxen_get_dma_watchdog_disabled(config_word) \ | |
945 | (((config_word) >> 1) & 0x1) | |
946 | ||
3d396eb1 AK |
947 | /* Max number of xmit producer threads that can run simultaneously */ |
948 | #define MAX_XMIT_PRODUCERS 16 | |
949 | ||
cb8011ad AK |
950 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
951 | ((adapter)->ahw.pci_base0 + (off)) | |
952 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | |
953 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) | |
954 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ | |
955 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) | |
956 | ||
957 | static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter, | |
958 | unsigned long off) | |
959 | { | |
960 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
961 | return (adapter->ahw.pci_base0 + off); | |
962 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
963 | (off >= SECOND_PAGE_GROUP_START)) { | |
964 | return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START); | |
965 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
966 | (off >= THIRD_PAGE_GROUP_START)) { | |
967 | return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START); | |
968 | } | |
969 | return NULL; | |
970 | } | |
971 | ||
972 | static inline void __iomem *pci_base(struct netxen_adapter *adapter, | |
973 | unsigned long off) | |
974 | { | |
975 | if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) { | |
976 | return adapter->ahw.pci_base0; | |
977 | } else if ((off < SECOND_PAGE_GROUP_END) && | |
978 | (off >= SECOND_PAGE_GROUP_START)) { | |
979 | return adapter->ahw.pci_base1; | |
980 | } else if ((off < THIRD_PAGE_GROUP_END) && | |
981 | (off >= THIRD_PAGE_GROUP_START)) { | |
982 | return adapter->ahw.pci_base2; | |
983 | } | |
984 | return NULL; | |
985 | } | |
986 | ||
13ba9c77 MT |
987 | int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter); |
988 | int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter); | |
989 | int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter); | |
990 | int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter); | |
3d396eb1 AK |
991 | void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter); |
992 | void netxen_nic_gbe_handle_phy_intr(struct netxen_adapter *adapter); | |
13ba9c77 | 993 | int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg, |
a608ab9c | 994 | __u32 * readval); |
13ba9c77 | 995 | int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, |
a608ab9c | 996 | long reg, __u32 val); |
3d396eb1 AK |
997 | |
998 | /* Functions available from netxen_nic_hw.c */ | |
3176ff3e MT |
999 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); |
1000 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); | |
3d396eb1 AK |
1001 | void netxen_nic_init_niu_gb(struct netxen_adapter *adapter); |
1002 | void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw); | |
1003 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); | |
1004 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); | |
1005 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); | |
1006 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value); | |
1007 | ||
1008 | int netxen_nic_get_board_info(struct netxen_adapter *adapter); | |
1009 | int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
1010 | int len); | |
1011 | int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
1012 | int len); | |
1013 | void netxen_crb_writelit_adapter(struct netxen_adapter *adapter, | |
1014 | unsigned long off, int data); | |
1015 | ||
1016 | /* Functions from netxen_nic_init.c */ | |
ed25ffa1 AK |
1017 | void netxen_free_adapter_offload(struct netxen_adapter *adapter); |
1018 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter); | |
96acb6eb DP |
1019 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); |
1020 | int netxen_load_firmware(struct netxen_adapter *adapter); | |
3d396eb1 AK |
1021 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose); |
1022 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); | |
4790654c | 1023 | int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 | 1024 | u8 *bytes, size_t size); |
4790654c | 1025 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
1026 | u8 *bytes, size_t size); |
1027 | int netxen_flash_unlock(struct netxen_adapter *adapter); | |
1028 | int netxen_backup_crbinit(struct netxen_adapter *adapter); | |
1029 | int netxen_flash_erase_secondary(struct netxen_adapter *adapter); | |
1030 | int netxen_flash_erase_primary(struct netxen_adapter *adapter); | |
e45d9ab4 | 1031 | void netxen_halt_pegs(struct netxen_adapter *adapter); |
27d2ab54 | 1032 | |
cb8011ad | 1033 | int netxen_rom_se(struct netxen_adapter *adapter, int addr); |
3d396eb1 AK |
1034 | |
1035 | /* Functions from netxen_nic_isr.c */ | |
3d396eb1 | 1036 | void netxen_initialize_adapter_sw(struct netxen_adapter *adapter); |
cb8011ad AK |
1037 | void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr, |
1038 | struct pci_dev **used_dev); | |
3d396eb1 AK |
1039 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter); |
1040 | int netxen_init_firmware(struct netxen_adapter *adapter); | |
1041 | void netxen_free_hw_resources(struct netxen_adapter *adapter); | |
1042 | void netxen_tso_check(struct netxen_adapter *adapter, | |
1043 | struct cmd_desc_type0 *desc, struct sk_buff *skb); | |
1044 | int netxen_nic_hw_resources(struct netxen_adapter *adapter); | |
1045 | void netxen_nic_clear_stats(struct netxen_adapter *adapter); | |
6d5aefb8 | 1046 | void netxen_watchdog_task(struct work_struct *work); |
3d396eb1 AK |
1047 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, |
1048 | u32 ringid); | |
05aaa02d | 1049 | int netxen_process_cmd_ring(struct netxen_adapter *adapter); |
3d396eb1 AK |
1050 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max); |
1051 | void netxen_nic_set_multi(struct net_device *netdev); | |
1052 | int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); | |
1053 | int netxen_nic_set_mac(struct net_device *netdev, void *p); | |
1054 | struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev); | |
1055 | ||
cb8011ad AK |
1056 | |
1057 | /* | |
1058 | * NetXen Board information | |
1059 | */ | |
1060 | ||
1061 | #define NETXEN_MAX_SHORT_NAME 16 | |
71bd7877 | 1062 | struct netxen_brdinfo { |
cb8011ad AK |
1063 | netxen_brdtype_t brdtype; /* type of board */ |
1064 | long ports; /* max no of physical ports */ | |
1065 | char short_name[NETXEN_MAX_SHORT_NAME]; | |
71bd7877 | 1066 | }; |
cb8011ad | 1067 | |
71bd7877 | 1068 | static const struct netxen_brdinfo netxen_boards[] = { |
cb8011ad AK |
1069 | {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, |
1070 | {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, | |
1071 | {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, | |
1072 | {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, | |
1073 | {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, | |
1074 | {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, | |
1075 | }; | |
1076 | ||
ff8ac609 | 1077 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards) |
cb8011ad | 1078 | |
cb8011ad AK |
1079 | static inline void get_brd_name_by_type(u32 type, char *name) |
1080 | { | |
1081 | int i, found = 0; | |
1082 | for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { | |
1083 | if (netxen_boards[i].brdtype == type) { | |
1084 | strcpy(name, netxen_boards[i].short_name); | |
1085 | found = 1; | |
1086 | break; | |
1087 | } | |
1088 | ||
3d396eb1 | 1089 | } |
cb8011ad AK |
1090 | if (!found) |
1091 | name = "Unknown"; | |
3d396eb1 AK |
1092 | } |
1093 | ||
96acb6eb DP |
1094 | static inline int |
1095 | dma_watchdog_shutdown_request(struct netxen_adapter *adapter) | |
1096 | { | |
1097 | u32 ctrl; | |
1098 | ||
1099 | /* check if already inactive */ | |
1100 | if (netxen_nic_hw_read_wx(adapter, | |
1101 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) | |
1102 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1103 | ||
1104 | if (netxen_get_dma_watchdog_enabled(ctrl) == 0) | |
1105 | return 1; | |
1106 | ||
1107 | /* Send the disable request */ | |
1108 | netxen_set_dma_watchdog_disable_req(ctrl); | |
1109 | netxen_crb_writelit_adapter(adapter, | |
1110 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | static inline int | |
1116 | dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter) | |
1117 | { | |
1118 | u32 ctrl; | |
1119 | ||
1120 | if (netxen_nic_hw_read_wx(adapter, | |
1121 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) | |
1122 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1123 | ||
ceded32f | 1124 | return (netxen_get_dma_watchdog_enabled(ctrl) == 0); |
96acb6eb DP |
1125 | } |
1126 | ||
1127 | static inline int | |
1128 | dma_watchdog_wakeup(struct netxen_adapter *adapter) | |
1129 | { | |
1130 | u32 ctrl; | |
1131 | ||
1132 | if (netxen_nic_hw_read_wx(adapter, | |
1133 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) | |
1134 | printk(KERN_ERR "failed to read dma watchdog status\n"); | |
1135 | ||
1136 | if (netxen_get_dma_watchdog_enabled(ctrl)) | |
1137 | return 1; | |
1138 | ||
1139 | /* send the wakeup request */ | |
1140 | netxen_set_dma_watchdog_enable_req(ctrl); | |
1141 | ||
1142 | netxen_crb_writelit_adapter(adapter, | |
1143 | NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl); | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | ||
3d396eb1 | 1149 | int netxen_is_flash_supported(struct netxen_adapter *adapter); |
f305f789 | 1150 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]); |
3d396eb1 AK |
1151 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
1152 | extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, | |
1153 | int *valp); | |
1154 | ||
1155 | extern struct ethtool_ops netxen_nic_ethtool_ops; | |
1156 | ||
1157 | #endif /* __NETXEN_NIC_H_ */ |