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3d396eb1 | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
13af7a6e | 3 | * Copyright (C) 2009 - QLogic Corporation. |
3d396eb1 | 4 | * All rights reserved. |
80922fbc | 5 | * |
3d396eb1 AK |
6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
cb8011ad | 10 | * |
3d396eb1 AK |
11 | * This program is distributed in the hope that it will be useful, but |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
cb8011ad | 15 | * |
3d396eb1 AK |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
19 | * MA 02111-1307, USA. | |
80922fbc | 20 | * |
3d396eb1 | 21 | * The full GNU General Public License is included in this distribution |
4d21fef4 | 22 | * in the file called "COPYING". |
80922fbc | 23 | * |
3d396eb1 AK |
24 | */ |
25 | ||
5a0e3ad6 | 26 | #include <linux/slab.h> |
3d396eb1 AK |
27 | #include "netxen_nic.h" |
28 | #include "netxen_nic_hw.h" | |
3d396eb1 | 29 | |
c9bdd4b5 ACM |
30 | #include <net/ip.h> |
31 | ||
3ce06a32 DP |
32 | #define MASK(n) ((1ULL<<(n))-1) |
33 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) | |
34 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) | |
35 | #define MS_WIN(addr) (addr & 0x0ffc0000) | |
36 | ||
37 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) | |
38 | ||
39 | #define CRB_BLK(off) ((off >> 20) & 0x3f) | |
40 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) | |
41 | #define CRB_WINDOW_2M (0x130060) | |
42 | #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) | |
43 | #define CRB_INDIRECT_2M (0x1e0000UL) | |
44 | ||
f03b0ebd DP |
45 | static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, |
46 | void __iomem *addr, u32 data); | |
47 | static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, | |
48 | void __iomem *addr); | |
49 | ||
e98e3350 DP |
50 | #ifndef readq |
51 | static inline u64 readq(void __iomem *addr) | |
52 | { | |
53 | return readl(addr) | (((u64) readl(addr + 4)) << 32LL); | |
54 | } | |
55 | #endif | |
56 | ||
57 | #ifndef writeq | |
58 | static inline void writeq(u64 val, void __iomem *addr) | |
59 | { | |
60 | writel(((u32) (val)), (addr)); | |
61 | writel(((u32) (val >> 32)), (addr + 4)); | |
62 | } | |
63 | #endif | |
64 | ||
1fbe6323 DP |
65 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ |
66 | ((adapter)->ahw.pci_base0 + (off)) | |
67 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | |
68 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) | |
69 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ | |
70 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) | |
71 | ||
72 | static void __iomem *pci_base_offset(struct netxen_adapter *adapter, | |
73 | unsigned long off) | |
74 | { | |
75 | if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END)) | |
76 | return PCI_OFFSET_FIRST_RANGE(adapter, off); | |
77 | ||
78 | if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END)) | |
79 | return PCI_OFFSET_SECOND_RANGE(adapter, off); | |
80 | ||
81 | if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END)) | |
82 | return PCI_OFFSET_THIRD_RANGE(adapter, off); | |
83 | ||
84 | return NULL; | |
85 | } | |
86 | ||
ea7eaa39 DP |
87 | static crb_128M_2M_block_map_t |
88 | crb_128M_2M_map[64] __cacheline_aligned_in_smp = { | |
3ce06a32 DP |
89 | {{{0, 0, 0, 0} } }, /* 0: PCI */ |
90 | {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ | |
91 | {1, 0x0110000, 0x0120000, 0x130000}, | |
92 | {1, 0x0120000, 0x0122000, 0x124000}, | |
93 | {1, 0x0130000, 0x0132000, 0x126000}, | |
94 | {1, 0x0140000, 0x0142000, 0x128000}, | |
95 | {1, 0x0150000, 0x0152000, 0x12a000}, | |
96 | {1, 0x0160000, 0x0170000, 0x110000}, | |
97 | {1, 0x0170000, 0x0172000, 0x12e000}, | |
98 | {0, 0x0000000, 0x0000000, 0x000000}, | |
99 | {0, 0x0000000, 0x0000000, 0x000000}, | |
100 | {0, 0x0000000, 0x0000000, 0x000000}, | |
101 | {0, 0x0000000, 0x0000000, 0x000000}, | |
102 | {0, 0x0000000, 0x0000000, 0x000000}, | |
103 | {0, 0x0000000, 0x0000000, 0x000000}, | |
104 | {1, 0x01e0000, 0x01e0800, 0x122000}, | |
105 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
106 | {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ | |
107 | {{{0, 0, 0, 0} } }, /* 3: */ | |
108 | {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ | |
109 | {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ | |
110 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ | |
111 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ | |
112 | {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ | |
113 | {0, 0x0000000, 0x0000000, 0x000000}, | |
114 | {0, 0x0000000, 0x0000000, 0x000000}, | |
115 | {0, 0x0000000, 0x0000000, 0x000000}, | |
116 | {0, 0x0000000, 0x0000000, 0x000000}, | |
117 | {0, 0x0000000, 0x0000000, 0x000000}, | |
118 | {0, 0x0000000, 0x0000000, 0x000000}, | |
119 | {0, 0x0000000, 0x0000000, 0x000000}, | |
120 | {0, 0x0000000, 0x0000000, 0x000000}, | |
121 | {0, 0x0000000, 0x0000000, 0x000000}, | |
122 | {0, 0x0000000, 0x0000000, 0x000000}, | |
123 | {0, 0x0000000, 0x0000000, 0x000000}, | |
124 | {0, 0x0000000, 0x0000000, 0x000000}, | |
125 | {0, 0x0000000, 0x0000000, 0x000000}, | |
126 | {0, 0x0000000, 0x0000000, 0x000000}, | |
127 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, | |
128 | {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ | |
129 | {0, 0x0000000, 0x0000000, 0x000000}, | |
130 | {0, 0x0000000, 0x0000000, 0x000000}, | |
131 | {0, 0x0000000, 0x0000000, 0x000000}, | |
132 | {0, 0x0000000, 0x0000000, 0x000000}, | |
133 | {0, 0x0000000, 0x0000000, 0x000000}, | |
134 | {0, 0x0000000, 0x0000000, 0x000000}, | |
135 | {0, 0x0000000, 0x0000000, 0x000000}, | |
136 | {0, 0x0000000, 0x0000000, 0x000000}, | |
137 | {0, 0x0000000, 0x0000000, 0x000000}, | |
138 | {0, 0x0000000, 0x0000000, 0x000000}, | |
139 | {0, 0x0000000, 0x0000000, 0x000000}, | |
140 | {0, 0x0000000, 0x0000000, 0x000000}, | |
141 | {0, 0x0000000, 0x0000000, 0x000000}, | |
142 | {0, 0x0000000, 0x0000000, 0x000000}, | |
143 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, | |
144 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ | |
145 | {0, 0x0000000, 0x0000000, 0x000000}, | |
146 | {0, 0x0000000, 0x0000000, 0x000000}, | |
147 | {0, 0x0000000, 0x0000000, 0x000000}, | |
148 | {0, 0x0000000, 0x0000000, 0x000000}, | |
149 | {0, 0x0000000, 0x0000000, 0x000000}, | |
150 | {0, 0x0000000, 0x0000000, 0x000000}, | |
151 | {0, 0x0000000, 0x0000000, 0x000000}, | |
152 | {0, 0x0000000, 0x0000000, 0x000000}, | |
153 | {0, 0x0000000, 0x0000000, 0x000000}, | |
154 | {0, 0x0000000, 0x0000000, 0x000000}, | |
155 | {0, 0x0000000, 0x0000000, 0x000000}, | |
156 | {0, 0x0000000, 0x0000000, 0x000000}, | |
157 | {0, 0x0000000, 0x0000000, 0x000000}, | |
158 | {0, 0x0000000, 0x0000000, 0x000000}, | |
159 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, | |
160 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ | |
161 | {0, 0x0000000, 0x0000000, 0x000000}, | |
162 | {0, 0x0000000, 0x0000000, 0x000000}, | |
163 | {0, 0x0000000, 0x0000000, 0x000000}, | |
164 | {0, 0x0000000, 0x0000000, 0x000000}, | |
165 | {0, 0x0000000, 0x0000000, 0x000000}, | |
166 | {0, 0x0000000, 0x0000000, 0x000000}, | |
167 | {0, 0x0000000, 0x0000000, 0x000000}, | |
168 | {0, 0x0000000, 0x0000000, 0x000000}, | |
169 | {0, 0x0000000, 0x0000000, 0x000000}, | |
170 | {0, 0x0000000, 0x0000000, 0x000000}, | |
171 | {0, 0x0000000, 0x0000000, 0x000000}, | |
172 | {0, 0x0000000, 0x0000000, 0x000000}, | |
173 | {0, 0x0000000, 0x0000000, 0x000000}, | |
174 | {0, 0x0000000, 0x0000000, 0x000000}, | |
175 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, | |
176 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ | |
177 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ | |
178 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ | |
179 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ | |
180 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ | |
181 | {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ | |
182 | {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ | |
183 | {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ | |
184 | {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ | |
185 | {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ | |
186 | {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ | |
187 | {{{0, 0, 0, 0} } }, /* 23: */ | |
188 | {{{0, 0, 0, 0} } }, /* 24: */ | |
189 | {{{0, 0, 0, 0} } }, /* 25: */ | |
190 | {{{0, 0, 0, 0} } }, /* 26: */ | |
191 | {{{0, 0, 0, 0} } }, /* 27: */ | |
192 | {{{0, 0, 0, 0} } }, /* 28: */ | |
193 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ | |
194 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ | |
195 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ | |
196 | {{{0} } }, /* 32: PCI */ | |
197 | {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ | |
198 | {1, 0x2110000, 0x2120000, 0x130000}, | |
199 | {1, 0x2120000, 0x2122000, 0x124000}, | |
200 | {1, 0x2130000, 0x2132000, 0x126000}, | |
201 | {1, 0x2140000, 0x2142000, 0x128000}, | |
202 | {1, 0x2150000, 0x2152000, 0x12a000}, | |
203 | {1, 0x2160000, 0x2170000, 0x110000}, | |
204 | {1, 0x2170000, 0x2172000, 0x12e000}, | |
205 | {0, 0x0000000, 0x0000000, 0x000000}, | |
206 | {0, 0x0000000, 0x0000000, 0x000000}, | |
207 | {0, 0x0000000, 0x0000000, 0x000000}, | |
208 | {0, 0x0000000, 0x0000000, 0x000000}, | |
209 | {0, 0x0000000, 0x0000000, 0x000000}, | |
210 | {0, 0x0000000, 0x0000000, 0x000000}, | |
211 | {0, 0x0000000, 0x0000000, 0x000000}, | |
212 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
213 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ | |
214 | {{{0} } }, /* 35: */ | |
215 | {{{0} } }, /* 36: */ | |
216 | {{{0} } }, /* 37: */ | |
217 | {{{0} } }, /* 38: */ | |
218 | {{{0} } }, /* 39: */ | |
219 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ | |
220 | {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ | |
221 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ | |
222 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ | |
223 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ | |
224 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ | |
225 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ | |
226 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ | |
227 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ | |
228 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ | |
229 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ | |
230 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ | |
231 | {{{0} } }, /* 52: */ | |
232 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ | |
233 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ | |
234 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ | |
235 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ | |
236 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ | |
237 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ | |
238 | {{{0} } }, /* 59: I2C0 */ | |
239 | {{{0} } }, /* 60: I2C1 */ | |
240 | {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ | |
241 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ | |
242 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ | |
243 | }; | |
244 | ||
245 | /* | |
246 | * top 12 bits of crb internal address (hub, agent) | |
247 | */ | |
248 | static unsigned crb_hub_agt[64] = | |
249 | { | |
250 | 0, | |
251 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, | |
252 | NETXEN_HW_CRB_HUB_AGT_ADR_MN, | |
253 | NETXEN_HW_CRB_HUB_AGT_ADR_MS, | |
254 | 0, | |
255 | NETXEN_HW_CRB_HUB_AGT_ADR_SRE, | |
256 | NETXEN_HW_CRB_HUB_AGT_ADR_NIU, | |
257 | NETXEN_HW_CRB_HUB_AGT_ADR_QMN, | |
258 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN0, | |
259 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN1, | |
260 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN2, | |
261 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN3, | |
262 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, | |
263 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, | |
264 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
265 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN4, | |
266 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, | |
267 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN0, | |
268 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN1, | |
269 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN2, | |
270 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN3, | |
271 | NETXEN_HW_CRB_HUB_AGT_ADR_PGND, | |
272 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNI, | |
273 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS0, | |
274 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS1, | |
275 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS2, | |
276 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS3, | |
277 | 0, | |
278 | NETXEN_HW_CRB_HUB_AGT_ADR_PGSI, | |
279 | NETXEN_HW_CRB_HUB_AGT_ADR_SN, | |
280 | 0, | |
281 | NETXEN_HW_CRB_HUB_AGT_ADR_EG, | |
282 | 0, | |
283 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, | |
284 | NETXEN_HW_CRB_HUB_AGT_ADR_CAM, | |
285 | 0, | |
286 | 0, | |
287 | 0, | |
288 | 0, | |
289 | 0, | |
290 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, | |
291 | 0, | |
292 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1, | |
293 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2, | |
294 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3, | |
295 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4, | |
296 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5, | |
297 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6, | |
298 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7, | |
299 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, | |
300 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, | |
301 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
302 | 0, | |
303 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0, | |
304 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8, | |
305 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9, | |
306 | NETXEN_HW_CRB_HUB_AGT_ADR_OCM0, | |
307 | 0, | |
308 | NETXEN_HW_CRB_HUB_AGT_ADR_SMB, | |
309 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C0, | |
310 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C1, | |
311 | 0, | |
312 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNC, | |
313 | 0, | |
314 | }; | |
315 | ||
3d396eb1 AK |
316 | /* PCI Windowing for DDR regions. */ |
317 | ||
3ce06a32 | 318 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ |
3d396eb1 | 319 | |
c9517e58 DP |
320 | #define NETXEN_PCIE_SEM_TIMEOUT 10000 |
321 | ||
322 | int | |
323 | netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg) | |
324 | { | |
325 | int done = 0, timeout = 0; | |
326 | ||
327 | while (!done) { | |
328 | done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem))); | |
329 | if (done == 1) | |
330 | break; | |
331 | if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT) | |
7cecdca1 | 332 | return -EIO; |
c9517e58 DP |
333 | msleep(1); |
334 | } | |
335 | ||
336 | if (id_reg) | |
337 | NXWR32(adapter, id_reg, adapter->portnum); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | void | |
343 | netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem) | |
344 | { | |
581e8ae4 | 345 | NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem))); |
c9517e58 DP |
346 | } |
347 | ||
3ad4467c DP |
348 | int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port) |
349 | { | |
350 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
351 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447); | |
352 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5); | |
353 | } | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | /* Disable an XG interface */ | |
359 | int netxen_niu_disable_xg_port(struct netxen_adapter *adapter) | |
360 | { | |
361 | __u32 mac_cfg; | |
362 | u32 port = adapter->physical_port; | |
363 | ||
364 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | |
365 | return 0; | |
366 | ||
367 | if (port > NETXEN_NIU_MAX_XG_PORTS) | |
368 | return -EINVAL; | |
369 | ||
370 | mac_cfg = 0; | |
371 | if (NXWR32(adapter, | |
372 | NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg)) | |
373 | return -EIO; | |
374 | return 0; | |
375 | } | |
376 | ||
623621b0 DP |
377 | #define NETXEN_UNICAST_ADDR(port, index) \ |
378 | (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8)) | |
379 | #define NETXEN_MCAST_ADDR(port, index) \ | |
380 | (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8)) | |
381 | #define MAC_HI(addr) \ | |
382 | ((addr[2] << 16) | (addr[1] << 8) | (addr[0])) | |
383 | #define MAC_LO(addr) \ | |
384 | ((addr[5] << 16) | (addr[4] << 8) | (addr[3])) | |
385 | ||
3ad4467c DP |
386 | int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) |
387 | { | |
a7483b0a NK |
388 | u32 mac_cfg; |
389 | u32 cnt = 0; | |
390 | __u32 reg = 0x0200; | |
3ad4467c | 391 | u32 port = adapter->physical_port; |
a7483b0a | 392 | u16 board_type = adapter->ahw.board_type; |
3ad4467c DP |
393 | |
394 | if (port > NETXEN_NIU_MAX_XG_PORTS) | |
395 | return -EINVAL; | |
396 | ||
a7483b0a NK |
397 | mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port)); |
398 | mac_cfg &= ~0x4; | |
399 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); | |
3ad4467c | 400 | |
a7483b0a NK |
401 | if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) || |
402 | (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ)) | |
403 | reg = (0x20 << port); | |
3ad4467c | 404 | |
a7483b0a NK |
405 | NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg); |
406 | ||
407 | mdelay(10); | |
408 | ||
409 | while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20) | |
410 | mdelay(10); | |
411 | ||
412 | if (cnt < 20) { | |
413 | ||
414 | reg = NXRD32(adapter, | |
415 | NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port)); | |
416 | ||
417 | if (mode == NETXEN_NIU_PROMISC_MODE) | |
418 | reg = (reg | 0x2000UL); | |
419 | else | |
420 | reg = (reg & ~0x2000UL); | |
421 | ||
422 | if (mode == NETXEN_NIU_ALLMULTI_MODE) | |
423 | reg = (reg | 0x1000UL); | |
424 | else | |
425 | reg = (reg & ~0x1000UL); | |
426 | ||
427 | NXWR32(adapter, | |
428 | NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg); | |
429 | } | |
430 | ||
431 | mac_cfg |= 0x4; | |
432 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); | |
3ad4467c DP |
433 | |
434 | return 0; | |
435 | } | |
436 | ||
437 | int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) | |
438 | { | |
439 | u32 mac_hi, mac_lo; | |
440 | u32 reg_hi, reg_lo; | |
441 | ||
442 | u8 phy = adapter->physical_port; | |
443 | ||
444 | if (phy >= NETXEN_NIU_MAX_XG_PORTS) | |
445 | return -EINVAL; | |
446 | ||
447 | mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24); | |
448 | mac_hi = addr[2] | ((u32)addr[3] << 8) | | |
449 | ((u32)addr[4] << 16) | ((u32)addr[5] << 24); | |
450 | ||
451 | reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy); | |
452 | reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy); | |
453 | ||
454 | /* write twice to flush */ | |
455 | if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) | |
456 | return -EIO; | |
457 | if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) | |
458 | return -EIO; | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
623621b0 DP |
463 | static int |
464 | netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter) | |
465 | { | |
466 | u32 val = 0; | |
467 | u16 port = adapter->physical_port; | |
5d09e534 | 468 | u8 *addr = adapter->mac_addr; |
623621b0 DP |
469 | |
470 | if (adapter->mc_enabled) | |
471 | return 0; | |
472 | ||
f98a9f69 | 473 | val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); |
623621b0 | 474 | val |= (1UL << (28+port)); |
f98a9f69 | 475 | NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); |
623621b0 DP |
476 | |
477 | /* add broadcast addr to filter */ | |
478 | val = 0xffffff; | |
f98a9f69 DP |
479 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
480 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); | |
623621b0 DP |
481 | |
482 | /* add station addr to filter */ | |
483 | val = MAC_HI(addr); | |
f98a9f69 | 484 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val); |
623621b0 | 485 | val = MAC_LO(addr); |
f98a9f69 | 486 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val); |
623621b0 DP |
487 | |
488 | adapter->mc_enabled = 1; | |
489 | return 0; | |
490 | } | |
491 | ||
492 | static int | |
493 | netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter) | |
494 | { | |
495 | u32 val = 0; | |
496 | u16 port = adapter->physical_port; | |
5d09e534 | 497 | u8 *addr = adapter->mac_addr; |
623621b0 DP |
498 | |
499 | if (!adapter->mc_enabled) | |
500 | return 0; | |
501 | ||
f98a9f69 | 502 | val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); |
623621b0 | 503 | val &= ~(1UL << (28+port)); |
f98a9f69 | 504 | NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); |
623621b0 DP |
505 | |
506 | val = MAC_HI(addr); | |
f98a9f69 | 507 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
623621b0 | 508 | val = MAC_LO(addr); |
f98a9f69 | 509 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); |
623621b0 | 510 | |
f98a9f69 DP |
511 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); |
512 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); | |
623621b0 DP |
513 | |
514 | adapter->mc_enabled = 0; | |
515 | return 0; | |
516 | } | |
517 | ||
518 | static int | |
519 | netxen_nic_set_mcast_addr(struct netxen_adapter *adapter, | |
520 | int index, u8 *addr) | |
521 | { | |
522 | u32 hi = 0, lo = 0; | |
523 | u16 port = adapter->physical_port; | |
524 | ||
525 | lo = MAC_LO(addr); | |
526 | hi = MAC_HI(addr); | |
527 | ||
f98a9f69 DP |
528 | NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi); |
529 | NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo); | |
623621b0 DP |
530 | |
531 | return 0; | |
532 | } | |
533 | ||
c9fc891f | 534 | void netxen_p2_nic_set_multi(struct net_device *netdev) |
3d396eb1 | 535 | { |
3176ff3e | 536 | struct netxen_adapter *adapter = netdev_priv(netdev); |
22bedad3 | 537 | struct netdev_hw_addr *ha; |
623621b0 | 538 | u8 null_addr[6]; |
f9dcbcc9 | 539 | int i; |
623621b0 DP |
540 | |
541 | memset(null_addr, 0, 6); | |
3d396eb1 | 542 | |
3d396eb1 | 543 | if (netdev->flags & IFF_PROMISC) { |
623621b0 DP |
544 | |
545 | adapter->set_promisc(adapter, | |
546 | NETXEN_NIU_PROMISC_MODE); | |
547 | ||
548 | /* Full promiscuous mode */ | |
549 | netxen_nic_disable_mcast_filter(adapter); | |
550 | ||
551 | return; | |
552 | } | |
553 | ||
4cd24eaf | 554 | if (netdev_mc_empty(netdev)) { |
623621b0 DP |
555 | adapter->set_promisc(adapter, |
556 | NETXEN_NIU_NON_PROMISC_MODE); | |
557 | netxen_nic_disable_mcast_filter(adapter); | |
558 | return; | |
559 | } | |
560 | ||
561 | adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE); | |
562 | if (netdev->flags & IFF_ALLMULTI || | |
4cd24eaf | 563 | netdev_mc_count(netdev) > adapter->max_mc_count) { |
623621b0 DP |
564 | netxen_nic_disable_mcast_filter(adapter); |
565 | return; | |
3d396eb1 | 566 | } |
623621b0 DP |
567 | |
568 | netxen_nic_enable_mcast_filter(adapter); | |
569 | ||
f9dcbcc9 | 570 | i = 0; |
22bedad3 JP |
571 | netdev_for_each_mc_addr(ha, netdev) |
572 | netxen_nic_set_mcast_addr(adapter, i++, ha->addr); | |
623621b0 DP |
573 | |
574 | /* Clear out remaining addresses */ | |
f9dcbcc9 JP |
575 | while (i < adapter->max_mc_count) |
576 | netxen_nic_set_mcast_addr(adapter, i++, null_addr); | |
3d396eb1 AK |
577 | } |
578 | ||
c9fc891f DP |
579 | static int |
580 | netxen_send_cmd_descs(struct netxen_adapter *adapter, | |
d877f1e3 | 581 | struct cmd_desc_type0 *cmd_desc_arr, int nr_desc) |
c9fc891f | 582 | { |
d877f1e3 | 583 | u32 i, producer, consumer; |
c9fc891f DP |
584 | struct netxen_cmd_buffer *pbuf; |
585 | struct cmd_desc_type0 *cmd_desc; | |
d877f1e3 | 586 | struct nx_host_tx_ring *tx_ring; |
c9fc891f DP |
587 | |
588 | i = 0; | |
589 | ||
db4cfd8a DP |
590 | if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) |
591 | return -EIO; | |
592 | ||
4ea528a1 | 593 | tx_ring = adapter->tx_ring; |
b2af9cb0 | 594 | __netif_tx_lock_bh(tx_ring->txq); |
03e678ee | 595 | |
d877f1e3 DP |
596 | producer = tx_ring->producer; |
597 | consumer = tx_ring->sw_consumer; | |
598 | ||
b2af9cb0 DP |
599 | if (nr_desc >= netxen_tx_avail(tx_ring)) { |
600 | netif_tx_stop_queue(tx_ring->txq); | |
601 | __netif_tx_unlock_bh(tx_ring->txq); | |
d877f1e3 DP |
602 | return -EBUSY; |
603 | } | |
604 | ||
c9fc891f DP |
605 | do { |
606 | cmd_desc = &cmd_desc_arr[i]; | |
607 | ||
d877f1e3 | 608 | pbuf = &tx_ring->cmd_buf_arr[producer]; |
c9fc891f | 609 | pbuf->skb = NULL; |
c9fc891f | 610 | pbuf->frag_count = 0; |
c9fc891f | 611 | |
d877f1e3 | 612 | memcpy(&tx_ring->desc_head[producer], |
c9fc891f DP |
613 | &cmd_desc_arr[i], sizeof(struct cmd_desc_type0)); |
614 | ||
d877f1e3 | 615 | producer = get_next_index(producer, tx_ring->num_desc); |
c9fc891f DP |
616 | i++; |
617 | ||
d877f1e3 | 618 | } while (i != nr_desc); |
c9fc891f | 619 | |
d877f1e3 | 620 | tx_ring->producer = producer; |
c9fc891f | 621 | |
cb2107be | 622 | netxen_nic_update_cmd_producer(adapter, tx_ring); |
c9fc891f | 623 | |
b2af9cb0 | 624 | __netif_tx_unlock_bh(tx_ring->txq); |
03e678ee | 625 | |
c9fc891f DP |
626 | return 0; |
627 | } | |
628 | ||
5cf4d323 DP |
629 | static int |
630 | nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op) | |
c9fc891f | 631 | { |
c9fc891f | 632 | nx_nic_req_t req; |
2edbb454 DP |
633 | nx_mac_req_t *mac_req; |
634 | u64 word; | |
c9fc891f DP |
635 | |
636 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
2edbb454 DP |
637 | req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23); |
638 | ||
639 | word = NX_MAC_EVENT | ((u64)adapter->portnum << 16); | |
640 | req.req_hdr = cpu_to_le64(word); | |
641 | ||
642 | mac_req = (nx_mac_req_t *)&req.words[0]; | |
643 | mac_req->op = op; | |
644 | memcpy(mac_req->mac_addr, addr, 6); | |
c9fc891f | 645 | |
5cf4d323 DP |
646 | return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
647 | } | |
648 | ||
649 | static int nx_p3_nic_add_mac(struct netxen_adapter *adapter, | |
650 | u8 *addr, struct list_head *del_list) | |
651 | { | |
652 | struct list_head *head; | |
653 | nx_mac_list_t *cur; | |
654 | ||
655 | /* look up if already exists */ | |
656 | list_for_each(head, del_list) { | |
657 | cur = list_entry(head, nx_mac_list_t, list); | |
658 | ||
659 | if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) { | |
660 | list_move_tail(head, &adapter->mac_list); | |
661 | return 0; | |
662 | } | |
c9fc891f DP |
663 | } |
664 | ||
5cf4d323 DP |
665 | cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC); |
666 | if (cur == NULL) { | |
667 | printk(KERN_ERR "%s: failed to add mac address filter\n", | |
668 | adapter->netdev->name); | |
669 | return -ENOMEM; | |
670 | } | |
671 | memcpy(cur->mac_addr, addr, ETH_ALEN); | |
672 | list_add_tail(&cur->list, &adapter->mac_list); | |
673 | return nx_p3_sre_macaddr_change(adapter, | |
674 | cur->mac_addr, NETXEN_MAC_ADD); | |
c9fc891f DP |
675 | } |
676 | ||
677 | void netxen_p3_nic_set_multi(struct net_device *netdev) | |
678 | { | |
679 | struct netxen_adapter *adapter = netdev_priv(netdev); | |
22bedad3 | 680 | struct netdev_hw_addr *ha; |
c9fc891f | 681 | u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
9ad27643 | 682 | u32 mode = VPORT_MISS_MODE_DROP; |
5cf4d323 DP |
683 | LIST_HEAD(del_list); |
684 | struct list_head *head; | |
685 | nx_mac_list_t *cur; | |
c9fc891f | 686 | |
d49c9640 AKS |
687 | if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) |
688 | return; | |
689 | ||
5cf4d323 | 690 | list_splice_tail_init(&adapter->mac_list, &del_list); |
c9fc891f | 691 | |
5d09e534 | 692 | nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list); |
5cf4d323 | 693 | nx_p3_nic_add_mac(adapter, bcast_addr, &del_list); |
9ad27643 DP |
694 | |
695 | if (netdev->flags & IFF_PROMISC) { | |
696 | mode = VPORT_MISS_MODE_ACCEPT_ALL; | |
697 | goto send_fw_cmd; | |
698 | } | |
699 | ||
700 | if ((netdev->flags & IFF_ALLMULTI) || | |
4cd24eaf | 701 | (netdev_mc_count(netdev) > adapter->max_mc_count)) { |
9ad27643 DP |
702 | mode = VPORT_MISS_MODE_ACCEPT_MULTI; |
703 | goto send_fw_cmd; | |
704 | } | |
705 | ||
4cd24eaf | 706 | if (!netdev_mc_empty(netdev)) { |
22bedad3 JP |
707 | netdev_for_each_mc_addr(ha, netdev) |
708 | nx_p3_nic_add_mac(adapter, ha->addr, &del_list); | |
c9fc891f | 709 | } |
9ad27643 DP |
710 | |
711 | send_fw_cmd: | |
712 | adapter->set_promisc(adapter, mode); | |
5cf4d323 DP |
713 | head = &del_list; |
714 | while (!list_empty(head)) { | |
715 | cur = list_entry(head->next, nx_mac_list_t, list); | |
716 | ||
717 | nx_p3_sre_macaddr_change(adapter, | |
718 | cur->mac_addr, NETXEN_MAC_DEL); | |
719 | list_del(&cur->list); | |
c9fc891f | 720 | kfree(cur); |
c9fc891f DP |
721 | } |
722 | } | |
723 | ||
9ad27643 DP |
724 | int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) |
725 | { | |
726 | nx_nic_req_t req; | |
2edbb454 | 727 | u64 word; |
9ad27643 DP |
728 | |
729 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
730 | ||
2edbb454 DP |
731 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); |
732 | ||
733 | word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE | | |
734 | ((u64)adapter->portnum << 16); | |
735 | req.req_hdr = cpu_to_le64(word); | |
736 | ||
9ad27643 DP |
737 | req.words[0] = cpu_to_le64(mode); |
738 | ||
739 | return netxen_send_cmd_descs(adapter, | |
740 | (struct cmd_desc_type0 *)&req, 1); | |
741 | } | |
742 | ||
06e9d9f9 DP |
743 | void netxen_p3_free_mac_list(struct netxen_adapter *adapter) |
744 | { | |
5cf4d323 DP |
745 | nx_mac_list_t *cur; |
746 | struct list_head *head = &adapter->mac_list; | |
747 | ||
748 | while (!list_empty(head)) { | |
749 | cur = list_entry(head->next, nx_mac_list_t, list); | |
750 | nx_p3_sre_macaddr_change(adapter, | |
751 | cur->mac_addr, NETXEN_MAC_DEL); | |
752 | list_del(&cur->list); | |
06e9d9f9 | 753 | kfree(cur); |
06e9d9f9 DP |
754 | } |
755 | } | |
756 | ||
3d0a3cc9 DP |
757 | int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) |
758 | { | |
759 | /* assuming caller has already copied new addr to netdev */ | |
760 | netxen_p3_nic_set_multi(adapter->netdev); | |
761 | return 0; | |
762 | } | |
763 | ||
cd1f8160 DP |
764 | #define NETXEN_CONFIG_INTR_COALESCE 3 |
765 | ||
766 | /* | |
767 | * Send the interrupt coalescing parameter set by ethtool to the card. | |
768 | */ | |
769 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter) | |
770 | { | |
771 | nx_nic_req_t req; | |
c0703950 AKS |
772 | u64 word[6]; |
773 | int rv, i; | |
cd1f8160 DP |
774 | |
775 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
c0703950 | 776 | memset(word, 0, sizeof(word)); |
cd1f8160 | 777 | |
1bb482f8 | 778 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); |
2edbb454 | 779 | |
c0703950 AKS |
780 | word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16); |
781 | req.req_hdr = cpu_to_le64(word[0]); | |
cd1f8160 | 782 | |
c0703950 AKS |
783 | memcpy(&word[0], &adapter->coal, sizeof(adapter->coal)); |
784 | for (i = 0; i < 6; i++) | |
785 | req.words[i] = cpu_to_le64(word[i]); | |
cd1f8160 DP |
786 | |
787 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
788 | if (rv != 0) { | |
789 | printk(KERN_ERR "ERROR. Could not send " | |
790 | "interrupt coalescing parameters\n"); | |
791 | } | |
792 | ||
793 | return rv; | |
794 | } | |
795 | ||
1bb482f8 NK |
796 | int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable) |
797 | { | |
798 | nx_nic_req_t req; | |
799 | u64 word; | |
800 | int rv = 0; | |
801 | ||
802 | if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable) | |
803 | return 0; | |
804 | ||
805 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
806 | ||
807 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
808 | ||
809 | word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16); | |
810 | req.req_hdr = cpu_to_le64(word); | |
811 | ||
812 | req.words[0] = cpu_to_le64(enable); | |
813 | ||
814 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
815 | if (rv != 0) { | |
816 | printk(KERN_ERR "ERROR. Could not send " | |
817 | "configure hw lro request\n"); | |
818 | } | |
819 | ||
820 | adapter->flags ^= NETXEN_NIC_LRO_ENABLED; | |
821 | ||
822 | return rv; | |
823 | } | |
824 | ||
fa3ce355 NK |
825 | int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable) |
826 | { | |
827 | nx_nic_req_t req; | |
828 | u64 word; | |
829 | int rv = 0; | |
830 | ||
831 | if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable) | |
832 | return rv; | |
833 | ||
834 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
835 | ||
836 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
837 | ||
838 | word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING | | |
839 | ((u64)adapter->portnum << 16); | |
840 | req.req_hdr = cpu_to_le64(word); | |
841 | ||
842 | req.words[0] = cpu_to_le64(enable); | |
843 | ||
844 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
845 | if (rv != 0) { | |
846 | printk(KERN_ERR "ERROR. Could not send " | |
847 | "configure bridge mode request\n"); | |
848 | } | |
849 | ||
850 | adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED; | |
851 | ||
852 | return rv; | |
853 | } | |
854 | ||
855 | ||
d8b100c5 DP |
856 | #define RSS_HASHTYPE_IP_TCP 0x3 |
857 | ||
858 | int netxen_config_rss(struct netxen_adapter *adapter, int enable) | |
859 | { | |
860 | nx_nic_req_t req; | |
861 | u64 word; | |
862 | int i, rv; | |
863 | ||
864 | u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, | |
865 | 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, | |
866 | 0x255b0ec26d5a56daULL }; | |
867 | ||
868 | ||
869 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
870 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
871 | ||
872 | word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16); | |
873 | req.req_hdr = cpu_to_le64(word); | |
874 | ||
875 | /* | |
876 | * RSS request: | |
877 | * bits 3-0: hash_method | |
878 | * 5-4: hash_type_ipv4 | |
879 | * 7-6: hash_type_ipv6 | |
880 | * 8: enable | |
881 | * 9: use indirection table | |
882 | * 47-10: reserved | |
883 | * 63-48: indirection table mask | |
884 | */ | |
885 | word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | | |
886 | ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | | |
887 | ((u64)(enable & 0x1) << 8) | | |
888 | ((0x7ULL) << 48); | |
889 | req.words[0] = cpu_to_le64(word); | |
890 | for (i = 0; i < 5; i++) | |
891 | req.words[i+1] = cpu_to_le64(key[i]); | |
892 | ||
893 | ||
894 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
895 | if (rv != 0) { | |
896 | printk(KERN_ERR "%s: could not configure RSS\n", | |
897 | adapter->netdev->name); | |
898 | } | |
899 | ||
900 | return rv; | |
901 | } | |
902 | ||
6598b169 DP |
903 | int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd) |
904 | { | |
905 | nx_nic_req_t req; | |
906 | u64 word; | |
907 | int rv; | |
908 | ||
909 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
910 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
911 | ||
912 | word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16); | |
913 | req.req_hdr = cpu_to_le64(word); | |
914 | ||
915 | req.words[0] = cpu_to_le64(cmd); | |
916 | req.words[1] = cpu_to_le64(ip); | |
917 | ||
918 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
919 | if (rv != 0) { | |
920 | printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n", | |
921 | adapter->netdev->name, | |
922 | (cmd == NX_IP_UP) ? "Add" : "Remove", ip); | |
923 | } | |
924 | return rv; | |
925 | } | |
926 | ||
3bf26ce3 DP |
927 | int netxen_linkevent_request(struct netxen_adapter *adapter, int enable) |
928 | { | |
929 | nx_nic_req_t req; | |
930 | u64 word; | |
931 | int rv; | |
932 | ||
933 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
934 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
935 | ||
936 | word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16); | |
937 | req.req_hdr = cpu_to_le64(word); | |
22527864 | 938 | req.words[0] = cpu_to_le64(enable | (enable << 8)); |
3bf26ce3 DP |
939 | |
940 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
941 | if (rv != 0) { | |
942 | printk(KERN_ERR "%s: could not configure link notification\n", | |
943 | adapter->netdev->name); | |
944 | } | |
945 | ||
946 | return rv; | |
947 | } | |
948 | ||
1bb482f8 NK |
949 | int netxen_send_lro_cleanup(struct netxen_adapter *adapter) |
950 | { | |
951 | nx_nic_req_t req; | |
952 | u64 word; | |
953 | int rv; | |
954 | ||
955 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
956 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
957 | ||
958 | word = NX_NIC_H2C_OPCODE_LRO_REQUEST | | |
959 | ((u64)adapter->portnum << 16) | | |
960 | ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ; | |
961 | ||
962 | req.req_hdr = cpu_to_le64(word); | |
963 | ||
964 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
965 | if (rv != 0) { | |
966 | printk(KERN_ERR "%s: could not cleanup lro flows\n", | |
967 | adapter->netdev->name); | |
968 | } | |
969 | return rv; | |
970 | } | |
971 | ||
3d396eb1 AK |
972 | /* |
973 | * netxen_nic_change_mtu - Change the Maximum Transfer Unit | |
974 | * @returns 0 on success, negative on failure | |
975 | */ | |
c9fc891f DP |
976 | |
977 | #define MTU_FUDGE_FACTOR 100 | |
978 | ||
3d396eb1 AK |
979 | int netxen_nic_change_mtu(struct net_device *netdev, int mtu) |
980 | { | |
3176ff3e | 981 | struct netxen_adapter *adapter = netdev_priv(netdev); |
c9fc891f | 982 | int max_mtu; |
9ad27643 | 983 | int rc = 0; |
3d396eb1 | 984 | |
c9fc891f DP |
985 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
986 | max_mtu = P3_MAX_MTU; | |
987 | else | |
988 | max_mtu = P2_MAX_MTU; | |
989 | ||
990 | if (mtu > max_mtu) { | |
991 | printk(KERN_ERR "%s: mtu > %d bytes unsupported\n", | |
992 | netdev->name, max_mtu); | |
3d396eb1 AK |
993 | return -EINVAL; |
994 | } | |
995 | ||
80922fbc | 996 | if (adapter->set_mtu) |
9ad27643 | 997 | rc = adapter->set_mtu(adapter, mtu); |
3d396eb1 | 998 | |
9ad27643 DP |
999 | if (!rc) |
1000 | netdev->mtu = mtu; | |
c9fc891f | 1001 | |
9ad27643 | 1002 | return rc; |
3d396eb1 AK |
1003 | } |
1004 | ||
3d396eb1 | 1005 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, |
f305f789 | 1006 | int size, __le32 * buf) |
3d396eb1 | 1007 | { |
1e2d0059 | 1008 | int i, v, addr; |
f305f789 | 1009 | __le32 *ptr32; |
3d396eb1 AK |
1010 | |
1011 | addr = base; | |
1012 | ptr32 = buf; | |
1013 | for (i = 0; i < size / sizeof(u32); i++) { | |
f305f789 | 1014 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) |
3d396eb1 | 1015 | return -1; |
f305f789 | 1016 | *ptr32 = cpu_to_le32(v); |
3d396eb1 AK |
1017 | ptr32++; |
1018 | addr += sizeof(u32); | |
1019 | } | |
1020 | if ((char *)buf + size > (char *)ptr32) { | |
f305f789 AV |
1021 | __le32 local; |
1022 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) | |
3d396eb1 | 1023 | return -1; |
f305f789 | 1024 | local = cpu_to_le32(v); |
3d396eb1 AK |
1025 | memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); |
1026 | } | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
a03d2451 | 1031 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac) |
3d396eb1 | 1032 | { |
9dc28efe DP |
1033 | __le32 *pmac = (__le32 *) mac; |
1034 | u32 offset; | |
3d396eb1 | 1035 | |
06db58c0 | 1036 | offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64)); |
9dc28efe DP |
1037 | |
1038 | if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1) | |
3d396eb1 | 1039 | return -1; |
9dc28efe | 1040 | |
f305f789 | 1041 | if (*mac == cpu_to_le64(~0ULL)) { |
9dc28efe | 1042 | |
06db58c0 DP |
1043 | offset = NX_OLD_MAC_ADDR_OFFSET + |
1044 | (adapter->portnum * sizeof(u64)); | |
9dc28efe | 1045 | |
3d396eb1 | 1046 | if (netxen_get_flash_block(adapter, |
9dc28efe | 1047 | offset, sizeof(u64), pmac) == -1) |
3d396eb1 | 1048 | return -1; |
9dc28efe | 1049 | |
f305f789 | 1050 | if (*mac == cpu_to_le64(~0ULL)) |
3d396eb1 AK |
1051 | return -1; |
1052 | } | |
1053 | return 0; | |
1054 | } | |
1055 | ||
a03d2451 | 1056 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac) |
9dc28efe DP |
1057 | { |
1058 | uint32_t crbaddr, mac_hi, mac_lo; | |
1059 | int pci_func = adapter->ahw.pci_func; | |
1060 | ||
1061 | crbaddr = CRB_MAC_BLOCK_START + | |
1062 | (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); | |
1063 | ||
f98a9f69 DP |
1064 | mac_lo = NXRD32(adapter, crbaddr); |
1065 | mac_hi = NXRD32(adapter, crbaddr+4); | |
9dc28efe | 1066 | |
9dc28efe | 1067 | if (pci_func & 1) |
2edbb454 | 1068 | *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16)); |
9dc28efe | 1069 | else |
2edbb454 | 1070 | *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32)); |
9dc28efe DP |
1071 | |
1072 | return 0; | |
1073 | } | |
1074 | ||
3d396eb1 AK |
1075 | /* |
1076 | * Changes the CRB window to the specified window. | |
1077 | */ | |
195c5f98 | 1078 | static void |
907fa120 DP |
1079 | netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter, |
1080 | u32 window) | |
3d396eb1 AK |
1081 | { |
1082 | void __iomem *offset; | |
907fa120 DP |
1083 | int count = 10; |
1084 | u8 func = adapter->ahw.pci_func; | |
3d396eb1 | 1085 | |
907fa120 | 1086 | if (adapter->ahw.crb_win == window) |
3d396eb1 | 1087 | return; |
907fa120 | 1088 | |
e4c93c81 DP |
1089 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
1090 | NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func))); | |
3d396eb1 | 1091 | |
907fa120 DP |
1092 | writel(window, offset); |
1093 | do { | |
1094 | if (window == readl(offset)) | |
1095 | break; | |
3d396eb1 | 1096 | |
907fa120 DP |
1097 | if (printk_ratelimit()) |
1098 | dev_warn(&adapter->pdev->dev, | |
1099 | "failed to set CRB window to %d\n", | |
1100 | (window == NETXEN_WINDOW_ONE)); | |
1101 | udelay(1); | |
3d396eb1 | 1102 | |
907fa120 | 1103 | } while (--count > 0); |
3d396eb1 | 1104 | |
907fa120 DP |
1105 | if (count > 0) |
1106 | adapter->ahw.crb_win = window; | |
3d396eb1 AK |
1107 | } |
1108 | ||
3ce06a32 | 1109 | /* |
7cecdca1 | 1110 | * Returns < 0 if off is not valid, |
3ce06a32 DP |
1111 | * 1 if window access is needed. 'off' is set to offset from |
1112 | * CRB space in 128M pci map | |
1113 | * 0 if no window access is needed. 'off' is set to 2M addr | |
1114 | * In: 'off' is offset from base in 128M pci map | |
1115 | */ | |
1116 | static int | |
a9ac07de DP |
1117 | netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, |
1118 | ulong off, void __iomem **addr) | |
3ce06a32 | 1119 | { |
3ce06a32 DP |
1120 | crb_128M_2M_sub_block_map_t *m; |
1121 | ||
1122 | ||
a9ac07de | 1123 | if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE)) |
7cecdca1 | 1124 | return -EINVAL; |
3ce06a32 | 1125 | |
a9ac07de | 1126 | off -= NETXEN_PCI_CRBSPACE; |
3ce06a32 DP |
1127 | |
1128 | /* | |
1129 | * Try direct map | |
1130 | */ | |
a9ac07de | 1131 | m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)]; |
3ce06a32 | 1132 | |
a9ac07de DP |
1133 | if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) { |
1134 | *addr = adapter->ahw.pci_base0 + m->start_2M + | |
1135 | (off - m->start_128M); | |
3ce06a32 DP |
1136 | return 0; |
1137 | } | |
1138 | ||
1139 | /* | |
1140 | * Not in direct map, use crb window | |
1141 | */ | |
a9ac07de DP |
1142 | *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + |
1143 | (off & MASK(16)); | |
3ce06a32 DP |
1144 | return 1; |
1145 | } | |
1146 | ||
1147 | /* | |
1148 | * In: 'off' is offset from CRB space in 128M pci map | |
1149 | * Out: 'off' is 2M pci map addr | |
1150 | * side effect: lock crb window | |
1151 | */ | |
1152 | static void | |
a9ac07de | 1153 | netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off) |
3ce06a32 | 1154 | { |
907fa120 DP |
1155 | u32 window; |
1156 | void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M; | |
3ce06a32 | 1157 | |
a9ac07de DP |
1158 | off -= NETXEN_PCI_CRBSPACE; |
1159 | ||
1160 | window = CRB_HI(off); | |
907fa120 DP |
1161 | |
1162 | if (adapter->ahw.crb_win == window) | |
a9ac07de | 1163 | return; |
907fa120 DP |
1164 | |
1165 | writel(window, addr); | |
1166 | if (readl(addr) != window) { | |
1167 | if (printk_ratelimit()) | |
1168 | dev_warn(&adapter->pdev->dev, | |
1169 | "failed to set CRB window to %d off 0x%lx\n", | |
a9ac07de | 1170 | window, off); |
3ce06a32 | 1171 | } |
907fa120 | 1172 | adapter->ahw.crb_win = window; |
3ce06a32 DP |
1173 | } |
1174 | ||
f58dbd73 NK |
1175 | static void __iomem * |
1176 | netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter, | |
1177 | ulong win_off, void __iomem **mem_ptr) | |
1178 | { | |
1179 | ulong off = win_off; | |
1180 | void __iomem *addr; | |
1181 | resource_size_t mem_base; | |
1182 | ||
1183 | if (ADDR_IN_WINDOW1(win_off)) | |
1184 | off = NETXEN_CRB_NORMAL(win_off); | |
1185 | ||
1186 | addr = pci_base_offset(adapter, off); | |
1187 | if (addr) | |
1188 | return addr; | |
1189 | ||
1190 | if (adapter->ahw.pci_len0 == 0) | |
1191 | off -= NETXEN_PCI_CRBSPACE; | |
1192 | ||
1193 | mem_base = pci_resource_start(adapter->pdev, 0); | |
1194 | *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE); | |
1195 | if (*mem_ptr) | |
1196 | addr = *mem_ptr + (off & (PAGE_SIZE - 1)); | |
1197 | ||
1198 | return addr; | |
1199 | } | |
1200 | ||
195c5f98 | 1201 | static int |
1fbe6323 | 1202 | netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data) |
3d396eb1 | 1203 | { |
195c5f98 | 1204 | unsigned long flags; |
f58dbd73 | 1205 | void __iomem *addr, *mem_ptr = NULL; |
3d396eb1 | 1206 | |
f58dbd73 NK |
1207 | addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr); |
1208 | if (!addr) | |
1209 | return -EIO; | |
195c5f98 | 1210 | |
f58dbd73 | 1211 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ |
f03b0ebd | 1212 | netxen_nic_io_write_128M(adapter, addr, data); |
f58dbd73 | 1213 | } else { /* Window 0 */ |
f03b0ebd | 1214 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
907fa120 | 1215 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
195c5f98 | 1216 | writel(data, addr); |
907fa120 DP |
1217 | netxen_nic_pci_set_crbwindow_128M(adapter, |
1218 | NETXEN_WINDOW_ONE); | |
f03b0ebd | 1219 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
cb8011ad AK |
1220 | } |
1221 | ||
f58dbd73 NK |
1222 | if (mem_ptr) |
1223 | iounmap(mem_ptr); | |
1224 | ||
3d396eb1 AK |
1225 | return 0; |
1226 | } | |
1227 | ||
195c5f98 | 1228 | static u32 |
1fbe6323 | 1229 | netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off) |
3d396eb1 | 1230 | { |
195c5f98 | 1231 | unsigned long flags; |
f58dbd73 | 1232 | void __iomem *addr, *mem_ptr = NULL; |
1fbe6323 | 1233 | u32 data; |
d8313ce0 | 1234 | |
f58dbd73 NK |
1235 | addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr); |
1236 | if (!addr) | |
1237 | return -EIO; | |
3d396eb1 | 1238 | |
f58dbd73 | 1239 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ |
f03b0ebd | 1240 | data = netxen_nic_io_read_128M(adapter, addr); |
f58dbd73 | 1241 | } else { /* Window 0 */ |
f03b0ebd | 1242 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
907fa120 | 1243 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
195c5f98 | 1244 | data = readl(addr); |
907fa120 DP |
1245 | netxen_nic_pci_set_crbwindow_128M(adapter, |
1246 | NETXEN_WINDOW_ONE); | |
f03b0ebd | 1247 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
195c5f98 | 1248 | } |
3d396eb1 | 1249 | |
f58dbd73 NK |
1250 | if (mem_ptr) |
1251 | iounmap(mem_ptr); | |
1252 | ||
1fbe6323 | 1253 | return data; |
3d396eb1 AK |
1254 | } |
1255 | ||
195c5f98 | 1256 | static int |
1fbe6323 | 1257 | netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data) |
3ce06a32 | 1258 | { |
195c5f98 | 1259 | unsigned long flags; |
3ce06a32 | 1260 | int rv; |
a9ac07de | 1261 | void __iomem *addr = NULL; |
3d396eb1 | 1262 | |
a9ac07de | 1263 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr); |
3d396eb1 | 1264 | |
7cecdca1 | 1265 | if (rv == 0) { |
a9ac07de | 1266 | writel(data, addr); |
7cecdca1 | 1267 | return 0; |
3ce06a32 DP |
1268 | } |
1269 | ||
7cecdca1 DP |
1270 | if (rv > 0) { |
1271 | /* indirect access */ | |
f03b0ebd | 1272 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
3ce06a32 | 1273 | crb_win_lock(adapter); |
a9ac07de DP |
1274 | netxen_nic_pci_set_crbwindow_2M(adapter, off); |
1275 | writel(data, addr); | |
3ce06a32 | 1276 | crb_win_unlock(adapter); |
f03b0ebd | 1277 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
7cecdca1 DP |
1278 | return 0; |
1279 | } | |
3ce06a32 | 1280 | |
7cecdca1 DP |
1281 | dev_err(&adapter->pdev->dev, |
1282 | "%s: invalid offset: 0x%016lx\n", __func__, off); | |
1283 | dump_stack(); | |
1284 | return -EIO; | |
3d396eb1 AK |
1285 | } |
1286 | ||
195c5f98 | 1287 | static u32 |
1fbe6323 | 1288 | netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off) |
3ce06a32 | 1289 | { |
195c5f98 | 1290 | unsigned long flags; |
3ce06a32 | 1291 | int rv; |
1fbe6323 | 1292 | u32 data; |
a9ac07de | 1293 | void __iomem *addr = NULL; |
3d396eb1 | 1294 | |
a9ac07de | 1295 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr); |
3ce06a32 | 1296 | |
7cecdca1 | 1297 | if (rv == 0) |
a9ac07de | 1298 | return readl(addr); |
3ce06a32 | 1299 | |
7cecdca1 DP |
1300 | if (rv > 0) { |
1301 | /* indirect access */ | |
f03b0ebd | 1302 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
3ce06a32 | 1303 | crb_win_lock(adapter); |
a9ac07de DP |
1304 | netxen_nic_pci_set_crbwindow_2M(adapter, off); |
1305 | data = readl(addr); | |
3ce06a32 | 1306 | crb_win_unlock(adapter); |
f03b0ebd | 1307 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
7cecdca1 DP |
1308 | return data; |
1309 | } | |
3ce06a32 | 1310 | |
7cecdca1 DP |
1311 | dev_err(&adapter->pdev->dev, |
1312 | "%s: invalid offset: 0x%016lx\n", __func__, off); | |
1313 | dump_stack(); | |
1314 | return -1; | |
3ce06a32 DP |
1315 | } |
1316 | ||
195c5f98 AKS |
1317 | /* window 1 registers only */ |
1318 | static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, | |
1319 | void __iomem *addr, u32 data) | |
3ce06a32 | 1320 | { |
f03b0ebd | 1321 | read_lock(&adapter->ahw.crb_lock); |
195c5f98 | 1322 | writel(data, addr); |
f03b0ebd | 1323 | read_unlock(&adapter->ahw.crb_lock); |
195c5f98 AKS |
1324 | } |
1325 | ||
1326 | static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, | |
1327 | void __iomem *addr) | |
1328 | { | |
1329 | u32 val; | |
1330 | ||
f03b0ebd | 1331 | read_lock(&adapter->ahw.crb_lock); |
195c5f98 | 1332 | val = readl(addr); |
f03b0ebd | 1333 | read_unlock(&adapter->ahw.crb_lock); |
195c5f98 AKS |
1334 | |
1335 | return val; | |
3ce06a32 DP |
1336 | } |
1337 | ||
195c5f98 AKS |
1338 | static void netxen_nic_io_write_2M(struct netxen_adapter *adapter, |
1339 | void __iomem *addr, u32 data) | |
3ce06a32 | 1340 | { |
195c5f98 AKS |
1341 | writel(data, addr); |
1342 | } | |
1343 | ||
1344 | static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter, | |
1345 | void __iomem *addr) | |
1346 | { | |
1347 | return readl(addr); | |
1348 | } | |
1349 | ||
1350 | void __iomem * | |
1351 | netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset) | |
1352 | { | |
a9ac07de | 1353 | void __iomem *addr = NULL; |
195c5f98 AKS |
1354 | |
1355 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
a9ac07de DP |
1356 | if ((offset < NETXEN_CRB_PCIX_HOST2) && |
1357 | (offset > NETXEN_CRB_PCIX_HOST)) | |
1358 | addr = PCI_OFFSET_SECOND_RANGE(adapter, offset); | |
1359 | else | |
1360 | addr = NETXEN_CRB_NORMALIZE(adapter, offset); | |
1361 | } else { | |
1362 | WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter, | |
1363 | offset, &addr)); | |
195c5f98 AKS |
1364 | } |
1365 | ||
a9ac07de | 1366 | return addr; |
3ce06a32 DP |
1367 | } |
1368 | ||
47abe356 DP |
1369 | static int |
1370 | netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, | |
1371 | u64 addr, u32 *start) | |
3ce06a32 | 1372 | { |
47abe356 DP |
1373 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
1374 | *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0); | |
1375 | return 0; | |
3ce06a32 | 1376 | } else if (ADDR_IN_RANGE(addr, |
47abe356 DP |
1377 | NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { |
1378 | *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1); | |
1379 | return 0; | |
1380 | } | |
3ce06a32 | 1381 | |
47abe356 DP |
1382 | return -EIO; |
1383 | } | |
3ce06a32 | 1384 | |
47abe356 DP |
1385 | static int |
1386 | netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |
1387 | u64 addr, u32 *start) | |
1388 | { | |
6abb4b83 | 1389 | u32 window; |
3ce06a32 | 1390 | |
14e2cfbb | 1391 | window = OCM_WIN(addr); |
6abb4b83 | 1392 | |
47abe356 | 1393 | writel(window, adapter->ahw.ocm_win_crb); |
6abb4b83 AKS |
1394 | /* read back to flush */ |
1395 | readl(adapter->ahw.ocm_win_crb); | |
47abe356 DP |
1396 | |
1397 | adapter->ahw.ocm_win = window; | |
1398 | *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr); | |
1399 | return 0; | |
3ce06a32 | 1400 | } |
47abe356 DP |
1401 | |
1402 | static int | |
1403 | netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off, | |
1404 | u64 *data, int op) | |
1405 | { | |
1406 | void __iomem *addr, *mem_ptr = NULL; | |
1407 | resource_size_t mem_base; | |
14e2cfbb | 1408 | int ret; |
47abe356 DP |
1409 | u32 start; |
1410 | ||
f03b0ebd | 1411 | spin_lock(&adapter->ahw.mem_lock); |
47abe356 DP |
1412 | |
1413 | ret = adapter->pci_set_window(adapter, off, &start); | |
1414 | if (ret != 0) | |
1415 | goto unlock; | |
1416 | ||
14e2cfbb SC |
1417 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
1418 | addr = adapter->ahw.pci_base0 + start; | |
1419 | } else { | |
1420 | addr = pci_base_offset(adapter, start); | |
1421 | if (addr) | |
1422 | goto noremap; | |
1423 | ||
1424 | mem_base = pci_resource_start(adapter->pdev, 0) + | |
1425 | (start & PAGE_MASK); | |
1426 | mem_ptr = ioremap(mem_base, PAGE_SIZE); | |
1427 | if (mem_ptr == NULL) { | |
1428 | ret = -EIO; | |
1429 | goto unlock; | |
1430 | } | |
47abe356 | 1431 | |
14e2cfbb | 1432 | addr = mem_ptr + (start & (PAGE_SIZE-1)); |
3d396eb1 | 1433 | } |
47abe356 DP |
1434 | noremap: |
1435 | if (op == 0) /* read */ | |
1436 | *data = readq(addr); | |
1437 | else /* write */ | |
1438 | writeq(*data, addr); | |
1439 | ||
1440 | unlock: | |
f03b0ebd DP |
1441 | spin_unlock(&adapter->ahw.mem_lock); |
1442 | ||
47abe356 DP |
1443 | if (mem_ptr) |
1444 | iounmap(mem_ptr); | |
1445 | return ret; | |
3d396eb1 AK |
1446 | } |
1447 | ||
0b9715e6 AKS |
1448 | void |
1449 | netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data) | |
1450 | { | |
1451 | void __iomem *addr = adapter->ahw.pci_base0 + | |
1452 | NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM); | |
1453 | ||
1454 | spin_lock(&adapter->ahw.mem_lock); | |
1455 | *data = readq(addr); | |
1456 | spin_unlock(&adapter->ahw.mem_lock); | |
1457 | } | |
1458 | ||
1459 | void | |
1460 | netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data) | |
1461 | { | |
1462 | void __iomem *addr = adapter->ahw.pci_base0 + | |
1463 | NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM); | |
1464 | ||
1465 | spin_lock(&adapter->ahw.mem_lock); | |
1466 | writeq(data, addr); | |
1467 | spin_unlock(&adapter->ahw.mem_lock); | |
1468 | } | |
1469 | ||
3ce06a32 DP |
1470 | #define MAX_CTL_CHECK 1000 |
1471 | ||
195c5f98 | 1472 | static int |
3ce06a32 | 1473 | netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, |
1f5e055d | 1474 | u64 off, u64 data) |
3ce06a32 | 1475 | { |
1f5e055d AKS |
1476 | int j, ret; |
1477 | u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo; | |
d8313ce0 | 1478 | void __iomem *mem_crb; |
3ce06a32 | 1479 | |
1f5e055d AKS |
1480 | /* Only 64-bit aligned access */ |
1481 | if (off & 7) | |
ea6828b8 DP |
1482 | return -EIO; |
1483 | ||
1f5e055d | 1484 | /* P2 has different SIU and MIU test agent base addr */ |
ea6828b8 DP |
1485 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1486 | NETXEN_ADDR_QDR_NET_MAX_P2)) { | |
1f5e055d AKS |
1487 | mem_crb = pci_base_offset(adapter, |
1488 | NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE); | |
1489 | addr_hi = SIU_TEST_AGT_ADDR_HI; | |
1490 | data_lo = SIU_TEST_AGT_WRDATA_LO; | |
1491 | data_hi = SIU_TEST_AGT_WRDATA_HI; | |
1492 | off_lo = off & SIU_TEST_AGT_ADDR_MASK; | |
1493 | off_hi = SIU_TEST_AGT_UPPER_ADDR(off); | |
ea6828b8 DP |
1494 | goto correct; |
1495 | } | |
3ce06a32 | 1496 | |
ea6828b8 | 1497 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
1f5e055d AKS |
1498 | mem_crb = pci_base_offset(adapter, |
1499 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
1500 | addr_hi = MIU_TEST_AGT_ADDR_HI; | |
1501 | data_lo = MIU_TEST_AGT_WRDATA_LO; | |
1502 | data_hi = MIU_TEST_AGT_WRDATA_HI; | |
1503 | off_lo = off & MIU_TEST_AGT_ADDR_MASK; | |
1504 | off_hi = 0; | |
ea6828b8 DP |
1505 | goto correct; |
1506 | } | |
1507 | ||
47abe356 DP |
1508 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) || |
1509 | ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { | |
1510 | if (adapter->ahw.pci_len0 != 0) { | |
1511 | return netxen_nic_pci_mem_access_direct(adapter, | |
1512 | off, &data, 1); | |
1513 | } | |
1514 | } | |
1515 | ||
ea6828b8 DP |
1516 | return -EIO; |
1517 | ||
1518 | correct: | |
f03b0ebd | 1519 | spin_lock(&adapter->ahw.mem_lock); |
907fa120 | 1520 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
3ce06a32 | 1521 | |
1f5e055d AKS |
1522 | writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1523 | writel(off_hi, (mem_crb + addr_hi)); | |
1524 | writel(data & 0xffffffff, (mem_crb + data_lo)); | |
1525 | writel((data >> 32) & 0xffffffff, (mem_crb + data_hi)); | |
1526 | writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); | |
1527 | writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), | |
1528 | (mem_crb + TEST_AGT_CTRL)); | |
1529 | ||
1530 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1531 | temp = readl((mem_crb + TEST_AGT_CTRL)); | |
1532 | if ((temp & TA_CTL_BUSY) == 0) | |
3ce06a32 | 1533 | break; |
3ce06a32 DP |
1534 | } |
1535 | ||
1f5e055d AKS |
1536 | if (j >= MAX_CTL_CHECK) { |
1537 | if (printk_ratelimit()) | |
1538 | dev_err(&adapter->pdev->dev, | |
1539 | "failed to write through agent\n"); | |
1540 | ret = -EIO; | |
1541 | } else | |
1542 | ret = 0; | |
1543 | ||
907fa120 | 1544 | netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE); |
f03b0ebd | 1545 | spin_unlock(&adapter->ahw.mem_lock); |
3ce06a32 DP |
1546 | return ret; |
1547 | } | |
1548 | ||
195c5f98 | 1549 | static int |
3ce06a32 | 1550 | netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, |
1f5e055d | 1551 | u64 off, u64 *data) |
3ce06a32 | 1552 | { |
1f5e055d AKS |
1553 | int j, ret; |
1554 | u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo; | |
1555 | u64 val; | |
d8313ce0 | 1556 | void __iomem *mem_crb; |
3ce06a32 | 1557 | |
1f5e055d AKS |
1558 | /* Only 64-bit aligned access */ |
1559 | if (off & 7) | |
ea6828b8 DP |
1560 | return -EIO; |
1561 | ||
1f5e055d | 1562 | /* P2 has different SIU and MIU test agent base addr */ |
ea6828b8 DP |
1563 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1564 | NETXEN_ADDR_QDR_NET_MAX_P2)) { | |
1f5e055d AKS |
1565 | mem_crb = pci_base_offset(adapter, |
1566 | NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE); | |
1567 | addr_hi = SIU_TEST_AGT_ADDR_HI; | |
1568 | data_lo = SIU_TEST_AGT_RDDATA_LO; | |
1569 | data_hi = SIU_TEST_AGT_RDDATA_HI; | |
1570 | off_lo = off & SIU_TEST_AGT_ADDR_MASK; | |
1571 | off_hi = SIU_TEST_AGT_UPPER_ADDR(off); | |
ea6828b8 DP |
1572 | goto correct; |
1573 | } | |
3ce06a32 | 1574 | |
ea6828b8 | 1575 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
1f5e055d AKS |
1576 | mem_crb = pci_base_offset(adapter, |
1577 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
1578 | addr_hi = MIU_TEST_AGT_ADDR_HI; | |
1579 | data_lo = MIU_TEST_AGT_RDDATA_LO; | |
1580 | data_hi = MIU_TEST_AGT_RDDATA_HI; | |
1581 | off_lo = off & MIU_TEST_AGT_ADDR_MASK; | |
1582 | off_hi = 0; | |
ea6828b8 DP |
1583 | goto correct; |
1584 | } | |
1585 | ||
47abe356 DP |
1586 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) || |
1587 | ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { | |
1588 | if (adapter->ahw.pci_len0 != 0) { | |
1589 | return netxen_nic_pci_mem_access_direct(adapter, | |
1590 | off, data, 0); | |
1591 | } | |
1592 | } | |
1593 | ||
ea6828b8 | 1594 | return -EIO; |
3ce06a32 | 1595 | |
ea6828b8 | 1596 | correct: |
f03b0ebd | 1597 | spin_lock(&adapter->ahw.mem_lock); |
907fa120 | 1598 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
3ce06a32 | 1599 | |
1f5e055d AKS |
1600 | writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1601 | writel(off_hi, (mem_crb + addr_hi)); | |
1602 | writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); | |
1603 | writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL)); | |
3ce06a32 | 1604 | |
1f5e055d AKS |
1605 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
1606 | temp = readl(mem_crb + TEST_AGT_CTRL); | |
1607 | if ((temp & TA_CTL_BUSY) == 0) | |
3ce06a32 | 1608 | break; |
1f5e055d | 1609 | } |
3ce06a32 | 1610 | |
1f5e055d AKS |
1611 | if (j >= MAX_CTL_CHECK) { |
1612 | if (printk_ratelimit()) | |
1613 | dev_err(&adapter->pdev->dev, | |
1614 | "failed to read through agent\n"); | |
1615 | ret = -EIO; | |
1616 | } else { | |
1617 | ||
1618 | temp = readl(mem_crb + data_hi); | |
1619 | val = ((u64)temp << 32); | |
1620 | val |= readl(mem_crb + data_lo); | |
1621 | *data = val; | |
1622 | ret = 0; | |
3ce06a32 DP |
1623 | } |
1624 | ||
907fa120 | 1625 | netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE); |
f03b0ebd | 1626 | spin_unlock(&adapter->ahw.mem_lock); |
3ce06a32 | 1627 | |
1f5e055d | 1628 | return ret; |
3ce06a32 DP |
1629 | } |
1630 | ||
195c5f98 | 1631 | static int |
3ce06a32 | 1632 | netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, |
1f5e055d | 1633 | u64 off, u64 data) |
3ce06a32 | 1634 | { |
215387a4 | 1635 | int j, ret; |
1f5e055d | 1636 | u32 temp, off8; |
ea6828b8 | 1637 | void __iomem *mem_crb; |
3ce06a32 | 1638 | |
1f5e055d AKS |
1639 | /* Only 64-bit aligned access */ |
1640 | if (off & 7) | |
ea6828b8 DP |
1641 | return -EIO; |
1642 | ||
1f5e055d | 1643 | /* P3 onward, test agent base for MIU and SIU is same */ |
ea6828b8 DP |
1644 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1645 | NETXEN_ADDR_QDR_NET_MAX_P3)) { | |
1f5e055d AKS |
1646 | mem_crb = netxen_get_ioaddr(adapter, |
1647 | NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 DP |
1648 | goto correct; |
1649 | } | |
1650 | ||
1651 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { | |
1f5e055d AKS |
1652 | mem_crb = netxen_get_ioaddr(adapter, |
1653 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 | 1654 | goto correct; |
3ce06a32 DP |
1655 | } |
1656 | ||
47abe356 DP |
1657 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) |
1658 | return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1); | |
1659 | ||
ea6828b8 DP |
1660 | return -EIO; |
1661 | ||
1662 | correct: | |
215387a4 | 1663 | off8 = off & 0xfffffff8; |
3ce06a32 | 1664 | |
f03b0ebd | 1665 | spin_lock(&adapter->ahw.mem_lock); |
3ce06a32 | 1666 | |
1f5e055d AKS |
1667 | writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1668 | writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); | |
fb1f6a43 | 1669 | |
fb1f6a43 | 1670 | writel(data & 0xffffffff, |
215387a4 | 1671 | mem_crb + MIU_TEST_AGT_WRDATA_LO); |
fb1f6a43 | 1672 | writel((data >> 32) & 0xffffffff, |
215387a4 | 1673 | mem_crb + MIU_TEST_AGT_WRDATA_HI); |
fb1f6a43 | 1674 | |
1f5e055d AKS |
1675 | writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); |
1676 | writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), | |
1677 | (mem_crb + TEST_AGT_CTRL)); | |
1678 | ||
1679 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1680 | temp = readl(mem_crb + TEST_AGT_CTRL); | |
1681 | if ((temp & TA_CTL_BUSY) == 0) | |
1682 | break; | |
3ce06a32 DP |
1683 | } |
1684 | ||
1f5e055d AKS |
1685 | if (j >= MAX_CTL_CHECK) { |
1686 | if (printk_ratelimit()) | |
1687 | dev_err(&adapter->pdev->dev, | |
39754f44 | 1688 | "failed to write through agent\n"); |
1f5e055d AKS |
1689 | ret = -EIO; |
1690 | } else | |
1691 | ret = 0; | |
1692 | ||
f03b0ebd | 1693 | spin_unlock(&adapter->ahw.mem_lock); |
3ce06a32 | 1694 | |
3ce06a32 DP |
1695 | return ret; |
1696 | } | |
1697 | ||
195c5f98 | 1698 | static int |
3ce06a32 | 1699 | netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, |
1f5e055d | 1700 | u64 off, u64 *data) |
3ce06a32 | 1701 | { |
1f5e055d AKS |
1702 | int j, ret; |
1703 | u32 temp, off8; | |
215387a4 | 1704 | u64 val; |
ea6828b8 | 1705 | void __iomem *mem_crb; |
3ce06a32 | 1706 | |
1f5e055d AKS |
1707 | /* Only 64-bit aligned access */ |
1708 | if (off & 7) | |
ea6828b8 | 1709 | return -EIO; |
3ce06a32 | 1710 | |
1f5e055d | 1711 | /* P3 onward, test agent base for MIU and SIU is same */ |
ea6828b8 DP |
1712 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1713 | NETXEN_ADDR_QDR_NET_MAX_P3)) { | |
1f5e055d AKS |
1714 | mem_crb = netxen_get_ioaddr(adapter, |
1715 | NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 | 1716 | goto correct; |
3ce06a32 DP |
1717 | } |
1718 | ||
ea6828b8 | 1719 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
1f5e055d AKS |
1720 | mem_crb = netxen_get_ioaddr(adapter, |
1721 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 DP |
1722 | goto correct; |
1723 | } | |
1724 | ||
907fa120 DP |
1725 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
1726 | return netxen_nic_pci_mem_access_direct(adapter, | |
1727 | off, data, 0); | |
1728 | } | |
47abe356 | 1729 | |
ea6828b8 DP |
1730 | return -EIO; |
1731 | ||
1732 | correct: | |
215387a4 | 1733 | off8 = off & 0xfffffff8; |
3ce06a32 | 1734 | |
f03b0ebd | 1735 | spin_lock(&adapter->ahw.mem_lock); |
3ce06a32 | 1736 | |
1f5e055d AKS |
1737 | writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1738 | writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); | |
1739 | writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); | |
1740 | writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL)); | |
3ce06a32 | 1741 | |
1f5e055d AKS |
1742 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
1743 | temp = readl(mem_crb + TEST_AGT_CTRL); | |
1744 | if ((temp & TA_CTL_BUSY) == 0) | |
3ce06a32 | 1745 | break; |
3ce06a32 DP |
1746 | } |
1747 | ||
1f5e055d AKS |
1748 | if (j >= MAX_CTL_CHECK) { |
1749 | if (printk_ratelimit()) | |
1750 | dev_err(&adapter->pdev->dev, | |
1751 | "failed to read through agent\n"); | |
1752 | ret = -EIO; | |
3ce06a32 | 1753 | } else { |
215387a4 SC |
1754 | val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32; |
1755 | val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO); | |
1f5e055d AKS |
1756 | *data = val; |
1757 | ret = 0; | |
3ce06a32 DP |
1758 | } |
1759 | ||
f03b0ebd | 1760 | spin_unlock(&adapter->ahw.mem_lock); |
1f5e055d AKS |
1761 | |
1762 | return ret; | |
3ce06a32 DP |
1763 | } |
1764 | ||
195c5f98 AKS |
1765 | void |
1766 | netxen_setup_hwops(struct netxen_adapter *adapter) | |
3ce06a32 | 1767 | { |
195c5f98 AKS |
1768 | adapter->init_port = netxen_niu_xg_init_port; |
1769 | adapter->stop_port = netxen_niu_disable_xg_port; | |
3ce06a32 | 1770 | |
195c5f98 AKS |
1771 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
1772 | adapter->crb_read = netxen_nic_hw_read_wx_128M, | |
1773 | adapter->crb_write = netxen_nic_hw_write_wx_128M, | |
1774 | adapter->pci_set_window = netxen_nic_pci_set_window_128M, | |
1775 | adapter->pci_mem_read = netxen_nic_pci_mem_read_128M, | |
1776 | adapter->pci_mem_write = netxen_nic_pci_mem_write_128M, | |
1777 | adapter->io_read = netxen_nic_io_read_128M, | |
1778 | adapter->io_write = netxen_nic_io_write_128M, | |
1779 | ||
1780 | adapter->macaddr_set = netxen_p2_nic_set_mac_addr; | |
1781 | adapter->set_multi = netxen_p2_nic_set_multi; | |
1782 | adapter->set_mtu = netxen_nic_set_mtu_xgb; | |
1783 | adapter->set_promisc = netxen_p2_nic_set_promisc; | |
3ce06a32 | 1784 | |
195c5f98 AKS |
1785 | } else { |
1786 | adapter->crb_read = netxen_nic_hw_read_wx_2M, | |
1787 | adapter->crb_write = netxen_nic_hw_write_wx_2M, | |
1788 | adapter->pci_set_window = netxen_nic_pci_set_window_2M, | |
1789 | adapter->pci_mem_read = netxen_nic_pci_mem_read_2M, | |
1790 | adapter->pci_mem_write = netxen_nic_pci_mem_write_2M, | |
1791 | adapter->io_read = netxen_nic_io_read_2M, | |
1792 | adapter->io_write = netxen_nic_io_write_2M, | |
1793 | ||
1794 | adapter->set_mtu = nx_fw_cmd_set_mtu; | |
1795 | adapter->set_promisc = netxen_p3_nic_set_promisc; | |
1796 | adapter->macaddr_set = netxen_p3_nic_set_mac_addr; | |
1797 | adapter->set_multi = netxen_p3_nic_set_multi; | |
1798 | ||
1799 | adapter->phy_read = nx_fw_cmd_query_phy; | |
1800 | adapter->phy_write = nx_fw_cmd_set_phy; | |
1801 | } | |
3ce06a32 DP |
1802 | } |
1803 | ||
3d396eb1 AK |
1804 | int netxen_nic_get_board_info(struct netxen_adapter *adapter) |
1805 | { | |
0dc6d9cb | 1806 | int offset, board_type, magic; |
1e2d0059 | 1807 | struct pci_dev *pdev = adapter->pdev; |
3d396eb1 | 1808 | |
06db58c0 | 1809 | offset = NX_FW_MAGIC_OFFSET; |
1e2d0059 DP |
1810 | if (netxen_rom_fast_read(adapter, offset, &magic)) |
1811 | return -EIO; | |
3d396eb1 | 1812 | |
0dc6d9cb DP |
1813 | if (magic != NETXEN_BDINFO_MAGIC) { |
1814 | dev_err(&pdev->dev, "invalid board config, magic=%08x\n", | |
1815 | magic); | |
1e2d0059 | 1816 | return -EIO; |
3d396eb1 AK |
1817 | } |
1818 | ||
06db58c0 | 1819 | offset = NX_BRDTYPE_OFFSET; |
1e2d0059 DP |
1820 | if (netxen_rom_fast_read(adapter, offset, &board_type)) |
1821 | return -EIO; | |
1822 | ||
1823 | adapter->ahw.board_type = board_type; | |
1824 | ||
1825 | if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { | |
f98a9f69 | 1826 | u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I); |
c7860a2a | 1827 | if ((gpio & 0x8000) == 0) |
1e2d0059 | 1828 | board_type = NETXEN_BRDTYPE_P3_10G_TP; |
c7860a2a DP |
1829 | } |
1830 | ||
e98e3350 | 1831 | switch (board_type) { |
3d396eb1 | 1832 | case NETXEN_BRDTYPE_P2_SB35_4G: |
1e2d0059 | 1833 | adapter->ahw.port_type = NETXEN_NIC_GBE; |
3d396eb1 AK |
1834 | break; |
1835 | case NETXEN_BRDTYPE_P2_SB31_10G: | |
1836 | case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: | |
1837 | case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: | |
1838 | case NETXEN_BRDTYPE_P2_SB31_10G_CX4: | |
e4c93c81 DP |
1839 | case NETXEN_BRDTYPE_P3_HMEZ: |
1840 | case NETXEN_BRDTYPE_P3_XG_LOM: | |
1841 | case NETXEN_BRDTYPE_P3_10G_CX4: | |
1842 | case NETXEN_BRDTYPE_P3_10G_CX4_LP: | |
1843 | case NETXEN_BRDTYPE_P3_IMEZ: | |
1844 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: | |
a70f9393 DP |
1845 | case NETXEN_BRDTYPE_P3_10G_SFP_CT: |
1846 | case NETXEN_BRDTYPE_P3_10G_SFP_QT: | |
e4c93c81 DP |
1847 | case NETXEN_BRDTYPE_P3_10G_XFP: |
1848 | case NETXEN_BRDTYPE_P3_10000_BASE_T: | |
1e2d0059 | 1849 | adapter->ahw.port_type = NETXEN_NIC_XGBE; |
3d396eb1 AK |
1850 | break; |
1851 | case NETXEN_BRDTYPE_P1_BD: | |
1852 | case NETXEN_BRDTYPE_P1_SB: | |
1853 | case NETXEN_BRDTYPE_P1_SMAX: | |
1854 | case NETXEN_BRDTYPE_P1_SOCK: | |
e4c93c81 DP |
1855 | case NETXEN_BRDTYPE_P3_REF_QG: |
1856 | case NETXEN_BRDTYPE_P3_4_GB: | |
1857 | case NETXEN_BRDTYPE_P3_4_GB_MM: | |
1e2d0059 | 1858 | adapter->ahw.port_type = NETXEN_NIC_GBE; |
3d396eb1 | 1859 | break; |
c7860a2a | 1860 | case NETXEN_BRDTYPE_P3_10G_TP: |
1e2d0059 | 1861 | adapter->ahw.port_type = (adapter->portnum < 2) ? |
c7860a2a DP |
1862 | NETXEN_NIC_XGBE : NETXEN_NIC_GBE; |
1863 | break; | |
3d396eb1 | 1864 | default: |
1e2d0059 DP |
1865 | dev_err(&pdev->dev, "unknown board type %x\n", board_type); |
1866 | adapter->ahw.port_type = NETXEN_NIC_XGBE; | |
3d396eb1 AK |
1867 | break; |
1868 | } | |
1869 | ||
1e2d0059 | 1870 | return 0; |
3d396eb1 AK |
1871 | } |
1872 | ||
1873 | /* NIU access sections */ | |
1874 | ||
3176ff3e | 1875 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 1876 | { |
9ad27643 | 1877 | new_mtu += MTU_FUDGE_FACTOR; |
f98a9f69 | 1878 | NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), |
3276fbad | 1879 | new_mtu); |
3d396eb1 AK |
1880 | return 0; |
1881 | } | |
1882 | ||
3176ff3e | 1883 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 1884 | { |
9ad27643 | 1885 | new_mtu += MTU_FUDGE_FACTOR; |
3276fbad | 1886 | if (adapter->physical_port == 0) |
f98a9f69 | 1887 | NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu); |
4790654c | 1888 | else |
f98a9f69 | 1889 | NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu); |
3d396eb1 AK |
1890 | return 0; |
1891 | } | |
1892 | ||
3176ff3e | 1893 | void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) |
3d396eb1 | 1894 | { |
a608ab9c AV |
1895 | __u32 status; |
1896 | __u32 autoneg; | |
24a7a455 | 1897 | __u32 port_mode; |
3d396eb1 | 1898 | |
c7860a2a DP |
1899 | if (!netif_carrier_ok(adapter->netdev)) { |
1900 | adapter->link_speed = 0; | |
1901 | adapter->link_duplex = -1; | |
1902 | adapter->link_autoneg = AUTONEG_ENABLE; | |
1903 | return; | |
1904 | } | |
24a7a455 | 1905 | |
1e2d0059 | 1906 | if (adapter->ahw.port_type == NETXEN_NIC_GBE) { |
f98a9f69 | 1907 | port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR); |
24a7a455 DP |
1908 | if (port_mode == NETXEN_PORT_MODE_802_3_AP) { |
1909 | adapter->link_speed = SPEED_1000; | |
1910 | adapter->link_duplex = DUPLEX_FULL; | |
1911 | adapter->link_autoneg = AUTONEG_DISABLE; | |
1912 | return; | |
1913 | } | |
1914 | ||
8e95a202 JP |
1915 | if (adapter->phy_read && |
1916 | adapter->phy_read(adapter, | |
1917 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, | |
1918 | &status) == 0) { | |
3d396eb1 AK |
1919 | if (netxen_get_phy_link(status)) { |
1920 | switch (netxen_get_phy_speed(status)) { | |
1921 | case 0: | |
3176ff3e | 1922 | adapter->link_speed = SPEED_10; |
3d396eb1 AK |
1923 | break; |
1924 | case 1: | |
3176ff3e | 1925 | adapter->link_speed = SPEED_100; |
3d396eb1 AK |
1926 | break; |
1927 | case 2: | |
3176ff3e | 1928 | adapter->link_speed = SPEED_1000; |
3d396eb1 AK |
1929 | break; |
1930 | default: | |
c7860a2a | 1931 | adapter->link_speed = 0; |
3d396eb1 AK |
1932 | break; |
1933 | } | |
1934 | switch (netxen_get_phy_duplex(status)) { | |
1935 | case 0: | |
3176ff3e | 1936 | adapter->link_duplex = DUPLEX_HALF; |
3d396eb1 AK |
1937 | break; |
1938 | case 1: | |
3176ff3e | 1939 | adapter->link_duplex = DUPLEX_FULL; |
3d396eb1 AK |
1940 | break; |
1941 | default: | |
3176ff3e | 1942 | adapter->link_duplex = -1; |
3d396eb1 AK |
1943 | break; |
1944 | } | |
8e95a202 JP |
1945 | if (adapter->phy_read && |
1946 | adapter->phy_read(adapter, | |
1947 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, | |
1948 | &autoneg) != 0) | |
3176ff3e | 1949 | adapter->link_autoneg = autoneg; |
3d396eb1 AK |
1950 | } else |
1951 | goto link_down; | |
1952 | } else { | |
1953 | link_down: | |
c7860a2a | 1954 | adapter->link_speed = 0; |
3176ff3e | 1955 | adapter->link_duplex = -1; |
3d396eb1 AK |
1956 | } |
1957 | } | |
1958 | } | |
1959 | ||
0b72e659 DP |
1960 | int |
1961 | netxen_nic_wol_supported(struct netxen_adapter *adapter) | |
1962 | { | |
1963 | u32 wol_cfg; | |
1964 | ||
1965 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
1966 | return 0; | |
1967 | ||
f98a9f69 | 1968 | wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV); |
0b72e659 | 1969 | if (wol_cfg & (1UL << adapter->portnum)) { |
f98a9f69 | 1970 | wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG); |
0b72e659 DP |
1971 | if (wol_cfg & (1 << adapter->portnum)) |
1972 | return 1; | |
1973 | } | |
1974 | ||
1975 | return 0; | |
1976 | } |