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3d396eb1 | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
13af7a6e | 3 | * Copyright (C) 2009 - QLogic Corporation. |
3d396eb1 | 4 | * All rights reserved. |
80922fbc | 5 | * |
3d396eb1 AK |
6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
cb8011ad | 10 | * |
3d396eb1 AK |
11 | * This program is distributed in the hope that it will be useful, but |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
cb8011ad | 15 | * |
3d396eb1 AK |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
19 | * MA 02111-1307, USA. | |
80922fbc | 20 | * |
3d396eb1 | 21 | * The full GNU General Public License is included in this distribution |
4d21fef4 | 22 | * in the file called "COPYING". |
80922fbc | 23 | * |
3d396eb1 AK |
24 | */ |
25 | ||
5a0e3ad6 | 26 | #include <linux/slab.h> |
3d396eb1 AK |
27 | #include "netxen_nic.h" |
28 | #include "netxen_nic_hw.h" | |
3d396eb1 | 29 | |
c9bdd4b5 ACM |
30 | #include <net/ip.h> |
31 | ||
3ce06a32 DP |
32 | #define MASK(n) ((1ULL<<(n))-1) |
33 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) | |
34 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) | |
6abb4b83 | 35 | #define OCM_WIN_P3P(addr) (addr & 0xffc0000) |
3ce06a32 DP |
36 | #define MS_WIN(addr) (addr & 0x0ffc0000) |
37 | ||
38 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) | |
39 | ||
40 | #define CRB_BLK(off) ((off >> 20) & 0x3f) | |
41 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) | |
42 | #define CRB_WINDOW_2M (0x130060) | |
43 | #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) | |
44 | #define CRB_INDIRECT_2M (0x1e0000UL) | |
45 | ||
f03b0ebd DP |
46 | static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, |
47 | void __iomem *addr, u32 data); | |
48 | static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, | |
49 | void __iomem *addr); | |
50 | ||
e98e3350 DP |
51 | #ifndef readq |
52 | static inline u64 readq(void __iomem *addr) | |
53 | { | |
54 | return readl(addr) | (((u64) readl(addr + 4)) << 32LL); | |
55 | } | |
56 | #endif | |
57 | ||
58 | #ifndef writeq | |
59 | static inline void writeq(u64 val, void __iomem *addr) | |
60 | { | |
61 | writel(((u32) (val)), (addr)); | |
62 | writel(((u32) (val >> 32)), (addr + 4)); | |
63 | } | |
64 | #endif | |
65 | ||
1fbe6323 DP |
66 | #define ADDR_IN_RANGE(addr, low, high) \ |
67 | (((addr) < (high)) && ((addr) >= (low))) | |
68 | ||
69 | #define PCI_OFFSET_FIRST_RANGE(adapter, off) \ | |
70 | ((adapter)->ahw.pci_base0 + (off)) | |
71 | #define PCI_OFFSET_SECOND_RANGE(adapter, off) \ | |
72 | ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) | |
73 | #define PCI_OFFSET_THIRD_RANGE(adapter, off) \ | |
74 | ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) | |
75 | ||
76 | static void __iomem *pci_base_offset(struct netxen_adapter *adapter, | |
77 | unsigned long off) | |
78 | { | |
79 | if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END)) | |
80 | return PCI_OFFSET_FIRST_RANGE(adapter, off); | |
81 | ||
82 | if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END)) | |
83 | return PCI_OFFSET_SECOND_RANGE(adapter, off); | |
84 | ||
85 | if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END)) | |
86 | return PCI_OFFSET_THIRD_RANGE(adapter, off); | |
87 | ||
88 | return NULL; | |
89 | } | |
90 | ||
ea7eaa39 DP |
91 | static crb_128M_2M_block_map_t |
92 | crb_128M_2M_map[64] __cacheline_aligned_in_smp = { | |
3ce06a32 DP |
93 | {{{0, 0, 0, 0} } }, /* 0: PCI */ |
94 | {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ | |
95 | {1, 0x0110000, 0x0120000, 0x130000}, | |
96 | {1, 0x0120000, 0x0122000, 0x124000}, | |
97 | {1, 0x0130000, 0x0132000, 0x126000}, | |
98 | {1, 0x0140000, 0x0142000, 0x128000}, | |
99 | {1, 0x0150000, 0x0152000, 0x12a000}, | |
100 | {1, 0x0160000, 0x0170000, 0x110000}, | |
101 | {1, 0x0170000, 0x0172000, 0x12e000}, | |
102 | {0, 0x0000000, 0x0000000, 0x000000}, | |
103 | {0, 0x0000000, 0x0000000, 0x000000}, | |
104 | {0, 0x0000000, 0x0000000, 0x000000}, | |
105 | {0, 0x0000000, 0x0000000, 0x000000}, | |
106 | {0, 0x0000000, 0x0000000, 0x000000}, | |
107 | {0, 0x0000000, 0x0000000, 0x000000}, | |
108 | {1, 0x01e0000, 0x01e0800, 0x122000}, | |
109 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
110 | {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ | |
111 | {{{0, 0, 0, 0} } }, /* 3: */ | |
112 | {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ | |
113 | {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ | |
114 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ | |
115 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ | |
116 | {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ | |
117 | {0, 0x0000000, 0x0000000, 0x000000}, | |
118 | {0, 0x0000000, 0x0000000, 0x000000}, | |
119 | {0, 0x0000000, 0x0000000, 0x000000}, | |
120 | {0, 0x0000000, 0x0000000, 0x000000}, | |
121 | {0, 0x0000000, 0x0000000, 0x000000}, | |
122 | {0, 0x0000000, 0x0000000, 0x000000}, | |
123 | {0, 0x0000000, 0x0000000, 0x000000}, | |
124 | {0, 0x0000000, 0x0000000, 0x000000}, | |
125 | {0, 0x0000000, 0x0000000, 0x000000}, | |
126 | {0, 0x0000000, 0x0000000, 0x000000}, | |
127 | {0, 0x0000000, 0x0000000, 0x000000}, | |
128 | {0, 0x0000000, 0x0000000, 0x000000}, | |
129 | {0, 0x0000000, 0x0000000, 0x000000}, | |
130 | {0, 0x0000000, 0x0000000, 0x000000}, | |
131 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, | |
132 | {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ | |
133 | {0, 0x0000000, 0x0000000, 0x000000}, | |
134 | {0, 0x0000000, 0x0000000, 0x000000}, | |
135 | {0, 0x0000000, 0x0000000, 0x000000}, | |
136 | {0, 0x0000000, 0x0000000, 0x000000}, | |
137 | {0, 0x0000000, 0x0000000, 0x000000}, | |
138 | {0, 0x0000000, 0x0000000, 0x000000}, | |
139 | {0, 0x0000000, 0x0000000, 0x000000}, | |
140 | {0, 0x0000000, 0x0000000, 0x000000}, | |
141 | {0, 0x0000000, 0x0000000, 0x000000}, | |
142 | {0, 0x0000000, 0x0000000, 0x000000}, | |
143 | {0, 0x0000000, 0x0000000, 0x000000}, | |
144 | {0, 0x0000000, 0x0000000, 0x000000}, | |
145 | {0, 0x0000000, 0x0000000, 0x000000}, | |
146 | {0, 0x0000000, 0x0000000, 0x000000}, | |
147 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, | |
148 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ | |
149 | {0, 0x0000000, 0x0000000, 0x000000}, | |
150 | {0, 0x0000000, 0x0000000, 0x000000}, | |
151 | {0, 0x0000000, 0x0000000, 0x000000}, | |
152 | {0, 0x0000000, 0x0000000, 0x000000}, | |
153 | {0, 0x0000000, 0x0000000, 0x000000}, | |
154 | {0, 0x0000000, 0x0000000, 0x000000}, | |
155 | {0, 0x0000000, 0x0000000, 0x000000}, | |
156 | {0, 0x0000000, 0x0000000, 0x000000}, | |
157 | {0, 0x0000000, 0x0000000, 0x000000}, | |
158 | {0, 0x0000000, 0x0000000, 0x000000}, | |
159 | {0, 0x0000000, 0x0000000, 0x000000}, | |
160 | {0, 0x0000000, 0x0000000, 0x000000}, | |
161 | {0, 0x0000000, 0x0000000, 0x000000}, | |
162 | {0, 0x0000000, 0x0000000, 0x000000}, | |
163 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, | |
164 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ | |
165 | {0, 0x0000000, 0x0000000, 0x000000}, | |
166 | {0, 0x0000000, 0x0000000, 0x000000}, | |
167 | {0, 0x0000000, 0x0000000, 0x000000}, | |
168 | {0, 0x0000000, 0x0000000, 0x000000}, | |
169 | {0, 0x0000000, 0x0000000, 0x000000}, | |
170 | {0, 0x0000000, 0x0000000, 0x000000}, | |
171 | {0, 0x0000000, 0x0000000, 0x000000}, | |
172 | {0, 0x0000000, 0x0000000, 0x000000}, | |
173 | {0, 0x0000000, 0x0000000, 0x000000}, | |
174 | {0, 0x0000000, 0x0000000, 0x000000}, | |
175 | {0, 0x0000000, 0x0000000, 0x000000}, | |
176 | {0, 0x0000000, 0x0000000, 0x000000}, | |
177 | {0, 0x0000000, 0x0000000, 0x000000}, | |
178 | {0, 0x0000000, 0x0000000, 0x000000}, | |
179 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, | |
180 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ | |
181 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ | |
182 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ | |
183 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ | |
184 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ | |
185 | {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ | |
186 | {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ | |
187 | {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ | |
188 | {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ | |
189 | {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ | |
190 | {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ | |
191 | {{{0, 0, 0, 0} } }, /* 23: */ | |
192 | {{{0, 0, 0, 0} } }, /* 24: */ | |
193 | {{{0, 0, 0, 0} } }, /* 25: */ | |
194 | {{{0, 0, 0, 0} } }, /* 26: */ | |
195 | {{{0, 0, 0, 0} } }, /* 27: */ | |
196 | {{{0, 0, 0, 0} } }, /* 28: */ | |
197 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ | |
198 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ | |
199 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ | |
200 | {{{0} } }, /* 32: PCI */ | |
201 | {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ | |
202 | {1, 0x2110000, 0x2120000, 0x130000}, | |
203 | {1, 0x2120000, 0x2122000, 0x124000}, | |
204 | {1, 0x2130000, 0x2132000, 0x126000}, | |
205 | {1, 0x2140000, 0x2142000, 0x128000}, | |
206 | {1, 0x2150000, 0x2152000, 0x12a000}, | |
207 | {1, 0x2160000, 0x2170000, 0x110000}, | |
208 | {1, 0x2170000, 0x2172000, 0x12e000}, | |
209 | {0, 0x0000000, 0x0000000, 0x000000}, | |
210 | {0, 0x0000000, 0x0000000, 0x000000}, | |
211 | {0, 0x0000000, 0x0000000, 0x000000}, | |
212 | {0, 0x0000000, 0x0000000, 0x000000}, | |
213 | {0, 0x0000000, 0x0000000, 0x000000}, | |
214 | {0, 0x0000000, 0x0000000, 0x000000}, | |
215 | {0, 0x0000000, 0x0000000, 0x000000}, | |
216 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
217 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ | |
218 | {{{0} } }, /* 35: */ | |
219 | {{{0} } }, /* 36: */ | |
220 | {{{0} } }, /* 37: */ | |
221 | {{{0} } }, /* 38: */ | |
222 | {{{0} } }, /* 39: */ | |
223 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ | |
224 | {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ | |
225 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ | |
226 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ | |
227 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ | |
228 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ | |
229 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ | |
230 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ | |
231 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ | |
232 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ | |
233 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ | |
234 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ | |
235 | {{{0} } }, /* 52: */ | |
236 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ | |
237 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ | |
238 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ | |
239 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ | |
240 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ | |
241 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ | |
242 | {{{0} } }, /* 59: I2C0 */ | |
243 | {{{0} } }, /* 60: I2C1 */ | |
244 | {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ | |
245 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ | |
246 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ | |
247 | }; | |
248 | ||
249 | /* | |
250 | * top 12 bits of crb internal address (hub, agent) | |
251 | */ | |
252 | static unsigned crb_hub_agt[64] = | |
253 | { | |
254 | 0, | |
255 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, | |
256 | NETXEN_HW_CRB_HUB_AGT_ADR_MN, | |
257 | NETXEN_HW_CRB_HUB_AGT_ADR_MS, | |
258 | 0, | |
259 | NETXEN_HW_CRB_HUB_AGT_ADR_SRE, | |
260 | NETXEN_HW_CRB_HUB_AGT_ADR_NIU, | |
261 | NETXEN_HW_CRB_HUB_AGT_ADR_QMN, | |
262 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN0, | |
263 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN1, | |
264 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN2, | |
265 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN3, | |
266 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, | |
267 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, | |
268 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
269 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN4, | |
270 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, | |
271 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN0, | |
272 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN1, | |
273 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN2, | |
274 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN3, | |
275 | NETXEN_HW_CRB_HUB_AGT_ADR_PGND, | |
276 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNI, | |
277 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS0, | |
278 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS1, | |
279 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS2, | |
280 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS3, | |
281 | 0, | |
282 | NETXEN_HW_CRB_HUB_AGT_ADR_PGSI, | |
283 | NETXEN_HW_CRB_HUB_AGT_ADR_SN, | |
284 | 0, | |
285 | NETXEN_HW_CRB_HUB_AGT_ADR_EG, | |
286 | 0, | |
287 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, | |
288 | NETXEN_HW_CRB_HUB_AGT_ADR_CAM, | |
289 | 0, | |
290 | 0, | |
291 | 0, | |
292 | 0, | |
293 | 0, | |
294 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, | |
295 | 0, | |
296 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1, | |
297 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2, | |
298 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3, | |
299 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4, | |
300 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5, | |
301 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6, | |
302 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7, | |
303 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, | |
304 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, | |
305 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
306 | 0, | |
307 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0, | |
308 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8, | |
309 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9, | |
310 | NETXEN_HW_CRB_HUB_AGT_ADR_OCM0, | |
311 | 0, | |
312 | NETXEN_HW_CRB_HUB_AGT_ADR_SMB, | |
313 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C0, | |
314 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C1, | |
315 | 0, | |
316 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNC, | |
317 | 0, | |
318 | }; | |
319 | ||
3d396eb1 AK |
320 | /* PCI Windowing for DDR regions. */ |
321 | ||
3ce06a32 | 322 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ |
3d396eb1 | 323 | |
c9517e58 DP |
324 | #define NETXEN_PCIE_SEM_TIMEOUT 10000 |
325 | ||
326 | int | |
327 | netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg) | |
328 | { | |
329 | int done = 0, timeout = 0; | |
330 | ||
331 | while (!done) { | |
332 | done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem))); | |
333 | if (done == 1) | |
334 | break; | |
335 | if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT) | |
7cecdca1 | 336 | return -EIO; |
c9517e58 DP |
337 | msleep(1); |
338 | } | |
339 | ||
340 | if (id_reg) | |
341 | NXWR32(adapter, id_reg, adapter->portnum); | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | void | |
347 | netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem) | |
348 | { | |
581e8ae4 | 349 | NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem))); |
c9517e58 DP |
350 | } |
351 | ||
3ad4467c DP |
352 | int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port) |
353 | { | |
354 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
355 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447); | |
356 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5); | |
357 | } | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | /* Disable an XG interface */ | |
363 | int netxen_niu_disable_xg_port(struct netxen_adapter *adapter) | |
364 | { | |
365 | __u32 mac_cfg; | |
366 | u32 port = adapter->physical_port; | |
367 | ||
368 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | |
369 | return 0; | |
370 | ||
371 | if (port > NETXEN_NIU_MAX_XG_PORTS) | |
372 | return -EINVAL; | |
373 | ||
374 | mac_cfg = 0; | |
375 | if (NXWR32(adapter, | |
376 | NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg)) | |
377 | return -EIO; | |
378 | return 0; | |
379 | } | |
380 | ||
623621b0 DP |
381 | #define NETXEN_UNICAST_ADDR(port, index) \ |
382 | (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8)) | |
383 | #define NETXEN_MCAST_ADDR(port, index) \ | |
384 | (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8)) | |
385 | #define MAC_HI(addr) \ | |
386 | ((addr[2] << 16) | (addr[1] << 8) | (addr[0])) | |
387 | #define MAC_LO(addr) \ | |
388 | ((addr[5] << 16) | (addr[4] << 8) | (addr[3])) | |
389 | ||
3ad4467c DP |
390 | int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) |
391 | { | |
a7483b0a NK |
392 | u32 mac_cfg; |
393 | u32 cnt = 0; | |
394 | __u32 reg = 0x0200; | |
3ad4467c | 395 | u32 port = adapter->physical_port; |
a7483b0a | 396 | u16 board_type = adapter->ahw.board_type; |
3ad4467c DP |
397 | |
398 | if (port > NETXEN_NIU_MAX_XG_PORTS) | |
399 | return -EINVAL; | |
400 | ||
a7483b0a NK |
401 | mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port)); |
402 | mac_cfg &= ~0x4; | |
403 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); | |
3ad4467c | 404 | |
a7483b0a NK |
405 | if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) || |
406 | (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ)) | |
407 | reg = (0x20 << port); | |
3ad4467c | 408 | |
a7483b0a NK |
409 | NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg); |
410 | ||
411 | mdelay(10); | |
412 | ||
413 | while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20) | |
414 | mdelay(10); | |
415 | ||
416 | if (cnt < 20) { | |
417 | ||
418 | reg = NXRD32(adapter, | |
419 | NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port)); | |
420 | ||
421 | if (mode == NETXEN_NIU_PROMISC_MODE) | |
422 | reg = (reg | 0x2000UL); | |
423 | else | |
424 | reg = (reg & ~0x2000UL); | |
425 | ||
426 | if (mode == NETXEN_NIU_ALLMULTI_MODE) | |
427 | reg = (reg | 0x1000UL); | |
428 | else | |
429 | reg = (reg & ~0x1000UL); | |
430 | ||
431 | NXWR32(adapter, | |
432 | NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg); | |
433 | } | |
434 | ||
435 | mac_cfg |= 0x4; | |
436 | NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); | |
3ad4467c DP |
437 | |
438 | return 0; | |
439 | } | |
440 | ||
441 | int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) | |
442 | { | |
443 | u32 mac_hi, mac_lo; | |
444 | u32 reg_hi, reg_lo; | |
445 | ||
446 | u8 phy = adapter->physical_port; | |
447 | ||
448 | if (phy >= NETXEN_NIU_MAX_XG_PORTS) | |
449 | return -EINVAL; | |
450 | ||
451 | mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24); | |
452 | mac_hi = addr[2] | ((u32)addr[3] << 8) | | |
453 | ((u32)addr[4] << 16) | ((u32)addr[5] << 24); | |
454 | ||
455 | reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy); | |
456 | reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy); | |
457 | ||
458 | /* write twice to flush */ | |
459 | if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) | |
460 | return -EIO; | |
461 | if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) | |
462 | return -EIO; | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
623621b0 DP |
467 | static int |
468 | netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter) | |
469 | { | |
470 | u32 val = 0; | |
471 | u16 port = adapter->physical_port; | |
5d09e534 | 472 | u8 *addr = adapter->mac_addr; |
623621b0 DP |
473 | |
474 | if (adapter->mc_enabled) | |
475 | return 0; | |
476 | ||
f98a9f69 | 477 | val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); |
623621b0 | 478 | val |= (1UL << (28+port)); |
f98a9f69 | 479 | NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); |
623621b0 DP |
480 | |
481 | /* add broadcast addr to filter */ | |
482 | val = 0xffffff; | |
f98a9f69 DP |
483 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
484 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); | |
623621b0 DP |
485 | |
486 | /* add station addr to filter */ | |
487 | val = MAC_HI(addr); | |
f98a9f69 | 488 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val); |
623621b0 | 489 | val = MAC_LO(addr); |
f98a9f69 | 490 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val); |
623621b0 DP |
491 | |
492 | adapter->mc_enabled = 1; | |
493 | return 0; | |
494 | } | |
495 | ||
496 | static int | |
497 | netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter) | |
498 | { | |
499 | u32 val = 0; | |
500 | u16 port = adapter->physical_port; | |
5d09e534 | 501 | u8 *addr = adapter->mac_addr; |
623621b0 DP |
502 | |
503 | if (!adapter->mc_enabled) | |
504 | return 0; | |
505 | ||
f98a9f69 | 506 | val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); |
623621b0 | 507 | val &= ~(1UL << (28+port)); |
f98a9f69 | 508 | NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); |
623621b0 DP |
509 | |
510 | val = MAC_HI(addr); | |
f98a9f69 | 511 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
623621b0 | 512 | val = MAC_LO(addr); |
f98a9f69 | 513 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); |
623621b0 | 514 | |
f98a9f69 DP |
515 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); |
516 | NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); | |
623621b0 DP |
517 | |
518 | adapter->mc_enabled = 0; | |
519 | return 0; | |
520 | } | |
521 | ||
522 | static int | |
523 | netxen_nic_set_mcast_addr(struct netxen_adapter *adapter, | |
524 | int index, u8 *addr) | |
525 | { | |
526 | u32 hi = 0, lo = 0; | |
527 | u16 port = adapter->physical_port; | |
528 | ||
529 | lo = MAC_LO(addr); | |
530 | hi = MAC_HI(addr); | |
531 | ||
f98a9f69 DP |
532 | NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi); |
533 | NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo); | |
623621b0 DP |
534 | |
535 | return 0; | |
536 | } | |
537 | ||
c9fc891f | 538 | void netxen_p2_nic_set_multi(struct net_device *netdev) |
3d396eb1 | 539 | { |
3176ff3e | 540 | struct netxen_adapter *adapter = netdev_priv(netdev); |
3d396eb1 | 541 | struct dev_mc_list *mc_ptr; |
623621b0 | 542 | u8 null_addr[6]; |
f9dcbcc9 | 543 | int i; |
623621b0 DP |
544 | |
545 | memset(null_addr, 0, 6); | |
3d396eb1 | 546 | |
3d396eb1 | 547 | if (netdev->flags & IFF_PROMISC) { |
623621b0 DP |
548 | |
549 | adapter->set_promisc(adapter, | |
550 | NETXEN_NIU_PROMISC_MODE); | |
551 | ||
552 | /* Full promiscuous mode */ | |
553 | netxen_nic_disable_mcast_filter(adapter); | |
554 | ||
555 | return; | |
556 | } | |
557 | ||
4cd24eaf | 558 | if (netdev_mc_empty(netdev)) { |
623621b0 DP |
559 | adapter->set_promisc(adapter, |
560 | NETXEN_NIU_NON_PROMISC_MODE); | |
561 | netxen_nic_disable_mcast_filter(adapter); | |
562 | return; | |
563 | } | |
564 | ||
565 | adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE); | |
566 | if (netdev->flags & IFF_ALLMULTI || | |
4cd24eaf | 567 | netdev_mc_count(netdev) > adapter->max_mc_count) { |
623621b0 DP |
568 | netxen_nic_disable_mcast_filter(adapter); |
569 | return; | |
3d396eb1 | 570 | } |
623621b0 DP |
571 | |
572 | netxen_nic_enable_mcast_filter(adapter); | |
573 | ||
f9dcbcc9 JP |
574 | i = 0; |
575 | netdev_for_each_mc_addr(mc_ptr, netdev) | |
576 | netxen_nic_set_mcast_addr(adapter, i++, mc_ptr->dmi_addr); | |
623621b0 DP |
577 | |
578 | /* Clear out remaining addresses */ | |
f9dcbcc9 JP |
579 | while (i < adapter->max_mc_count) |
580 | netxen_nic_set_mcast_addr(adapter, i++, null_addr); | |
3d396eb1 AK |
581 | } |
582 | ||
c9fc891f DP |
583 | static int |
584 | netxen_send_cmd_descs(struct netxen_adapter *adapter, | |
d877f1e3 | 585 | struct cmd_desc_type0 *cmd_desc_arr, int nr_desc) |
c9fc891f | 586 | { |
d877f1e3 | 587 | u32 i, producer, consumer; |
c9fc891f DP |
588 | struct netxen_cmd_buffer *pbuf; |
589 | struct cmd_desc_type0 *cmd_desc; | |
d877f1e3 | 590 | struct nx_host_tx_ring *tx_ring; |
c9fc891f DP |
591 | |
592 | i = 0; | |
593 | ||
db4cfd8a DP |
594 | if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) |
595 | return -EIO; | |
596 | ||
4ea528a1 | 597 | tx_ring = adapter->tx_ring; |
b2af9cb0 | 598 | __netif_tx_lock_bh(tx_ring->txq); |
03e678ee | 599 | |
d877f1e3 DP |
600 | producer = tx_ring->producer; |
601 | consumer = tx_ring->sw_consumer; | |
602 | ||
b2af9cb0 DP |
603 | if (nr_desc >= netxen_tx_avail(tx_ring)) { |
604 | netif_tx_stop_queue(tx_ring->txq); | |
605 | __netif_tx_unlock_bh(tx_ring->txq); | |
d877f1e3 DP |
606 | return -EBUSY; |
607 | } | |
608 | ||
c9fc891f DP |
609 | do { |
610 | cmd_desc = &cmd_desc_arr[i]; | |
611 | ||
d877f1e3 | 612 | pbuf = &tx_ring->cmd_buf_arr[producer]; |
c9fc891f | 613 | pbuf->skb = NULL; |
c9fc891f | 614 | pbuf->frag_count = 0; |
c9fc891f | 615 | |
d877f1e3 | 616 | memcpy(&tx_ring->desc_head[producer], |
c9fc891f DP |
617 | &cmd_desc_arr[i], sizeof(struct cmd_desc_type0)); |
618 | ||
d877f1e3 | 619 | producer = get_next_index(producer, tx_ring->num_desc); |
c9fc891f DP |
620 | i++; |
621 | ||
d877f1e3 | 622 | } while (i != nr_desc); |
c9fc891f | 623 | |
d877f1e3 | 624 | tx_ring->producer = producer; |
c9fc891f | 625 | |
cb2107be | 626 | netxen_nic_update_cmd_producer(adapter, tx_ring); |
c9fc891f | 627 | |
b2af9cb0 | 628 | __netif_tx_unlock_bh(tx_ring->txq); |
03e678ee | 629 | |
c9fc891f DP |
630 | return 0; |
631 | } | |
632 | ||
5cf4d323 DP |
633 | static int |
634 | nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op) | |
c9fc891f | 635 | { |
c9fc891f | 636 | nx_nic_req_t req; |
2edbb454 DP |
637 | nx_mac_req_t *mac_req; |
638 | u64 word; | |
c9fc891f DP |
639 | |
640 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
2edbb454 DP |
641 | req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23); |
642 | ||
643 | word = NX_MAC_EVENT | ((u64)adapter->portnum << 16); | |
644 | req.req_hdr = cpu_to_le64(word); | |
645 | ||
646 | mac_req = (nx_mac_req_t *)&req.words[0]; | |
647 | mac_req->op = op; | |
648 | memcpy(mac_req->mac_addr, addr, 6); | |
c9fc891f | 649 | |
5cf4d323 DP |
650 | return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); |
651 | } | |
652 | ||
653 | static int nx_p3_nic_add_mac(struct netxen_adapter *adapter, | |
654 | u8 *addr, struct list_head *del_list) | |
655 | { | |
656 | struct list_head *head; | |
657 | nx_mac_list_t *cur; | |
658 | ||
659 | /* look up if already exists */ | |
660 | list_for_each(head, del_list) { | |
661 | cur = list_entry(head, nx_mac_list_t, list); | |
662 | ||
663 | if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) { | |
664 | list_move_tail(head, &adapter->mac_list); | |
665 | return 0; | |
666 | } | |
c9fc891f DP |
667 | } |
668 | ||
5cf4d323 DP |
669 | cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC); |
670 | if (cur == NULL) { | |
671 | printk(KERN_ERR "%s: failed to add mac address filter\n", | |
672 | adapter->netdev->name); | |
673 | return -ENOMEM; | |
674 | } | |
675 | memcpy(cur->mac_addr, addr, ETH_ALEN); | |
676 | list_add_tail(&cur->list, &adapter->mac_list); | |
677 | return nx_p3_sre_macaddr_change(adapter, | |
678 | cur->mac_addr, NETXEN_MAC_ADD); | |
c9fc891f DP |
679 | } |
680 | ||
681 | void netxen_p3_nic_set_multi(struct net_device *netdev) | |
682 | { | |
683 | struct netxen_adapter *adapter = netdev_priv(netdev); | |
c9fc891f DP |
684 | struct dev_mc_list *mc_ptr; |
685 | u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | |
9ad27643 | 686 | u32 mode = VPORT_MISS_MODE_DROP; |
5cf4d323 DP |
687 | LIST_HEAD(del_list); |
688 | struct list_head *head; | |
689 | nx_mac_list_t *cur; | |
c9fc891f | 690 | |
d49c9640 AKS |
691 | if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) |
692 | return; | |
693 | ||
5cf4d323 | 694 | list_splice_tail_init(&adapter->mac_list, &del_list); |
c9fc891f | 695 | |
5d09e534 | 696 | nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list); |
5cf4d323 | 697 | nx_p3_nic_add_mac(adapter, bcast_addr, &del_list); |
9ad27643 DP |
698 | |
699 | if (netdev->flags & IFF_PROMISC) { | |
700 | mode = VPORT_MISS_MODE_ACCEPT_ALL; | |
701 | goto send_fw_cmd; | |
702 | } | |
703 | ||
704 | if ((netdev->flags & IFF_ALLMULTI) || | |
4cd24eaf | 705 | (netdev_mc_count(netdev) > adapter->max_mc_count)) { |
9ad27643 DP |
706 | mode = VPORT_MISS_MODE_ACCEPT_MULTI; |
707 | goto send_fw_cmd; | |
708 | } | |
709 | ||
4cd24eaf | 710 | if (!netdev_mc_empty(netdev)) { |
f9dcbcc9 | 711 | netdev_for_each_mc_addr(mc_ptr, netdev) |
5cf4d323 | 712 | nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list); |
c9fc891f | 713 | } |
9ad27643 DP |
714 | |
715 | send_fw_cmd: | |
716 | adapter->set_promisc(adapter, mode); | |
5cf4d323 DP |
717 | head = &del_list; |
718 | while (!list_empty(head)) { | |
719 | cur = list_entry(head->next, nx_mac_list_t, list); | |
720 | ||
721 | nx_p3_sre_macaddr_change(adapter, | |
722 | cur->mac_addr, NETXEN_MAC_DEL); | |
723 | list_del(&cur->list); | |
c9fc891f | 724 | kfree(cur); |
c9fc891f DP |
725 | } |
726 | } | |
727 | ||
9ad27643 DP |
728 | int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) |
729 | { | |
730 | nx_nic_req_t req; | |
2edbb454 | 731 | u64 word; |
9ad27643 DP |
732 | |
733 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
734 | ||
2edbb454 DP |
735 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); |
736 | ||
737 | word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE | | |
738 | ((u64)adapter->portnum << 16); | |
739 | req.req_hdr = cpu_to_le64(word); | |
740 | ||
9ad27643 DP |
741 | req.words[0] = cpu_to_le64(mode); |
742 | ||
743 | return netxen_send_cmd_descs(adapter, | |
744 | (struct cmd_desc_type0 *)&req, 1); | |
745 | } | |
746 | ||
06e9d9f9 DP |
747 | void netxen_p3_free_mac_list(struct netxen_adapter *adapter) |
748 | { | |
5cf4d323 DP |
749 | nx_mac_list_t *cur; |
750 | struct list_head *head = &adapter->mac_list; | |
751 | ||
752 | while (!list_empty(head)) { | |
753 | cur = list_entry(head->next, nx_mac_list_t, list); | |
754 | nx_p3_sre_macaddr_change(adapter, | |
755 | cur->mac_addr, NETXEN_MAC_DEL); | |
756 | list_del(&cur->list); | |
06e9d9f9 | 757 | kfree(cur); |
06e9d9f9 DP |
758 | } |
759 | } | |
760 | ||
3d0a3cc9 DP |
761 | int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) |
762 | { | |
763 | /* assuming caller has already copied new addr to netdev */ | |
764 | netxen_p3_nic_set_multi(adapter->netdev); | |
765 | return 0; | |
766 | } | |
767 | ||
cd1f8160 DP |
768 | #define NETXEN_CONFIG_INTR_COALESCE 3 |
769 | ||
770 | /* | |
771 | * Send the interrupt coalescing parameter set by ethtool to the card. | |
772 | */ | |
773 | int netxen_config_intr_coalesce(struct netxen_adapter *adapter) | |
774 | { | |
775 | nx_nic_req_t req; | |
c0703950 AKS |
776 | u64 word[6]; |
777 | int rv, i; | |
cd1f8160 DP |
778 | |
779 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
c0703950 | 780 | memset(word, 0, sizeof(word)); |
cd1f8160 | 781 | |
1bb482f8 | 782 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); |
2edbb454 | 783 | |
c0703950 AKS |
784 | word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16); |
785 | req.req_hdr = cpu_to_le64(word[0]); | |
cd1f8160 | 786 | |
c0703950 AKS |
787 | memcpy(&word[0], &adapter->coal, sizeof(adapter->coal)); |
788 | for (i = 0; i < 6; i++) | |
789 | req.words[i] = cpu_to_le64(word[i]); | |
cd1f8160 DP |
790 | |
791 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
792 | if (rv != 0) { | |
793 | printk(KERN_ERR "ERROR. Could not send " | |
794 | "interrupt coalescing parameters\n"); | |
795 | } | |
796 | ||
797 | return rv; | |
798 | } | |
799 | ||
1bb482f8 NK |
800 | int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable) |
801 | { | |
802 | nx_nic_req_t req; | |
803 | u64 word; | |
804 | int rv = 0; | |
805 | ||
806 | if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable) | |
807 | return 0; | |
808 | ||
809 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
810 | ||
811 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
812 | ||
813 | word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16); | |
814 | req.req_hdr = cpu_to_le64(word); | |
815 | ||
816 | req.words[0] = cpu_to_le64(enable); | |
817 | ||
818 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
819 | if (rv != 0) { | |
820 | printk(KERN_ERR "ERROR. Could not send " | |
821 | "configure hw lro request\n"); | |
822 | } | |
823 | ||
824 | adapter->flags ^= NETXEN_NIC_LRO_ENABLED; | |
825 | ||
826 | return rv; | |
827 | } | |
828 | ||
fa3ce355 NK |
829 | int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable) |
830 | { | |
831 | nx_nic_req_t req; | |
832 | u64 word; | |
833 | int rv = 0; | |
834 | ||
835 | if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable) | |
836 | return rv; | |
837 | ||
838 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
839 | ||
840 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
841 | ||
842 | word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING | | |
843 | ((u64)adapter->portnum << 16); | |
844 | req.req_hdr = cpu_to_le64(word); | |
845 | ||
846 | req.words[0] = cpu_to_le64(enable); | |
847 | ||
848 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
849 | if (rv != 0) { | |
850 | printk(KERN_ERR "ERROR. Could not send " | |
851 | "configure bridge mode request\n"); | |
852 | } | |
853 | ||
854 | adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED; | |
855 | ||
856 | return rv; | |
857 | } | |
858 | ||
859 | ||
d8b100c5 DP |
860 | #define RSS_HASHTYPE_IP_TCP 0x3 |
861 | ||
862 | int netxen_config_rss(struct netxen_adapter *adapter, int enable) | |
863 | { | |
864 | nx_nic_req_t req; | |
865 | u64 word; | |
866 | int i, rv; | |
867 | ||
868 | u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, | |
869 | 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, | |
870 | 0x255b0ec26d5a56daULL }; | |
871 | ||
872 | ||
873 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
874 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
875 | ||
876 | word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16); | |
877 | req.req_hdr = cpu_to_le64(word); | |
878 | ||
879 | /* | |
880 | * RSS request: | |
881 | * bits 3-0: hash_method | |
882 | * 5-4: hash_type_ipv4 | |
883 | * 7-6: hash_type_ipv6 | |
884 | * 8: enable | |
885 | * 9: use indirection table | |
886 | * 47-10: reserved | |
887 | * 63-48: indirection table mask | |
888 | */ | |
889 | word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | | |
890 | ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | | |
891 | ((u64)(enable & 0x1) << 8) | | |
892 | ((0x7ULL) << 48); | |
893 | req.words[0] = cpu_to_le64(word); | |
894 | for (i = 0; i < 5; i++) | |
895 | req.words[i+1] = cpu_to_le64(key[i]); | |
896 | ||
897 | ||
898 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
899 | if (rv != 0) { | |
900 | printk(KERN_ERR "%s: could not configure RSS\n", | |
901 | adapter->netdev->name); | |
902 | } | |
903 | ||
904 | return rv; | |
905 | } | |
906 | ||
6598b169 DP |
907 | int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd) |
908 | { | |
909 | nx_nic_req_t req; | |
910 | u64 word; | |
911 | int rv; | |
912 | ||
913 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
914 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
915 | ||
916 | word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16); | |
917 | req.req_hdr = cpu_to_le64(word); | |
918 | ||
919 | req.words[0] = cpu_to_le64(cmd); | |
920 | req.words[1] = cpu_to_le64(ip); | |
921 | ||
922 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
923 | if (rv != 0) { | |
924 | printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n", | |
925 | adapter->netdev->name, | |
926 | (cmd == NX_IP_UP) ? "Add" : "Remove", ip); | |
927 | } | |
928 | return rv; | |
929 | } | |
930 | ||
3bf26ce3 DP |
931 | int netxen_linkevent_request(struct netxen_adapter *adapter, int enable) |
932 | { | |
933 | nx_nic_req_t req; | |
934 | u64 word; | |
935 | int rv; | |
936 | ||
937 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
938 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
939 | ||
940 | word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16); | |
941 | req.req_hdr = cpu_to_le64(word); | |
22527864 | 942 | req.words[0] = cpu_to_le64(enable | (enable << 8)); |
3bf26ce3 DP |
943 | |
944 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
945 | if (rv != 0) { | |
946 | printk(KERN_ERR "%s: could not configure link notification\n", | |
947 | adapter->netdev->name); | |
948 | } | |
949 | ||
950 | return rv; | |
951 | } | |
952 | ||
1bb482f8 NK |
953 | int netxen_send_lro_cleanup(struct netxen_adapter *adapter) |
954 | { | |
955 | nx_nic_req_t req; | |
956 | u64 word; | |
957 | int rv; | |
958 | ||
959 | memset(&req, 0, sizeof(nx_nic_req_t)); | |
960 | req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); | |
961 | ||
962 | word = NX_NIC_H2C_OPCODE_LRO_REQUEST | | |
963 | ((u64)adapter->portnum << 16) | | |
964 | ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ; | |
965 | ||
966 | req.req_hdr = cpu_to_le64(word); | |
967 | ||
968 | rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); | |
969 | if (rv != 0) { | |
970 | printk(KERN_ERR "%s: could not cleanup lro flows\n", | |
971 | adapter->netdev->name); | |
972 | } | |
973 | return rv; | |
974 | } | |
975 | ||
3d396eb1 AK |
976 | /* |
977 | * netxen_nic_change_mtu - Change the Maximum Transfer Unit | |
978 | * @returns 0 on success, negative on failure | |
979 | */ | |
c9fc891f DP |
980 | |
981 | #define MTU_FUDGE_FACTOR 100 | |
982 | ||
3d396eb1 AK |
983 | int netxen_nic_change_mtu(struct net_device *netdev, int mtu) |
984 | { | |
3176ff3e | 985 | struct netxen_adapter *adapter = netdev_priv(netdev); |
c9fc891f | 986 | int max_mtu; |
9ad27643 | 987 | int rc = 0; |
3d396eb1 | 988 | |
c9fc891f DP |
989 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
990 | max_mtu = P3_MAX_MTU; | |
991 | else | |
992 | max_mtu = P2_MAX_MTU; | |
993 | ||
994 | if (mtu > max_mtu) { | |
995 | printk(KERN_ERR "%s: mtu > %d bytes unsupported\n", | |
996 | netdev->name, max_mtu); | |
3d396eb1 AK |
997 | return -EINVAL; |
998 | } | |
999 | ||
80922fbc | 1000 | if (adapter->set_mtu) |
9ad27643 | 1001 | rc = adapter->set_mtu(adapter, mtu); |
3d396eb1 | 1002 | |
9ad27643 DP |
1003 | if (!rc) |
1004 | netdev->mtu = mtu; | |
c9fc891f | 1005 | |
9ad27643 | 1006 | return rc; |
3d396eb1 AK |
1007 | } |
1008 | ||
3d396eb1 | 1009 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, |
f305f789 | 1010 | int size, __le32 * buf) |
3d396eb1 | 1011 | { |
1e2d0059 | 1012 | int i, v, addr; |
f305f789 | 1013 | __le32 *ptr32; |
3d396eb1 AK |
1014 | |
1015 | addr = base; | |
1016 | ptr32 = buf; | |
1017 | for (i = 0; i < size / sizeof(u32); i++) { | |
f305f789 | 1018 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) |
3d396eb1 | 1019 | return -1; |
f305f789 | 1020 | *ptr32 = cpu_to_le32(v); |
3d396eb1 AK |
1021 | ptr32++; |
1022 | addr += sizeof(u32); | |
1023 | } | |
1024 | if ((char *)buf + size > (char *)ptr32) { | |
f305f789 AV |
1025 | __le32 local; |
1026 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) | |
3d396eb1 | 1027 | return -1; |
f305f789 | 1028 | local = cpu_to_le32(v); |
3d396eb1 AK |
1029 | memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); |
1030 | } | |
1031 | ||
1032 | return 0; | |
1033 | } | |
1034 | ||
a03d2451 | 1035 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac) |
3d396eb1 | 1036 | { |
9dc28efe DP |
1037 | __le32 *pmac = (__le32 *) mac; |
1038 | u32 offset; | |
3d396eb1 | 1039 | |
06db58c0 | 1040 | offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64)); |
9dc28efe DP |
1041 | |
1042 | if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1) | |
3d396eb1 | 1043 | return -1; |
9dc28efe | 1044 | |
f305f789 | 1045 | if (*mac == cpu_to_le64(~0ULL)) { |
9dc28efe | 1046 | |
06db58c0 DP |
1047 | offset = NX_OLD_MAC_ADDR_OFFSET + |
1048 | (adapter->portnum * sizeof(u64)); | |
9dc28efe | 1049 | |
3d396eb1 | 1050 | if (netxen_get_flash_block(adapter, |
9dc28efe | 1051 | offset, sizeof(u64), pmac) == -1) |
3d396eb1 | 1052 | return -1; |
9dc28efe | 1053 | |
f305f789 | 1054 | if (*mac == cpu_to_le64(~0ULL)) |
3d396eb1 AK |
1055 | return -1; |
1056 | } | |
1057 | return 0; | |
1058 | } | |
1059 | ||
a03d2451 | 1060 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac) |
9dc28efe DP |
1061 | { |
1062 | uint32_t crbaddr, mac_hi, mac_lo; | |
1063 | int pci_func = adapter->ahw.pci_func; | |
1064 | ||
1065 | crbaddr = CRB_MAC_BLOCK_START + | |
1066 | (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); | |
1067 | ||
f98a9f69 DP |
1068 | mac_lo = NXRD32(adapter, crbaddr); |
1069 | mac_hi = NXRD32(adapter, crbaddr+4); | |
9dc28efe | 1070 | |
9dc28efe | 1071 | if (pci_func & 1) |
2edbb454 | 1072 | *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16)); |
9dc28efe | 1073 | else |
2edbb454 | 1074 | *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32)); |
9dc28efe DP |
1075 | |
1076 | return 0; | |
1077 | } | |
1078 | ||
3d396eb1 AK |
1079 | /* |
1080 | * Changes the CRB window to the specified window. | |
1081 | */ | |
195c5f98 | 1082 | static void |
907fa120 DP |
1083 | netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter, |
1084 | u32 window) | |
3d396eb1 AK |
1085 | { |
1086 | void __iomem *offset; | |
907fa120 DP |
1087 | int count = 10; |
1088 | u8 func = adapter->ahw.pci_func; | |
3d396eb1 | 1089 | |
907fa120 | 1090 | if (adapter->ahw.crb_win == window) |
3d396eb1 | 1091 | return; |
907fa120 | 1092 | |
e4c93c81 DP |
1093 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
1094 | NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func))); | |
3d396eb1 | 1095 | |
907fa120 DP |
1096 | writel(window, offset); |
1097 | do { | |
1098 | if (window == readl(offset)) | |
1099 | break; | |
3d396eb1 | 1100 | |
907fa120 DP |
1101 | if (printk_ratelimit()) |
1102 | dev_warn(&adapter->pdev->dev, | |
1103 | "failed to set CRB window to %d\n", | |
1104 | (window == NETXEN_WINDOW_ONE)); | |
1105 | udelay(1); | |
3d396eb1 | 1106 | |
907fa120 | 1107 | } while (--count > 0); |
3d396eb1 | 1108 | |
907fa120 DP |
1109 | if (count > 0) |
1110 | adapter->ahw.crb_win = window; | |
3d396eb1 AK |
1111 | } |
1112 | ||
3ce06a32 | 1113 | /* |
7cecdca1 | 1114 | * Returns < 0 if off is not valid, |
3ce06a32 DP |
1115 | * 1 if window access is needed. 'off' is set to offset from |
1116 | * CRB space in 128M pci map | |
1117 | * 0 if no window access is needed. 'off' is set to 2M addr | |
1118 | * In: 'off' is offset from base in 128M pci map | |
1119 | */ | |
1120 | static int | |
a9ac07de DP |
1121 | netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, |
1122 | ulong off, void __iomem **addr) | |
3ce06a32 | 1123 | { |
3ce06a32 DP |
1124 | crb_128M_2M_sub_block_map_t *m; |
1125 | ||
1126 | ||
a9ac07de | 1127 | if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE)) |
7cecdca1 | 1128 | return -EINVAL; |
3ce06a32 | 1129 | |
a9ac07de | 1130 | off -= NETXEN_PCI_CRBSPACE; |
3ce06a32 DP |
1131 | |
1132 | /* | |
1133 | * Try direct map | |
1134 | */ | |
a9ac07de | 1135 | m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)]; |
3ce06a32 | 1136 | |
a9ac07de DP |
1137 | if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) { |
1138 | *addr = adapter->ahw.pci_base0 + m->start_2M + | |
1139 | (off - m->start_128M); | |
3ce06a32 DP |
1140 | return 0; |
1141 | } | |
1142 | ||
1143 | /* | |
1144 | * Not in direct map, use crb window | |
1145 | */ | |
a9ac07de DP |
1146 | *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + |
1147 | (off & MASK(16)); | |
3ce06a32 DP |
1148 | return 1; |
1149 | } | |
1150 | ||
1151 | /* | |
1152 | * In: 'off' is offset from CRB space in 128M pci map | |
1153 | * Out: 'off' is 2M pci map addr | |
1154 | * side effect: lock crb window | |
1155 | */ | |
1156 | static void | |
a9ac07de | 1157 | netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off) |
3ce06a32 | 1158 | { |
907fa120 DP |
1159 | u32 window; |
1160 | void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M; | |
3ce06a32 | 1161 | |
a9ac07de DP |
1162 | off -= NETXEN_PCI_CRBSPACE; |
1163 | ||
1164 | window = CRB_HI(off); | |
907fa120 DP |
1165 | |
1166 | if (adapter->ahw.crb_win == window) | |
a9ac07de | 1167 | return; |
907fa120 DP |
1168 | |
1169 | writel(window, addr); | |
1170 | if (readl(addr) != window) { | |
1171 | if (printk_ratelimit()) | |
1172 | dev_warn(&adapter->pdev->dev, | |
1173 | "failed to set CRB window to %d off 0x%lx\n", | |
a9ac07de | 1174 | window, off); |
3ce06a32 | 1175 | } |
907fa120 | 1176 | adapter->ahw.crb_win = window; |
3ce06a32 DP |
1177 | } |
1178 | ||
f58dbd73 NK |
1179 | static void __iomem * |
1180 | netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter, | |
1181 | ulong win_off, void __iomem **mem_ptr) | |
1182 | { | |
1183 | ulong off = win_off; | |
1184 | void __iomem *addr; | |
1185 | resource_size_t mem_base; | |
1186 | ||
1187 | if (ADDR_IN_WINDOW1(win_off)) | |
1188 | off = NETXEN_CRB_NORMAL(win_off); | |
1189 | ||
1190 | addr = pci_base_offset(adapter, off); | |
1191 | if (addr) | |
1192 | return addr; | |
1193 | ||
1194 | if (adapter->ahw.pci_len0 == 0) | |
1195 | off -= NETXEN_PCI_CRBSPACE; | |
1196 | ||
1197 | mem_base = pci_resource_start(adapter->pdev, 0); | |
1198 | *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE); | |
1199 | if (*mem_ptr) | |
1200 | addr = *mem_ptr + (off & (PAGE_SIZE - 1)); | |
1201 | ||
1202 | return addr; | |
1203 | } | |
1204 | ||
195c5f98 | 1205 | static int |
1fbe6323 | 1206 | netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data) |
3d396eb1 | 1207 | { |
195c5f98 | 1208 | unsigned long flags; |
f58dbd73 | 1209 | void __iomem *addr, *mem_ptr = NULL; |
3d396eb1 | 1210 | |
f58dbd73 NK |
1211 | addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr); |
1212 | if (!addr) | |
1213 | return -EIO; | |
195c5f98 | 1214 | |
f58dbd73 | 1215 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ |
f03b0ebd | 1216 | netxen_nic_io_write_128M(adapter, addr, data); |
f58dbd73 | 1217 | } else { /* Window 0 */ |
f03b0ebd | 1218 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
907fa120 | 1219 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
195c5f98 | 1220 | writel(data, addr); |
907fa120 DP |
1221 | netxen_nic_pci_set_crbwindow_128M(adapter, |
1222 | NETXEN_WINDOW_ONE); | |
f03b0ebd | 1223 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
cb8011ad AK |
1224 | } |
1225 | ||
f58dbd73 NK |
1226 | if (mem_ptr) |
1227 | iounmap(mem_ptr); | |
1228 | ||
3d396eb1 AK |
1229 | return 0; |
1230 | } | |
1231 | ||
195c5f98 | 1232 | static u32 |
1fbe6323 | 1233 | netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off) |
3d396eb1 | 1234 | { |
195c5f98 | 1235 | unsigned long flags; |
f58dbd73 | 1236 | void __iomem *addr, *mem_ptr = NULL; |
1fbe6323 | 1237 | u32 data; |
d8313ce0 | 1238 | |
f58dbd73 NK |
1239 | addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr); |
1240 | if (!addr) | |
1241 | return -EIO; | |
3d396eb1 | 1242 | |
f58dbd73 | 1243 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ |
f03b0ebd | 1244 | data = netxen_nic_io_read_128M(adapter, addr); |
f58dbd73 | 1245 | } else { /* Window 0 */ |
f03b0ebd | 1246 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
907fa120 | 1247 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
195c5f98 | 1248 | data = readl(addr); |
907fa120 DP |
1249 | netxen_nic_pci_set_crbwindow_128M(adapter, |
1250 | NETXEN_WINDOW_ONE); | |
f03b0ebd | 1251 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
195c5f98 | 1252 | } |
3d396eb1 | 1253 | |
f58dbd73 NK |
1254 | if (mem_ptr) |
1255 | iounmap(mem_ptr); | |
1256 | ||
1fbe6323 | 1257 | return data; |
3d396eb1 AK |
1258 | } |
1259 | ||
195c5f98 | 1260 | static int |
1fbe6323 | 1261 | netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data) |
3ce06a32 | 1262 | { |
195c5f98 | 1263 | unsigned long flags; |
3ce06a32 | 1264 | int rv; |
a9ac07de | 1265 | void __iomem *addr = NULL; |
3d396eb1 | 1266 | |
a9ac07de | 1267 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr); |
3d396eb1 | 1268 | |
7cecdca1 | 1269 | if (rv == 0) { |
a9ac07de | 1270 | writel(data, addr); |
7cecdca1 | 1271 | return 0; |
3ce06a32 DP |
1272 | } |
1273 | ||
7cecdca1 DP |
1274 | if (rv > 0) { |
1275 | /* indirect access */ | |
f03b0ebd | 1276 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
3ce06a32 | 1277 | crb_win_lock(adapter); |
a9ac07de DP |
1278 | netxen_nic_pci_set_crbwindow_2M(adapter, off); |
1279 | writel(data, addr); | |
3ce06a32 | 1280 | crb_win_unlock(adapter); |
f03b0ebd | 1281 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
7cecdca1 DP |
1282 | return 0; |
1283 | } | |
3ce06a32 | 1284 | |
7cecdca1 DP |
1285 | dev_err(&adapter->pdev->dev, |
1286 | "%s: invalid offset: 0x%016lx\n", __func__, off); | |
1287 | dump_stack(); | |
1288 | return -EIO; | |
3d396eb1 AK |
1289 | } |
1290 | ||
195c5f98 | 1291 | static u32 |
1fbe6323 | 1292 | netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off) |
3ce06a32 | 1293 | { |
195c5f98 | 1294 | unsigned long flags; |
3ce06a32 | 1295 | int rv; |
1fbe6323 | 1296 | u32 data; |
a9ac07de | 1297 | void __iomem *addr = NULL; |
3d396eb1 | 1298 | |
a9ac07de | 1299 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr); |
3ce06a32 | 1300 | |
7cecdca1 | 1301 | if (rv == 0) |
a9ac07de | 1302 | return readl(addr); |
3ce06a32 | 1303 | |
7cecdca1 DP |
1304 | if (rv > 0) { |
1305 | /* indirect access */ | |
f03b0ebd | 1306 | write_lock_irqsave(&adapter->ahw.crb_lock, flags); |
3ce06a32 | 1307 | crb_win_lock(adapter); |
a9ac07de DP |
1308 | netxen_nic_pci_set_crbwindow_2M(adapter, off); |
1309 | data = readl(addr); | |
3ce06a32 | 1310 | crb_win_unlock(adapter); |
f03b0ebd | 1311 | write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); |
7cecdca1 DP |
1312 | return data; |
1313 | } | |
3ce06a32 | 1314 | |
7cecdca1 DP |
1315 | dev_err(&adapter->pdev->dev, |
1316 | "%s: invalid offset: 0x%016lx\n", __func__, off); | |
1317 | dump_stack(); | |
1318 | return -1; | |
3ce06a32 DP |
1319 | } |
1320 | ||
195c5f98 AKS |
1321 | /* window 1 registers only */ |
1322 | static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, | |
1323 | void __iomem *addr, u32 data) | |
3ce06a32 | 1324 | { |
f03b0ebd | 1325 | read_lock(&adapter->ahw.crb_lock); |
195c5f98 | 1326 | writel(data, addr); |
f03b0ebd | 1327 | read_unlock(&adapter->ahw.crb_lock); |
195c5f98 AKS |
1328 | } |
1329 | ||
1330 | static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, | |
1331 | void __iomem *addr) | |
1332 | { | |
1333 | u32 val; | |
1334 | ||
f03b0ebd | 1335 | read_lock(&adapter->ahw.crb_lock); |
195c5f98 | 1336 | val = readl(addr); |
f03b0ebd | 1337 | read_unlock(&adapter->ahw.crb_lock); |
195c5f98 AKS |
1338 | |
1339 | return val; | |
3ce06a32 DP |
1340 | } |
1341 | ||
195c5f98 AKS |
1342 | static void netxen_nic_io_write_2M(struct netxen_adapter *adapter, |
1343 | void __iomem *addr, u32 data) | |
3ce06a32 | 1344 | { |
195c5f98 AKS |
1345 | writel(data, addr); |
1346 | } | |
1347 | ||
1348 | static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter, | |
1349 | void __iomem *addr) | |
1350 | { | |
1351 | return readl(addr); | |
1352 | } | |
1353 | ||
1354 | void __iomem * | |
1355 | netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset) | |
1356 | { | |
a9ac07de | 1357 | void __iomem *addr = NULL; |
195c5f98 AKS |
1358 | |
1359 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
a9ac07de DP |
1360 | if ((offset < NETXEN_CRB_PCIX_HOST2) && |
1361 | (offset > NETXEN_CRB_PCIX_HOST)) | |
1362 | addr = PCI_OFFSET_SECOND_RANGE(adapter, offset); | |
1363 | else | |
1364 | addr = NETXEN_CRB_NORMALIZE(adapter, offset); | |
1365 | } else { | |
1366 | WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter, | |
1367 | offset, &addr)); | |
195c5f98 AKS |
1368 | } |
1369 | ||
a9ac07de | 1370 | return addr; |
3ce06a32 DP |
1371 | } |
1372 | ||
47abe356 DP |
1373 | static int |
1374 | netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, | |
1375 | u64 addr, u32 *start) | |
3ce06a32 | 1376 | { |
47abe356 DP |
1377 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
1378 | *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0); | |
1379 | return 0; | |
3ce06a32 | 1380 | } else if (ADDR_IN_RANGE(addr, |
47abe356 DP |
1381 | NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { |
1382 | *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1); | |
1383 | return 0; | |
1384 | } | |
3ce06a32 | 1385 | |
47abe356 DP |
1386 | return -EIO; |
1387 | } | |
3ce06a32 | 1388 | |
47abe356 DP |
1389 | static int |
1390 | netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |
1391 | u64 addr, u32 *start) | |
1392 | { | |
6abb4b83 | 1393 | u32 window; |
47abe356 | 1394 | struct pci_dev *pdev = adapter->pdev; |
3ce06a32 | 1395 | |
47abe356 DP |
1396 | if ((addr & 0x00ff800) == 0xff800) { |
1397 | if (printk_ratelimit()) | |
1398 | dev_warn(&pdev->dev, "QM access not handled\n"); | |
1399 | return -EIO; | |
1400 | } | |
1401 | ||
6abb4b83 AKS |
1402 | if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) |
1403 | window = OCM_WIN_P3P(addr); | |
1404 | else | |
1405 | window = OCM_WIN(addr); | |
1406 | ||
47abe356 | 1407 | writel(window, adapter->ahw.ocm_win_crb); |
6abb4b83 AKS |
1408 | /* read back to flush */ |
1409 | readl(adapter->ahw.ocm_win_crb); | |
47abe356 DP |
1410 | |
1411 | adapter->ahw.ocm_win = window; | |
1412 | *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr); | |
1413 | return 0; | |
3ce06a32 | 1414 | } |
47abe356 DP |
1415 | |
1416 | static int | |
1417 | netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off, | |
1418 | u64 *data, int op) | |
1419 | { | |
1420 | void __iomem *addr, *mem_ptr = NULL; | |
1421 | resource_size_t mem_base; | |
47abe356 DP |
1422 | int ret = -EIO; |
1423 | u32 start; | |
1424 | ||
f03b0ebd | 1425 | spin_lock(&adapter->ahw.mem_lock); |
47abe356 DP |
1426 | |
1427 | ret = adapter->pci_set_window(adapter, off, &start); | |
1428 | if (ret != 0) | |
1429 | goto unlock; | |
1430 | ||
1431 | addr = pci_base_offset(adapter, start); | |
1432 | if (addr) | |
1433 | goto noremap; | |
1434 | ||
1435 | mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK); | |
1436 | ||
1437 | mem_ptr = ioremap(mem_base, PAGE_SIZE); | |
1438 | if (mem_ptr == NULL) { | |
1439 | ret = -EIO; | |
1440 | goto unlock; | |
3d396eb1 | 1441 | } |
47abe356 DP |
1442 | |
1443 | addr = mem_ptr + (start & (PAGE_SIZE - 1)); | |
1444 | ||
1445 | noremap: | |
1446 | if (op == 0) /* read */ | |
1447 | *data = readq(addr); | |
1448 | else /* write */ | |
1449 | writeq(*data, addr); | |
1450 | ||
1451 | unlock: | |
f03b0ebd DP |
1452 | spin_unlock(&adapter->ahw.mem_lock); |
1453 | ||
47abe356 DP |
1454 | if (mem_ptr) |
1455 | iounmap(mem_ptr); | |
1456 | return ret; | |
3d396eb1 AK |
1457 | } |
1458 | ||
3ce06a32 DP |
1459 | #define MAX_CTL_CHECK 1000 |
1460 | ||
195c5f98 | 1461 | static int |
3ce06a32 | 1462 | netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, |
1f5e055d | 1463 | u64 off, u64 data) |
3ce06a32 | 1464 | { |
1f5e055d AKS |
1465 | int j, ret; |
1466 | u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo; | |
d8313ce0 | 1467 | void __iomem *mem_crb; |
3ce06a32 | 1468 | |
1f5e055d AKS |
1469 | /* Only 64-bit aligned access */ |
1470 | if (off & 7) | |
ea6828b8 DP |
1471 | return -EIO; |
1472 | ||
1f5e055d | 1473 | /* P2 has different SIU and MIU test agent base addr */ |
ea6828b8 DP |
1474 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1475 | NETXEN_ADDR_QDR_NET_MAX_P2)) { | |
1f5e055d AKS |
1476 | mem_crb = pci_base_offset(adapter, |
1477 | NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE); | |
1478 | addr_hi = SIU_TEST_AGT_ADDR_HI; | |
1479 | data_lo = SIU_TEST_AGT_WRDATA_LO; | |
1480 | data_hi = SIU_TEST_AGT_WRDATA_HI; | |
1481 | off_lo = off & SIU_TEST_AGT_ADDR_MASK; | |
1482 | off_hi = SIU_TEST_AGT_UPPER_ADDR(off); | |
ea6828b8 DP |
1483 | goto correct; |
1484 | } | |
3ce06a32 | 1485 | |
ea6828b8 | 1486 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
1f5e055d AKS |
1487 | mem_crb = pci_base_offset(adapter, |
1488 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
1489 | addr_hi = MIU_TEST_AGT_ADDR_HI; | |
1490 | data_lo = MIU_TEST_AGT_WRDATA_LO; | |
1491 | data_hi = MIU_TEST_AGT_WRDATA_HI; | |
1492 | off_lo = off & MIU_TEST_AGT_ADDR_MASK; | |
1493 | off_hi = 0; | |
ea6828b8 DP |
1494 | goto correct; |
1495 | } | |
1496 | ||
47abe356 DP |
1497 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) || |
1498 | ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { | |
1499 | if (adapter->ahw.pci_len0 != 0) { | |
1500 | return netxen_nic_pci_mem_access_direct(adapter, | |
1501 | off, &data, 1); | |
1502 | } | |
1503 | } | |
1504 | ||
ea6828b8 DP |
1505 | return -EIO; |
1506 | ||
1507 | correct: | |
f03b0ebd | 1508 | spin_lock(&adapter->ahw.mem_lock); |
907fa120 | 1509 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
3ce06a32 | 1510 | |
1f5e055d AKS |
1511 | writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1512 | writel(off_hi, (mem_crb + addr_hi)); | |
1513 | writel(data & 0xffffffff, (mem_crb + data_lo)); | |
1514 | writel((data >> 32) & 0xffffffff, (mem_crb + data_hi)); | |
1515 | writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); | |
1516 | writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), | |
1517 | (mem_crb + TEST_AGT_CTRL)); | |
1518 | ||
1519 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1520 | temp = readl((mem_crb + TEST_AGT_CTRL)); | |
1521 | if ((temp & TA_CTL_BUSY) == 0) | |
3ce06a32 | 1522 | break; |
3ce06a32 DP |
1523 | } |
1524 | ||
1f5e055d AKS |
1525 | if (j >= MAX_CTL_CHECK) { |
1526 | if (printk_ratelimit()) | |
1527 | dev_err(&adapter->pdev->dev, | |
1528 | "failed to write through agent\n"); | |
1529 | ret = -EIO; | |
1530 | } else | |
1531 | ret = 0; | |
1532 | ||
907fa120 | 1533 | netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE); |
f03b0ebd | 1534 | spin_unlock(&adapter->ahw.mem_lock); |
3ce06a32 DP |
1535 | return ret; |
1536 | } | |
1537 | ||
195c5f98 | 1538 | static int |
3ce06a32 | 1539 | netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, |
1f5e055d | 1540 | u64 off, u64 *data) |
3ce06a32 | 1541 | { |
1f5e055d AKS |
1542 | int j, ret; |
1543 | u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo; | |
1544 | u64 val; | |
d8313ce0 | 1545 | void __iomem *mem_crb; |
3ce06a32 | 1546 | |
1f5e055d AKS |
1547 | /* Only 64-bit aligned access */ |
1548 | if (off & 7) | |
ea6828b8 DP |
1549 | return -EIO; |
1550 | ||
1f5e055d | 1551 | /* P2 has different SIU and MIU test agent base addr */ |
ea6828b8 DP |
1552 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1553 | NETXEN_ADDR_QDR_NET_MAX_P2)) { | |
1f5e055d AKS |
1554 | mem_crb = pci_base_offset(adapter, |
1555 | NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE); | |
1556 | addr_hi = SIU_TEST_AGT_ADDR_HI; | |
1557 | data_lo = SIU_TEST_AGT_RDDATA_LO; | |
1558 | data_hi = SIU_TEST_AGT_RDDATA_HI; | |
1559 | off_lo = off & SIU_TEST_AGT_ADDR_MASK; | |
1560 | off_hi = SIU_TEST_AGT_UPPER_ADDR(off); | |
ea6828b8 DP |
1561 | goto correct; |
1562 | } | |
3ce06a32 | 1563 | |
ea6828b8 | 1564 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
1f5e055d AKS |
1565 | mem_crb = pci_base_offset(adapter, |
1566 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
1567 | addr_hi = MIU_TEST_AGT_ADDR_HI; | |
1568 | data_lo = MIU_TEST_AGT_RDDATA_LO; | |
1569 | data_hi = MIU_TEST_AGT_RDDATA_HI; | |
1570 | off_lo = off & MIU_TEST_AGT_ADDR_MASK; | |
1571 | off_hi = 0; | |
ea6828b8 DP |
1572 | goto correct; |
1573 | } | |
1574 | ||
47abe356 DP |
1575 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) || |
1576 | ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { | |
1577 | if (adapter->ahw.pci_len0 != 0) { | |
1578 | return netxen_nic_pci_mem_access_direct(adapter, | |
1579 | off, data, 0); | |
1580 | } | |
1581 | } | |
1582 | ||
ea6828b8 | 1583 | return -EIO; |
3ce06a32 | 1584 | |
ea6828b8 | 1585 | correct: |
f03b0ebd | 1586 | spin_lock(&adapter->ahw.mem_lock); |
907fa120 | 1587 | netxen_nic_pci_set_crbwindow_128M(adapter, 0); |
3ce06a32 | 1588 | |
1f5e055d AKS |
1589 | writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1590 | writel(off_hi, (mem_crb + addr_hi)); | |
1591 | writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); | |
1592 | writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL)); | |
3ce06a32 | 1593 | |
1f5e055d AKS |
1594 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
1595 | temp = readl(mem_crb + TEST_AGT_CTRL); | |
1596 | if ((temp & TA_CTL_BUSY) == 0) | |
3ce06a32 | 1597 | break; |
1f5e055d | 1598 | } |
3ce06a32 | 1599 | |
1f5e055d AKS |
1600 | if (j >= MAX_CTL_CHECK) { |
1601 | if (printk_ratelimit()) | |
1602 | dev_err(&adapter->pdev->dev, | |
1603 | "failed to read through agent\n"); | |
1604 | ret = -EIO; | |
1605 | } else { | |
1606 | ||
1607 | temp = readl(mem_crb + data_hi); | |
1608 | val = ((u64)temp << 32); | |
1609 | val |= readl(mem_crb + data_lo); | |
1610 | *data = val; | |
1611 | ret = 0; | |
3ce06a32 DP |
1612 | } |
1613 | ||
907fa120 | 1614 | netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE); |
f03b0ebd | 1615 | spin_unlock(&adapter->ahw.mem_lock); |
3ce06a32 | 1616 | |
1f5e055d | 1617 | return ret; |
3ce06a32 DP |
1618 | } |
1619 | ||
195c5f98 | 1620 | static int |
3ce06a32 | 1621 | netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, |
1f5e055d | 1622 | u64 off, u64 data) |
3ce06a32 | 1623 | { |
fb1f6a43 | 1624 | int i, j, ret; |
1f5e055d | 1625 | u32 temp, off8; |
fb1f6a43 | 1626 | u64 stride; |
ea6828b8 | 1627 | void __iomem *mem_crb; |
3ce06a32 | 1628 | |
1f5e055d AKS |
1629 | /* Only 64-bit aligned access */ |
1630 | if (off & 7) | |
ea6828b8 DP |
1631 | return -EIO; |
1632 | ||
1f5e055d | 1633 | /* P3 onward, test agent base for MIU and SIU is same */ |
ea6828b8 DP |
1634 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1635 | NETXEN_ADDR_QDR_NET_MAX_P3)) { | |
1f5e055d AKS |
1636 | mem_crb = netxen_get_ioaddr(adapter, |
1637 | NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 DP |
1638 | goto correct; |
1639 | } | |
1640 | ||
1641 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { | |
1f5e055d AKS |
1642 | mem_crb = netxen_get_ioaddr(adapter, |
1643 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 | 1644 | goto correct; |
3ce06a32 DP |
1645 | } |
1646 | ||
47abe356 DP |
1647 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) |
1648 | return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1); | |
1649 | ||
ea6828b8 DP |
1650 | return -EIO; |
1651 | ||
1652 | correct: | |
fb1f6a43 AKS |
1653 | stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8; |
1654 | ||
1655 | off8 = off & ~(stride-1); | |
3ce06a32 | 1656 | |
f03b0ebd | 1657 | spin_lock(&adapter->ahw.mem_lock); |
3ce06a32 | 1658 | |
1f5e055d AKS |
1659 | writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1660 | writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); | |
fb1f6a43 AKS |
1661 | |
1662 | i = 0; | |
1663 | if (stride == 16) { | |
1664 | writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); | |
1665 | writel((TA_CTL_START | TA_CTL_ENABLE), | |
1666 | (mem_crb + TEST_AGT_CTRL)); | |
1667 | ||
1668 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1669 | temp = readl(mem_crb + TEST_AGT_CTRL); | |
1670 | if ((temp & TA_CTL_BUSY) == 0) | |
1671 | break; | |
1672 | } | |
1673 | ||
1674 | if (j >= MAX_CTL_CHECK) { | |
1675 | ret = -EIO; | |
1676 | goto done; | |
1677 | } | |
1678 | ||
1679 | i = (off & 0xf) ? 0 : 2; | |
1680 | writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)), | |
1681 | mem_crb + MIU_TEST_AGT_WRDATA(i)); | |
1682 | writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)), | |
1683 | mem_crb + MIU_TEST_AGT_WRDATA(i+1)); | |
1684 | i = (off & 0xf) ? 2 : 0; | |
1685 | } | |
1686 | ||
1687 | writel(data & 0xffffffff, | |
1688 | mem_crb + MIU_TEST_AGT_WRDATA(i)); | |
1689 | writel((data >> 32) & 0xffffffff, | |
1690 | mem_crb + MIU_TEST_AGT_WRDATA(i+1)); | |
1691 | ||
1f5e055d AKS |
1692 | writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); |
1693 | writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), | |
1694 | (mem_crb + TEST_AGT_CTRL)); | |
1695 | ||
1696 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1697 | temp = readl(mem_crb + TEST_AGT_CTRL); | |
1698 | if ((temp & TA_CTL_BUSY) == 0) | |
1699 | break; | |
3ce06a32 DP |
1700 | } |
1701 | ||
1f5e055d AKS |
1702 | if (j >= MAX_CTL_CHECK) { |
1703 | if (printk_ratelimit()) | |
1704 | dev_err(&adapter->pdev->dev, | |
39754f44 | 1705 | "failed to write through agent\n"); |
1f5e055d AKS |
1706 | ret = -EIO; |
1707 | } else | |
1708 | ret = 0; | |
1709 | ||
fb1f6a43 | 1710 | done: |
f03b0ebd | 1711 | spin_unlock(&adapter->ahw.mem_lock); |
3ce06a32 | 1712 | |
3ce06a32 DP |
1713 | return ret; |
1714 | } | |
1715 | ||
195c5f98 | 1716 | static int |
3ce06a32 | 1717 | netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, |
1f5e055d | 1718 | u64 off, u64 *data) |
3ce06a32 | 1719 | { |
1f5e055d AKS |
1720 | int j, ret; |
1721 | u32 temp, off8; | |
fb1f6a43 | 1722 | u64 val, stride; |
ea6828b8 | 1723 | void __iomem *mem_crb; |
3ce06a32 | 1724 | |
1f5e055d AKS |
1725 | /* Only 64-bit aligned access */ |
1726 | if (off & 7) | |
ea6828b8 | 1727 | return -EIO; |
3ce06a32 | 1728 | |
1f5e055d | 1729 | /* P3 onward, test agent base for MIU and SIU is same */ |
ea6828b8 DP |
1730 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
1731 | NETXEN_ADDR_QDR_NET_MAX_P3)) { | |
1f5e055d AKS |
1732 | mem_crb = netxen_get_ioaddr(adapter, |
1733 | NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 | 1734 | goto correct; |
3ce06a32 DP |
1735 | } |
1736 | ||
ea6828b8 | 1737 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
1f5e055d AKS |
1738 | mem_crb = netxen_get_ioaddr(adapter, |
1739 | NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); | |
ea6828b8 DP |
1740 | goto correct; |
1741 | } | |
1742 | ||
907fa120 DP |
1743 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
1744 | return netxen_nic_pci_mem_access_direct(adapter, | |
1745 | off, data, 0); | |
1746 | } | |
47abe356 | 1747 | |
ea6828b8 DP |
1748 | return -EIO; |
1749 | ||
1750 | correct: | |
fb1f6a43 AKS |
1751 | stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8; |
1752 | ||
1753 | off8 = off & ~(stride-1); | |
3ce06a32 | 1754 | |
f03b0ebd | 1755 | spin_lock(&adapter->ahw.mem_lock); |
3ce06a32 | 1756 | |
1f5e055d AKS |
1757 | writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); |
1758 | writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); | |
1759 | writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); | |
1760 | writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL)); | |
3ce06a32 | 1761 | |
1f5e055d AKS |
1762 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
1763 | temp = readl(mem_crb + TEST_AGT_CTRL); | |
1764 | if ((temp & TA_CTL_BUSY) == 0) | |
3ce06a32 | 1765 | break; |
3ce06a32 DP |
1766 | } |
1767 | ||
1f5e055d AKS |
1768 | if (j >= MAX_CTL_CHECK) { |
1769 | if (printk_ratelimit()) | |
1770 | dev_err(&adapter->pdev->dev, | |
1771 | "failed to read through agent\n"); | |
1772 | ret = -EIO; | |
3ce06a32 | 1773 | } else { |
fb1f6a43 AKS |
1774 | off8 = MIU_TEST_AGT_RDDATA_LO; |
1775 | if ((stride == 16) && (off & 0xf)) | |
1776 | off8 = MIU_TEST_AGT_RDDATA_UPPER_LO; | |
1777 | ||
1778 | temp = readl(mem_crb + off8 + 4); | |
1f5e055d | 1779 | val = (u64)temp << 32; |
fb1f6a43 | 1780 | val |= readl(mem_crb + off8); |
1f5e055d AKS |
1781 | *data = val; |
1782 | ret = 0; | |
3ce06a32 DP |
1783 | } |
1784 | ||
f03b0ebd | 1785 | spin_unlock(&adapter->ahw.mem_lock); |
1f5e055d AKS |
1786 | |
1787 | return ret; | |
3ce06a32 DP |
1788 | } |
1789 | ||
195c5f98 AKS |
1790 | void |
1791 | netxen_setup_hwops(struct netxen_adapter *adapter) | |
3ce06a32 | 1792 | { |
195c5f98 AKS |
1793 | adapter->init_port = netxen_niu_xg_init_port; |
1794 | adapter->stop_port = netxen_niu_disable_xg_port; | |
3ce06a32 | 1795 | |
195c5f98 AKS |
1796 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
1797 | adapter->crb_read = netxen_nic_hw_read_wx_128M, | |
1798 | adapter->crb_write = netxen_nic_hw_write_wx_128M, | |
1799 | adapter->pci_set_window = netxen_nic_pci_set_window_128M, | |
1800 | adapter->pci_mem_read = netxen_nic_pci_mem_read_128M, | |
1801 | adapter->pci_mem_write = netxen_nic_pci_mem_write_128M, | |
1802 | adapter->io_read = netxen_nic_io_read_128M, | |
1803 | adapter->io_write = netxen_nic_io_write_128M, | |
1804 | ||
1805 | adapter->macaddr_set = netxen_p2_nic_set_mac_addr; | |
1806 | adapter->set_multi = netxen_p2_nic_set_multi; | |
1807 | adapter->set_mtu = netxen_nic_set_mtu_xgb; | |
1808 | adapter->set_promisc = netxen_p2_nic_set_promisc; | |
3ce06a32 | 1809 | |
195c5f98 AKS |
1810 | } else { |
1811 | adapter->crb_read = netxen_nic_hw_read_wx_2M, | |
1812 | adapter->crb_write = netxen_nic_hw_write_wx_2M, | |
1813 | adapter->pci_set_window = netxen_nic_pci_set_window_2M, | |
1814 | adapter->pci_mem_read = netxen_nic_pci_mem_read_2M, | |
1815 | adapter->pci_mem_write = netxen_nic_pci_mem_write_2M, | |
1816 | adapter->io_read = netxen_nic_io_read_2M, | |
1817 | adapter->io_write = netxen_nic_io_write_2M, | |
1818 | ||
1819 | adapter->set_mtu = nx_fw_cmd_set_mtu; | |
1820 | adapter->set_promisc = netxen_p3_nic_set_promisc; | |
1821 | adapter->macaddr_set = netxen_p3_nic_set_mac_addr; | |
1822 | adapter->set_multi = netxen_p3_nic_set_multi; | |
1823 | ||
1824 | adapter->phy_read = nx_fw_cmd_query_phy; | |
1825 | adapter->phy_write = nx_fw_cmd_set_phy; | |
1826 | } | |
3ce06a32 DP |
1827 | } |
1828 | ||
3d396eb1 AK |
1829 | int netxen_nic_get_board_info(struct netxen_adapter *adapter) |
1830 | { | |
0dc6d9cb | 1831 | int offset, board_type, magic; |
1e2d0059 | 1832 | struct pci_dev *pdev = adapter->pdev; |
3d396eb1 | 1833 | |
06db58c0 | 1834 | offset = NX_FW_MAGIC_OFFSET; |
1e2d0059 DP |
1835 | if (netxen_rom_fast_read(adapter, offset, &magic)) |
1836 | return -EIO; | |
3d396eb1 | 1837 | |
0dc6d9cb DP |
1838 | if (magic != NETXEN_BDINFO_MAGIC) { |
1839 | dev_err(&pdev->dev, "invalid board config, magic=%08x\n", | |
1840 | magic); | |
1e2d0059 | 1841 | return -EIO; |
3d396eb1 AK |
1842 | } |
1843 | ||
06db58c0 | 1844 | offset = NX_BRDTYPE_OFFSET; |
1e2d0059 DP |
1845 | if (netxen_rom_fast_read(adapter, offset, &board_type)) |
1846 | return -EIO; | |
1847 | ||
1848 | adapter->ahw.board_type = board_type; | |
1849 | ||
1850 | if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { | |
f98a9f69 | 1851 | u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I); |
c7860a2a | 1852 | if ((gpio & 0x8000) == 0) |
1e2d0059 | 1853 | board_type = NETXEN_BRDTYPE_P3_10G_TP; |
c7860a2a DP |
1854 | } |
1855 | ||
e98e3350 | 1856 | switch (board_type) { |
3d396eb1 | 1857 | case NETXEN_BRDTYPE_P2_SB35_4G: |
1e2d0059 | 1858 | adapter->ahw.port_type = NETXEN_NIC_GBE; |
3d396eb1 AK |
1859 | break; |
1860 | case NETXEN_BRDTYPE_P2_SB31_10G: | |
1861 | case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: | |
1862 | case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: | |
1863 | case NETXEN_BRDTYPE_P2_SB31_10G_CX4: | |
e4c93c81 DP |
1864 | case NETXEN_BRDTYPE_P3_HMEZ: |
1865 | case NETXEN_BRDTYPE_P3_XG_LOM: | |
1866 | case NETXEN_BRDTYPE_P3_10G_CX4: | |
1867 | case NETXEN_BRDTYPE_P3_10G_CX4_LP: | |
1868 | case NETXEN_BRDTYPE_P3_IMEZ: | |
1869 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: | |
a70f9393 DP |
1870 | case NETXEN_BRDTYPE_P3_10G_SFP_CT: |
1871 | case NETXEN_BRDTYPE_P3_10G_SFP_QT: | |
e4c93c81 DP |
1872 | case NETXEN_BRDTYPE_P3_10G_XFP: |
1873 | case NETXEN_BRDTYPE_P3_10000_BASE_T: | |
1e2d0059 | 1874 | adapter->ahw.port_type = NETXEN_NIC_XGBE; |
3d396eb1 AK |
1875 | break; |
1876 | case NETXEN_BRDTYPE_P1_BD: | |
1877 | case NETXEN_BRDTYPE_P1_SB: | |
1878 | case NETXEN_BRDTYPE_P1_SMAX: | |
1879 | case NETXEN_BRDTYPE_P1_SOCK: | |
e4c93c81 DP |
1880 | case NETXEN_BRDTYPE_P3_REF_QG: |
1881 | case NETXEN_BRDTYPE_P3_4_GB: | |
1882 | case NETXEN_BRDTYPE_P3_4_GB_MM: | |
1e2d0059 | 1883 | adapter->ahw.port_type = NETXEN_NIC_GBE; |
3d396eb1 | 1884 | break; |
c7860a2a | 1885 | case NETXEN_BRDTYPE_P3_10G_TP: |
1e2d0059 | 1886 | adapter->ahw.port_type = (adapter->portnum < 2) ? |
c7860a2a DP |
1887 | NETXEN_NIC_XGBE : NETXEN_NIC_GBE; |
1888 | break; | |
3d396eb1 | 1889 | default: |
1e2d0059 DP |
1890 | dev_err(&pdev->dev, "unknown board type %x\n", board_type); |
1891 | adapter->ahw.port_type = NETXEN_NIC_XGBE; | |
3d396eb1 AK |
1892 | break; |
1893 | } | |
1894 | ||
1e2d0059 | 1895 | return 0; |
3d396eb1 AK |
1896 | } |
1897 | ||
1898 | /* NIU access sections */ | |
1899 | ||
3176ff3e | 1900 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 1901 | { |
9ad27643 | 1902 | new_mtu += MTU_FUDGE_FACTOR; |
f98a9f69 | 1903 | NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), |
3276fbad | 1904 | new_mtu); |
3d396eb1 AK |
1905 | return 0; |
1906 | } | |
1907 | ||
3176ff3e | 1908 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 1909 | { |
9ad27643 | 1910 | new_mtu += MTU_FUDGE_FACTOR; |
3276fbad | 1911 | if (adapter->physical_port == 0) |
f98a9f69 | 1912 | NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu); |
4790654c | 1913 | else |
f98a9f69 | 1914 | NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu); |
3d396eb1 AK |
1915 | return 0; |
1916 | } | |
1917 | ||
3176ff3e | 1918 | void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) |
3d396eb1 | 1919 | { |
a608ab9c AV |
1920 | __u32 status; |
1921 | __u32 autoneg; | |
24a7a455 | 1922 | __u32 port_mode; |
3d396eb1 | 1923 | |
c7860a2a DP |
1924 | if (!netif_carrier_ok(adapter->netdev)) { |
1925 | adapter->link_speed = 0; | |
1926 | adapter->link_duplex = -1; | |
1927 | adapter->link_autoneg = AUTONEG_ENABLE; | |
1928 | return; | |
1929 | } | |
24a7a455 | 1930 | |
1e2d0059 | 1931 | if (adapter->ahw.port_type == NETXEN_NIC_GBE) { |
f98a9f69 | 1932 | port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR); |
24a7a455 DP |
1933 | if (port_mode == NETXEN_PORT_MODE_802_3_AP) { |
1934 | adapter->link_speed = SPEED_1000; | |
1935 | adapter->link_duplex = DUPLEX_FULL; | |
1936 | adapter->link_autoneg = AUTONEG_DISABLE; | |
1937 | return; | |
1938 | } | |
1939 | ||
8e95a202 JP |
1940 | if (adapter->phy_read && |
1941 | adapter->phy_read(adapter, | |
1942 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, | |
1943 | &status) == 0) { | |
3d396eb1 AK |
1944 | if (netxen_get_phy_link(status)) { |
1945 | switch (netxen_get_phy_speed(status)) { | |
1946 | case 0: | |
3176ff3e | 1947 | adapter->link_speed = SPEED_10; |
3d396eb1 AK |
1948 | break; |
1949 | case 1: | |
3176ff3e | 1950 | adapter->link_speed = SPEED_100; |
3d396eb1 AK |
1951 | break; |
1952 | case 2: | |
3176ff3e | 1953 | adapter->link_speed = SPEED_1000; |
3d396eb1 AK |
1954 | break; |
1955 | default: | |
c7860a2a | 1956 | adapter->link_speed = 0; |
3d396eb1 AK |
1957 | break; |
1958 | } | |
1959 | switch (netxen_get_phy_duplex(status)) { | |
1960 | case 0: | |
3176ff3e | 1961 | adapter->link_duplex = DUPLEX_HALF; |
3d396eb1 AK |
1962 | break; |
1963 | case 1: | |
3176ff3e | 1964 | adapter->link_duplex = DUPLEX_FULL; |
3d396eb1 AK |
1965 | break; |
1966 | default: | |
3176ff3e | 1967 | adapter->link_duplex = -1; |
3d396eb1 AK |
1968 | break; |
1969 | } | |
8e95a202 JP |
1970 | if (adapter->phy_read && |
1971 | adapter->phy_read(adapter, | |
1972 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, | |
1973 | &autoneg) != 0) | |
3176ff3e | 1974 | adapter->link_autoneg = autoneg; |
3d396eb1 AK |
1975 | } else |
1976 | goto link_down; | |
1977 | } else { | |
1978 | link_down: | |
c7860a2a | 1979 | adapter->link_speed = 0; |
3176ff3e | 1980 | adapter->link_duplex = -1; |
3d396eb1 AK |
1981 | } |
1982 | } | |
1983 | } | |
1984 | ||
0b72e659 DP |
1985 | int |
1986 | netxen_nic_wol_supported(struct netxen_adapter *adapter) | |
1987 | { | |
1988 | u32 wol_cfg; | |
1989 | ||
1990 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
1991 | return 0; | |
1992 | ||
f98a9f69 | 1993 | wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV); |
0b72e659 | 1994 | if (wol_cfg & (1UL << adapter->portnum)) { |
f98a9f69 | 1995 | wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG); |
0b72e659 DP |
1996 | if (wol_cfg & (1 << adapter->portnum)) |
1997 | return 1; | |
1998 | } | |
1999 | ||
2000 | return 0; | |
2001 | } |