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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
cb8011ad | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
cb8011ad | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | * | |
29 | * | |
30 | * Source file for NIC routines to access the Phantom hardware | |
31 | * | |
32 | */ | |
33 | ||
34 | #include "netxen_nic.h" | |
35 | #include "netxen_nic_hw.h" | |
36 | #include "netxen_nic_phan_reg.h" | |
37 | ||
3176ff3e | 38 | |
c9bdd4b5 ACM |
39 | #include <net/ip.h> |
40 | ||
3176ff3e MT |
41 | struct netxen_recv_crb recv_crb_registers[] = { |
42 | /* | |
43 | * Instance 0. | |
44 | */ | |
45 | { | |
7830b22c DP |
46 | /* crb_rcv_producer: */ |
47 | { | |
48 | NETXEN_NIC_REG(0x100), | |
49 | /* Jumbo frames */ | |
50 | NETXEN_NIC_REG(0x110), | |
51 | /* LRO */ | |
52 | NETXEN_NIC_REG(0x120) | |
53 | }, | |
54 | /* crb_sts_consumer: */ | |
55 | NETXEN_NIC_REG(0x138), | |
56 | }, | |
3176ff3e MT |
57 | /* |
58 | * Instance 1, | |
59 | */ | |
60 | { | |
7830b22c DP |
61 | /* crb_rcv_producer: */ |
62 | { | |
63 | NETXEN_NIC_REG(0x144), | |
64 | /* Jumbo frames */ | |
65 | NETXEN_NIC_REG(0x154), | |
66 | /* LRO */ | |
67 | NETXEN_NIC_REG(0x164) | |
68 | }, | |
69 | /* crb_sts_consumer: */ | |
70 | NETXEN_NIC_REG(0x17c), | |
71 | }, | |
595e3fb8 | 72 | /* |
6c80b18d | 73 | * Instance 2, |
595e3fb8 MT |
74 | */ |
75 | { | |
7830b22c DP |
76 | /* crb_rcv_producer: */ |
77 | { | |
78 | NETXEN_NIC_REG(0x1d8), | |
79 | /* Jumbo frames */ | |
80 | NETXEN_NIC_REG(0x1f8), | |
81 | /* LRO */ | |
82 | NETXEN_NIC_REG(0x208) | |
83 | }, | |
84 | /* crb_sts_consumer: */ | |
85 | NETXEN_NIC_REG(0x220), | |
595e3fb8 MT |
86 | }, |
87 | /* | |
6c80b18d | 88 | * Instance 3, |
595e3fb8 MT |
89 | */ |
90 | { | |
7830b22c DP |
91 | /* crb_rcv_producer: */ |
92 | { | |
93 | NETXEN_NIC_REG(0x22c), | |
94 | /* Jumbo frames */ | |
95 | NETXEN_NIC_REG(0x23c), | |
96 | /* LRO */ | |
97 | NETXEN_NIC_REG(0x24c) | |
98 | }, | |
99 | /* crb_sts_consumer: */ | |
100 | NETXEN_NIC_REG(0x264), | |
595e3fb8 | 101 | }, |
3176ff3e MT |
102 | }; |
103 | ||
993fb90c | 104 | static u64 ctx_addr_sig_regs[][3] = { |
3176ff3e MT |
105 | {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)}, |
106 | {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)}, | |
107 | {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)}, | |
108 | {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)} | |
109 | }; | |
993fb90c AB |
110 | #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0]) |
111 | #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2]) | |
112 | #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1]) | |
3176ff3e MT |
113 | |
114 | ||
3d396eb1 AK |
115 | /* PCI Windowing for DDR regions. */ |
116 | ||
117 | #define ADDR_IN_RANGE(addr, low, high) \ | |
118 | (((addr) <= (high)) && ((addr) >= (low))) | |
119 | ||
0d04761d | 120 | #define NETXEN_FLASH_BASE (NETXEN_BOOTLD_START) |
3d396eb1 | 121 | #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE) |
ed25ffa1 | 122 | #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE |
cb8011ad | 123 | #define NETXEN_MIN_MTU 64 |
3d396eb1 AK |
124 | #define NETXEN_ETH_FCS_SIZE 4 |
125 | #define NETXEN_ENET_HEADER_SIZE 14 | |
cb8011ad | 126 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ |
3d396eb1 AK |
127 | #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4) |
128 | #define NETXEN_NIU_HDRSIZE (0x1 << 6) | |
129 | #define NETXEN_NIU_TLRSIZE (0x1 << 5) | |
130 | ||
cb8011ad AK |
131 | #define lower32(x) ((u32)((x) & 0xffffffff)) |
132 | #define upper32(x) \ | |
133 | ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff)) | |
134 | ||
135 | #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL | |
136 | #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL | |
137 | #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL | |
138 | #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL | |
139 | ||
140 | #define NETXEN_NIC_WINDOW_MARGIN 0x100000 | |
141 | ||
993fb90c AB |
142 | static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter, |
143 | unsigned long long addr); | |
3d396eb1 AK |
144 | void netxen_free_hw_resources(struct netxen_adapter *adapter); |
145 | ||
146 | int netxen_nic_set_mac(struct net_device *netdev, void *p) | |
147 | { | |
3176ff3e | 148 | struct netxen_adapter *adapter = netdev_priv(netdev); |
3d396eb1 AK |
149 | struct sockaddr *addr = p; |
150 | ||
151 | if (netif_running(netdev)) | |
152 | return -EBUSY; | |
153 | ||
154 | if (!is_valid_ether_addr(addr->sa_data)) | |
155 | return -EADDRNOTAVAIL; | |
156 | ||
3d396eb1 AK |
157 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
158 | ||
80922fbc | 159 | if (adapter->macaddr_set) |
3176ff3e | 160 | adapter->macaddr_set(adapter, addr->sa_data); |
3d396eb1 AK |
161 | |
162 | return 0; | |
163 | } | |
164 | ||
623621b0 DP |
165 | #define NETXEN_UNICAST_ADDR(port, index) \ |
166 | (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8)) | |
167 | #define NETXEN_MCAST_ADDR(port, index) \ | |
168 | (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8)) | |
169 | #define MAC_HI(addr) \ | |
170 | ((addr[2] << 16) | (addr[1] << 8) | (addr[0])) | |
171 | #define MAC_LO(addr) \ | |
172 | ((addr[5] << 16) | (addr[4] << 8) | (addr[3])) | |
173 | ||
174 | static int | |
175 | netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter) | |
176 | { | |
177 | u32 val = 0; | |
178 | u16 port = adapter->physical_port; | |
179 | u8 *addr = adapter->netdev->dev_addr; | |
180 | ||
181 | if (adapter->mc_enabled) | |
182 | return 0; | |
183 | ||
184 | netxen_nic_hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); | |
185 | val |= (1UL << (28+port)); | |
186 | netxen_nic_hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); | |
187 | ||
188 | /* add broadcast addr to filter */ | |
189 | val = 0xffffff; | |
190 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); | |
191 | netxen_crb_writelit_adapter(adapter, | |
192 | NETXEN_UNICAST_ADDR(port, 0)+4, val); | |
193 | ||
194 | /* add station addr to filter */ | |
195 | val = MAC_HI(addr); | |
196 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val); | |
197 | val = MAC_LO(addr); | |
198 | netxen_crb_writelit_adapter(adapter, | |
199 | NETXEN_UNICAST_ADDR(port, 1)+4, val); | |
200 | ||
201 | adapter->mc_enabled = 1; | |
202 | return 0; | |
203 | } | |
204 | ||
205 | static int | |
206 | netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter) | |
207 | { | |
208 | u32 val = 0; | |
209 | u16 port = adapter->physical_port; | |
210 | u8 *addr = adapter->netdev->dev_addr; | |
211 | ||
212 | if (!adapter->mc_enabled) | |
213 | return 0; | |
214 | ||
215 | netxen_nic_hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); | |
216 | val &= ~(1UL << (28+port)); | |
217 | netxen_nic_hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); | |
218 | ||
219 | val = MAC_HI(addr); | |
220 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); | |
221 | val = MAC_LO(addr); | |
222 | netxen_crb_writelit_adapter(adapter, | |
223 | NETXEN_UNICAST_ADDR(port, 0)+4, val); | |
224 | ||
225 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); | |
226 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); | |
227 | ||
228 | adapter->mc_enabled = 0; | |
229 | return 0; | |
230 | } | |
231 | ||
232 | static int | |
233 | netxen_nic_set_mcast_addr(struct netxen_adapter *adapter, | |
234 | int index, u8 *addr) | |
235 | { | |
236 | u32 hi = 0, lo = 0; | |
237 | u16 port = adapter->physical_port; | |
238 | ||
239 | lo = MAC_LO(addr); | |
240 | hi = MAC_HI(addr); | |
241 | ||
242 | netxen_crb_writelit_adapter(adapter, | |
243 | NETXEN_MCAST_ADDR(port, index), hi); | |
244 | netxen_crb_writelit_adapter(adapter, | |
245 | NETXEN_MCAST_ADDR(port, index)+4, lo); | |
246 | ||
247 | return 0; | |
248 | } | |
249 | ||
3d396eb1 AK |
250 | /* |
251 | * netxen_nic_set_multi - Multicast | |
252 | */ | |
253 | void netxen_nic_set_multi(struct net_device *netdev) | |
254 | { | |
3176ff3e | 255 | struct netxen_adapter *adapter = netdev_priv(netdev); |
3d396eb1 | 256 | struct dev_mc_list *mc_ptr; |
623621b0 DP |
257 | u8 null_addr[6]; |
258 | int index = 0; | |
259 | ||
260 | memset(null_addr, 0, 6); | |
3d396eb1 | 261 | |
3d396eb1 | 262 | if (netdev->flags & IFF_PROMISC) { |
623621b0 DP |
263 | |
264 | adapter->set_promisc(adapter, | |
265 | NETXEN_NIU_PROMISC_MODE); | |
266 | ||
267 | /* Full promiscuous mode */ | |
268 | netxen_nic_disable_mcast_filter(adapter); | |
269 | ||
270 | return; | |
271 | } | |
272 | ||
273 | if (netdev->mc_count == 0) { | |
274 | adapter->set_promisc(adapter, | |
275 | NETXEN_NIU_NON_PROMISC_MODE); | |
276 | netxen_nic_disable_mcast_filter(adapter); | |
277 | return; | |
278 | } | |
279 | ||
280 | adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE); | |
281 | if (netdev->flags & IFF_ALLMULTI || | |
282 | netdev->mc_count > adapter->max_mc_count) { | |
283 | netxen_nic_disable_mcast_filter(adapter); | |
284 | return; | |
3d396eb1 | 285 | } |
623621b0 DP |
286 | |
287 | netxen_nic_enable_mcast_filter(adapter); | |
288 | ||
289 | for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++) | |
290 | netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr); | |
291 | ||
292 | if (index != netdev->mc_count) | |
293 | printk(KERN_WARNING "%s: %s multicast address count mismatch\n", | |
294 | netxen_nic_driver_name, netdev->name); | |
295 | ||
296 | /* Clear out remaining addresses */ | |
297 | for (; index < adapter->max_mc_count; index++) | |
298 | netxen_nic_set_mcast_addr(adapter, index, null_addr); | |
3d396eb1 AK |
299 | } |
300 | ||
301 | /* | |
302 | * netxen_nic_change_mtu - Change the Maximum Transfer Unit | |
303 | * @returns 0 on success, negative on failure | |
304 | */ | |
305 | int netxen_nic_change_mtu(struct net_device *netdev, int mtu) | |
306 | { | |
3176ff3e | 307 | struct netxen_adapter *adapter = netdev_priv(netdev); |
3d396eb1 AK |
308 | int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE; |
309 | ||
310 | if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) { | |
311 | printk(KERN_ERR "%s: %s %d is not supported.\n", | |
312 | netxen_nic_driver_name, netdev->name, mtu); | |
313 | return -EINVAL; | |
314 | } | |
315 | ||
80922fbc | 316 | if (adapter->set_mtu) |
3176ff3e | 317 | adapter->set_mtu(adapter, mtu); |
3d396eb1 AK |
318 | netdev->mtu = mtu; |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
323 | /* | |
324 | * check if the firmware has been downloaded and ready to run and | |
325 | * setup the address for the descriptors in the adapter | |
326 | */ | |
327 | int netxen_nic_hw_resources(struct netxen_adapter *adapter) | |
328 | { | |
329 | struct netxen_hardware_context *hw = &adapter->ahw; | |
3d396eb1 AK |
330 | u32 state = 0; |
331 | void *addr; | |
332 | int loops = 0, err = 0; | |
333 | int ctx, ring; | |
3d396eb1 AK |
334 | struct netxen_recv_context *recv_ctx; |
335 | struct netxen_rcv_desc_ctx *rcv_desc; | |
595e3fb8 | 336 | int func_id = adapter->portnum; |
3d396eb1 | 337 | |
80922fbc | 338 | DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE, |
cb8011ad | 339 | PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE)); |
80922fbc | 340 | DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM, |
cb8011ad | 341 | pci_base_offset(adapter, NETXEN_CRB_CAM)); |
80922fbc | 342 | DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE, |
cb8011ad | 343 | pci_base_offset(adapter, NETXEN_CAM_RAM_BASE)); |
3d396eb1 | 344 | |
3d396eb1 AK |
345 | |
346 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
347 | DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n"); | |
348 | loops = 0; | |
349 | state = 0; | |
350 | /* Window 1 call */ | |
7830b22c | 351 | state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_RCVPEG_STATE)); |
3d396eb1 | 352 | while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) { |
96acb6eb | 353 | msleep(1); |
3d396eb1 AK |
354 | /* Window 1 call */ |
355 | state = readl(NETXEN_CRB_NORMALIZE(adapter, | |
7830b22c | 356 | CRB_RCVPEG_STATE)); |
3d396eb1 AK |
357 | loops++; |
358 | } | |
359 | if (loops >= 20) { | |
360 | printk(KERN_ERR "Rcv Peg initialization not complete:" | |
361 | "%x.\n", state); | |
362 | err = -EIO; | |
363 | return err; | |
364 | } | |
365 | } | |
2d1a3bbd | 366 | adapter->intr_scheme = readl( |
367 | NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW)); | |
443be796 DP |
368 | adapter->msi_mode = readl( |
369 | NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW)); | |
3d396eb1 | 370 | |
7830b22c DP |
371 | addr = pci_alloc_consistent(adapter->pdev, |
372 | sizeof(struct netxen_ring_ctx) + sizeof(uint32_t), | |
373 | &adapter->ctx_desc_phys_addr); | |
cb8011ad | 374 | |
3d396eb1 AK |
375 | if (addr == NULL) { |
376 | DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); | |
ed25ffa1 AK |
377 | err = -ENOMEM; |
378 | return err; | |
cb8011ad | 379 | } |
ed25ffa1 AK |
380 | memset(addr, 0, sizeof(struct netxen_ring_ctx)); |
381 | adapter->ctx_desc = (struct netxen_ring_ctx *)addr; | |
6c80b18d | 382 | adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum); |
a608ab9c AV |
383 | adapter->ctx_desc->cmd_consumer_offset = |
384 | cpu_to_le64(adapter->ctx_desc_phys_addr + | |
385 | sizeof(struct netxen_ring_ctx)); | |
f305f789 | 386 | adapter->cmd_consumer = (__le32 *) (((char *)addr) + |
ed25ffa1 AK |
387 | sizeof(struct netxen_ring_ctx)); |
388 | ||
7830b22c | 389 | addr = pci_alloc_consistent(adapter->pdev, |
9de06610 AK |
390 | sizeof(struct cmd_desc_type0) * |
391 | adapter->max_tx_desc_count, | |
7830b22c | 392 | &hw->cmd_desc_phys_addr); |
cb8011ad | 393 | |
ed25ffa1 AK |
394 | if (addr == NULL) { |
395 | DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); | |
396 | netxen_free_hw_resources(adapter); | |
cb8011ad | 397 | return -ENOMEM; |
3d396eb1 AK |
398 | } |
399 | ||
a608ab9c AV |
400 | adapter->ctx_desc->cmd_ring_addr = |
401 | cpu_to_le64(hw->cmd_desc_phys_addr); | |
402 | adapter->ctx_desc->cmd_ring_size = | |
403 | cpu_to_le32(adapter->max_tx_desc_count); | |
3d396eb1 AK |
404 | |
405 | hw->cmd_desc_head = (struct cmd_desc_type0 *)addr; | |
406 | ||
407 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
408 | recv_ctx = &adapter->recv_ctx[ctx]; | |
409 | ||
410 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { | |
411 | rcv_desc = &recv_ctx->rcv_desc[ring]; | |
7830b22c | 412 | addr = pci_alloc_consistent(adapter->pdev, |
cb8011ad | 413 | RCV_DESC_RINGSIZE, |
7830b22c | 414 | &rcv_desc->phys_addr); |
3d396eb1 AK |
415 | if (addr == NULL) { |
416 | DPRINTK(ERR, "bad return from " | |
417 | "pci_alloc_consistent\n"); | |
418 | netxen_free_hw_resources(adapter); | |
419 | err = -ENOMEM; | |
420 | return err; | |
421 | } | |
422 | rcv_desc->desc_head = (struct rcv_desc *)addr; | |
a608ab9c AV |
423 | adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr = |
424 | cpu_to_le64(rcv_desc->phys_addr); | |
ed25ffa1 | 425 | adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size = |
a608ab9c | 426 | cpu_to_le32(rcv_desc->max_rx_desc_count); |
7830b22c DP |
427 | rcv_desc->crb_rcv_producer = |
428 | recv_crb_registers[adapter->portnum]. | |
429 | crb_rcv_producer[ring]; | |
3d396eb1 AK |
430 | } |
431 | ||
7830b22c DP |
432 | addr = pci_alloc_consistent(adapter->pdev, STATUS_DESC_RINGSIZE, |
433 | &recv_ctx->rcv_status_desc_phys_addr); | |
3d396eb1 AK |
434 | if (addr == NULL) { |
435 | DPRINTK(ERR, "bad return from" | |
436 | " pci_alloc_consistent\n"); | |
437 | netxen_free_hw_resources(adapter); | |
438 | err = -ENOMEM; | |
439 | return err; | |
440 | } | |
441 | recv_ctx->rcv_status_desc_head = (struct status_desc *)addr; | |
a608ab9c AV |
442 | adapter->ctx_desc->sts_ring_addr = |
443 | cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr); | |
444 | adapter->ctx_desc->sts_ring_size = | |
445 | cpu_to_le32(adapter->max_rx_desc_count); | |
7830b22c DP |
446 | recv_ctx->crb_sts_consumer = |
447 | recv_crb_registers[adapter->portnum].crb_sts_consumer; | |
3d396eb1 | 448 | |
3d396eb1 AK |
449 | } |
450 | /* Window = 1 */ | |
ed25ffa1 AK |
451 | |
452 | writel(lower32(adapter->ctx_desc_phys_addr), | |
595e3fb8 | 453 | NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id))); |
ed25ffa1 | 454 | writel(upper32(adapter->ctx_desc_phys_addr), |
595e3fb8 MT |
455 | NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id))); |
456 | writel(NETXEN_CTX_SIGNATURE | func_id, | |
457 | NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id))); | |
3d396eb1 AK |
458 | return err; |
459 | } | |
460 | ||
461 | void netxen_free_hw_resources(struct netxen_adapter *adapter) | |
462 | { | |
463 | struct netxen_recv_context *recv_ctx; | |
464 | struct netxen_rcv_desc_ctx *rcv_desc; | |
465 | int ctx, ring; | |
466 | ||
ed25ffa1 | 467 | if (adapter->ctx_desc != NULL) { |
7830b22c | 468 | pci_free_consistent(adapter->pdev, |
ed25ffa1 AK |
469 | sizeof(struct netxen_ring_ctx) + |
470 | sizeof(uint32_t), | |
471 | adapter->ctx_desc, | |
472 | adapter->ctx_desc_phys_addr); | |
473 | adapter->ctx_desc = NULL; | |
474 | } | |
475 | ||
3d396eb1 | 476 | if (adapter->ahw.cmd_desc_head != NULL) { |
7830b22c | 477 | pci_free_consistent(adapter->pdev, |
3d396eb1 AK |
478 | sizeof(struct cmd_desc_type0) * |
479 | adapter->max_tx_desc_count, | |
480 | adapter->ahw.cmd_desc_head, | |
481 | adapter->ahw.cmd_desc_phys_addr); | |
482 | adapter->ahw.cmd_desc_head = NULL; | |
483 | } | |
484 | ||
485 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
486 | recv_ctx = &adapter->recv_ctx[ctx]; | |
487 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { | |
488 | rcv_desc = &recv_ctx->rcv_desc[ring]; | |
489 | ||
490 | if (rcv_desc->desc_head != NULL) { | |
7830b22c | 491 | pci_free_consistent(adapter->pdev, |
3d396eb1 AK |
492 | RCV_DESC_RINGSIZE, |
493 | rcv_desc->desc_head, | |
494 | rcv_desc->phys_addr); | |
495 | rcv_desc->desc_head = NULL; | |
496 | } | |
497 | } | |
498 | ||
499 | if (recv_ctx->rcv_status_desc_head != NULL) { | |
7830b22c | 500 | pci_free_consistent(adapter->pdev, |
3d396eb1 AK |
501 | STATUS_DESC_RINGSIZE, |
502 | recv_ctx->rcv_status_desc_head, | |
503 | recv_ctx-> | |
504 | rcv_status_desc_phys_addr); | |
505 | recv_ctx->rcv_status_desc_head = NULL; | |
506 | } | |
507 | } | |
508 | } | |
509 | ||
510 | void netxen_tso_check(struct netxen_adapter *adapter, | |
511 | struct cmd_desc_type0 *desc, struct sk_buff *skb) | |
512 | { | |
513 | if (desc->mss) { | |
c9bdd4b5 | 514 | desc->total_hdr_length = (sizeof(struct ethhdr) + |
ab6a5bb6 | 515 | ip_hdrlen(skb) + tcp_hdrlen(skb)); |
ed25ffa1 | 516 | netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO); |
c75e86b4 | 517 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 | 518 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) { |
ed25ffa1 | 519 | netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT); |
eddc9ec5 | 520 | } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
ed25ffa1 | 521 | netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT); |
3d396eb1 AK |
522 | } else { |
523 | return; | |
524 | } | |
525 | } | |
ea2ae17d | 526 | desc->tcp_hdr_offset = skb_transport_offset(skb); |
bbe735e4 | 527 | desc->ip_hdr_offset = skb_network_offset(skb); |
3d396eb1 AK |
528 | } |
529 | ||
530 | int netxen_is_flash_supported(struct netxen_adapter *adapter) | |
531 | { | |
532 | const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 }; | |
533 | int addr, val01, val02, i, j; | |
534 | ||
535 | /* if the flash size less than 4Mb, make huge war cry and die */ | |
536 | for (j = 1; j < 4; j++) { | |
cb8011ad | 537 | addr = j * NETXEN_NIC_WINDOW_MARGIN; |
ff8ac609 | 538 | for (i = 0; i < ARRAY_SIZE(locs); i++) { |
3d396eb1 AK |
539 | if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0 |
540 | && netxen_rom_fast_read(adapter, (addr + locs[i]), | |
541 | &val02) == 0) { | |
542 | if (val01 == val02) | |
543 | return -1; | |
544 | } else | |
545 | return -1; | |
546 | } | |
547 | } | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, | |
f305f789 | 553 | int size, __le32 * buf) |
3d396eb1 AK |
554 | { |
555 | int i, addr; | |
f305f789 AV |
556 | __le32 *ptr32; |
557 | u32 v; | |
3d396eb1 AK |
558 | |
559 | addr = base; | |
560 | ptr32 = buf; | |
561 | for (i = 0; i < size / sizeof(u32); i++) { | |
f305f789 | 562 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) |
3d396eb1 | 563 | return -1; |
f305f789 | 564 | *ptr32 = cpu_to_le32(v); |
3d396eb1 AK |
565 | ptr32++; |
566 | addr += sizeof(u32); | |
567 | } | |
568 | if ((char *)buf + size > (char *)ptr32) { | |
f305f789 AV |
569 | __le32 local; |
570 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) | |
3d396eb1 | 571 | return -1; |
f305f789 | 572 | local = cpu_to_le32(v); |
3d396eb1 AK |
573 | memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
f305f789 | 579 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]) |
3d396eb1 | 580 | { |
f305f789 | 581 | __le32 *pmac = (__le32 *) & mac[0]; |
3d396eb1 AK |
582 | |
583 | if (netxen_get_flash_block(adapter, | |
0d04761d | 584 | NETXEN_USER_START + |
3d396eb1 AK |
585 | offsetof(struct netxen_new_user_info, |
586 | mac_addr), | |
587 | FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) { | |
588 | return -1; | |
589 | } | |
f305f789 | 590 | if (*mac == cpu_to_le64(~0ULL)) { |
3d396eb1 | 591 | if (netxen_get_flash_block(adapter, |
0d04761d | 592 | NETXEN_USER_START_OLD + |
3d396eb1 AK |
593 | offsetof(struct netxen_user_old_info, |
594 | mac_addr), | |
595 | FLASH_NUM_PORTS * sizeof(u64), | |
596 | pmac) == -1) | |
597 | return -1; | |
f305f789 | 598 | if (*mac == cpu_to_le64(~0ULL)) |
3d396eb1 AK |
599 | return -1; |
600 | } | |
601 | return 0; | |
602 | } | |
603 | ||
604 | /* | |
605 | * Changes the CRB window to the specified window. | |
606 | */ | |
607 | void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw) | |
608 | { | |
609 | void __iomem *offset; | |
610 | u32 tmp; | |
611 | int count = 0; | |
612 | ||
613 | if (adapter->curr_window == wndw) | |
614 | return; | |
13ba9c77 | 615 | switch(adapter->ahw.pci_func) { |
3176ff3e MT |
616 | case 0: |
617 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
618 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW)); | |
619 | break; | |
620 | case 1: | |
621 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
622 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1)); | |
623 | break; | |
624 | case 2: | |
625 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
626 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2)); | |
627 | break; | |
628 | case 3: | |
629 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
630 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3)); | |
631 | break; | |
632 | default: | |
5bc51424 | 633 | printk(KERN_INFO "Changing the window for PCI function " |
13ba9c77 | 634 | "%d\n", adapter->ahw.pci_func); |
3176ff3e MT |
635 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
636 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW)); | |
637 | break; | |
638 | } | |
3d396eb1 AK |
639 | /* |
640 | * Move the CRB window. | |
641 | * We need to write to the "direct access" region of PCI | |
642 | * to avoid a race condition where the window register has | |
643 | * not been successfully written across CRB before the target | |
644 | * register address is received by PCI. The direct region bypasses | |
645 | * the CRB bus. | |
646 | */ | |
3d396eb1 AK |
647 | |
648 | if (wndw & 0x1) | |
649 | wndw = NETXEN_WINDOW_ONE; | |
650 | ||
651 | writel(wndw, offset); | |
652 | ||
653 | /* MUST make sure window is set before we forge on... */ | |
654 | while ((tmp = readl(offset)) != wndw) { | |
655 | printk(KERN_WARNING "%s: %s WARNING: CRB window value not " | |
656 | "registered properly: 0x%08x.\n", | |
657 | netxen_nic_driver_name, __FUNCTION__, tmp); | |
658 | mdelay(1); | |
659 | if (count >= 10) | |
660 | break; | |
661 | count++; | |
662 | } | |
663 | ||
6c80b18d MT |
664 | if (wndw == NETXEN_WINDOW_ONE) |
665 | adapter->curr_window = 1; | |
666 | else | |
667 | adapter->curr_window = 0; | |
3d396eb1 AK |
668 | } |
669 | ||
96acb6eb | 670 | int netxen_load_firmware(struct netxen_adapter *adapter) |
3d396eb1 AK |
671 | { |
672 | int i; | |
e0e20a1a LCMT |
673 | u32 data, size = 0; |
674 | u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE; | |
3d396eb1 AK |
675 | u64 off; |
676 | void __iomem *addr; | |
677 | ||
678 | size = NETXEN_FIRMWARE_LEN; | |
679 | writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST)); | |
680 | ||
681 | for (i = 0; i < size; i++) { | |
96acb6eb DP |
682 | int retries = 10; |
683 | if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) | |
684 | return -EIO; | |
685 | ||
cb8011ad AK |
686 | off = netxen_nic_pci_set_window(adapter, memaddr); |
687 | addr = pci_base_offset(adapter, off); | |
3d396eb1 | 688 | writel(data, addr); |
96acb6eb DP |
689 | do { |
690 | if (readl(addr) == data) | |
691 | break; | |
692 | msleep(100); | |
693 | writel(data, addr); | |
694 | } while (--retries); | |
695 | if (!retries) { | |
696 | printk(KERN_ERR "%s: firmware load aborted, write failed at 0x%x\n", | |
697 | netxen_nic_driver_name, memaddr); | |
698 | return -EIO; | |
699 | } | |
3d396eb1 AK |
700 | flashaddr += 4; |
701 | memaddr += 4; | |
702 | } | |
703 | udelay(100); | |
704 | /* make sure Casper is powered on */ | |
705 | writel(0x3fff, | |
706 | NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL)); | |
707 | writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST)); | |
708 | ||
96acb6eb | 709 | return 0; |
3d396eb1 AK |
710 | } |
711 | ||
712 | int | |
713 | netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
714 | int len) | |
715 | { | |
716 | void __iomem *addr; | |
717 | ||
718 | if (ADDR_IN_WINDOW1(off)) { | |
719 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
720 | } else { /* Window 0 */ | |
cb8011ad | 721 | addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
722 | netxen_nic_pci_change_crbwindow(adapter, 0); |
723 | } | |
724 | ||
725 | DPRINTK(INFO, "writing to base %lx offset %llx addr %p" | |
726 | " data %llx len %d\n", | |
cb8011ad | 727 | pci_base(adapter, off), off, addr, |
3d396eb1 | 728 | *(unsigned long long *)data, len); |
cb8011ad AK |
729 | if (!addr) { |
730 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
731 | return 1; | |
732 | } | |
733 | ||
3d396eb1 AK |
734 | switch (len) { |
735 | case 1: | |
736 | writeb(*(u8 *) data, addr); | |
737 | break; | |
738 | case 2: | |
739 | writew(*(u16 *) data, addr); | |
740 | break; | |
741 | case 4: | |
742 | writel(*(u32 *) data, addr); | |
743 | break; | |
744 | case 8: | |
745 | writeq(*(u64 *) data, addr); | |
746 | break; | |
747 | default: | |
748 | DPRINTK(INFO, | |
749 | "writing data %lx to offset %llx, num words=%d\n", | |
750 | *(unsigned long *)data, off, (len >> 3)); | |
751 | ||
752 | netxen_nic_hw_block_write64((u64 __iomem *) data, addr, | |
753 | (len >> 3)); | |
754 | break; | |
755 | } | |
756 | if (!ADDR_IN_WINDOW1(off)) | |
757 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
762 | int | |
763 | netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
764 | int len) | |
765 | { | |
766 | void __iomem *addr; | |
767 | ||
768 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ | |
769 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
770 | } else { /* Window 0 */ | |
cb8011ad | 771 | addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
772 | netxen_nic_pci_change_crbwindow(adapter, 0); |
773 | } | |
774 | ||
775 | DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", | |
cb8011ad AK |
776 | pci_base(adapter, off), off, addr); |
777 | if (!addr) { | |
778 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
779 | return 1; | |
780 | } | |
3d396eb1 AK |
781 | switch (len) { |
782 | case 1: | |
783 | *(u8 *) data = readb(addr); | |
784 | break; | |
785 | case 2: | |
786 | *(u16 *) data = readw(addr); | |
787 | break; | |
788 | case 4: | |
789 | *(u32 *) data = readl(addr); | |
790 | break; | |
791 | case 8: | |
792 | *(u64 *) data = readq(addr); | |
793 | break; | |
794 | default: | |
795 | netxen_nic_hw_block_read64((u64 __iomem *) data, addr, | |
796 | (len >> 3)); | |
797 | break; | |
798 | } | |
799 | DPRINTK(INFO, "read %lx\n", *(unsigned long *)data); | |
800 | ||
801 | if (!ADDR_IN_WINDOW1(off)) | |
802 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
807 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val) | |
808 | { /* Only for window 1 */ | |
809 | void __iomem *addr; | |
810 | ||
811 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
812 | DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n", | |
80922fbc | 813 | pci_base(adapter, off), off, addr, val); |
3d396eb1 AK |
814 | writel(val, addr); |
815 | ||
816 | } | |
817 | ||
818 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off) | |
819 | { /* Only for window 1 */ | |
820 | void __iomem *addr; | |
821 | int val; | |
822 | ||
823 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
824 | DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", | |
80922fbc | 825 | pci_base(adapter, off), off, addr); |
3d396eb1 AK |
826 | val = readl(addr); |
827 | writel(val, addr); | |
828 | ||
829 | return val; | |
830 | } | |
831 | ||
832 | /* Change the window to 0, write and change back to window 1. */ | |
833 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value) | |
834 | { | |
835 | void __iomem *addr; | |
836 | ||
837 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
71bd7877 | 838 | addr = pci_base_offset(adapter, index); |
3d396eb1 AK |
839 | writel(value, addr); |
840 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
841 | } | |
842 | ||
843 | /* Change the window to 0, read and change back to window 1. */ | |
844 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value) | |
845 | { | |
846 | void __iomem *addr; | |
847 | ||
71bd7877 | 848 | addr = pci_base_offset(adapter, index); |
3d396eb1 AK |
849 | |
850 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
851 | *value = readl(addr); | |
852 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
853 | } | |
854 | ||
4790654c | 855 | static int netxen_pci_set_window_warning_count; |
3d396eb1 | 856 | |
993fb90c AB |
857 | static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter, |
858 | unsigned long long addr) | |
3d396eb1 AK |
859 | { |
860 | static int ddr_mn_window = -1; | |
861 | static int qdr_sn_window = -1; | |
862 | int window; | |
863 | ||
864 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { | |
865 | /* DDR network side */ | |
866 | addr -= NETXEN_ADDR_DDR_NET; | |
867 | window = (addr >> 25) & 0x3ff; | |
868 | if (ddr_mn_window != window) { | |
869 | ddr_mn_window = window; | |
cb8011ad AK |
870 | writel(window, PCI_OFFSET_SECOND_RANGE(adapter, |
871 | NETXEN_PCIX_PH_REG | |
3052246c | 872 | (PCIX_MN_WINDOW(adapter->ahw.pci_func)))); |
3d396eb1 | 873 | /* MUST make sure window is set before we forge on... */ |
cb8011ad AK |
874 | readl(PCI_OFFSET_SECOND_RANGE(adapter, |
875 | NETXEN_PCIX_PH_REG | |
3052246c | 876 | (PCIX_MN_WINDOW(adapter->ahw.pci_func)))); |
3d396eb1 | 877 | } |
cb8011ad | 878 | addr -= (window * NETXEN_WINDOW_ONE); |
3d396eb1 AK |
879 | addr += NETXEN_PCI_DDR_NET; |
880 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { | |
881 | addr -= NETXEN_ADDR_OCM0; | |
882 | addr += NETXEN_PCI_OCM0; | |
883 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { | |
884 | addr -= NETXEN_ADDR_OCM1; | |
885 | addr += NETXEN_PCI_OCM1; | |
886 | } else | |
887 | if (ADDR_IN_RANGE | |
888 | (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) { | |
889 | /* QDR network side */ | |
890 | addr -= NETXEN_ADDR_QDR_NET; | |
891 | window = (addr >> 22) & 0x3f; | |
892 | if (qdr_sn_window != window) { | |
893 | qdr_sn_window = window; | |
cb8011ad AK |
894 | writel((window << 22), |
895 | PCI_OFFSET_SECOND_RANGE(adapter, | |
896 | NETXEN_PCIX_PH_REG | |
3052246c | 897 | (PCIX_SN_WINDOW(adapter->ahw.pci_func)))); |
3d396eb1 | 898 | /* MUST make sure window is set before we forge on... */ |
cb8011ad AK |
899 | readl(PCI_OFFSET_SECOND_RANGE(adapter, |
900 | NETXEN_PCIX_PH_REG | |
3052246c | 901 | (PCIX_SN_WINDOW(adapter->ahw.pci_func)))); |
3d396eb1 AK |
902 | } |
903 | addr -= (window * 0x400000); | |
904 | addr += NETXEN_PCI_QDR_NET; | |
905 | } else { | |
906 | /* | |
907 | * peg gdb frequently accesses memory that doesn't exist, | |
908 | * this limits the chit chat so debugging isn't slowed down. | |
909 | */ | |
910 | if ((netxen_pci_set_window_warning_count++ < 8) | |
911 | || (netxen_pci_set_window_warning_count % 64 == 0)) | |
912 | printk("%s: Warning:netxen_nic_pci_set_window()" | |
913 | " Unknown address range!\n", | |
914 | netxen_nic_driver_name); | |
915 | ||
916 | } | |
917 | return addr; | |
918 | } | |
919 | ||
993fb90c | 920 | #if 0 |
13ba9c77 MT |
921 | int |
922 | netxen_nic_erase_pxe(struct netxen_adapter *adapter) | |
923 | { | |
0d04761d | 924 | if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) { |
4790654c | 925 | printk(KERN_ERR "%s: erase pxe failed\n", |
13ba9c77 MT |
926 | netxen_nic_driver_name); |
927 | return -1; | |
928 | } | |
929 | return 0; | |
930 | } | |
993fb90c | 931 | #endif /* 0 */ |
13ba9c77 | 932 | |
3d396eb1 AK |
933 | int netxen_nic_get_board_info(struct netxen_adapter *adapter) |
934 | { | |
935 | int rv = 0; | |
0d04761d | 936 | int addr = NETXEN_BRDCFG_START; |
3d396eb1 AK |
937 | struct netxen_board_info *boardinfo; |
938 | int index; | |
939 | u32 *ptr32; | |
940 | ||
941 | boardinfo = &adapter->ahw.boardcfg; | |
942 | ptr32 = (u32 *) boardinfo; | |
943 | ||
944 | for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32); | |
945 | index++) { | |
946 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { | |
947 | return -EIO; | |
948 | } | |
949 | ptr32++; | |
950 | addr += sizeof(u32); | |
951 | } | |
952 | if (boardinfo->magic != NETXEN_BDINFO_MAGIC) { | |
953 | printk("%s: ERROR reading %s board config." | |
954 | " Read %x, expected %x\n", netxen_nic_driver_name, | |
955 | netxen_nic_driver_name, | |
956 | boardinfo->magic, NETXEN_BDINFO_MAGIC); | |
957 | rv = -1; | |
958 | } | |
959 | if (boardinfo->header_version != NETXEN_BDINFO_VERSION) { | |
960 | printk("%s: Unknown board config version." | |
961 | " Read %x, expected %x\n", netxen_nic_driver_name, | |
962 | boardinfo->header_version, NETXEN_BDINFO_VERSION); | |
963 | rv = -1; | |
964 | } | |
965 | ||
966 | DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type); | |
967 | switch ((netxen_brdtype_t) boardinfo->board_type) { | |
968 | case NETXEN_BRDTYPE_P2_SB35_4G: | |
969 | adapter->ahw.board_type = NETXEN_NIC_GBE; | |
970 | break; | |
971 | case NETXEN_BRDTYPE_P2_SB31_10G: | |
972 | case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: | |
973 | case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: | |
974 | case NETXEN_BRDTYPE_P2_SB31_10G_CX4: | |
975 | adapter->ahw.board_type = NETXEN_NIC_XGBE; | |
976 | break; | |
977 | case NETXEN_BRDTYPE_P1_BD: | |
978 | case NETXEN_BRDTYPE_P1_SB: | |
979 | case NETXEN_BRDTYPE_P1_SMAX: | |
980 | case NETXEN_BRDTYPE_P1_SOCK: | |
981 | adapter->ahw.board_type = NETXEN_NIC_GBE; | |
982 | break; | |
983 | default: | |
984 | printk("%s: Unknown(%x)\n", netxen_nic_driver_name, | |
985 | boardinfo->board_type); | |
986 | break; | |
987 | } | |
988 | ||
989 | return rv; | |
990 | } | |
991 | ||
992 | /* NIU access sections */ | |
993 | ||
3176ff3e | 994 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 995 | { |
3d396eb1 | 996 | netxen_nic_write_w0(adapter, |
3276fbad DP |
997 | NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), |
998 | new_mtu); | |
3d396eb1 AK |
999 | return 0; |
1000 | } | |
1001 | ||
3176ff3e | 1002 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 1003 | { |
3d396eb1 | 1004 | new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE; |
3276fbad | 1005 | if (adapter->physical_port == 0) |
4790654c | 1006 | netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, |
595e3fb8 | 1007 | new_mtu); |
4790654c | 1008 | else |
595e3fb8 MT |
1009 | netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, |
1010 | new_mtu); | |
3d396eb1 AK |
1011 | return 0; |
1012 | } | |
1013 | ||
1014 | void netxen_nic_init_niu_gb(struct netxen_adapter *adapter) | |
1015 | { | |
3276fbad | 1016 | netxen_niu_gbe_init_port(adapter, adapter->physical_port); |
3d396eb1 AK |
1017 | } |
1018 | ||
1019 | void | |
1020 | netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off, | |
1021 | int data) | |
1022 | { | |
1023 | void __iomem *addr; | |
1024 | ||
1025 | if (ADDR_IN_WINDOW1(off)) { | |
1026 | writel(data, NETXEN_CRB_NORMALIZE(adapter, off)); | |
1027 | } else { | |
1028 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
71bd7877 | 1029 | addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
1030 | writel(data, addr); |
1031 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
1032 | } | |
1033 | } | |
1034 | ||
3176ff3e | 1035 | void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) |
3d396eb1 | 1036 | { |
a608ab9c AV |
1037 | __u32 status; |
1038 | __u32 autoneg; | |
1039 | __u32 mode; | |
3d396eb1 AK |
1040 | |
1041 | netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode); | |
1042 | if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */ | |
80922fbc AK |
1043 | if (adapter->phy_read |
1044 | && adapter-> | |
13ba9c77 | 1045 | phy_read(adapter, |
3d396eb1 AK |
1046 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, |
1047 | &status) == 0) { | |
1048 | if (netxen_get_phy_link(status)) { | |
1049 | switch (netxen_get_phy_speed(status)) { | |
1050 | case 0: | |
3176ff3e | 1051 | adapter->link_speed = SPEED_10; |
3d396eb1 AK |
1052 | break; |
1053 | case 1: | |
3176ff3e | 1054 | adapter->link_speed = SPEED_100; |
3d396eb1 AK |
1055 | break; |
1056 | case 2: | |
3176ff3e | 1057 | adapter->link_speed = SPEED_1000; |
3d396eb1 AK |
1058 | break; |
1059 | default: | |
3176ff3e | 1060 | adapter->link_speed = -1; |
3d396eb1 AK |
1061 | break; |
1062 | } | |
1063 | switch (netxen_get_phy_duplex(status)) { | |
1064 | case 0: | |
3176ff3e | 1065 | adapter->link_duplex = DUPLEX_HALF; |
3d396eb1 AK |
1066 | break; |
1067 | case 1: | |
3176ff3e | 1068 | adapter->link_duplex = DUPLEX_FULL; |
3d396eb1 AK |
1069 | break; |
1070 | default: | |
3176ff3e | 1071 | adapter->link_duplex = -1; |
3d396eb1 AK |
1072 | break; |
1073 | } | |
80922fbc AK |
1074 | if (adapter->phy_read |
1075 | && adapter-> | |
13ba9c77 | 1076 | phy_read(adapter, |
3d396eb1 | 1077 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, |
ed25ffa1 | 1078 | &autoneg) != 0) |
3176ff3e | 1079 | adapter->link_autoneg = autoneg; |
3d396eb1 AK |
1080 | } else |
1081 | goto link_down; | |
1082 | } else { | |
1083 | link_down: | |
3176ff3e MT |
1084 | adapter->link_speed = -1; |
1085 | adapter->link_duplex = -1; | |
3d396eb1 AK |
1086 | } |
1087 | } | |
1088 | } | |
1089 | ||
1090 | void netxen_nic_flash_print(struct netxen_adapter *adapter) | |
1091 | { | |
3d396eb1 AK |
1092 | u32 fw_major = 0; |
1093 | u32 fw_minor = 0; | |
1094 | u32 fw_build = 0; | |
cb8011ad | 1095 | char brd_name[NETXEN_MAX_SHORT_NAME]; |
8d74849b HH |
1096 | char serial_num[32]; |
1097 | int i, addr; | |
6d1495f2 | 1098 | __le32 *ptr32; |
3d396eb1 AK |
1099 | |
1100 | struct netxen_board_info *board_info = &(adapter->ahw.boardcfg); | |
dcd56fdb DP |
1101 | |
1102 | adapter->driver_mismatch = 0; | |
1103 | ||
1104 | ptr32 = (u32 *)&serial_num; | |
1105 | addr = NETXEN_USER_START + | |
1106 | offsetof(struct netxen_new_user_info, serial_num); | |
1107 | for (i = 0; i < 8; i++) { | |
1108 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { | |
1109 | printk("%s: ERROR reading %s board userarea.\n", | |
1110 | netxen_nic_driver_name, | |
1111 | netxen_nic_driver_name); | |
1112 | adapter->driver_mismatch = 1; | |
1113 | return; | |
cb8011ad | 1114 | } |
dcd56fdb DP |
1115 | ptr32++; |
1116 | addr += sizeof(u32); | |
1117 | } | |
1118 | ||
1119 | fw_major = readl(NETXEN_CRB_NORMALIZE(adapter, | |
1120 | NETXEN_FW_VERSION_MAJOR)); | |
1121 | fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter, | |
1122 | NETXEN_FW_VERSION_MINOR)); | |
1123 | fw_build = | |
1124 | readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB)); | |
8d74849b | 1125 | |
dcd56fdb | 1126 | if (adapter->portnum == 0) { |
cb8011ad AK |
1127 | get_brd_name_by_type(board_info->board_type, brd_name); |
1128 | ||
1129 | printk("NetXen %s Board S/N %s Chip id 0x%x\n", | |
dcd56fdb DP |
1130 | brd_name, serial_num, board_info->chip_id); |
1131 | printk("NetXen Firmware version %d.%d.%d\n", fw_major, | |
1132 | fw_minor, fw_build); | |
3d396eb1 | 1133 | } |
dcd56fdb | 1134 | |
3d396eb1 | 1135 | if (fw_major != _NETXEN_NIC_LINUX_MAJOR) { |
3d396eb1 AK |
1136 | adapter->driver_mismatch = 1; |
1137 | } | |
90f8b1d2 AK |
1138 | if (fw_minor != _NETXEN_NIC_LINUX_MINOR && |
1139 | fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) { | |
3d396eb1 AK |
1140 | adapter->driver_mismatch = 1; |
1141 | } | |
dcd56fdb DP |
1142 | if (adapter->driver_mismatch) { |
1143 | printk(KERN_ERR "%s: driver and firmware version mismatch\n", | |
1144 | adapter->netdev->name); | |
1145 | return; | |
1146 | } | |
1147 | ||
1148 | switch (adapter->ahw.board_type) { | |
1149 | case NETXEN_NIC_GBE: | |
1150 | dev_info(&adapter->pdev->dev, "%s: GbE port initialized\n", | |
1151 | adapter->netdev->name); | |
1152 | break; | |
1153 | case NETXEN_NIC_XGBE: | |
1154 | dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n", | |
1155 | adapter->netdev->name); | |
1156 | break; | |
1157 | } | |
3d396eb1 AK |
1158 | } |
1159 |