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bnx2: Update version to 2.0.2.
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3d396eb1 3 * All rights reserved.
80922fbc 4 *
3d396eb1
AK		 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
cb8011ad 9 *
3d396eb1
AK		 10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
cb8011ad 14 *
3d396eb1
AK		 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
80922fbc 19 *
3d396eb1
AK		 20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
80922fbc 22 *
3d396eb1
AK		 23 * Contact Information:
24 * info@netxen.com
5d242f1c
DP		 25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
3d396eb1
AK		 28 *
29 */
30
31#include "netxen_nic.h"
32#include "netxen_nic_hw.h"
33#include "netxen_nic_phan_reg.h"
34
c9bdd4b5
ACM		 35#include <net/ip.h>
36
3ce06a32
DP		 37#define MASK(n) ((1ULL<<(n))-1)
38#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
39#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
40#define MS_WIN(addr) (addr & 0x0ffc0000)
41
42#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
43
44#define CRB_BLK(off) ((off >> 20) & 0x3f)
45#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
46#define CRB_WINDOW_2M (0x130060)
47#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
48#define CRB_INDIRECT_2M (0x1e0000UL)
49
e98e3350
DP		 50#ifndef readq
51static inline u64 readq(void __iomem *addr)
52{
53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
54}
55#endif
56
57#ifndef writeq
58static inline void writeq(u64 val, void __iomem *addr)
59{
60 writel(((u32) (val)), (addr));
61 writel(((u32) (val >> 32)), (addr + 4));
62}
63#endif
64
1fbe6323
DP		 65#define ADDR_IN_RANGE(addr, low, high) \
66 (((addr) < (high)) && ((addr) >= (low)))
67
68#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
69 ((adapter)->ahw.pci_base0 + (off))
70#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
71 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
72#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
73 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
74
75static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
76 unsigned long off)
77{
78 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
79 return PCI_OFFSET_FIRST_RANGE(adapter, off);
80
81 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
82 return PCI_OFFSET_SECOND_RANGE(adapter, off);
83
84 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
85 return PCI_OFFSET_THIRD_RANGE(adapter, off);
86
87 return NULL;
88}
89
3ce06a32 90#define CRB_WIN_LOCK_TIMEOUT 100000000
ea7eaa39
DP		 91static crb_128M_2M_block_map_t
92crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
3ce06a32
DP		 93 {{{0, 0, 0, 0} } }, /* 0: PCI */
94 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
95 {1, 0x0110000, 0x0120000, 0x130000},
96 {1, 0x0120000, 0x0122000, 0x124000},
97 {1, 0x0130000, 0x0132000, 0x126000},
98 {1, 0x0140000, 0x0142000, 0x128000},
99 {1, 0x0150000, 0x0152000, 0x12a000},
100 {1, 0x0160000, 0x0170000, 0x110000},
101 {1, 0x0170000, 0x0172000, 0x12e000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {1, 0x01e0000, 0x01e0800, 0x122000},
109 {0, 0x0000000, 0x0000000, 0x000000} } },
110 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
111 {{{0, 0, 0, 0} } }, /* 3: */
112 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
113 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
114 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
115 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
116 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {1, 0x08f0000, 0x08f2000, 0x172000} } },
132 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {1, 0x09f0000, 0x09f2000, 0x176000} } },
148 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
164 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
180 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
181 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
182 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
183 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
184 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
185 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
186 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
187 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
188 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
189 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
190 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
191 {{{0, 0, 0, 0} } }, /* 23: */
192 {{{0, 0, 0, 0} } }, /* 24: */
193 {{{0, 0, 0, 0} } }, /* 25: */
194 {{{0, 0, 0, 0} } }, /* 26: */
195 {{{0, 0, 0, 0} } }, /* 27: */
196 {{{0, 0, 0, 0} } }, /* 28: */
197 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
198 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
199 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
200 {{{0} } }, /* 32: PCI */
201 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
202 {1, 0x2110000, 0x2120000, 0x130000},
203 {1, 0x2120000, 0x2122000, 0x124000},
204 {1, 0x2130000, 0x2132000, 0x126000},
205 {1, 0x2140000, 0x2142000, 0x128000},
206 {1, 0x2150000, 0x2152000, 0x12a000},
207 {1, 0x2160000, 0x2170000, 0x110000},
208 {1, 0x2170000, 0x2172000, 0x12e000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000},
215 {0, 0x0000000, 0x0000000, 0x000000},
216 {0, 0x0000000, 0x0000000, 0x000000} } },
217 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
218 {{{0} } }, /* 35: */
219 {{{0} } }, /* 36: */
220 {{{0} } }, /* 37: */
221 {{{0} } }, /* 38: */
222 {{{0} } }, /* 39: */
223 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
224 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
225 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
226 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
227 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
228 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
229 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
230 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
231 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
232 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
233 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
234 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
235 {{{0} } }, /* 52: */
236 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
237 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
238 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
239 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
240 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
241 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
242 {{{0} } }, /* 59: I2C0 */
243 {{{0} } }, /* 60: I2C1 */
244 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
245 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
246 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
247};
248
249/*
250 * top 12 bits of crb internal address (hub, agent)
251 */
252static unsigned crb_hub_agt[64] =
253{
254 0,
255 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
256 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
257 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
260 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
261 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
264 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
265 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
266 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
267 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
270 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
281 0,
282 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
283 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
284 0,
285 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
286 0,
287 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
288 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
289 0,
290 0,
291 0,
292 0,
293 0,
294 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
295 0,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
303 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
304 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
305 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
306 0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
308 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
309 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
310 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
311 0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
313 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
314 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
315 0,
316 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
317 0,
318};
319
3d396eb1
AK		 320/* PCI Windowing for DDR regions. */
321
3ce06a32 322#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1 323
623621b0
DP		 324#define NETXEN_UNICAST_ADDR(port, index) \
325 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
326#define NETXEN_MCAST_ADDR(port, index) \
327 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
328#define MAC_HI(addr) \
329 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
330#define MAC_LO(addr) \
331 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
332
333static int
334netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
335{
336 u32 val = 0;
337 u16 port = adapter->physical_port;
338 u8 *addr = adapter->netdev->dev_addr;
339
340 if (adapter->mc_enabled)
341 return 0;
342
f98a9f69 343 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 344 val |= (1UL << (28+port));
f98a9f69 345 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 346
347 /* add broadcast addr to filter */
348 val = 0xffffff;
f98a9f69
DP		 349 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
350 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0
DP		 351
352 /* add station addr to filter */
353 val = MAC_HI(addr);
f98a9f69 354 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
623621b0 355 val = MAC_LO(addr);
f98a9f69 356 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
623621b0
DP		 357
358 adapter->mc_enabled = 1;
359 return 0;
360}
361
362static int
363netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
364{
365 u32 val = 0;
366 u16 port = adapter->physical_port;
367 u8 *addr = adapter->netdev->dev_addr;
368
369 if (!adapter->mc_enabled)
370 return 0;
371
f98a9f69 372 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 373 val &= ~(1UL << (28+port));
f98a9f69 374 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 375
376 val = MAC_HI(addr);
f98a9f69 377 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
623621b0 378 val = MAC_LO(addr);
f98a9f69 379 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0 380
f98a9f69
DP		 381 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
382 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
623621b0
DP		 383
384 adapter->mc_enabled = 0;
385 return 0;
386}
387
388static int
389netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
390 int index, u8 *addr)
391{
392 u32 hi = 0, lo = 0;
393 u16 port = adapter->physical_port;
394
395 lo = MAC_LO(addr);
396 hi = MAC_HI(addr);
397
f98a9f69
DP		 398 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
399 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
623621b0
DP		 400
401 return 0;
402}
403
c9fc891f 404void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 405{
3176ff3e 406 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1 407 struct dev_mc_list *mc_ptr;
623621b0
DP		 408 u8 null_addr[6];
409 int index = 0;
410
411 memset(null_addr, 0, 6);
3d396eb1 412
3d396eb1 413 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 414
415 adapter->set_promisc(adapter,
416 NETXEN_NIU_PROMISC_MODE);
417
418 /* Full promiscuous mode */
419 netxen_nic_disable_mcast_filter(adapter);
420
421 return;
422 }
423
424 if (netdev->mc_count == 0) {
425 adapter->set_promisc(adapter,
426 NETXEN_NIU_NON_PROMISC_MODE);
427 netxen_nic_disable_mcast_filter(adapter);
428 return;
429 }
430
431 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
432 if (netdev->flags & IFF_ALLMULTI ||
433 netdev->mc_count > adapter->max_mc_count) {
434 netxen_nic_disable_mcast_filter(adapter);
435 return;
3d396eb1 436 }
623621b0
DP		 437
438 netxen_nic_enable_mcast_filter(adapter);
439
440 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
441 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
442
443 if (index != netdev->mc_count)
444 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
445 netxen_nic_driver_name, netdev->name);
446
447 /* Clear out remaining addresses */
448 for (; index < adapter->max_mc_count; index++)
449 netxen_nic_set_mcast_addr(adapter, index, null_addr);
3d396eb1
AK		 450}
451
c9fc891f
DP		 452static int
453netxen_send_cmd_descs(struct netxen_adapter *adapter,
d877f1e3 454 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
c9fc891f 455{
d877f1e3 456 u32 i, producer, consumer;
c9fc891f
DP		 457 struct netxen_cmd_buffer *pbuf;
458 struct cmd_desc_type0 *cmd_desc;
d877f1e3 459 struct nx_host_tx_ring *tx_ring;
c9fc891f
DP		 460
461 i = 0;
462
4ea528a1 463 tx_ring = adapter->tx_ring;
b2af9cb0 464 __netif_tx_lock_bh(tx_ring->txq);
03e678ee 465
d877f1e3
DP		 466 producer = tx_ring->producer;
467 consumer = tx_ring->sw_consumer;
468
b2af9cb0
DP		 469 if (nr_desc >= netxen_tx_avail(tx_ring)) {
470 netif_tx_stop_queue(tx_ring->txq);
471 __netif_tx_unlock_bh(tx_ring->txq);
d877f1e3
DP		 472 return -EBUSY;
473 }
474
c9fc891f
DP		 475 do {
476 cmd_desc = &cmd_desc_arr[i];
477
d877f1e3 478 pbuf = &tx_ring->cmd_buf_arr[producer];
c9fc891f 479 pbuf->skb = NULL;
c9fc891f 480 pbuf->frag_count = 0;
c9fc891f 481
d877f1e3 482 memcpy(&tx_ring->desc_head[producer],
c9fc891f
DP		 483 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
484
d877f1e3 485 producer = get_next_index(producer, tx_ring->num_desc);
c9fc891f
DP		 486 i++;
487
d877f1e3 488 } while (i != nr_desc);
c9fc891f 489
d877f1e3 490 tx_ring->producer = producer;
c9fc891f 491
cb2107be 492 netxen_nic_update_cmd_producer(adapter, tx_ring);
c9fc891f 493
b2af9cb0 494 __netif_tx_unlock_bh(tx_ring->txq);
03e678ee 495
c9fc891f
DP		 496 return 0;
497}
498
5cf4d323
DP		 499static int
500nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
c9fc891f 501{
c9fc891f 502 nx_nic_req_t req;
2edbb454
DP		 503 nx_mac_req_t *mac_req;
504 u64 word;
c9fc891f
DP		 505
506 memset(&req, 0, sizeof(nx_nic_req_t));
2edbb454
DP		 507 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
508
509 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
510 req.req_hdr = cpu_to_le64(word);
511
512 mac_req = (nx_mac_req_t *)&req.words[0];
513 mac_req->op = op;
514 memcpy(mac_req->mac_addr, addr, 6);
c9fc891f 515
5cf4d323
DP		 516 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
517}
518
519static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
520 u8 *addr, struct list_head *del_list)
521{
522 struct list_head *head;
523 nx_mac_list_t *cur;
524
525 /* look up if already exists */
526 list_for_each(head, del_list) {
527 cur = list_entry(head, nx_mac_list_t, list);
528
529 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
530 list_move_tail(head, &adapter->mac_list);
531 return 0;
532 }
c9fc891f
DP		 533 }
534
5cf4d323
DP		 535 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
536 if (cur == NULL) {
537 printk(KERN_ERR "%s: failed to add mac address filter\n",
538 adapter->netdev->name);
539 return -ENOMEM;
540 }
541 memcpy(cur->mac_addr, addr, ETH_ALEN);
542 list_add_tail(&cur->list, &adapter->mac_list);
543 return nx_p3_sre_macaddr_change(adapter,
544 cur->mac_addr, NETXEN_MAC_ADD);
c9fc891f
DP		 545}
546
547void netxen_p3_nic_set_multi(struct net_device *netdev)
548{
549 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f
DP		 550 struct dev_mc_list *mc_ptr;
551 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
9ad27643 552 u32 mode = VPORT_MISS_MODE_DROP;
5cf4d323
DP		 553 LIST_HEAD(del_list);
554 struct list_head *head;
555 nx_mac_list_t *cur;
c9fc891f 556
5cf4d323 557 list_splice_tail_init(&adapter->mac_list, &del_list);
c9fc891f 558
5cf4d323
DP		 559 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
560 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
9ad27643
DP		 561
562 if (netdev->flags & IFF_PROMISC) {
563 mode = VPORT_MISS_MODE_ACCEPT_ALL;
564 goto send_fw_cmd;
565 }
566
567 if ((netdev->flags & IFF_ALLMULTI) ||
568 (netdev->mc_count > adapter->max_mc_count)) {
569 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
570 goto send_fw_cmd;
571 }
572
c9fc891f 573 if (netdev->mc_count > 0) {
c9fc891f
DP		 574 for (mc_ptr = netdev->mc_list; mc_ptr;
575 mc_ptr = mc_ptr->next) {
5cf4d323 576 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
c9fc891f
DP		 577 }
578 }
9ad27643
DP		 579
580send_fw_cmd:
581 adapter->set_promisc(adapter, mode);
5cf4d323
DP		 582 head = &del_list;
583 while (!list_empty(head)) {
584 cur = list_entry(head->next, nx_mac_list_t, list);
585
586 nx_p3_sre_macaddr_change(adapter,
587 cur->mac_addr, NETXEN_MAC_DEL);
588 list_del(&cur->list);
c9fc891f 589 kfree(cur);
c9fc891f
DP		 590 }
591}
592
9ad27643
DP		 593int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
594{
595 nx_nic_req_t req;
2edbb454 596 u64 word;
9ad27643
DP		 597
598 memset(&req, 0, sizeof(nx_nic_req_t));
599
2edbb454
DP		 600 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
601
602 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
603 ((u64)adapter->portnum << 16);
604 req.req_hdr = cpu_to_le64(word);
605
9ad27643
DP		 606 req.words[0] = cpu_to_le64(mode);
607
608 return netxen_send_cmd_descs(adapter,
609 (struct cmd_desc_type0 *)&req, 1);
610}
611
06e9d9f9
DP		 612void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
613{
5cf4d323
DP		 614 nx_mac_list_t *cur;
615 struct list_head *head = &adapter->mac_list;
616
617 while (!list_empty(head)) {
618 cur = list_entry(head->next, nx_mac_list_t, list);
619 nx_p3_sre_macaddr_change(adapter,
620 cur->mac_addr, NETXEN_MAC_DEL);
621 list_del(&cur->list);
06e9d9f9 622 kfree(cur);
06e9d9f9
DP		 623 }
624}
625
3d0a3cc9
DP		 626int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
627{
628 /* assuming caller has already copied new addr to netdev */
629 netxen_p3_nic_set_multi(adapter->netdev);
630 return 0;
631}
632
cd1f8160
DP		 633#define NETXEN_CONFIG_INTR_COALESCE 3
634
635/*
636 * Send the interrupt coalescing parameter set by ethtool to the card.
637 */
638int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
639{
640 nx_nic_req_t req;
2edbb454 641 u64 word;
cd1f8160
DP		 642 int rv;
643
644 memset(&req, 0, sizeof(nx_nic_req_t));
645
2edbb454
DP		 646 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
647
648 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
649 req.req_hdr = cpu_to_le64(word);
cd1f8160
DP		 650
651 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
652
653 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
654 if (rv != 0) {
655 printk(KERN_ERR "ERROR. Could not send "
656 "interrupt coalescing parameters\n");
657 }
658
659 return rv;
660}
661
d8b100c5
DP		 662#define RSS_HASHTYPE_IP_TCP 0x3
663
664int netxen_config_rss(struct netxen_adapter *adapter, int enable)
665{
666 nx_nic_req_t req;
667 u64 word;
668 int i, rv;
669
670 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
671 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
672 0x255b0ec26d5a56daULL };
673
674
675 memset(&req, 0, sizeof(nx_nic_req_t));
676 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
677
678 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
679 req.req_hdr = cpu_to_le64(word);
680
681 /*
682 * RSS request:
683 * bits 3-0: hash_method
684 * 5-4: hash_type_ipv4
685 * 7-6: hash_type_ipv6
686 * 8: enable
687 * 9: use indirection table
688 * 47-10: reserved
689 * 63-48: indirection table mask
690 */
691 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
692 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
693 ((u64)(enable & 0x1) << 8) |
694 ((0x7ULL) << 48);
695 req.words[0] = cpu_to_le64(word);
696 for (i = 0; i < 5; i++)
697 req.words[i+1] = cpu_to_le64(key[i]);
698
699
700 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
701 if (rv != 0) {
702 printk(KERN_ERR "%s: could not configure RSS\n",
703 adapter->netdev->name);
704 }
705
706 return rv;
707}
708
6598b169
DP		 709int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
710{
711 nx_nic_req_t req;
712 u64 word;
713 int rv;
714
715 memset(&req, 0, sizeof(nx_nic_req_t));
716 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
717
718 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
719 req.req_hdr = cpu_to_le64(word);
720
721 req.words[0] = cpu_to_le64(cmd);
722 req.words[1] = cpu_to_le64(ip);
723
724 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
725 if (rv != 0) {
726 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
727 adapter->netdev->name,
728 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
729 }
730 return rv;
731}
732
3bf26ce3
DP		 733int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
734{
735 nx_nic_req_t req;
736 u64 word;
737 int rv;
738
739 memset(&req, 0, sizeof(nx_nic_req_t));
740 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
741
742 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
743 req.req_hdr = cpu_to_le64(word);
22527864 744 req.words[0] = cpu_to_le64(enable | (enable << 8));
3bf26ce3
DP		 745
746 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
747 if (rv != 0) {
748 printk(KERN_ERR "%s: could not configure link notification\n",
749 adapter->netdev->name);
750 }
751
752 return rv;
753}
754
3d396eb1
AK		 755/*
756 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
757 * @returns 0 on success, negative on failure
758 */
c9fc891f
DP		 759
760#define MTU_FUDGE_FACTOR 100
761
3d396eb1
AK		 762int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
763{
3176ff3e 764 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 765 int max_mtu;
9ad27643 766 int rc = 0;
3d396eb1 767
c9fc891f
DP		 768 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
769 max_mtu = P3_MAX_MTU;
770 else
771 max_mtu = P2_MAX_MTU;
772
773 if (mtu > max_mtu) {
774 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
775 netdev->name, max_mtu);
3d396eb1
AK		 776 return -EINVAL;
777 }
778
80922fbc 779 if (adapter->set_mtu)
9ad27643 780 rc = adapter->set_mtu(adapter, mtu);
3d396eb1 781
9ad27643
DP		 782 if (!rc)
783 netdev->mtu = mtu;
c9fc891f 784
9ad27643 785 return rc;
3d396eb1
AK		 786}
787
3d396eb1 788static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 789 int size, __le32 * buf)
3d396eb1 790{
1e2d0059 791 int i, v, addr;
f305f789 792 __le32 *ptr32;
3d396eb1
AK		 793
794 addr = base;
795 ptr32 = buf;
796 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 797 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 798 return -1;
f305f789 799 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 800 ptr32++;
801 addr += sizeof(u32);
802 }
803 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 804 __le32 local;
805 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 806 return -1;
f305f789 807 local = cpu_to_le32(v);
3d396eb1
AK		 808 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
809 }
810
811 return 0;
812}
813
9dc28efe 814int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
3d396eb1 815{
9dc28efe
DP		 816 __le32 *pmac = (__le32 *) mac;
817 u32 offset;
3d396eb1 818
06db58c0 819 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
9dc28efe
DP		 820
821 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
3d396eb1 822 return -1;
9dc28efe 823
f305f789 824 if (*mac == cpu_to_le64(~0ULL)) {
9dc28efe 825
06db58c0
DP		 826 offset = NX_OLD_MAC_ADDR_OFFSET +
827 (adapter->portnum * sizeof(u64));
9dc28efe 828
3d396eb1 829 if (netxen_get_flash_block(adapter,
9dc28efe 830 offset, sizeof(u64), pmac) == -1)
3d396eb1 831 return -1;
9dc28efe 832
f305f789 833 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 834 return -1;
835 }
836 return 0;
837}
838
9dc28efe
DP		 839int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
840{
841 uint32_t crbaddr, mac_hi, mac_lo;
842 int pci_func = adapter->ahw.pci_func;
843
844 crbaddr = CRB_MAC_BLOCK_START +
845 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
846
f98a9f69
DP		 847 mac_lo = NXRD32(adapter, crbaddr);
848 mac_hi = NXRD32(adapter, crbaddr+4);
9dc28efe 849
9dc28efe 850 if (pci_func & 1)
2edbb454 851 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
9dc28efe 852 else
2edbb454 853 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
9dc28efe
DP		 854
855 return 0;
856}
857
3ce06a32
DP		 858#define CRB_WIN_LOCK_TIMEOUT 100000000
859
860static int crb_win_lock(struct netxen_adapter *adapter)
861{
862 int done = 0, timeout = 0;
863
864 while (!done) {
865 /* acquire semaphore3 from PCI HW block */
f98a9f69 866 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_LOCK));
3ce06a32
DP		 867 if (done == 1)
868 break;
869 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
870 return -1;
871 timeout++;
872 udelay(1);
873 }
f98a9f69 874 NXWR32(adapter, NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
3ce06a32
DP		 875 return 0;
876}
877
878static void crb_win_unlock(struct netxen_adapter *adapter)
879{
880 int val;
881
f98a9f69 882 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK));
3ce06a32
DP		 883}
884
3d396eb1
AK		 885/*
886 * Changes the CRB window to the specified window.
887 */
3ce06a32
DP		 888void
889netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
3d396eb1
AK		 890{
891 void __iomem *offset;
892 u32 tmp;
893 int count = 0;
e4c93c81 894 uint8_t func = adapter->ahw.pci_func;
3d396eb1
AK		 895
896 if (adapter->curr_window == wndw)
897 return;
3d396eb1
AK		 898 /*
899 * Move the CRB window.
900 * We need to write to the "direct access" region of PCI
901 * to avoid a race condition where the window register has
902 * not been successfully written across CRB before the target
903 * register address is received by PCI. The direct region bypasses
904 * the CRB bus.
905 */
e4c93c81
DP		 906 offset = PCI_OFFSET_SECOND_RANGE(adapter,
907 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1
AK		 908
909 if (wndw & 0x1)
910 wndw = NETXEN_WINDOW_ONE;
911
912 writel(wndw, offset);
913
914 /* MUST make sure window is set before we forge on... */
915 while ((tmp = readl(offset)) != wndw) {
916 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
917 "registered properly: 0x%08x.\n",
3ce06a32 918 netxen_nic_driver_name, __func__, tmp);
3d396eb1
AK		 919 mdelay(1);
920 if (count >= 10)
921 break;
922 count++;
923 }
924
6c80b18d
MT		 925 if (wndw == NETXEN_WINDOW_ONE)
926 adapter->curr_window = 1;
927 else
928 adapter->curr_window = 0;
3d396eb1
AK		 929}
930
3ce06a32
DP		 931/*
932 * Return -1 if off is not valid,
933 * 1 if window access is needed. 'off' is set to offset from
934 * CRB space in 128M pci map
935 * 0 if no window access is needed. 'off' is set to 2M addr
936 * In: 'off' is offset from base in 128M pci map
937 */
938static int
23b6cc42 939netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
3ce06a32 940{
3ce06a32
DP		 941 crb_128M_2M_sub_block_map_t *m;
942
943
944 if (*off >= NETXEN_CRB_MAX)
945 return -1;
946
23b6cc42 947 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
3ce06a32
DP		 948 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
949 (ulong)adapter->ahw.pci_base0;
950 return 0;
951 }
952
953 if (*off < NETXEN_PCI_CRBSPACE)
954 return -1;
955
956 *off -= NETXEN_PCI_CRBSPACE;
3ce06a32
DP		 957
958 /*
959 * Try direct map
960 */
961 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
962
23b6cc42 963 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
3ce06a32
DP		 964 *off = *off + m->start_2M - m->start_128M +
965 (ulong)adapter->ahw.pci_base0;
966 return 0;
967 }
968
969 /*
970 * Not in direct map, use crb window
971 */
972 return 1;
973}
974
975/*
976 * In: 'off' is offset from CRB space in 128M pci map
977 * Out: 'off' is 2M pci map addr
978 * side effect: lock crb window
979 */
980static void
981netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
982{
983 u32 win_read;
984
985 adapter->crb_win = CRB_HI(*off);
d8313ce0 986 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
3ce06a32
DP		 987 /*
988 * Read back value to make sure write has gone through before trying
989 * to use it.
990 */
d8313ce0 991 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
3ce06a32
DP		 992 if (win_read != adapter->crb_win) {
993 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
994 "Read crbwin (0x%x), off=0x%lx\n",
995 __func__, adapter->crb_win, win_read, *off);
996 }
997 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
998 (ulong)adapter->ahw.pci_base0;
999}
1000
3d396eb1 1001int
1fbe6323 1002netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
3d396eb1
AK		 1003{
1004 void __iomem *addr;
1005
1006 if (ADDR_IN_WINDOW1(off)) {
1007 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1008 } else { /* Window 0 */
cb8011ad 1009 addr = pci_base_offset(adapter, off);
3ce06a32 1010 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 1011 }
1012
cb8011ad 1013 if (!addr) {
3ce06a32 1014 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1015 return 1;
1016 }
1017
1fbe6323 1018 writel(data, addr);
3d396eb1 1019
3d396eb1 1020 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1021 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 1022
1023 return 0;
1024}
1025
1fbe6323
DP		 1026u32
1027netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
3d396eb1
AK		 1028{
1029 void __iomem *addr;
1fbe6323 1030 u32 data;
d8313ce0 1031
3d396eb1
AK		 1032 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1033 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1034 } else { /* Window 0 */
cb8011ad 1035 addr = pci_base_offset(adapter, off);
3ce06a32 1036 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 1037 }
1038
cb8011ad 1039 if (!addr) {
3ce06a32 1040 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1041 return 1;
1042 }
d8313ce0 1043
1fbe6323 1044 data = readl(addr);
3d396eb1
AK		 1045
1046 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1047 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1 1048
1fbe6323 1049 return data;
3d396eb1
AK		 1050}
1051
3ce06a32 1052int
1fbe6323 1053netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
3ce06a32
DP		 1054{
1055 unsigned long flags = 0;
1056 int rv;
3d396eb1 1057
23b6cc42 1058 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
3d396eb1 1059
3ce06a32
DP		 1060 if (rv == -1) {
1061 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1062 __func__, off);
1063 dump_stack();
1064 return -1;
1065 }
1066
1067 if (rv == 1) {
1068 write_lock_irqsave(&adapter->adapter_lock, flags);
1069 crb_win_lock(adapter);
1070 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1fbe6323 1071 writel(data, (void __iomem *)off);
3ce06a32
DP		 1072 crb_win_unlock(adapter);
1073 write_unlock_irqrestore(&adapter->adapter_lock, flags);
d8313ce0 1074 } else
1fbe6323 1075 writel(data, (void __iomem *)off);
d8313ce0 1076
3ce06a32
DP		 1077
1078 return 0;
3d396eb1
AK		 1079}
1080
1fbe6323
DP		 1081u32
1082netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
3ce06a32
DP		 1083{
1084 unsigned long flags = 0;
1085 int rv;
1fbe6323 1086 u32 data;
3d396eb1 1087
23b6cc42 1088 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
3ce06a32
DP		 1089
1090 if (rv == -1) {
1091 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1092 __func__, off);
1093 dump_stack();
1094 return -1;
1095 }
1096
1097 if (rv == 1) {
1098 write_lock_irqsave(&adapter->adapter_lock, flags);
1099 crb_win_lock(adapter);
1100 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1fbe6323 1101 data = readl((void __iomem *)off);
3ce06a32
DP		 1102 crb_win_unlock(adapter);
1103 write_unlock_irqrestore(&adapter->adapter_lock, flags);
d8313ce0 1104 } else
1fbe6323 1105 data = readl((void __iomem *)off);
3ce06a32 1106
1fbe6323 1107 return data;
3ce06a32
DP		 1108}
1109
3ce06a32
DP		 1110/*
1111 * check memory access boundary.
1112 * used by test agent. support ddr access only for now
1113 */
1114static unsigned long
1115netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1116 unsigned long long addr, int size)
1117{
1118 if (!ADDR_IN_RANGE(addr,
1119 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1120 !ADDR_IN_RANGE(addr+size-1,
1121 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1122 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1123 return 0;
1124 }
3d396eb1 1125
3ce06a32 1126 return 1;
3d396eb1
AK		 1127}
1128
4790654c 1129static int netxen_pci_set_window_warning_count;
3d396eb1 1130
3ce06a32
DP		 1131unsigned long
1132netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1133 unsigned long long addr)
3d396eb1 1134{
e4c93c81 1135 void __iomem *offset;
3d396eb1 1136 int window;
3ce06a32 1137 unsigned long long qdr_max;
e4c93c81 1138 uint8_t func = adapter->ahw.pci_func;
3d396eb1 1139
3ce06a32
DP		 1140 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1141 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1142 } else {
1143 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1144 }
1145
3d396eb1
AK		 1146 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1147 /* DDR network side */
1148 addr -= NETXEN_ADDR_DDR_NET;
1149 window = (addr >> 25) & 0x3ff;
3ce06a32
DP		 1150 if (adapter->ahw.ddr_mn_window != window) {
1151 adapter->ahw.ddr_mn_window = window;
e4c93c81
DP		 1152 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1153 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1154 writel(window, offset);
3d396eb1 1155 /* MUST make sure window is set before we forge on... */
e4c93c81 1156 readl(offset);
3d396eb1 1157 }
cb8011ad 1158 addr -= (window * NETXEN_WINDOW_ONE);
3d396eb1
AK		 1159 addr += NETXEN_PCI_DDR_NET;
1160 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1161 addr -= NETXEN_ADDR_OCM0;
1162 addr += NETXEN_PCI_OCM0;
1163 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1164 addr -= NETXEN_ADDR_OCM1;
1165 addr += NETXEN_PCI_OCM1;
3ce06a32 1166 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
3d396eb1
AK		 1167 /* QDR network side */
1168 addr -= NETXEN_ADDR_QDR_NET;
1169 window = (addr >> 22) & 0x3f;
3ce06a32
DP		 1170 if (adapter->ahw.qdr_sn_window != window) {
1171 adapter->ahw.qdr_sn_window = window;
e4c93c81
DP		 1172 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1173 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1174 writel((window << 22), offset);
3d396eb1 1175 /* MUST make sure window is set before we forge on... */
e4c93c81 1176 readl(offset);
3d396eb1
AK		 1177 }
1178 addr -= (window * 0x400000);
1179 addr += NETXEN_PCI_QDR_NET;
1180 } else {
1181 /*
1182 * peg gdb frequently accesses memory that doesn't exist,
1183 * this limits the chit chat so debugging isn't slowed down.
1184 */
1185 if ((netxen_pci_set_window_warning_count++ < 8)
1186 || (netxen_pci_set_window_warning_count % 64 == 0))
1187 printk("%s: Warning:netxen_nic_pci_set_window()"
1188 " Unknown address range!\n",
1189 netxen_nic_driver_name);
3ce06a32
DP		 1190 addr = -1UL;
1191 }
1192 return addr;
1193}
1194
1195/*
1196 * Note : only 32-bit writes!
1197 */
1198int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1199 u64 off, u32 data)
1200{
1201 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1202 return 0;
1203}
1204
1205u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1206{
1207 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1208}
1209
3ce06a32
DP		 1210unsigned long
1211netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1212 unsigned long long addr)
1213{
1214 int window;
1215 u32 win_read;
3d396eb1 1216
3ce06a32
DP		 1217 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1218 /* DDR network side */
1219 window = MN_WIN(addr);
1220 adapter->ahw.ddr_mn_window = window;
f98a9f69 1221 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1fbe6323 1222 window);
f98a9f69 1223 win_read = NXRD32(adapter,
1fbe6323 1224 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
3ce06a32
DP		 1225 if ((win_read << 17) != window) {
1226 printk(KERN_INFO "Written MNwin (0x%x) != "
1227 "Read MNwin (0x%x)\n", window, win_read);
1228 }
1229 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1230 } else if (ADDR_IN_RANGE(addr,
1231 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1232 if ((addr & 0x00ff800) == 0xff800) {
1233 printk("%s: QM access not handled.\n", __func__);
1234 addr = -1UL;
1235 }
1236
1237 window = OCM_WIN(addr);
1238 adapter->ahw.ddr_mn_window = window;
f98a9f69 1239 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1fbe6323 1240 window);
f98a9f69 1241 win_read = NXRD32(adapter,
1fbe6323 1242 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
3ce06a32
DP		 1243 if ((win_read >> 7) != window) {
1244 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1245 "Read OCMwin (0x%x)\n",
1246 __func__, window, win_read);
1247 }
1248 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1249
1250 } else if (ADDR_IN_RANGE(addr,
1251 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1252 /* QDR network side */
1253 window = MS_WIN(addr);
1254 adapter->ahw.qdr_sn_window = window;
f98a9f69 1255 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1fbe6323 1256 window);
f98a9f69 1257 win_read = NXRD32(adapter,
1fbe6323 1258 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
3ce06a32
DP		 1259 if (win_read != window) {
1260 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1261 "Read MSwin (0x%x)\n",
1262 __func__, window, win_read);
1263 }
1264 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1265
1266 } else {
1267 /*
1268 * peg gdb frequently accesses memory that doesn't exist,
1269 * this limits the chit chat so debugging isn't slowed down.
1270 */
1271 if ((netxen_pci_set_window_warning_count++ < 8)
1272 || (netxen_pci_set_window_warning_count%64 == 0)) {
1273 printk("%s: Warning:%s Unknown address range!\n",
1274 __func__, netxen_nic_driver_name);
1275}
1276 addr = -1UL;
3d396eb1
AK		 1277 }
1278 return addr;
1279}
1280
3ce06a32
DP		 1281static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1282 unsigned long long addr)
1283{
1284 int window;
1285 unsigned long long qdr_max;
1286
1287 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1288 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1289 else
1290 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1291
1292 if (ADDR_IN_RANGE(addr,
1293 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1294 /* DDR network side */
1295 BUG(); /* MN access can not come here */
1296 } else if (ADDR_IN_RANGE(addr,
1297 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1298 return 1;
1299 } else if (ADDR_IN_RANGE(addr,
1300 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1301 return 1;
1302 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1303 /* QDR network side */
1304 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1305 if (adapter->ahw.qdr_sn_window == window)
1306 return 1;
1307 }
1308
1309 return 0;
1310}
1311
1312static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1313 u64 off, void *data, int size)
1314{
1315 unsigned long flags;
d8313ce0 1316 void __iomem *addr, *mem_ptr = NULL;
3ce06a32
DP		 1317 int ret = 0;
1318 u64 start;
3ce06a32
DP		 1319 unsigned long mem_base;
1320 unsigned long mem_page;
1321
1322 write_lock_irqsave(&adapter->adapter_lock, flags);
1323
1324 /*
1325 * If attempting to access unknown address or straddle hw windows,
1326 * do not access.
1327 */
1328 start = adapter->pci_set_window(adapter, off);
1329 if ((start == -1UL) ||
1330 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1331 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1332 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1333 "offset is 0x%llx\n", netxen_nic_driver_name,
1334 (unsigned long long)off);
3ce06a32
DP		 1335 return -1;
1336 }
1337
d8313ce0 1338 addr = pci_base_offset(adapter, start);
3ce06a32
DP		 1339 if (!addr) {
1340 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1341 mem_base = pci_resource_start(adapter->pdev, 0);
1342 mem_page = start & PAGE_MASK;
1343 /* Map two pages whenever user tries to access addresses in two
1344 consecutive pages.
1345 */
1346 if (mem_page != ((start + size - 1) & PAGE_MASK))
1347 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1348 else
1349 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
f8057b7f 1350 if (mem_ptr == NULL) {
3ce06a32
DP		 1351 *(uint8_t *)data = 0;
1352 return -1;
1353 }
1354 addr = mem_ptr;
1355 addr += start & (PAGE_SIZE - 1);
1356 write_lock_irqsave(&adapter->adapter_lock, flags);
1357 }
1358
1359 switch (size) {
1360 case 1:
1361 *(uint8_t *)data = readb(addr);
1362 break;
1363 case 2:
1364 *(uint16_t *)data = readw(addr);
1365 break;
1366 case 4:
1367 *(uint32_t *)data = readl(addr);
1368 break;
1369 case 8:
1370 *(uint64_t *)data = readq(addr);
1371 break;
1372 default:
1373 ret = -1;
1374 break;
1375 }
1376 write_unlock_irqrestore(&adapter->adapter_lock, flags);
3ce06a32
DP		 1377
1378 if (mem_ptr)
1379 iounmap(mem_ptr);
1380 return ret;
1381}
1382
1383static int
1384netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1385 void *data, int size)
1386{
1387 unsigned long flags;
d8313ce0 1388 void __iomem *addr, *mem_ptr = NULL;
3ce06a32
DP		 1389 int ret = 0;
1390 u64 start;
3ce06a32
DP		 1391 unsigned long mem_base;
1392 unsigned long mem_page;
1393
1394 write_lock_irqsave(&adapter->adapter_lock, flags);
1395
1396 /*
1397 * If attempting to access unknown address or straddle hw windows,
1398 * do not access.
1399 */
1400 start = adapter->pci_set_window(adapter, off);
1401 if ((start == -1UL) ||
1402 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1403 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1404 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1405 "offset is 0x%llx\n", netxen_nic_driver_name,
1406 (unsigned long long)off);
3ce06a32
DP		 1407 return -1;
1408 }
1409
d8313ce0 1410 addr = pci_base_offset(adapter, start);
3ce06a32
DP		 1411 if (!addr) {
1412 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1413 mem_base = pci_resource_start(adapter->pdev, 0);
1414 mem_page = start & PAGE_MASK;
1415 /* Map two pages whenever user tries to access addresses in two
1416 * consecutive pages.
1417 */
1418 if (mem_page != ((start + size - 1) & PAGE_MASK))
1419 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1420 else
1421 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
f8057b7f 1422 if (mem_ptr == NULL)
3ce06a32
DP		 1423 return -1;
1424 addr = mem_ptr;
1425 addr += start & (PAGE_SIZE - 1);
1426 write_lock_irqsave(&adapter->adapter_lock, flags);
1427 }
1428
1429 switch (size) {
1430 case 1:
1431 writeb(*(uint8_t *)data, addr);
1432 break;
1433 case 2:
1434 writew(*(uint16_t *)data, addr);
1435 break;
1436 case 4:
1437 writel(*(uint32_t *)data, addr);
1438 break;
1439 case 8:
1440 writeq(*(uint64_t *)data, addr);
1441 break;
1442 default:
1443 ret = -1;
1444 break;
1445 }
1446 write_unlock_irqrestore(&adapter->adapter_lock, flags);
3ce06a32
DP		 1447 if (mem_ptr)
1448 iounmap(mem_ptr);
1449 return ret;
1450}
1451
1452#define MAX_CTL_CHECK 1000
1453
1454int
1455netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1456 u64 off, void *data, int size)
1457{
d8313ce0 1458 unsigned long flags;
3ce06a32
DP		 1459 int i, j, ret = 0, loop, sz[2], off0;
1460 uint32_t temp;
1461 uint64_t off8, tmpw, word[2] = {0, 0};
d8313ce0 1462 void __iomem *mem_crb;
3ce06a32
DP		 1463
1464 /*
1465 * If not MN, go check for MS or invalid.
1466 */
1467 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1468 return netxen_nic_pci_mem_write_direct(adapter,
1469 off, data, size);
1470
1471 off8 = off & 0xfffffff8;
1472 off0 = off & 0x7;
1473 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1474 sz[1] = size - sz[0];
1475 loop = ((off0 + size - 1) >> 3) + 1;
d8313ce0 1476 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
3ce06a32
DP		 1477
1478 if ((size != 8) || (off0 != 0)) {
1479 for (i = 0; i < loop; i++) {
1480 if (adapter->pci_mem_read(adapter,
1481 off8 + (i << 3), &word[i], 8))
1482 return -1;
1483 }
1484 }
1485
1486 switch (size) {
1487 case 1:
1488 tmpw = *((uint8_t *)data);
1489 break;
1490 case 2:
1491 tmpw = *((uint16_t *)data);
1492 break;
1493 case 4:
1494 tmpw = *((uint32_t *)data);
1495 break;
1496 case 8:
1497 default:
1498 tmpw = *((uint64_t *)data);
1499 break;
1500 }
1501 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1502 word[0] |= tmpw << (off0 * 8);
1503
1504 if (loop == 2) {
1505 word[1] &= ~(~0ULL << (sz[1] * 8));
1506 word[1] |= tmpw >> (sz[0] * 8);
1507 }
1508
1509 write_lock_irqsave(&adapter->adapter_lock, flags);
1510 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1511
1512 for (i = 0; i < loop; i++) {
1513 writel((uint32_t)(off8 + (i << 3)),
d8313ce0 1514 (mem_crb+MIU_TEST_AGT_ADDR_LO));
3ce06a32 1515 writel(0,
d8313ce0 1516 (mem_crb+MIU_TEST_AGT_ADDR_HI));
3ce06a32 1517 writel(word[i] & 0xffffffff,
d8313ce0 1518 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
3ce06a32 1519 writel((word[i] >> 32) & 0xffffffff,
d8313ce0 1520 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
3ce06a32 1521 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
d8313ce0 1522 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32 1523 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
d8313ce0 1524 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1525
1526 for (j = 0; j < MAX_CTL_CHECK; j++) {
1527 temp = readl(
d8313ce0 1528 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1529 if ((temp & MIU_TA_CTL_BUSY) == 0)
1530 break;
1531 }
1532
1533 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1534 if (printk_ratelimit())
1535 dev_err(&adapter->pdev->dev,
1536 "failed to write through agent\n");
3ce06a32
DP		 1537 ret = -1;
1538 break;
1539 }
1540 }
1541
1542 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1543 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1544 return ret;
1545}
1546
1547int
1548netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1549 u64 off, void *data, int size)
1550{
d8313ce0 1551 unsigned long flags;
3ce06a32
DP		 1552 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1553 uint32_t temp;
1554 uint64_t off8, val, word[2] = {0, 0};
d8313ce0 1555 void __iomem *mem_crb;
3ce06a32
DP		 1556
1557
1558 /*
1559 * If not MN, go check for MS or invalid.
1560 */
1561 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1562 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1563
1564 off8 = off & 0xfffffff8;
1565 off0[0] = off & 0x7;
1566 off0[1] = 0;
1567 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1568 sz[1] = size - sz[0];
1569 loop = ((off0[0] + size - 1) >> 3) + 1;
d8313ce0 1570 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
3ce06a32
DP		 1571
1572 write_lock_irqsave(&adapter->adapter_lock, flags);
1573 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1574
1575 for (i = 0; i < loop; i++) {
1576 writel((uint32_t)(off8 + (i << 3)),
d8313ce0 1577 (mem_crb+MIU_TEST_AGT_ADDR_LO));
3ce06a32 1578 writel(0,
d8313ce0 1579 (mem_crb+MIU_TEST_AGT_ADDR_HI));
3ce06a32 1580 writel(MIU_TA_CTL_ENABLE,
d8313ce0 1581 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32 1582 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
d8313ce0 1583 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1584
1585 for (j = 0; j < MAX_CTL_CHECK; j++) {
1586 temp = readl(
d8313ce0 1587 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1588 if ((temp & MIU_TA_CTL_BUSY) == 0)
1589 break;
1590 }
1591
1592 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1593 if (printk_ratelimit())
1594 dev_err(&adapter->pdev->dev,
1595 "failed to read through agent\n");
3ce06a32
DP		 1596 break;
1597 }
1598
1599 start = off0[i] >> 2;
1600 end = (off0[i] + sz[i] - 1) >> 2;
1601 for (k = start; k <= end; k++) {
1602 word[i] |= ((uint64_t) readl(
d8313ce0 1603 (mem_crb +
3ce06a32
DP		 1604 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1605 }
1606 }
1607
1608 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1609 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1610
1611 if (j >= MAX_CTL_CHECK)
1612 return -1;
1613
1614 if (sz[0] == 8) {
1615 val = word[0];
1616 } else {
1617 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1618 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1619 }
1620
1621 switch (size) {
1622 case 1:
1623 *(uint8_t *)data = val;
1624 break;
1625 case 2:
1626 *(uint16_t *)data = val;
1627 break;
1628 case 4:
1629 *(uint32_t *)data = val;
1630 break;
1631 case 8:
1632 *(uint64_t *)data = val;
1633 break;
1634 }
3ce06a32
DP		 1635 return 0;
1636}
1637
1638int
1639netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1640 u64 off, void *data, int size)
1641{
1642 int i, j, ret = 0, loop, sz[2], off0;
1643 uint32_t temp;
1644 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1645
1646 /*
1647 * If not MN, go check for MS or invalid.
1648 */
1649 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1650 mem_crb = NETXEN_CRB_QDR_NET;
1651 else {
1652 mem_crb = NETXEN_CRB_DDR_NET;
1653 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1654 return netxen_nic_pci_mem_write_direct(adapter,
1655 off, data, size);
1656 }
1657
1658 off8 = off & 0xfffffff8;
1659 off0 = off & 0x7;
1660 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1661 sz[1] = size - sz[0];
1662 loop = ((off0 + size - 1) >> 3) + 1;
1663
1664 if ((size != 8) || (off0 != 0)) {
1665 for (i = 0; i < loop; i++) {
1666 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1667 &word[i], 8))
1668 return -1;
1669 }
1670 }
1671
1672 switch (size) {
1673 case 1:
1674 tmpw = *((uint8_t *)data);
1675 break;
1676 case 2:
1677 tmpw = *((uint16_t *)data);
1678 break;
1679 case 4:
1680 tmpw = *((uint32_t *)data);
1681 break;
1682 case 8:
1683 default:
1684 tmpw = *((uint64_t *)data);
1685 break;
1686 }
1687
1688 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1689 word[0] |= tmpw << (off0 * 8);
1690
1691 if (loop == 2) {
1692 word[1] &= ~(~0ULL << (sz[1] * 8));
1693 word[1] |= tmpw >> (sz[0] * 8);
1694 }
1695
1696 /*
1697 * don't lock here - write_wx gets the lock if each time
1698 * write_lock_irqsave(&adapter->adapter_lock, flags);
1699 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1700 */
1701
1702 for (i = 0; i < loop; i++) {
1703 temp = off8 + (i << 3);
f98a9f69 1704 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
3ce06a32 1705 temp = 0;
f98a9f69 1706 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
3ce06a32 1707 temp = word[i] & 0xffffffff;
f98a9f69 1708 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
3ce06a32 1709 temp = (word[i] >> 32) & 0xffffffff;
f98a9f69 1710 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
3ce06a32 1711 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
f98a9f69 1712 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
3ce06a32 1713 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
f98a9f69 1714 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
3ce06a32
DP		 1715
1716 for (j = 0; j < MAX_CTL_CHECK; j++) {
f98a9f69 1717 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
3ce06a32
DP		 1718 if ((temp & MIU_TA_CTL_BUSY) == 0)
1719 break;
1720 }
1721
1722 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1723 if (printk_ratelimit())
1724 dev_err(&adapter->pdev->dev,
1725 "failed to write through agent\n");
3ce06a32
DP		 1726 ret = -1;
1727 break;
1728 }
1729 }
1730
1731 /*
1732 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1733 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1734 */
1735 return ret;
1736}
1737
1738int
1739netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1740 u64 off, void *data, int size)
1741{
1742 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1743 uint32_t temp;
1744 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1745
1746 /*
1747 * If not MN, go check for MS or invalid.
1748 */
1749
1750 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1751 mem_crb = NETXEN_CRB_QDR_NET;
1752 else {
1753 mem_crb = NETXEN_CRB_DDR_NET;
1754 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1755 return netxen_nic_pci_mem_read_direct(adapter,
1756 off, data, size);
1757 }
1758
1759 off8 = off & 0xfffffff8;
1760 off0[0] = off & 0x7;
1761 off0[1] = 0;
1762 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1763 sz[1] = size - sz[0];
1764 loop = ((off0[0] + size - 1) >> 3) + 1;
1765
1766 /*
1767 * don't lock here - write_wx gets the lock if each time
1768 * write_lock_irqsave(&adapter->adapter_lock, flags);
1769 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1770 */
1771
1772 for (i = 0; i < loop; i++) {
1773 temp = off8 + (i << 3);
f98a9f69 1774 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
3ce06a32 1775 temp = 0;
f98a9f69 1776 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
3ce06a32 1777 temp = MIU_TA_CTL_ENABLE;
f98a9f69 1778 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
3ce06a32 1779 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
f98a9f69 1780 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
3ce06a32
DP		 1781
1782 for (j = 0; j < MAX_CTL_CHECK; j++) {
f98a9f69 1783 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
3ce06a32
DP		 1784 if ((temp & MIU_TA_CTL_BUSY) == 0)
1785 break;
1786 }
1787
1788 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1789 if (printk_ratelimit())
1790 dev_err(&adapter->pdev->dev,
1791 "failed to read through agent\n");
3ce06a32
DP		 1792 break;
1793 }
1794
1795 start = off0[i] >> 2;
1796 end = (off0[i] + sz[i] - 1) >> 2;
1797 for (k = start; k <= end; k++) {
f98a9f69 1798 temp = NXRD32(adapter,
1fbe6323 1799 mem_crb + MIU_TEST_AGT_RDDATA(k));
3ce06a32
DP		 1800 word[i] |= ((uint64_t)temp << (32 * k));
1801 }
1802 }
1803
1804 /*
1805 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1806 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1807 */
1808
1809 if (j >= MAX_CTL_CHECK)
1810 return -1;
1811
1812 if (sz[0] == 8) {
1813 val = word[0];
1814 } else {
1815 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1816 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1817 }
1818
1819 switch (size) {
1820 case 1:
1821 *(uint8_t *)data = val;
1822 break;
1823 case 2:
1824 *(uint16_t *)data = val;
1825 break;
1826 case 4:
1827 *(uint32_t *)data = val;
1828 break;
1829 case 8:
1830 *(uint64_t *)data = val;
1831 break;
1832 }
3ce06a32
DP		 1833 return 0;
1834}
1835
1836/*
1837 * Note : only 32-bit writes!
1838 */
1839int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1840 u64 off, u32 data)
1841{
f98a9f69 1842 NXWR32(adapter, off, data);
3ce06a32
DP		 1843
1844 return 0;
1845}
1846
1847u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1848{
f98a9f69 1849 return NXRD32(adapter, off);
3ce06a32
DP		 1850}
1851
3d396eb1
AK		 1852int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1853{
1e2d0059
DP		 1854 int offset, board_type, magic, header_version;
1855 struct pci_dev *pdev = adapter->pdev;
3d396eb1 1856
06db58c0 1857 offset = NX_FW_MAGIC_OFFSET;
1e2d0059
DP		 1858 if (netxen_rom_fast_read(adapter, offset, &magic))
1859 return -EIO;
3d396eb1 1860
06db58c0 1861 offset = NX_HDR_VERSION_OFFSET;
1e2d0059
DP		 1862 if (netxen_rom_fast_read(adapter, offset, &header_version))
1863 return -EIO;
1864
1865 if (magic != NETXEN_BDINFO_MAGIC ||
1866 header_version != NETXEN_BDINFO_VERSION) {
1867 dev_err(&pdev->dev,
1868 "invalid board config, magic=%08x, version=%08x\n",
1869 magic, header_version);
1870 return -EIO;
3d396eb1
AK		 1871 }
1872
06db58c0 1873 offset = NX_BRDTYPE_OFFSET;
1e2d0059
DP		 1874 if (netxen_rom_fast_read(adapter, offset, &board_type))
1875 return -EIO;
1876
1877 adapter->ahw.board_type = board_type;
1878
1879 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
f98a9f69 1880 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
c7860a2a 1881 if ((gpio & 0x8000) == 0)
1e2d0059 1882 board_type = NETXEN_BRDTYPE_P3_10G_TP;
c7860a2a
DP		 1883 }
1884
e98e3350 1885 switch (board_type) {
3d396eb1 1886 case NETXEN_BRDTYPE_P2_SB35_4G:
1e2d0059 1887 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1
AK		 1888 break;
1889 case NETXEN_BRDTYPE_P2_SB31_10G:
1890 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1891 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1892 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 1893 case NETXEN_BRDTYPE_P3_HMEZ:
1894 case NETXEN_BRDTYPE_P3_XG_LOM:
1895 case NETXEN_BRDTYPE_P3_10G_CX4:
1896 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1897 case NETXEN_BRDTYPE_P3_IMEZ:
1898 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
a70f9393
DP		 1899 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1900 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
e4c93c81
DP		 1901 case NETXEN_BRDTYPE_P3_10G_XFP:
1902 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1e2d0059 1903 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1904 break;
1905 case NETXEN_BRDTYPE_P1_BD:
1906 case NETXEN_BRDTYPE_P1_SB:
1907 case NETXEN_BRDTYPE_P1_SMAX:
1908 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 1909 case NETXEN_BRDTYPE_P3_REF_QG:
1910 case NETXEN_BRDTYPE_P3_4_GB:
1911 case NETXEN_BRDTYPE_P3_4_GB_MM:
1e2d0059 1912 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1 1913 break;
c7860a2a 1914 case NETXEN_BRDTYPE_P3_10G_TP:
1e2d0059 1915 adapter->ahw.port_type = (adapter->portnum < 2) ?
c7860a2a
DP		 1916 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1917 break;
3d396eb1 1918 default:
1e2d0059
DP		 1919 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1920 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1921 break;
1922 }
1923
1e2d0059 1924 return 0;
3d396eb1
AK		 1925}
1926
1927/* NIU access sections */
1928
3176ff3e 1929int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1930{
9ad27643 1931 new_mtu += MTU_FUDGE_FACTOR;
f98a9f69 1932 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
3276fbad 1933 new_mtu);
3d396eb1
AK		 1934 return 0;
1935}
1936
3176ff3e 1937int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1938{
9ad27643 1939 new_mtu += MTU_FUDGE_FACTOR;
3276fbad 1940 if (adapter->physical_port == 0)
f98a9f69 1941 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
4790654c 1942 else
f98a9f69 1943 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
3d396eb1
AK		 1944 return 0;
1945}
1946
3176ff3e 1947void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 1948{
a608ab9c
AV		 1949 __u32 status;
1950 __u32 autoneg;
24a7a455 1951 __u32 port_mode;
3d396eb1 1952
c7860a2a
DP		 1953 if (!netif_carrier_ok(adapter->netdev)) {
1954 adapter->link_speed = 0;
1955 adapter->link_duplex = -1;
1956 adapter->link_autoneg = AUTONEG_ENABLE;
1957 return;
1958 }
24a7a455 1959
1e2d0059 1960 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
f98a9f69 1961 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
24a7a455
DP		 1962 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1963 adapter->link_speed = SPEED_1000;
1964 adapter->link_duplex = DUPLEX_FULL;
1965 adapter->link_autoneg = AUTONEG_DISABLE;
1966 return;
1967 }
1968
80922fbc 1969 if (adapter->phy_read
24a7a455 1970 && adapter->phy_read(adapter,
3d396eb1
AK		 1971 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1972 &status) == 0) {
1973 if (netxen_get_phy_link(status)) {
1974 switch (netxen_get_phy_speed(status)) {
1975 case 0:
3176ff3e 1976 adapter->link_speed = SPEED_10;
3d396eb1
AK		 1977 break;
1978 case 1:
3176ff3e 1979 adapter->link_speed = SPEED_100;
3d396eb1
AK		 1980 break;
1981 case 2:
3176ff3e 1982 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 1983 break;
1984 default:
c7860a2a 1985 adapter->link_speed = 0;
3d396eb1
AK		 1986 break;
1987 }
1988 switch (netxen_get_phy_duplex(status)) {
1989 case 0:
3176ff3e 1990 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 1991 break;
1992 case 1:
3176ff3e 1993 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 1994 break;
1995 default:
3176ff3e 1996 adapter->link_duplex = -1;
3d396eb1
AK		 1997 break;
1998 }
80922fbc 1999 if (adapter->phy_read
24a7a455 2000 && adapter->phy_read(adapter,
3d396eb1 2001 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
ed25ffa1 2002 &autoneg) != 0)
3176ff3e 2003 adapter->link_autoneg = autoneg;
3d396eb1
AK		 2004 } else
2005 goto link_down;
2006 } else {
2007 link_down:
c7860a2a 2008 adapter->link_speed = 0;
3176ff3e 2009 adapter->link_duplex = -1;
3d396eb1
AK		 2010 }
2011 }
2012}
2013
1e2d0059 2014void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
3d396eb1 2015{
1e2d0059 2016 u32 fw_major, fw_minor, fw_build;
cb8011ad 2017 char brd_name[NETXEN_MAX_SHORT_NAME];
8d74849b 2018 char serial_num[32];
06db58c0 2019 int i, offset, val;
d8313ce0 2020 int *ptr32;
1e2d0059 2021 struct pci_dev *pdev = adapter->pdev;
dcd56fdb
DP		 2022
2023 adapter->driver_mismatch = 0;
2024
d8313ce0 2025 ptr32 = (int *)&serial_num;
06db58c0 2026 offset = NX_FW_SERIAL_NUM_OFFSET;
dcd56fdb 2027 for (i = 0; i < 8; i++) {
06db58c0 2028 if (netxen_rom_fast_read(adapter, offset, &val) == -1) {
fbb52f22 2029 dev_err(&pdev->dev, "error reading board info\n");
dcd56fdb
DP		 2030 adapter->driver_mismatch = 1;
2031 return;
cb8011ad 2032 }
fbb52f22 2033 ptr32[i] = cpu_to_le32(val);
06db58c0 2034 offset += sizeof(u32);
dcd56fdb
DP		 2035 }
2036
f98a9f69
DP		 2037 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
2038 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
2039 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
8d74849b 2040
1e2d0059 2041 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2956640d 2042
dcd56fdb 2043 if (adapter->portnum == 0) {
1e2d0059 2044 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
cb8011ad 2045
11d89d63
DP		 2046 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2047 brd_name, serial_num, adapter->ahw.revision_id);
3d396eb1 2048 }
dcd56fdb 2049
1e2d0059 2050 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
3d396eb1 2051 adapter->driver_mismatch = 1;
1e2d0059 2052 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
58735567 2053 fw_major, fw_minor, fw_build);
dcd56fdb
DP		 2054 return;
2055 }
1e2d0059
DP		 2056
2057 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2058 fw_major, fw_minor, fw_build);
2059
2060 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
d1733460
DP		 2061 i = NXRD32(adapter, NETXEN_SRE_MISC);
2062 adapter->ahw.cut_through = (i & 0x8000) ? 1 : 0;
1e2d0059
DP		 2063 dev_info(&pdev->dev, "firmware running in %s mode\n",
2064 adapter->ahw.cut_through ? "cut-through" : "legacy");
2065 }
68b3cae0
DP		 2066
2067 if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222))
2068 adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
3d396eb1
AK		 2069}
2070
0b72e659
DP		 2071int
2072netxen_nic_wol_supported(struct netxen_adapter *adapter)
2073{
2074 u32 wol_cfg;
2075
2076 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2077 return 0;
2078
f98a9f69 2079 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
0b72e659 2080 if (wol_cfg & (1UL << adapter->portnum)) {
f98a9f69 2081 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
0b72e659
DP		 2082 if (wol_cfg & (1 << adapter->portnum))
2083 return 1;
2084 }
2085
2086 return 0;
2087}
Ubuntu Hirsute Linux kernel mirror