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netxen: cut-through rx changes
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1
AK		 1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
80922fbc 4 *
3d396eb1
AK		 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
cb8011ad 9 *
3d396eb1
AK		 10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
cb8011ad 14 *
3d396eb1
AK		 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
80922fbc 19 *
3d396eb1
AK		 20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
80922fbc 22 *
3d396eb1
AK		 23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34#include "netxen_nic.h"
35#include "netxen_nic_hw.h"
36#include "netxen_nic_phan_reg.h"
37
3176ff3e 38
c9bdd4b5
ACM		 39#include <net/ip.h>
40
3ce06a32
DP		 41#define MASK(n) ((1ULL<<(n))-1)
42#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44#define MS_WIN(addr) (addr & 0x0ffc0000)
45
46#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
47
48#define CRB_BLK(off) ((off >> 20) & 0x3f)
49#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50#define CRB_WINDOW_2M (0x130060)
51#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52#define CRB_INDIRECT_2M (0x1e0000UL)
53
54#define CRB_WIN_LOCK_TIMEOUT 100000000
55static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
181 {{{0} } }, /* 35: */
182 {{{0} } }, /* 36: */
183 {{{0} } }, /* 37: */
184 {{{0} } }, /* 38: */
185 {{{0} } }, /* 39: */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
198 {{{0} } }, /* 52: */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
210};
211
212/*
213 * top 12 bits of crb internal address (hub, agent)
214 */
215static unsigned crb_hub_agt[64] =
216{
217 0,
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
221 0,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
244 0,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
249 0,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
252 0,
253 0,
254 0,
255 0,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
278 0,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
280 0,
281};
282
3d396eb1
AK		 283/* PCI Windowing for DDR regions. */
284
285#define ADDR_IN_RANGE(addr, low, high) \
286 (((addr) <= (high)) && ((addr) >= (low)))
287
ed25ffa1 288#define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
cb8011ad 289#define NETXEN_MIN_MTU 64
3d396eb1
AK		 290#define NETXEN_ETH_FCS_SIZE 4
291#define NETXEN_ENET_HEADER_SIZE 14
3ce06a32 292#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1
AK		 293#define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
294#define NETXEN_NIU_HDRSIZE (0x1 << 6)
295#define NETXEN_NIU_TLRSIZE (0x1 << 5)
296
cb8011ad
AK		 297#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
298#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
299#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
300#define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
301
302#define NETXEN_NIC_WINDOW_MARGIN 0x100000
303
3d396eb1
AK		 304int netxen_nic_set_mac(struct net_device *netdev, void *p)
305{
3176ff3e 306 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1
AK		 307 struct sockaddr *addr = p;
308
309 if (netif_running(netdev))
310 return -EBUSY;
311
312 if (!is_valid_ether_addr(addr->sa_data))
313 return -EADDRNOTAVAIL;
314
3d396eb1
AK		 315 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
316
c9fc891f
DP		 317 /* For P3, MAC addr is not set in NIU */
318 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
319 if (adapter->macaddr_set)
320 adapter->macaddr_set(adapter, addr->sa_data);
3d396eb1
AK		 321
322 return 0;
323}
324
623621b0
DP		 325#define NETXEN_UNICAST_ADDR(port, index) \
326 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
327#define NETXEN_MCAST_ADDR(port, index) \
328 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
329#define MAC_HI(addr) \
330 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
331#define MAC_LO(addr) \
332 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
333
334static int
335netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
336{
337 u32 val = 0;
338 u16 port = adapter->physical_port;
339 u8 *addr = adapter->netdev->dev_addr;
340
341 if (adapter->mc_enabled)
342 return 0;
343
3ce06a32 344 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0 345 val |= (1UL << (28+port));
3ce06a32 346 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0
DP		 347
348 /* add broadcast addr to filter */
349 val = 0xffffff;
350 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
351 netxen_crb_writelit_adapter(adapter,
352 NETXEN_UNICAST_ADDR(port, 0)+4, val);
353
354 /* add station addr to filter */
355 val = MAC_HI(addr);
356 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
357 val = MAC_LO(addr);
358 netxen_crb_writelit_adapter(adapter,
359 NETXEN_UNICAST_ADDR(port, 1)+4, val);
360
361 adapter->mc_enabled = 1;
362 return 0;
363}
364
365static int
366netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
367{
368 u32 val = 0;
369 u16 port = adapter->physical_port;
370 u8 *addr = adapter->netdev->dev_addr;
371
372 if (!adapter->mc_enabled)
373 return 0;
374
3ce06a32 375 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0 376 val &= ~(1UL << (28+port));
3ce06a32 377 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
623621b0
DP		 378
379 val = MAC_HI(addr);
380 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
381 val = MAC_LO(addr);
382 netxen_crb_writelit_adapter(adapter,
383 NETXEN_UNICAST_ADDR(port, 0)+4, val);
384
385 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
386 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
387
388 adapter->mc_enabled = 0;
389 return 0;
390}
391
392static int
393netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
394 int index, u8 *addr)
395{
396 u32 hi = 0, lo = 0;
397 u16 port = adapter->physical_port;
398
399 lo = MAC_LO(addr);
400 hi = MAC_HI(addr);
401
402 netxen_crb_writelit_adapter(adapter,
403 NETXEN_MCAST_ADDR(port, index), hi);
404 netxen_crb_writelit_adapter(adapter,
405 NETXEN_MCAST_ADDR(port, index)+4, lo);
406
407 return 0;
408}
409
c9fc891f 410void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 411{
3176ff3e 412 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1 413 struct dev_mc_list *mc_ptr;
623621b0
DP		 414 u8 null_addr[6];
415 int index = 0;
416
417 memset(null_addr, 0, 6);
3d396eb1 418
3d396eb1 419 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 420
421 adapter->set_promisc(adapter,
422 NETXEN_NIU_PROMISC_MODE);
423
424 /* Full promiscuous mode */
425 netxen_nic_disable_mcast_filter(adapter);
426
427 return;
428 }
429
430 if (netdev->mc_count == 0) {
431 adapter->set_promisc(adapter,
432 NETXEN_NIU_NON_PROMISC_MODE);
433 netxen_nic_disable_mcast_filter(adapter);
434 return;
435 }
436
437 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
438 if (netdev->flags & IFF_ALLMULTI ||
439 netdev->mc_count > adapter->max_mc_count) {
440 netxen_nic_disable_mcast_filter(adapter);
441 return;
3d396eb1 442 }
623621b0
DP		 443
444 netxen_nic_enable_mcast_filter(adapter);
445
446 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
447 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
448
449 if (index != netdev->mc_count)
450 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
451 netxen_nic_driver_name, netdev->name);
452
453 /* Clear out remaining addresses */
454 for (; index < adapter->max_mc_count; index++)
455 netxen_nic_set_mcast_addr(adapter, index, null_addr);
3d396eb1
AK		 456}
457
c9fc891f
DP		 458static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
459 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
460{
461 nx_mac_list_t *cur, *prev;
462
463 /* if in del_list, move it to adapter->mac_list */
464 for (cur = *del_list, prev = NULL; cur;) {
465 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
466 if (prev == NULL)
467 *del_list = cur->next;
468 else
469 prev->next = cur->next;
470 cur->next = adapter->mac_list;
471 adapter->mac_list = cur;
472 return 0;
473 }
474 prev = cur;
475 cur = cur->next;
476 }
477
478 /* make sure to add each mac address only once */
479 for (cur = adapter->mac_list; cur; cur = cur->next) {
480 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
481 return 0;
482 }
483 /* not in del_list, create new entry and add to add_list */
484 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
485 if (cur == NULL) {
486 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
487 "not work properly from now.\n", __func__);
488 return -1;
489 }
490
491 memcpy(cur->mac_addr, addr, ETH_ALEN);
492 cur->next = *add_list;
493 *add_list = cur;
494 return 0;
495}
496
497static int
498netxen_send_cmd_descs(struct netxen_adapter *adapter,
499 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
500{
501 uint32_t i, producer;
502 struct netxen_cmd_buffer *pbuf;
503 struct cmd_desc_type0 *cmd_desc;
504
505 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
506 printk(KERN_WARNING "%s: Too many command descriptors in a "
507 "request\n", __func__);
508 return -EINVAL;
509 }
510
511 i = 0;
512
513 producer = adapter->cmd_producer;
514 do {
515 cmd_desc = &cmd_desc_arr[i];
516
517 pbuf = &adapter->cmd_buf_arr[producer];
518 pbuf->mss = 0;
519 pbuf->total_length = 0;
520 pbuf->skb = NULL;
521 pbuf->cmd = 0;
522 pbuf->frag_count = 0;
523 pbuf->port = 0;
524
525 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
526 memcpy(&adapter->ahw.cmd_desc_head[producer],
527 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
528
529 producer = get_next_index(producer,
530 adapter->max_tx_desc_count);
531 i++;
532
533 } while (i != nr_elements);
534
535 adapter->cmd_producer = producer;
536
537 /* write producer index to start the xmit */
538
539 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
540
541 return 0;
542}
543
544#define NIC_REQUEST 0x14
545#define NETXEN_MAC_EVENT 0x1
546
547static int nx_p3_sre_macaddr_change(struct net_device *dev,
548 u8 *addr, unsigned op)
549{
550 struct netxen_adapter *adapter = (struct netxen_adapter *)dev->priv;
551 nx_nic_req_t req;
552 nx_mac_req_t mac_req;
553 int rv;
554
555 memset(&req, 0, sizeof(nx_nic_req_t));
556 req.qhdr |= (NIC_REQUEST << 23);
557 req.req_hdr |= NETXEN_MAC_EVENT;
558 req.req_hdr |= ((u64)adapter->portnum << 16);
559 mac_req.op = op;
560 memcpy(&mac_req.mac_addr, addr, 6);
561 req.words[0] = cpu_to_le64(*(u64 *)&mac_req);
562
563 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
564 if (rv != 0) {
565 printk(KERN_ERR "ERROR. Could not send mac update\n");
566 return rv;
567 }
568
569 return 0;
570}
571
572void netxen_p3_nic_set_multi(struct net_device *netdev)
573{
574 struct netxen_adapter *adapter = netdev_priv(netdev);
575 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
576 struct dev_mc_list *mc_ptr;
577 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
578
579 adapter->set_promisc(adapter, NETXEN_NIU_PROMISC_MODE);
580
581 /*
582 * Programming mac addresses will automaticly enabling L2 filtering.
583 * HW will replace timestamp with L2 conid when L2 filtering is
584 * enabled. This causes problem for LSA. Do not enabling L2 filtering
585 * until that problem is fixed.
586 */
587 if ((netdev->flags & IFF_PROMISC) ||
588 (netdev->mc_count > adapter->max_mc_count))
589 return;
590
591 del_list = adapter->mac_list;
592 adapter->mac_list = NULL;
593
594 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
595 if (netdev->mc_count > 0) {
596 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
597 for (mc_ptr = netdev->mc_list; mc_ptr;
598 mc_ptr = mc_ptr->next) {
599 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
600 &add_list, &del_list);
601 }
602 }
603 for (cur = del_list; cur;) {
604 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
605 next = cur->next;
606 kfree(cur);
607 cur = next;
608 }
609 for (cur = add_list; cur;) {
610 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
611 next = cur->next;
612 cur->next = adapter->mac_list;
613 adapter->mac_list = cur;
614 cur = next;
615 }
616}
617
3d396eb1
AK		 618/*
619 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
620 * @returns 0 on success, negative on failure
621 */
c9fc891f
DP		 622
623#define MTU_FUDGE_FACTOR 100
624
3d396eb1
AK		 625int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
626{
3176ff3e 627 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 628 int max_mtu;
3d396eb1 629
c9fc891f
DP		 630 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
631 max_mtu = P3_MAX_MTU;
632 else
633 max_mtu = P2_MAX_MTU;
634
635 if (mtu > max_mtu) {
636 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
637 netdev->name, max_mtu);
3d396eb1
AK		 638 return -EINVAL;
639 }
640
80922fbc 641 if (adapter->set_mtu)
3176ff3e 642 adapter->set_mtu(adapter, mtu);
3d396eb1
AK		 643 netdev->mtu = mtu;
644
c9fc891f
DP		 645 mtu += MTU_FUDGE_FACTOR;
646 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
647 nx_fw_cmd_set_mtu(adapter, mtu);
648 else if (adapter->set_mtu)
649 adapter->set_mtu(adapter, mtu);
650
3d396eb1
AK		 651 return 0;
652}
653
3d396eb1
AK		 654void netxen_tso_check(struct netxen_adapter *adapter,
655 struct cmd_desc_type0 *desc, struct sk_buff *skb)
656{
657 if (desc->mss) {
c9bdd4b5 658 desc->total_hdr_length = (sizeof(struct ethhdr) +
ab6a5bb6 659 ip_hdrlen(skb) + tcp_hdrlen(skb));
ed25ffa1 660 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
c75e86b4 661 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 662 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
ed25ffa1 663 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
eddc9ec5 664 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
ed25ffa1 665 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
3d396eb1
AK		 666 } else {
667 return;
668 }
669 }
ea2ae17d 670 desc->tcp_hdr_offset = skb_transport_offset(skb);
bbe735e4 671 desc->ip_hdr_offset = skb_network_offset(skb);
3d396eb1
AK		 672}
673
674int netxen_is_flash_supported(struct netxen_adapter *adapter)
675{
676 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
677 int addr, val01, val02, i, j;
678
679 /* if the flash size less than 4Mb, make huge war cry and die */
680 for (j = 1; j < 4; j++) {
cb8011ad 681 addr = j * NETXEN_NIC_WINDOW_MARGIN;
ff8ac609 682 for (i = 0; i < ARRAY_SIZE(locs); i++) {
3d396eb1
AK		 683 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
684 && netxen_rom_fast_read(adapter, (addr + locs[i]),
685 &val02) == 0) {
686 if (val01 == val02)
687 return -1;
688 } else
689 return -1;
690 }
691 }
692
693 return 0;
694}
695
696static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 697 int size, __le32 * buf)
3d396eb1
AK		 698{
699 int i, addr;
f305f789
AV		 700 __le32 *ptr32;
701 u32 v;
3d396eb1
AK		 702
703 addr = base;
704 ptr32 = buf;
705 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 706 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 707 return -1;
f305f789 708 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 709 ptr32++;
710 addr += sizeof(u32);
711 }
712 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 713 __le32 local;
714 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 715 return -1;
f305f789 716 local = cpu_to_le32(v);
3d396eb1
AK		 717 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
718 }
719
720 return 0;
721}
722
f305f789 723int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
3d396eb1 724{
f305f789 725 __le32 *pmac = (__le32 *) & mac[0];
3d396eb1
AK		 726
727 if (netxen_get_flash_block(adapter,
0d04761d 728 NETXEN_USER_START +
3d396eb1
AK		 729 offsetof(struct netxen_new_user_info,
730 mac_addr),
731 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
732 return -1;
733 }
f305f789 734 if (*mac == cpu_to_le64(~0ULL)) {
3d396eb1 735 if (netxen_get_flash_block(adapter,
0d04761d 736 NETXEN_USER_START_OLD +
3d396eb1
AK		 737 offsetof(struct netxen_user_old_info,
738 mac_addr),
739 FLASH_NUM_PORTS * sizeof(u64),
740 pmac) == -1)
741 return -1;
f305f789 742 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 743 return -1;
744 }
745 return 0;
746}
747
3ce06a32
DP		 748#define CRB_WIN_LOCK_TIMEOUT 100000000
749
750static int crb_win_lock(struct netxen_adapter *adapter)
751{
752 int done = 0, timeout = 0;
753
754 while (!done) {
755 /* acquire semaphore3 from PCI HW block */
756 adapter->hw_read_wx(adapter,
757 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
758 if (done == 1)
759 break;
760 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
761 return -1;
762 timeout++;
763 udelay(1);
764 }
765 netxen_crb_writelit_adapter(adapter,
766 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
767 return 0;
768}
769
770static void crb_win_unlock(struct netxen_adapter *adapter)
771{
772 int val;
773
774 adapter->hw_read_wx(adapter,
775 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
776}
777
3d396eb1
AK		 778/*
779 * Changes the CRB window to the specified window.
780 */
3ce06a32
DP		 781void
782netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
3d396eb1
AK		 783{
784 void __iomem *offset;
785 u32 tmp;
786 int count = 0;
e4c93c81 787 uint8_t func = adapter->ahw.pci_func;
3d396eb1
AK		 788
789 if (adapter->curr_window == wndw)
790 return;
3d396eb1
AK		 791 /*
792 * Move the CRB window.
793 * We need to write to the "direct access" region of PCI
794 * to avoid a race condition where the window register has
795 * not been successfully written across CRB before the target
796 * register address is received by PCI. The direct region bypasses
797 * the CRB bus.
798 */
e4c93c81
DP		 799 offset = PCI_OFFSET_SECOND_RANGE(adapter,
800 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1
AK		 801
802 if (wndw & 0x1)
803 wndw = NETXEN_WINDOW_ONE;
804
805 writel(wndw, offset);
806
807 /* MUST make sure window is set before we forge on... */
808 while ((tmp = readl(offset)) != wndw) {
809 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
810 "registered properly: 0x%08x.\n",
3ce06a32 811 netxen_nic_driver_name, __func__, tmp);
3d396eb1
AK		 812 mdelay(1);
813 if (count >= 10)
814 break;
815 count++;
816 }
817
6c80b18d
MT		 818 if (wndw == NETXEN_WINDOW_ONE)
819 adapter->curr_window = 1;
820 else
821 adapter->curr_window = 0;
3d396eb1
AK		 822}
823
3ce06a32
DP		 824/*
825 * Return -1 if off is not valid,
826 * 1 if window access is needed. 'off' is set to offset from
827 * CRB space in 128M pci map
828 * 0 if no window access is needed. 'off' is set to 2M addr
829 * In: 'off' is offset from base in 128M pci map
830 */
831static int
832netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
833 ulong *off, int len)
834{
835 unsigned long end = *off + len;
836 crb_128M_2M_sub_block_map_t *m;
837
838
839 if (*off >= NETXEN_CRB_MAX)
840 return -1;
841
842 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
843 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
844 (ulong)adapter->ahw.pci_base0;
845 return 0;
846 }
847
848 if (*off < NETXEN_PCI_CRBSPACE)
849 return -1;
850
851 *off -= NETXEN_PCI_CRBSPACE;
852 end = *off + len;
853
854 /*
855 * Try direct map
856 */
857 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
858
859 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
860 *off = *off + m->start_2M - m->start_128M +
861 (ulong)adapter->ahw.pci_base0;
862 return 0;
863 }
864
865 /*
866 * Not in direct map, use crb window
867 */
868 return 1;
869}
870
871/*
872 * In: 'off' is offset from CRB space in 128M pci map
873 * Out: 'off' is 2M pci map addr
874 * side effect: lock crb window
875 */
876static void
877netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
878{
879 u32 win_read;
880
881 adapter->crb_win = CRB_HI(*off);
882 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
883 adapter->ahw.pci_base0));
884 /*
885 * Read back value to make sure write has gone through before trying
886 * to use it.
887 */
888 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
889 if (win_read != adapter->crb_win) {
890 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
891 "Read crbwin (0x%x), off=0x%lx\n",
892 __func__, adapter->crb_win, win_read, *off);
893 }
894 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
895 (ulong)adapter->ahw.pci_base0;
896}
897
96acb6eb 898int netxen_load_firmware(struct netxen_adapter *adapter)
3d396eb1
AK		 899{
900 int i;
e0e20a1a 901 u32 data, size = 0;
2956640d
DP		 902 u32 flashaddr = NETXEN_BOOTLD_START, memaddr = NETXEN_BOOTLD_START;
903
904 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4;
3d396eb1 905
2956640d
DP		 906 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
907 adapter->pci_write_normalize(adapter,
3ce06a32 908 NETXEN_ROMUSB_GLB_CAS_RST, 1);
3d396eb1
AK		 909
910 for (i = 0; i < size; i++) {
96acb6eb
DP		 911 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
912 return -EIO;
913
3ce06a32 914 adapter->pci_mem_write(adapter, memaddr, &data, 4);
3d396eb1
AK		 915 flashaddr += 4;
916 memaddr += 4;
3ce06a32 917 cond_resched();
3d396eb1 918 }
2956640d
DP		 919 msleep(1);
920
921 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
922 adapter->pci_write_normalize(adapter,
923 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
924 else {
925 adapter->pci_write_normalize(adapter,
3ce06a32 926 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
2956640d 927 adapter->pci_write_normalize(adapter,
3ce06a32 928 NETXEN_ROMUSB_GLB_CAS_RST, 0);
2956640d 929 }
3d396eb1 930
96acb6eb 931 return 0;
3d396eb1
AK		 932}
933
934int
3ce06a32
DP		 935netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
936 ulong off, void *data, int len)
3d396eb1
AK		 937{
938 void __iomem *addr;
939
940 if (ADDR_IN_WINDOW1(off)) {
941 addr = NETXEN_CRB_NORMALIZE(adapter, off);
942 } else { /* Window 0 */
cb8011ad 943 addr = pci_base_offset(adapter, off);
3ce06a32 944 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 945 }
946
947 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
948 " data %llx len %d\n",
cb8011ad 949 pci_base(adapter, off), off, addr,
3d396eb1 950 *(unsigned long long *)data, len);
cb8011ad 951 if (!addr) {
3ce06a32 952 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 953 return 1;
954 }
955
3d396eb1
AK		 956 switch (len) {
957 case 1:
958 writeb(*(u8 *) data, addr);
959 break;
960 case 2:
961 writew(*(u16 *) data, addr);
962 break;
963 case 4:
964 writel(*(u32 *) data, addr);
965 break;
966 case 8:
967 writeq(*(u64 *) data, addr);
968 break;
969 default:
970 DPRINTK(INFO,
971 "writing data %lx to offset %llx, num words=%d\n",
972 *(unsigned long *)data, off, (len >> 3));
973
974 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
975 (len >> 3));
976 break;
977 }
978 if (!ADDR_IN_WINDOW1(off))
3ce06a32 979 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 980
981 return 0;
982}
983
984int
3ce06a32
DP		 985netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
986 ulong off, void *data, int len)
3d396eb1
AK		 987{
988 void __iomem *addr;
989
990 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
991 addr = NETXEN_CRB_NORMALIZE(adapter, off);
992 } else { /* Window 0 */
cb8011ad 993 addr = pci_base_offset(adapter, off);
3ce06a32 994 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 995 }
996
997 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
cb8011ad
AK		 998 pci_base(adapter, off), off, addr);
999 if (!addr) {
3ce06a32 1000 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1001 return 1;
1002 }
3d396eb1
AK		 1003 switch (len) {
1004 case 1:
1005 *(u8 *) data = readb(addr);
1006 break;
1007 case 2:
1008 *(u16 *) data = readw(addr);
1009 break;
1010 case 4:
1011 *(u32 *) data = readl(addr);
1012 break;
1013 case 8:
1014 *(u64 *) data = readq(addr);
1015 break;
1016 default:
1017 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
1018 (len >> 3));
1019 break;
1020 }
1021 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
1022
1023 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1024 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 1025
1026 return 0;
1027}
1028
3ce06a32
DP		 1029int
1030netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1031 ulong off, void *data, int len)
1032{
1033 unsigned long flags = 0;
1034 int rv;
3d396eb1 1035
3ce06a32 1036 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
3d396eb1 1037
3ce06a32
DP		 1038 if (rv == -1) {
1039 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1040 __func__, off);
1041 dump_stack();
1042 return -1;
1043 }
1044
1045 if (rv == 1) {
1046 write_lock_irqsave(&adapter->adapter_lock, flags);
1047 crb_win_lock(adapter);
1048 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1049 }
1050
1051 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1052 *(unsigned long *)data, off, len);
1053
1054 switch (len) {
1055 case 1:
1056 writeb(*(uint8_t *)data, (void *)off);
1057 break;
1058 case 2:
1059 writew(*(uint16_t *)data, (void *)off);
1060 break;
1061 case 4:
1062 writel(*(uint32_t *)data, (void *)off);
1063 break;
1064 case 8:
1065 writeq(*(uint64_t *)data, (void *)off);
1066 break;
1067 default:
1068 DPRINTK(1, INFO,
1069 "writing data %lx to offset %llx, num words=%d\n",
1070 *(unsigned long *)data, off, (len>>3));
1071 break;
1072 }
1073 if (rv == 1) {
1074 crb_win_unlock(adapter);
1075 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1076 }
1077
1078 return 0;
3d396eb1
AK		 1079}
1080
3ce06a32
DP		 1081int
1082netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1083 ulong off, void *data, int len)
1084{
1085 unsigned long flags = 0;
1086 int rv;
3d396eb1 1087
3ce06a32
DP		 1088 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1089
1090 if (rv == -1) {
1091 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1092 __func__, off);
1093 dump_stack();
1094 return -1;
1095 }
1096
1097 if (rv == 1) {
1098 write_lock_irqsave(&adapter->adapter_lock, flags);
1099 crb_win_lock(adapter);
1100 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1101 }
1102
1103 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1104
1105 switch (len) {
1106 case 1:
1107 *(uint8_t *)data = readb((void *)off);
1108 break;
1109 case 2:
1110 *(uint16_t *)data = readw((void *)off);
1111 break;
1112 case 4:
1113 *(uint32_t *)data = readl((void *)off);
1114 break;
1115 case 8:
1116 *(uint64_t *)data = readq((void *)off);
1117 break;
1118 default:
1119 break;
1120 }
1121
1122 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
3d396eb1 1123
3ce06a32
DP		 1124 if (rv == 1) {
1125 crb_win_unlock(adapter);
1126 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1127 }
1128
1129 return 0;
1130}
1131
1132void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1133{
1134 adapter->hw_write_wx(adapter, off, &val, 4);
1135}
1136
1137int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1138{
1139 int val;
1140 adapter->hw_read_wx(adapter, off, &val, 4);
3d396eb1
AK		 1141 return val;
1142}
1143
1144/* Change the window to 0, write and change back to window 1. */
1145void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1146{
3ce06a32 1147 adapter->hw_write_wx(adapter, index, &value, 4);
3d396eb1
AK		 1148}
1149
1150/* Change the window to 0, read and change back to window 1. */
3ce06a32 1151void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
3d396eb1 1152{
3ce06a32
DP		 1153 adapter->hw_read_wx(adapter, index, value, 4);
1154}
3d396eb1 1155
3ce06a32
DP		 1156void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1157{
1158 adapter->hw_write_wx(adapter, index, &value, 4);
1159}
1160
1161void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1162{
1163 adapter->hw_read_wx(adapter, index, value, 4);
1164}
1165
1166/*
1167 * check memory access boundary.
1168 * used by test agent. support ddr access only for now
1169 */
1170static unsigned long
1171netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1172 unsigned long long addr, int size)
1173{
1174 if (!ADDR_IN_RANGE(addr,
1175 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1176 !ADDR_IN_RANGE(addr+size-1,
1177 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1178 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1179 return 0;
1180 }
3d396eb1 1181
3ce06a32 1182 return 1;
3d396eb1
AK		 1183}
1184
4790654c 1185static int netxen_pci_set_window_warning_count;
3d396eb1 1186
3ce06a32
DP		 1187unsigned long
1188netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1189 unsigned long long addr)
3d396eb1 1190{
e4c93c81 1191 void __iomem *offset;
3d396eb1 1192 int window;
3ce06a32 1193 unsigned long long qdr_max;
e4c93c81 1194 uint8_t func = adapter->ahw.pci_func;
3d396eb1 1195
3ce06a32
DP		 1196 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1197 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1198 } else {
1199 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1200 }
1201
3d396eb1
AK		 1202 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1203 /* DDR network side */
1204 addr -= NETXEN_ADDR_DDR_NET;
1205 window = (addr >> 25) & 0x3ff;
3ce06a32
DP		 1206 if (adapter->ahw.ddr_mn_window != window) {
1207 adapter->ahw.ddr_mn_window = window;
e4c93c81
DP		 1208 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1209 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1210 writel(window, offset);
3d396eb1 1211 /* MUST make sure window is set before we forge on... */
e4c93c81 1212 readl(offset);
3d396eb1 1213 }
cb8011ad 1214 addr -= (window * NETXEN_WINDOW_ONE);
3d396eb1
AK		 1215 addr += NETXEN_PCI_DDR_NET;
1216 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1217 addr -= NETXEN_ADDR_OCM0;
1218 addr += NETXEN_PCI_OCM0;
1219 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1220 addr -= NETXEN_ADDR_OCM1;
1221 addr += NETXEN_PCI_OCM1;
3ce06a32 1222 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
3d396eb1
AK		 1223 /* QDR network side */
1224 addr -= NETXEN_ADDR_QDR_NET;
1225 window = (addr >> 22) & 0x3f;
3ce06a32
DP		 1226 if (adapter->ahw.qdr_sn_window != window) {
1227 adapter->ahw.qdr_sn_window = window;
e4c93c81
DP		 1228 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1229 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1230 writel((window << 22), offset);
3d396eb1 1231 /* MUST make sure window is set before we forge on... */
e4c93c81 1232 readl(offset);
3d396eb1
AK		 1233 }
1234 addr -= (window * 0x400000);
1235 addr += NETXEN_PCI_QDR_NET;
1236 } else {
1237 /*
1238 * peg gdb frequently accesses memory that doesn't exist,
1239 * this limits the chit chat so debugging isn't slowed down.
1240 */
1241 if ((netxen_pci_set_window_warning_count++ < 8)
1242 || (netxen_pci_set_window_warning_count % 64 == 0))
1243 printk("%s: Warning:netxen_nic_pci_set_window()"
1244 " Unknown address range!\n",
1245 netxen_nic_driver_name);
3ce06a32
DP		 1246 addr = -1UL;
1247 }
1248 return addr;
1249}
1250
1251/*
1252 * Note : only 32-bit writes!
1253 */
1254int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1255 u64 off, u32 data)
1256{
1257 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1258 return 0;
1259}
1260
1261u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1262{
1263 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1264}
1265
1266void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1267 u64 off, u32 data)
1268{
1269 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1270}
1271
1272u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1273{
1274 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1275}
1276
1277unsigned long
1278netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1279 unsigned long long addr)
1280{
1281 int window;
1282 u32 win_read;
3d396eb1 1283
3ce06a32
DP		 1284 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1285 /* DDR network side */
1286 window = MN_WIN(addr);
1287 adapter->ahw.ddr_mn_window = window;
1288 adapter->hw_write_wx(adapter,
1289 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1290 &window, 4);
1291 adapter->hw_read_wx(adapter,
1292 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1293 &win_read, 4);
1294 if ((win_read << 17) != window) {
1295 printk(KERN_INFO "Written MNwin (0x%x) != "
1296 "Read MNwin (0x%x)\n", window, win_read);
1297 }
1298 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1299 } else if (ADDR_IN_RANGE(addr,
1300 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1301 if ((addr & 0x00ff800) == 0xff800) {
1302 printk("%s: QM access not handled.\n", __func__);
1303 addr = -1UL;
1304 }
1305
1306 window = OCM_WIN(addr);
1307 adapter->ahw.ddr_mn_window = window;
1308 adapter->hw_write_wx(adapter,
1309 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1310 &window, 4);
1311 adapter->hw_read_wx(adapter,
1312 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1313 &win_read, 4);
1314 if ((win_read >> 7) != window) {
1315 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1316 "Read OCMwin (0x%x)\n",
1317 __func__, window, win_read);
1318 }
1319 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1320
1321 } else if (ADDR_IN_RANGE(addr,
1322 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1323 /* QDR network side */
1324 window = MS_WIN(addr);
1325 adapter->ahw.qdr_sn_window = window;
1326 adapter->hw_write_wx(adapter,
1327 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1328 &window, 4);
1329 adapter->hw_read_wx(adapter,
1330 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1331 &win_read, 4);
1332 if (win_read != window) {
1333 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1334 "Read MSwin (0x%x)\n",
1335 __func__, window, win_read);
1336 }
1337 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1338
1339 } else {
1340 /*
1341 * peg gdb frequently accesses memory that doesn't exist,
1342 * this limits the chit chat so debugging isn't slowed down.
1343 */
1344 if ((netxen_pci_set_window_warning_count++ < 8)
1345 || (netxen_pci_set_window_warning_count%64 == 0)) {
1346 printk("%s: Warning:%s Unknown address range!\n",
1347 __func__, netxen_nic_driver_name);
1348}
1349 addr = -1UL;
3d396eb1
AK		 1350 }
1351 return addr;
1352}
1353
3ce06a32
DP		 1354static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1355 unsigned long long addr)
1356{
1357 int window;
1358 unsigned long long qdr_max;
1359
1360 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1361 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1362 else
1363 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1364
1365 if (ADDR_IN_RANGE(addr,
1366 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1367 /* DDR network side */
1368 BUG(); /* MN access can not come here */
1369 } else if (ADDR_IN_RANGE(addr,
1370 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1371 return 1;
1372 } else if (ADDR_IN_RANGE(addr,
1373 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1374 return 1;
1375 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1376 /* QDR network side */
1377 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1378 if (adapter->ahw.qdr_sn_window == window)
1379 return 1;
1380 }
1381
1382 return 0;
1383}
1384
1385static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1386 u64 off, void *data, int size)
1387{
1388 unsigned long flags;
1389 void *addr;
1390 int ret = 0;
1391 u64 start;
1392 uint8_t *mem_ptr = NULL;
1393 unsigned long mem_base;
1394 unsigned long mem_page;
1395
1396 write_lock_irqsave(&adapter->adapter_lock, flags);
1397
1398 /*
1399 * If attempting to access unknown address or straddle hw windows,
1400 * do not access.
1401 */
1402 start = adapter->pci_set_window(adapter, off);
1403 if ((start == -1UL) ||
1404 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1405 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1406 printk(KERN_ERR "%s out of bound pci memory access. "
1407 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1408 return -1;
1409 }
1410
1411 addr = (void *)(pci_base_offset(adapter, start));
1412 if (!addr) {
1413 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1414 mem_base = pci_resource_start(adapter->pdev, 0);
1415 mem_page = start & PAGE_MASK;
1416 /* Map two pages whenever user tries to access addresses in two
1417 consecutive pages.
1418 */
1419 if (mem_page != ((start + size - 1) & PAGE_MASK))
1420 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1421 else
1422 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1423 if (mem_ptr == 0UL) {
1424 *(uint8_t *)data = 0;
1425 return -1;
1426 }
1427 addr = mem_ptr;
1428 addr += start & (PAGE_SIZE - 1);
1429 write_lock_irqsave(&adapter->adapter_lock, flags);
1430 }
1431
1432 switch (size) {
1433 case 1:
1434 *(uint8_t *)data = readb(addr);
1435 break;
1436 case 2:
1437 *(uint16_t *)data = readw(addr);
1438 break;
1439 case 4:
1440 *(uint32_t *)data = readl(addr);
1441 break;
1442 case 8:
1443 *(uint64_t *)data = readq(addr);
1444 break;
1445 default:
1446 ret = -1;
1447 break;
1448 }
1449 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1450 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1451
1452 if (mem_ptr)
1453 iounmap(mem_ptr);
1454 return ret;
1455}
1456
1457static int
1458netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1459 void *data, int size)
1460{
1461 unsigned long flags;
1462 void *addr;
1463 int ret = 0;
1464 u64 start;
1465 uint8_t *mem_ptr = NULL;
1466 unsigned long mem_base;
1467 unsigned long mem_page;
1468
1469 write_lock_irqsave(&adapter->adapter_lock, flags);
1470
1471 /*
1472 * If attempting to access unknown address or straddle hw windows,
1473 * do not access.
1474 */
1475 start = adapter->pci_set_window(adapter, off);
1476 if ((start == -1UL) ||
1477 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1478 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1479 printk(KERN_ERR "%s out of bound pci memory access. "
1480 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1481 return -1;
1482 }
1483
1484 addr = (void *)(pci_base_offset(adapter, start));
1485 if (!addr) {
1486 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1487 mem_base = pci_resource_start(adapter->pdev, 0);
1488 mem_page = start & PAGE_MASK;
1489 /* Map two pages whenever user tries to access addresses in two
1490 * consecutive pages.
1491 */
1492 if (mem_page != ((start + size - 1) & PAGE_MASK))
1493 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1494 else
1495 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1496 if (mem_ptr == 0UL)
1497 return -1;
1498 addr = mem_ptr;
1499 addr += start & (PAGE_SIZE - 1);
1500 write_lock_irqsave(&adapter->adapter_lock, flags);
1501 }
1502
1503 switch (size) {
1504 case 1:
1505 writeb(*(uint8_t *)data, addr);
1506 break;
1507 case 2:
1508 writew(*(uint16_t *)data, addr);
1509 break;
1510 case 4:
1511 writel(*(uint32_t *)data, addr);
1512 break;
1513 case 8:
1514 writeq(*(uint64_t *)data, addr);
1515 break;
1516 default:
1517 ret = -1;
1518 break;
1519 }
1520 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1521 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1522 *(unsigned long long *)data, start);
1523 if (mem_ptr)
1524 iounmap(mem_ptr);
1525 return ret;
1526}
1527
1528#define MAX_CTL_CHECK 1000
1529
1530int
1531netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1532 u64 off, void *data, int size)
1533{
1534 unsigned long flags, mem_crb;
1535 int i, j, ret = 0, loop, sz[2], off0;
1536 uint32_t temp;
1537 uint64_t off8, tmpw, word[2] = {0, 0};
1538
1539 /*
1540 * If not MN, go check for MS or invalid.
1541 */
1542 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1543 return netxen_nic_pci_mem_write_direct(adapter,
1544 off, data, size);
1545
1546 off8 = off & 0xfffffff8;
1547 off0 = off & 0x7;
1548 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1549 sz[1] = size - sz[0];
1550 loop = ((off0 + size - 1) >> 3) + 1;
1551 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1552
1553 if ((size != 8) || (off0 != 0)) {
1554 for (i = 0; i < loop; i++) {
1555 if (adapter->pci_mem_read(adapter,
1556 off8 + (i << 3), &word[i], 8))
1557 return -1;
1558 }
1559 }
1560
1561 switch (size) {
1562 case 1:
1563 tmpw = *((uint8_t *)data);
1564 break;
1565 case 2:
1566 tmpw = *((uint16_t *)data);
1567 break;
1568 case 4:
1569 tmpw = *((uint32_t *)data);
1570 break;
1571 case 8:
1572 default:
1573 tmpw = *((uint64_t *)data);
1574 break;
1575 }
1576 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1577 word[0] |= tmpw << (off0 * 8);
1578
1579 if (loop == 2) {
1580 word[1] &= ~(~0ULL << (sz[1] * 8));
1581 word[1] |= tmpw >> (sz[0] * 8);
1582 }
1583
1584 write_lock_irqsave(&adapter->adapter_lock, flags);
1585 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1586
1587 for (i = 0; i < loop; i++) {
1588 writel((uint32_t)(off8 + (i << 3)),
1589 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1590 writel(0,
1591 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1592 writel(word[i] & 0xffffffff,
1593 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1594 writel((word[i] >> 32) & 0xffffffff,
1595 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1596 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1597 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1598 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1599 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1600
1601 for (j = 0; j < MAX_CTL_CHECK; j++) {
1602 temp = readl(
1603 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1604 if ((temp & MIU_TA_CTL_BUSY) == 0)
1605 break;
1606 }
1607
1608 if (j >= MAX_CTL_CHECK) {
1609 printk("%s: %s Fail to write through agent\n",
1610 __func__, netxen_nic_driver_name);
1611 ret = -1;
1612 break;
1613 }
1614 }
1615
1616 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1617 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1618 return ret;
1619}
1620
1621int
1622netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1623 u64 off, void *data, int size)
1624{
1625 unsigned long flags, mem_crb;
1626 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1627 uint32_t temp;
1628 uint64_t off8, val, word[2] = {0, 0};
1629
1630
1631 /*
1632 * If not MN, go check for MS or invalid.
1633 */
1634 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1635 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1636
1637 off8 = off & 0xfffffff8;
1638 off0[0] = off & 0x7;
1639 off0[1] = 0;
1640 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1641 sz[1] = size - sz[0];
1642 loop = ((off0[0] + size - 1) >> 3) + 1;
1643 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1644
1645 write_lock_irqsave(&adapter->adapter_lock, flags);
1646 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1647
1648 for (i = 0; i < loop; i++) {
1649 writel((uint32_t)(off8 + (i << 3)),
1650 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1651 writel(0,
1652 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1653 writel(MIU_TA_CTL_ENABLE,
1654 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1655 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1656 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1657
1658 for (j = 0; j < MAX_CTL_CHECK; j++) {
1659 temp = readl(
1660 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1661 if ((temp & MIU_TA_CTL_BUSY) == 0)
1662 break;
1663 }
1664
1665 if (j >= MAX_CTL_CHECK) {
1666 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1667 __func__, netxen_nic_driver_name);
1668 break;
1669 }
1670
1671 start = off0[i] >> 2;
1672 end = (off0[i] + sz[i] - 1) >> 2;
1673 for (k = start; k <= end; k++) {
1674 word[i] |= ((uint64_t) readl(
1675 (void *)(mem_crb +
1676 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1677 }
1678 }
1679
1680 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1681 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1682
1683 if (j >= MAX_CTL_CHECK)
1684 return -1;
1685
1686 if (sz[0] == 8) {
1687 val = word[0];
1688 } else {
1689 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1690 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1691 }
1692
1693 switch (size) {
1694 case 1:
1695 *(uint8_t *)data = val;
1696 break;
1697 case 2:
1698 *(uint16_t *)data = val;
1699 break;
1700 case 4:
1701 *(uint32_t *)data = val;
1702 break;
1703 case 8:
1704 *(uint64_t *)data = val;
1705 break;
1706 }
1707 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1708 return 0;
1709}
1710
1711int
1712netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1713 u64 off, void *data, int size)
1714{
1715 int i, j, ret = 0, loop, sz[2], off0;
1716 uint32_t temp;
1717 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1718
1719 /*
1720 * If not MN, go check for MS or invalid.
1721 */
1722 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1723 mem_crb = NETXEN_CRB_QDR_NET;
1724 else {
1725 mem_crb = NETXEN_CRB_DDR_NET;
1726 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1727 return netxen_nic_pci_mem_write_direct(adapter,
1728 off, data, size);
1729 }
1730
1731 off8 = off & 0xfffffff8;
1732 off0 = off & 0x7;
1733 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1734 sz[1] = size - sz[0];
1735 loop = ((off0 + size - 1) >> 3) + 1;
1736
1737 if ((size != 8) || (off0 != 0)) {
1738 for (i = 0; i < loop; i++) {
1739 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1740 &word[i], 8))
1741 return -1;
1742 }
1743 }
1744
1745 switch (size) {
1746 case 1:
1747 tmpw = *((uint8_t *)data);
1748 break;
1749 case 2:
1750 tmpw = *((uint16_t *)data);
1751 break;
1752 case 4:
1753 tmpw = *((uint32_t *)data);
1754 break;
1755 case 8:
1756 default:
1757 tmpw = *((uint64_t *)data);
1758 break;
1759 }
1760
1761 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1762 word[0] |= tmpw << (off0 * 8);
1763
1764 if (loop == 2) {
1765 word[1] &= ~(~0ULL << (sz[1] * 8));
1766 word[1] |= tmpw >> (sz[0] * 8);
1767 }
1768
1769 /*
1770 * don't lock here - write_wx gets the lock if each time
1771 * write_lock_irqsave(&adapter->adapter_lock, flags);
1772 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1773 */
1774
1775 for (i = 0; i < loop; i++) {
1776 temp = off8 + (i << 3);
1777 adapter->hw_write_wx(adapter,
1778 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1779 temp = 0;
1780 adapter->hw_write_wx(adapter,
1781 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1782 temp = word[i] & 0xffffffff;
1783 adapter->hw_write_wx(adapter,
1784 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1785 temp = (word[i] >> 32) & 0xffffffff;
1786 adapter->hw_write_wx(adapter,
1787 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1788 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1789 adapter->hw_write_wx(adapter,
1790 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1791 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1792 adapter->hw_write_wx(adapter,
1793 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1794
1795 for (j = 0; j < MAX_CTL_CHECK; j++) {
1796 adapter->hw_read_wx(adapter,
1797 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1798 if ((temp & MIU_TA_CTL_BUSY) == 0)
1799 break;
1800 }
1801
1802 if (j >= MAX_CTL_CHECK) {
1803 printk(KERN_ERR "%s: Fail to write through agent\n",
1804 netxen_nic_driver_name);
1805 ret = -1;
1806 break;
1807 }
1808 }
1809
1810 /*
1811 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1812 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1813 */
1814 return ret;
1815}
1816
1817int
1818netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1819 u64 off, void *data, int size)
1820{
1821 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1822 uint32_t temp;
1823 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1824
1825 /*
1826 * If not MN, go check for MS or invalid.
1827 */
1828
1829 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1830 mem_crb = NETXEN_CRB_QDR_NET;
1831 else {
1832 mem_crb = NETXEN_CRB_DDR_NET;
1833 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1834 return netxen_nic_pci_mem_read_direct(adapter,
1835 off, data, size);
1836 }
1837
1838 off8 = off & 0xfffffff8;
1839 off0[0] = off & 0x7;
1840 off0[1] = 0;
1841 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1842 sz[1] = size - sz[0];
1843 loop = ((off0[0] + size - 1) >> 3) + 1;
1844
1845 /*
1846 * don't lock here - write_wx gets the lock if each time
1847 * write_lock_irqsave(&adapter->adapter_lock, flags);
1848 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1849 */
1850
1851 for (i = 0; i < loop; i++) {
1852 temp = off8 + (i << 3);
1853 adapter->hw_write_wx(adapter,
1854 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1855 temp = 0;
1856 adapter->hw_write_wx(adapter,
1857 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1858 temp = MIU_TA_CTL_ENABLE;
1859 adapter->hw_write_wx(adapter,
1860 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1861 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1862 adapter->hw_write_wx(adapter,
1863 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1864
1865 for (j = 0; j < MAX_CTL_CHECK; j++) {
1866 adapter->hw_read_wx(adapter,
1867 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1868 if ((temp & MIU_TA_CTL_BUSY) == 0)
1869 break;
1870 }
1871
1872 if (j >= MAX_CTL_CHECK) {
1873 printk(KERN_ERR "%s: Fail to read through agent\n",
1874 netxen_nic_driver_name);
1875 break;
1876 }
1877
1878 start = off0[i] >> 2;
1879 end = (off0[i] + sz[i] - 1) >> 2;
1880 for (k = start; k <= end; k++) {
1881 adapter->hw_read_wx(adapter,
1882 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1883 word[i] |= ((uint64_t)temp << (32 * k));
1884 }
1885 }
1886
1887 /*
1888 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1889 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1890 */
1891
1892 if (j >= MAX_CTL_CHECK)
1893 return -1;
1894
1895 if (sz[0] == 8) {
1896 val = word[0];
1897 } else {
1898 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1899 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1900 }
1901
1902 switch (size) {
1903 case 1:
1904 *(uint8_t *)data = val;
1905 break;
1906 case 2:
1907 *(uint16_t *)data = val;
1908 break;
1909 case 4:
1910 *(uint32_t *)data = val;
1911 break;
1912 case 8:
1913 *(uint64_t *)data = val;
1914 break;
1915 }
1916 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1917 return 0;
1918}
1919
1920/*
1921 * Note : only 32-bit writes!
1922 */
1923int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1924 u64 off, u32 data)
1925{
1926 adapter->hw_write_wx(adapter, off, &data, 4);
1927
1928 return 0;
1929}
1930
1931u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1932{
1933 u32 temp;
1934 adapter->hw_read_wx(adapter, off, &temp, 4);
1935 return temp;
1936}
1937
1938void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1939 u64 off, u32 data)
1940{
1941 adapter->hw_write_wx(adapter, off, &data, 4);
1942}
1943
1944u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
1945{
1946 u32 temp;
1947 adapter->hw_read_wx(adapter, off, &temp, 4);
1948 return temp;
1949}
1950
993fb90c 1951#if 0
13ba9c77
MT		 1952int
1953netxen_nic_erase_pxe(struct netxen_adapter *adapter)
1954{
0d04761d 1955 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
4790654c 1956 printk(KERN_ERR "%s: erase pxe failed\n",
13ba9c77
MT		 1957 netxen_nic_driver_name);
1958 return -1;
1959 }
1960 return 0;
1961}
993fb90c 1962#endif /* 0 */
13ba9c77 1963
3d396eb1
AK		 1964int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1965{
1966 int rv = 0;
0d04761d 1967 int addr = NETXEN_BRDCFG_START;
3d396eb1
AK		 1968 struct netxen_board_info *boardinfo;
1969 int index;
1970 u32 *ptr32;
1971
1972 boardinfo = &adapter->ahw.boardcfg;
1973 ptr32 = (u32 *) boardinfo;
1974
1975 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
1976 index++) {
1977 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1978 return -EIO;
1979 }
1980 ptr32++;
1981 addr += sizeof(u32);
1982 }
1983 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
1984 printk("%s: ERROR reading %s board config."
1985 " Read %x, expected %x\n", netxen_nic_driver_name,
1986 netxen_nic_driver_name,
1987 boardinfo->magic, NETXEN_BDINFO_MAGIC);
1988 rv = -1;
1989 }
1990 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
1991 printk("%s: Unknown board config version."
1992 " Read %x, expected %x\n", netxen_nic_driver_name,
1993 boardinfo->header_version, NETXEN_BDINFO_VERSION);
1994 rv = -1;
1995 }
1996
1997 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
1998 switch ((netxen_brdtype_t) boardinfo->board_type) {
1999 case NETXEN_BRDTYPE_P2_SB35_4G:
2000 adapter->ahw.board_type = NETXEN_NIC_GBE;
2001 break;
2002 case NETXEN_BRDTYPE_P2_SB31_10G:
2003 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2004 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2005 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 2006 case NETXEN_BRDTYPE_P3_HMEZ:
2007 case NETXEN_BRDTYPE_P3_XG_LOM:
2008 case NETXEN_BRDTYPE_P3_10G_CX4:
2009 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2010 case NETXEN_BRDTYPE_P3_IMEZ:
2011 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2012 case NETXEN_BRDTYPE_P3_10G_XFP:
2013 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2014
3d396eb1
AK		 2015 adapter->ahw.board_type = NETXEN_NIC_XGBE;
2016 break;
2017 case NETXEN_BRDTYPE_P1_BD:
2018 case NETXEN_BRDTYPE_P1_SB:
2019 case NETXEN_BRDTYPE_P1_SMAX:
2020 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 2021 case NETXEN_BRDTYPE_P3_REF_QG:
2022 case NETXEN_BRDTYPE_P3_4_GB:
2023 case NETXEN_BRDTYPE_P3_4_GB_MM:
2024
3d396eb1
AK		 2025 adapter->ahw.board_type = NETXEN_NIC_GBE;
2026 break;
2027 default:
2028 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
2029 boardinfo->board_type);
2030 break;
2031 }
2032
2033 return rv;
2034}
2035
2036/* NIU access sections */
2037
3176ff3e 2038int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 2039{
3d396eb1 2040 netxen_nic_write_w0(adapter,
3276fbad
DP		 2041 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2042 new_mtu);
3d396eb1
AK		 2043 return 0;
2044}
2045
3176ff3e 2046int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 2047{
3d396eb1 2048 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
3276fbad 2049 if (adapter->physical_port == 0)
4790654c 2050 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
595e3fb8 2051 new_mtu);
4790654c 2052 else
595e3fb8
MT		 2053 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2054 new_mtu);
3d396eb1
AK		 2055 return 0;
2056}
2057
3d396eb1 2058void
3ce06a32
DP		 2059netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2060 unsigned long off, int data)
3d396eb1 2061{
3ce06a32 2062 adapter->hw_write_wx(adapter, off, &data, 4);
3d396eb1
AK		 2063}
2064
3176ff3e 2065void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 2066{
a608ab9c
AV		 2067 __u32 status;
2068 __u32 autoneg;
2069 __u32 mode;
3d396eb1
AK		 2070
2071 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
2072 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
80922fbc
AK		 2073 if (adapter->phy_read
2074 && adapter->
13ba9c77 2075 phy_read(adapter,
3d396eb1
AK		 2076 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2077 &status) == 0) {
2078 if (netxen_get_phy_link(status)) {
2079 switch (netxen_get_phy_speed(status)) {
2080 case 0:
3176ff3e 2081 adapter->link_speed = SPEED_10;
3d396eb1
AK		 2082 break;
2083 case 1:
3176ff3e 2084 adapter->link_speed = SPEED_100;
3d396eb1
AK		 2085 break;
2086 case 2:
3176ff3e 2087 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 2088 break;
2089 default:
3176ff3e 2090 adapter->link_speed = -1;
3d396eb1
AK		 2091 break;
2092 }
2093 switch (netxen_get_phy_duplex(status)) {
2094 case 0:
3176ff3e 2095 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 2096 break;
2097 case 1:
3176ff3e 2098 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 2099 break;
2100 default:
3176ff3e 2101 adapter->link_duplex = -1;
3d396eb1
AK		 2102 break;
2103 }
80922fbc
AK		 2104 if (adapter->phy_read
2105 && adapter->
13ba9c77 2106 phy_read(adapter,
3d396eb1 2107 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
ed25ffa1 2108 &autoneg) != 0)
3176ff3e 2109 adapter->link_autoneg = autoneg;
3d396eb1
AK		 2110 } else
2111 goto link_down;
2112 } else {
2113 link_down:
3176ff3e
MT		 2114 adapter->link_speed = -1;
2115 adapter->link_duplex = -1;
3d396eb1
AK		 2116 }
2117 }
2118}
2119
2120void netxen_nic_flash_print(struct netxen_adapter *adapter)
2121{
3d396eb1
AK		 2122 u32 fw_major = 0;
2123 u32 fw_minor = 0;
2124 u32 fw_build = 0;
cb8011ad 2125 char brd_name[NETXEN_MAX_SHORT_NAME];
8d74849b
HH		 2126 char serial_num[32];
2127 int i, addr;
6d1495f2 2128 __le32 *ptr32;
3d396eb1
AK		 2129
2130 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
dcd56fdb
DP		 2131
2132 adapter->driver_mismatch = 0;
2133
2134 ptr32 = (u32 *)&serial_num;
2135 addr = NETXEN_USER_START +
2136 offsetof(struct netxen_new_user_info, serial_num);
2137 for (i = 0; i < 8; i++) {
2138 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2139 printk("%s: ERROR reading %s board userarea.\n",
2140 netxen_nic_driver_name,
2141 netxen_nic_driver_name);
2142 adapter->driver_mismatch = 1;
2143 return;
cb8011ad 2144 }
dcd56fdb
DP		 2145 ptr32++;
2146 addr += sizeof(u32);
2147 }
2148
3ce06a32
DP		 2149 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2150 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2151 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
8d74849b 2152
2956640d
DP		 2153 adapter->fw_major = fw_major;
2154
dcd56fdb 2155 if (adapter->portnum == 0) {
cb8011ad
AK		 2156 get_brd_name_by_type(board_info->board_type, brd_name);
2157
2158 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
dcd56fdb
DP		 2159 brd_name, serial_num, board_info->chip_id);
2160 printk("NetXen Firmware version %d.%d.%d\n", fw_major,
2161 fw_minor, fw_build);
3d396eb1 2162 }
dcd56fdb 2163
3d396eb1 2164 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
3d396eb1
AK		 2165 adapter->driver_mismatch = 1;
2166 }
90f8b1d2
AK		 2167 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
2168 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
3d396eb1
AK		 2169 adapter->driver_mismatch = 1;
2170 }
dcd56fdb
DP		 2171 if (adapter->driver_mismatch) {
2172 printk(KERN_ERR "%s: driver and firmware version mismatch\n",
2173 adapter->netdev->name);
2174 return;
2175 }
3d396eb1
AK		 2176}
2177
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