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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
cb8011ad | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
cb8011ad | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | * | |
29 | * | |
30 | * Source file for NIC routines to access the Phantom hardware | |
31 | * | |
32 | */ | |
33 | ||
34 | #include "netxen_nic.h" | |
35 | #include "netxen_nic_hw.h" | |
36 | #include "netxen_nic_phan_reg.h" | |
37 | ||
3176ff3e | 38 | |
c9bdd4b5 ACM |
39 | #include <net/ip.h> |
40 | ||
3176ff3e MT |
41 | struct netxen_recv_crb recv_crb_registers[] = { |
42 | /* | |
43 | * Instance 0. | |
44 | */ | |
45 | { | |
46 | /* rcv_desc_crb: */ | |
47 | { | |
48 | { | |
49 | /* crb_rcv_producer_offset: */ | |
50 | NETXEN_NIC_REG(0x100), | |
51 | /* crb_rcv_consumer_offset: */ | |
52 | NETXEN_NIC_REG(0x104), | |
53 | /* crb_gloablrcv_ring: */ | |
54 | NETXEN_NIC_REG(0x108), | |
55 | /* crb_rcv_ring_size */ | |
56 | NETXEN_NIC_REG(0x10c), | |
57 | ||
58 | }, | |
59 | /* Jumbo frames */ | |
60 | { | |
61 | /* crb_rcv_producer_offset: */ | |
62 | NETXEN_NIC_REG(0x110), | |
63 | /* crb_rcv_consumer_offset: */ | |
64 | NETXEN_NIC_REG(0x114), | |
65 | /* crb_gloablrcv_ring: */ | |
66 | NETXEN_NIC_REG(0x118), | |
67 | /* crb_rcv_ring_size */ | |
68 | NETXEN_NIC_REG(0x11c), | |
69 | }, | |
70 | /* LRO */ | |
71 | { | |
72 | /* crb_rcv_producer_offset: */ | |
73 | NETXEN_NIC_REG(0x120), | |
74 | /* crb_rcv_consumer_offset: */ | |
75 | NETXEN_NIC_REG(0x124), | |
76 | /* crb_gloablrcv_ring: */ | |
77 | NETXEN_NIC_REG(0x128), | |
78 | /* crb_rcv_ring_size */ | |
79 | NETXEN_NIC_REG(0x12c), | |
80 | } | |
81 | }, | |
82 | /* crb_rcvstatus_ring: */ | |
83 | NETXEN_NIC_REG(0x130), | |
84 | /* crb_rcv_status_producer: */ | |
85 | NETXEN_NIC_REG(0x134), | |
86 | /* crb_rcv_status_consumer: */ | |
87 | NETXEN_NIC_REG(0x138), | |
88 | /* crb_rcvpeg_state: */ | |
89 | NETXEN_NIC_REG(0x13c), | |
90 | /* crb_status_ring_size */ | |
91 | NETXEN_NIC_REG(0x140), | |
92 | ||
93 | }, | |
94 | /* | |
95 | * Instance 1, | |
96 | */ | |
97 | { | |
98 | /* rcv_desc_crb: */ | |
99 | { | |
100 | { | |
101 | /* crb_rcv_producer_offset: */ | |
102 | NETXEN_NIC_REG(0x144), | |
103 | /* crb_rcv_consumer_offset: */ | |
104 | NETXEN_NIC_REG(0x148), | |
105 | /* crb_globalrcv_ring: */ | |
106 | NETXEN_NIC_REG(0x14c), | |
107 | /* crb_rcv_ring_size */ | |
108 | NETXEN_NIC_REG(0x150), | |
109 | ||
110 | }, | |
111 | /* Jumbo frames */ | |
112 | { | |
113 | /* crb_rcv_producer_offset: */ | |
114 | NETXEN_NIC_REG(0x154), | |
115 | /* crb_rcv_consumer_offset: */ | |
116 | NETXEN_NIC_REG(0x158), | |
117 | /* crb_globalrcv_ring: */ | |
118 | NETXEN_NIC_REG(0x15c), | |
119 | /* crb_rcv_ring_size */ | |
120 | NETXEN_NIC_REG(0x160), | |
121 | }, | |
122 | /* LRO */ | |
123 | { | |
124 | /* crb_rcv_producer_offset: */ | |
125 | NETXEN_NIC_REG(0x164), | |
126 | /* crb_rcv_consumer_offset: */ | |
127 | NETXEN_NIC_REG(0x168), | |
128 | /* crb_globalrcv_ring: */ | |
129 | NETXEN_NIC_REG(0x16c), | |
130 | /* crb_rcv_ring_size */ | |
131 | NETXEN_NIC_REG(0x170), | |
132 | } | |
133 | ||
134 | }, | |
135 | /* crb_rcvstatus_ring: */ | |
136 | NETXEN_NIC_REG(0x174), | |
137 | /* crb_rcv_status_producer: */ | |
138 | NETXEN_NIC_REG(0x178), | |
139 | /* crb_rcv_status_consumer: */ | |
140 | NETXEN_NIC_REG(0x17c), | |
141 | /* crb_rcvpeg_state: */ | |
142 | NETXEN_NIC_REG(0x180), | |
143 | /* crb_status_ring_size */ | |
144 | NETXEN_NIC_REG(0x184), | |
3176ff3e | 145 | }, |
595e3fb8 | 146 | /* |
6c80b18d | 147 | * Instance 2, |
595e3fb8 MT |
148 | */ |
149 | { | |
150 | { | |
151 | { | |
152 | /* crb_rcv_producer_offset: */ | |
153 | NETXEN_NIC_REG(0x1d8), | |
154 | /* crb_rcv_consumer_offset: */ | |
155 | NETXEN_NIC_REG(0x1dc), | |
156 | /* crb_gloablrcv_ring: */ | |
157 | NETXEN_NIC_REG(0x1f0), | |
158 | /* crb_rcv_ring_size */ | |
159 | NETXEN_NIC_REG(0x1f4), | |
160 | }, | |
161 | /* Jumbo frames */ | |
162 | { | |
4790654c | 163 | /* crb_rcv_producer_offset: */ |
595e3fb8 MT |
164 | NETXEN_NIC_REG(0x1f8), |
165 | /* crb_rcv_consumer_offset: */ | |
166 | NETXEN_NIC_REG(0x1fc), | |
167 | /* crb_gloablrcv_ring: */ | |
168 | NETXEN_NIC_REG(0x200), | |
169 | /* crb_rcv_ring_size */ | |
170 | NETXEN_NIC_REG(0x204), | |
171 | }, | |
172 | /* LRO */ | |
173 | { | |
174 | /* crb_rcv_producer_offset: */ | |
175 | NETXEN_NIC_REG(0x208), | |
176 | /* crb_rcv_consumer_offset: */ | |
177 | NETXEN_NIC_REG(0x20c), | |
178 | /* crb_gloablrcv_ring: */ | |
179 | NETXEN_NIC_REG(0x210), | |
180 | /* crb_rcv_ring_size */ | |
181 | NETXEN_NIC_REG(0x214), | |
182 | } | |
183 | }, | |
184 | /* crb_rcvstatus_ring: */ | |
185 | NETXEN_NIC_REG(0x218), | |
186 | /* crb_rcv_status_producer: */ | |
187 | NETXEN_NIC_REG(0x21c), | |
188 | /* crb_rcv_status_consumer: */ | |
189 | NETXEN_NIC_REG(0x220), | |
190 | /* crb_rcvpeg_state: */ | |
191 | NETXEN_NIC_REG(0x224), | |
192 | /* crb_status_ring_size */ | |
193 | NETXEN_NIC_REG(0x228), | |
194 | }, | |
195 | /* | |
6c80b18d | 196 | * Instance 3, |
595e3fb8 MT |
197 | */ |
198 | { | |
199 | { | |
200 | { | |
201 | /* crb_rcv_producer_offset: */ | |
202 | NETXEN_NIC_REG(0x22c), | |
203 | /* crb_rcv_consumer_offset: */ | |
204 | NETXEN_NIC_REG(0x230), | |
205 | /* crb_gloablrcv_ring: */ | |
206 | NETXEN_NIC_REG(0x234), | |
207 | /* crb_rcv_ring_size */ | |
208 | NETXEN_NIC_REG(0x238), | |
209 | }, | |
210 | /* Jumbo frames */ | |
211 | { | |
4790654c | 212 | /* crb_rcv_producer_offset: */ |
595e3fb8 MT |
213 | NETXEN_NIC_REG(0x23c), |
214 | /* crb_rcv_consumer_offset: */ | |
215 | NETXEN_NIC_REG(0x240), | |
216 | /* crb_gloablrcv_ring: */ | |
217 | NETXEN_NIC_REG(0x244), | |
218 | /* crb_rcv_ring_size */ | |
219 | NETXEN_NIC_REG(0x248), | |
220 | }, | |
221 | /* LRO */ | |
222 | { | |
223 | /* crb_rcv_producer_offset: */ | |
224 | NETXEN_NIC_REG(0x24c), | |
225 | /* crb_rcv_consumer_offset: */ | |
226 | NETXEN_NIC_REG(0x250), | |
227 | /* crb_gloablrcv_ring: */ | |
228 | NETXEN_NIC_REG(0x254), | |
229 | /* crb_rcv_ring_size */ | |
230 | NETXEN_NIC_REG(0x258), | |
231 | } | |
232 | }, | |
233 | /* crb_rcvstatus_ring: */ | |
234 | NETXEN_NIC_REG(0x25c), | |
235 | /* crb_rcv_status_producer: */ | |
236 | NETXEN_NIC_REG(0x260), | |
237 | /* crb_rcv_status_consumer: */ | |
238 | NETXEN_NIC_REG(0x264), | |
239 | /* crb_rcvpeg_state: */ | |
240 | NETXEN_NIC_REG(0x268), | |
241 | /* crb_status_ring_size */ | |
242 | NETXEN_NIC_REG(0x26c), | |
243 | }, | |
3176ff3e MT |
244 | }; |
245 | ||
993fb90c | 246 | static u64 ctx_addr_sig_regs[][3] = { |
3176ff3e MT |
247 | {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)}, |
248 | {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)}, | |
249 | {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)}, | |
250 | {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)} | |
251 | }; | |
993fb90c AB |
252 | #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0]) |
253 | #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2]) | |
254 | #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1]) | |
3176ff3e MT |
255 | |
256 | ||
3d396eb1 AK |
257 | /* PCI Windowing for DDR regions. */ |
258 | ||
259 | #define ADDR_IN_RANGE(addr, low, high) \ | |
260 | (((addr) <= (high)) && ((addr) >= (low))) | |
261 | ||
0d04761d | 262 | #define NETXEN_FLASH_BASE (NETXEN_BOOTLD_START) |
3d396eb1 | 263 | #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE) |
ed25ffa1 | 264 | #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE |
cb8011ad | 265 | #define NETXEN_MIN_MTU 64 |
3d396eb1 AK |
266 | #define NETXEN_ETH_FCS_SIZE 4 |
267 | #define NETXEN_ENET_HEADER_SIZE 14 | |
cb8011ad | 268 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ |
3d396eb1 AK |
269 | #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4) |
270 | #define NETXEN_NIU_HDRSIZE (0x1 << 6) | |
271 | #define NETXEN_NIU_TLRSIZE (0x1 << 5) | |
272 | ||
cb8011ad AK |
273 | #define lower32(x) ((u32)((x) & 0xffffffff)) |
274 | #define upper32(x) \ | |
275 | ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff)) | |
276 | ||
277 | #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL | |
278 | #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL | |
279 | #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL | |
280 | #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL | |
281 | ||
282 | #define NETXEN_NIC_WINDOW_MARGIN 0x100000 | |
283 | ||
993fb90c AB |
284 | static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter, |
285 | unsigned long long addr); | |
3d396eb1 AK |
286 | void netxen_free_hw_resources(struct netxen_adapter *adapter); |
287 | ||
288 | int netxen_nic_set_mac(struct net_device *netdev, void *p) | |
289 | { | |
3176ff3e | 290 | struct netxen_adapter *adapter = netdev_priv(netdev); |
3d396eb1 AK |
291 | struct sockaddr *addr = p; |
292 | ||
293 | if (netif_running(netdev)) | |
294 | return -EBUSY; | |
295 | ||
296 | if (!is_valid_ether_addr(addr->sa_data)) | |
297 | return -EADDRNOTAVAIL; | |
298 | ||
299 | DPRINTK(INFO, "valid ether addr\n"); | |
300 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
301 | ||
80922fbc | 302 | if (adapter->macaddr_set) |
3176ff3e | 303 | adapter->macaddr_set(adapter, addr->sa_data); |
3d396eb1 AK |
304 | |
305 | return 0; | |
306 | } | |
307 | ||
308 | /* | |
309 | * netxen_nic_set_multi - Multicast | |
310 | */ | |
311 | void netxen_nic_set_multi(struct net_device *netdev) | |
312 | { | |
3176ff3e | 313 | struct netxen_adapter *adapter = netdev_priv(netdev); |
3d396eb1 | 314 | struct dev_mc_list *mc_ptr; |
3d396eb1 AK |
315 | |
316 | mc_ptr = netdev->mc_list; | |
317 | if (netdev->flags & IFF_PROMISC) { | |
80922fbc AK |
318 | if (adapter->set_promisc) |
319 | adapter->set_promisc(adapter, | |
80922fbc | 320 | NETXEN_NIU_PROMISC_MODE); |
3d396eb1 | 321 | } else { |
6c80b18d | 322 | if (adapter->unset_promisc) |
80922fbc | 323 | adapter->unset_promisc(adapter, |
80922fbc | 324 | NETXEN_NIU_NON_PROMISC_MODE); |
3d396eb1 | 325 | } |
3d396eb1 AK |
326 | } |
327 | ||
328 | /* | |
329 | * netxen_nic_change_mtu - Change the Maximum Transfer Unit | |
330 | * @returns 0 on success, negative on failure | |
331 | */ | |
332 | int netxen_nic_change_mtu(struct net_device *netdev, int mtu) | |
333 | { | |
3176ff3e | 334 | struct netxen_adapter *adapter = netdev_priv(netdev); |
3d396eb1 AK |
335 | int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE; |
336 | ||
337 | if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) { | |
338 | printk(KERN_ERR "%s: %s %d is not supported.\n", | |
339 | netxen_nic_driver_name, netdev->name, mtu); | |
340 | return -EINVAL; | |
341 | } | |
342 | ||
80922fbc | 343 | if (adapter->set_mtu) |
3176ff3e | 344 | adapter->set_mtu(adapter, mtu); |
3d396eb1 AK |
345 | netdev->mtu = mtu; |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | /* | |
351 | * check if the firmware has been downloaded and ready to run and | |
352 | * setup the address for the descriptors in the adapter | |
353 | */ | |
354 | int netxen_nic_hw_resources(struct netxen_adapter *adapter) | |
355 | { | |
356 | struct netxen_hardware_context *hw = &adapter->ahw; | |
3d396eb1 AK |
357 | u32 state = 0; |
358 | void *addr; | |
359 | int loops = 0, err = 0; | |
360 | int ctx, ring; | |
3d396eb1 AK |
361 | struct netxen_recv_context *recv_ctx; |
362 | struct netxen_rcv_desc_ctx *rcv_desc; | |
595e3fb8 | 363 | int func_id = adapter->portnum; |
3d396eb1 | 364 | |
80922fbc | 365 | DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE, |
cb8011ad | 366 | PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE)); |
80922fbc | 367 | DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM, |
cb8011ad | 368 | pci_base_offset(adapter, NETXEN_CRB_CAM)); |
80922fbc | 369 | DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE, |
cb8011ad | 370 | pci_base_offset(adapter, NETXEN_CAM_RAM_BASE)); |
3d396eb1 | 371 | |
3d396eb1 AK |
372 | |
373 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
374 | DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n"); | |
375 | loops = 0; | |
376 | state = 0; | |
377 | /* Window 1 call */ | |
378 | state = readl(NETXEN_CRB_NORMALIZE(adapter, | |
379 | recv_crb_registers[ctx]. | |
380 | crb_rcvpeg_state)); | |
381 | while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) { | |
96acb6eb | 382 | msleep(1); |
3d396eb1 AK |
383 | /* Window 1 call */ |
384 | state = readl(NETXEN_CRB_NORMALIZE(adapter, | |
385 | recv_crb_registers | |
386 | [ctx]. | |
387 | crb_rcvpeg_state)); | |
388 | loops++; | |
389 | } | |
390 | if (loops >= 20) { | |
391 | printk(KERN_ERR "Rcv Peg initialization not complete:" | |
392 | "%x.\n", state); | |
393 | err = -EIO; | |
394 | return err; | |
395 | } | |
396 | } | |
2d1a3bbd | 397 | adapter->intr_scheme = readl( |
398 | NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW)); | |
443be796 DP |
399 | adapter->msi_mode = readl( |
400 | NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW)); | |
3d396eb1 | 401 | |
cb8011ad | 402 | addr = netxen_alloc(adapter->ahw.pdev, |
ed25ffa1 AK |
403 | sizeof(struct netxen_ring_ctx) + |
404 | sizeof(uint32_t), | |
405 | (dma_addr_t *) & adapter->ctx_desc_phys_addr, | |
406 | &adapter->ctx_desc_pdev); | |
cb8011ad | 407 | |
3d396eb1 AK |
408 | if (addr == NULL) { |
409 | DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); | |
ed25ffa1 AK |
410 | err = -ENOMEM; |
411 | return err; | |
cb8011ad | 412 | } |
ed25ffa1 AK |
413 | memset(addr, 0, sizeof(struct netxen_ring_ctx)); |
414 | adapter->ctx_desc = (struct netxen_ring_ctx *)addr; | |
6c80b18d | 415 | adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum); |
a608ab9c AV |
416 | adapter->ctx_desc->cmd_consumer_offset = |
417 | cpu_to_le64(adapter->ctx_desc_phys_addr + | |
418 | sizeof(struct netxen_ring_ctx)); | |
f305f789 | 419 | adapter->cmd_consumer = (__le32 *) (((char *)addr) + |
ed25ffa1 AK |
420 | sizeof(struct netxen_ring_ctx)); |
421 | ||
9de06610 AK |
422 | addr = netxen_alloc(adapter->ahw.pdev, |
423 | sizeof(struct cmd_desc_type0) * | |
424 | adapter->max_tx_desc_count, | |
425 | (dma_addr_t *) & hw->cmd_desc_phys_addr, | |
426 | &adapter->ahw.cmd_desc_pdev); | |
cb8011ad | 427 | |
ed25ffa1 AK |
428 | if (addr == NULL) { |
429 | DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); | |
430 | netxen_free_hw_resources(adapter); | |
cb8011ad | 431 | return -ENOMEM; |
3d396eb1 AK |
432 | } |
433 | ||
a608ab9c AV |
434 | adapter->ctx_desc->cmd_ring_addr = |
435 | cpu_to_le64(hw->cmd_desc_phys_addr); | |
436 | adapter->ctx_desc->cmd_ring_size = | |
437 | cpu_to_le32(adapter->max_tx_desc_count); | |
3d396eb1 AK |
438 | |
439 | hw->cmd_desc_head = (struct cmd_desc_type0 *)addr; | |
440 | ||
441 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
442 | recv_ctx = &adapter->recv_ctx[ctx]; | |
443 | ||
444 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { | |
445 | rcv_desc = &recv_ctx->rcv_desc[ring]; | |
cb8011ad AK |
446 | addr = netxen_alloc(adapter->ahw.pdev, |
447 | RCV_DESC_RINGSIZE, | |
448 | &rcv_desc->phys_addr, | |
449 | &rcv_desc->phys_pdev); | |
3d396eb1 AK |
450 | if (addr == NULL) { |
451 | DPRINTK(ERR, "bad return from " | |
452 | "pci_alloc_consistent\n"); | |
453 | netxen_free_hw_resources(adapter); | |
454 | err = -ENOMEM; | |
455 | return err; | |
456 | } | |
457 | rcv_desc->desc_head = (struct rcv_desc *)addr; | |
a608ab9c AV |
458 | adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr = |
459 | cpu_to_le64(rcv_desc->phys_addr); | |
ed25ffa1 | 460 | adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size = |
a608ab9c | 461 | cpu_to_le32(rcv_desc->max_rx_desc_count); |
3d396eb1 AK |
462 | } |
463 | ||
71bd7877 AK |
464 | addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE, |
465 | &recv_ctx->rcv_status_desc_phys_addr, | |
cb8011ad | 466 | &recv_ctx->rcv_status_desc_pdev); |
3d396eb1 AK |
467 | if (addr == NULL) { |
468 | DPRINTK(ERR, "bad return from" | |
469 | " pci_alloc_consistent\n"); | |
470 | netxen_free_hw_resources(adapter); | |
471 | err = -ENOMEM; | |
472 | return err; | |
473 | } | |
474 | recv_ctx->rcv_status_desc_head = (struct status_desc *)addr; | |
a608ab9c AV |
475 | adapter->ctx_desc->sts_ring_addr = |
476 | cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr); | |
477 | adapter->ctx_desc->sts_ring_size = | |
478 | cpu_to_le32(adapter->max_rx_desc_count); | |
3d396eb1 | 479 | |
3d396eb1 AK |
480 | } |
481 | /* Window = 1 */ | |
ed25ffa1 AK |
482 | |
483 | writel(lower32(adapter->ctx_desc_phys_addr), | |
595e3fb8 | 484 | NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id))); |
ed25ffa1 | 485 | writel(upper32(adapter->ctx_desc_phys_addr), |
595e3fb8 MT |
486 | NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id))); |
487 | writel(NETXEN_CTX_SIGNATURE | func_id, | |
488 | NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id))); | |
3d396eb1 AK |
489 | return err; |
490 | } | |
491 | ||
492 | void netxen_free_hw_resources(struct netxen_adapter *adapter) | |
493 | { | |
494 | struct netxen_recv_context *recv_ctx; | |
495 | struct netxen_rcv_desc_ctx *rcv_desc; | |
496 | int ctx, ring; | |
497 | ||
ed25ffa1 AK |
498 | if (adapter->ctx_desc != NULL) { |
499 | pci_free_consistent(adapter->ctx_desc_pdev, | |
500 | sizeof(struct netxen_ring_ctx) + | |
501 | sizeof(uint32_t), | |
502 | adapter->ctx_desc, | |
503 | adapter->ctx_desc_phys_addr); | |
504 | adapter->ctx_desc = NULL; | |
505 | } | |
506 | ||
3d396eb1 | 507 | if (adapter->ahw.cmd_desc_head != NULL) { |
cb8011ad | 508 | pci_free_consistent(adapter->ahw.cmd_desc_pdev, |
3d396eb1 AK |
509 | sizeof(struct cmd_desc_type0) * |
510 | adapter->max_tx_desc_count, | |
511 | adapter->ahw.cmd_desc_head, | |
512 | adapter->ahw.cmd_desc_phys_addr); | |
513 | adapter->ahw.cmd_desc_head = NULL; | |
514 | } | |
515 | ||
516 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { | |
517 | recv_ctx = &adapter->recv_ctx[ctx]; | |
518 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { | |
519 | rcv_desc = &recv_ctx->rcv_desc[ring]; | |
520 | ||
521 | if (rcv_desc->desc_head != NULL) { | |
cb8011ad | 522 | pci_free_consistent(rcv_desc->phys_pdev, |
3d396eb1 AK |
523 | RCV_DESC_RINGSIZE, |
524 | rcv_desc->desc_head, | |
525 | rcv_desc->phys_addr); | |
526 | rcv_desc->desc_head = NULL; | |
527 | } | |
528 | } | |
529 | ||
530 | if (recv_ctx->rcv_status_desc_head != NULL) { | |
cb8011ad | 531 | pci_free_consistent(recv_ctx->rcv_status_desc_pdev, |
3d396eb1 AK |
532 | STATUS_DESC_RINGSIZE, |
533 | recv_ctx->rcv_status_desc_head, | |
534 | recv_ctx-> | |
535 | rcv_status_desc_phys_addr); | |
536 | recv_ctx->rcv_status_desc_head = NULL; | |
537 | } | |
538 | } | |
539 | } | |
540 | ||
541 | void netxen_tso_check(struct netxen_adapter *adapter, | |
542 | struct cmd_desc_type0 *desc, struct sk_buff *skb) | |
543 | { | |
544 | if (desc->mss) { | |
c9bdd4b5 | 545 | desc->total_hdr_length = (sizeof(struct ethhdr) + |
ab6a5bb6 | 546 | ip_hdrlen(skb) + tcp_hdrlen(skb)); |
ed25ffa1 | 547 | netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO); |
c75e86b4 | 548 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 | 549 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) { |
ed25ffa1 | 550 | netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT); |
eddc9ec5 | 551 | } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
ed25ffa1 | 552 | netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT); |
3d396eb1 AK |
553 | } else { |
554 | return; | |
555 | } | |
556 | } | |
ea2ae17d | 557 | desc->tcp_hdr_offset = skb_transport_offset(skb); |
bbe735e4 | 558 | desc->ip_hdr_offset = skb_network_offset(skb); |
3d396eb1 AK |
559 | } |
560 | ||
561 | int netxen_is_flash_supported(struct netxen_adapter *adapter) | |
562 | { | |
563 | const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 }; | |
564 | int addr, val01, val02, i, j; | |
565 | ||
566 | /* if the flash size less than 4Mb, make huge war cry and die */ | |
567 | for (j = 1; j < 4; j++) { | |
cb8011ad | 568 | addr = j * NETXEN_NIC_WINDOW_MARGIN; |
ff8ac609 | 569 | for (i = 0; i < ARRAY_SIZE(locs); i++) { |
3d396eb1 AK |
570 | if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0 |
571 | && netxen_rom_fast_read(adapter, (addr + locs[i]), | |
572 | &val02) == 0) { | |
573 | if (val01 == val02) | |
574 | return -1; | |
575 | } else | |
576 | return -1; | |
577 | } | |
578 | } | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
583 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, | |
f305f789 | 584 | int size, __le32 * buf) |
3d396eb1 AK |
585 | { |
586 | int i, addr; | |
f305f789 AV |
587 | __le32 *ptr32; |
588 | u32 v; | |
3d396eb1 AK |
589 | |
590 | addr = base; | |
591 | ptr32 = buf; | |
592 | for (i = 0; i < size / sizeof(u32); i++) { | |
f305f789 | 593 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) |
3d396eb1 | 594 | return -1; |
f305f789 | 595 | *ptr32 = cpu_to_le32(v); |
3d396eb1 AK |
596 | ptr32++; |
597 | addr += sizeof(u32); | |
598 | } | |
599 | if ((char *)buf + size > (char *)ptr32) { | |
f305f789 AV |
600 | __le32 local; |
601 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) | |
3d396eb1 | 602 | return -1; |
f305f789 | 603 | local = cpu_to_le32(v); |
3d396eb1 AK |
604 | memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); |
605 | } | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
f305f789 | 610 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]) |
3d396eb1 | 611 | { |
f305f789 | 612 | __le32 *pmac = (__le32 *) & mac[0]; |
3d396eb1 AK |
613 | |
614 | if (netxen_get_flash_block(adapter, | |
0d04761d | 615 | NETXEN_USER_START + |
3d396eb1 AK |
616 | offsetof(struct netxen_new_user_info, |
617 | mac_addr), | |
618 | FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) { | |
619 | return -1; | |
620 | } | |
f305f789 | 621 | if (*mac == cpu_to_le64(~0ULL)) { |
3d396eb1 | 622 | if (netxen_get_flash_block(adapter, |
0d04761d | 623 | NETXEN_USER_START_OLD + |
3d396eb1 AK |
624 | offsetof(struct netxen_user_old_info, |
625 | mac_addr), | |
626 | FLASH_NUM_PORTS * sizeof(u64), | |
627 | pmac) == -1) | |
628 | return -1; | |
f305f789 | 629 | if (*mac == cpu_to_le64(~0ULL)) |
3d396eb1 AK |
630 | return -1; |
631 | } | |
632 | return 0; | |
633 | } | |
634 | ||
635 | /* | |
636 | * Changes the CRB window to the specified window. | |
637 | */ | |
638 | void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw) | |
639 | { | |
640 | void __iomem *offset; | |
641 | u32 tmp; | |
642 | int count = 0; | |
643 | ||
644 | if (adapter->curr_window == wndw) | |
645 | return; | |
13ba9c77 | 646 | switch(adapter->ahw.pci_func) { |
3176ff3e MT |
647 | case 0: |
648 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
649 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW)); | |
650 | break; | |
651 | case 1: | |
652 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
653 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1)); | |
654 | break; | |
655 | case 2: | |
656 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
657 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2)); | |
658 | break; | |
659 | case 3: | |
660 | offset = PCI_OFFSET_SECOND_RANGE(adapter, | |
661 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3)); | |
662 | break; | |
663 | default: | |
5bc51424 | 664 | printk(KERN_INFO "Changing the window for PCI function " |
13ba9c77 | 665 | "%d\n", adapter->ahw.pci_func); |
3176ff3e MT |
666 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
667 | NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW)); | |
668 | break; | |
669 | } | |
3d396eb1 AK |
670 | /* |
671 | * Move the CRB window. | |
672 | * We need to write to the "direct access" region of PCI | |
673 | * to avoid a race condition where the window register has | |
674 | * not been successfully written across CRB before the target | |
675 | * register address is received by PCI. The direct region bypasses | |
676 | * the CRB bus. | |
677 | */ | |
3d396eb1 AK |
678 | |
679 | if (wndw & 0x1) | |
680 | wndw = NETXEN_WINDOW_ONE; | |
681 | ||
682 | writel(wndw, offset); | |
683 | ||
684 | /* MUST make sure window is set before we forge on... */ | |
685 | while ((tmp = readl(offset)) != wndw) { | |
686 | printk(KERN_WARNING "%s: %s WARNING: CRB window value not " | |
687 | "registered properly: 0x%08x.\n", | |
688 | netxen_nic_driver_name, __FUNCTION__, tmp); | |
689 | mdelay(1); | |
690 | if (count >= 10) | |
691 | break; | |
692 | count++; | |
693 | } | |
694 | ||
6c80b18d MT |
695 | if (wndw == NETXEN_WINDOW_ONE) |
696 | adapter->curr_window = 1; | |
697 | else | |
698 | adapter->curr_window = 0; | |
3d396eb1 AK |
699 | } |
700 | ||
96acb6eb | 701 | int netxen_load_firmware(struct netxen_adapter *adapter) |
3d396eb1 AK |
702 | { |
703 | int i; | |
e0e20a1a LCMT |
704 | u32 data, size = 0; |
705 | u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE; | |
3d396eb1 AK |
706 | u64 off; |
707 | void __iomem *addr; | |
708 | ||
709 | size = NETXEN_FIRMWARE_LEN; | |
710 | writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST)); | |
711 | ||
712 | for (i = 0; i < size; i++) { | |
96acb6eb DP |
713 | int retries = 10; |
714 | if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) | |
715 | return -EIO; | |
716 | ||
cb8011ad AK |
717 | off = netxen_nic_pci_set_window(adapter, memaddr); |
718 | addr = pci_base_offset(adapter, off); | |
3d396eb1 | 719 | writel(data, addr); |
96acb6eb DP |
720 | do { |
721 | if (readl(addr) == data) | |
722 | break; | |
723 | msleep(100); | |
724 | writel(data, addr); | |
725 | } while (--retries); | |
726 | if (!retries) { | |
727 | printk(KERN_ERR "%s: firmware load aborted, write failed at 0x%x\n", | |
728 | netxen_nic_driver_name, memaddr); | |
729 | return -EIO; | |
730 | } | |
3d396eb1 AK |
731 | flashaddr += 4; |
732 | memaddr += 4; | |
733 | } | |
734 | udelay(100); | |
735 | /* make sure Casper is powered on */ | |
736 | writel(0x3fff, | |
737 | NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL)); | |
738 | writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST)); | |
739 | ||
96acb6eb | 740 | return 0; |
3d396eb1 AK |
741 | } |
742 | ||
743 | int | |
744 | netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
745 | int len) | |
746 | { | |
747 | void __iomem *addr; | |
748 | ||
749 | if (ADDR_IN_WINDOW1(off)) { | |
750 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
751 | } else { /* Window 0 */ | |
cb8011ad | 752 | addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
753 | netxen_nic_pci_change_crbwindow(adapter, 0); |
754 | } | |
755 | ||
756 | DPRINTK(INFO, "writing to base %lx offset %llx addr %p" | |
757 | " data %llx len %d\n", | |
cb8011ad | 758 | pci_base(adapter, off), off, addr, |
3d396eb1 | 759 | *(unsigned long long *)data, len); |
cb8011ad AK |
760 | if (!addr) { |
761 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
762 | return 1; | |
763 | } | |
764 | ||
3d396eb1 AK |
765 | switch (len) { |
766 | case 1: | |
767 | writeb(*(u8 *) data, addr); | |
768 | break; | |
769 | case 2: | |
770 | writew(*(u16 *) data, addr); | |
771 | break; | |
772 | case 4: | |
773 | writel(*(u32 *) data, addr); | |
774 | break; | |
775 | case 8: | |
776 | writeq(*(u64 *) data, addr); | |
777 | break; | |
778 | default: | |
779 | DPRINTK(INFO, | |
780 | "writing data %lx to offset %llx, num words=%d\n", | |
781 | *(unsigned long *)data, off, (len >> 3)); | |
782 | ||
783 | netxen_nic_hw_block_write64((u64 __iomem *) data, addr, | |
784 | (len >> 3)); | |
785 | break; | |
786 | } | |
787 | if (!ADDR_IN_WINDOW1(off)) | |
788 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
793 | int | |
794 | netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, | |
795 | int len) | |
796 | { | |
797 | void __iomem *addr; | |
798 | ||
799 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ | |
800 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
801 | } else { /* Window 0 */ | |
cb8011ad | 802 | addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
803 | netxen_nic_pci_change_crbwindow(adapter, 0); |
804 | } | |
805 | ||
806 | DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", | |
cb8011ad AK |
807 | pci_base(adapter, off), off, addr); |
808 | if (!addr) { | |
809 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
810 | return 1; | |
811 | } | |
3d396eb1 AK |
812 | switch (len) { |
813 | case 1: | |
814 | *(u8 *) data = readb(addr); | |
815 | break; | |
816 | case 2: | |
817 | *(u16 *) data = readw(addr); | |
818 | break; | |
819 | case 4: | |
820 | *(u32 *) data = readl(addr); | |
821 | break; | |
822 | case 8: | |
823 | *(u64 *) data = readq(addr); | |
824 | break; | |
825 | default: | |
826 | netxen_nic_hw_block_read64((u64 __iomem *) data, addr, | |
827 | (len >> 3)); | |
828 | break; | |
829 | } | |
830 | DPRINTK(INFO, "read %lx\n", *(unsigned long *)data); | |
831 | ||
832 | if (!ADDR_IN_WINDOW1(off)) | |
833 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
834 | ||
835 | return 0; | |
836 | } | |
837 | ||
838 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val) | |
839 | { /* Only for window 1 */ | |
840 | void __iomem *addr; | |
841 | ||
842 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
843 | DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n", | |
80922fbc | 844 | pci_base(adapter, off), off, addr, val); |
3d396eb1 AK |
845 | writel(val, addr); |
846 | ||
847 | } | |
848 | ||
849 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off) | |
850 | { /* Only for window 1 */ | |
851 | void __iomem *addr; | |
852 | int val; | |
853 | ||
854 | addr = NETXEN_CRB_NORMALIZE(adapter, off); | |
855 | DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", | |
80922fbc | 856 | pci_base(adapter, off), off, addr); |
3d396eb1 AK |
857 | val = readl(addr); |
858 | writel(val, addr); | |
859 | ||
860 | return val; | |
861 | } | |
862 | ||
863 | /* Change the window to 0, write and change back to window 1. */ | |
864 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value) | |
865 | { | |
866 | void __iomem *addr; | |
867 | ||
868 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
71bd7877 | 869 | addr = pci_base_offset(adapter, index); |
3d396eb1 AK |
870 | writel(value, addr); |
871 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
872 | } | |
873 | ||
874 | /* Change the window to 0, read and change back to window 1. */ | |
875 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value) | |
876 | { | |
877 | void __iomem *addr; | |
878 | ||
71bd7877 | 879 | addr = pci_base_offset(adapter, index); |
3d396eb1 AK |
880 | |
881 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
882 | *value = readl(addr); | |
883 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
884 | } | |
885 | ||
4790654c | 886 | static int netxen_pci_set_window_warning_count; |
3d396eb1 | 887 | |
993fb90c AB |
888 | static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter, |
889 | unsigned long long addr) | |
3d396eb1 AK |
890 | { |
891 | static int ddr_mn_window = -1; | |
892 | static int qdr_sn_window = -1; | |
893 | int window; | |
894 | ||
895 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { | |
896 | /* DDR network side */ | |
897 | addr -= NETXEN_ADDR_DDR_NET; | |
898 | window = (addr >> 25) & 0x3ff; | |
899 | if (ddr_mn_window != window) { | |
900 | ddr_mn_window = window; | |
cb8011ad AK |
901 | writel(window, PCI_OFFSET_SECOND_RANGE(adapter, |
902 | NETXEN_PCIX_PH_REG | |
3052246c | 903 | (PCIX_MN_WINDOW(adapter->ahw.pci_func)))); |
3d396eb1 | 904 | /* MUST make sure window is set before we forge on... */ |
cb8011ad AK |
905 | readl(PCI_OFFSET_SECOND_RANGE(adapter, |
906 | NETXEN_PCIX_PH_REG | |
3052246c | 907 | (PCIX_MN_WINDOW(adapter->ahw.pci_func)))); |
3d396eb1 | 908 | } |
cb8011ad | 909 | addr -= (window * NETXEN_WINDOW_ONE); |
3d396eb1 AK |
910 | addr += NETXEN_PCI_DDR_NET; |
911 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { | |
912 | addr -= NETXEN_ADDR_OCM0; | |
913 | addr += NETXEN_PCI_OCM0; | |
914 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { | |
915 | addr -= NETXEN_ADDR_OCM1; | |
916 | addr += NETXEN_PCI_OCM1; | |
917 | } else | |
918 | if (ADDR_IN_RANGE | |
919 | (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) { | |
920 | /* QDR network side */ | |
921 | addr -= NETXEN_ADDR_QDR_NET; | |
922 | window = (addr >> 22) & 0x3f; | |
923 | if (qdr_sn_window != window) { | |
924 | qdr_sn_window = window; | |
cb8011ad AK |
925 | writel((window << 22), |
926 | PCI_OFFSET_SECOND_RANGE(adapter, | |
927 | NETXEN_PCIX_PH_REG | |
3052246c | 928 | (PCIX_SN_WINDOW(adapter->ahw.pci_func)))); |
3d396eb1 | 929 | /* MUST make sure window is set before we forge on... */ |
cb8011ad AK |
930 | readl(PCI_OFFSET_SECOND_RANGE(adapter, |
931 | NETXEN_PCIX_PH_REG | |
3052246c | 932 | (PCIX_SN_WINDOW(adapter->ahw.pci_func)))); |
3d396eb1 AK |
933 | } |
934 | addr -= (window * 0x400000); | |
935 | addr += NETXEN_PCI_QDR_NET; | |
936 | } else { | |
937 | /* | |
938 | * peg gdb frequently accesses memory that doesn't exist, | |
939 | * this limits the chit chat so debugging isn't slowed down. | |
940 | */ | |
941 | if ((netxen_pci_set_window_warning_count++ < 8) | |
942 | || (netxen_pci_set_window_warning_count % 64 == 0)) | |
943 | printk("%s: Warning:netxen_nic_pci_set_window()" | |
944 | " Unknown address range!\n", | |
945 | netxen_nic_driver_name); | |
946 | ||
947 | } | |
948 | return addr; | |
949 | } | |
950 | ||
993fb90c | 951 | #if 0 |
13ba9c77 MT |
952 | int |
953 | netxen_nic_erase_pxe(struct netxen_adapter *adapter) | |
954 | { | |
0d04761d | 955 | if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) { |
4790654c | 956 | printk(KERN_ERR "%s: erase pxe failed\n", |
13ba9c77 MT |
957 | netxen_nic_driver_name); |
958 | return -1; | |
959 | } | |
960 | return 0; | |
961 | } | |
993fb90c | 962 | #endif /* 0 */ |
13ba9c77 | 963 | |
3d396eb1 AK |
964 | int netxen_nic_get_board_info(struct netxen_adapter *adapter) |
965 | { | |
966 | int rv = 0; | |
0d04761d | 967 | int addr = NETXEN_BRDCFG_START; |
3d396eb1 AK |
968 | struct netxen_board_info *boardinfo; |
969 | int index; | |
970 | u32 *ptr32; | |
971 | ||
972 | boardinfo = &adapter->ahw.boardcfg; | |
973 | ptr32 = (u32 *) boardinfo; | |
974 | ||
975 | for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32); | |
976 | index++) { | |
977 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { | |
978 | return -EIO; | |
979 | } | |
980 | ptr32++; | |
981 | addr += sizeof(u32); | |
982 | } | |
983 | if (boardinfo->magic != NETXEN_BDINFO_MAGIC) { | |
984 | printk("%s: ERROR reading %s board config." | |
985 | " Read %x, expected %x\n", netxen_nic_driver_name, | |
986 | netxen_nic_driver_name, | |
987 | boardinfo->magic, NETXEN_BDINFO_MAGIC); | |
988 | rv = -1; | |
989 | } | |
990 | if (boardinfo->header_version != NETXEN_BDINFO_VERSION) { | |
991 | printk("%s: Unknown board config version." | |
992 | " Read %x, expected %x\n", netxen_nic_driver_name, | |
993 | boardinfo->header_version, NETXEN_BDINFO_VERSION); | |
994 | rv = -1; | |
995 | } | |
996 | ||
997 | DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type); | |
998 | switch ((netxen_brdtype_t) boardinfo->board_type) { | |
999 | case NETXEN_BRDTYPE_P2_SB35_4G: | |
1000 | adapter->ahw.board_type = NETXEN_NIC_GBE; | |
1001 | break; | |
1002 | case NETXEN_BRDTYPE_P2_SB31_10G: | |
1003 | case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: | |
1004 | case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: | |
1005 | case NETXEN_BRDTYPE_P2_SB31_10G_CX4: | |
1006 | adapter->ahw.board_type = NETXEN_NIC_XGBE; | |
1007 | break; | |
1008 | case NETXEN_BRDTYPE_P1_BD: | |
1009 | case NETXEN_BRDTYPE_P1_SB: | |
1010 | case NETXEN_BRDTYPE_P1_SMAX: | |
1011 | case NETXEN_BRDTYPE_P1_SOCK: | |
1012 | adapter->ahw.board_type = NETXEN_NIC_GBE; | |
1013 | break; | |
1014 | default: | |
1015 | printk("%s: Unknown(%x)\n", netxen_nic_driver_name, | |
1016 | boardinfo->board_type); | |
1017 | break; | |
1018 | } | |
1019 | ||
1020 | return rv; | |
1021 | } | |
1022 | ||
1023 | /* NIU access sections */ | |
1024 | ||
3176ff3e | 1025 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 1026 | { |
3d396eb1 | 1027 | netxen_nic_write_w0(adapter, |
3276fbad DP |
1028 | NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), |
1029 | new_mtu); | |
3d396eb1 AK |
1030 | return 0; |
1031 | } | |
1032 | ||
3176ff3e | 1033 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) |
3d396eb1 | 1034 | { |
3d396eb1 | 1035 | new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE; |
3276fbad | 1036 | if (adapter->physical_port == 0) |
4790654c | 1037 | netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, |
595e3fb8 | 1038 | new_mtu); |
4790654c | 1039 | else |
595e3fb8 MT |
1040 | netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, |
1041 | new_mtu); | |
3d396eb1 AK |
1042 | return 0; |
1043 | } | |
1044 | ||
1045 | void netxen_nic_init_niu_gb(struct netxen_adapter *adapter) | |
1046 | { | |
3276fbad | 1047 | netxen_niu_gbe_init_port(adapter, adapter->physical_port); |
3d396eb1 AK |
1048 | } |
1049 | ||
1050 | void | |
1051 | netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off, | |
1052 | int data) | |
1053 | { | |
1054 | void __iomem *addr; | |
1055 | ||
1056 | if (ADDR_IN_WINDOW1(off)) { | |
1057 | writel(data, NETXEN_CRB_NORMALIZE(adapter, off)); | |
1058 | } else { | |
1059 | netxen_nic_pci_change_crbwindow(adapter, 0); | |
71bd7877 | 1060 | addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
1061 | writel(data, addr); |
1062 | netxen_nic_pci_change_crbwindow(adapter, 1); | |
1063 | } | |
1064 | } | |
1065 | ||
3176ff3e | 1066 | void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) |
3d396eb1 | 1067 | { |
a608ab9c AV |
1068 | __u32 status; |
1069 | __u32 autoneg; | |
1070 | __u32 mode; | |
3d396eb1 AK |
1071 | |
1072 | netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode); | |
1073 | if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */ | |
80922fbc AK |
1074 | if (adapter->phy_read |
1075 | && adapter-> | |
13ba9c77 | 1076 | phy_read(adapter, |
3d396eb1 AK |
1077 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, |
1078 | &status) == 0) { | |
1079 | if (netxen_get_phy_link(status)) { | |
1080 | switch (netxen_get_phy_speed(status)) { | |
1081 | case 0: | |
3176ff3e | 1082 | adapter->link_speed = SPEED_10; |
3d396eb1 AK |
1083 | break; |
1084 | case 1: | |
3176ff3e | 1085 | adapter->link_speed = SPEED_100; |
3d396eb1 AK |
1086 | break; |
1087 | case 2: | |
3176ff3e | 1088 | adapter->link_speed = SPEED_1000; |
3d396eb1 AK |
1089 | break; |
1090 | default: | |
3176ff3e | 1091 | adapter->link_speed = -1; |
3d396eb1 AK |
1092 | break; |
1093 | } | |
1094 | switch (netxen_get_phy_duplex(status)) { | |
1095 | case 0: | |
3176ff3e | 1096 | adapter->link_duplex = DUPLEX_HALF; |
3d396eb1 AK |
1097 | break; |
1098 | case 1: | |
3176ff3e | 1099 | adapter->link_duplex = DUPLEX_FULL; |
3d396eb1 AK |
1100 | break; |
1101 | default: | |
3176ff3e | 1102 | adapter->link_duplex = -1; |
3d396eb1 AK |
1103 | break; |
1104 | } | |
80922fbc AK |
1105 | if (adapter->phy_read |
1106 | && adapter-> | |
13ba9c77 | 1107 | phy_read(adapter, |
3d396eb1 | 1108 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, |
ed25ffa1 | 1109 | &autoneg) != 0) |
3176ff3e | 1110 | adapter->link_autoneg = autoneg; |
3d396eb1 AK |
1111 | } else |
1112 | goto link_down; | |
1113 | } else { | |
1114 | link_down: | |
3176ff3e MT |
1115 | adapter->link_speed = -1; |
1116 | adapter->link_duplex = -1; | |
3d396eb1 AK |
1117 | } |
1118 | } | |
1119 | } | |
1120 | ||
1121 | void netxen_nic_flash_print(struct netxen_adapter *adapter) | |
1122 | { | |
3d396eb1 AK |
1123 | u32 fw_major = 0; |
1124 | u32 fw_minor = 0; | |
1125 | u32 fw_build = 0; | |
cb8011ad | 1126 | char brd_name[NETXEN_MAX_SHORT_NAME]; |
8d74849b HH |
1127 | char serial_num[32]; |
1128 | int i, addr; | |
6d1495f2 | 1129 | __le32 *ptr32; |
3d396eb1 AK |
1130 | |
1131 | struct netxen_board_info *board_info = &(adapter->ahw.boardcfg); | |
dcd56fdb DP |
1132 | |
1133 | adapter->driver_mismatch = 0; | |
1134 | ||
1135 | ptr32 = (u32 *)&serial_num; | |
1136 | addr = NETXEN_USER_START + | |
1137 | offsetof(struct netxen_new_user_info, serial_num); | |
1138 | for (i = 0; i < 8; i++) { | |
1139 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { | |
1140 | printk("%s: ERROR reading %s board userarea.\n", | |
1141 | netxen_nic_driver_name, | |
1142 | netxen_nic_driver_name); | |
1143 | adapter->driver_mismatch = 1; | |
1144 | return; | |
cb8011ad | 1145 | } |
dcd56fdb DP |
1146 | ptr32++; |
1147 | addr += sizeof(u32); | |
1148 | } | |
1149 | ||
1150 | fw_major = readl(NETXEN_CRB_NORMALIZE(adapter, | |
1151 | NETXEN_FW_VERSION_MAJOR)); | |
1152 | fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter, | |
1153 | NETXEN_FW_VERSION_MINOR)); | |
1154 | fw_build = | |
1155 | readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB)); | |
8d74849b | 1156 | |
dcd56fdb | 1157 | if (adapter->portnum == 0) { |
cb8011ad AK |
1158 | get_brd_name_by_type(board_info->board_type, brd_name); |
1159 | ||
1160 | printk("NetXen %s Board S/N %s Chip id 0x%x\n", | |
dcd56fdb DP |
1161 | brd_name, serial_num, board_info->chip_id); |
1162 | printk("NetXen Firmware version %d.%d.%d\n", fw_major, | |
1163 | fw_minor, fw_build); | |
3d396eb1 | 1164 | } |
dcd56fdb | 1165 | |
3d396eb1 | 1166 | if (fw_major != _NETXEN_NIC_LINUX_MAJOR) { |
3d396eb1 AK |
1167 | adapter->driver_mismatch = 1; |
1168 | } | |
90f8b1d2 AK |
1169 | if (fw_minor != _NETXEN_NIC_LINUX_MINOR && |
1170 | fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) { | |
3d396eb1 AK |
1171 | adapter->driver_mismatch = 1; |
1172 | } | |
dcd56fdb DP |
1173 | if (adapter->driver_mismatch) { |
1174 | printk(KERN_ERR "%s: driver and firmware version mismatch\n", | |
1175 | adapter->netdev->name); | |
1176 | return; | |
1177 | } | |
1178 | ||
1179 | switch (adapter->ahw.board_type) { | |
1180 | case NETXEN_NIC_GBE: | |
1181 | dev_info(&adapter->pdev->dev, "%s: GbE port initialized\n", | |
1182 | adapter->netdev->name); | |
1183 | break; | |
1184 | case NETXEN_NIC_XGBE: | |
1185 | dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n", | |
1186 | adapter->netdev->name); | |
1187 | break; | |
1188 | } | |
3d396eb1 AK |
1189 | } |
1190 |