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[mirror_ubuntu-bionic-kernel.git] / drivers / net / netxen / netxen_nic_init.c
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1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
80922fbc 4 *
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5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
80922fbc 9 *
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10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
80922fbc 14 *
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15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
80922fbc 19 *
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20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
80922fbc 22 *
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23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to initialize the Phantom Hardware
31 *
32 */
33
34#include <linux/netdevice.h>
35#include <linux/delay.h>
36#include "netxen_nic.h"
37#include "netxen_nic_hw.h"
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38#include "netxen_nic_phan_reg.h"
39
40struct crb_addr_pair {
e0e20a1a
LCMT
41 u32 addr;
42 u32 data;
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43};
44
45#define NETXEN_MAX_CRB_XFORM 60
46static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
e0e20a1a 47#define NETXEN_ADDR_ERROR (0xffffffff)
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48
49#define crb_addr_transform(name) \
50 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
51 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
52
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53#define NETXEN_NIC_XDMA_RESET 0x8000ff
54
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55static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
56 uint32_t ctx, uint32_t ringid);
57
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58static void crb_addr_transform_setup(void)
59{
60 crb_addr_transform(XDMA);
61 crb_addr_transform(TIMR);
62 crb_addr_transform(SRE);
63 crb_addr_transform(SQN3);
64 crb_addr_transform(SQN2);
65 crb_addr_transform(SQN1);
66 crb_addr_transform(SQN0);
67 crb_addr_transform(SQS3);
68 crb_addr_transform(SQS2);
69 crb_addr_transform(SQS1);
70 crb_addr_transform(SQS0);
71 crb_addr_transform(RPMX7);
72 crb_addr_transform(RPMX6);
73 crb_addr_transform(RPMX5);
74 crb_addr_transform(RPMX4);
75 crb_addr_transform(RPMX3);
76 crb_addr_transform(RPMX2);
77 crb_addr_transform(RPMX1);
78 crb_addr_transform(RPMX0);
79 crb_addr_transform(ROMUSB);
80 crb_addr_transform(SN);
81 crb_addr_transform(QMN);
82 crb_addr_transform(QMS);
83 crb_addr_transform(PGNI);
84 crb_addr_transform(PGND);
85 crb_addr_transform(PGN3);
86 crb_addr_transform(PGN2);
87 crb_addr_transform(PGN1);
88 crb_addr_transform(PGN0);
89 crb_addr_transform(PGSI);
90 crb_addr_transform(PGSD);
91 crb_addr_transform(PGS3);
92 crb_addr_transform(PGS2);
93 crb_addr_transform(PGS1);
94 crb_addr_transform(PGS0);
95 crb_addr_transform(PS);
96 crb_addr_transform(PH);
97 crb_addr_transform(NIU);
98 crb_addr_transform(I2Q);
99 crb_addr_transform(EG);
100 crb_addr_transform(MN);
101 crb_addr_transform(MS);
102 crb_addr_transform(CAS2);
103 crb_addr_transform(CAS1);
104 crb_addr_transform(CAS0);
105 crb_addr_transform(CAM);
106 crb_addr_transform(C2C1);
107 crb_addr_transform(C2C0);
1fcca1a5 108 crb_addr_transform(SMB);
e4c93c81
DP
109 crb_addr_transform(OCM0);
110 crb_addr_transform(I2C0);
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111}
112
113int netxen_init_firmware(struct netxen_adapter *adapter)
114{
115 u32 state = 0, loops = 0, err = 0;
116
117 /* Window 1 call */
3ce06a32 118 state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
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119
120 if (state == PHAN_INITIALIZE_ACK)
121 return 0;
122
123 while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
2956640d 124 msleep(1);
3d396eb1 125 /* Window 1 call */
3ce06a32 126 state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
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127
128 loops++;
129 }
130 if (loops >= 2000) {
131 printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
132 state);
133 err = -EIO;
134 return err;
135 }
136 /* Window 1 call */
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DP
137 adapter->pci_write_normalize(adapter,
138 CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
139 adapter->pci_write_normalize(adapter,
140 CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
141 adapter->pci_write_normalize(adapter,
142 CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
143 adapter->pci_write_normalize(adapter,
144 CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
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145
146 return err;
147}
148
2956640d 149void netxen_release_rx_buffers(struct netxen_adapter *adapter)
3d396eb1 150{
2956640d 151 struct netxen_recv_context *recv_ctx;
48bfd1e0 152 struct nx_host_rds_ring *rds_ring;
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153 struct netxen_rx_buffer *rx_buf;
154 int i, ctxid, ring;
3d396eb1 155
3d396eb1 156 for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
2956640d 157 recv_ctx = &adapter->recv_ctx[ctxid];
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DP
158 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
159 rds_ring = &recv_ctx->rds_rings[ring];
160 for (i = 0; i < rds_ring->max_rx_desc_count; ++i) {
161 rx_buf = &(rds_ring->rx_buf_arr[i]);
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DP
162 if (rx_buf->state == NETXEN_BUFFER_FREE)
163 continue;
164 pci_unmap_single(adapter->pdev,
165 rx_buf->dma,
48bfd1e0 166 rds_ring->dma_size,
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DP
167 PCI_DMA_FROMDEVICE);
168 if (rx_buf->skb != NULL)
169 dev_kfree_skb_any(rx_buf->skb);
170 }
171 }
172 }
173}
174
175void netxen_release_tx_buffers(struct netxen_adapter *adapter)
176{
177 struct netxen_cmd_buffer *cmd_buf;
178 struct netxen_skb_frag *buffrag;
179 int i, j;
180
181 cmd_buf = adapter->cmd_buf_arr;
182 for (i = 0; i < adapter->max_tx_desc_count; i++) {
183 buffrag = cmd_buf->frag_array;
184 if (buffrag->dma) {
185 pci_unmap_single(adapter->pdev, buffrag->dma,
186 buffrag->length, PCI_DMA_TODEVICE);
187 buffrag->dma = 0ULL;
188 }
189 for (j = 0; j < cmd_buf->frag_count; j++) {
190 buffrag++;
191 if (buffrag->dma) {
192 pci_unmap_page(adapter->pdev, buffrag->dma,
193 buffrag->length,
194 PCI_DMA_TODEVICE);
195 buffrag->dma = 0ULL;
196 }
197 }
198 /* Free the skb we received in netxen_nic_xmit_frame */
199 if (cmd_buf->skb) {
200 dev_kfree_skb_any(cmd_buf->skb);
201 cmd_buf->skb = NULL;
202 }
203 cmd_buf++;
204 }
205}
206
207void netxen_free_sw_resources(struct netxen_adapter *adapter)
208{
209 struct netxen_recv_context *recv_ctx;
48bfd1e0 210 struct nx_host_rds_ring *rds_ring;
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211 int ctx, ring;
212
213 for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
214 recv_ctx = &adapter->recv_ctx[ctx];
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215 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
216 rds_ring = &recv_ctx->rds_rings[ring];
217 if (rds_ring->rx_buf_arr) {
218 vfree(rds_ring->rx_buf_arr);
219 rds_ring->rx_buf_arr = NULL;
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220 }
221 }
222 }
223 if (adapter->cmd_buf_arr)
224 vfree(adapter->cmd_buf_arr);
225 return;
226}
227
228int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
229{
230 struct netxen_recv_context *recv_ctx;
48bfd1e0 231 struct nx_host_rds_ring *rds_ring;
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232 struct netxen_rx_buffer *rx_buf;
233 int ctx, ring, i, num_rx_bufs;
234
235 struct netxen_cmd_buffer *cmd_buf_arr;
236 struct net_device *netdev = adapter->netdev;
237
238 cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
239 if (cmd_buf_arr == NULL) {
240 printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
241 netdev->name);
242 return -ENOMEM;
243 }
244 memset(cmd_buf_arr, 0, TX_RINGSIZE);
245 adapter->cmd_buf_arr = cmd_buf_arr;
246
247 for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
248 recv_ctx = &adapter->recv_ctx[ctx];
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DP
249 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
250 rds_ring = &recv_ctx->rds_rings[ring];
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DP
251 switch (RCV_DESC_TYPE(ring)) {
252 case RCV_DESC_NORMAL:
48bfd1e0 253 rds_ring->max_rx_desc_count =
2956640d 254 adapter->max_rx_desc_count;
48bfd1e0 255 rds_ring->flags = RCV_DESC_NORMAL;
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DP
256 if (adapter->ahw.cut_through) {
257 rds_ring->dma_size =
258 NX_CT_DEFAULT_RX_BUF_LEN;
259 rds_ring->skb_size =
260 NX_CT_DEFAULT_RX_BUF_LEN;
261 } else {
262 rds_ring->dma_size = RX_DMA_MAP_LEN;
263 rds_ring->skb_size =
264 MAX_RX_BUFFER_LENGTH;
265 }
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266 break;
267
268 case RCV_DESC_JUMBO:
48bfd1e0 269 rds_ring->max_rx_desc_count =
2956640d 270 adapter->max_jumbo_rx_desc_count;
48bfd1e0 271 rds_ring->flags = RCV_DESC_JUMBO;
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DP
272 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
273 rds_ring->dma_size =
274 NX_P3_RX_JUMBO_BUF_MAX_LEN;
275 else
276 rds_ring->dma_size =
277 NX_P2_RX_JUMBO_BUF_MAX_LEN;
48bfd1e0 278 rds_ring->skb_size =
d9e651bc 279 rds_ring->dma_size + NET_IP_ALIGN;
2956640d
DP
280 break;
281
282 case RCV_RING_LRO:
48bfd1e0 283 rds_ring->max_rx_desc_count =
2956640d 284 adapter->max_lro_rx_desc_count;
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DP
285 rds_ring->flags = RCV_DESC_LRO;
286 rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
287 rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
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DP
288 break;
289
290 }
48bfd1e0 291 rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
2956640d 292 vmalloc(RCV_BUFFSIZE);
48bfd1e0 293 if (rds_ring->rx_buf_arr == NULL) {
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DP
294 printk(KERN_ERR "%s: Failed to allocate "
295 "rx buffer ring %d\n",
296 netdev->name, ring);
297 /* free whatever was already allocated */
298 goto err_out;
299 }
48bfd1e0 300 memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE);
d9e651bc 301 INIT_LIST_HEAD(&rds_ring->free_list);
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302 /*
303 * Now go through all of them, set reference handles
304 * and put them in the queues.
305 */
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306 num_rx_bufs = rds_ring->max_rx_desc_count;
307 rx_buf = rds_ring->rx_buf_arr;
3d396eb1 308 for (i = 0; i < num_rx_bufs; i++) {
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309 list_add_tail(&rx_buf->list,
310 &rds_ring->free_list);
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311 rx_buf->ref_handle = i;
312 rx_buf->state = NETXEN_BUFFER_FREE;
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313 rx_buf++;
314 }
315 }
316 }
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317
318 return 0;
319
320err_out:
321 netxen_free_sw_resources(adapter);
322 return -ENOMEM;
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323}
324
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325void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
326{
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327 switch (adapter->ahw.board_type) {
328 case NETXEN_NIC_GBE:
80922fbc 329 adapter->enable_phy_interrupts =
3d396eb1 330 netxen_niu_gbe_enable_phy_interrupts;
80922fbc 331 adapter->disable_phy_interrupts =
3d396eb1 332 netxen_niu_gbe_disable_phy_interrupts;
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333 adapter->macaddr_set = netxen_niu_macaddr_set;
334 adapter->set_mtu = netxen_nic_set_mtu_gb;
335 adapter->set_promisc = netxen_niu_set_promiscuous_mode;
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336 adapter->phy_read = netxen_niu_gbe_phy_read;
337 adapter->phy_write = netxen_niu_gbe_phy_write;
c9fc891f 338 adapter->init_port = netxen_niu_gbe_init_port;
80922fbc 339 adapter->stop_port = netxen_niu_disable_gbe_port;
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340 break;
341
342 case NETXEN_NIC_XGBE:
80922fbc 343 adapter->enable_phy_interrupts =
3d396eb1 344 netxen_niu_xgbe_enable_phy_interrupts;
80922fbc 345 adapter->disable_phy_interrupts =
3d396eb1 346 netxen_niu_xgbe_disable_phy_interrupts;
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347 adapter->macaddr_set = netxen_niu_xg_macaddr_set;
348 adapter->set_mtu = netxen_nic_set_mtu_xgb;
349 adapter->init_port = netxen_niu_xg_init_port;
350 adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
80922fbc 351 adapter->stop_port = netxen_niu_disable_xg_port;
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352 break;
353
354 default:
355 break;
356 }
9ad27643
DP
357
358 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
359 adapter->set_mtu = nx_fw_cmd_set_mtu;
360 adapter->set_promisc = netxen_p3_nic_set_promisc;
361 }
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362}
363
364/*
365 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
366 * address to external PCI CRB address.
367 */
993fb90c 368static u32 netxen_decode_crb_addr(u32 addr)
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369{
370 int i;
e0e20a1a 371 u32 base_addr, offset, pci_base;
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372
373 crb_addr_transform_setup();
374
375 pci_base = NETXEN_ADDR_ERROR;
376 base_addr = addr & 0xfff00000;
377 offset = addr & 0x000fffff;
378
379 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
380 if (crb_addr_xform[i] == base_addr) {
381 pci_base = i << 20;
382 break;
383 }
384 }
385 if (pci_base == NETXEN_ADDR_ERROR)
386 return pci_base;
387 else
388 return (pci_base + offset);
389}
390
13ba9c77
MT
391static long rom_max_timeout = 100;
392static long rom_lock_timeout = 10000;
3d396eb1 393
993fb90c 394static int rom_lock(struct netxen_adapter *adapter)
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395{
396 int iter;
397 u32 done = 0;
398 int timeout = 0;
399
400 while (!done) {
401 /* acquire semaphore2 from PCI HW block */
402 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
403 &done);
404 if (done == 1)
405 break;
406 if (timeout >= rom_lock_timeout)
407 return -EIO;
408
409 timeout++;
410 /*
411 * Yield CPU
412 */
413 if (!in_atomic())
414 schedule();
415 else {
416 for (iter = 0; iter < 20; iter++)
417 cpu_relax(); /*This a nop instr on i386 */
418 }
419 }
420 netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
421 return 0;
422}
423
993fb90c 424static int netxen_wait_rom_done(struct netxen_adapter *adapter)
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425{
426 long timeout = 0;
427 long done = 0;
428
27c915a4
DP
429 cond_resched();
430
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431 while (done == 0) {
432 done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
433 done &= 2;
434 timeout++;
435 if (timeout >= rom_max_timeout) {
436 printk("Timeout reached waiting for rom done");
437 return -EIO;
438 }
439 }
440 return 0;
441}
442
993fb90c 443static void netxen_rom_unlock(struct netxen_adapter *adapter)
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444{
445 u32 val;
446
447 /* release semaphore2 */
448 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
449
450}
451
993fb90c
AB
452static int do_rom_fast_read(struct netxen_adapter *adapter,
453 int addr, int *valp)
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454{
455 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
3d396eb1 456 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
27c915a4 457 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
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458 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
459 if (netxen_wait_rom_done(adapter)) {
460 printk("Error waiting for rom done\n");
461 return -EIO;
462 }
463 /* reset abyte_cnt and dummy_byte_cnt */
464 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
27c915a4 465 udelay(10);
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466 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
467
468 *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
469 return 0;
470}
471
993fb90c
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472static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
473 u8 *bytes, size_t size)
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474{
475 int addridx;
476 int ret = 0;
477
478 for (addridx = addr; addridx < (addr + size); addridx += 4) {
f305f789
AV
479 int v;
480 ret = do_rom_fast_read(adapter, addridx, &v);
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481 if (ret != 0)
482 break;
f305f789 483 *(__le32 *)bytes = cpu_to_le32(v);
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484 bytes += 4;
485 }
486
487 return ret;
488}
489
490int
4790654c 491netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
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492 u8 *bytes, size_t size)
493{
494 int ret;
495
496 ret = rom_lock(adapter);
497 if (ret < 0)
498 return ret;
499
500 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
501
502 netxen_rom_unlock(adapter);
503 return ret;
504}
505
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506int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
507{
508 int ret;
509
510 if (rom_lock(adapter) != 0)
511 return -EIO;
512
513 ret = do_rom_fast_read(adapter, addr, valp);
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514 netxen_rom_unlock(adapter);
515 return ret;
516}
517
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518#define NETXEN_BOARDTYPE 0x4008
519#define NETXEN_BOARDNUM 0x400c
520#define NETXEN_CHIPNUM 0x4010
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521
522int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
523{
dcd56fdb 524 int addr, val;
27c915a4 525 int i, n, init_delay = 0;
3d396eb1 526 struct crb_addr_pair *buf;
27c915a4 527 unsigned offset;
e0e20a1a 528 u32 off;
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529
530 /* resetall */
27c915a4 531 rom_lock(adapter);
3d396eb1 532 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
2956640d 533 0xffffffff);
27c915a4 534 netxen_rom_unlock(adapter);
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535
536 if (verbose) {
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537 if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
538 printk("P2 ROM board type: 0x%08x\n", val);
539 else
540 printk("Could not read board type\n");
541 if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
542 printk("P2 ROM board num: 0x%08x\n", val);
543 else
544 printk("Could not read board number\n");
545 if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
546 printk("P2 ROM chip num: 0x%08x\n", val);
547 else
548 printk("Could not read chip number\n");
549 }
550
2956640d
DP
551 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
552 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
27c915a4 553 (n != 0xcafecafe) ||
2956640d
DP
554 netxen_rom_fast_read(adapter, 4, &n) != 0) {
555 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
556 "n: %08x\n", netxen_nic_driver_name, n);
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557 return -EIO;
558 }
2956640d
DP
559 offset = n & 0xffffU;
560 n = (n >> 16) & 0xffffU;
561 } else {
562 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
563 !(n & 0x80000000)) {
564 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
565 "n: %08x\n", netxen_nic_driver_name, n);
566 return -EIO;
3d396eb1 567 }
2956640d
DP
568 offset = 1;
569 n &= ~0x80000000;
570 }
571
572 if (n < 1024) {
573 if (verbose)
574 printk(KERN_DEBUG "%s: %d CRB init values found"
575 " in ROM.\n", netxen_nic_driver_name, n);
576 } else {
577 printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
578 " initialized.\n", __func__, n);
579 return -EIO;
580 }
3d396eb1 581
2956640d
DP
582 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
583 if (buf == NULL) {
584 printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
585 netxen_nic_driver_name);
586 return -ENOMEM;
587 }
588 for (i = 0; i < n; i++) {
589 if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
584dbe94
DM
590 netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
591 kfree(buf);
2956640d 592 return -EIO;
584dbe94 593 }
2956640d
DP
594
595 buf[i].addr = addr;
596 buf[i].data = val;
597
598 if (verbose)
599 printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
600 netxen_nic_driver_name,
601 (u32)netxen_decode_crb_addr(addr), val);
602 }
603 for (i = 0; i < n; i++) {
604
605 off = netxen_decode_crb_addr(buf[i].addr);
606 if (off == NETXEN_ADDR_ERROR) {
607 printk(KERN_ERR"CRB init value out of range %x\n",
1fcca1a5 608 buf[i].addr);
2956640d
DP
609 continue;
610 }
611 off += NETXEN_PCI_CRBSPACE;
612 /* skipping cold reboot MAGIC */
613 if (off == NETXEN_CAM_RAM(0x1fc))
614 continue;
615
616 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
617 /* do not reset PCI */
618 if (off == (ROMUSB_GLB + 0xbc))
1fcca1a5 619 continue;
27c915a4
DP
620 if (off == (ROMUSB_GLB + 0xa8))
621 continue;
622 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
623 continue;
624 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
625 continue;
626 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
627 continue;
2956640d
DP
628 if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
629 buf[i].data = 0x1020;
630 /* skip the function enable register */
631 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
3d396eb1 632 continue;
2956640d
DP
633 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
634 continue;
635 if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
636 continue;
637 }
3d396eb1 638
2956640d
DP
639 if (off == NETXEN_ADDR_ERROR) {
640 printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
641 netxen_nic_driver_name, buf[i].addr);
642 continue;
643 }
644
27c915a4 645 init_delay = 1;
2956640d
DP
646 /* After writing this register, HW needs time for CRB */
647 /* to quiet down (else crb_window returns 0xffffffff) */
648 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
27c915a4 649 init_delay = 1000;
2956640d 650 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
3d396eb1 651 /* hold xdma in reset also */
cb8011ad 652 buf[i].data = NETXEN_NIC_XDMA_RESET;
27c915a4 653 buf[i].data = 0x8000ff;
3d396eb1 654 }
2956640d 655 }
3d396eb1 656
2956640d 657 adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
3d396eb1 658
27c915a4 659 msleep(init_delay);
2956640d
DP
660 }
661 kfree(buf);
3d396eb1 662
2956640d 663 /* disable_peg_cache_all */
3d396eb1 664
2956640d
DP
665 /* unreset_net_cache */
666 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
667 adapter->hw_read_wx(adapter,
668 NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
3d396eb1 669 netxen_crb_writelit_adapter(adapter,
2956640d 670 NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
3d396eb1 671 }
2956640d
DP
672
673 /* p2dn replyCount */
674 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
675 /* disable_peg_cache 0 */
676 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
677 /* disable_peg_cache 1 */
678 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
679
680 /* peg_clr_all */
681
682 /* peg_clr 0 */
683 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
684 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
685 /* peg_clr 1 */
686 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
687 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
688 /* peg_clr 2 */
689 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
690 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
691 /* peg_clr 3 */
692 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
693 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
3d396eb1
AK
694 return 0;
695}
696
ed25ffa1
AK
697int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
698{
699 uint64_t addr;
700 uint32_t hi;
701 uint32_t lo;
702
703 adapter->dummy_dma.addr =
7830b22c 704 pci_alloc_consistent(adapter->pdev,
ed25ffa1
AK
705 NETXEN_HOST_DUMMY_DMA_SIZE,
706 &adapter->dummy_dma.phys_addr);
707 if (adapter->dummy_dma.addr == NULL) {
708 printk("%s: ERROR: Could not allocate dummy DMA memory\n",
2956640d 709 __func__);
ed25ffa1
AK
710 return -ENOMEM;
711 }
712
713 addr = (uint64_t) adapter->dummy_dma.phys_addr;
714 hi = (addr >> 32) & 0xffffffff;
715 lo = addr & 0xffffffff;
716
3ce06a32
DP
717 adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
718 adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
ed25ffa1 719
2956640d
DP
720 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
721 uint32_t temp = 0;
722 adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
723 }
724
ed25ffa1
AK
725 return 0;
726}
727
728void netxen_free_adapter_offload(struct netxen_adapter *adapter)
729{
15eef1e1
DP
730 int i = 100;
731
732 if (!adapter->dummy_dma.addr)
733 return;
439b454e 734
15eef1e1 735 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
439b454e
DP
736 do {
737 if (dma_watchdog_shutdown_request(adapter) == 1)
738 break;
739 msleep(50);
740 if (dma_watchdog_shutdown_poll_result(adapter) == 1)
741 break;
742 } while (--i);
15eef1e1 743 }
439b454e 744
15eef1e1
DP
745 if (i) {
746 pci_free_consistent(adapter->pdev,
747 NETXEN_HOST_DUMMY_DMA_SIZE,
748 adapter->dummy_dma.addr,
749 adapter->dummy_dma.phys_addr);
750 adapter->dummy_dma.addr = NULL;
751 } else {
752 printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
753 adapter->netdev->name);
ed25ffa1
AK
754 }
755}
756
96acb6eb 757int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
3d396eb1
AK
758{
759 u32 val = 0;
2956640d 760 int retries = 60;
3d396eb1 761
cb8011ad 762 if (!pegtune_val) {
96acb6eb 763 do {
3ce06a32
DP
764 val = adapter->pci_read_normalize(adapter,
765 CRB_CMDPEG_STATE);
96acb6eb
DP
766
767 if (val == PHAN_INITIALIZE_COMPLETE ||
768 val == PHAN_INITIALIZE_ACK)
769 return 0;
770
2956640d
DP
771 msleep(500);
772
96acb6eb 773 } while (--retries);
2956640d 774
96acb6eb 775 if (!retries) {
2956640d
DP
776 pegtune_val = adapter->pci_read_normalize(adapter,
777 NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
96acb6eb
DP
778 printk(KERN_WARNING "netxen_phantom_init: init failed, "
779 "pegtune_val=%x\n", pegtune_val);
780 return -1;
3d396eb1 781 }
3d396eb1 782 }
96acb6eb
DP
783
784 return 0;
3d396eb1
AK
785}
786
2956640d
DP
787int netxen_receive_peg_ready(struct netxen_adapter *adapter)
788{
789 u32 val = 0;
790 int retries = 2000;
791
792 do {
793 val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
794
795 if (val == PHAN_PEG_RCV_INITIALIZED)
796 return 0;
797
798 msleep(10);
799
800 } while (--retries);
801
802 if (!retries) {
803 printk(KERN_ERR "Receive Peg initialization not "
804 "complete, state: 0x%x.\n", val);
805 return -EIO;
806 }
807
808 return 0;
809}
810
d9e651bc
DP
811static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
812 struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
813{
814 struct netxen_rx_buffer *buffer;
815 struct sk_buff *skb;
816
817 buffer = &rds_ring->rx_buf_arr[index];
818
819 pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
820 PCI_DMA_FROMDEVICE);
821
822 skb = buffer->skb;
823 if (!skb)
824 goto no_skb;
825
826 if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
827 adapter->stats.csummed++;
828 skb->ip_summed = CHECKSUM_UNNECESSARY;
829 } else
830 skb->ip_summed = CHECKSUM_NONE;
831
832 skb->dev = adapter->netdev;
833
834 buffer->skb = NULL;
835
836no_skb:
837 buffer->state = NETXEN_BUFFER_FREE;
838 buffer->lro_current_frags = 0;
839 buffer->lro_expected_frags = 0;
840 list_add_tail(&buffer->list, &rds_ring->free_list);
841 return skb;
842}
843
3d396eb1
AK
844/*
845 * netxen_process_rcv() send the received packet to the protocol stack.
846 * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
847 * invoke the routine to send more rx buffers to the Phantom...
848 */
993fb90c 849static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
d9e651bc 850 struct status_desc *desc, struct status_desc *frag_desc)
3d396eb1 851{
3176ff3e 852 struct net_device *netdev = adapter->netdev;
5dc16268
DP
853 u64 sts_data = le64_to_cpu(desc->status_desc_data);
854 int index = netxen_get_sts_refhandle(sts_data);
3d396eb1
AK
855 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
856 struct netxen_rx_buffer *buffer;
857 struct sk_buff *skb;
5dc16268 858 u32 length = netxen_get_sts_totallength(sts_data);
3d396eb1 859 u32 desc_ctx;
d9e651bc 860 u16 pkt_offset = 0, cksum;
48bfd1e0 861 struct nx_host_rds_ring *rds_ring;
3d396eb1 862
5dc16268 863 desc_ctx = netxen_get_sts_type(sts_data);
3d396eb1
AK
864 if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
865 printk("%s: %s Bad Rcv descriptor ring\n",
866 netxen_nic_driver_name, netdev->name);
867 return;
868 }
869
48bfd1e0
DP
870 rds_ring = &recv_ctx->rds_rings[desc_ctx];
871 if (unlikely(index > rds_ring->max_rx_desc_count)) {
ed25ffa1 872 DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
48bfd1e0 873 index, rds_ring->max_rx_desc_count);
ed25ffa1
AK
874 return;
875 }
48bfd1e0 876 buffer = &rds_ring->rx_buf_arr[index];
ed25ffa1
AK
877 if (desc_ctx == RCV_DESC_LRO_CTXID) {
878 buffer->lro_current_frags++;
879 if (netxen_get_sts_desc_lro_last_frag(desc)) {
880 buffer->lro_expected_frags =
881 netxen_get_sts_desc_lro_cnt(desc);
882 buffer->lro_length = length;
883 }
884 if (buffer->lro_current_frags != buffer->lro_expected_frags) {
885 if (buffer->lro_expected_frags != 0) {
5bc51424
JP
886 printk("LRO: (refhandle:%x) recv frag. "
887 "wait for last. flags: %x expected:%d "
ed25ffa1
AK
888 "have:%d\n", index,
889 netxen_get_sts_desc_lro_last_frag(desc),
890 buffer->lro_expected_frags,
891 buffer->lro_current_frags);
892 }
893 return;
894 }
895 }
3d396eb1 896
d9e651bc 897 cksum = netxen_get_sts_status(sts_data);
3d396eb1 898
d9e651bc
DP
899 skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
900 if (!skb)
901 return;
200eef20 902
ed25ffa1
AK
903 if (desc_ctx == RCV_DESC_LRO_CTXID) {
904 /* True length was only available on the last pkt */
905 skb_put(skb, buffer->lro_length);
906 } else {
d9e651bc
DP
907 if (length > rds_ring->skb_size)
908 skb_put(skb, rds_ring->skb_size);
909 else
910 skb_put(skb, length);
911
912 pkt_offset = netxen_get_sts_pkt_offset(sts_data);
913 if (pkt_offset)
914 skb_pull(skb, pkt_offset);
ed25ffa1
AK
915 }
916
3d396eb1
AK
917 skb->protocol = eth_type_trans(skb, netdev);
918
3d396eb1 919 /*
d9e651bc
DP
920 * rx buffer chaining is disabled, walk and free
921 * any spurious rx buffer chain.
3d396eb1 922 */
d9e651bc
DP
923 if (frag_desc) {
924 u16 i, nr_frags = desc->nr_frags;
925
926 dev_kfree_skb_any(skb);
927 for (i = 0; i < nr_frags; i++) {
2edbb454 928 index = le16_to_cpu(frag_desc->frag_handles[i]);
d9e651bc
DP
929 skb = netxen_process_rxbuf(adapter,
930 rds_ring, index, cksum);
931 if (skb)
932 dev_kfree_skb_any(skb);
933 }
934 adapter->stats.rxdropped++;
935 } else {
d9e651bc 936 netif_receive_skb(skb);
d9e651bc
DP
937
938 adapter->stats.no_rcv++;
939 adapter->stats.rxbytes += length;
940 }
3d396eb1
AK
941}
942
943/* Process Receive status ring */
944u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
945{
946 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
947 struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
d9e651bc 948 struct status_desc *desc, *frag_desc;
3d396eb1
AK
949 u32 consumer = recv_ctx->status_rx_consumer;
950 int count = 0, ring;
d9e651bc
DP
951 u64 sts_data;
952 u16 opcode;
3d396eb1 953
3d396eb1
AK
954 while (count < max) {
955 desc = &desc_head[consumer];
a608ab9c 956 if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
ed25ffa1
AK
957 DPRINTK(ERR, "desc %p ownedby %x\n", desc,
958 netxen_get_sts_owner(desc));
3d396eb1
AK
959 break;
960 }
d9e651bc
DP
961
962 sts_data = le64_to_cpu(desc->status_desc_data);
963 opcode = netxen_get_sts_opcode(sts_data);
964 frag_desc = NULL;
965 if (opcode == NETXEN_NIC_RXPKT_DESC) {
966 if (desc->nr_frags) {
967 consumer = get_next_index(consumer,
968 adapter->max_rx_desc_count);
969 frag_desc = &desc_head[consumer];
970 netxen_set_sts_owner(frag_desc,
971 STATUS_OWNER_PHANTOM);
972 }
973 }
974
975 netxen_process_rcv(adapter, ctxid, desc, frag_desc);
976
a608ab9c 977 netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
d9e651bc
DP
978
979 consumer = get_next_index(consumer,
980 adapter->max_rx_desc_count);
3d396eb1
AK
981 count++;
982 }
48bfd1e0 983 for (ring = 0; ring < adapter->max_rds_rings; ring++)
05aaa02d 984 netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
3d396eb1
AK
985
986 /* update the consumer index in phantom */
987 if (count) {
3d396eb1
AK
988 recv_ctx->status_rx_consumer = consumer;
989
990 /* Window = 1 */
3ce06a32
DP
991 adapter->pci_write_normalize(adapter,
992 recv_ctx->crb_sts_consumer, consumer);
3d396eb1
AK
993 }
994
995 return count;
996}
997
998/* Process Command status ring */
05aaa02d 999int netxen_process_cmd_ring(struct netxen_adapter *adapter)
3d396eb1 1000{
ba53e6b4
DP
1001 u32 last_consumer, consumer;
1002 int count = 0, i;
3d396eb1 1003 struct netxen_cmd_buffer *buffer;
ba53e6b4
DP
1004 struct pci_dev *pdev = adapter->pdev;
1005 struct net_device *netdev = adapter->netdev;
3d396eb1 1006 struct netxen_skb_frag *frag;
ba53e6b4 1007 int done = 0;
3d396eb1 1008
3d396eb1 1009 last_consumer = adapter->last_cmd_consumer;
9b410117 1010 consumer = le32_to_cpu(*(adapter->cmd_consumer));
3d396eb1 1011
ba53e6b4 1012 while (last_consumer != consumer) {
3d396eb1 1013 buffer = &adapter->cmd_buf_arr[last_consumer];
53a01e00 1014 if (buffer->skb) {
1015 frag = &buffer->frag_array[0];
3d396eb1
AK
1016 pci_unmap_single(pdev, frag->dma, frag->length,
1017 PCI_DMA_TODEVICE);
96acb6eb 1018 frag->dma = 0ULL;
3d396eb1 1019 for (i = 1; i < buffer->frag_count; i++) {
3d396eb1
AK
1020 frag++; /* Get the next frag */
1021 pci_unmap_page(pdev, frag->dma, frag->length,
1022 PCI_DMA_TODEVICE);
96acb6eb 1023 frag->dma = 0ULL;
3d396eb1
AK
1024 }
1025
ba53e6b4 1026 adapter->stats.xmitfinished++;
53a01e00 1027 dev_kfree_skb_any(buffer->skb);
1028 buffer->skb = NULL;
3d396eb1
AK
1029 }
1030
1031 last_consumer = get_next_index(last_consumer,
1032 adapter->max_tx_desc_count);
ba53e6b4
DP
1033 if (++count >= MAX_STATUS_HANDLE)
1034 break;
3d396eb1 1035 }
3d396eb1 1036
ba53e6b4 1037 if (count) {
3d396eb1 1038 adapter->last_cmd_consumer = last_consumer;
ba53e6b4
DP
1039 smp_mb();
1040 if (netif_queue_stopped(netdev) && netif_running(netdev)) {
1041 netif_tx_lock(netdev);
1042 netif_wake_queue(netdev);
1043 smp_mb();
1044 netif_tx_unlock(netdev);
3d396eb1
AK
1045 }
1046 }
ed25ffa1
AK
1047 /*
1048 * If everything is freed up to consumer then check if the ring is full
1049 * If the ring is full then check if more needs to be freed and
1050 * schedule the call back again.
1051 *
1052 * This happens when there are 2 CPUs. One could be freeing and the
1053 * other filling it. If the ring is full when we get out of here and
1054 * the card has already interrupted the host then the host can miss the
1055 * interrupt.
1056 *
1057 * There is still a possible race condition and the host could miss an
1058 * interrupt. The card has to take care of this.
1059 */
ba53e6b4
DP
1060 consumer = le32_to_cpu(*(adapter->cmd_consumer));
1061 done = (last_consumer == consumer);
3d396eb1 1062
ed25ffa1 1063 return (done);
3d396eb1
AK
1064}
1065
1066/*
1067 * netxen_post_rx_buffers puts buffer in the Phantom memory
1068 */
1069void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
1070{
7830b22c 1071 struct pci_dev *pdev = adapter->pdev;
3d396eb1
AK
1072 struct sk_buff *skb;
1073 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
48bfd1e0 1074 struct nx_host_rds_ring *rds_ring = NULL;
ed25ffa1 1075 uint producer;
3d396eb1
AK
1076 struct rcv_desc *pdesc;
1077 struct netxen_rx_buffer *buffer;
1078 int count = 0;
ed25ffa1
AK
1079 netxen_ctx_msg msg = 0;
1080 dma_addr_t dma;
d9e651bc 1081 struct list_head *head;
3d396eb1 1082
48bfd1e0 1083 rds_ring = &recv_ctx->rds_rings[ringid];
3d396eb1 1084
48bfd1e0 1085 producer = rds_ring->producer;
d9e651bc
DP
1086 head = &rds_ring->free_list;
1087
3d396eb1 1088 /* We can start writing rx descriptors into the phantom memory. */
d9e651bc
DP
1089 while (!list_empty(head)) {
1090
48bfd1e0 1091 skb = dev_alloc_skb(rds_ring->skb_size);
3d396eb1 1092 if (unlikely(!skb)) {
3d396eb1
AK
1093 break;
1094 }
ed25ffa1 1095
6f703406
DP
1096 if (!adapter->ahw.cut_through)
1097 skb_reserve(skb, 2);
1098
1099 dma = pci_map_single(pdev, skb->data,
1100 rds_ring->dma_size, PCI_DMA_FROMDEVICE);
1101 if (pci_dma_mapping_error(pdev, dma)) {
1102 dev_kfree_skb_any(skb);
1103 break;
1104 }
1105
1106 count++;
d9e651bc
DP
1107 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
1108 list_del(&buffer->list);
1109
ed25ffa1
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1110 buffer->skb = skb;
1111 buffer->state = NETXEN_BUFFER_BUSY;
1112 buffer->dma = dma;
6f703406 1113
ed25ffa1 1114 /* make a rcv descriptor */
6f703406
DP
1115 pdesc = &rds_ring->desc_head[producer];
1116 pdesc->addr_buffer = cpu_to_le64(dma);
ed33ebe4 1117 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1118 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
6f703406
DP
1119
1120 producer = get_next_index(producer, rds_ring->max_rx_desc_count);
ed25ffa1
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1121 }
1122 /* if we did allocate buffers, then write the count to Phantom */
1123 if (count) {
48bfd1e0 1124 rds_ring->producer = producer;
ed25ffa1 1125 /* Window = 1 */
3ce06a32 1126 adapter->pci_write_normalize(adapter,
48bfd1e0
DP
1127 rds_ring->crb_rcv_producer,
1128 (producer-1) & (rds_ring->max_rx_desc_count-1));
1129
1130 if (adapter->fw_major < 4) {
ed25ffa1
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1131 /*
1132 * Write a doorbell msg to tell phanmon of change in
1133 * receive ring producer
48bfd1e0 1134 * Only for firmware version < 4.0.0
ed25ffa1
AK
1135 */
1136 netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
1137 netxen_set_msg_privid(msg);
1138 netxen_set_msg_count(msg,
1139 ((producer -
48bfd1e0 1140 1) & (rds_ring->
ed25ffa1 1141 max_rx_desc_count - 1)));
3176ff3e 1142 netxen_set_msg_ctxid(msg, adapter->portnum);
ed25ffa1
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1143 netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
1144 writel(msg,
1145 DB_NORMALIZE(adapter,
1146 NETXEN_RCV_PRODUCER_OFFSET));
48bfd1e0 1147 }
ed25ffa1
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1148 }
1149}
1150
993fb90c
AB
1151static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1152 uint32_t ctx, uint32_t ringid)
ed25ffa1 1153{
7830b22c 1154 struct pci_dev *pdev = adapter->pdev;
ed25ffa1
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1155 struct sk_buff *skb;
1156 struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
48bfd1e0 1157 struct nx_host_rds_ring *rds_ring = NULL;
ed25ffa1
AK
1158 u32 producer;
1159 struct rcv_desc *pdesc;
1160 struct netxen_rx_buffer *buffer;
1161 int count = 0;
d9e651bc 1162 struct list_head *head;
6f703406 1163 dma_addr_t dma;
ed25ffa1 1164
48bfd1e0 1165 rds_ring = &recv_ctx->rds_rings[ringid];
ed25ffa1 1166
48bfd1e0 1167 producer = rds_ring->producer;
d9e651bc 1168 head = &rds_ring->free_list;
ed25ffa1 1169 /* We can start writing rx descriptors into the phantom memory. */
d9e651bc
DP
1170 while (!list_empty(head)) {
1171
48bfd1e0 1172 skb = dev_alloc_skb(rds_ring->skb_size);
ed25ffa1 1173 if (unlikely(!skb)) {
ed25ffa1
AK
1174 break;
1175 }
d9e651bc 1176
6f703406
DP
1177 if (!adapter->ahw.cut_through)
1178 skb_reserve(skb, 2);
1179
1180 dma = pci_map_single(pdev, skb->data,
1181 rds_ring->dma_size, PCI_DMA_FROMDEVICE);
1182 if (pci_dma_mapping_error(pdev, dma)) {
1183 dev_kfree_skb_any(skb);
1184 break;
1185 }
1186
1187 count++;
d9e651bc
DP
1188 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
1189 list_del(&buffer->list);
1190
3d396eb1
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1191 buffer->skb = skb;
1192 buffer->state = NETXEN_BUFFER_BUSY;
6f703406 1193 buffer->dma = dma;
ed25ffa1 1194
3d396eb1 1195 /* make a rcv descriptor */
6f703406 1196 pdesc = &rds_ring->desc_head[producer];
ed33ebe4 1197 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1198 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
3d396eb1 1199 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
6f703406
DP
1200
1201 producer = get_next_index(producer, rds_ring->max_rx_desc_count);
3d396eb1
AK
1202 }
1203
1204 /* if we did allocate buffers, then write the count to Phantom */
1205 if (count) {
48bfd1e0 1206 rds_ring->producer = producer;
3d396eb1 1207 /* Window = 1 */
3ce06a32 1208 adapter->pci_write_normalize(adapter,
48bfd1e0
DP
1209 rds_ring->crb_rcv_producer,
1210 (producer-1) & (rds_ring->max_rx_desc_count-1));
3d396eb1 1211 wmb();
3d396eb1
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1212 }
1213}
1214
3d396eb1
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1215void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1216{
3d396eb1 1217 memset(&adapter->stats, 0, sizeof(adapter->stats));
3176ff3e 1218 return;
3d396eb1
AK
1219}
1220