]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/netxen/netxen_nic_init.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
via-velocity: Remove private device list
[mirror_ubuntu-bionic-kernel.git] / drivers / net / netxen / netxen_nic_init.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
13af7a6e 3 * Copyright (C) 2009 - QLogic Corporation.
3d396eb1 4 * All rights reserved.
80922fbc 5 *
3d396eb1
AK		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
80922fbc 10 *
3d396eb1
AK		 11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
80922fbc 15 *
3d396eb1
AK		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
80922fbc 20 *
3d396eb1
AK		 21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
80922fbc 23 *
3d396eb1
AK		 24 */
25
26#include <linux/netdevice.h>
27#include <linux/delay.h>
28#include "netxen_nic.h"
29#include "netxen_nic_hw.h"
3d396eb1
AK		 30
31struct crb_addr_pair {
e0e20a1a
LCMT		 32 u32 addr;
33 u32 data;
3d396eb1
AK		 34};
35
36#define NETXEN_MAX_CRB_XFORM 60
37static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
e0e20a1a 38#define NETXEN_ADDR_ERROR (0xffffffff)
3d396eb1
AK		 39
40#define crb_addr_transform(name) \
41 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
42 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
43
cb8011ad
AK		 44#define NETXEN_NIC_XDMA_RESET 0x8000ff
45
becf46a0 46static void
d8b100c5
DP		 47netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
48 struct nx_host_rds_ring *rds_ring);
993fb90c 49
3d396eb1
AK		 50static void crb_addr_transform_setup(void)
51{
52 crb_addr_transform(XDMA);
53 crb_addr_transform(TIMR);
54 crb_addr_transform(SRE);
55 crb_addr_transform(SQN3);
56 crb_addr_transform(SQN2);
57 crb_addr_transform(SQN1);
58 crb_addr_transform(SQN0);
59 crb_addr_transform(SQS3);
60 crb_addr_transform(SQS2);
61 crb_addr_transform(SQS1);
62 crb_addr_transform(SQS0);
63 crb_addr_transform(RPMX7);
64 crb_addr_transform(RPMX6);
65 crb_addr_transform(RPMX5);
66 crb_addr_transform(RPMX4);
67 crb_addr_transform(RPMX3);
68 crb_addr_transform(RPMX2);
69 crb_addr_transform(RPMX1);
70 crb_addr_transform(RPMX0);
71 crb_addr_transform(ROMUSB);
72 crb_addr_transform(SN);
73 crb_addr_transform(QMN);
74 crb_addr_transform(QMS);
75 crb_addr_transform(PGNI);
76 crb_addr_transform(PGND);
77 crb_addr_transform(PGN3);
78 crb_addr_transform(PGN2);
79 crb_addr_transform(PGN1);
80 crb_addr_transform(PGN0);
81 crb_addr_transform(PGSI);
82 crb_addr_transform(PGSD);
83 crb_addr_transform(PGS3);
84 crb_addr_transform(PGS2);
85 crb_addr_transform(PGS1);
86 crb_addr_transform(PGS0);
87 crb_addr_transform(PS);
88 crb_addr_transform(PH);
89 crb_addr_transform(NIU);
90 crb_addr_transform(I2Q);
91 crb_addr_transform(EG);
92 crb_addr_transform(MN);
93 crb_addr_transform(MS);
94 crb_addr_transform(CAS2);
95 crb_addr_transform(CAS1);
96 crb_addr_transform(CAS0);
97 crb_addr_transform(CAM);
98 crb_addr_transform(C2C1);
99 crb_addr_transform(C2C0);
1fcca1a5 100 crb_addr_transform(SMB);
e4c93c81
DP		 101 crb_addr_transform(OCM0);
102 crb_addr_transform(I2C0);
3d396eb1
AK		 103}
104
2956640d 105void netxen_release_rx_buffers(struct netxen_adapter *adapter)
3d396eb1 106{
2956640d 107 struct netxen_recv_context *recv_ctx;
48bfd1e0 108 struct nx_host_rds_ring *rds_ring;
2956640d 109 struct netxen_rx_buffer *rx_buf;
becf46a0
DP		 110 int i, ring;
111
112 recv_ctx = &adapter->recv_ctx;
113 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
114 rds_ring = &recv_ctx->rds_rings[ring];
438627c7 115 for (i = 0; i < rds_ring->num_desc; ++i) {
becf46a0
DP		 116 rx_buf = &(rds_ring->rx_buf_arr[i]);
117 if (rx_buf->state == NETXEN_BUFFER_FREE)
118 continue;
119 pci_unmap_single(adapter->pdev,
120 rx_buf->dma,
121 rds_ring->dma_size,
122 PCI_DMA_FROMDEVICE);
123 if (rx_buf->skb != NULL)
124 dev_kfree_skb_any(rx_buf->skb);
2956640d
DP		 125 }
126 }
127}
128
129void netxen_release_tx_buffers(struct netxen_adapter *adapter)
130{
131 struct netxen_cmd_buffer *cmd_buf;
132 struct netxen_skb_frag *buffrag;
133 int i, j;
4ea528a1 134 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
2956640d 135
d877f1e3
DP		 136 cmd_buf = tx_ring->cmd_buf_arr;
137 for (i = 0; i < tx_ring->num_desc; i++) {
2956640d
DP		 138 buffrag = cmd_buf->frag_array;
139 if (buffrag->dma) {
140 pci_unmap_single(adapter->pdev, buffrag->dma,
141 buffrag->length, PCI_DMA_TODEVICE);
142 buffrag->dma = 0ULL;
143 }
144 for (j = 0; j < cmd_buf->frag_count; j++) {
145 buffrag++;
146 if (buffrag->dma) {
147 pci_unmap_page(adapter->pdev, buffrag->dma,
148 buffrag->length,
149 PCI_DMA_TODEVICE);
150 buffrag->dma = 0ULL;
151 }
152 }
2956640d
DP		 153 if (cmd_buf->skb) {
154 dev_kfree_skb_any(cmd_buf->skb);
155 cmd_buf->skb = NULL;
156 }
157 cmd_buf++;
158 }
159}
160
161void netxen_free_sw_resources(struct netxen_adapter *adapter)
162{
163 struct netxen_recv_context *recv_ctx;
48bfd1e0 164 struct nx_host_rds_ring *rds_ring;
d877f1e3 165 struct nx_host_tx_ring *tx_ring;
becf46a0
DP		 166 int ring;
167
168 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 169
170 if (recv_ctx->rds_rings == NULL)
171 goto skip_rds;
172
becf46a0
DP		 173 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
174 rds_ring = &recv_ctx->rds_rings[ring];
f2333a01
F		 175 vfree(rds_ring->rx_buf_arr);
176 rds_ring->rx_buf_arr = NULL;
2956640d 177 }
4ea528a1
DP		 178 kfree(recv_ctx->rds_rings);
179
180skip_rds:
181 if (adapter->tx_ring == NULL)
182 return;
becf46a0 183
4ea528a1 184 tx_ring = adapter->tx_ring;
f2333a01 185 vfree(tx_ring->cmd_buf_arr);
2956640d
DP		 186}
187
188int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
189{
190 struct netxen_recv_context *recv_ctx;
48bfd1e0 191 struct nx_host_rds_ring *rds_ring;
d8b100c5 192 struct nx_host_sds_ring *sds_ring;
4ea528a1 193 struct nx_host_tx_ring *tx_ring;
2956640d 194 struct netxen_rx_buffer *rx_buf;
4ea528a1 195 int ring, i, size;
2956640d
DP		 196
197 struct netxen_cmd_buffer *cmd_buf_arr;
198 struct net_device *netdev = adapter->netdev;
d877f1e3 199 struct pci_dev *pdev = adapter->pdev;
2956640d 200
4ea528a1
DP		 201 size = sizeof(struct nx_host_tx_ring);
202 tx_ring = kzalloc(size, GFP_KERNEL);
203 if (tx_ring == NULL) {
204 dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
205 netdev->name);
206 return -ENOMEM;
207 }
208 adapter->tx_ring = tx_ring;
209
d877f1e3 210 tx_ring->num_desc = adapter->num_txd;
b2af9cb0 211 tx_ring->txq = netdev_get_tx_queue(netdev, 0);
4ea528a1
DP		 212
213 cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
2956640d 214 if (cmd_buf_arr == NULL) {
d877f1e3 215 dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
2956640d
DP		 216 netdev->name);
217 return -ENOMEM;
218 }
d877f1e3
DP		 219 memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
220 tx_ring->cmd_buf_arr = cmd_buf_arr;
2956640d 221
becf46a0 222 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 223
224 size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
225 rds_ring = kzalloc(size, GFP_KERNEL);
226 if (rds_ring == NULL) {
227 dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
228 netdev->name);
229 return -ENOMEM;
230 }
231 recv_ctx->rds_rings = rds_ring;
232
becf46a0
DP		 233 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
234 rds_ring = &recv_ctx->rds_rings[ring];
438627c7
DP		 235 switch (ring) {
236 case RCV_RING_NORMAL:
237 rds_ring->num_desc = adapter->num_rxd;
becf46a0
DP		 238 if (adapter->ahw.cut_through) {
239 rds_ring->dma_size =
240 NX_CT_DEFAULT_RX_BUF_LEN;
48bfd1e0 241 rds_ring->skb_size =
becf46a0
DP		 242 NX_CT_DEFAULT_RX_BUF_LEN;
243 } else {
9b08beba
DP		 244 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
245 rds_ring->dma_size =
246 NX_P3_RX_BUF_MAX_LEN;
247 else
248 rds_ring->dma_size =
249 NX_P2_RX_BUF_MAX_LEN;
becf46a0 250 rds_ring->skb_size =
9b08beba 251 rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 252 }
253 break;
2956640d 254
438627c7
DP		 255 case RCV_RING_JUMBO:
256 rds_ring->num_desc = adapter->num_jumbo_rxd;
becf46a0
DP		 257 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
258 rds_ring->dma_size =
259 NX_P3_RX_JUMBO_BUF_MAX_LEN;
260 else
261 rds_ring->dma_size =
262 NX_P2_RX_JUMBO_BUF_MAX_LEN;
bc75e5bf
DP		 263
264 if (adapter->capabilities & NX_CAP0_HW_LRO)
265 rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
266
becf46a0
DP		 267 rds_ring->skb_size =
268 rds_ring->dma_size + NET_IP_ALIGN;
269 break;
2956640d 270
becf46a0 271 case RCV_RING_LRO:
438627c7 272 rds_ring->num_desc = adapter->num_lro_rxd;
9b08beba
DP		 273 rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
274 rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 275 break;
276
277 }
278 rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
d8b100c5 279 vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 280 if (rds_ring->rx_buf_arr == NULL) {
281 printk(KERN_ERR "%s: Failed to allocate "
282 "rx buffer ring %d\n",
283 netdev->name, ring);
284 /* free whatever was already allocated */
285 goto err_out;
286 }
d8b100c5 287 memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 288 INIT_LIST_HEAD(&rds_ring->free_list);
289 /*
290 * Now go through all of them, set reference handles
291 * and put them in the queues.
292 */
becf46a0 293 rx_buf = rds_ring->rx_buf_arr;
4ea528a1 294 for (i = 0; i < rds_ring->num_desc; i++) {
becf46a0
DP		 295 list_add_tail(&rx_buf->list,
296 &rds_ring->free_list);
297 rx_buf->ref_handle = i;
298 rx_buf->state = NETXEN_BUFFER_FREE;
299 rx_buf++;
3d396eb1 300 }
d8b100c5
DP		 301 spin_lock_init(&rds_ring->lock);
302 }
303
304 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
305 sds_ring = &recv_ctx->sds_rings[ring];
306 sds_ring->irq = adapter->msix_entries[ring].vector;
d8b100c5
DP		 307 sds_ring->adapter = adapter;
308 sds_ring->num_desc = adapter->num_rxd;
309
310 for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
311 INIT_LIST_HEAD(&sds_ring->free_list[i]);
3d396eb1 312 }
2956640d
DP		 313
314 return 0;
315
316err_out:
317 netxen_free_sw_resources(adapter);
318 return -ENOMEM;
3d396eb1
AK		 319}
320
3d396eb1
AK		 321/*
322 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
323 * address to external PCI CRB address.
324 */
993fb90c 325static u32 netxen_decode_crb_addr(u32 addr)
3d396eb1
AK		 326{
327 int i;
e0e20a1a 328 u32 base_addr, offset, pci_base;
3d396eb1
AK		 329
330 crb_addr_transform_setup();
331
332 pci_base = NETXEN_ADDR_ERROR;
333 base_addr = addr & 0xfff00000;
334 offset = addr & 0x000fffff;
335
336 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
337 if (crb_addr_xform[i] == base_addr) {
338 pci_base = i << 20;
339 break;
340 }
341 }
342 if (pci_base == NETXEN_ADDR_ERROR)
343 return pci_base;
344 else
345 return (pci_base + offset);
346}
347
c9517e58 348#define NETXEN_MAX_ROM_WAIT_USEC 100
3d396eb1 349
993fb90c 350static int netxen_wait_rom_done(struct netxen_adapter *adapter)
3d396eb1
AK		 351{
352 long timeout = 0;
353 long done = 0;
354
27c915a4
DP		 355 cond_resched();
356
3d396eb1 357 while (done == 0) {
f98a9f69 358 done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
3d396eb1 359 done &= 2;
c9517e58
DP		 360 if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
361 dev_err(&adapter->pdev->dev,
362 "Timeout reached waiting for rom done");
3d396eb1
AK		 363 return -EIO;
364 }
c9517e58 365 udelay(1);
3d396eb1
AK		 366 }
367 return 0;
368}
369
993fb90c
AB		 370static int do_rom_fast_read(struct netxen_adapter *adapter,
371 int addr, int *valp)
3d396eb1 372{
f98a9f69
DP		 373 NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
374 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
375 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
376 NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
3d396eb1
AK		 377 if (netxen_wait_rom_done(adapter)) {
378 printk("Error waiting for rom done\n");
379 return -EIO;
380 }
381 /* reset abyte_cnt and dummy_byte_cnt */
f98a9f69 382 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
27c915a4 383 udelay(10);
f98a9f69 384 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
3d396eb1 385
f98a9f69 386 *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
3d396eb1
AK		 387 return 0;
388}
389
993fb90c
AB		 390static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
391 u8 *bytes, size_t size)
27d2ab54
AK		 392{
393 int addridx;
394 int ret = 0;
395
396 for (addridx = addr; addridx < (addr + size); addridx += 4) {
f305f789
AV		 397 int v;
398 ret = do_rom_fast_read(adapter, addridx, &v);
27d2ab54
AK		 399 if (ret != 0)
400 break;
f305f789 401 *(__le32 *)bytes = cpu_to_le32(v);
27d2ab54
AK		 402 bytes += 4;
403 }
404
405 return ret;
406}
407
408int
4790654c 409netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
27d2ab54
AK		 410 u8 *bytes, size_t size)
411{
412 int ret;
413
c9517e58 414 ret = netxen_rom_lock(adapter);
27d2ab54
AK		 415 if (ret < 0)
416 return ret;
417
418 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
419
420 netxen_rom_unlock(adapter);
421 return ret;
422}
423
3d396eb1
AK		 424int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
425{
426 int ret;
427
c9517e58 428 if (netxen_rom_lock(adapter) != 0)
3d396eb1
AK		 429 return -EIO;
430
431 ret = do_rom_fast_read(adapter, addr, valp);
cb8011ad
AK		 432 netxen_rom_unlock(adapter);
433 return ret;
434}
435
3d396eb1
AK		 436#define NETXEN_BOARDTYPE 0x4008
437#define NETXEN_BOARDNUM 0x400c
438#define NETXEN_CHIPNUM 0x4010
3d396eb1 439
0be367bd 440int netxen_pinit_from_rom(struct netxen_adapter *adapter)
3d396eb1 441{
dcd56fdb 442 int addr, val;
27c915a4 443 int i, n, init_delay = 0;
3d396eb1 444 struct crb_addr_pair *buf;
27c915a4 445 unsigned offset;
e0e20a1a 446 u32 off;
3d396eb1
AK		 447
448 /* resetall */
c9517e58 449 netxen_rom_lock(adapter);
f98a9f69 450 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
27c915a4 451 netxen_rom_unlock(adapter);
3d396eb1 452
2956640d
DP		 453 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
454 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
27c915a4 455 (n != 0xcafecafe) ||
2956640d
DP		 456 netxen_rom_fast_read(adapter, 4, &n) != 0) {
457 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
458 "n: %08x\n", netxen_nic_driver_name, n);
3d396eb1
AK		 459 return -EIO;
460 }
2956640d
DP		 461 offset = n & 0xffffU;
462 n = (n >> 16) & 0xffffU;
463 } else {
464 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
465 !(n & 0x80000000)) {
466 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
467 "n: %08x\n", netxen_nic_driver_name, n);
468 return -EIO;
3d396eb1 469 }
2956640d
DP		 470 offset = 1;
471 n &= ~0x80000000;
472 }
473
0be367bd 474 if (n >= 1024) {
2956640d
DP		 475 printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
476 " initialized.\n", __func__, n);
477 return -EIO;
478 }
3d396eb1 479
2956640d
DP		 480 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
481 if (buf == NULL) {
482 printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
483 netxen_nic_driver_name);
484 return -ENOMEM;
485 }
0be367bd 486
2956640d
DP		 487 for (i = 0; i < n; i++) {
488 if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
584dbe94
DM		 489 netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
490 kfree(buf);
2956640d 491 return -EIO;
584dbe94 492 }
2956640d
DP		 493
494 buf[i].addr = addr;
495 buf[i].data = val;
496
2956640d 497 }
0be367bd 498
2956640d
DP		 499 for (i = 0; i < n; i++) {
500
501 off = netxen_decode_crb_addr(buf[i].addr);
502 if (off == NETXEN_ADDR_ERROR) {
503 printk(KERN_ERR"CRB init value out of range %x\n",
1fcca1a5 504 buf[i].addr);
2956640d
DP		 505 continue;
506 }
507 off += NETXEN_PCI_CRBSPACE;
0be367bd
AKS		 508
509 if (off & 1)
510 continue;
511
2956640d
DP		 512 /* skipping cold reboot MAGIC */
513 if (off == NETXEN_CAM_RAM(0x1fc))
514 continue;
515
516 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
8bee0a91
DP		 517 if (off == (NETXEN_CRB_I2C0 + 0x1c))
518 continue;
2956640d
DP		 519 /* do not reset PCI */
520 if (off == (ROMUSB_GLB + 0xbc))
1fcca1a5 521 continue;
27c915a4
DP		 522 if (off == (ROMUSB_GLB + 0xa8))
523 continue;
524 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
525 continue;
526 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
527 continue;
528 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
529 continue;
0be367bd
AKS		 530 if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
531 !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
2956640d
DP		 532 buf[i].data = 0x1020;
533 /* skip the function enable register */
534 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
3d396eb1 535 continue;
2956640d
DP		 536 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
537 continue;
538 if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
539 continue;
540 }
3d396eb1 541
27c915a4 542 init_delay = 1;
2956640d
DP		 543 /* After writing this register, HW needs time for CRB */
544 /* to quiet down (else crb_window returns 0xffffffff) */
545 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
27c915a4 546 init_delay = 1000;
2956640d 547 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
3d396eb1 548 /* hold xdma in reset also */
cb8011ad 549 buf[i].data = NETXEN_NIC_XDMA_RESET;
27c915a4 550 buf[i].data = 0x8000ff;
3d396eb1 551 }
2956640d 552 }
3d396eb1 553
f98a9f69 554 NXWR32(adapter, off, buf[i].data);
3d396eb1 555
27c915a4 556 msleep(init_delay);
2956640d
DP		 557 }
558 kfree(buf);
3d396eb1 559
2956640d 560 /* disable_peg_cache_all */
3d396eb1 561
2956640d
DP		 562 /* unreset_net_cache */
563 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
f98a9f69
DP		 564 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
565 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
3d396eb1 566 }
2956640d
DP		 567
568 /* p2dn replyCount */
f98a9f69 569 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
2956640d 570 /* disable_peg_cache 0 */
f98a9f69 571 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
2956640d 572 /* disable_peg_cache 1 */
f98a9f69 573 NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
2956640d
DP		 574
575 /* peg_clr_all */
576
577 /* peg_clr 0 */
f98a9f69
DP		 578 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
579 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
2956640d 580 /* peg_clr 1 */
f98a9f69
DP		 581 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
582 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
2956640d 583 /* peg_clr 2 */
f98a9f69
DP		 584 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
585 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
2956640d 586 /* peg_clr 3 */
f98a9f69
DP		 587 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
588 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
3d396eb1
AK		 589 return 0;
590}
591
67c38fc6
DP		 592int
593netxen_need_fw_reset(struct netxen_adapter *adapter)
594{
595 u32 count, old_count;
596 u32 val, version, major, minor, build;
597 int i, timeout;
598 u8 fw_type;
599
600 /* NX2031 firmware doesn't support heartbit */
601 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
602 return 1;
603
604 /* last attempt had failed */
605 if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
606 return 1;
607
608 old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
609
610 for (i = 0; i < 10; i++) {
611
612 timeout = msleep_interruptible(200);
613 if (timeout) {
614 NXWR32(adapter, CRB_CMDPEG_STATE,
615 PHAN_INITIALIZE_FAILED);
616 return -EINTR;
617 }
618
619 count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
620 if (count != old_count)
621 break;
622 }
623
624 /* firmware is dead */
625 if (count == old_count)
626 return 1;
627
628 /* check if we have got newer or different file firmware */
629 if (adapter->fw) {
630
631 const struct firmware *fw = adapter->fw;
632
633 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
634 version = NETXEN_DECODE_VERSION(val);
635
636 major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
637 minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
638 build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
639
640 if (version > NETXEN_VERSION_CODE(major, minor, build))
641 return 1;
642
643 if (version == NETXEN_VERSION_CODE(major, minor, build)) {
644
645 val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
646 fw_type = (val & 0x4) ?
647 NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
648
649 if (adapter->fw_type != fw_type)
650 return 1;
651 }
652 }
653
654 return 0;
655}
656
657static char *fw_name[] = {
658 "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
659};
660
f7185c71
DP		 661int
662netxen_load_firmware(struct netxen_adapter *adapter)
663{
664 u64 *ptr64;
665 u32 i, flashaddr, size;
666 const struct firmware *fw = adapter->fw;
67c38fc6
DP		 667 struct pci_dev *pdev = adapter->pdev;
668
669 dev_info(&pdev->dev, "loading firmware from %s\n",
670 fw_name[adapter->fw_type]);
f7185c71
DP		 671
672 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
673 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
674
675 if (fw) {
676 __le64 data;
677
678 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
679
680 ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
681 flashaddr = NETXEN_BOOTLD_START;
682
683 for (i = 0; i < size; i++) {
684 data = cpu_to_le64(ptr64[i]);
1f5e055d
AKS		 685 if (adapter->pci_mem_write(adapter,
686 flashaddr, data))
687 return -EIO;
688
f7185c71
DP		 689 flashaddr += 8;
690 }
691
692 size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
693 size = (__force u32)cpu_to_le32(size) / 8;
694
695 ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
696 flashaddr = NETXEN_IMAGE_START;
697
698 for (i = 0; i < size; i++) {
699 data = cpu_to_le64(ptr64[i]);
700
701 if (adapter->pci_mem_write(adapter,
1f5e055d 702 flashaddr, data))
f7185c71
DP		 703 return -EIO;
704
705 flashaddr += 8;
706 }
707 } else {
f78c0850
AKS		 708 u64 data;
709 u32 hi, lo;
f7185c71 710
f78c0850 711 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
f7185c71
DP		 712 flashaddr = NETXEN_BOOTLD_START;
713
714 for (i = 0; i < size; i++) {
715 if (netxen_rom_fast_read(adapter,
1f5e055d 716 flashaddr, (int *)&lo) != 0)
f78c0850
AKS		 717 return -EIO;
718 if (netxen_rom_fast_read(adapter,
1f5e055d 719 flashaddr + 4, (int *)&hi) != 0)
f7185c71
DP		 720 return -EIO;
721
f78c0850
AKS		 722 /* hi, lo are already in host endian byteorder */
723 data = (((u64)hi << 32) | lo);
724
f7185c71 725 if (adapter->pci_mem_write(adapter,
1f5e055d 726 flashaddr, data))
f7185c71
DP		 727 return -EIO;
728
f78c0850 729 flashaddr += 8;
f7185c71
DP		 730 }
731 }
732 msleep(1);
733
0be367bd
AKS		 734 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
735 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
736 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
737 } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
f7185c71
DP		 738 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
739 else {
740 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
741 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
742 }
743
744 return 0;
745}
746
747static int
748netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
749{
750 __le32 val;
98e31bb0 751 u32 ver, min_ver, bios;
f7185c71
DP		 752 struct pci_dev *pdev = adapter->pdev;
753 const struct firmware *fw = adapter->fw;
754
755 if (fw->size < NX_FW_MIN_SIZE)
756 return -EINVAL;
757
758 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
759 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
760 return -EINVAL;
761
762 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
f7185c71
DP		 763
764 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
765 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
766 else
767 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
768
98e31bb0 769 ver = NETXEN_DECODE_VERSION(val);
f7185c71 770
98e31bb0 771 if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
f7185c71
DP		 772 dev_err(&pdev->dev,
773 "%s: firmware version %d.%d.%d unsupported\n",
98e31bb0 774 fwname, _major(ver), _minor(ver), _build(ver));
f7185c71
DP		 775 return -EINVAL;
776 }
777
778 val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
779 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
780 if ((__force u32)val != bios) {
781 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
782 fwname);
783 return -EINVAL;
784 }
785
786 /* check if flashed firmware is newer */
787 if (netxen_rom_fast_read(adapter,
788 NX_FW_VERSION_OFFSET, (int *)&val))
789 return -EIO;
98e31bb0
DP		 790 val = NETXEN_DECODE_VERSION(val);
791 if (val > ver) {
792 dev_info(&pdev->dev, "%s: firmware is older than flash\n",
793 fwname);
f7185c71 794 return -EINVAL;
98e31bb0 795 }
f7185c71
DP		 796
797 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
798 return 0;
799}
800
6598b169
DP		 801static int
802netxen_p3_has_mn(struct netxen_adapter *adapter)
f7185c71
DP		 803{
804 u32 capability, flashed_ver;
f7185c71
DP		 805 capability = 0;
806
807 netxen_rom_fast_read(adapter,
808 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
98e31bb0
DP		 809 flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
810
f7185c71 811 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
6598b169 812
f7185c71 813 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
6598b169
DP		 814 if (capability & NX_PEG_TUNE_MN_PRESENT)
815 return 1;
816 }
817 return 0;
818}
819
820void netxen_request_firmware(struct netxen_adapter *adapter)
821{
822 u8 fw_type;
823 struct pci_dev *pdev = adapter->pdev;
824 int rc = 0;
825
826 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
827 fw_type = NX_P2_MN_ROMIMAGE;
828 goto request_fw;
f7185c71
DP		 829 }
830
7cecdca1
DP		 831 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
832 /* No file firmware for the time being */
833 fw_type = NX_FLASH_ROMIMAGE;
834 goto done;
835 }
836
6598b169
DP		 837 fw_type = netxen_p3_has_mn(adapter) ?
838 NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
98e31bb0 839
f7185c71
DP		 840request_fw:
841 rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
842 if (rc != 0) {
6598b169 843 if (fw_type == NX_P3_MN_ROMIMAGE) {
f7185c71 844 msleep(1);
6598b169
DP		 845 fw_type = NX_P3_CT_ROMIMAGE;
846 goto request_fw;
f7185c71
DP		 847 }
848
67c38fc6 849 fw_type = NX_FLASH_ROMIMAGE;
f7185c71
DP		 850 adapter->fw = NULL;
851 goto done;
852 }
853
854 rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
855 if (rc != 0) {
856 release_firmware(adapter->fw);
857
6598b169 858 if (fw_type == NX_P3_MN_ROMIMAGE) {
f7185c71 859 msleep(1);
6598b169
DP		 860 fw_type = NX_P3_CT_ROMIMAGE;
861 goto request_fw;
f7185c71
DP		 862 }
863
67c38fc6 864 fw_type = NX_FLASH_ROMIMAGE;
f7185c71
DP		 865 adapter->fw = NULL;
866 goto done;
867 }
868
869done:
67c38fc6 870 adapter->fw_type = fw_type;
f7185c71
DP		 871}
872
873
874void
875netxen_release_firmware(struct netxen_adapter *adapter)
876{
877 if (adapter->fw)
878 release_firmware(adapter->fw);
db4cfd8a 879 adapter->fw = NULL;
f7185c71
DP		 880}
881
83ac51fa 882int netxen_init_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 883{
83ac51fa
DP		 884 u64 addr;
885 u32 hi, lo;
ed25ffa1 886
83ac51fa
DP		 887 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
888 return 0;
889
890 adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
ed25ffa1
AK		 891 NETXEN_HOST_DUMMY_DMA_SIZE,
892 &adapter->dummy_dma.phys_addr);
893 if (adapter->dummy_dma.addr == NULL) {
83ac51fa
DP		 894 dev_err(&adapter->pdev->dev,
895 "ERROR: Could not allocate dummy DMA memory\n");
ed25ffa1
AK		 896 return -ENOMEM;
897 }
898
899 addr = (uint64_t) adapter->dummy_dma.phys_addr;
900 hi = (addr >> 32) & 0xffffffff;
901 lo = addr & 0xffffffff;
902
f98a9f69
DP		 903 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
904 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
ed25ffa1
AK		 905
906 return 0;
907}
908
83ac51fa
DP		 909/*
910 * NetXen DMA watchdog control:
911 *
912 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
913 * Bit 1 : disable_request => 1 req disable dma watchdog
914 * Bit 2 : enable_request => 1 req enable dma watchdog
915 * Bit 3-31 : unused
916 */
917void netxen_free_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 918{
15eef1e1 919 int i = 100;
83ac51fa
DP		 920 u32 ctrl;
921
922 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
923 return;
15eef1e1
DP		 924
925 if (!adapter->dummy_dma.addr)
926 return;
439b454e 927
83ac51fa
DP		 928 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
929 if ((ctrl & 0x1) != 0) {
930 NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
931
932 while ((ctrl & 0x1) != 0) {
933
439b454e 934 msleep(50);
83ac51fa
DP		 935
936 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
937
938 if (--i == 0)
439b454e 939 break;
83ac51fa 940 };
15eef1e1 941 }
439b454e 942
15eef1e1
DP		 943 if (i) {
944 pci_free_consistent(adapter->pdev,
945 NETXEN_HOST_DUMMY_DMA_SIZE,
946 adapter->dummy_dma.addr,
947 adapter->dummy_dma.phys_addr);
948 adapter->dummy_dma.addr = NULL;
83ac51fa
DP		 949 } else
950 dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
ed25ffa1
AK		 951}
952
96acb6eb 953int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
3d396eb1
AK		 954{
955 u32 val = 0;
2956640d 956 int retries = 60;
3d396eb1 957
96f2ebd2
DP		 958 if (pegtune_val)
959 return 0;
960
961 do {
962 val = NXRD32(adapter, CRB_CMDPEG_STATE);
96acb6eb 963
96f2ebd2
DP		 964 switch (val) {
965 case PHAN_INITIALIZE_COMPLETE:
966 case PHAN_INITIALIZE_ACK:
967 return 0;
968 case PHAN_INITIALIZE_FAILED:
969 goto out_err;
970 default:
971 break;
972 }
96acb6eb 973
96f2ebd2 974 msleep(500);
2956640d 975
96f2ebd2 976 } while (--retries);
2956640d 977
96f2ebd2 978 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
96acb6eb 979
96f2ebd2
DP		 980out_err:
981 dev_warn(&adapter->pdev->dev, "firmware init failed\n");
982 return -EIO;
3d396eb1
AK		 983}
984
56a00787
DP		 985static int
986netxen_receive_peg_ready(struct netxen_adapter *adapter)
2956640d
DP		 987{
988 u32 val = 0;
989 int retries = 2000;
990
991 do {
f98a9f69 992 val = NXRD32(adapter, CRB_RCVPEG_STATE);
2956640d
DP		 993
994 if (val == PHAN_PEG_RCV_INITIALIZED)
995 return 0;
996
997 msleep(10);
998
999 } while (--retries);
1000
1001 if (!retries) {
1002 printk(KERN_ERR "Receive Peg initialization not "
1003 "complete, state: 0x%x.\n", val);
1004 return -EIO;
1005 }
1006
1007 return 0;
1008}
1009
56a00787
DP		 1010int netxen_init_firmware(struct netxen_adapter *adapter)
1011{
1012 int err;
1013
1014 err = netxen_receive_peg_ready(adapter);
1015 if (err)
1016 return err;
1017
f98a9f69
DP		 1018 NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
1019 NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
1020 NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
1021 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
56a00787
DP		 1022
1023 return err;
1024}
1025
3bf26ce3
DP		 1026static void
1027netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
1028{
1029 u32 cable_OUI;
1030 u16 cable_len;
1031 u16 link_speed;
1032 u8 link_status, module, duplex, autoneg;
1033 struct net_device *netdev = adapter->netdev;
1034
1035 adapter->has_link_events = 1;
1036
1037 cable_OUI = msg->body[1] & 0xffffffff;
1038 cable_len = (msg->body[1] >> 32) & 0xffff;
1039 link_speed = (msg->body[1] >> 48) & 0xffff;
1040
1041 link_status = msg->body[2] & 0xff;
1042 duplex = (msg->body[2] >> 16) & 0xff;
1043 autoneg = (msg->body[2] >> 24) & 0xff;
1044
1045 module = (msg->body[2] >> 8) & 0xff;
1046 if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
1047 printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
1048 netdev->name, cable_OUI, cable_len);
1049 } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
1050 printk(KERN_INFO "%s: unsupported cable length %d\n",
1051 netdev->name, cable_len);
1052 }
1053
1054 netxen_advert_link_change(adapter, link_status);
1055
1056 /* update link parameters */
1057 if (duplex == LINKEVENT_FULL_DUPLEX)
1058 adapter->link_duplex = DUPLEX_FULL;
1059 else
1060 adapter->link_duplex = DUPLEX_HALF;
1061 adapter->module_type = module;
1062 adapter->link_autoneg = autoneg;
1063 adapter->link_speed = link_speed;
1064}
1065
1066static void
1067netxen_handle_fw_message(int desc_cnt, int index,
1068 struct nx_host_sds_ring *sds_ring)
1069{
1070 nx_fw_msg_t msg;
1071 struct status_desc *desc;
1072 int i = 0, opcode;
1073
1074 while (desc_cnt > 0 && i < 8) {
1075 desc = &sds_ring->desc_head[index];
1076 msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
1077 msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
1078
1079 index = get_next_index(index, sds_ring->num_desc);
1080 desc_cnt--;
1081 }
1082
1083 opcode = netxen_get_nic_msg_opcode(msg.body[0]);
1084 switch (opcode) {
1085 case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
1086 netxen_handle_linkevent(sds_ring->adapter, &msg);
1087 break;
1088 default:
1089 break;
1090 }
1091}
1092
d8b100c5
DP		 1093static int
1094netxen_alloc_rx_skb(struct netxen_adapter *adapter,
1095 struct nx_host_rds_ring *rds_ring,
1096 struct netxen_rx_buffer *buffer)
1097{
1098 struct sk_buff *skb;
1099 dma_addr_t dma;
1100 struct pci_dev *pdev = adapter->pdev;
1101
1102 buffer->skb = dev_alloc_skb(rds_ring->skb_size);
1103 if (!buffer->skb)
1104 return 1;
1105
1106 skb = buffer->skb;
1107
1108 if (!adapter->ahw.cut_through)
1109 skb_reserve(skb, 2);
1110
1111 dma = pci_map_single(pdev, skb->data,
1112 rds_ring->dma_size, PCI_DMA_FROMDEVICE);
1113
1114 if (pci_dma_mapping_error(pdev, dma)) {
1115 dev_kfree_skb_any(skb);
1116 buffer->skb = NULL;
1117 return 1;
1118 }
1119
1120 buffer->skb = skb;
1121 buffer->dma = dma;
1122 buffer->state = NETXEN_BUFFER_BUSY;
1123
1124 return 0;
1125}
1126
d9e651bc
DP		 1127static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
1128 struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
1129{
1130 struct netxen_rx_buffer *buffer;
1131 struct sk_buff *skb;
1132
1133 buffer = &rds_ring->rx_buf_arr[index];
1134
1135 pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
1136 PCI_DMA_FROMDEVICE);
1137
1138 skb = buffer->skb;
1139 if (!skb)
1140 goto no_skb;
1141
1142 if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
1143 adapter->stats.csummed++;
1144 skb->ip_summed = CHECKSUM_UNNECESSARY;
1145 } else
1146 skb->ip_summed = CHECKSUM_NONE;
1147
1148 skb->dev = adapter->netdev;
1149
1150 buffer->skb = NULL;
d9e651bc
DP		 1151no_skb:
1152 buffer->state = NETXEN_BUFFER_FREE;
d9e651bc
DP		 1153 return skb;
1154}
1155
d8b100c5 1156static struct netxen_rx_buffer *
9b3ef55c 1157netxen_process_rcv(struct netxen_adapter *adapter,
c1c00ab8
DP		 1158 struct nx_host_sds_ring *sds_ring,
1159 int ring, u64 sts_data0)
3d396eb1 1160{
3176ff3e 1161 struct net_device *netdev = adapter->netdev;
becf46a0 1162 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
3d396eb1
AK		 1163 struct netxen_rx_buffer *buffer;
1164 struct sk_buff *skb;
c1c00ab8
DP		 1165 struct nx_host_rds_ring *rds_ring;
1166 int index, length, cksum, pkt_offset;
3d396eb1 1167
c1c00ab8
DP		 1168 if (unlikely(ring >= adapter->max_rds_rings))
1169 return NULL;
1170
1171 rds_ring = &recv_ctx->rds_rings[ring];
1172
1173 index = netxen_get_sts_refhandle(sts_data0);
1174 if (unlikely(index >= rds_ring->num_desc))
d8b100c5 1175 return NULL;
438627c7 1176
48bfd1e0 1177 buffer = &rds_ring->rx_buf_arr[index];
3d396eb1 1178
c1c00ab8
DP		 1179 length = netxen_get_sts_totallength(sts_data0);
1180 cksum = netxen_get_sts_status(sts_data0);
1181 pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
1182
d9e651bc
DP		 1183 skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
1184 if (!skb)
d8b100c5 1185 return buffer;
200eef20 1186
9b3ef55c
DP		 1187 if (length > rds_ring->skb_size)
1188 skb_put(skb, rds_ring->skb_size);
1189 else
1190 skb_put(skb, length);
d9e651bc 1191
9b3ef55c
DP		 1192
1193 if (pkt_offset)
1194 skb_pull(skb, pkt_offset);
ed25ffa1 1195
bc75e5bf 1196 skb->truesize = skb->len + sizeof(struct sk_buff);
3d396eb1
AK		 1197 skb->protocol = eth_type_trans(skb, netdev);
1198
a92e9e65 1199 napi_gro_receive(&sds_ring->napi, skb);
d9e651bc 1200
1bb482f8 1201 adapter->stats.rx_pkts++;
0ddc110c 1202 adapter->stats.rxbytes += length;
d8b100c5
DP		 1203
1204 return buffer;
3d396eb1
AK		 1205}
1206
c1c00ab8
DP		 1207#define TCP_HDR_SIZE 20
1208#define TCP_TS_OPTION_SIZE 12
1209#define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
1210
1211static struct netxen_rx_buffer *
1212netxen_process_lro(struct netxen_adapter *adapter,
1213 struct nx_host_sds_ring *sds_ring,
1214 int ring, u64 sts_data0, u64 sts_data1)
1215{
1216 struct net_device *netdev = adapter->netdev;
1217 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
1218 struct netxen_rx_buffer *buffer;
1219 struct sk_buff *skb;
1220 struct nx_host_rds_ring *rds_ring;
1221 struct iphdr *iph;
1222 struct tcphdr *th;
1223 bool push, timestamp;
1224 int l2_hdr_offset, l4_hdr_offset;
1225 int index;
1226 u16 lro_length, length, data_offset;
1227 u32 seq_number;
1228
1229 if (unlikely(ring > adapter->max_rds_rings))
1230 return NULL;
1231
1232 rds_ring = &recv_ctx->rds_rings[ring];
1233
1234 index = netxen_get_lro_sts_refhandle(sts_data0);
1235 if (unlikely(index > rds_ring->num_desc))
1236 return NULL;
1237
1238 buffer = &rds_ring->rx_buf_arr[index];
1239
1240 timestamp = netxen_get_lro_sts_timestamp(sts_data0);
1241 lro_length = netxen_get_lro_sts_length(sts_data0);
1242 l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
1243 l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
1244 push = netxen_get_lro_sts_push_flag(sts_data0);
1245 seq_number = netxen_get_lro_sts_seq_number(sts_data1);
1246
1247 skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
1248 if (!skb)
1249 return buffer;
1250
1251 if (timestamp)
1252 data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
1253 else
1254 data_offset = l4_hdr_offset + TCP_HDR_SIZE;
1255
1256 skb_put(skb, lro_length + data_offset);
1257
bc75e5bf 1258 skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
c1c00ab8
DP		 1259
1260 skb_pull(skb, l2_hdr_offset);
1261 skb->protocol = eth_type_trans(skb, netdev);
1262
1263 iph = (struct iphdr *)skb->data;
1264 th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
1265
1266 length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
1267 iph->tot_len = htons(length);
1268 iph->check = 0;
1269 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
1270 th->psh = push;
1271 th->seq = htonl(seq_number);
1272
1bb482f8
NK		 1273 length = skb->len;
1274
c1c00ab8
DP		 1275 netif_receive_skb(skb);
1276
1bb482f8
NK		 1277 adapter->stats.lro_pkts++;
1278 adapter->stats.rxbytes += length;
1279
c1c00ab8
DP		 1280 return buffer;
1281}
1282
d8b100c5
DP		 1283#define netxen_merge_rx_buffers(list, head) \
1284 do { list_splice_tail_init(list, head); } while (0);
1285
becf46a0 1286int
d8b100c5 1287netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
3d396eb1 1288{
d8b100c5
DP		 1289 struct netxen_adapter *adapter = sds_ring->adapter;
1290
1291 struct list_head *cur;
1292
0ddc110c 1293 struct status_desc *desc;
d8b100c5
DP		 1294 struct netxen_rx_buffer *rxbuf;
1295
1296 u32 consumer = sds_ring->consumer;
1297
9b3ef55c 1298 int count = 0;
c1c00ab8
DP		 1299 u64 sts_data0, sts_data1;
1300 int opcode, ring = 0, desc_cnt;
3d396eb1 1301
3d396eb1 1302 while (count < max) {
d8b100c5 1303 desc = &sds_ring->desc_head[consumer];
c1c00ab8 1304 sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
0ddc110c 1305
c1c00ab8 1306 if (!(sts_data0 & STATUS_OWNER_HOST))
3d396eb1 1307 break;
d9e651bc 1308
c1c00ab8 1309 desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
3bf26ce3 1310
c1c00ab8 1311 opcode = netxen_get_sts_opcode(sts_data0);
d9e651bc 1312
3bf26ce3
DP		 1313 switch (opcode) {
1314 case NETXEN_NIC_RXPKT_DESC:
1315 case NETXEN_OLD_RXPKT_DESC:
6598b169 1316 case NETXEN_NIC_SYN_OFFLOAD:
c1c00ab8
DP		 1317 ring = netxen_get_sts_type(sts_data0);
1318 rxbuf = netxen_process_rcv(adapter, sds_ring,
1319 ring, sts_data0);
1320 break;
1321 case NETXEN_NIC_LRO_DESC:
1322 ring = netxen_get_lro_sts_type(sts_data0);
1323 sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
1324 rxbuf = netxen_process_lro(adapter, sds_ring,
1325 ring, sts_data0, sts_data1);
3bf26ce3
DP		 1326 break;
1327 case NETXEN_NIC_RESPONSE_DESC:
1328 netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
1329 default:
1330 goto skip;
1331 }
1332
1333 WARN_ON(desc_cnt > 1);
1334
d8b100c5
DP		 1335 if (rxbuf)
1336 list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
1337
3bf26ce3
DP		 1338skip:
1339 for (; desc_cnt > 0; desc_cnt--) {
1340 desc = &sds_ring->desc_head[consumer];
1341 desc->status_desc_data[0] =
1342 cpu_to_le64(STATUS_OWNER_PHANTOM);
1343 consumer = get_next_index(consumer, sds_ring->num_desc);
1344 }
3d396eb1
AK		 1345 count++;
1346 }
0ddc110c 1347
d8b100c5
DP		 1348 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1349 struct nx_host_rds_ring *rds_ring =
1350 &adapter->recv_ctx.rds_rings[ring];
1351
1352 if (!list_empty(&sds_ring->free_list[ring])) {
1353 list_for_each(cur, &sds_ring->free_list[ring]) {
1354 rxbuf = list_entry(cur,
1355 struct netxen_rx_buffer, list);
1356 netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
1357 }
1358 spin_lock(&rds_ring->lock);
1359 netxen_merge_rx_buffers(&sds_ring->free_list[ring],
1360 &rds_ring->free_list);
1361 spin_unlock(&rds_ring->lock);
1362 }
1363
1364 netxen_post_rx_buffers_nodb(adapter, rds_ring);
1365 }
3d396eb1 1366
3d396eb1 1367 if (count) {
d8b100c5 1368 sds_ring->consumer = consumer;
195c5f98 1369 NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
3d396eb1
AK		 1370 }
1371
1372 return count;
1373}
1374
1375/* Process Command status ring */
05aaa02d 1376int netxen_process_cmd_ring(struct netxen_adapter *adapter)
3d396eb1 1377{
d877f1e3 1378 u32 sw_consumer, hw_consumer;
ba53e6b4 1379 int count = 0, i;
3d396eb1 1380 struct netxen_cmd_buffer *buffer;
ba53e6b4
DP		 1381 struct pci_dev *pdev = adapter->pdev;
1382 struct net_device *netdev = adapter->netdev;
3d396eb1 1383 struct netxen_skb_frag *frag;
ba53e6b4 1384 int done = 0;
4ea528a1 1385 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
3d396eb1 1386
d8b100c5
DP		 1387 if (!spin_trylock(&adapter->tx_clean_lock))
1388 return 1;
1389
d877f1e3 1390 sw_consumer = tx_ring->sw_consumer;
d877f1e3 1391 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
3d396eb1 1392
d877f1e3
DP		 1393 while (sw_consumer != hw_consumer) {
1394 buffer = &tx_ring->cmd_buf_arr[sw_consumer];
53a01e00 1395 if (buffer->skb) {
1396 frag = &buffer->frag_array[0];
3d396eb1
AK		 1397 pci_unmap_single(pdev, frag->dma, frag->length,
1398 PCI_DMA_TODEVICE);
96acb6eb 1399 frag->dma = 0ULL;
3d396eb1 1400 for (i = 1; i < buffer->frag_count; i++) {
3d396eb1
AK		 1401 frag++; /* Get the next frag */
1402 pci_unmap_page(pdev, frag->dma, frag->length,
1403 PCI_DMA_TODEVICE);
96acb6eb 1404 frag->dma = 0ULL;
3d396eb1
AK		 1405 }
1406
ba53e6b4 1407 adapter->stats.xmitfinished++;
53a01e00 1408 dev_kfree_skb_any(buffer->skb);
1409 buffer->skb = NULL;
3d396eb1
AK		 1410 }
1411
d877f1e3 1412 sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
ba53e6b4
DP		 1413 if (++count >= MAX_STATUS_HANDLE)
1414 break;
3d396eb1 1415 }
3d396eb1 1416
22527864 1417 if (count && netif_running(netdev)) {
cb2107be
DP		 1418 tx_ring->sw_consumer = sw_consumer;
1419
ba53e6b4 1420 smp_mb();
cb2107be 1421
22527864 1422 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
b2af9cb0 1423 __netif_tx_lock(tx_ring->txq, smp_processor_id());
74c520da 1424 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
cb2107be 1425 netif_wake_queue(netdev);
74c520da
AKS		 1426 adapter->tx_timeo_cnt = 0;
1427 }
b2af9cb0 1428 __netif_tx_unlock(tx_ring->txq);
3d396eb1
AK		 1429 }
1430 }
ed25ffa1
AK		 1431 /*
1432 * If everything is freed up to consumer then check if the ring is full
1433 * If the ring is full then check if more needs to be freed and
1434 * schedule the call back again.
1435 *
1436 * This happens when there are 2 CPUs. One could be freeing and the
1437 * other filling it. If the ring is full when we get out of here and
1438 * the card has already interrupted the host then the host can miss the
1439 * interrupt.
1440 *
1441 * There is still a possible race condition and the host could miss an
1442 * interrupt. The card has to take care of this.
1443 */
d877f1e3
DP		 1444 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1445 done = (sw_consumer == hw_consumer);
d8b100c5 1446 spin_unlock(&adapter->tx_clean_lock);
3d396eb1 1447
ed25ffa1 1448 return (done);
3d396eb1
AK		 1449}
1450
becf46a0 1451void
d8b100c5
DP		 1452netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1453 struct nx_host_rds_ring *rds_ring)
3d396eb1 1454{
3d396eb1
AK		 1455 struct rcv_desc *pdesc;
1456 struct netxen_rx_buffer *buffer;
d8b100c5 1457 int producer, count = 0;
ed25ffa1 1458 netxen_ctx_msg msg = 0;
d9e651bc 1459 struct list_head *head;
3d396eb1 1460
48bfd1e0 1461 producer = rds_ring->producer;
d9e651bc 1462
d8b100c5
DP		 1463 spin_lock(&rds_ring->lock);
1464 head = &rds_ring->free_list;
d9e651bc
DP		 1465 while (!list_empty(head)) {
1466
d8b100c5 1467 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1468
d8b100c5
DP		 1469 if (!buffer->skb) {
1470 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1471 break;
6f703406
DP		 1472 }
1473
1474 count++;
d9e651bc
DP		 1475 list_del(&buffer->list);
1476
ed25ffa1 1477 /* make a rcv descriptor */
6f703406 1478 pdesc = &rds_ring->desc_head[producer];
d8b100c5 1479 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
ed33ebe4 1480 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1481 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
6f703406 1482
438627c7 1483 producer = get_next_index(producer, rds_ring->num_desc);
ed25ffa1 1484 }
d8b100c5 1485 spin_unlock(&rds_ring->lock);
9b3ef55c 1486
ed25ffa1 1487 if (count) {
48bfd1e0 1488 rds_ring->producer = producer;
195c5f98 1489 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1490 (producer-1) & (rds_ring->num_desc-1));
48bfd1e0 1491
4f96b988 1492 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
ed25ffa1
AK		 1493 /*
1494 * Write a doorbell msg to tell phanmon of change in
1495 * receive ring producer
48bfd1e0 1496 * Only for firmware version < 4.0.0
ed25ffa1
AK		 1497 */
1498 netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
1499 netxen_set_msg_privid(msg);
1500 netxen_set_msg_count(msg,
438627c7
DP		 1501 ((producer - 1) &
1502 (rds_ring->num_desc - 1)));
3176ff3e 1503 netxen_set_msg_ctxid(msg, adapter->portnum);
ed25ffa1 1504 netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
f03b0ebd
DP		 1505 NXWRIO(adapter, DB_NORMALIZE(adapter,
1506 NETXEN_RCV_PRODUCER_OFFSET), msg);
48bfd1e0 1507 }
ed25ffa1
AK		 1508 }
1509}
1510
becf46a0 1511static void
d8b100c5
DP		 1512netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1513 struct nx_host_rds_ring *rds_ring)
ed25ffa1 1514{
ed25ffa1
AK		 1515 struct rcv_desc *pdesc;
1516 struct netxen_rx_buffer *buffer;
d8b100c5 1517 int producer, count = 0;
d9e651bc 1518 struct list_head *head;
ed25ffa1 1519
48bfd1e0 1520 producer = rds_ring->producer;
d8b100c5
DP		 1521 if (!spin_trylock(&rds_ring->lock))
1522 return;
1523
d9e651bc 1524 head = &rds_ring->free_list;
d9e651bc
DP		 1525 while (!list_empty(head)) {
1526
d8b100c5 1527 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1528
d8b100c5
DP		 1529 if (!buffer->skb) {
1530 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1531 break;
6f703406
DP		 1532 }
1533
1534 count++;
d9e651bc
DP		 1535 list_del(&buffer->list);
1536
3d396eb1 1537 /* make a rcv descriptor */
6f703406 1538 pdesc = &rds_ring->desc_head[producer];
ed33ebe4 1539 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1540 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
3d396eb1 1541 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
6f703406 1542
438627c7 1543 producer = get_next_index(producer, rds_ring->num_desc);
3d396eb1
AK		 1544 }
1545
3d396eb1 1546 if (count) {
48bfd1e0 1547 rds_ring->producer = producer;
195c5f98 1548 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1549 (producer - 1) & (rds_ring->num_desc - 1));
3d396eb1 1550 }
d8b100c5 1551 spin_unlock(&rds_ring->lock);
3d396eb1
AK		 1552}
1553
3d396eb1
AK		 1554void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1555{
3d396eb1 1556 memset(&adapter->stats, 0, sizeof(adapter->stats));
3176ff3e 1557 return;
3d396eb1
AK		 1558}
1559
ubuntu-bionic-kernel mirror