]>
Commit | Line | Data |
---|---|---|
3d396eb1 | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
3d396eb1 | 3 | * All rights reserved. |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
5d242f1c DP |
25 | * NetXen Inc, |
26 | * 18922 Forge Drive | |
27 | * Cupertino, CA 95014-0701 | |
3d396eb1 AK |
28 | * |
29 | */ | |
30 | ||
31 | #include <linux/netdevice.h> | |
32 | #include <linux/delay.h> | |
33 | #include "netxen_nic.h" | |
34 | #include "netxen_nic_hw.h" | |
3d396eb1 AK |
35 | #include "netxen_nic_phan_reg.h" |
36 | ||
37 | struct crb_addr_pair { | |
e0e20a1a LCMT |
38 | u32 addr; |
39 | u32 data; | |
3d396eb1 AK |
40 | }; |
41 | ||
42 | #define NETXEN_MAX_CRB_XFORM 60 | |
43 | static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM]; | |
e0e20a1a | 44 | #define NETXEN_ADDR_ERROR (0xffffffff) |
3d396eb1 AK |
45 | |
46 | #define crb_addr_transform(name) \ | |
47 | crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \ | |
48 | NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20 | |
49 | ||
cb8011ad AK |
50 | #define NETXEN_NIC_XDMA_RESET 0x8000ff |
51 | ||
becf46a0 | 52 | static void |
d8b100c5 DP |
53 | netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
54 | struct nx_host_rds_ring *rds_ring); | |
993fb90c | 55 | |
3d396eb1 AK |
56 | static void crb_addr_transform_setup(void) |
57 | { | |
58 | crb_addr_transform(XDMA); | |
59 | crb_addr_transform(TIMR); | |
60 | crb_addr_transform(SRE); | |
61 | crb_addr_transform(SQN3); | |
62 | crb_addr_transform(SQN2); | |
63 | crb_addr_transform(SQN1); | |
64 | crb_addr_transform(SQN0); | |
65 | crb_addr_transform(SQS3); | |
66 | crb_addr_transform(SQS2); | |
67 | crb_addr_transform(SQS1); | |
68 | crb_addr_transform(SQS0); | |
69 | crb_addr_transform(RPMX7); | |
70 | crb_addr_transform(RPMX6); | |
71 | crb_addr_transform(RPMX5); | |
72 | crb_addr_transform(RPMX4); | |
73 | crb_addr_transform(RPMX3); | |
74 | crb_addr_transform(RPMX2); | |
75 | crb_addr_transform(RPMX1); | |
76 | crb_addr_transform(RPMX0); | |
77 | crb_addr_transform(ROMUSB); | |
78 | crb_addr_transform(SN); | |
79 | crb_addr_transform(QMN); | |
80 | crb_addr_transform(QMS); | |
81 | crb_addr_transform(PGNI); | |
82 | crb_addr_transform(PGND); | |
83 | crb_addr_transform(PGN3); | |
84 | crb_addr_transform(PGN2); | |
85 | crb_addr_transform(PGN1); | |
86 | crb_addr_transform(PGN0); | |
87 | crb_addr_transform(PGSI); | |
88 | crb_addr_transform(PGSD); | |
89 | crb_addr_transform(PGS3); | |
90 | crb_addr_transform(PGS2); | |
91 | crb_addr_transform(PGS1); | |
92 | crb_addr_transform(PGS0); | |
93 | crb_addr_transform(PS); | |
94 | crb_addr_transform(PH); | |
95 | crb_addr_transform(NIU); | |
96 | crb_addr_transform(I2Q); | |
97 | crb_addr_transform(EG); | |
98 | crb_addr_transform(MN); | |
99 | crb_addr_transform(MS); | |
100 | crb_addr_transform(CAS2); | |
101 | crb_addr_transform(CAS1); | |
102 | crb_addr_transform(CAS0); | |
103 | crb_addr_transform(CAM); | |
104 | crb_addr_transform(C2C1); | |
105 | crb_addr_transform(C2C0); | |
1fcca1a5 | 106 | crb_addr_transform(SMB); |
e4c93c81 DP |
107 | crb_addr_transform(OCM0); |
108 | crb_addr_transform(I2C0); | |
3d396eb1 AK |
109 | } |
110 | ||
2956640d | 111 | void netxen_release_rx_buffers(struct netxen_adapter *adapter) |
3d396eb1 | 112 | { |
2956640d | 113 | struct netxen_recv_context *recv_ctx; |
48bfd1e0 | 114 | struct nx_host_rds_ring *rds_ring; |
2956640d | 115 | struct netxen_rx_buffer *rx_buf; |
becf46a0 DP |
116 | int i, ring; |
117 | ||
118 | recv_ctx = &adapter->recv_ctx; | |
119 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
120 | rds_ring = &recv_ctx->rds_rings[ring]; | |
438627c7 | 121 | for (i = 0; i < rds_ring->num_desc; ++i) { |
becf46a0 DP |
122 | rx_buf = &(rds_ring->rx_buf_arr[i]); |
123 | if (rx_buf->state == NETXEN_BUFFER_FREE) | |
124 | continue; | |
125 | pci_unmap_single(adapter->pdev, | |
126 | rx_buf->dma, | |
127 | rds_ring->dma_size, | |
128 | PCI_DMA_FROMDEVICE); | |
129 | if (rx_buf->skb != NULL) | |
130 | dev_kfree_skb_any(rx_buf->skb); | |
2956640d DP |
131 | } |
132 | } | |
133 | } | |
134 | ||
135 | void netxen_release_tx_buffers(struct netxen_adapter *adapter) | |
136 | { | |
137 | struct netxen_cmd_buffer *cmd_buf; | |
138 | struct netxen_skb_frag *buffrag; | |
139 | int i, j; | |
4ea528a1 | 140 | struct nx_host_tx_ring *tx_ring = adapter->tx_ring; |
2956640d | 141 | |
d877f1e3 DP |
142 | cmd_buf = tx_ring->cmd_buf_arr; |
143 | for (i = 0; i < tx_ring->num_desc; i++) { | |
2956640d DP |
144 | buffrag = cmd_buf->frag_array; |
145 | if (buffrag->dma) { | |
146 | pci_unmap_single(adapter->pdev, buffrag->dma, | |
147 | buffrag->length, PCI_DMA_TODEVICE); | |
148 | buffrag->dma = 0ULL; | |
149 | } | |
150 | for (j = 0; j < cmd_buf->frag_count; j++) { | |
151 | buffrag++; | |
152 | if (buffrag->dma) { | |
153 | pci_unmap_page(adapter->pdev, buffrag->dma, | |
154 | buffrag->length, | |
155 | PCI_DMA_TODEVICE); | |
156 | buffrag->dma = 0ULL; | |
157 | } | |
158 | } | |
2956640d DP |
159 | if (cmd_buf->skb) { |
160 | dev_kfree_skb_any(cmd_buf->skb); | |
161 | cmd_buf->skb = NULL; | |
162 | } | |
163 | cmd_buf++; | |
164 | } | |
165 | } | |
166 | ||
167 | void netxen_free_sw_resources(struct netxen_adapter *adapter) | |
168 | { | |
169 | struct netxen_recv_context *recv_ctx; | |
48bfd1e0 | 170 | struct nx_host_rds_ring *rds_ring; |
d877f1e3 | 171 | struct nx_host_tx_ring *tx_ring; |
becf46a0 DP |
172 | int ring; |
173 | ||
174 | recv_ctx = &adapter->recv_ctx; | |
4ea528a1 DP |
175 | |
176 | if (recv_ctx->rds_rings == NULL) | |
177 | goto skip_rds; | |
178 | ||
becf46a0 DP |
179 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
180 | rds_ring = &recv_ctx->rds_rings[ring]; | |
f2333a01 F |
181 | vfree(rds_ring->rx_buf_arr); |
182 | rds_ring->rx_buf_arr = NULL; | |
2956640d | 183 | } |
4ea528a1 DP |
184 | kfree(recv_ctx->rds_rings); |
185 | ||
186 | skip_rds: | |
187 | if (adapter->tx_ring == NULL) | |
188 | return; | |
becf46a0 | 189 | |
4ea528a1 | 190 | tx_ring = adapter->tx_ring; |
f2333a01 | 191 | vfree(tx_ring->cmd_buf_arr); |
2956640d DP |
192 | } |
193 | ||
194 | int netxen_alloc_sw_resources(struct netxen_adapter *adapter) | |
195 | { | |
196 | struct netxen_recv_context *recv_ctx; | |
48bfd1e0 | 197 | struct nx_host_rds_ring *rds_ring; |
d8b100c5 | 198 | struct nx_host_sds_ring *sds_ring; |
4ea528a1 | 199 | struct nx_host_tx_ring *tx_ring; |
2956640d | 200 | struct netxen_rx_buffer *rx_buf; |
4ea528a1 | 201 | int ring, i, size; |
2956640d DP |
202 | |
203 | struct netxen_cmd_buffer *cmd_buf_arr; | |
204 | struct net_device *netdev = adapter->netdev; | |
d877f1e3 | 205 | struct pci_dev *pdev = adapter->pdev; |
2956640d | 206 | |
4ea528a1 DP |
207 | size = sizeof(struct nx_host_tx_ring); |
208 | tx_ring = kzalloc(size, GFP_KERNEL); | |
209 | if (tx_ring == NULL) { | |
210 | dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n", | |
211 | netdev->name); | |
212 | return -ENOMEM; | |
213 | } | |
214 | adapter->tx_ring = tx_ring; | |
215 | ||
d877f1e3 | 216 | tx_ring->num_desc = adapter->num_txd; |
4ea528a1 DP |
217 | |
218 | cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring)); | |
2956640d | 219 | if (cmd_buf_arr == NULL) { |
d877f1e3 | 220 | dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n", |
2956640d DP |
221 | netdev->name); |
222 | return -ENOMEM; | |
223 | } | |
d877f1e3 DP |
224 | memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring)); |
225 | tx_ring->cmd_buf_arr = cmd_buf_arr; | |
2956640d | 226 | |
becf46a0 | 227 | recv_ctx = &adapter->recv_ctx; |
4ea528a1 DP |
228 | |
229 | size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring); | |
230 | rds_ring = kzalloc(size, GFP_KERNEL); | |
231 | if (rds_ring == NULL) { | |
232 | dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n", | |
233 | netdev->name); | |
234 | return -ENOMEM; | |
235 | } | |
236 | recv_ctx->rds_rings = rds_ring; | |
237 | ||
becf46a0 DP |
238 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
239 | rds_ring = &recv_ctx->rds_rings[ring]; | |
438627c7 DP |
240 | switch (ring) { |
241 | case RCV_RING_NORMAL: | |
242 | rds_ring->num_desc = adapter->num_rxd; | |
becf46a0 DP |
243 | if (adapter->ahw.cut_through) { |
244 | rds_ring->dma_size = | |
245 | NX_CT_DEFAULT_RX_BUF_LEN; | |
48bfd1e0 | 246 | rds_ring->skb_size = |
becf46a0 DP |
247 | NX_CT_DEFAULT_RX_BUF_LEN; |
248 | } else { | |
249 | rds_ring->dma_size = RX_DMA_MAP_LEN; | |
250 | rds_ring->skb_size = | |
251 | MAX_RX_BUFFER_LENGTH; | |
252 | } | |
253 | break; | |
2956640d | 254 | |
438627c7 DP |
255 | case RCV_RING_JUMBO: |
256 | rds_ring->num_desc = adapter->num_jumbo_rxd; | |
becf46a0 DP |
257 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
258 | rds_ring->dma_size = | |
259 | NX_P3_RX_JUMBO_BUF_MAX_LEN; | |
260 | else | |
261 | rds_ring->dma_size = | |
262 | NX_P2_RX_JUMBO_BUF_MAX_LEN; | |
263 | rds_ring->skb_size = | |
264 | rds_ring->dma_size + NET_IP_ALIGN; | |
265 | break; | |
2956640d | 266 | |
becf46a0 | 267 | case RCV_RING_LRO: |
438627c7 | 268 | rds_ring->num_desc = adapter->num_lro_rxd; |
becf46a0 DP |
269 | rds_ring->dma_size = RX_LRO_DMA_MAP_LEN; |
270 | rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH; | |
271 | break; | |
272 | ||
273 | } | |
274 | rds_ring->rx_buf_arr = (struct netxen_rx_buffer *) | |
d8b100c5 | 275 | vmalloc(RCV_BUFF_RINGSIZE(rds_ring)); |
becf46a0 DP |
276 | if (rds_ring->rx_buf_arr == NULL) { |
277 | printk(KERN_ERR "%s: Failed to allocate " | |
278 | "rx buffer ring %d\n", | |
279 | netdev->name, ring); | |
280 | /* free whatever was already allocated */ | |
281 | goto err_out; | |
282 | } | |
d8b100c5 | 283 | memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring)); |
becf46a0 DP |
284 | INIT_LIST_HEAD(&rds_ring->free_list); |
285 | /* | |
286 | * Now go through all of them, set reference handles | |
287 | * and put them in the queues. | |
288 | */ | |
becf46a0 | 289 | rx_buf = rds_ring->rx_buf_arr; |
4ea528a1 | 290 | for (i = 0; i < rds_ring->num_desc; i++) { |
becf46a0 DP |
291 | list_add_tail(&rx_buf->list, |
292 | &rds_ring->free_list); | |
293 | rx_buf->ref_handle = i; | |
294 | rx_buf->state = NETXEN_BUFFER_FREE; | |
295 | rx_buf++; | |
3d396eb1 | 296 | } |
d8b100c5 DP |
297 | spin_lock_init(&rds_ring->lock); |
298 | } | |
299 | ||
300 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | |
301 | sds_ring = &recv_ctx->sds_rings[ring]; | |
302 | sds_ring->irq = adapter->msix_entries[ring].vector; | |
d8b100c5 DP |
303 | sds_ring->adapter = adapter; |
304 | sds_ring->num_desc = adapter->num_rxd; | |
305 | ||
306 | for (i = 0; i < NUM_RCV_DESC_RINGS; i++) | |
307 | INIT_LIST_HEAD(&sds_ring->free_list[i]); | |
3d396eb1 | 308 | } |
2956640d DP |
309 | |
310 | return 0; | |
311 | ||
312 | err_out: | |
313 | netxen_free_sw_resources(adapter); | |
314 | return -ENOMEM; | |
3d396eb1 AK |
315 | } |
316 | ||
3d396eb1 AK |
317 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter) |
318 | { | |
3d0a3cc9 DP |
319 | adapter->macaddr_set = netxen_p2_nic_set_mac_addr; |
320 | adapter->set_multi = netxen_p2_nic_set_multi; | |
321 | ||
1e2d0059 | 322 | switch (adapter->ahw.port_type) { |
3d396eb1 | 323 | case NETXEN_NIC_GBE: |
80922fbc | 324 | adapter->enable_phy_interrupts = |
3d396eb1 | 325 | netxen_niu_gbe_enable_phy_interrupts; |
80922fbc | 326 | adapter->disable_phy_interrupts = |
3d396eb1 | 327 | netxen_niu_gbe_disable_phy_interrupts; |
80922fbc AK |
328 | adapter->set_mtu = netxen_nic_set_mtu_gb; |
329 | adapter->set_promisc = netxen_niu_set_promiscuous_mode; | |
80922fbc AK |
330 | adapter->phy_read = netxen_niu_gbe_phy_read; |
331 | adapter->phy_write = netxen_niu_gbe_phy_write; | |
c9fc891f | 332 | adapter->init_port = netxen_niu_gbe_init_port; |
80922fbc | 333 | adapter->stop_port = netxen_niu_disable_gbe_port; |
3d396eb1 AK |
334 | break; |
335 | ||
336 | case NETXEN_NIC_XGBE: | |
80922fbc | 337 | adapter->enable_phy_interrupts = |
3d396eb1 | 338 | netxen_niu_xgbe_enable_phy_interrupts; |
80922fbc | 339 | adapter->disable_phy_interrupts = |
3d396eb1 | 340 | netxen_niu_xgbe_disable_phy_interrupts; |
80922fbc AK |
341 | adapter->set_mtu = netxen_nic_set_mtu_xgb; |
342 | adapter->init_port = netxen_niu_xg_init_port; | |
343 | adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode; | |
80922fbc | 344 | adapter->stop_port = netxen_niu_disable_xg_port; |
3d396eb1 AK |
345 | break; |
346 | ||
347 | default: | |
348 | break; | |
349 | } | |
9ad27643 DP |
350 | |
351 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | |
352 | adapter->set_mtu = nx_fw_cmd_set_mtu; | |
353 | adapter->set_promisc = netxen_p3_nic_set_promisc; | |
3d0a3cc9 DP |
354 | adapter->macaddr_set = netxen_p3_nic_set_mac_addr; |
355 | adapter->set_multi = netxen_p3_nic_set_multi; | |
9ad27643 | 356 | } |
3d396eb1 AK |
357 | } |
358 | ||
359 | /* | |
360 | * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB | |
361 | * address to external PCI CRB address. | |
362 | */ | |
993fb90c | 363 | static u32 netxen_decode_crb_addr(u32 addr) |
3d396eb1 AK |
364 | { |
365 | int i; | |
e0e20a1a | 366 | u32 base_addr, offset, pci_base; |
3d396eb1 AK |
367 | |
368 | crb_addr_transform_setup(); | |
369 | ||
370 | pci_base = NETXEN_ADDR_ERROR; | |
371 | base_addr = addr & 0xfff00000; | |
372 | offset = addr & 0x000fffff; | |
373 | ||
374 | for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) { | |
375 | if (crb_addr_xform[i] == base_addr) { | |
376 | pci_base = i << 20; | |
377 | break; | |
378 | } | |
379 | } | |
380 | if (pci_base == NETXEN_ADDR_ERROR) | |
381 | return pci_base; | |
382 | else | |
383 | return (pci_base + offset); | |
384 | } | |
385 | ||
13ba9c77 MT |
386 | static long rom_max_timeout = 100; |
387 | static long rom_lock_timeout = 10000; | |
3d396eb1 | 388 | |
993fb90c | 389 | static int rom_lock(struct netxen_adapter *adapter) |
3d396eb1 AK |
390 | { |
391 | int iter; | |
392 | u32 done = 0; | |
393 | int timeout = 0; | |
394 | ||
395 | while (!done) { | |
396 | /* acquire semaphore2 from PCI HW block */ | |
f98a9f69 | 397 | done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK)); |
3d396eb1 AK |
398 | if (done == 1) |
399 | break; | |
400 | if (timeout >= rom_lock_timeout) | |
401 | return -EIO; | |
402 | ||
403 | timeout++; | |
404 | /* | |
405 | * Yield CPU | |
406 | */ | |
407 | if (!in_atomic()) | |
408 | schedule(); | |
409 | else { | |
410 | for (iter = 0; iter < 20; iter++) | |
411 | cpu_relax(); /*This a nop instr on i386 */ | |
412 | } | |
413 | } | |
f98a9f69 | 414 | NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER); |
3d396eb1 AK |
415 | return 0; |
416 | } | |
417 | ||
993fb90c | 418 | static int netxen_wait_rom_done(struct netxen_adapter *adapter) |
3d396eb1 AK |
419 | { |
420 | long timeout = 0; | |
421 | long done = 0; | |
422 | ||
27c915a4 DP |
423 | cond_resched(); |
424 | ||
3d396eb1 | 425 | while (done == 0) { |
f98a9f69 | 426 | done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS); |
3d396eb1 AK |
427 | done &= 2; |
428 | timeout++; | |
429 | if (timeout >= rom_max_timeout) { | |
430 | printk("Timeout reached waiting for rom done"); | |
431 | return -EIO; | |
432 | } | |
433 | } | |
434 | return 0; | |
435 | } | |
436 | ||
993fb90c | 437 | static void netxen_rom_unlock(struct netxen_adapter *adapter) |
cb8011ad | 438 | { |
cb8011ad | 439 | /* release semaphore2 */ |
f98a9f69 | 440 | NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK)); |
cb8011ad AK |
441 | |
442 | } | |
443 | ||
993fb90c AB |
444 | static int do_rom_fast_read(struct netxen_adapter *adapter, |
445 | int addr, int *valp) | |
3d396eb1 | 446 | { |
f98a9f69 DP |
447 | NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); |
448 | NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); | |
449 | NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
450 | NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); | |
3d396eb1 AK |
451 | if (netxen_wait_rom_done(adapter)) { |
452 | printk("Error waiting for rom done\n"); | |
453 | return -EIO; | |
454 | } | |
455 | /* reset abyte_cnt and dummy_byte_cnt */ | |
f98a9f69 | 456 | NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); |
27c915a4 | 457 | udelay(10); |
f98a9f69 | 458 | NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
3d396eb1 | 459 | |
f98a9f69 | 460 | *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA); |
3d396eb1 AK |
461 | return 0; |
462 | } | |
463 | ||
993fb90c AB |
464 | static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
465 | u8 *bytes, size_t size) | |
27d2ab54 AK |
466 | { |
467 | int addridx; | |
468 | int ret = 0; | |
469 | ||
470 | for (addridx = addr; addridx < (addr + size); addridx += 4) { | |
f305f789 AV |
471 | int v; |
472 | ret = do_rom_fast_read(adapter, addridx, &v); | |
27d2ab54 AK |
473 | if (ret != 0) |
474 | break; | |
f305f789 | 475 | *(__le32 *)bytes = cpu_to_le32(v); |
27d2ab54 AK |
476 | bytes += 4; |
477 | } | |
478 | ||
479 | return ret; | |
480 | } | |
481 | ||
482 | int | |
4790654c | 483 | netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
484 | u8 *bytes, size_t size) |
485 | { | |
486 | int ret; | |
487 | ||
488 | ret = rom_lock(adapter); | |
489 | if (ret < 0) | |
490 | return ret; | |
491 | ||
492 | ret = do_rom_fast_read_words(adapter, addr, bytes, size); | |
493 | ||
494 | netxen_rom_unlock(adapter); | |
495 | return ret; | |
496 | } | |
497 | ||
3d396eb1 AK |
498 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp) |
499 | { | |
500 | int ret; | |
501 | ||
502 | if (rom_lock(adapter) != 0) | |
503 | return -EIO; | |
504 | ||
505 | ret = do_rom_fast_read(adapter, addr, valp); | |
cb8011ad AK |
506 | netxen_rom_unlock(adapter); |
507 | return ret; | |
508 | } | |
509 | ||
3d396eb1 AK |
510 | #define NETXEN_BOARDTYPE 0x4008 |
511 | #define NETXEN_BOARDNUM 0x400c | |
512 | #define NETXEN_CHIPNUM 0x4010 | |
3d396eb1 AK |
513 | |
514 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose) | |
515 | { | |
dcd56fdb | 516 | int addr, val; |
27c915a4 | 517 | int i, n, init_delay = 0; |
3d396eb1 | 518 | struct crb_addr_pair *buf; |
27c915a4 | 519 | unsigned offset; |
e0e20a1a | 520 | u32 off; |
3d396eb1 AK |
521 | |
522 | /* resetall */ | |
27c915a4 | 523 | rom_lock(adapter); |
f98a9f69 | 524 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff); |
27c915a4 | 525 | netxen_rom_unlock(adapter); |
3d396eb1 AK |
526 | |
527 | if (verbose) { | |
3d396eb1 AK |
528 | if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0) |
529 | printk("P2 ROM board type: 0x%08x\n", val); | |
530 | else | |
531 | printk("Could not read board type\n"); | |
532 | if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0) | |
533 | printk("P2 ROM board num: 0x%08x\n", val); | |
534 | else | |
535 | printk("Could not read board number\n"); | |
536 | if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0) | |
537 | printk("P2 ROM chip num: 0x%08x\n", val); | |
538 | else | |
539 | printk("Could not read chip number\n"); | |
540 | } | |
541 | ||
2956640d DP |
542 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
543 | if (netxen_rom_fast_read(adapter, 0, &n) != 0 || | |
27c915a4 | 544 | (n != 0xcafecafe) || |
2956640d DP |
545 | netxen_rom_fast_read(adapter, 4, &n) != 0) { |
546 | printk(KERN_ERR "%s: ERROR Reading crb_init area: " | |
547 | "n: %08x\n", netxen_nic_driver_name, n); | |
3d396eb1 AK |
548 | return -EIO; |
549 | } | |
2956640d DP |
550 | offset = n & 0xffffU; |
551 | n = (n >> 16) & 0xffffU; | |
552 | } else { | |
553 | if (netxen_rom_fast_read(adapter, 0, &n) != 0 || | |
554 | !(n & 0x80000000)) { | |
555 | printk(KERN_ERR "%s: ERROR Reading crb_init area: " | |
556 | "n: %08x\n", netxen_nic_driver_name, n); | |
557 | return -EIO; | |
3d396eb1 | 558 | } |
2956640d DP |
559 | offset = 1; |
560 | n &= ~0x80000000; | |
561 | } | |
562 | ||
563 | if (n < 1024) { | |
564 | if (verbose) | |
565 | printk(KERN_DEBUG "%s: %d CRB init values found" | |
566 | " in ROM.\n", netxen_nic_driver_name, n); | |
567 | } else { | |
568 | printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not" | |
569 | " initialized.\n", __func__, n); | |
570 | return -EIO; | |
571 | } | |
3d396eb1 | 572 | |
2956640d DP |
573 | buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL); |
574 | if (buf == NULL) { | |
575 | printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n", | |
576 | netxen_nic_driver_name); | |
577 | return -ENOMEM; | |
578 | } | |
579 | for (i = 0; i < n; i++) { | |
580 | if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 || | |
584dbe94 DM |
581 | netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) { |
582 | kfree(buf); | |
2956640d | 583 | return -EIO; |
584dbe94 | 584 | } |
2956640d DP |
585 | |
586 | buf[i].addr = addr; | |
587 | buf[i].data = val; | |
588 | ||
589 | if (verbose) | |
590 | printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n", | |
591 | netxen_nic_driver_name, | |
592 | (u32)netxen_decode_crb_addr(addr), val); | |
593 | } | |
594 | for (i = 0; i < n; i++) { | |
595 | ||
596 | off = netxen_decode_crb_addr(buf[i].addr); | |
597 | if (off == NETXEN_ADDR_ERROR) { | |
598 | printk(KERN_ERR"CRB init value out of range %x\n", | |
1fcca1a5 | 599 | buf[i].addr); |
2956640d DP |
600 | continue; |
601 | } | |
602 | off += NETXEN_PCI_CRBSPACE; | |
603 | /* skipping cold reboot MAGIC */ | |
604 | if (off == NETXEN_CAM_RAM(0x1fc)) | |
605 | continue; | |
606 | ||
607 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | |
608 | /* do not reset PCI */ | |
609 | if (off == (ROMUSB_GLB + 0xbc)) | |
1fcca1a5 | 610 | continue; |
27c915a4 DP |
611 | if (off == (ROMUSB_GLB + 0xa8)) |
612 | continue; | |
613 | if (off == (ROMUSB_GLB + 0xc8)) /* core clock */ | |
614 | continue; | |
615 | if (off == (ROMUSB_GLB + 0x24)) /* MN clock */ | |
616 | continue; | |
617 | if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */ | |
618 | continue; | |
2956640d DP |
619 | if (off == (NETXEN_CRB_PEG_NET_1 + 0x18)) |
620 | buf[i].data = 0x1020; | |
621 | /* skip the function enable register */ | |
622 | if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION)) | |
3d396eb1 | 623 | continue; |
2956640d DP |
624 | if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2)) |
625 | continue; | |
626 | if ((off & 0x0ff00000) == NETXEN_CRB_SMB) | |
627 | continue; | |
628 | } | |
3d396eb1 | 629 | |
2956640d DP |
630 | if (off == NETXEN_ADDR_ERROR) { |
631 | printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n", | |
632 | netxen_nic_driver_name, buf[i].addr); | |
633 | continue; | |
634 | } | |
635 | ||
27c915a4 | 636 | init_delay = 1; |
2956640d DP |
637 | /* After writing this register, HW needs time for CRB */ |
638 | /* to quiet down (else crb_window returns 0xffffffff) */ | |
639 | if (off == NETXEN_ROMUSB_GLB_SW_RESET) { | |
27c915a4 | 640 | init_delay = 1000; |
2956640d | 641 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
3d396eb1 | 642 | /* hold xdma in reset also */ |
cb8011ad | 643 | buf[i].data = NETXEN_NIC_XDMA_RESET; |
27c915a4 | 644 | buf[i].data = 0x8000ff; |
3d396eb1 | 645 | } |
2956640d | 646 | } |
3d396eb1 | 647 | |
f98a9f69 | 648 | NXWR32(adapter, off, buf[i].data); |
3d396eb1 | 649 | |
27c915a4 | 650 | msleep(init_delay); |
2956640d DP |
651 | } |
652 | kfree(buf); | |
3d396eb1 | 653 | |
2956640d | 654 | /* disable_peg_cache_all */ |
3d396eb1 | 655 | |
2956640d DP |
656 | /* unreset_net_cache */ |
657 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
f98a9f69 DP |
658 | val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET); |
659 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f)); | |
3d396eb1 | 660 | } |
2956640d DP |
661 | |
662 | /* p2dn replyCount */ | |
f98a9f69 | 663 | NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); |
2956640d | 664 | /* disable_peg_cache 0 */ |
f98a9f69 | 665 | NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8); |
2956640d | 666 | /* disable_peg_cache 1 */ |
f98a9f69 | 667 | NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8); |
2956640d DP |
668 | |
669 | /* peg_clr_all */ | |
670 | ||
671 | /* peg_clr 0 */ | |
f98a9f69 DP |
672 | NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0); |
673 | NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0); | |
2956640d | 674 | /* peg_clr 1 */ |
f98a9f69 DP |
675 | NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0); |
676 | NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0); | |
2956640d | 677 | /* peg_clr 2 */ |
f98a9f69 DP |
678 | NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0); |
679 | NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0); | |
2956640d | 680 | /* peg_clr 3 */ |
f98a9f69 DP |
681 | NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0); |
682 | NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0); | |
3d396eb1 AK |
683 | return 0; |
684 | } | |
685 | ||
f7185c71 DP |
686 | int |
687 | netxen_load_firmware(struct netxen_adapter *adapter) | |
688 | { | |
689 | u64 *ptr64; | |
690 | u32 i, flashaddr, size; | |
691 | const struct firmware *fw = adapter->fw; | |
692 | ||
693 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
694 | NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1); | |
695 | ||
696 | if (fw) { | |
697 | __le64 data; | |
698 | ||
699 | size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8; | |
700 | ||
701 | ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START]; | |
702 | flashaddr = NETXEN_BOOTLD_START; | |
703 | ||
704 | for (i = 0; i < size; i++) { | |
705 | data = cpu_to_le64(ptr64[i]); | |
706 | adapter->pci_mem_write(adapter, flashaddr, &data, 8); | |
707 | flashaddr += 8; | |
708 | } | |
709 | ||
710 | size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET]; | |
711 | size = (__force u32)cpu_to_le32(size) / 8; | |
712 | ||
713 | ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START]; | |
714 | flashaddr = NETXEN_IMAGE_START; | |
715 | ||
716 | for (i = 0; i < size; i++) { | |
717 | data = cpu_to_le64(ptr64[i]); | |
718 | ||
719 | if (adapter->pci_mem_write(adapter, | |
720 | flashaddr, &data, 8)) | |
721 | return -EIO; | |
722 | ||
723 | flashaddr += 8; | |
724 | } | |
725 | } else { | |
726 | u32 data; | |
727 | ||
728 | size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4; | |
729 | flashaddr = NETXEN_BOOTLD_START; | |
730 | ||
731 | for (i = 0; i < size; i++) { | |
732 | if (netxen_rom_fast_read(adapter, | |
733 | flashaddr, (int *)&data) != 0) | |
734 | return -EIO; | |
735 | ||
736 | if (adapter->pci_mem_write(adapter, | |
737 | flashaddr, &data, 4)) | |
738 | return -EIO; | |
739 | ||
740 | flashaddr += 4; | |
741 | } | |
742 | } | |
743 | msleep(1); | |
744 | ||
745 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | |
746 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d); | |
747 | else { | |
748 | NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff); | |
749 | NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0); | |
750 | } | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
755 | static int | |
756 | netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname) | |
757 | { | |
758 | __le32 val; | |
759 | u32 major, minor, build, ver, min_ver, bios; | |
760 | struct pci_dev *pdev = adapter->pdev; | |
761 | const struct firmware *fw = adapter->fw; | |
762 | ||
763 | if (fw->size < NX_FW_MIN_SIZE) | |
764 | return -EINVAL; | |
765 | ||
766 | val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]); | |
767 | if ((__force u32)val != NETXEN_BDINFO_MAGIC) | |
768 | return -EINVAL; | |
769 | ||
770 | val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]); | |
771 | major = (__force u32)val & 0xff; | |
772 | minor = ((__force u32)val >> 8) & 0xff; | |
773 | build = (__force u32)val >> 16; | |
774 | ||
775 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | |
776 | min_ver = NETXEN_VERSION_CODE(4, 0, 216); | |
777 | else | |
778 | min_ver = NETXEN_VERSION_CODE(3, 4, 216); | |
779 | ||
780 | ver = NETXEN_VERSION_CODE(major, minor, build); | |
781 | ||
782 | if ((major > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) { | |
783 | dev_err(&pdev->dev, | |
784 | "%s: firmware version %d.%d.%d unsupported\n", | |
785 | fwname, major, minor, build); | |
786 | return -EINVAL; | |
787 | } | |
788 | ||
789 | val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]); | |
790 | netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios); | |
791 | if ((__force u32)val != bios) { | |
792 | dev_err(&pdev->dev, "%s: firmware bios is incompatible\n", | |
793 | fwname); | |
794 | return -EINVAL; | |
795 | } | |
796 | ||
797 | /* check if flashed firmware is newer */ | |
798 | if (netxen_rom_fast_read(adapter, | |
799 | NX_FW_VERSION_OFFSET, (int *)&val)) | |
800 | return -EIO; | |
801 | major = (__force u32)val & 0xff; | |
802 | minor = ((__force u32)val >> 8) & 0xff; | |
803 | build = (__force u32)val >> 16; | |
804 | if (NETXEN_VERSION_CODE(major, minor, build) > ver) | |
805 | return -EINVAL; | |
806 | ||
807 | NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC); | |
808 | return 0; | |
809 | } | |
810 | ||
811 | static char *fw_name[] = { "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin" }; | |
812 | ||
813 | void netxen_request_firmware(struct netxen_adapter *adapter) | |
814 | { | |
815 | u32 capability, flashed_ver; | |
816 | int fw_type; | |
817 | struct pci_dev *pdev = adapter->pdev; | |
818 | int rc = 0; | |
819 | ||
820 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
821 | fw_type = NX_P2_MN_ROMIMAGE; | |
822 | goto request_fw; | |
823 | } else { | |
824 | fw_type = NX_P3_CT_ROMIMAGE; | |
825 | goto request_fw; | |
826 | } | |
827 | ||
828 | request_mn: | |
829 | capability = 0; | |
830 | ||
831 | netxen_rom_fast_read(adapter, | |
832 | NX_FW_VERSION_OFFSET, (int *)&flashed_ver); | |
833 | if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) { | |
834 | capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY); | |
835 | if (capability & NX_PEG_TUNE_MN_PRESENT) { | |
836 | fw_type = NX_P3_MN_ROMIMAGE; | |
837 | goto request_fw; | |
838 | } | |
839 | } | |
840 | ||
841 | request_fw: | |
842 | rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev); | |
843 | if (rc != 0) { | |
844 | if (fw_type == NX_P3_CT_ROMIMAGE) { | |
845 | msleep(1); | |
846 | goto request_mn; | |
847 | } | |
848 | ||
849 | adapter->fw = NULL; | |
850 | goto done; | |
851 | } | |
852 | ||
853 | rc = netxen_validate_firmware(adapter, fw_name[fw_type]); | |
854 | if (rc != 0) { | |
855 | release_firmware(adapter->fw); | |
856 | ||
857 | if (fw_type == NX_P3_CT_ROMIMAGE) { | |
858 | msleep(1); | |
859 | goto request_mn; | |
860 | } | |
861 | ||
862 | adapter->fw = NULL; | |
863 | goto done; | |
864 | } | |
865 | ||
866 | done: | |
867 | if (adapter->fw) | |
868 | dev_info(&pdev->dev, "loading firmware from file %s\n", | |
869 | fw_name[fw_type]); | |
870 | else | |
871 | dev_info(&pdev->dev, "loading firmware from flash\n"); | |
872 | } | |
873 | ||
874 | ||
875 | void | |
876 | netxen_release_firmware(struct netxen_adapter *adapter) | |
877 | { | |
878 | if (adapter->fw) | |
879 | release_firmware(adapter->fw); | |
880 | } | |
881 | ||
ed25ffa1 AK |
882 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter) |
883 | { | |
884 | uint64_t addr; | |
885 | uint32_t hi; | |
886 | uint32_t lo; | |
887 | ||
888 | adapter->dummy_dma.addr = | |
7830b22c | 889 | pci_alloc_consistent(adapter->pdev, |
ed25ffa1 AK |
890 | NETXEN_HOST_DUMMY_DMA_SIZE, |
891 | &adapter->dummy_dma.phys_addr); | |
892 | if (adapter->dummy_dma.addr == NULL) { | |
893 | printk("%s: ERROR: Could not allocate dummy DMA memory\n", | |
2956640d | 894 | __func__); |
ed25ffa1 AK |
895 | return -ENOMEM; |
896 | } | |
897 | ||
898 | addr = (uint64_t) adapter->dummy_dma.phys_addr; | |
899 | hi = (addr >> 32) & 0xffffffff; | |
900 | lo = addr & 0xffffffff; | |
901 | ||
f98a9f69 DP |
902 | NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi); |
903 | NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo); | |
ed25ffa1 | 904 | |
2956640d DP |
905 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
906 | uint32_t temp = 0; | |
f98a9f69 | 907 | NXWR32(adapter, CRB_HOST_DUMMY_BUF, temp); |
2956640d DP |
908 | } |
909 | ||
ed25ffa1 AK |
910 | return 0; |
911 | } | |
912 | ||
913 | void netxen_free_adapter_offload(struct netxen_adapter *adapter) | |
914 | { | |
15eef1e1 DP |
915 | int i = 100; |
916 | ||
917 | if (!adapter->dummy_dma.addr) | |
918 | return; | |
439b454e | 919 | |
15eef1e1 | 920 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
439b454e DP |
921 | do { |
922 | if (dma_watchdog_shutdown_request(adapter) == 1) | |
923 | break; | |
924 | msleep(50); | |
925 | if (dma_watchdog_shutdown_poll_result(adapter) == 1) | |
926 | break; | |
927 | } while (--i); | |
15eef1e1 | 928 | } |
439b454e | 929 | |
15eef1e1 DP |
930 | if (i) { |
931 | pci_free_consistent(adapter->pdev, | |
932 | NETXEN_HOST_DUMMY_DMA_SIZE, | |
933 | adapter->dummy_dma.addr, | |
934 | adapter->dummy_dma.phys_addr); | |
935 | adapter->dummy_dma.addr = NULL; | |
936 | } else { | |
937 | printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n", | |
938 | adapter->netdev->name); | |
ed25ffa1 AK |
939 | } |
940 | } | |
941 | ||
96acb6eb | 942 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val) |
3d396eb1 AK |
943 | { |
944 | u32 val = 0; | |
2956640d | 945 | int retries = 60; |
3d396eb1 | 946 | |
96f2ebd2 DP |
947 | if (pegtune_val) |
948 | return 0; | |
949 | ||
950 | do { | |
951 | val = NXRD32(adapter, CRB_CMDPEG_STATE); | |
96acb6eb | 952 | |
96f2ebd2 DP |
953 | switch (val) { |
954 | case PHAN_INITIALIZE_COMPLETE: | |
955 | case PHAN_INITIALIZE_ACK: | |
956 | return 0; | |
957 | case PHAN_INITIALIZE_FAILED: | |
958 | goto out_err; | |
959 | default: | |
960 | break; | |
961 | } | |
96acb6eb | 962 | |
96f2ebd2 | 963 | msleep(500); |
2956640d | 964 | |
96f2ebd2 | 965 | } while (--retries); |
2956640d | 966 | |
96f2ebd2 | 967 | NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); |
96acb6eb | 968 | |
96f2ebd2 DP |
969 | out_err: |
970 | dev_warn(&adapter->pdev->dev, "firmware init failed\n"); | |
971 | return -EIO; | |
3d396eb1 AK |
972 | } |
973 | ||
56a00787 DP |
974 | static int |
975 | netxen_receive_peg_ready(struct netxen_adapter *adapter) | |
2956640d DP |
976 | { |
977 | u32 val = 0; | |
978 | int retries = 2000; | |
979 | ||
980 | do { | |
f98a9f69 | 981 | val = NXRD32(adapter, CRB_RCVPEG_STATE); |
2956640d DP |
982 | |
983 | if (val == PHAN_PEG_RCV_INITIALIZED) | |
984 | return 0; | |
985 | ||
986 | msleep(10); | |
987 | ||
988 | } while (--retries); | |
989 | ||
990 | if (!retries) { | |
991 | printk(KERN_ERR "Receive Peg initialization not " | |
992 | "complete, state: 0x%x.\n", val); | |
993 | return -EIO; | |
994 | } | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
56a00787 DP |
999 | int netxen_init_firmware(struct netxen_adapter *adapter) |
1000 | { | |
1001 | int err; | |
1002 | ||
1003 | err = netxen_receive_peg_ready(adapter); | |
1004 | if (err) | |
1005 | return err; | |
1006 | ||
f98a9f69 DP |
1007 | NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT); |
1008 | NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC); | |
1009 | NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE); | |
1010 | NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK); | |
56a00787 | 1011 | |
3bf26ce3 | 1012 | if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222)) { |
f98a9f69 | 1013 | adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1); |
3bf26ce3 DP |
1014 | } |
1015 | ||
56a00787 DP |
1016 | return err; |
1017 | } | |
1018 | ||
3bf26ce3 DP |
1019 | static void |
1020 | netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg) | |
1021 | { | |
1022 | u32 cable_OUI; | |
1023 | u16 cable_len; | |
1024 | u16 link_speed; | |
1025 | u8 link_status, module, duplex, autoneg; | |
1026 | struct net_device *netdev = adapter->netdev; | |
1027 | ||
1028 | adapter->has_link_events = 1; | |
1029 | ||
1030 | cable_OUI = msg->body[1] & 0xffffffff; | |
1031 | cable_len = (msg->body[1] >> 32) & 0xffff; | |
1032 | link_speed = (msg->body[1] >> 48) & 0xffff; | |
1033 | ||
1034 | link_status = msg->body[2] & 0xff; | |
1035 | duplex = (msg->body[2] >> 16) & 0xff; | |
1036 | autoneg = (msg->body[2] >> 24) & 0xff; | |
1037 | ||
1038 | module = (msg->body[2] >> 8) & 0xff; | |
1039 | if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) { | |
1040 | printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n", | |
1041 | netdev->name, cable_OUI, cable_len); | |
1042 | } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) { | |
1043 | printk(KERN_INFO "%s: unsupported cable length %d\n", | |
1044 | netdev->name, cable_len); | |
1045 | } | |
1046 | ||
1047 | netxen_advert_link_change(adapter, link_status); | |
1048 | ||
1049 | /* update link parameters */ | |
1050 | if (duplex == LINKEVENT_FULL_DUPLEX) | |
1051 | adapter->link_duplex = DUPLEX_FULL; | |
1052 | else | |
1053 | adapter->link_duplex = DUPLEX_HALF; | |
1054 | adapter->module_type = module; | |
1055 | adapter->link_autoneg = autoneg; | |
1056 | adapter->link_speed = link_speed; | |
1057 | } | |
1058 | ||
1059 | static void | |
1060 | netxen_handle_fw_message(int desc_cnt, int index, | |
1061 | struct nx_host_sds_ring *sds_ring) | |
1062 | { | |
1063 | nx_fw_msg_t msg; | |
1064 | struct status_desc *desc; | |
1065 | int i = 0, opcode; | |
1066 | ||
1067 | while (desc_cnt > 0 && i < 8) { | |
1068 | desc = &sds_ring->desc_head[index]; | |
1069 | msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]); | |
1070 | msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]); | |
1071 | ||
1072 | index = get_next_index(index, sds_ring->num_desc); | |
1073 | desc_cnt--; | |
1074 | } | |
1075 | ||
1076 | opcode = netxen_get_nic_msg_opcode(msg.body[0]); | |
1077 | switch (opcode) { | |
1078 | case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE: | |
1079 | netxen_handle_linkevent(sds_ring->adapter, &msg); | |
1080 | break; | |
1081 | default: | |
1082 | break; | |
1083 | } | |
1084 | } | |
1085 | ||
d8b100c5 DP |
1086 | static int |
1087 | netxen_alloc_rx_skb(struct netxen_adapter *adapter, | |
1088 | struct nx_host_rds_ring *rds_ring, | |
1089 | struct netxen_rx_buffer *buffer) | |
1090 | { | |
1091 | struct sk_buff *skb; | |
1092 | dma_addr_t dma; | |
1093 | struct pci_dev *pdev = adapter->pdev; | |
1094 | ||
1095 | buffer->skb = dev_alloc_skb(rds_ring->skb_size); | |
1096 | if (!buffer->skb) | |
1097 | return 1; | |
1098 | ||
1099 | skb = buffer->skb; | |
1100 | ||
1101 | if (!adapter->ahw.cut_through) | |
1102 | skb_reserve(skb, 2); | |
1103 | ||
1104 | dma = pci_map_single(pdev, skb->data, | |
1105 | rds_ring->dma_size, PCI_DMA_FROMDEVICE); | |
1106 | ||
1107 | if (pci_dma_mapping_error(pdev, dma)) { | |
1108 | dev_kfree_skb_any(skb); | |
1109 | buffer->skb = NULL; | |
1110 | return 1; | |
1111 | } | |
1112 | ||
1113 | buffer->skb = skb; | |
1114 | buffer->dma = dma; | |
1115 | buffer->state = NETXEN_BUFFER_BUSY; | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
d9e651bc DP |
1120 | static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter, |
1121 | struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum) | |
1122 | { | |
1123 | struct netxen_rx_buffer *buffer; | |
1124 | struct sk_buff *skb; | |
1125 | ||
1126 | buffer = &rds_ring->rx_buf_arr[index]; | |
1127 | ||
1128 | pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size, | |
1129 | PCI_DMA_FROMDEVICE); | |
1130 | ||
1131 | skb = buffer->skb; | |
1132 | if (!skb) | |
1133 | goto no_skb; | |
1134 | ||
1135 | if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) { | |
1136 | adapter->stats.csummed++; | |
1137 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1138 | } else | |
1139 | skb->ip_summed = CHECKSUM_NONE; | |
1140 | ||
1141 | skb->dev = adapter->netdev; | |
1142 | ||
1143 | buffer->skb = NULL; | |
d9e651bc DP |
1144 | no_skb: |
1145 | buffer->state = NETXEN_BUFFER_FREE; | |
d9e651bc DP |
1146 | return skb; |
1147 | } | |
1148 | ||
d8b100c5 | 1149 | static struct netxen_rx_buffer * |
9b3ef55c | 1150 | netxen_process_rcv(struct netxen_adapter *adapter, |
a92e9e65 AKS |
1151 | int ring, int index, int length, int cksum, int pkt_offset, |
1152 | struct nx_host_sds_ring *sds_ring) | |
3d396eb1 | 1153 | { |
3176ff3e | 1154 | struct net_device *netdev = adapter->netdev; |
becf46a0 | 1155 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; |
3d396eb1 AK |
1156 | struct netxen_rx_buffer *buffer; |
1157 | struct sk_buff *skb; | |
9b3ef55c | 1158 | struct nx_host_rds_ring *rds_ring = &recv_ctx->rds_rings[ring]; |
3d396eb1 | 1159 | |
438627c7 | 1160 | if (unlikely(index > rds_ring->num_desc)) |
d8b100c5 | 1161 | return NULL; |
438627c7 | 1162 | |
48bfd1e0 | 1163 | buffer = &rds_ring->rx_buf_arr[index]; |
3d396eb1 | 1164 | |
d9e651bc DP |
1165 | skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum); |
1166 | if (!skb) | |
d8b100c5 | 1167 | return buffer; |
200eef20 | 1168 | |
9b3ef55c DP |
1169 | if (length > rds_ring->skb_size) |
1170 | skb_put(skb, rds_ring->skb_size); | |
1171 | else | |
1172 | skb_put(skb, length); | |
d9e651bc | 1173 | |
9b3ef55c DP |
1174 | |
1175 | if (pkt_offset) | |
1176 | skb_pull(skb, pkt_offset); | |
ed25ffa1 | 1177 | |
3d396eb1 AK |
1178 | skb->protocol = eth_type_trans(skb, netdev); |
1179 | ||
a92e9e65 | 1180 | napi_gro_receive(&sds_ring->napi, skb); |
d9e651bc | 1181 | |
0ddc110c DP |
1182 | adapter->stats.no_rcv++; |
1183 | adapter->stats.rxbytes += length; | |
d8b100c5 DP |
1184 | |
1185 | return buffer; | |
3d396eb1 AK |
1186 | } |
1187 | ||
d8b100c5 DP |
1188 | #define netxen_merge_rx_buffers(list, head) \ |
1189 | do { list_splice_tail_init(list, head); } while (0); | |
1190 | ||
becf46a0 | 1191 | int |
d8b100c5 | 1192 | netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max) |
3d396eb1 | 1193 | { |
d8b100c5 DP |
1194 | struct netxen_adapter *adapter = sds_ring->adapter; |
1195 | ||
1196 | struct list_head *cur; | |
1197 | ||
0ddc110c | 1198 | struct status_desc *desc; |
d8b100c5 DP |
1199 | struct netxen_rx_buffer *rxbuf; |
1200 | ||
1201 | u32 consumer = sds_ring->consumer; | |
1202 | ||
9b3ef55c | 1203 | int count = 0; |
d9e651bc | 1204 | u64 sts_data; |
3bf26ce3 | 1205 | int opcode, ring, index, length, cksum, pkt_offset, desc_cnt; |
3d396eb1 | 1206 | |
3d396eb1 | 1207 | while (count < max) { |
d8b100c5 | 1208 | desc = &sds_ring->desc_head[consumer]; |
3bf26ce3 | 1209 | sts_data = le64_to_cpu(desc->status_desc_data[0]); |
0ddc110c DP |
1210 | |
1211 | if (!(sts_data & STATUS_OWNER_HOST)) | |
3d396eb1 | 1212 | break; |
d9e651bc | 1213 | |
3bf26ce3 | 1214 | desc_cnt = netxen_get_sts_desc_cnt(sts_data); |
9b3ef55c | 1215 | ring = netxen_get_sts_type(sts_data); |
3bf26ce3 | 1216 | |
9b3ef55c | 1217 | if (ring > RCV_RING_JUMBO) |
3bf26ce3 | 1218 | goto skip; |
9b3ef55c | 1219 | |
d9e651bc | 1220 | opcode = netxen_get_sts_opcode(sts_data); |
d9e651bc | 1221 | |
3bf26ce3 DP |
1222 | switch (opcode) { |
1223 | case NETXEN_NIC_RXPKT_DESC: | |
1224 | case NETXEN_OLD_RXPKT_DESC: | |
1225 | break; | |
1226 | case NETXEN_NIC_RESPONSE_DESC: | |
1227 | netxen_handle_fw_message(desc_cnt, consumer, sds_ring); | |
1228 | default: | |
1229 | goto skip; | |
1230 | } | |
1231 | ||
1232 | WARN_ON(desc_cnt > 1); | |
1233 | ||
9b3ef55c DP |
1234 | index = netxen_get_sts_refhandle(sts_data); |
1235 | length = netxen_get_sts_totallength(sts_data); | |
1236 | cksum = netxen_get_sts_status(sts_data); | |
1237 | pkt_offset = netxen_get_sts_pkt_offset(sts_data); | |
1238 | ||
d8b100c5 | 1239 | rxbuf = netxen_process_rcv(adapter, ring, index, |
a92e9e65 | 1240 | length, cksum, pkt_offset, sds_ring); |
d9e651bc | 1241 | |
d8b100c5 DP |
1242 | if (rxbuf) |
1243 | list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]); | |
1244 | ||
3bf26ce3 DP |
1245 | skip: |
1246 | for (; desc_cnt > 0; desc_cnt--) { | |
1247 | desc = &sds_ring->desc_head[consumer]; | |
1248 | desc->status_desc_data[0] = | |
1249 | cpu_to_le64(STATUS_OWNER_PHANTOM); | |
1250 | consumer = get_next_index(consumer, sds_ring->num_desc); | |
1251 | } | |
3d396eb1 AK |
1252 | count++; |
1253 | } | |
0ddc110c | 1254 | |
d8b100c5 DP |
1255 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
1256 | struct nx_host_rds_ring *rds_ring = | |
1257 | &adapter->recv_ctx.rds_rings[ring]; | |
1258 | ||
1259 | if (!list_empty(&sds_ring->free_list[ring])) { | |
1260 | list_for_each(cur, &sds_ring->free_list[ring]) { | |
1261 | rxbuf = list_entry(cur, | |
1262 | struct netxen_rx_buffer, list); | |
1263 | netxen_alloc_rx_skb(adapter, rds_ring, rxbuf); | |
1264 | } | |
1265 | spin_lock(&rds_ring->lock); | |
1266 | netxen_merge_rx_buffers(&sds_ring->free_list[ring], | |
1267 | &rds_ring->free_list); | |
1268 | spin_unlock(&rds_ring->lock); | |
1269 | } | |
1270 | ||
1271 | netxen_post_rx_buffers_nodb(adapter, rds_ring); | |
1272 | } | |
3d396eb1 | 1273 | |
3d396eb1 | 1274 | if (count) { |
d8b100c5 | 1275 | sds_ring->consumer = consumer; |
f98a9f69 | 1276 | NXWR32(adapter, sds_ring->crb_sts_consumer, consumer); |
3d396eb1 AK |
1277 | } |
1278 | ||
1279 | return count; | |
1280 | } | |
1281 | ||
1282 | /* Process Command status ring */ | |
05aaa02d | 1283 | int netxen_process_cmd_ring(struct netxen_adapter *adapter) |
3d396eb1 | 1284 | { |
d877f1e3 | 1285 | u32 sw_consumer, hw_consumer; |
ba53e6b4 | 1286 | int count = 0, i; |
3d396eb1 | 1287 | struct netxen_cmd_buffer *buffer; |
ba53e6b4 DP |
1288 | struct pci_dev *pdev = adapter->pdev; |
1289 | struct net_device *netdev = adapter->netdev; | |
3d396eb1 | 1290 | struct netxen_skb_frag *frag; |
ba53e6b4 | 1291 | int done = 0; |
4ea528a1 | 1292 | struct nx_host_tx_ring *tx_ring = adapter->tx_ring; |
3d396eb1 | 1293 | |
d8b100c5 DP |
1294 | if (!spin_trylock(&adapter->tx_clean_lock)) |
1295 | return 1; | |
1296 | ||
d877f1e3 | 1297 | sw_consumer = tx_ring->sw_consumer; |
d877f1e3 | 1298 | hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer)); |
3d396eb1 | 1299 | |
d877f1e3 DP |
1300 | while (sw_consumer != hw_consumer) { |
1301 | buffer = &tx_ring->cmd_buf_arr[sw_consumer]; | |
53a01e00 | 1302 | if (buffer->skb) { |
1303 | frag = &buffer->frag_array[0]; | |
3d396eb1 AK |
1304 | pci_unmap_single(pdev, frag->dma, frag->length, |
1305 | PCI_DMA_TODEVICE); | |
96acb6eb | 1306 | frag->dma = 0ULL; |
3d396eb1 | 1307 | for (i = 1; i < buffer->frag_count; i++) { |
3d396eb1 AK |
1308 | frag++; /* Get the next frag */ |
1309 | pci_unmap_page(pdev, frag->dma, frag->length, | |
1310 | PCI_DMA_TODEVICE); | |
96acb6eb | 1311 | frag->dma = 0ULL; |
3d396eb1 AK |
1312 | } |
1313 | ||
ba53e6b4 | 1314 | adapter->stats.xmitfinished++; |
53a01e00 | 1315 | dev_kfree_skb_any(buffer->skb); |
1316 | buffer->skb = NULL; | |
3d396eb1 AK |
1317 | } |
1318 | ||
d877f1e3 | 1319 | sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc); |
ba53e6b4 DP |
1320 | if (++count >= MAX_STATUS_HANDLE) |
1321 | break; | |
3d396eb1 | 1322 | } |
3d396eb1 | 1323 | |
22527864 | 1324 | if (count && netif_running(netdev)) { |
cb2107be DP |
1325 | tx_ring->sw_consumer = sw_consumer; |
1326 | ||
ba53e6b4 | 1327 | smp_mb(); |
cb2107be | 1328 | |
22527864 | 1329 | if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) { |
ba53e6b4 | 1330 | netif_tx_lock(netdev); |
cb2107be DP |
1331 | if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) |
1332 | netif_wake_queue(netdev); | |
ba53e6b4 | 1333 | netif_tx_unlock(netdev); |
3d396eb1 AK |
1334 | } |
1335 | } | |
ed25ffa1 AK |
1336 | /* |
1337 | * If everything is freed up to consumer then check if the ring is full | |
1338 | * If the ring is full then check if more needs to be freed and | |
1339 | * schedule the call back again. | |
1340 | * | |
1341 | * This happens when there are 2 CPUs. One could be freeing and the | |
1342 | * other filling it. If the ring is full when we get out of here and | |
1343 | * the card has already interrupted the host then the host can miss the | |
1344 | * interrupt. | |
1345 | * | |
1346 | * There is still a possible race condition and the host could miss an | |
1347 | * interrupt. The card has to take care of this. | |
1348 | */ | |
d877f1e3 DP |
1349 | hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer)); |
1350 | done = (sw_consumer == hw_consumer); | |
d8b100c5 | 1351 | spin_unlock(&adapter->tx_clean_lock); |
3d396eb1 | 1352 | |
ed25ffa1 | 1353 | return (done); |
3d396eb1 AK |
1354 | } |
1355 | ||
becf46a0 | 1356 | void |
d8b100c5 DP |
1357 | netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, |
1358 | struct nx_host_rds_ring *rds_ring) | |
3d396eb1 | 1359 | { |
3d396eb1 AK |
1360 | struct rcv_desc *pdesc; |
1361 | struct netxen_rx_buffer *buffer; | |
d8b100c5 | 1362 | int producer, count = 0; |
ed25ffa1 | 1363 | netxen_ctx_msg msg = 0; |
d9e651bc | 1364 | struct list_head *head; |
3d396eb1 | 1365 | |
48bfd1e0 | 1366 | producer = rds_ring->producer; |
d9e651bc | 1367 | |
d8b100c5 DP |
1368 | spin_lock(&rds_ring->lock); |
1369 | head = &rds_ring->free_list; | |
d9e651bc DP |
1370 | while (!list_empty(head)) { |
1371 | ||
d8b100c5 | 1372 | buffer = list_entry(head->next, struct netxen_rx_buffer, list); |
6f703406 | 1373 | |
d8b100c5 DP |
1374 | if (!buffer->skb) { |
1375 | if (netxen_alloc_rx_skb(adapter, rds_ring, buffer)) | |
1376 | break; | |
6f703406 DP |
1377 | } |
1378 | ||
1379 | count++; | |
d9e651bc DP |
1380 | list_del(&buffer->list); |
1381 | ||
ed25ffa1 | 1382 | /* make a rcv descriptor */ |
6f703406 | 1383 | pdesc = &rds_ring->desc_head[producer]; |
d8b100c5 | 1384 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
ed33ebe4 | 1385 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
48bfd1e0 | 1386 | pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); |
6f703406 | 1387 | |
438627c7 | 1388 | producer = get_next_index(producer, rds_ring->num_desc); |
ed25ffa1 | 1389 | } |
d8b100c5 | 1390 | spin_unlock(&rds_ring->lock); |
9b3ef55c | 1391 | |
ed25ffa1 | 1392 | if (count) { |
48bfd1e0 | 1393 | rds_ring->producer = producer; |
f98a9f69 | 1394 | NXWR32(adapter, rds_ring->crb_rcv_producer, |
438627c7 | 1395 | (producer-1) & (rds_ring->num_desc-1)); |
48bfd1e0 DP |
1396 | |
1397 | if (adapter->fw_major < 4) { | |
ed25ffa1 AK |
1398 | /* |
1399 | * Write a doorbell msg to tell phanmon of change in | |
1400 | * receive ring producer | |
48bfd1e0 | 1401 | * Only for firmware version < 4.0.0 |
ed25ffa1 AK |
1402 | */ |
1403 | netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID); | |
1404 | netxen_set_msg_privid(msg); | |
1405 | netxen_set_msg_count(msg, | |
438627c7 DP |
1406 | ((producer - 1) & |
1407 | (rds_ring->num_desc - 1))); | |
3176ff3e | 1408 | netxen_set_msg_ctxid(msg, adapter->portnum); |
ed25ffa1 AK |
1409 | netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid)); |
1410 | writel(msg, | |
1411 | DB_NORMALIZE(adapter, | |
1412 | NETXEN_RCV_PRODUCER_OFFSET)); | |
48bfd1e0 | 1413 | } |
ed25ffa1 AK |
1414 | } |
1415 | } | |
1416 | ||
becf46a0 | 1417 | static void |
d8b100c5 DP |
1418 | netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
1419 | struct nx_host_rds_ring *rds_ring) | |
ed25ffa1 | 1420 | { |
ed25ffa1 AK |
1421 | struct rcv_desc *pdesc; |
1422 | struct netxen_rx_buffer *buffer; | |
d8b100c5 | 1423 | int producer, count = 0; |
d9e651bc | 1424 | struct list_head *head; |
ed25ffa1 | 1425 | |
48bfd1e0 | 1426 | producer = rds_ring->producer; |
d8b100c5 DP |
1427 | if (!spin_trylock(&rds_ring->lock)) |
1428 | return; | |
1429 | ||
d9e651bc | 1430 | head = &rds_ring->free_list; |
d9e651bc DP |
1431 | while (!list_empty(head)) { |
1432 | ||
d8b100c5 | 1433 | buffer = list_entry(head->next, struct netxen_rx_buffer, list); |
6f703406 | 1434 | |
d8b100c5 DP |
1435 | if (!buffer->skb) { |
1436 | if (netxen_alloc_rx_skb(adapter, rds_ring, buffer)) | |
1437 | break; | |
6f703406 DP |
1438 | } |
1439 | ||
1440 | count++; | |
d9e651bc DP |
1441 | list_del(&buffer->list); |
1442 | ||
3d396eb1 | 1443 | /* make a rcv descriptor */ |
6f703406 | 1444 | pdesc = &rds_ring->desc_head[producer]; |
ed33ebe4 | 1445 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
48bfd1e0 | 1446 | pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); |
3d396eb1 | 1447 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
6f703406 | 1448 | |
438627c7 | 1449 | producer = get_next_index(producer, rds_ring->num_desc); |
3d396eb1 AK |
1450 | } |
1451 | ||
3d396eb1 | 1452 | if (count) { |
48bfd1e0 | 1453 | rds_ring->producer = producer; |
f98a9f69 | 1454 | NXWR32(adapter, rds_ring->crb_rcv_producer, |
438627c7 | 1455 | (producer - 1) & (rds_ring->num_desc - 1)); |
3d396eb1 | 1456 | } |
d8b100c5 | 1457 | spin_unlock(&rds_ring->lock); |
3d396eb1 AK |
1458 | } |
1459 | ||
3d396eb1 AK |
1460 | void netxen_nic_clear_stats(struct netxen_adapter *adapter) |
1461 | { | |
3d396eb1 | 1462 | memset(&adapter->stats, 0, sizeof(adapter->stats)); |
3176ff3e | 1463 | return; |
3d396eb1 AK |
1464 | } |
1465 |