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a3138df9 DM |
1 | /* niu.c: Neptune ethernet driver. |
2 | * | |
3 | * Copyright (C) 2007 David S. Miller (davem@davemloft.net) | |
4 | */ | |
5 | ||
6 | #include <linux/module.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/dma-mapping.h> | |
10 | #include <linux/netdevice.h> | |
11 | #include <linux/ethtool.h> | |
12 | #include <linux/etherdevice.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/mii.h> | |
17 | #include <linux/if_ether.h> | |
18 | #include <linux/if_vlan.h> | |
19 | #include <linux/ip.h> | |
20 | #include <linux/in.h> | |
21 | #include <linux/ipv6.h> | |
22 | #include <linux/log2.h> | |
23 | #include <linux/jiffies.h> | |
24 | #include <linux/crc32.h> | |
25 | ||
26 | #include <linux/io.h> | |
27 | ||
28 | #ifdef CONFIG_SPARC64 | |
29 | #include <linux/of_device.h> | |
30 | #endif | |
31 | ||
32 | #include "niu.h" | |
33 | ||
34 | #define DRV_MODULE_NAME "niu" | |
35 | #define PFX DRV_MODULE_NAME ": " | |
a5d6ab56 MW |
36 | #define DRV_MODULE_VERSION "0.8" |
37 | #define DRV_MODULE_RELDATE "April 24, 2008" | |
a3138df9 DM |
38 | |
39 | static char version[] __devinitdata = | |
40 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | |
41 | ||
42 | MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); | |
43 | MODULE_DESCRIPTION("NIU ethernet driver"); | |
44 | MODULE_LICENSE("GPL"); | |
45 | MODULE_VERSION(DRV_MODULE_VERSION); | |
46 | ||
47 | #ifndef DMA_44BIT_MASK | |
48 | #define DMA_44BIT_MASK 0x00000fffffffffffULL | |
49 | #endif | |
50 | ||
51 | #ifndef readq | |
52 | static u64 readq(void __iomem *reg) | |
53 | { | |
54 | return (((u64)readl(reg + 0x4UL) << 32) | | |
55 | (u64)readl(reg)); | |
56 | } | |
57 | ||
58 | static void writeq(u64 val, void __iomem *reg) | |
59 | { | |
60 | writel(val & 0xffffffff, reg); | |
61 | writel(val >> 32, reg + 0x4UL); | |
62 | } | |
63 | #endif | |
64 | ||
65 | static struct pci_device_id niu_pci_tbl[] = { | |
66 | {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)}, | |
67 | {} | |
68 | }; | |
69 | ||
70 | MODULE_DEVICE_TABLE(pci, niu_pci_tbl); | |
71 | ||
72 | #define NIU_TX_TIMEOUT (5 * HZ) | |
73 | ||
74 | #define nr64(reg) readq(np->regs + (reg)) | |
75 | #define nw64(reg, val) writeq((val), np->regs + (reg)) | |
76 | ||
77 | #define nr64_mac(reg) readq(np->mac_regs + (reg)) | |
78 | #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg)) | |
79 | ||
80 | #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg)) | |
81 | #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg)) | |
82 | ||
83 | #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg)) | |
84 | #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg)) | |
85 | ||
86 | #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg)) | |
87 | #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg)) | |
88 | ||
89 | #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) | |
90 | ||
91 | static int niu_debug; | |
92 | static int debug = -1; | |
93 | module_param(debug, int, 0); | |
94 | MODULE_PARM_DESC(debug, "NIU debug level"); | |
95 | ||
96 | #define niudbg(TYPE, f, a...) \ | |
97 | do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \ | |
98 | printk(KERN_DEBUG PFX f, ## a); \ | |
99 | } while (0) | |
100 | ||
101 | #define niuinfo(TYPE, f, a...) \ | |
102 | do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \ | |
103 | printk(KERN_INFO PFX f, ## a); \ | |
104 | } while (0) | |
105 | ||
106 | #define niuwarn(TYPE, f, a...) \ | |
107 | do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \ | |
108 | printk(KERN_WARNING PFX f, ## a); \ | |
109 | } while (0) | |
110 | ||
111 | #define niu_lock_parent(np, flags) \ | |
112 | spin_lock_irqsave(&np->parent->lock, flags) | |
113 | #define niu_unlock_parent(np, flags) \ | |
114 | spin_unlock_irqrestore(&np->parent->lock, flags) | |
115 | ||
5fbd7e24 MW |
116 | static int serdes_init_10g_serdes(struct niu *np); |
117 | ||
a3138df9 DM |
118 | static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg, |
119 | u64 bits, int limit, int delay) | |
120 | { | |
121 | while (--limit >= 0) { | |
122 | u64 val = nr64_mac(reg); | |
123 | ||
124 | if (!(val & bits)) | |
125 | break; | |
126 | udelay(delay); | |
127 | } | |
128 | if (limit < 0) | |
129 | return -ENODEV; | |
130 | return 0; | |
131 | } | |
132 | ||
133 | static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg, | |
134 | u64 bits, int limit, int delay, | |
135 | const char *reg_name) | |
136 | { | |
137 | int err; | |
138 | ||
139 | nw64_mac(reg, bits); | |
140 | err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay); | |
141 | if (err) | |
142 | dev_err(np->device, PFX "%s: bits (%llx) of register %s " | |
143 | "would not clear, val[%llx]\n", | |
144 | np->dev->name, (unsigned long long) bits, reg_name, | |
145 | (unsigned long long) nr64_mac(reg)); | |
146 | return err; | |
147 | } | |
148 | ||
149 | #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ | |
150 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ | |
151 | __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ | |
152 | }) | |
153 | ||
154 | static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg, | |
155 | u64 bits, int limit, int delay) | |
156 | { | |
157 | while (--limit >= 0) { | |
158 | u64 val = nr64_ipp(reg); | |
159 | ||
160 | if (!(val & bits)) | |
161 | break; | |
162 | udelay(delay); | |
163 | } | |
164 | if (limit < 0) | |
165 | return -ENODEV; | |
166 | return 0; | |
167 | } | |
168 | ||
169 | static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg, | |
170 | u64 bits, int limit, int delay, | |
171 | const char *reg_name) | |
172 | { | |
173 | int err; | |
174 | u64 val; | |
175 | ||
176 | val = nr64_ipp(reg); | |
177 | val |= bits; | |
178 | nw64_ipp(reg, val); | |
179 | ||
180 | err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay); | |
181 | if (err) | |
182 | dev_err(np->device, PFX "%s: bits (%llx) of register %s " | |
183 | "would not clear, val[%llx]\n", | |
184 | np->dev->name, (unsigned long long) bits, reg_name, | |
185 | (unsigned long long) nr64_ipp(reg)); | |
186 | return err; | |
187 | } | |
188 | ||
189 | #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ | |
190 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ | |
191 | __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ | |
192 | }) | |
193 | ||
194 | static int __niu_wait_bits_clear(struct niu *np, unsigned long reg, | |
195 | u64 bits, int limit, int delay) | |
196 | { | |
197 | while (--limit >= 0) { | |
198 | u64 val = nr64(reg); | |
199 | ||
200 | if (!(val & bits)) | |
201 | break; | |
202 | udelay(delay); | |
203 | } | |
204 | if (limit < 0) | |
205 | return -ENODEV; | |
206 | return 0; | |
207 | } | |
208 | ||
209 | #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ | |
210 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ | |
211 | __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \ | |
212 | }) | |
213 | ||
214 | static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg, | |
215 | u64 bits, int limit, int delay, | |
216 | const char *reg_name) | |
217 | { | |
218 | int err; | |
219 | ||
220 | nw64(reg, bits); | |
221 | err = __niu_wait_bits_clear(np, reg, bits, limit, delay); | |
222 | if (err) | |
223 | dev_err(np->device, PFX "%s: bits (%llx) of register %s " | |
224 | "would not clear, val[%llx]\n", | |
225 | np->dev->name, (unsigned long long) bits, reg_name, | |
226 | (unsigned long long) nr64(reg)); | |
227 | return err; | |
228 | } | |
229 | ||
230 | #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ | |
231 | ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ | |
232 | __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ | |
233 | }) | |
234 | ||
235 | static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on) | |
236 | { | |
237 | u64 val = (u64) lp->timer; | |
238 | ||
239 | if (on) | |
240 | val |= LDG_IMGMT_ARM; | |
241 | ||
242 | nw64(LDG_IMGMT(lp->ldg_num), val); | |
243 | } | |
244 | ||
245 | static int niu_ldn_irq_enable(struct niu *np, int ldn, int on) | |
246 | { | |
247 | unsigned long mask_reg, bits; | |
248 | u64 val; | |
249 | ||
250 | if (ldn < 0 || ldn > LDN_MAX) | |
251 | return -EINVAL; | |
252 | ||
253 | if (ldn < 64) { | |
254 | mask_reg = LD_IM0(ldn); | |
255 | bits = LD_IM0_MASK; | |
256 | } else { | |
257 | mask_reg = LD_IM1(ldn - 64); | |
258 | bits = LD_IM1_MASK; | |
259 | } | |
260 | ||
261 | val = nr64(mask_reg); | |
262 | if (on) | |
263 | val &= ~bits; | |
264 | else | |
265 | val |= bits; | |
266 | nw64(mask_reg, val); | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on) | |
272 | { | |
273 | struct niu_parent *parent = np->parent; | |
274 | int i; | |
275 | ||
276 | for (i = 0; i <= LDN_MAX; i++) { | |
277 | int err; | |
278 | ||
279 | if (parent->ldg_map[i] != lp->ldg_num) | |
280 | continue; | |
281 | ||
282 | err = niu_ldn_irq_enable(np, i, on); | |
283 | if (err) | |
284 | return err; | |
285 | } | |
286 | return 0; | |
287 | } | |
288 | ||
289 | static int niu_enable_interrupts(struct niu *np, int on) | |
290 | { | |
291 | int i; | |
292 | ||
293 | for (i = 0; i < np->num_ldg; i++) { | |
294 | struct niu_ldg *lp = &np->ldg[i]; | |
295 | int err; | |
296 | ||
297 | err = niu_enable_ldn_in_ldg(np, lp, on); | |
298 | if (err) | |
299 | return err; | |
300 | } | |
301 | for (i = 0; i < np->num_ldg; i++) | |
302 | niu_ldg_rearm(np, &np->ldg[i], on); | |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
307 | static u32 phy_encode(u32 type, int port) | |
308 | { | |
309 | return (type << (port * 2)); | |
310 | } | |
311 | ||
312 | static u32 phy_decode(u32 val, int port) | |
313 | { | |
314 | return (val >> (port * 2)) & PORT_TYPE_MASK; | |
315 | } | |
316 | ||
317 | static int mdio_wait(struct niu *np) | |
318 | { | |
319 | int limit = 1000; | |
320 | u64 val; | |
321 | ||
322 | while (--limit > 0) { | |
323 | val = nr64(MIF_FRAME_OUTPUT); | |
324 | if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1) | |
325 | return val & MIF_FRAME_OUTPUT_DATA; | |
326 | ||
327 | udelay(10); | |
328 | } | |
329 | ||
330 | return -ENODEV; | |
331 | } | |
332 | ||
333 | static int mdio_read(struct niu *np, int port, int dev, int reg) | |
334 | { | |
335 | int err; | |
336 | ||
337 | nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); | |
338 | err = mdio_wait(np); | |
339 | if (err < 0) | |
340 | return err; | |
341 | ||
342 | nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev)); | |
343 | return mdio_wait(np); | |
344 | } | |
345 | ||
346 | static int mdio_write(struct niu *np, int port, int dev, int reg, int data) | |
347 | { | |
348 | int err; | |
349 | ||
350 | nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); | |
351 | err = mdio_wait(np); | |
352 | if (err < 0) | |
353 | return err; | |
354 | ||
355 | nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data)); | |
356 | err = mdio_wait(np); | |
357 | if (err < 0) | |
358 | return err; | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | static int mii_read(struct niu *np, int port, int reg) | |
364 | { | |
365 | nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg)); | |
366 | return mdio_wait(np); | |
367 | } | |
368 | ||
369 | static int mii_write(struct niu *np, int port, int reg, int data) | |
370 | { | |
371 | int err; | |
372 | ||
373 | nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data)); | |
374 | err = mdio_wait(np); | |
375 | if (err < 0) | |
376 | return err; | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val) | |
382 | { | |
383 | int err; | |
384 | ||
385 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, | |
386 | ESR2_TI_PLL_TX_CFG_L(channel), | |
387 | val & 0xffff); | |
388 | if (!err) | |
389 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, | |
390 | ESR2_TI_PLL_TX_CFG_H(channel), | |
391 | val >> 16); | |
392 | return err; | |
393 | } | |
394 | ||
395 | static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val) | |
396 | { | |
397 | int err; | |
398 | ||
399 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, | |
400 | ESR2_TI_PLL_RX_CFG_L(channel), | |
401 | val & 0xffff); | |
402 | if (!err) | |
403 | err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, | |
404 | ESR2_TI_PLL_RX_CFG_H(channel), | |
405 | val >> 16); | |
406 | return err; | |
407 | } | |
408 | ||
409 | /* Mode is always 10G fiber. */ | |
410 | static int serdes_init_niu(struct niu *np) | |
411 | { | |
412 | struct niu_link_config *lp = &np->link_config; | |
413 | u32 tx_cfg, rx_cfg; | |
414 | unsigned long i; | |
415 | ||
416 | tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); | |
417 | rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | | |
418 | PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | | |
419 | PLL_RX_CFG_EQ_LP_ADAPTIVE); | |
420 | ||
421 | if (lp->loopback_mode == LOOPBACK_PHY) { | |
422 | u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; | |
423 | ||
424 | mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, | |
425 | ESR2_TI_PLL_TEST_CFG_L, test_cfg); | |
426 | ||
427 | tx_cfg |= PLL_TX_CFG_ENTEST; | |
428 | rx_cfg |= PLL_RX_CFG_ENTEST; | |
429 | } | |
430 | ||
431 | /* Initialize all 4 lanes of the SERDES. */ | |
432 | for (i = 0; i < 4; i++) { | |
433 | int err = esr2_set_tx_cfg(np, i, tx_cfg); | |
434 | if (err) | |
435 | return err; | |
436 | } | |
437 | ||
438 | for (i = 0; i < 4; i++) { | |
439 | int err = esr2_set_rx_cfg(np, i, rx_cfg); | |
440 | if (err) | |
441 | return err; | |
442 | } | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val) | |
448 | { | |
449 | int err; | |
450 | ||
451 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan)); | |
452 | if (err >= 0) { | |
453 | *val = (err & 0xffff); | |
454 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, | |
455 | ESR_RXTX_CTRL_H(chan)); | |
456 | if (err >= 0) | |
457 | *val |= ((err & 0xffff) << 16); | |
458 | err = 0; | |
459 | } | |
460 | return err; | |
461 | } | |
462 | ||
463 | static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val) | |
464 | { | |
465 | int err; | |
466 | ||
467 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, | |
468 | ESR_GLUE_CTRL0_L(chan)); | |
469 | if (err >= 0) { | |
470 | *val = (err & 0xffff); | |
471 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, | |
472 | ESR_GLUE_CTRL0_H(chan)); | |
473 | if (err >= 0) { | |
474 | *val |= ((err & 0xffff) << 16); | |
475 | err = 0; | |
476 | } | |
477 | } | |
478 | return err; | |
479 | } | |
480 | ||
481 | static int esr_read_reset(struct niu *np, u32 *val) | |
482 | { | |
483 | int err; | |
484 | ||
485 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, | |
486 | ESR_RXTX_RESET_CTRL_L); | |
487 | if (err >= 0) { | |
488 | *val = (err & 0xffff); | |
489 | err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, | |
490 | ESR_RXTX_RESET_CTRL_H); | |
491 | if (err >= 0) { | |
492 | *val |= ((err & 0xffff) << 16); | |
493 | err = 0; | |
494 | } | |
495 | } | |
496 | return err; | |
497 | } | |
498 | ||
499 | static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val) | |
500 | { | |
501 | int err; | |
502 | ||
503 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
504 | ESR_RXTX_CTRL_L(chan), val & 0xffff); | |
505 | if (!err) | |
506 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
507 | ESR_RXTX_CTRL_H(chan), (val >> 16)); | |
508 | return err; | |
509 | } | |
510 | ||
511 | static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) | |
512 | { | |
513 | int err; | |
514 | ||
515 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
516 | ESR_GLUE_CTRL0_L(chan), val & 0xffff); | |
517 | if (!err) | |
518 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
519 | ESR_GLUE_CTRL0_H(chan), (val >> 16)); | |
520 | return err; | |
521 | } | |
522 | ||
523 | static int esr_reset(struct niu *np) | |
524 | { | |
525 | u32 reset; | |
526 | int err; | |
527 | ||
528 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
529 | ESR_RXTX_RESET_CTRL_L, 0x0000); | |
530 | if (err) | |
531 | return err; | |
532 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
533 | ESR_RXTX_RESET_CTRL_H, 0xffff); | |
534 | if (err) | |
535 | return err; | |
536 | udelay(200); | |
537 | ||
538 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
539 | ESR_RXTX_RESET_CTRL_L, 0xffff); | |
540 | if (err) | |
541 | return err; | |
542 | udelay(200); | |
543 | ||
544 | err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, | |
545 | ESR_RXTX_RESET_CTRL_H, 0x0000); | |
546 | if (err) | |
547 | return err; | |
548 | udelay(200); | |
549 | ||
550 | err = esr_read_reset(np, &reset); | |
551 | if (err) | |
552 | return err; | |
553 | if (reset != 0) { | |
554 | dev_err(np->device, PFX "Port %u ESR_RESET " | |
555 | "did not clear [%08x]\n", | |
556 | np->port, reset); | |
557 | return -ENODEV; | |
558 | } | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
563 | static int serdes_init_10g(struct niu *np) | |
564 | { | |
565 | struct niu_link_config *lp = &np->link_config; | |
566 | unsigned long ctrl_reg, test_cfg_reg, i; | |
567 | u64 ctrl_val, test_cfg_val, sig, mask, val; | |
568 | int err; | |
569 | ||
570 | switch (np->port) { | |
571 | case 0: | |
572 | ctrl_reg = ENET_SERDES_0_CTRL_CFG; | |
573 | test_cfg_reg = ENET_SERDES_0_TEST_CFG; | |
574 | break; | |
575 | case 1: | |
576 | ctrl_reg = ENET_SERDES_1_CTRL_CFG; | |
577 | test_cfg_reg = ENET_SERDES_1_TEST_CFG; | |
578 | break; | |
579 | ||
580 | default: | |
581 | return -EINVAL; | |
582 | } | |
583 | ctrl_val = (ENET_SERDES_CTRL_SDET_0 | | |
584 | ENET_SERDES_CTRL_SDET_1 | | |
585 | ENET_SERDES_CTRL_SDET_2 | | |
586 | ENET_SERDES_CTRL_SDET_3 | | |
587 | (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | | |
588 | (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | | |
589 | (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | | |
590 | (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | | |
591 | (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | | |
592 | (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | | |
593 | (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | | |
594 | (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); | |
595 | test_cfg_val = 0; | |
596 | ||
597 | if (lp->loopback_mode == LOOPBACK_PHY) { | |
598 | test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << | |
599 | ENET_SERDES_TEST_MD_0_SHIFT) | | |
600 | (ENET_TEST_MD_PAD_LOOPBACK << | |
601 | ENET_SERDES_TEST_MD_1_SHIFT) | | |
602 | (ENET_TEST_MD_PAD_LOOPBACK << | |
603 | ENET_SERDES_TEST_MD_2_SHIFT) | | |
604 | (ENET_TEST_MD_PAD_LOOPBACK << | |
605 | ENET_SERDES_TEST_MD_3_SHIFT)); | |
606 | } | |
607 | ||
608 | nw64(ctrl_reg, ctrl_val); | |
609 | nw64(test_cfg_reg, test_cfg_val); | |
610 | ||
611 | /* Initialize all 4 lanes of the SERDES. */ | |
612 | for (i = 0; i < 4; i++) { | |
613 | u32 rxtx_ctrl, glue0; | |
614 | ||
615 | err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); | |
616 | if (err) | |
617 | return err; | |
618 | err = esr_read_glue0(np, i, &glue0); | |
619 | if (err) | |
620 | return err; | |
621 | ||
622 | rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); | |
623 | rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | | |
624 | (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); | |
625 | ||
626 | glue0 &= ~(ESR_GLUE_CTRL0_SRATE | | |
627 | ESR_GLUE_CTRL0_THCNT | | |
628 | ESR_GLUE_CTRL0_BLTIME); | |
629 | glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | | |
630 | (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | | |
631 | (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | | |
632 | (BLTIME_300_CYCLES << | |
633 | ESR_GLUE_CTRL0_BLTIME_SHIFT)); | |
634 | ||
635 | err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); | |
636 | if (err) | |
637 | return err; | |
638 | err = esr_write_glue0(np, i, glue0); | |
639 | if (err) | |
640 | return err; | |
641 | } | |
642 | ||
643 | err = esr_reset(np); | |
644 | if (err) | |
645 | return err; | |
646 | ||
647 | sig = nr64(ESR_INT_SIGNALS); | |
648 | switch (np->port) { | |
649 | case 0: | |
650 | mask = ESR_INT_SIGNALS_P0_BITS; | |
651 | val = (ESR_INT_SRDY0_P0 | | |
652 | ESR_INT_DET0_P0 | | |
653 | ESR_INT_XSRDY_P0 | | |
654 | ESR_INT_XDP_P0_CH3 | | |
655 | ESR_INT_XDP_P0_CH2 | | |
656 | ESR_INT_XDP_P0_CH1 | | |
657 | ESR_INT_XDP_P0_CH0); | |
658 | break; | |
659 | ||
660 | case 1: | |
661 | mask = ESR_INT_SIGNALS_P1_BITS; | |
662 | val = (ESR_INT_SRDY0_P1 | | |
663 | ESR_INT_DET0_P1 | | |
664 | ESR_INT_XSRDY_P1 | | |
665 | ESR_INT_XDP_P1_CH3 | | |
666 | ESR_INT_XDP_P1_CH2 | | |
667 | ESR_INT_XDP_P1_CH1 | | |
668 | ESR_INT_XDP_P1_CH0); | |
669 | break; | |
670 | ||
671 | default: | |
672 | return -EINVAL; | |
673 | } | |
674 | ||
675 | if ((sig & mask) != val) { | |
a5d6ab56 MW |
676 | if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { |
677 | np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; | |
678 | return 0; | |
679 | } | |
a3138df9 DM |
680 | dev_err(np->device, PFX "Port %u signal bits [%08x] are not " |
681 | "[%08x]\n", np->port, (int) (sig & mask), (int) val); | |
682 | return -ENODEV; | |
683 | } | |
a5d6ab56 MW |
684 | if (np->flags & NIU_FLAGS_HOTPLUG_PHY) |
685 | np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; | |
a3138df9 DM |
686 | return 0; |
687 | } | |
688 | ||
689 | static int serdes_init_1g(struct niu *np) | |
690 | { | |
691 | u64 val; | |
692 | ||
693 | val = nr64(ENET_SERDES_1_PLL_CFG); | |
694 | val &= ~ENET_SERDES_PLL_FBDIV2; | |
695 | switch (np->port) { | |
696 | case 0: | |
697 | val |= ENET_SERDES_PLL_HRATE0; | |
698 | break; | |
699 | case 1: | |
700 | val |= ENET_SERDES_PLL_HRATE1; | |
701 | break; | |
702 | case 2: | |
703 | val |= ENET_SERDES_PLL_HRATE2; | |
704 | break; | |
705 | case 3: | |
706 | val |= ENET_SERDES_PLL_HRATE3; | |
707 | break; | |
708 | default: | |
709 | return -EINVAL; | |
710 | } | |
711 | nw64(ENET_SERDES_1_PLL_CFG, val); | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
5fbd7e24 MW |
716 | static int serdes_init_1g_serdes(struct niu *np) |
717 | { | |
718 | struct niu_link_config *lp = &np->link_config; | |
719 | unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; | |
720 | u64 ctrl_val, test_cfg_val, sig, mask, val; | |
721 | int err; | |
722 | u64 reset_val, val_rd; | |
723 | ||
724 | val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 | | |
725 | ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 | | |
726 | ENET_SERDES_PLL_FBDIV0; | |
727 | switch (np->port) { | |
728 | case 0: | |
729 | reset_val = ENET_SERDES_RESET_0; | |
730 | ctrl_reg = ENET_SERDES_0_CTRL_CFG; | |
731 | test_cfg_reg = ENET_SERDES_0_TEST_CFG; | |
732 | pll_cfg = ENET_SERDES_0_PLL_CFG; | |
733 | break; | |
734 | case 1: | |
735 | reset_val = ENET_SERDES_RESET_1; | |
736 | ctrl_reg = ENET_SERDES_1_CTRL_CFG; | |
737 | test_cfg_reg = ENET_SERDES_1_TEST_CFG; | |
738 | pll_cfg = ENET_SERDES_1_PLL_CFG; | |
739 | break; | |
740 | ||
741 | default: | |
742 | return -EINVAL; | |
743 | } | |
744 | ctrl_val = (ENET_SERDES_CTRL_SDET_0 | | |
745 | ENET_SERDES_CTRL_SDET_1 | | |
746 | ENET_SERDES_CTRL_SDET_2 | | |
747 | ENET_SERDES_CTRL_SDET_3 | | |
748 | (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | | |
749 | (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | | |
750 | (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | | |
751 | (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | | |
752 | (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | | |
753 | (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | | |
754 | (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | | |
755 | (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); | |
756 | test_cfg_val = 0; | |
757 | ||
758 | if (lp->loopback_mode == LOOPBACK_PHY) { | |
759 | test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << | |
760 | ENET_SERDES_TEST_MD_0_SHIFT) | | |
761 | (ENET_TEST_MD_PAD_LOOPBACK << | |
762 | ENET_SERDES_TEST_MD_1_SHIFT) | | |
763 | (ENET_TEST_MD_PAD_LOOPBACK << | |
764 | ENET_SERDES_TEST_MD_2_SHIFT) | | |
765 | (ENET_TEST_MD_PAD_LOOPBACK << | |
766 | ENET_SERDES_TEST_MD_3_SHIFT)); | |
767 | } | |
768 | ||
769 | nw64(ENET_SERDES_RESET, reset_val); | |
770 | mdelay(20); | |
771 | val_rd = nr64(ENET_SERDES_RESET); | |
772 | val_rd &= ~reset_val; | |
773 | nw64(pll_cfg, val); | |
774 | nw64(ctrl_reg, ctrl_val); | |
775 | nw64(test_cfg_reg, test_cfg_val); | |
776 | nw64(ENET_SERDES_RESET, val_rd); | |
777 | mdelay(2000); | |
778 | ||
779 | /* Initialize all 4 lanes of the SERDES. */ | |
780 | for (i = 0; i < 4; i++) { | |
781 | u32 rxtx_ctrl, glue0; | |
782 | ||
783 | err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); | |
784 | if (err) | |
785 | return err; | |
786 | err = esr_read_glue0(np, i, &glue0); | |
787 | if (err) | |
788 | return err; | |
789 | ||
790 | rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); | |
791 | rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | | |
792 | (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); | |
793 | ||
794 | glue0 &= ~(ESR_GLUE_CTRL0_SRATE | | |
795 | ESR_GLUE_CTRL0_THCNT | | |
796 | ESR_GLUE_CTRL0_BLTIME); | |
797 | glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | | |
798 | (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | | |
799 | (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | | |
800 | (BLTIME_300_CYCLES << | |
801 | ESR_GLUE_CTRL0_BLTIME_SHIFT)); | |
802 | ||
803 | err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); | |
804 | if (err) | |
805 | return err; | |
806 | err = esr_write_glue0(np, i, glue0); | |
807 | if (err) | |
808 | return err; | |
809 | } | |
810 | ||
811 | ||
812 | sig = nr64(ESR_INT_SIGNALS); | |
813 | switch (np->port) { | |
814 | case 0: | |
815 | val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); | |
816 | mask = val; | |
817 | break; | |
818 | ||
819 | case 1: | |
820 | val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); | |
821 | mask = val; | |
822 | break; | |
823 | ||
824 | default: | |
825 | return -EINVAL; | |
826 | } | |
827 | ||
828 | if ((sig & mask) != val) { | |
829 | dev_err(np->device, PFX "Port %u signal bits [%08x] are not " | |
830 | "[%08x]\n", np->port, (int) (sig & mask), (int) val); | |
831 | return -ENODEV; | |
832 | } | |
833 | ||
834 | return 0; | |
835 | } | |
836 | ||
837 | static int link_status_1g_serdes(struct niu *np, int *link_up_p) | |
838 | { | |
839 | struct niu_link_config *lp = &np->link_config; | |
840 | int link_up; | |
841 | u64 val; | |
842 | u16 current_speed; | |
843 | unsigned long flags; | |
844 | u8 current_duplex; | |
845 | ||
846 | link_up = 0; | |
847 | current_speed = SPEED_INVALID; | |
848 | current_duplex = DUPLEX_INVALID; | |
849 | ||
850 | spin_lock_irqsave(&np->lock, flags); | |
851 | ||
852 | val = nr64_pcs(PCS_MII_STAT); | |
853 | ||
854 | if (val & PCS_MII_STAT_LINK_STATUS) { | |
855 | link_up = 1; | |
856 | current_speed = SPEED_1000; | |
857 | current_duplex = DUPLEX_FULL; | |
858 | } | |
859 | ||
860 | lp->active_speed = current_speed; | |
861 | lp->active_duplex = current_duplex; | |
862 | spin_unlock_irqrestore(&np->lock, flags); | |
863 | ||
864 | *link_up_p = link_up; | |
865 | return 0; | |
866 | } | |
867 | ||
868 | ||
869 | static int link_status_10g_serdes(struct niu *np, int *link_up_p) | |
870 | { | |
871 | unsigned long flags; | |
872 | struct niu_link_config *lp = &np->link_config; | |
873 | int link_up = 0; | |
874 | int link_ok = 1; | |
875 | u64 val, val2; | |
876 | u16 current_speed; | |
877 | u8 current_duplex; | |
878 | ||
879 | if (!(np->flags & NIU_FLAGS_10G)) | |
880 | return link_status_1g_serdes(np, link_up_p); | |
881 | ||
882 | current_speed = SPEED_INVALID; | |
883 | current_duplex = DUPLEX_INVALID; | |
884 | spin_lock_irqsave(&np->lock, flags); | |
885 | ||
886 | val = nr64_xpcs(XPCS_STATUS(0)); | |
887 | val2 = nr64_mac(XMAC_INTER2); | |
888 | if (val2 & 0x01000000) | |
889 | link_ok = 0; | |
890 | ||
891 | if ((val & 0x1000ULL) && link_ok) { | |
892 | link_up = 1; | |
893 | current_speed = SPEED_10000; | |
894 | current_duplex = DUPLEX_FULL; | |
895 | } | |
896 | lp->active_speed = current_speed; | |
897 | lp->active_duplex = current_duplex; | |
898 | spin_unlock_irqrestore(&np->lock, flags); | |
899 | *link_up_p = link_up; | |
900 | return 0; | |
901 | } | |
902 | ||
903 | ||
904 | static int link_status_1g_rgmii(struct niu *np, int *link_up_p) | |
905 | { | |
906 | struct niu_link_config *lp = &np->link_config; | |
907 | u16 current_speed, bmsr; | |
908 | unsigned long flags; | |
909 | u8 current_duplex; | |
910 | int err, link_up; | |
911 | ||
912 | link_up = 0; | |
913 | current_speed = SPEED_INVALID; | |
914 | current_duplex = DUPLEX_INVALID; | |
915 | ||
916 | spin_lock_irqsave(&np->lock, flags); | |
917 | ||
918 | err = -EINVAL; | |
919 | ||
920 | err = mii_read(np, np->phy_addr, MII_BMSR); | |
921 | if (err < 0) | |
922 | goto out; | |
923 | ||
924 | bmsr = err; | |
925 | if (bmsr & BMSR_LSTATUS) { | |
926 | u16 adv, lpa, common, estat; | |
927 | ||
928 | err = mii_read(np, np->phy_addr, MII_ADVERTISE); | |
929 | if (err < 0) | |
930 | goto out; | |
931 | adv = err; | |
932 | ||
933 | err = mii_read(np, np->phy_addr, MII_LPA); | |
934 | if (err < 0) | |
935 | goto out; | |
936 | lpa = err; | |
937 | ||
938 | common = adv & lpa; | |
939 | ||
940 | err = mii_read(np, np->phy_addr, MII_ESTATUS); | |
941 | if (err < 0) | |
942 | goto out; | |
943 | estat = err; | |
944 | link_up = 1; | |
945 | current_speed = SPEED_1000; | |
946 | current_duplex = DUPLEX_FULL; | |
947 | ||
948 | } | |
949 | lp->active_speed = current_speed; | |
950 | lp->active_duplex = current_duplex; | |
951 | err = 0; | |
952 | ||
953 | out: | |
954 | spin_unlock_irqrestore(&np->lock, flags); | |
955 | ||
956 | *link_up_p = link_up; | |
957 | return err; | |
958 | } | |
959 | ||
960 | ||
a3138df9 DM |
961 | static int bcm8704_reset(struct niu *np) |
962 | { | |
963 | int err, limit; | |
964 | ||
965 | err = mdio_read(np, np->phy_addr, | |
966 | BCM8704_PHYXS_DEV_ADDR, MII_BMCR); | |
967 | if (err < 0) | |
968 | return err; | |
969 | err |= BMCR_RESET; | |
970 | err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, | |
971 | MII_BMCR, err); | |
972 | if (err) | |
973 | return err; | |
974 | ||
975 | limit = 1000; | |
976 | while (--limit >= 0) { | |
977 | err = mdio_read(np, np->phy_addr, | |
978 | BCM8704_PHYXS_DEV_ADDR, MII_BMCR); | |
979 | if (err < 0) | |
980 | return err; | |
981 | if (!(err & BMCR_RESET)) | |
982 | break; | |
983 | } | |
984 | if (limit < 0) { | |
985 | dev_err(np->device, PFX "Port %u PHY will not reset " | |
986 | "(bmcr=%04x)\n", np->port, (err & 0xffff)); | |
987 | return -ENODEV; | |
988 | } | |
989 | return 0; | |
990 | } | |
991 | ||
992 | /* When written, certain PHY registers need to be read back twice | |
993 | * in order for the bits to settle properly. | |
994 | */ | |
995 | static int bcm8704_user_dev3_readback(struct niu *np, int reg) | |
996 | { | |
997 | int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); | |
998 | if (err < 0) | |
999 | return err; | |
1000 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); | |
1001 | if (err < 0) | |
1002 | return err; | |
1003 | return 0; | |
1004 | } | |
1005 | ||
a5d6ab56 MW |
1006 | static int bcm8706_init_user_dev3(struct niu *np) |
1007 | { | |
1008 | int err; | |
1009 | ||
1010 | ||
1011 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
1012 | BCM8704_USER_OPT_DIGITAL_CTRL); | |
1013 | if (err < 0) | |
1014 | return err; | |
1015 | err &= ~USER_ODIG_CTRL_GPIOS; | |
1016 | err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); | |
1017 | err |= USER_ODIG_CTRL_RESV2; | |
1018 | err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
1019 | BCM8704_USER_OPT_DIGITAL_CTRL, err); | |
1020 | if (err) | |
1021 | return err; | |
1022 | ||
1023 | mdelay(1000); | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | ||
a3138df9 DM |
1028 | static int bcm8704_init_user_dev3(struct niu *np) |
1029 | { | |
1030 | int err; | |
1031 | ||
1032 | err = mdio_write(np, np->phy_addr, | |
1033 | BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL, | |
1034 | (USER_CONTROL_OPTXRST_LVL | | |
1035 | USER_CONTROL_OPBIASFLT_LVL | | |
1036 | USER_CONTROL_OBTMPFLT_LVL | | |
1037 | USER_CONTROL_OPPRFLT_LVL | | |
1038 | USER_CONTROL_OPTXFLT_LVL | | |
1039 | USER_CONTROL_OPRXLOS_LVL | | |
1040 | USER_CONTROL_OPRXFLT_LVL | | |
1041 | USER_CONTROL_OPTXON_LVL | | |
1042 | (0x3f << USER_CONTROL_RES1_SHIFT))); | |
1043 | if (err) | |
1044 | return err; | |
1045 | ||
1046 | err = mdio_write(np, np->phy_addr, | |
1047 | BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL, | |
1048 | (USER_PMD_TX_CTL_XFP_CLKEN | | |
1049 | (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) | | |
1050 | (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) | | |
1051 | USER_PMD_TX_CTL_TSCK_LPWREN)); | |
1052 | if (err) | |
1053 | return err; | |
1054 | ||
1055 | err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL); | |
1056 | if (err) | |
1057 | return err; | |
1058 | err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL); | |
1059 | if (err) | |
1060 | return err; | |
1061 | ||
1062 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
1063 | BCM8704_USER_OPT_DIGITAL_CTRL); | |
1064 | if (err < 0) | |
1065 | return err; | |
1066 | err &= ~USER_ODIG_CTRL_GPIOS; | |
1067 | err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); | |
1068 | err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
1069 | BCM8704_USER_OPT_DIGITAL_CTRL, err); | |
1070 | if (err) | |
1071 | return err; | |
1072 | ||
1073 | mdelay(1000); | |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
b0de8e40 ML |
1078 | static int mrvl88x2011_act_led(struct niu *np, int val) |
1079 | { | |
1080 | int err; | |
1081 | ||
1082 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, | |
1083 | MRVL88X2011_LED_8_TO_11_CTL); | |
1084 | if (err < 0) | |
1085 | return err; | |
1086 | ||
1087 | err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK); | |
1088 | err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val); | |
1089 | ||
1090 | return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, | |
1091 | MRVL88X2011_LED_8_TO_11_CTL, err); | |
1092 | } | |
1093 | ||
1094 | static int mrvl88x2011_led_blink_rate(struct niu *np, int rate) | |
1095 | { | |
1096 | int err; | |
1097 | ||
1098 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, | |
1099 | MRVL88X2011_LED_BLINK_CTL); | |
1100 | if (err >= 0) { | |
1101 | err &= ~MRVL88X2011_LED_BLKRATE_MASK; | |
1102 | err |= (rate << 4); | |
1103 | ||
1104 | err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, | |
1105 | MRVL88X2011_LED_BLINK_CTL, err); | |
1106 | } | |
1107 | ||
1108 | return err; | |
1109 | } | |
1110 | ||
1111 | static int xcvr_init_10g_mrvl88x2011(struct niu *np) | |
1112 | { | |
1113 | int err; | |
1114 | ||
1115 | /* Set LED functions */ | |
1116 | err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS); | |
1117 | if (err) | |
1118 | return err; | |
1119 | ||
1120 | /* led activity */ | |
1121 | err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF); | |
1122 | if (err) | |
1123 | return err; | |
1124 | ||
1125 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, | |
1126 | MRVL88X2011_GENERAL_CTL); | |
1127 | if (err < 0) | |
1128 | return err; | |
1129 | ||
1130 | err |= MRVL88X2011_ENA_XFPREFCLK; | |
1131 | ||
1132 | err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, | |
1133 | MRVL88X2011_GENERAL_CTL, err); | |
1134 | if (err < 0) | |
1135 | return err; | |
1136 | ||
1137 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, | |
1138 | MRVL88X2011_PMA_PMD_CTL_1); | |
1139 | if (err < 0) | |
1140 | return err; | |
1141 | ||
1142 | if (np->link_config.loopback_mode == LOOPBACK_MAC) | |
1143 | err |= MRVL88X2011_LOOPBACK; | |
1144 | else | |
1145 | err &= ~MRVL88X2011_LOOPBACK; | |
1146 | ||
1147 | err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, | |
1148 | MRVL88X2011_PMA_PMD_CTL_1, err); | |
1149 | if (err < 0) | |
1150 | return err; | |
1151 | ||
1152 | /* Enable PMD */ | |
1153 | return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, | |
1154 | MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX); | |
1155 | } | |
1156 | ||
a5d6ab56 MW |
1157 | |
1158 | static int xcvr_diag_bcm870x(struct niu *np) | |
a3138df9 | 1159 | { |
a3138df9 | 1160 | u16 analog_stat0, tx_alarm_status; |
a5d6ab56 | 1161 | int err = 0; |
a3138df9 DM |
1162 | |
1163 | #if 1 | |
1164 | err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, | |
1165 | MII_STAT1000); | |
1166 | if (err < 0) | |
1167 | return err; | |
1168 | pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n", | |
1169 | np->port, err); | |
1170 | ||
1171 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20); | |
1172 | if (err < 0) | |
1173 | return err; | |
1174 | pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n", | |
1175 | np->port, err); | |
1176 | ||
1177 | err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, | |
1178 | MII_NWAYTEST); | |
1179 | if (err < 0) | |
1180 | return err; | |
1181 | pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n", | |
1182 | np->port, err); | |
1183 | #endif | |
1184 | ||
1185 | /* XXX dig this out it might not be so useful XXX */ | |
1186 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
1187 | BCM8704_USER_ANALOG_STATUS0); | |
1188 | if (err < 0) | |
1189 | return err; | |
1190 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
1191 | BCM8704_USER_ANALOG_STATUS0); | |
1192 | if (err < 0) | |
1193 | return err; | |
1194 | analog_stat0 = err; | |
1195 | ||
1196 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
1197 | BCM8704_USER_TX_ALARM_STATUS); | |
1198 | if (err < 0) | |
1199 | return err; | |
1200 | err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, | |
1201 | BCM8704_USER_TX_ALARM_STATUS); | |
1202 | if (err < 0) | |
1203 | return err; | |
1204 | tx_alarm_status = err; | |
1205 | ||
1206 | if (analog_stat0 != 0x03fc) { | |
1207 | if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) { | |
1208 | pr_info(PFX "Port %u cable not connected " | |
1209 | "or bad cable.\n", np->port); | |
1210 | } else if (analog_stat0 == 0x639c) { | |
1211 | pr_info(PFX "Port %u optical module is bad " | |
1212 | "or missing.\n", np->port); | |
1213 | } | |
1214 | } | |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | ||
a5d6ab56 MW |
1219 | static int xcvr_10g_set_lb_bcm870x(struct niu *np) |
1220 | { | |
1221 | struct niu_link_config *lp = &np->link_config; | |
1222 | int err; | |
1223 | ||
1224 | err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, | |
1225 | MII_BMCR); | |
1226 | if (err < 0) | |
1227 | return err; | |
1228 | ||
1229 | err &= ~BMCR_LOOPBACK; | |
1230 | ||
1231 | if (lp->loopback_mode == LOOPBACK_MAC) | |
1232 | err |= BMCR_LOOPBACK; | |
1233 | ||
1234 | err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, | |
1235 | MII_BMCR, err); | |
1236 | if (err) | |
1237 | return err; | |
1238 | ||
1239 | return 0; | |
1240 | } | |
1241 | ||
1242 | static int xcvr_init_10g_bcm8706(struct niu *np) | |
1243 | { | |
1244 | int err = 0; | |
1245 | u64 val; | |
1246 | ||
1247 | if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) && | |
1248 | (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0) | |
1249 | return err; | |
1250 | ||
1251 | val = nr64_mac(XMAC_CONFIG); | |
1252 | val &= ~XMAC_CONFIG_LED_POLARITY; | |
1253 | val |= XMAC_CONFIG_FORCE_LED_ON; | |
1254 | nw64_mac(XMAC_CONFIG, val); | |
1255 | ||
1256 | val = nr64(MIF_CONFIG); | |
1257 | val |= MIF_CONFIG_INDIRECT_MODE; | |
1258 | nw64(MIF_CONFIG, val); | |
1259 | ||
1260 | err = bcm8704_reset(np); | |
1261 | if (err) | |
1262 | return err; | |
1263 | ||
1264 | err = xcvr_10g_set_lb_bcm870x(np); | |
1265 | if (err) | |
1266 | return err; | |
1267 | ||
1268 | err = bcm8706_init_user_dev3(np); | |
1269 | if (err) | |
1270 | return err; | |
1271 | ||
1272 | err = xcvr_diag_bcm870x(np); | |
1273 | if (err) | |
1274 | return err; | |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
1279 | static int xcvr_init_10g_bcm8704(struct niu *np) | |
1280 | { | |
1281 | int err; | |
1282 | ||
1283 | err = bcm8704_reset(np); | |
1284 | if (err) | |
1285 | return err; | |
1286 | ||
1287 | err = bcm8704_init_user_dev3(np); | |
1288 | if (err) | |
1289 | return err; | |
1290 | ||
1291 | err = xcvr_10g_set_lb_bcm870x(np); | |
1292 | if (err) | |
1293 | return err; | |
1294 | ||
1295 | err = xcvr_diag_bcm870x(np); | |
1296 | if (err) | |
1297 | return err; | |
1298 | ||
1299 | return 0; | |
1300 | } | |
1301 | ||
b0de8e40 ML |
1302 | static int xcvr_init_10g(struct niu *np) |
1303 | { | |
1304 | int phy_id, err; | |
1305 | u64 val; | |
1306 | ||
1307 | val = nr64_mac(XMAC_CONFIG); | |
1308 | val &= ~XMAC_CONFIG_LED_POLARITY; | |
1309 | val |= XMAC_CONFIG_FORCE_LED_ON; | |
1310 | nw64_mac(XMAC_CONFIG, val); | |
1311 | ||
1312 | /* XXX shared resource, lock parent XXX */ | |
1313 | val = nr64(MIF_CONFIG); | |
1314 | val |= MIF_CONFIG_INDIRECT_MODE; | |
1315 | nw64(MIF_CONFIG, val); | |
1316 | ||
1317 | phy_id = phy_decode(np->parent->port_phy, np->port); | |
1318 | phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; | |
1319 | ||
1320 | /* handle different phy types */ | |
1321 | switch (phy_id & NIU_PHY_ID_MASK) { | |
1322 | case NIU_PHY_ID_MRVL88X2011: | |
1323 | err = xcvr_init_10g_mrvl88x2011(np); | |
1324 | break; | |
1325 | ||
1326 | default: /* bcom 8704 */ | |
1327 | err = xcvr_init_10g_bcm8704(np); | |
1328 | break; | |
1329 | } | |
1330 | ||
1331 | return 0; | |
1332 | } | |
1333 | ||
a3138df9 DM |
1334 | static int mii_reset(struct niu *np) |
1335 | { | |
1336 | int limit, err; | |
1337 | ||
1338 | err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET); | |
1339 | if (err) | |
1340 | return err; | |
1341 | ||
1342 | limit = 1000; | |
1343 | while (--limit >= 0) { | |
1344 | udelay(500); | |
1345 | err = mii_read(np, np->phy_addr, MII_BMCR); | |
1346 | if (err < 0) | |
1347 | return err; | |
1348 | if (!(err & BMCR_RESET)) | |
1349 | break; | |
1350 | } | |
1351 | if (limit < 0) { | |
1352 | dev_err(np->device, PFX "Port %u MII would not reset, " | |
1353 | "bmcr[%04x]\n", np->port, err); | |
1354 | return -ENODEV; | |
1355 | } | |
1356 | ||
1357 | return 0; | |
1358 | } | |
1359 | ||
5fbd7e24 MW |
1360 | |
1361 | ||
1362 | static int xcvr_init_1g_rgmii(struct niu *np) | |
1363 | { | |
1364 | int err; | |
1365 | u64 val; | |
1366 | u16 bmcr, bmsr, estat; | |
1367 | ||
1368 | val = nr64(MIF_CONFIG); | |
1369 | val &= ~MIF_CONFIG_INDIRECT_MODE; | |
1370 | nw64(MIF_CONFIG, val); | |
1371 | ||
1372 | err = mii_reset(np); | |
1373 | if (err) | |
1374 | return err; | |
1375 | ||
1376 | err = mii_read(np, np->phy_addr, MII_BMSR); | |
1377 | if (err < 0) | |
1378 | return err; | |
1379 | bmsr = err; | |
1380 | ||
1381 | estat = 0; | |
1382 | if (bmsr & BMSR_ESTATEN) { | |
1383 | err = mii_read(np, np->phy_addr, MII_ESTATUS); | |
1384 | if (err < 0) | |
1385 | return err; | |
1386 | estat = err; | |
1387 | } | |
1388 | ||
1389 | bmcr = 0; | |
1390 | err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); | |
1391 | if (err) | |
1392 | return err; | |
1393 | ||
1394 | if (bmsr & BMSR_ESTATEN) { | |
1395 | u16 ctrl1000 = 0; | |
1396 | ||
1397 | if (estat & ESTATUS_1000_TFULL) | |
1398 | ctrl1000 |= ADVERTISE_1000FULL; | |
1399 | err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000); | |
1400 | if (err) | |
1401 | return err; | |
1402 | } | |
1403 | ||
1404 | bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX); | |
1405 | ||
1406 | err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); | |
1407 | if (err) | |
1408 | return err; | |
1409 | ||
1410 | err = mii_read(np, np->phy_addr, MII_BMCR); | |
1411 | if (err < 0) | |
1412 | return err; | |
1413 | bmcr = mii_read(np, np->phy_addr, MII_BMCR); | |
1414 | ||
1415 | err = mii_read(np, np->phy_addr, MII_BMSR); | |
1416 | if (err < 0) | |
1417 | return err; | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
1422 | ||
a3138df9 DM |
1423 | static int mii_init_common(struct niu *np) |
1424 | { | |
1425 | struct niu_link_config *lp = &np->link_config; | |
1426 | u16 bmcr, bmsr, adv, estat; | |
1427 | int err; | |
1428 | ||
1429 | err = mii_reset(np); | |
1430 | if (err) | |
1431 | return err; | |
1432 | ||
1433 | err = mii_read(np, np->phy_addr, MII_BMSR); | |
1434 | if (err < 0) | |
1435 | return err; | |
1436 | bmsr = err; | |
1437 | ||
1438 | estat = 0; | |
1439 | if (bmsr & BMSR_ESTATEN) { | |
1440 | err = mii_read(np, np->phy_addr, MII_ESTATUS); | |
1441 | if (err < 0) | |
1442 | return err; | |
1443 | estat = err; | |
1444 | } | |
1445 | ||
1446 | bmcr = 0; | |
1447 | err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); | |
1448 | if (err) | |
1449 | return err; | |
1450 | ||
1451 | if (lp->loopback_mode == LOOPBACK_MAC) { | |
1452 | bmcr |= BMCR_LOOPBACK; | |
1453 | if (lp->active_speed == SPEED_1000) | |
1454 | bmcr |= BMCR_SPEED1000; | |
1455 | if (lp->active_duplex == DUPLEX_FULL) | |
1456 | bmcr |= BMCR_FULLDPLX; | |
1457 | } | |
1458 | ||
1459 | if (lp->loopback_mode == LOOPBACK_PHY) { | |
1460 | u16 aux; | |
1461 | ||
1462 | aux = (BCM5464R_AUX_CTL_EXT_LB | | |
1463 | BCM5464R_AUX_CTL_WRITE_1); | |
1464 | err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux); | |
1465 | if (err) | |
1466 | return err; | |
1467 | } | |
1468 | ||
1469 | /* XXX configurable XXX */ | |
1470 | /* XXX for now don't advertise half-duplex or asym pause... XXX */ | |
1471 | adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP; | |
1472 | if (bmsr & BMSR_10FULL) | |
1473 | adv |= ADVERTISE_10FULL; | |
1474 | if (bmsr & BMSR_100FULL) | |
1475 | adv |= ADVERTISE_100FULL; | |
1476 | err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv); | |
1477 | if (err) | |
1478 | return err; | |
1479 | ||
1480 | if (bmsr & BMSR_ESTATEN) { | |
1481 | u16 ctrl1000 = 0; | |
1482 | ||
1483 | if (estat & ESTATUS_1000_TFULL) | |
1484 | ctrl1000 |= ADVERTISE_1000FULL; | |
1485 | err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000); | |
1486 | if (err) | |
1487 | return err; | |
1488 | } | |
1489 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
1490 | ||
1491 | err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); | |
1492 | if (err) | |
1493 | return err; | |
1494 | ||
1495 | err = mii_read(np, np->phy_addr, MII_BMCR); | |
1496 | if (err < 0) | |
1497 | return err; | |
1498 | err = mii_read(np, np->phy_addr, MII_BMSR); | |
1499 | if (err < 0) | |
1500 | return err; | |
1501 | #if 0 | |
1502 | pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n", | |
1503 | np->port, bmcr, bmsr); | |
1504 | #endif | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
1509 | static int xcvr_init_1g(struct niu *np) | |
1510 | { | |
1511 | u64 val; | |
1512 | ||
1513 | /* XXX shared resource, lock parent XXX */ | |
1514 | val = nr64(MIF_CONFIG); | |
1515 | val &= ~MIF_CONFIG_INDIRECT_MODE; | |
1516 | nw64(MIF_CONFIG, val); | |
1517 | ||
1518 | return mii_init_common(np); | |
1519 | } | |
1520 | ||
1521 | static int niu_xcvr_init(struct niu *np) | |
1522 | { | |
1523 | const struct niu_phy_ops *ops = np->phy_ops; | |
1524 | int err; | |
1525 | ||
1526 | err = 0; | |
1527 | if (ops->xcvr_init) | |
1528 | err = ops->xcvr_init(np); | |
1529 | ||
1530 | return err; | |
1531 | } | |
1532 | ||
1533 | static int niu_serdes_init(struct niu *np) | |
1534 | { | |
1535 | const struct niu_phy_ops *ops = np->phy_ops; | |
1536 | int err; | |
1537 | ||
1538 | err = 0; | |
1539 | if (ops->serdes_init) | |
1540 | err = ops->serdes_init(np); | |
1541 | ||
1542 | return err; | |
1543 | } | |
1544 | ||
1545 | static void niu_init_xif(struct niu *); | |
0c3b091b | 1546 | static void niu_handle_led(struct niu *, int status); |
a3138df9 DM |
1547 | |
1548 | static int niu_link_status_common(struct niu *np, int link_up) | |
1549 | { | |
1550 | struct niu_link_config *lp = &np->link_config; | |
1551 | struct net_device *dev = np->dev; | |
1552 | unsigned long flags; | |
1553 | ||
1554 | if (!netif_carrier_ok(dev) && link_up) { | |
1555 | niuinfo(LINK, "%s: Link is up at %s, %s duplex\n", | |
1556 | dev->name, | |
1557 | (lp->active_speed == SPEED_10000 ? | |
1558 | "10Gb/sec" : | |
1559 | (lp->active_speed == SPEED_1000 ? | |
1560 | "1Gb/sec" : | |
1561 | (lp->active_speed == SPEED_100 ? | |
1562 | "100Mbit/sec" : "10Mbit/sec"))), | |
1563 | (lp->active_duplex == DUPLEX_FULL ? | |
1564 | "full" : "half")); | |
1565 | ||
1566 | spin_lock_irqsave(&np->lock, flags); | |
1567 | niu_init_xif(np); | |
0c3b091b | 1568 | niu_handle_led(np, 1); |
a3138df9 DM |
1569 | spin_unlock_irqrestore(&np->lock, flags); |
1570 | ||
1571 | netif_carrier_on(dev); | |
1572 | } else if (netif_carrier_ok(dev) && !link_up) { | |
1573 | niuwarn(LINK, "%s: Link is down\n", dev->name); | |
0c3b091b ML |
1574 | spin_lock_irqsave(&np->lock, flags); |
1575 | niu_handle_led(np, 0); | |
1576 | spin_unlock_irqrestore(&np->lock, flags); | |
a3138df9 DM |
1577 | netif_carrier_off(dev); |
1578 | } | |
1579 | ||
1580 | return 0; | |
1581 | } | |
1582 | ||
b0de8e40 | 1583 | static int link_status_10g_mrvl(struct niu *np, int *link_up_p) |
a3138df9 | 1584 | { |
b0de8e40 | 1585 | int err, link_up, pma_status, pcs_status; |
a3138df9 DM |
1586 | |
1587 | link_up = 0; | |
1588 | ||
b0de8e40 ML |
1589 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, |
1590 | MRVL88X2011_10G_PMD_STATUS_2); | |
1591 | if (err < 0) | |
1592 | goto out; | |
a3138df9 | 1593 | |
b0de8e40 ML |
1594 | /* Check PMA/PMD Register: 1.0001.2 == 1 */ |
1595 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, | |
1596 | MRVL88X2011_PMA_PMD_STATUS_1); | |
1597 | if (err < 0) | |
1598 | goto out; | |
1599 | ||
1600 | pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); | |
1601 | ||
1602 | /* Check PMC Register : 3.0001.2 == 1: read twice */ | |
1603 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, | |
1604 | MRVL88X2011_PMA_PMD_STATUS_1); | |
1605 | if (err < 0) | |
1606 | goto out; | |
1607 | ||
1608 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, | |
1609 | MRVL88X2011_PMA_PMD_STATUS_1); | |
1610 | if (err < 0) | |
1611 | goto out; | |
1612 | ||
1613 | pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); | |
1614 | ||
1615 | /* Check XGXS Register : 4.0018.[0-3,12] */ | |
1616 | err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR, | |
1617 | MRVL88X2011_10G_XGXS_LANE_STAT); | |
1618 | if (err < 0) | |
a3138df9 DM |
1619 | goto out; |
1620 | ||
b0de8e40 ML |
1621 | if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 | |
1622 | PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 | | |
1623 | PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC | | |
1624 | 0x800)) | |
1625 | link_up = (pma_status && pcs_status) ? 1 : 0; | |
1626 | ||
1627 | np->link_config.active_speed = SPEED_10000; | |
1628 | np->link_config.active_duplex = DUPLEX_FULL; | |
1629 | err = 0; | |
1630 | out: | |
1631 | mrvl88x2011_act_led(np, (link_up ? | |
1632 | MRVL88X2011_LED_CTL_PCS_ACT : | |
1633 | MRVL88X2011_LED_CTL_OFF)); | |
1634 | ||
1635 | *link_up_p = link_up; | |
1636 | return err; | |
1637 | } | |
1638 | ||
a5d6ab56 MW |
1639 | static int link_status_10g_bcm8706(struct niu *np, int *link_up_p) |
1640 | { | |
1641 | int err, link_up; | |
1642 | link_up = 0; | |
1643 | ||
1644 | err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, | |
1645 | BCM8704_PMD_RCV_SIGDET); | |
1646 | if (err < 0) | |
1647 | goto out; | |
1648 | if (!(err & PMD_RCV_SIGDET_GLOBAL)) { | |
1649 | err = 0; | |
1650 | goto out; | |
1651 | } | |
1652 | ||
1653 | err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, | |
1654 | BCM8704_PCS_10G_R_STATUS); | |
1655 | if (err < 0) | |
1656 | goto out; | |
1657 | ||
1658 | if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { | |
1659 | err = 0; | |
1660 | goto out; | |
1661 | } | |
1662 | ||
1663 | err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, | |
1664 | BCM8704_PHYXS_XGXS_LANE_STAT); | |
1665 | if (err < 0) | |
1666 | goto out; | |
1667 | if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | | |
1668 | PHYXS_XGXS_LANE_STAT_MAGIC | | |
1669 | PHYXS_XGXS_LANE_STAT_PATTEST | | |
1670 | PHYXS_XGXS_LANE_STAT_LANE3 | | |
1671 | PHYXS_XGXS_LANE_STAT_LANE2 | | |
1672 | PHYXS_XGXS_LANE_STAT_LANE1 | | |
1673 | PHYXS_XGXS_LANE_STAT_LANE0)) { | |
1674 | err = 0; | |
1675 | np->link_config.active_speed = SPEED_INVALID; | |
1676 | np->link_config.active_duplex = DUPLEX_INVALID; | |
1677 | goto out; | |
1678 | } | |
1679 | ||
1680 | link_up = 1; | |
1681 | np->link_config.active_speed = SPEED_10000; | |
1682 | np->link_config.active_duplex = DUPLEX_FULL; | |
1683 | err = 0; | |
1684 | ||
1685 | out: | |
1686 | *link_up_p = link_up; | |
1687 | if (np->flags & NIU_FLAGS_HOTPLUG_PHY) | |
1688 | err = 0; | |
1689 | return err; | |
1690 | } | |
1691 | ||
b0de8e40 ML |
1692 | static int link_status_10g_bcom(struct niu *np, int *link_up_p) |
1693 | { | |
1694 | int err, link_up; | |
1695 | ||
1696 | link_up = 0; | |
1697 | ||
a3138df9 DM |
1698 | err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, |
1699 | BCM8704_PMD_RCV_SIGDET); | |
1700 | if (err < 0) | |
1701 | goto out; | |
1702 | if (!(err & PMD_RCV_SIGDET_GLOBAL)) { | |
1703 | err = 0; | |
1704 | goto out; | |
1705 | } | |
1706 | ||
1707 | err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, | |
1708 | BCM8704_PCS_10G_R_STATUS); | |
1709 | if (err < 0) | |
1710 | goto out; | |
1711 | if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { | |
1712 | err = 0; | |
1713 | goto out; | |
1714 | } | |
1715 | ||
1716 | err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, | |
1717 | BCM8704_PHYXS_XGXS_LANE_STAT); | |
1718 | if (err < 0) | |
1719 | goto out; | |
1720 | ||
1721 | if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | | |
1722 | PHYXS_XGXS_LANE_STAT_MAGIC | | |
1723 | PHYXS_XGXS_LANE_STAT_LANE3 | | |
1724 | PHYXS_XGXS_LANE_STAT_LANE2 | | |
1725 | PHYXS_XGXS_LANE_STAT_LANE1 | | |
1726 | PHYXS_XGXS_LANE_STAT_LANE0)) { | |
1727 | err = 0; | |
1728 | goto out; | |
1729 | } | |
1730 | ||
1731 | link_up = 1; | |
1732 | np->link_config.active_speed = SPEED_10000; | |
1733 | np->link_config.active_duplex = DUPLEX_FULL; | |
1734 | err = 0; | |
1735 | ||
1736 | out: | |
b0de8e40 ML |
1737 | *link_up_p = link_up; |
1738 | return err; | |
1739 | } | |
1740 | ||
1741 | static int link_status_10g(struct niu *np, int *link_up_p) | |
1742 | { | |
1743 | unsigned long flags; | |
1744 | int err = -EINVAL; | |
1745 | ||
1746 | spin_lock_irqsave(&np->lock, flags); | |
1747 | ||
1748 | if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { | |
1749 | int phy_id; | |
1750 | ||
1751 | phy_id = phy_decode(np->parent->port_phy, np->port); | |
1752 | phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; | |
1753 | ||
1754 | /* handle different phy types */ | |
1755 | switch (phy_id & NIU_PHY_ID_MASK) { | |
1756 | case NIU_PHY_ID_MRVL88X2011: | |
1757 | err = link_status_10g_mrvl(np, link_up_p); | |
1758 | break; | |
1759 | ||
1760 | default: /* bcom 8704 */ | |
1761 | err = link_status_10g_bcom(np, link_up_p); | |
1762 | break; | |
1763 | } | |
1764 | } | |
1765 | ||
a3138df9 DM |
1766 | spin_unlock_irqrestore(&np->lock, flags); |
1767 | ||
a3138df9 DM |
1768 | return err; |
1769 | } | |
1770 | ||
a5d6ab56 MW |
1771 | static int niu_10g_phy_present(struct niu *np) |
1772 | { | |
1773 | u64 sig, mask, val; | |
1774 | ||
1775 | sig = nr64(ESR_INT_SIGNALS); | |
1776 | switch (np->port) { | |
1777 | case 0: | |
1778 | mask = ESR_INT_SIGNALS_P0_BITS; | |
1779 | val = (ESR_INT_SRDY0_P0 | | |
1780 | ESR_INT_DET0_P0 | | |
1781 | ESR_INT_XSRDY_P0 | | |
1782 | ESR_INT_XDP_P0_CH3 | | |
1783 | ESR_INT_XDP_P0_CH2 | | |
1784 | ESR_INT_XDP_P0_CH1 | | |
1785 | ESR_INT_XDP_P0_CH0); | |
1786 | break; | |
1787 | ||
1788 | case 1: | |
1789 | mask = ESR_INT_SIGNALS_P1_BITS; | |
1790 | val = (ESR_INT_SRDY0_P1 | | |
1791 | ESR_INT_DET0_P1 | | |
1792 | ESR_INT_XSRDY_P1 | | |
1793 | ESR_INT_XDP_P1_CH3 | | |
1794 | ESR_INT_XDP_P1_CH2 | | |
1795 | ESR_INT_XDP_P1_CH1 | | |
1796 | ESR_INT_XDP_P1_CH0); | |
1797 | break; | |
1798 | ||
1799 | default: | |
1800 | return 0; | |
1801 | } | |
1802 | ||
1803 | if ((sig & mask) != val) | |
1804 | return 0; | |
1805 | return 1; | |
1806 | } | |
1807 | ||
1808 | static int link_status_10g_hotplug(struct niu *np, int *link_up_p) | |
1809 | { | |
1810 | unsigned long flags; | |
1811 | int err = 0; | |
1812 | int phy_present; | |
1813 | int phy_present_prev; | |
1814 | ||
1815 | spin_lock_irqsave(&np->lock, flags); | |
1816 | ||
1817 | if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { | |
1818 | phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ? | |
1819 | 1 : 0; | |
1820 | phy_present = niu_10g_phy_present(np); | |
1821 | if (phy_present != phy_present_prev) { | |
1822 | /* state change */ | |
1823 | if (phy_present) { | |
1824 | np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; | |
1825 | if (np->phy_ops->xcvr_init) | |
1826 | err = np->phy_ops->xcvr_init(np); | |
1827 | if (err) { | |
1828 | /* debounce */ | |
1829 | np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; | |
1830 | } | |
1831 | } else { | |
1832 | np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; | |
1833 | *link_up_p = 0; | |
1834 | niuwarn(LINK, "%s: Hotplug PHY Removed\n", | |
1835 | np->dev->name); | |
1836 | } | |
1837 | } | |
1838 | if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) | |
1839 | err = link_status_10g_bcm8706(np, link_up_p); | |
1840 | } | |
1841 | ||
1842 | spin_unlock_irqrestore(&np->lock, flags); | |
1843 | ||
1844 | return err; | |
1845 | } | |
1846 | ||
a3138df9 DM |
1847 | static int link_status_1g(struct niu *np, int *link_up_p) |
1848 | { | |
e415e6ea | 1849 | struct niu_link_config *lp = &np->link_config; |
a3138df9 DM |
1850 | u16 current_speed, bmsr; |
1851 | unsigned long flags; | |
1852 | u8 current_duplex; | |
1853 | int err, link_up; | |
1854 | ||
1855 | link_up = 0; | |
1856 | current_speed = SPEED_INVALID; | |
1857 | current_duplex = DUPLEX_INVALID; | |
1858 | ||
1859 | spin_lock_irqsave(&np->lock, flags); | |
1860 | ||
1861 | err = -EINVAL; | |
1862 | if (np->link_config.loopback_mode != LOOPBACK_DISABLED) | |
1863 | goto out; | |
1864 | ||
1865 | err = mii_read(np, np->phy_addr, MII_BMSR); | |
1866 | if (err < 0) | |
1867 | goto out; | |
1868 | ||
1869 | bmsr = err; | |
1870 | if (bmsr & BMSR_LSTATUS) { | |
1871 | u16 adv, lpa, common, estat; | |
1872 | ||
1873 | err = mii_read(np, np->phy_addr, MII_ADVERTISE); | |
1874 | if (err < 0) | |
1875 | goto out; | |
1876 | adv = err; | |
1877 | ||
1878 | err = mii_read(np, np->phy_addr, MII_LPA); | |
1879 | if (err < 0) | |
1880 | goto out; | |
1881 | lpa = err; | |
1882 | ||
1883 | common = adv & lpa; | |
1884 | ||
1885 | err = mii_read(np, np->phy_addr, MII_ESTATUS); | |
1886 | if (err < 0) | |
1887 | goto out; | |
1888 | estat = err; | |
1889 | ||
1890 | link_up = 1; | |
1891 | if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) { | |
1892 | current_speed = SPEED_1000; | |
1893 | if (estat & ESTATUS_1000_TFULL) | |
1894 | current_duplex = DUPLEX_FULL; | |
1895 | else | |
1896 | current_duplex = DUPLEX_HALF; | |
1897 | } else { | |
1898 | if (common & ADVERTISE_100BASE4) { | |
1899 | current_speed = SPEED_100; | |
1900 | current_duplex = DUPLEX_HALF; | |
1901 | } else if (common & ADVERTISE_100FULL) { | |
1902 | current_speed = SPEED_100; | |
1903 | current_duplex = DUPLEX_FULL; | |
1904 | } else if (common & ADVERTISE_100HALF) { | |
1905 | current_speed = SPEED_100; | |
1906 | current_duplex = DUPLEX_HALF; | |
1907 | } else if (common & ADVERTISE_10FULL) { | |
1908 | current_speed = SPEED_10; | |
1909 | current_duplex = DUPLEX_FULL; | |
1910 | } else if (common & ADVERTISE_10HALF) { | |
1911 | current_speed = SPEED_10; | |
1912 | current_duplex = DUPLEX_HALF; | |
1913 | } else | |
1914 | link_up = 0; | |
1915 | } | |
1916 | } | |
e415e6ea DM |
1917 | lp->active_speed = current_speed; |
1918 | lp->active_duplex = current_duplex; | |
a3138df9 DM |
1919 | err = 0; |
1920 | ||
1921 | out: | |
1922 | spin_unlock_irqrestore(&np->lock, flags); | |
1923 | ||
1924 | *link_up_p = link_up; | |
1925 | return err; | |
1926 | } | |
1927 | ||
1928 | static int niu_link_status(struct niu *np, int *link_up_p) | |
1929 | { | |
1930 | const struct niu_phy_ops *ops = np->phy_ops; | |
1931 | int err; | |
1932 | ||
1933 | err = 0; | |
1934 | if (ops->link_status) | |
1935 | err = ops->link_status(np, link_up_p); | |
1936 | ||
1937 | return err; | |
1938 | } | |
1939 | ||
1940 | static void niu_timer(unsigned long __opaque) | |
1941 | { | |
1942 | struct niu *np = (struct niu *) __opaque; | |
1943 | unsigned long off; | |
1944 | int err, link_up; | |
1945 | ||
1946 | err = niu_link_status(np, &link_up); | |
1947 | if (!err) | |
1948 | niu_link_status_common(np, link_up); | |
1949 | ||
1950 | if (netif_carrier_ok(np->dev)) | |
1951 | off = 5 * HZ; | |
1952 | else | |
1953 | off = 1 * HZ; | |
1954 | np->timer.expires = jiffies + off; | |
1955 | ||
1956 | add_timer(&np->timer); | |
1957 | } | |
1958 | ||
5fbd7e24 MW |
1959 | static const struct niu_phy_ops phy_ops_10g_serdes = { |
1960 | .serdes_init = serdes_init_10g_serdes, | |
1961 | .link_status = link_status_10g_serdes, | |
1962 | }; | |
1963 | ||
1964 | static const struct niu_phy_ops phy_ops_1g_rgmii = { | |
1965 | .xcvr_init = xcvr_init_1g_rgmii, | |
1966 | .link_status = link_status_1g_rgmii, | |
1967 | }; | |
1968 | ||
a3138df9 DM |
1969 | static const struct niu_phy_ops phy_ops_10g_fiber_niu = { |
1970 | .serdes_init = serdes_init_niu, | |
1971 | .xcvr_init = xcvr_init_10g, | |
1972 | .link_status = link_status_10g, | |
1973 | }; | |
1974 | ||
1975 | static const struct niu_phy_ops phy_ops_10g_fiber = { | |
1976 | .serdes_init = serdes_init_10g, | |
1977 | .xcvr_init = xcvr_init_10g, | |
1978 | .link_status = link_status_10g, | |
1979 | }; | |
1980 | ||
a5d6ab56 MW |
1981 | static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = { |
1982 | .serdes_init = serdes_init_10g, | |
1983 | .xcvr_init = xcvr_init_10g_bcm8706, | |
1984 | .link_status = link_status_10g_hotplug, | |
1985 | }; | |
1986 | ||
a3138df9 DM |
1987 | static const struct niu_phy_ops phy_ops_10g_copper = { |
1988 | .serdes_init = serdes_init_10g, | |
1989 | .link_status = link_status_10g, /* XXX */ | |
1990 | }; | |
1991 | ||
1992 | static const struct niu_phy_ops phy_ops_1g_fiber = { | |
1993 | .serdes_init = serdes_init_1g, | |
1994 | .xcvr_init = xcvr_init_1g, | |
1995 | .link_status = link_status_1g, | |
1996 | }; | |
1997 | ||
1998 | static const struct niu_phy_ops phy_ops_1g_copper = { | |
1999 | .xcvr_init = xcvr_init_1g, | |
2000 | .link_status = link_status_1g, | |
2001 | }; | |
2002 | ||
2003 | struct niu_phy_template { | |
2004 | const struct niu_phy_ops *ops; | |
2005 | u32 phy_addr_base; | |
2006 | }; | |
2007 | ||
2008 | static const struct niu_phy_template phy_template_niu = { | |
2009 | .ops = &phy_ops_10g_fiber_niu, | |
2010 | .phy_addr_base = 16, | |
2011 | }; | |
2012 | ||
2013 | static const struct niu_phy_template phy_template_10g_fiber = { | |
2014 | .ops = &phy_ops_10g_fiber, | |
2015 | .phy_addr_base = 8, | |
2016 | }; | |
2017 | ||
a5d6ab56 MW |
2018 | static const struct niu_phy_template phy_template_10g_fiber_hotplug = { |
2019 | .ops = &phy_ops_10g_fiber_hotplug, | |
2020 | .phy_addr_base = 8, | |
2021 | }; | |
2022 | ||
a3138df9 DM |
2023 | static const struct niu_phy_template phy_template_10g_copper = { |
2024 | .ops = &phy_ops_10g_copper, | |
2025 | .phy_addr_base = 10, | |
2026 | }; | |
2027 | ||
2028 | static const struct niu_phy_template phy_template_1g_fiber = { | |
2029 | .ops = &phy_ops_1g_fiber, | |
2030 | .phy_addr_base = 0, | |
2031 | }; | |
2032 | ||
2033 | static const struct niu_phy_template phy_template_1g_copper = { | |
2034 | .ops = &phy_ops_1g_copper, | |
2035 | .phy_addr_base = 0, | |
2036 | }; | |
2037 | ||
5fbd7e24 MW |
2038 | static const struct niu_phy_template phy_template_1g_rgmii = { |
2039 | .ops = &phy_ops_1g_rgmii, | |
2040 | .phy_addr_base = 0, | |
2041 | }; | |
2042 | ||
2043 | static const struct niu_phy_template phy_template_10g_serdes = { | |
2044 | .ops = &phy_ops_10g_serdes, | |
2045 | .phy_addr_base = 0, | |
2046 | }; | |
2047 | ||
2048 | static int niu_atca_port_num[4] = { | |
2049 | 0, 0, 11, 10 | |
2050 | }; | |
2051 | ||
2052 | static int serdes_init_10g_serdes(struct niu *np) | |
2053 | { | |
2054 | struct niu_link_config *lp = &np->link_config; | |
2055 | unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; | |
2056 | u64 ctrl_val, test_cfg_val, sig, mask, val; | |
2057 | int err; | |
2058 | u64 reset_val; | |
2059 | ||
2060 | switch (np->port) { | |
2061 | case 0: | |
2062 | reset_val = ENET_SERDES_RESET_0; | |
2063 | ctrl_reg = ENET_SERDES_0_CTRL_CFG; | |
2064 | test_cfg_reg = ENET_SERDES_0_TEST_CFG; | |
2065 | pll_cfg = ENET_SERDES_0_PLL_CFG; | |
2066 | break; | |
2067 | case 1: | |
2068 | reset_val = ENET_SERDES_RESET_1; | |
2069 | ctrl_reg = ENET_SERDES_1_CTRL_CFG; | |
2070 | test_cfg_reg = ENET_SERDES_1_TEST_CFG; | |
2071 | pll_cfg = ENET_SERDES_1_PLL_CFG; | |
2072 | break; | |
2073 | ||
2074 | default: | |
2075 | return -EINVAL; | |
2076 | } | |
2077 | ctrl_val = (ENET_SERDES_CTRL_SDET_0 | | |
2078 | ENET_SERDES_CTRL_SDET_1 | | |
2079 | ENET_SERDES_CTRL_SDET_2 | | |
2080 | ENET_SERDES_CTRL_SDET_3 | | |
2081 | (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | | |
2082 | (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | | |
2083 | (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | | |
2084 | (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | | |
2085 | (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | | |
2086 | (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | | |
2087 | (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | | |
2088 | (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); | |
2089 | test_cfg_val = 0; | |
2090 | ||
2091 | if (lp->loopback_mode == LOOPBACK_PHY) { | |
2092 | test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << | |
2093 | ENET_SERDES_TEST_MD_0_SHIFT) | | |
2094 | (ENET_TEST_MD_PAD_LOOPBACK << | |
2095 | ENET_SERDES_TEST_MD_1_SHIFT) | | |
2096 | (ENET_TEST_MD_PAD_LOOPBACK << | |
2097 | ENET_SERDES_TEST_MD_2_SHIFT) | | |
2098 | (ENET_TEST_MD_PAD_LOOPBACK << | |
2099 | ENET_SERDES_TEST_MD_3_SHIFT)); | |
2100 | } | |
2101 | ||
2102 | esr_reset(np); | |
2103 | nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2); | |
2104 | nw64(ctrl_reg, ctrl_val); | |
2105 | nw64(test_cfg_reg, test_cfg_val); | |
2106 | ||
2107 | /* Initialize all 4 lanes of the SERDES. */ | |
2108 | for (i = 0; i < 4; i++) { | |
2109 | u32 rxtx_ctrl, glue0; | |
2110 | ||
2111 | err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); | |
2112 | if (err) | |
2113 | return err; | |
2114 | err = esr_read_glue0(np, i, &glue0); | |
2115 | if (err) | |
2116 | return err; | |
2117 | ||
2118 | rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); | |
2119 | rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | | |
2120 | (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); | |
2121 | ||
2122 | glue0 &= ~(ESR_GLUE_CTRL0_SRATE | | |
2123 | ESR_GLUE_CTRL0_THCNT | | |
2124 | ESR_GLUE_CTRL0_BLTIME); | |
2125 | glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | | |
2126 | (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | | |
2127 | (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | | |
2128 | (BLTIME_300_CYCLES << | |
2129 | ESR_GLUE_CTRL0_BLTIME_SHIFT)); | |
2130 | ||
2131 | err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); | |
2132 | if (err) | |
2133 | return err; | |
2134 | err = esr_write_glue0(np, i, glue0); | |
2135 | if (err) | |
2136 | return err; | |
2137 | } | |
2138 | ||
2139 | ||
2140 | sig = nr64(ESR_INT_SIGNALS); | |
2141 | switch (np->port) { | |
2142 | case 0: | |
2143 | mask = ESR_INT_SIGNALS_P0_BITS; | |
2144 | val = (ESR_INT_SRDY0_P0 | | |
2145 | ESR_INT_DET0_P0 | | |
2146 | ESR_INT_XSRDY_P0 | | |
2147 | ESR_INT_XDP_P0_CH3 | | |
2148 | ESR_INT_XDP_P0_CH2 | | |
2149 | ESR_INT_XDP_P0_CH1 | | |
2150 | ESR_INT_XDP_P0_CH0); | |
2151 | break; | |
2152 | ||
2153 | case 1: | |
2154 | mask = ESR_INT_SIGNALS_P1_BITS; | |
2155 | val = (ESR_INT_SRDY0_P1 | | |
2156 | ESR_INT_DET0_P1 | | |
2157 | ESR_INT_XSRDY_P1 | | |
2158 | ESR_INT_XDP_P1_CH3 | | |
2159 | ESR_INT_XDP_P1_CH2 | | |
2160 | ESR_INT_XDP_P1_CH1 | | |
2161 | ESR_INT_XDP_P1_CH0); | |
2162 | break; | |
2163 | ||
2164 | default: | |
2165 | return -EINVAL; | |
2166 | } | |
2167 | ||
2168 | if ((sig & mask) != val) { | |
2169 | int err; | |
2170 | err = serdes_init_1g_serdes(np); | |
2171 | if (!err) { | |
2172 | np->flags &= ~NIU_FLAGS_10G; | |
2173 | np->mac_xcvr = MAC_XCVR_PCS; | |
2174 | } else { | |
2175 | dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n", | |
2176 | np->port); | |
2177 | return -ENODEV; | |
2178 | } | |
2179 | } | |
2180 | ||
2181 | return 0; | |
2182 | } | |
2183 | ||
a3138df9 DM |
2184 | static int niu_determine_phy_disposition(struct niu *np) |
2185 | { | |
2186 | struct niu_parent *parent = np->parent; | |
2187 | u8 plat_type = parent->plat_type; | |
2188 | const struct niu_phy_template *tp; | |
2189 | u32 phy_addr_off = 0; | |
2190 | ||
2191 | if (plat_type == PLAT_TYPE_NIU) { | |
2192 | tp = &phy_template_niu; | |
2193 | phy_addr_off += np->port; | |
2194 | } else { | |
5fbd7e24 MW |
2195 | switch (np->flags & |
2196 | (NIU_FLAGS_10G | | |
2197 | NIU_FLAGS_FIBER | | |
2198 | NIU_FLAGS_XCVR_SERDES)) { | |
a3138df9 DM |
2199 | case 0: |
2200 | /* 1G copper */ | |
2201 | tp = &phy_template_1g_copper; | |
2202 | if (plat_type == PLAT_TYPE_VF_P0) | |
2203 | phy_addr_off = 10; | |
2204 | else if (plat_type == PLAT_TYPE_VF_P1) | |
2205 | phy_addr_off = 26; | |
2206 | ||
2207 | phy_addr_off += (np->port ^ 0x3); | |
2208 | break; | |
2209 | ||
2210 | case NIU_FLAGS_10G: | |
2211 | /* 10G copper */ | |
2212 | tp = &phy_template_1g_copper; | |
2213 | break; | |
2214 | ||
2215 | case NIU_FLAGS_FIBER: | |
2216 | /* 1G fiber */ | |
2217 | tp = &phy_template_1g_fiber; | |
2218 | break; | |
2219 | ||
2220 | case NIU_FLAGS_10G | NIU_FLAGS_FIBER: | |
2221 | /* 10G fiber */ | |
2222 | tp = &phy_template_10g_fiber; | |
2223 | if (plat_type == PLAT_TYPE_VF_P0 || | |
2224 | plat_type == PLAT_TYPE_VF_P1) | |
2225 | phy_addr_off = 8; | |
2226 | phy_addr_off += np->port; | |
a5d6ab56 MW |
2227 | if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { |
2228 | tp = &phy_template_10g_fiber_hotplug; | |
2229 | if (np->port == 0) | |
2230 | phy_addr_off = 8; | |
2231 | if (np->port == 1) | |
2232 | phy_addr_off = 12; | |
2233 | } | |
a3138df9 DM |
2234 | break; |
2235 | ||
5fbd7e24 MW |
2236 | case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: |
2237 | case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: | |
2238 | case NIU_FLAGS_XCVR_SERDES: | |
2239 | switch(np->port) { | |
2240 | case 0: | |
2241 | case 1: | |
2242 | tp = &phy_template_10g_serdes; | |
2243 | break; | |
2244 | case 2: | |
2245 | case 3: | |
2246 | tp = &phy_template_1g_rgmii; | |
2247 | break; | |
2248 | default: | |
2249 | return -EINVAL; | |
2250 | break; | |
2251 | } | |
2252 | phy_addr_off = niu_atca_port_num[np->port]; | |
2253 | break; | |
2254 | ||
a3138df9 DM |
2255 | default: |
2256 | return -EINVAL; | |
2257 | } | |
2258 | } | |
2259 | ||
2260 | np->phy_ops = tp->ops; | |
2261 | np->phy_addr = tp->phy_addr_base + phy_addr_off; | |
2262 | ||
2263 | return 0; | |
2264 | } | |
2265 | ||
2266 | static int niu_init_link(struct niu *np) | |
2267 | { | |
2268 | struct niu_parent *parent = np->parent; | |
2269 | int err, ignore; | |
2270 | ||
2271 | if (parent->plat_type == PLAT_TYPE_NIU) { | |
2272 | err = niu_xcvr_init(np); | |
2273 | if (err) | |
2274 | return err; | |
2275 | msleep(200); | |
2276 | } | |
2277 | err = niu_serdes_init(np); | |
2278 | if (err) | |
2279 | return err; | |
2280 | msleep(200); | |
2281 | err = niu_xcvr_init(np); | |
2282 | if (!err) | |
2283 | niu_link_status(np, &ignore); | |
2284 | return 0; | |
2285 | } | |
2286 | ||
2287 | static void niu_set_primary_mac(struct niu *np, unsigned char *addr) | |
2288 | { | |
2289 | u16 reg0 = addr[4] << 8 | addr[5]; | |
2290 | u16 reg1 = addr[2] << 8 | addr[3]; | |
2291 | u16 reg2 = addr[0] << 8 | addr[1]; | |
2292 | ||
2293 | if (np->flags & NIU_FLAGS_XMAC) { | |
2294 | nw64_mac(XMAC_ADDR0, reg0); | |
2295 | nw64_mac(XMAC_ADDR1, reg1); | |
2296 | nw64_mac(XMAC_ADDR2, reg2); | |
2297 | } else { | |
2298 | nw64_mac(BMAC_ADDR0, reg0); | |
2299 | nw64_mac(BMAC_ADDR1, reg1); | |
2300 | nw64_mac(BMAC_ADDR2, reg2); | |
2301 | } | |
2302 | } | |
2303 | ||
2304 | static int niu_num_alt_addr(struct niu *np) | |
2305 | { | |
2306 | if (np->flags & NIU_FLAGS_XMAC) | |
2307 | return XMAC_NUM_ALT_ADDR; | |
2308 | else | |
2309 | return BMAC_NUM_ALT_ADDR; | |
2310 | } | |
2311 | ||
2312 | static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr) | |
2313 | { | |
2314 | u16 reg0 = addr[4] << 8 | addr[5]; | |
2315 | u16 reg1 = addr[2] << 8 | addr[3]; | |
2316 | u16 reg2 = addr[0] << 8 | addr[1]; | |
2317 | ||
2318 | if (index >= niu_num_alt_addr(np)) | |
2319 | return -EINVAL; | |
2320 | ||
2321 | if (np->flags & NIU_FLAGS_XMAC) { | |
2322 | nw64_mac(XMAC_ALT_ADDR0(index), reg0); | |
2323 | nw64_mac(XMAC_ALT_ADDR1(index), reg1); | |
2324 | nw64_mac(XMAC_ALT_ADDR2(index), reg2); | |
2325 | } else { | |
2326 | nw64_mac(BMAC_ALT_ADDR0(index), reg0); | |
2327 | nw64_mac(BMAC_ALT_ADDR1(index), reg1); | |
2328 | nw64_mac(BMAC_ALT_ADDR2(index), reg2); | |
2329 | } | |
2330 | ||
2331 | return 0; | |
2332 | } | |
2333 | ||
2334 | static int niu_enable_alt_mac(struct niu *np, int index, int on) | |
2335 | { | |
2336 | unsigned long reg; | |
2337 | u64 val, mask; | |
2338 | ||
2339 | if (index >= niu_num_alt_addr(np)) | |
2340 | return -EINVAL; | |
2341 | ||
fa907895 | 2342 | if (np->flags & NIU_FLAGS_XMAC) { |
a3138df9 | 2343 | reg = XMAC_ADDR_CMPEN; |
fa907895 MW |
2344 | mask = 1 << index; |
2345 | } else { | |
a3138df9 | 2346 | reg = BMAC_ADDR_CMPEN; |
fa907895 MW |
2347 | mask = 1 << (index + 1); |
2348 | } | |
a3138df9 DM |
2349 | |
2350 | val = nr64_mac(reg); | |
2351 | if (on) | |
2352 | val |= mask; | |
2353 | else | |
2354 | val &= ~mask; | |
2355 | nw64_mac(reg, val); | |
2356 | ||
2357 | return 0; | |
2358 | } | |
2359 | ||
2360 | static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg, | |
2361 | int num, int mac_pref) | |
2362 | { | |
2363 | u64 val = nr64_mac(reg); | |
2364 | val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR); | |
2365 | val |= num; | |
2366 | if (mac_pref) | |
2367 | val |= HOST_INFO_MPR; | |
2368 | nw64_mac(reg, val); | |
2369 | } | |
2370 | ||
2371 | static int __set_rdc_table_num(struct niu *np, | |
2372 | int xmac_index, int bmac_index, | |
2373 | int rdc_table_num, int mac_pref) | |
2374 | { | |
2375 | unsigned long reg; | |
2376 | ||
2377 | if (rdc_table_num & ~HOST_INFO_MACRDCTBLN) | |
2378 | return -EINVAL; | |
2379 | if (np->flags & NIU_FLAGS_XMAC) | |
2380 | reg = XMAC_HOST_INFO(xmac_index); | |
2381 | else | |
2382 | reg = BMAC_HOST_INFO(bmac_index); | |
2383 | __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref); | |
2384 | return 0; | |
2385 | } | |
2386 | ||
2387 | static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num, | |
2388 | int mac_pref) | |
2389 | { | |
2390 | return __set_rdc_table_num(np, 17, 0, table_num, mac_pref); | |
2391 | } | |
2392 | ||
2393 | static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num, | |
2394 | int mac_pref) | |
2395 | { | |
2396 | return __set_rdc_table_num(np, 16, 8, table_num, mac_pref); | |
2397 | } | |
2398 | ||
2399 | static int niu_set_alt_mac_rdc_table(struct niu *np, int idx, | |
2400 | int table_num, int mac_pref) | |
2401 | { | |
2402 | if (idx >= niu_num_alt_addr(np)) | |
2403 | return -EINVAL; | |
2404 | return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref); | |
2405 | } | |
2406 | ||
2407 | static u64 vlan_entry_set_parity(u64 reg_val) | |
2408 | { | |
2409 | u64 port01_mask; | |
2410 | u64 port23_mask; | |
2411 | ||
2412 | port01_mask = 0x00ff; | |
2413 | port23_mask = 0xff00; | |
2414 | ||
2415 | if (hweight64(reg_val & port01_mask) & 1) | |
2416 | reg_val |= ENET_VLAN_TBL_PARITY0; | |
2417 | else | |
2418 | reg_val &= ~ENET_VLAN_TBL_PARITY0; | |
2419 | ||
2420 | if (hweight64(reg_val & port23_mask) & 1) | |
2421 | reg_val |= ENET_VLAN_TBL_PARITY1; | |
2422 | else | |
2423 | reg_val &= ~ENET_VLAN_TBL_PARITY1; | |
2424 | ||
2425 | return reg_val; | |
2426 | } | |
2427 | ||
2428 | static void vlan_tbl_write(struct niu *np, unsigned long index, | |
2429 | int port, int vpr, int rdc_table) | |
2430 | { | |
2431 | u64 reg_val = nr64(ENET_VLAN_TBL(index)); | |
2432 | ||
2433 | reg_val &= ~((ENET_VLAN_TBL_VPR | | |
2434 | ENET_VLAN_TBL_VLANRDCTBLN) << | |
2435 | ENET_VLAN_TBL_SHIFT(port)); | |
2436 | if (vpr) | |
2437 | reg_val |= (ENET_VLAN_TBL_VPR << | |
2438 | ENET_VLAN_TBL_SHIFT(port)); | |
2439 | reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port)); | |
2440 | ||
2441 | reg_val = vlan_entry_set_parity(reg_val); | |
2442 | ||
2443 | nw64(ENET_VLAN_TBL(index), reg_val); | |
2444 | } | |
2445 | ||
2446 | static void vlan_tbl_clear(struct niu *np) | |
2447 | { | |
2448 | int i; | |
2449 | ||
2450 | for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) | |
2451 | nw64(ENET_VLAN_TBL(i), 0); | |
2452 | } | |
2453 | ||
2454 | static int tcam_wait_bit(struct niu *np, u64 bit) | |
2455 | { | |
2456 | int limit = 1000; | |
2457 | ||
2458 | while (--limit > 0) { | |
2459 | if (nr64(TCAM_CTL) & bit) | |
2460 | break; | |
2461 | udelay(1); | |
2462 | } | |
2463 | if (limit < 0) | |
2464 | return -ENODEV; | |
2465 | ||
2466 | return 0; | |
2467 | } | |
2468 | ||
2469 | static int tcam_flush(struct niu *np, int index) | |
2470 | { | |
2471 | nw64(TCAM_KEY_0, 0x00); | |
2472 | nw64(TCAM_KEY_MASK_0, 0xff); | |
2473 | nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); | |
2474 | ||
2475 | return tcam_wait_bit(np, TCAM_CTL_STAT); | |
2476 | } | |
2477 | ||
2478 | #if 0 | |
2479 | static int tcam_read(struct niu *np, int index, | |
2480 | u64 *key, u64 *mask) | |
2481 | { | |
2482 | int err; | |
2483 | ||
2484 | nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index)); | |
2485 | err = tcam_wait_bit(np, TCAM_CTL_STAT); | |
2486 | if (!err) { | |
2487 | key[0] = nr64(TCAM_KEY_0); | |
2488 | key[1] = nr64(TCAM_KEY_1); | |
2489 | key[2] = nr64(TCAM_KEY_2); | |
2490 | key[3] = nr64(TCAM_KEY_3); | |
2491 | mask[0] = nr64(TCAM_KEY_MASK_0); | |
2492 | mask[1] = nr64(TCAM_KEY_MASK_1); | |
2493 | mask[2] = nr64(TCAM_KEY_MASK_2); | |
2494 | mask[3] = nr64(TCAM_KEY_MASK_3); | |
2495 | } | |
2496 | return err; | |
2497 | } | |
2498 | #endif | |
2499 | ||
2500 | static int tcam_write(struct niu *np, int index, | |
2501 | u64 *key, u64 *mask) | |
2502 | { | |
2503 | nw64(TCAM_KEY_0, key[0]); | |
2504 | nw64(TCAM_KEY_1, key[1]); | |
2505 | nw64(TCAM_KEY_2, key[2]); | |
2506 | nw64(TCAM_KEY_3, key[3]); | |
2507 | nw64(TCAM_KEY_MASK_0, mask[0]); | |
2508 | nw64(TCAM_KEY_MASK_1, mask[1]); | |
2509 | nw64(TCAM_KEY_MASK_2, mask[2]); | |
2510 | nw64(TCAM_KEY_MASK_3, mask[3]); | |
2511 | nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); | |
2512 | ||
2513 | return tcam_wait_bit(np, TCAM_CTL_STAT); | |
2514 | } | |
2515 | ||
2516 | #if 0 | |
2517 | static int tcam_assoc_read(struct niu *np, int index, u64 *data) | |
2518 | { | |
2519 | int err; | |
2520 | ||
2521 | nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index)); | |
2522 | err = tcam_wait_bit(np, TCAM_CTL_STAT); | |
2523 | if (!err) | |
2524 | *data = nr64(TCAM_KEY_1); | |
2525 | ||
2526 | return err; | |
2527 | } | |
2528 | #endif | |
2529 | ||
2530 | static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data) | |
2531 | { | |
2532 | nw64(TCAM_KEY_1, assoc_data); | |
2533 | nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index)); | |
2534 | ||
2535 | return tcam_wait_bit(np, TCAM_CTL_STAT); | |
2536 | } | |
2537 | ||
2538 | static void tcam_enable(struct niu *np, int on) | |
2539 | { | |
2540 | u64 val = nr64(FFLP_CFG_1); | |
2541 | ||
2542 | if (on) | |
2543 | val &= ~FFLP_CFG_1_TCAM_DIS; | |
2544 | else | |
2545 | val |= FFLP_CFG_1_TCAM_DIS; | |
2546 | nw64(FFLP_CFG_1, val); | |
2547 | } | |
2548 | ||
2549 | static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio) | |
2550 | { | |
2551 | u64 val = nr64(FFLP_CFG_1); | |
2552 | ||
2553 | val &= ~(FFLP_CFG_1_FFLPINITDONE | | |
2554 | FFLP_CFG_1_CAMLAT | | |
2555 | FFLP_CFG_1_CAMRATIO); | |
2556 | val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT); | |
2557 | val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT); | |
2558 | nw64(FFLP_CFG_1, val); | |
2559 | ||
2560 | val = nr64(FFLP_CFG_1); | |
2561 | val |= FFLP_CFG_1_FFLPINITDONE; | |
2562 | nw64(FFLP_CFG_1, val); | |
2563 | } | |
2564 | ||
2565 | static int tcam_user_eth_class_enable(struct niu *np, unsigned long class, | |
2566 | int on) | |
2567 | { | |
2568 | unsigned long reg; | |
2569 | u64 val; | |
2570 | ||
2571 | if (class < CLASS_CODE_ETHERTYPE1 || | |
2572 | class > CLASS_CODE_ETHERTYPE2) | |
2573 | return -EINVAL; | |
2574 | ||
2575 | reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); | |
2576 | val = nr64(reg); | |
2577 | if (on) | |
2578 | val |= L2_CLS_VLD; | |
2579 | else | |
2580 | val &= ~L2_CLS_VLD; | |
2581 | nw64(reg, val); | |
2582 | ||
2583 | return 0; | |
2584 | } | |
2585 | ||
2586 | #if 0 | |
2587 | static int tcam_user_eth_class_set(struct niu *np, unsigned long class, | |
2588 | u64 ether_type) | |
2589 | { | |
2590 | unsigned long reg; | |
2591 | u64 val; | |
2592 | ||
2593 | if (class < CLASS_CODE_ETHERTYPE1 || | |
2594 | class > CLASS_CODE_ETHERTYPE2 || | |
2595 | (ether_type & ~(u64)0xffff) != 0) | |
2596 | return -EINVAL; | |
2597 | ||
2598 | reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); | |
2599 | val = nr64(reg); | |
2600 | val &= ~L2_CLS_ETYPE; | |
2601 | val |= (ether_type << L2_CLS_ETYPE_SHIFT); | |
2602 | nw64(reg, val); | |
2603 | ||
2604 | return 0; | |
2605 | } | |
2606 | #endif | |
2607 | ||
2608 | static int tcam_user_ip_class_enable(struct niu *np, unsigned long class, | |
2609 | int on) | |
2610 | { | |
2611 | unsigned long reg; | |
2612 | u64 val; | |
2613 | ||
2614 | if (class < CLASS_CODE_USER_PROG1 || | |
2615 | class > CLASS_CODE_USER_PROG4) | |
2616 | return -EINVAL; | |
2617 | ||
2618 | reg = L3_CLS(class - CLASS_CODE_USER_PROG1); | |
2619 | val = nr64(reg); | |
2620 | if (on) | |
2621 | val |= L3_CLS_VALID; | |
2622 | else | |
2623 | val &= ~L3_CLS_VALID; | |
2624 | nw64(reg, val); | |
2625 | ||
2626 | return 0; | |
2627 | } | |
2628 | ||
2629 | #if 0 | |
2630 | static int tcam_user_ip_class_set(struct niu *np, unsigned long class, | |
2631 | int ipv6, u64 protocol_id, | |
2632 | u64 tos_mask, u64 tos_val) | |
2633 | { | |
2634 | unsigned long reg; | |
2635 | u64 val; | |
2636 | ||
2637 | if (class < CLASS_CODE_USER_PROG1 || | |
2638 | class > CLASS_CODE_USER_PROG4 || | |
2639 | (protocol_id & ~(u64)0xff) != 0 || | |
2640 | (tos_mask & ~(u64)0xff) != 0 || | |
2641 | (tos_val & ~(u64)0xff) != 0) | |
2642 | return -EINVAL; | |
2643 | ||
2644 | reg = L3_CLS(class - CLASS_CODE_USER_PROG1); | |
2645 | val = nr64(reg); | |
2646 | val &= ~(L3_CLS_IPVER | L3_CLS_PID | | |
2647 | L3_CLS_TOSMASK | L3_CLS_TOS); | |
2648 | if (ipv6) | |
2649 | val |= L3_CLS_IPVER; | |
2650 | val |= (protocol_id << L3_CLS_PID_SHIFT); | |
2651 | val |= (tos_mask << L3_CLS_TOSMASK_SHIFT); | |
2652 | val |= (tos_val << L3_CLS_TOS_SHIFT); | |
2653 | nw64(reg, val); | |
2654 | ||
2655 | return 0; | |
2656 | } | |
2657 | #endif | |
2658 | ||
2659 | static int tcam_early_init(struct niu *np) | |
2660 | { | |
2661 | unsigned long i; | |
2662 | int err; | |
2663 | ||
2664 | tcam_enable(np, 0); | |
2665 | tcam_set_lat_and_ratio(np, | |
2666 | DEFAULT_TCAM_LATENCY, | |
2667 | DEFAULT_TCAM_ACCESS_RATIO); | |
2668 | for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) { | |
2669 | err = tcam_user_eth_class_enable(np, i, 0); | |
2670 | if (err) | |
2671 | return err; | |
2672 | } | |
2673 | for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) { | |
2674 | err = tcam_user_ip_class_enable(np, i, 0); | |
2675 | if (err) | |
2676 | return err; | |
2677 | } | |
2678 | ||
2679 | return 0; | |
2680 | } | |
2681 | ||
2682 | static int tcam_flush_all(struct niu *np) | |
2683 | { | |
2684 | unsigned long i; | |
2685 | ||
2686 | for (i = 0; i < np->parent->tcam_num_entries; i++) { | |
2687 | int err = tcam_flush(np, i); | |
2688 | if (err) | |
2689 | return err; | |
2690 | } | |
2691 | return 0; | |
2692 | } | |
2693 | ||
2694 | static u64 hash_addr_regval(unsigned long index, unsigned long num_entries) | |
2695 | { | |
2696 | return ((u64)index | (num_entries == 1 ? | |
2697 | HASH_TBL_ADDR_AUTOINC : 0)); | |
2698 | } | |
2699 | ||
2700 | #if 0 | |
2701 | static int hash_read(struct niu *np, unsigned long partition, | |
2702 | unsigned long index, unsigned long num_entries, | |
2703 | u64 *data) | |
2704 | { | |
2705 | u64 val = hash_addr_regval(index, num_entries); | |
2706 | unsigned long i; | |
2707 | ||
2708 | if (partition >= FCRAM_NUM_PARTITIONS || | |
2709 | index + num_entries > FCRAM_SIZE) | |
2710 | return -EINVAL; | |
2711 | ||
2712 | nw64(HASH_TBL_ADDR(partition), val); | |
2713 | for (i = 0; i < num_entries; i++) | |
2714 | data[i] = nr64(HASH_TBL_DATA(partition)); | |
2715 | ||
2716 | return 0; | |
2717 | } | |
2718 | #endif | |
2719 | ||
2720 | static int hash_write(struct niu *np, unsigned long partition, | |
2721 | unsigned long index, unsigned long num_entries, | |
2722 | u64 *data) | |
2723 | { | |
2724 | u64 val = hash_addr_regval(index, num_entries); | |
2725 | unsigned long i; | |
2726 | ||
2727 | if (partition >= FCRAM_NUM_PARTITIONS || | |
2728 | index + (num_entries * 8) > FCRAM_SIZE) | |
2729 | return -EINVAL; | |
2730 | ||
2731 | nw64(HASH_TBL_ADDR(partition), val); | |
2732 | for (i = 0; i < num_entries; i++) | |
2733 | nw64(HASH_TBL_DATA(partition), data[i]); | |
2734 | ||
2735 | return 0; | |
2736 | } | |
2737 | ||
2738 | static void fflp_reset(struct niu *np) | |
2739 | { | |
2740 | u64 val; | |
2741 | ||
2742 | nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST); | |
2743 | udelay(10); | |
2744 | nw64(FFLP_CFG_1, 0); | |
2745 | ||
2746 | val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE; | |
2747 | nw64(FFLP_CFG_1, val); | |
2748 | } | |
2749 | ||
2750 | static void fflp_set_timings(struct niu *np) | |
2751 | { | |
2752 | u64 val = nr64(FFLP_CFG_1); | |
2753 | ||
2754 | val &= ~FFLP_CFG_1_FFLPINITDONE; | |
2755 | val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT); | |
2756 | nw64(FFLP_CFG_1, val); | |
2757 | ||
2758 | val = nr64(FFLP_CFG_1); | |
2759 | val |= FFLP_CFG_1_FFLPINITDONE; | |
2760 | nw64(FFLP_CFG_1, val); | |
2761 | ||
2762 | val = nr64(FCRAM_REF_TMR); | |
2763 | val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN); | |
2764 | val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT); | |
2765 | val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT); | |
2766 | nw64(FCRAM_REF_TMR, val); | |
2767 | } | |
2768 | ||
2769 | static int fflp_set_partition(struct niu *np, u64 partition, | |
2770 | u64 mask, u64 base, int enable) | |
2771 | { | |
2772 | unsigned long reg; | |
2773 | u64 val; | |
2774 | ||
2775 | if (partition >= FCRAM_NUM_PARTITIONS || | |
2776 | (mask & ~(u64)0x1f) != 0 || | |
2777 | (base & ~(u64)0x1f) != 0) | |
2778 | return -EINVAL; | |
2779 | ||
2780 | reg = FLW_PRT_SEL(partition); | |
2781 | ||
2782 | val = nr64(reg); | |
2783 | val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE); | |
2784 | val |= (mask << FLW_PRT_SEL_MASK_SHIFT); | |
2785 | val |= (base << FLW_PRT_SEL_BASE_SHIFT); | |
2786 | if (enable) | |
2787 | val |= FLW_PRT_SEL_EXT; | |
2788 | nw64(reg, val); | |
2789 | ||
2790 | return 0; | |
2791 | } | |
2792 | ||
2793 | static int fflp_disable_all_partitions(struct niu *np) | |
2794 | { | |
2795 | unsigned long i; | |
2796 | ||
2797 | for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) { | |
2798 | int err = fflp_set_partition(np, 0, 0, 0, 0); | |
2799 | if (err) | |
2800 | return err; | |
2801 | } | |
2802 | return 0; | |
2803 | } | |
2804 | ||
2805 | static void fflp_llcsnap_enable(struct niu *np, int on) | |
2806 | { | |
2807 | u64 val = nr64(FFLP_CFG_1); | |
2808 | ||
2809 | if (on) | |
2810 | val |= FFLP_CFG_1_LLCSNAP; | |
2811 | else | |
2812 | val &= ~FFLP_CFG_1_LLCSNAP; | |
2813 | nw64(FFLP_CFG_1, val); | |
2814 | } | |
2815 | ||
2816 | static void fflp_errors_enable(struct niu *np, int on) | |
2817 | { | |
2818 | u64 val = nr64(FFLP_CFG_1); | |
2819 | ||
2820 | if (on) | |
2821 | val &= ~FFLP_CFG_1_ERRORDIS; | |
2822 | else | |
2823 | val |= FFLP_CFG_1_ERRORDIS; | |
2824 | nw64(FFLP_CFG_1, val); | |
2825 | } | |
2826 | ||
2827 | static int fflp_hash_clear(struct niu *np) | |
2828 | { | |
2829 | struct fcram_hash_ipv4 ent; | |
2830 | unsigned long i; | |
2831 | ||
2832 | /* IPV4 hash entry with valid bit clear, rest is don't care. */ | |
2833 | memset(&ent, 0, sizeof(ent)); | |
2834 | ent.header = HASH_HEADER_EXT; | |
2835 | ||
2836 | for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) { | |
2837 | int err = hash_write(np, 0, i, 1, (u64 *) &ent); | |
2838 | if (err) | |
2839 | return err; | |
2840 | } | |
2841 | return 0; | |
2842 | } | |
2843 | ||
2844 | static int fflp_early_init(struct niu *np) | |
2845 | { | |
2846 | struct niu_parent *parent; | |
2847 | unsigned long flags; | |
2848 | int err; | |
2849 | ||
2850 | niu_lock_parent(np, flags); | |
2851 | ||
2852 | parent = np->parent; | |
2853 | err = 0; | |
2854 | if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) { | |
2855 | niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n", | |
2856 | np->port); | |
2857 | if (np->parent->plat_type != PLAT_TYPE_NIU) { | |
2858 | fflp_reset(np); | |
2859 | fflp_set_timings(np); | |
2860 | err = fflp_disable_all_partitions(np); | |
2861 | if (err) { | |
2862 | niudbg(PROBE, "fflp_disable_all_partitions " | |
2863 | "failed, err=%d\n", err); | |
2864 | goto out; | |
2865 | } | |
2866 | } | |
2867 | ||
2868 | err = tcam_early_init(np); | |
2869 | if (err) { | |
2870 | niudbg(PROBE, "tcam_early_init failed, err=%d\n", | |
2871 | err); | |
2872 | goto out; | |
2873 | } | |
2874 | fflp_llcsnap_enable(np, 1); | |
2875 | fflp_errors_enable(np, 0); | |
2876 | nw64(H1POLY, 0); | |
2877 | nw64(H2POLY, 0); | |
2878 | ||
2879 | err = tcam_flush_all(np); | |
2880 | if (err) { | |
2881 | niudbg(PROBE, "tcam_flush_all failed, err=%d\n", | |
2882 | err); | |
2883 | goto out; | |
2884 | } | |
2885 | if (np->parent->plat_type != PLAT_TYPE_NIU) { | |
2886 | err = fflp_hash_clear(np); | |
2887 | if (err) { | |
2888 | niudbg(PROBE, "fflp_hash_clear failed, " | |
2889 | "err=%d\n", err); | |
2890 | goto out; | |
2891 | } | |
2892 | } | |
2893 | ||
2894 | vlan_tbl_clear(np); | |
2895 | ||
2896 | niudbg(PROBE, "fflp_early_init: Success\n"); | |
2897 | parent->flags |= PARENT_FLGS_CLS_HWINIT; | |
2898 | } | |
2899 | out: | |
2900 | niu_unlock_parent(np, flags); | |
2901 | return err; | |
2902 | } | |
2903 | ||
2904 | static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key) | |
2905 | { | |
2906 | if (class_code < CLASS_CODE_USER_PROG1 || | |
2907 | class_code > CLASS_CODE_SCTP_IPV6) | |
2908 | return -EINVAL; | |
2909 | ||
2910 | nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key); | |
2911 | return 0; | |
2912 | } | |
2913 | ||
2914 | static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key) | |
2915 | { | |
2916 | if (class_code < CLASS_CODE_USER_PROG1 || | |
2917 | class_code > CLASS_CODE_SCTP_IPV6) | |
2918 | return -EINVAL; | |
2919 | ||
2920 | nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key); | |
2921 | return 0; | |
2922 | } | |
2923 | ||
2924 | static void niu_rx_skb_append(struct sk_buff *skb, struct page *page, | |
2925 | u32 offset, u32 size) | |
2926 | { | |
2927 | int i = skb_shinfo(skb)->nr_frags; | |
2928 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2929 | ||
2930 | frag->page = page; | |
2931 | frag->page_offset = offset; | |
2932 | frag->size = size; | |
2933 | ||
2934 | skb->len += size; | |
2935 | skb->data_len += size; | |
2936 | skb->truesize += size; | |
2937 | ||
2938 | skb_shinfo(skb)->nr_frags = i + 1; | |
2939 | } | |
2940 | ||
2941 | static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a) | |
2942 | { | |
2943 | a >>= PAGE_SHIFT; | |
2944 | a ^= (a >> ilog2(MAX_RBR_RING_SIZE)); | |
2945 | ||
2946 | return (a & (MAX_RBR_RING_SIZE - 1)); | |
2947 | } | |
2948 | ||
2949 | static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr, | |
2950 | struct page ***link) | |
2951 | { | |
2952 | unsigned int h = niu_hash_rxaddr(rp, addr); | |
2953 | struct page *p, **pp; | |
2954 | ||
2955 | addr &= PAGE_MASK; | |
2956 | pp = &rp->rxhash[h]; | |
2957 | for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) { | |
2958 | if (p->index == addr) { | |
2959 | *link = pp; | |
2960 | break; | |
2961 | } | |
2962 | } | |
2963 | ||
2964 | return p; | |
2965 | } | |
2966 | ||
2967 | static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base) | |
2968 | { | |
2969 | unsigned int h = niu_hash_rxaddr(rp, base); | |
2970 | ||
2971 | page->index = base; | |
2972 | page->mapping = (struct address_space *) rp->rxhash[h]; | |
2973 | rp->rxhash[h] = page; | |
2974 | } | |
2975 | ||
2976 | static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp, | |
2977 | gfp_t mask, int start_index) | |
2978 | { | |
2979 | struct page *page; | |
2980 | u64 addr; | |
2981 | int i; | |
2982 | ||
2983 | page = alloc_page(mask); | |
2984 | if (!page) | |
2985 | return -ENOMEM; | |
2986 | ||
2987 | addr = np->ops->map_page(np->device, page, 0, | |
2988 | PAGE_SIZE, DMA_FROM_DEVICE); | |
2989 | ||
2990 | niu_hash_page(rp, page, addr); | |
2991 | if (rp->rbr_blocks_per_page > 1) | |
2992 | atomic_add(rp->rbr_blocks_per_page - 1, | |
2993 | &compound_head(page)->_count); | |
2994 | ||
2995 | for (i = 0; i < rp->rbr_blocks_per_page; i++) { | |
2996 | __le32 *rbr = &rp->rbr[start_index + i]; | |
2997 | ||
2998 | *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT); | |
2999 | addr += rp->rbr_block_size; | |
3000 | } | |
3001 | ||
3002 | return 0; | |
3003 | } | |
3004 | ||
3005 | static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) | |
3006 | { | |
3007 | int index = rp->rbr_index; | |
3008 | ||
3009 | rp->rbr_pending++; | |
3010 | if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) { | |
3011 | int err = niu_rbr_add_page(np, rp, mask, index); | |
3012 | ||
3013 | if (unlikely(err)) { | |
3014 | rp->rbr_pending--; | |
3015 | return; | |
3016 | } | |
3017 | ||
3018 | rp->rbr_index += rp->rbr_blocks_per_page; | |
3019 | BUG_ON(rp->rbr_index > rp->rbr_table_size); | |
3020 | if (rp->rbr_index == rp->rbr_table_size) | |
3021 | rp->rbr_index = 0; | |
3022 | ||
3023 | if (rp->rbr_pending >= rp->rbr_kick_thresh) { | |
3024 | nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending); | |
3025 | rp->rbr_pending = 0; | |
3026 | } | |
3027 | } | |
3028 | } | |
3029 | ||
3030 | static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp) | |
3031 | { | |
3032 | unsigned int index = rp->rcr_index; | |
3033 | int num_rcr = 0; | |
3034 | ||
3035 | rp->rx_dropped++; | |
3036 | while (1) { | |
3037 | struct page *page, **link; | |
3038 | u64 addr, val; | |
3039 | u32 rcr_size; | |
3040 | ||
3041 | num_rcr++; | |
3042 | ||
3043 | val = le64_to_cpup(&rp->rcr[index]); | |
3044 | addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << | |
3045 | RCR_ENTRY_PKT_BUF_ADDR_SHIFT; | |
3046 | page = niu_find_rxpage(rp, addr, &link); | |
3047 | ||
3048 | rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> | |
3049 | RCR_ENTRY_PKTBUFSZ_SHIFT]; | |
3050 | if ((page->index + PAGE_SIZE) - rcr_size == addr) { | |
3051 | *link = (struct page *) page->mapping; | |
3052 | np->ops->unmap_page(np->device, page->index, | |
3053 | PAGE_SIZE, DMA_FROM_DEVICE); | |
3054 | page->index = 0; | |
3055 | page->mapping = NULL; | |
3056 | __free_page(page); | |
3057 | rp->rbr_refill_pending++; | |
3058 | } | |
3059 | ||
3060 | index = NEXT_RCR(rp, index); | |
3061 | if (!(val & RCR_ENTRY_MULTI)) | |
3062 | break; | |
3063 | ||
3064 | } | |
3065 | rp->rcr_index = index; | |
3066 | ||
3067 | return num_rcr; | |
3068 | } | |
3069 | ||
3070 | static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp) | |
3071 | { | |
3072 | unsigned int index = rp->rcr_index; | |
3073 | struct sk_buff *skb; | |
3074 | int len, num_rcr; | |
3075 | ||
3076 | skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE); | |
3077 | if (unlikely(!skb)) | |
3078 | return niu_rx_pkt_ignore(np, rp); | |
3079 | ||
3080 | num_rcr = 0; | |
3081 | while (1) { | |
3082 | struct page *page, **link; | |
3083 | u32 rcr_size, append_size; | |
3084 | u64 addr, val, off; | |
3085 | ||
3086 | num_rcr++; | |
3087 | ||
3088 | val = le64_to_cpup(&rp->rcr[index]); | |
3089 | ||
3090 | len = (val & RCR_ENTRY_L2_LEN) >> | |
3091 | RCR_ENTRY_L2_LEN_SHIFT; | |
3092 | len -= ETH_FCS_LEN; | |
3093 | ||
3094 | addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << | |
3095 | RCR_ENTRY_PKT_BUF_ADDR_SHIFT; | |
3096 | page = niu_find_rxpage(rp, addr, &link); | |
3097 | ||
3098 | rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> | |
3099 | RCR_ENTRY_PKTBUFSZ_SHIFT]; | |
3100 | ||
3101 | off = addr & ~PAGE_MASK; | |
3102 | append_size = rcr_size; | |
3103 | if (num_rcr == 1) { | |
3104 | int ptype; | |
3105 | ||
3106 | off += 2; | |
3107 | append_size -= 2; | |
3108 | ||
3109 | ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT); | |
3110 | if ((ptype == RCR_PKT_TYPE_TCP || | |
3111 | ptype == RCR_PKT_TYPE_UDP) && | |
3112 | !(val & (RCR_ENTRY_NOPORT | | |
3113 | RCR_ENTRY_ERROR))) | |
3114 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
3115 | else | |
3116 | skb->ip_summed = CHECKSUM_NONE; | |
3117 | } | |
3118 | if (!(val & RCR_ENTRY_MULTI)) | |
3119 | append_size = len - skb->len; | |
3120 | ||
3121 | niu_rx_skb_append(skb, page, off, append_size); | |
3122 | if ((page->index + rp->rbr_block_size) - rcr_size == addr) { | |
3123 | *link = (struct page *) page->mapping; | |
3124 | np->ops->unmap_page(np->device, page->index, | |
3125 | PAGE_SIZE, DMA_FROM_DEVICE); | |
3126 | page->index = 0; | |
3127 | page->mapping = NULL; | |
3128 | rp->rbr_refill_pending++; | |
3129 | } else | |
3130 | get_page(page); | |
3131 | ||
3132 | index = NEXT_RCR(rp, index); | |
3133 | if (!(val & RCR_ENTRY_MULTI)) | |
3134 | break; | |
3135 | ||
3136 | } | |
3137 | rp->rcr_index = index; | |
3138 | ||
3139 | skb_reserve(skb, NET_IP_ALIGN); | |
3140 | __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX)); | |
3141 | ||
3142 | rp->rx_packets++; | |
3143 | rp->rx_bytes += skb->len; | |
3144 | ||
3145 | skb->protocol = eth_type_trans(skb, np->dev); | |
3146 | netif_receive_skb(skb); | |
3147 | ||
792dd90f DM |
3148 | np->dev->last_rx = jiffies; |
3149 | ||
a3138df9 DM |
3150 | return num_rcr; |
3151 | } | |
3152 | ||
3153 | static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) | |
3154 | { | |
3155 | int blocks_per_page = rp->rbr_blocks_per_page; | |
3156 | int err, index = rp->rbr_index; | |
3157 | ||
3158 | err = 0; | |
3159 | while (index < (rp->rbr_table_size - blocks_per_page)) { | |
3160 | err = niu_rbr_add_page(np, rp, mask, index); | |
3161 | if (err) | |
3162 | break; | |
3163 | ||
3164 | index += blocks_per_page; | |
3165 | } | |
3166 | ||
3167 | rp->rbr_index = index; | |
3168 | return err; | |
3169 | } | |
3170 | ||
3171 | static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp) | |
3172 | { | |
3173 | int i; | |
3174 | ||
3175 | for (i = 0; i < MAX_RBR_RING_SIZE; i++) { | |
3176 | struct page *page; | |
3177 | ||
3178 | page = rp->rxhash[i]; | |
3179 | while (page) { | |
3180 | struct page *next = (struct page *) page->mapping; | |
3181 | u64 base = page->index; | |
3182 | ||
3183 | np->ops->unmap_page(np->device, base, PAGE_SIZE, | |
3184 | DMA_FROM_DEVICE); | |
3185 | page->index = 0; | |
3186 | page->mapping = NULL; | |
3187 | ||
3188 | __free_page(page); | |
3189 | ||
3190 | page = next; | |
3191 | } | |
3192 | } | |
3193 | ||
3194 | for (i = 0; i < rp->rbr_table_size; i++) | |
3195 | rp->rbr[i] = cpu_to_le32(0); | |
3196 | rp->rbr_index = 0; | |
3197 | } | |
3198 | ||
3199 | static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx) | |
3200 | { | |
3201 | struct tx_buff_info *tb = &rp->tx_buffs[idx]; | |
3202 | struct sk_buff *skb = tb->skb; | |
3203 | struct tx_pkt_hdr *tp; | |
3204 | u64 tx_flags; | |
3205 | int i, len; | |
3206 | ||
3207 | tp = (struct tx_pkt_hdr *) skb->data; | |
3208 | tx_flags = le64_to_cpup(&tp->flags); | |
3209 | ||
3210 | rp->tx_packets++; | |
3211 | rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) - | |
3212 | ((tx_flags & TXHDR_PAD) / 2)); | |
3213 | ||
3214 | len = skb_headlen(skb); | |
3215 | np->ops->unmap_single(np->device, tb->mapping, | |
3216 | len, DMA_TO_DEVICE); | |
3217 | ||
3218 | if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK) | |
3219 | rp->mark_pending--; | |
3220 | ||
3221 | tb->skb = NULL; | |
3222 | do { | |
3223 | idx = NEXT_TX(rp, idx); | |
3224 | len -= MAX_TX_DESC_LEN; | |
3225 | } while (len > 0); | |
3226 | ||
3227 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
3228 | tb = &rp->tx_buffs[idx]; | |
3229 | BUG_ON(tb->skb != NULL); | |
3230 | np->ops->unmap_page(np->device, tb->mapping, | |
3231 | skb_shinfo(skb)->frags[i].size, | |
3232 | DMA_TO_DEVICE); | |
3233 | idx = NEXT_TX(rp, idx); | |
3234 | } | |
3235 | ||
3236 | dev_kfree_skb(skb); | |
3237 | ||
3238 | return idx; | |
3239 | } | |
3240 | ||
3241 | #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4) | |
3242 | ||
3243 | static void niu_tx_work(struct niu *np, struct tx_ring_info *rp) | |
3244 | { | |
3245 | u16 pkt_cnt, tmp; | |
3246 | int cons; | |
3247 | u64 cs; | |
3248 | ||
3249 | cs = rp->tx_cs; | |
3250 | if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK)))) | |
3251 | goto out; | |
3252 | ||
3253 | tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT; | |
3254 | pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) & | |
3255 | (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT); | |
3256 | ||
3257 | rp->last_pkt_cnt = tmp; | |
3258 | ||
3259 | cons = rp->cons; | |
3260 | ||
3261 | niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n", | |
3262 | np->dev->name, pkt_cnt, cons); | |
3263 | ||
3264 | while (pkt_cnt--) | |
3265 | cons = release_tx_packet(np, rp, cons); | |
3266 | ||
3267 | rp->cons = cons; | |
3268 | smp_mb(); | |
3269 | ||
3270 | out: | |
3271 | if (unlikely(netif_queue_stopped(np->dev) && | |
3272 | (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) { | |
3273 | netif_tx_lock(np->dev); | |
3274 | if (netif_queue_stopped(np->dev) && | |
3275 | (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))) | |
3276 | netif_wake_queue(np->dev); | |
3277 | netif_tx_unlock(np->dev); | |
3278 | } | |
3279 | } | |
3280 | ||
3281 | static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget) | |
3282 | { | |
3283 | int qlen, rcr_done = 0, work_done = 0; | |
3284 | struct rxdma_mailbox *mbox = rp->mbox; | |
3285 | u64 stat; | |
3286 | ||
3287 | #if 1 | |
3288 | stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); | |
3289 | qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN; | |
3290 | #else | |
3291 | stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); | |
3292 | qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN); | |
3293 | #endif | |
3294 | mbox->rx_dma_ctl_stat = 0; | |
3295 | mbox->rcrstat_a = 0; | |
3296 | ||
3297 | niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n", | |
3298 | np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen); | |
3299 | ||
3300 | rcr_done = work_done = 0; | |
3301 | qlen = min(qlen, budget); | |
3302 | while (work_done < qlen) { | |
3303 | rcr_done += niu_process_rx_pkt(np, rp); | |
3304 | work_done++; | |
3305 | } | |
3306 | ||
3307 | if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) { | |
3308 | unsigned int i; | |
3309 | ||
3310 | for (i = 0; i < rp->rbr_refill_pending; i++) | |
3311 | niu_rbr_refill(np, rp, GFP_ATOMIC); | |
3312 | rp->rbr_refill_pending = 0; | |
3313 | } | |
3314 | ||
3315 | stat = (RX_DMA_CTL_STAT_MEX | | |
3316 | ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) | | |
3317 | ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT)); | |
3318 | ||
3319 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat); | |
3320 | ||
3321 | return work_done; | |
3322 | } | |
3323 | ||
3324 | static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget) | |
3325 | { | |
3326 | u64 v0 = lp->v0; | |
3327 | u32 tx_vec = (v0 >> 32); | |
3328 | u32 rx_vec = (v0 & 0xffffffff); | |
3329 | int i, work_done = 0; | |
3330 | ||
3331 | niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n", | |
3332 | np->dev->name, (unsigned long long) v0); | |
3333 | ||
3334 | for (i = 0; i < np->num_tx_rings; i++) { | |
3335 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
3336 | if (tx_vec & (1 << rp->tx_channel)) | |
3337 | niu_tx_work(np, rp); | |
3338 | nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0); | |
3339 | } | |
3340 | ||
3341 | for (i = 0; i < np->num_rx_rings; i++) { | |
3342 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
3343 | ||
3344 | if (rx_vec & (1 << rp->rx_channel)) { | |
3345 | int this_work_done; | |
3346 | ||
3347 | this_work_done = niu_rx_work(np, rp, | |
3348 | budget); | |
3349 | ||
3350 | budget -= this_work_done; | |
3351 | work_done += this_work_done; | |
3352 | } | |
3353 | nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0); | |
3354 | } | |
3355 | ||
3356 | return work_done; | |
3357 | } | |
3358 | ||
3359 | static int niu_poll(struct napi_struct *napi, int budget) | |
3360 | { | |
3361 | struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi); | |
3362 | struct niu *np = lp->np; | |
3363 | int work_done; | |
3364 | ||
3365 | work_done = niu_poll_core(np, lp, budget); | |
3366 | ||
3367 | if (work_done < budget) { | |
3368 | netif_rx_complete(np->dev, napi); | |
3369 | niu_ldg_rearm(np, lp, 1); | |
3370 | } | |
3371 | return work_done; | |
3372 | } | |
3373 | ||
3374 | static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp, | |
3375 | u64 stat) | |
3376 | { | |
3377 | dev_err(np->device, PFX "%s: RX channel %u errors ( ", | |
3378 | np->dev->name, rp->rx_channel); | |
3379 | ||
3380 | if (stat & RX_DMA_CTL_STAT_RBR_TMOUT) | |
3381 | printk("RBR_TMOUT "); | |
3382 | if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR) | |
3383 | printk("RSP_CNT "); | |
3384 | if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS) | |
3385 | printk("BYTE_EN_BUS "); | |
3386 | if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR) | |
3387 | printk("RSP_DAT "); | |
3388 | if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR) | |
3389 | printk("RCR_ACK "); | |
3390 | if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR) | |
3391 | printk("RCR_SHA_PAR "); | |
3392 | if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR) | |
3393 | printk("RBR_PRE_PAR "); | |
3394 | if (stat & RX_DMA_CTL_STAT_CONFIG_ERR) | |
3395 | printk("CONFIG "); | |
3396 | if (stat & RX_DMA_CTL_STAT_RCRINCON) | |
3397 | printk("RCRINCON "); | |
3398 | if (stat & RX_DMA_CTL_STAT_RCRFULL) | |
3399 | printk("RCRFULL "); | |
3400 | if (stat & RX_DMA_CTL_STAT_RBRFULL) | |
3401 | printk("RBRFULL "); | |
3402 | if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE) | |
3403 | printk("RBRLOGPAGE "); | |
3404 | if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE) | |
3405 | printk("CFIGLOGPAGE "); | |
3406 | if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR) | |
3407 | printk("DC_FIDO "); | |
3408 | ||
3409 | printk(")\n"); | |
3410 | } | |
3411 | ||
3412 | static int niu_rx_error(struct niu *np, struct rx_ring_info *rp) | |
3413 | { | |
3414 | u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); | |
3415 | int err = 0; | |
3416 | ||
a3138df9 DM |
3417 | |
3418 | if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL | | |
3419 | RX_DMA_CTL_STAT_PORT_FATAL)) | |
3420 | err = -EINVAL; | |
3421 | ||
406f353c MW |
3422 | if (err) { |
3423 | dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n", | |
3424 | np->dev->name, rp->rx_channel, | |
3425 | (unsigned long long) stat); | |
3426 | ||
3427 | niu_log_rxchan_errors(np, rp, stat); | |
3428 | } | |
3429 | ||
a3138df9 DM |
3430 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), |
3431 | stat & RX_DMA_CTL_WRITE_CLEAR_ERRS); | |
3432 | ||
3433 | return err; | |
3434 | } | |
3435 | ||
3436 | static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp, | |
3437 | u64 cs) | |
3438 | { | |
3439 | dev_err(np->device, PFX "%s: TX channel %u errors ( ", | |
3440 | np->dev->name, rp->tx_channel); | |
3441 | ||
3442 | if (cs & TX_CS_MBOX_ERR) | |
3443 | printk("MBOX "); | |
3444 | if (cs & TX_CS_PKT_SIZE_ERR) | |
3445 | printk("PKT_SIZE "); | |
3446 | if (cs & TX_CS_TX_RING_OFLOW) | |
3447 | printk("TX_RING_OFLOW "); | |
3448 | if (cs & TX_CS_PREF_BUF_PAR_ERR) | |
3449 | printk("PREF_BUF_PAR "); | |
3450 | if (cs & TX_CS_NACK_PREF) | |
3451 | printk("NACK_PREF "); | |
3452 | if (cs & TX_CS_NACK_PKT_RD) | |
3453 | printk("NACK_PKT_RD "); | |
3454 | if (cs & TX_CS_CONF_PART_ERR) | |
3455 | printk("CONF_PART "); | |
3456 | if (cs & TX_CS_PKT_PRT_ERR) | |
3457 | printk("PKT_PTR "); | |
3458 | ||
3459 | printk(")\n"); | |
3460 | } | |
3461 | ||
3462 | static int niu_tx_error(struct niu *np, struct tx_ring_info *rp) | |
3463 | { | |
3464 | u64 cs, logh, logl; | |
3465 | ||
3466 | cs = nr64(TX_CS(rp->tx_channel)); | |
3467 | logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel)); | |
3468 | logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel)); | |
3469 | ||
3470 | dev_err(np->device, PFX "%s: TX channel %u error, " | |
3471 | "cs[%llx] logh[%llx] logl[%llx]\n", | |
3472 | np->dev->name, rp->tx_channel, | |
3473 | (unsigned long long) cs, | |
3474 | (unsigned long long) logh, | |
3475 | (unsigned long long) logl); | |
3476 | ||
3477 | niu_log_txchan_errors(np, rp, cs); | |
3478 | ||
3479 | return -ENODEV; | |
3480 | } | |
3481 | ||
3482 | static int niu_mif_interrupt(struct niu *np) | |
3483 | { | |
3484 | u64 mif_status = nr64(MIF_STATUS); | |
3485 | int phy_mdint = 0; | |
3486 | ||
3487 | if (np->flags & NIU_FLAGS_XMAC) { | |
3488 | u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS); | |
3489 | ||
3490 | if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT) | |
3491 | phy_mdint = 1; | |
3492 | } | |
3493 | ||
3494 | dev_err(np->device, PFX "%s: MIF interrupt, " | |
3495 | "stat[%llx] phy_mdint(%d)\n", | |
3496 | np->dev->name, (unsigned long long) mif_status, phy_mdint); | |
3497 | ||
3498 | return -ENODEV; | |
3499 | } | |
3500 | ||
3501 | static void niu_xmac_interrupt(struct niu *np) | |
3502 | { | |
3503 | struct niu_xmac_stats *mp = &np->mac_stats.xmac; | |
3504 | u64 val; | |
3505 | ||
3506 | val = nr64_mac(XTXMAC_STATUS); | |
3507 | if (val & XTXMAC_STATUS_FRAME_CNT_EXP) | |
3508 | mp->tx_frames += TXMAC_FRM_CNT_COUNT; | |
3509 | if (val & XTXMAC_STATUS_BYTE_CNT_EXP) | |
3510 | mp->tx_bytes += TXMAC_BYTE_CNT_COUNT; | |
3511 | if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR) | |
3512 | mp->tx_fifo_errors++; | |
3513 | if (val & XTXMAC_STATUS_TXMAC_OFLOW) | |
3514 | mp->tx_overflow_errors++; | |
3515 | if (val & XTXMAC_STATUS_MAX_PSIZE_ERR) | |
3516 | mp->tx_max_pkt_size_errors++; | |
3517 | if (val & XTXMAC_STATUS_TXMAC_UFLOW) | |
3518 | mp->tx_underflow_errors++; | |
3519 | ||
3520 | val = nr64_mac(XRXMAC_STATUS); | |
3521 | if (val & XRXMAC_STATUS_LCL_FLT_STATUS) | |
3522 | mp->rx_local_faults++; | |
3523 | if (val & XRXMAC_STATUS_RFLT_DET) | |
3524 | mp->rx_remote_faults++; | |
3525 | if (val & XRXMAC_STATUS_LFLT_CNT_EXP) | |
3526 | mp->rx_link_faults += LINK_FAULT_CNT_COUNT; | |
3527 | if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP) | |
3528 | mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT; | |
3529 | if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP) | |
3530 | mp->rx_frags += RXMAC_FRAG_CNT_COUNT; | |
3531 | if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP) | |
3532 | mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT; | |
3533 | if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) | |
3534 | mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; | |
3535 | if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) | |
3536 | mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; | |
3537 | if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP) | |
3538 | mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT; | |
3539 | if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP) | |
3540 | mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT; | |
3541 | if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP) | |
3542 | mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT; | |
3543 | if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP) | |
3544 | mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT; | |
3545 | if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP) | |
3546 | mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT; | |
3547 | if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP) | |
3548 | mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT; | |
3549 | if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP) | |
3550 | mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT; | |
3551 | if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP) | |
3552 | mp->rx_octets += RXMAC_BT_CNT_COUNT; | |
3553 | if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP) | |
3554 | mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT; | |
3555 | if (val & XRXMAC_STATUS_LENERR_CNT_EXP) | |
3556 | mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT; | |
3557 | if (val & XRXMAC_STATUS_CRCERR_CNT_EXP) | |
3558 | mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT; | |
3559 | if (val & XRXMAC_STATUS_RXUFLOW) | |
3560 | mp->rx_underflows++; | |
3561 | if (val & XRXMAC_STATUS_RXOFLOW) | |
3562 | mp->rx_overflows++; | |
3563 | ||
3564 | val = nr64_mac(XMAC_FC_STAT); | |
3565 | if (val & XMAC_FC_STAT_TX_MAC_NPAUSE) | |
3566 | mp->pause_off_state++; | |
3567 | if (val & XMAC_FC_STAT_TX_MAC_PAUSE) | |
3568 | mp->pause_on_state++; | |
3569 | if (val & XMAC_FC_STAT_RX_MAC_RPAUSE) | |
3570 | mp->pause_received++; | |
3571 | } | |
3572 | ||
3573 | static void niu_bmac_interrupt(struct niu *np) | |
3574 | { | |
3575 | struct niu_bmac_stats *mp = &np->mac_stats.bmac; | |
3576 | u64 val; | |
3577 | ||
3578 | val = nr64_mac(BTXMAC_STATUS); | |
3579 | if (val & BTXMAC_STATUS_UNDERRUN) | |
3580 | mp->tx_underflow_errors++; | |
3581 | if (val & BTXMAC_STATUS_MAX_PKT_ERR) | |
3582 | mp->tx_max_pkt_size_errors++; | |
3583 | if (val & BTXMAC_STATUS_BYTE_CNT_EXP) | |
3584 | mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT; | |
3585 | if (val & BTXMAC_STATUS_FRAME_CNT_EXP) | |
3586 | mp->tx_frames += BTXMAC_FRM_CNT_COUNT; | |
3587 | ||
3588 | val = nr64_mac(BRXMAC_STATUS); | |
3589 | if (val & BRXMAC_STATUS_OVERFLOW) | |
3590 | mp->rx_overflows++; | |
3591 | if (val & BRXMAC_STATUS_FRAME_CNT_EXP) | |
3592 | mp->rx_frames += BRXMAC_FRAME_CNT_COUNT; | |
3593 | if (val & BRXMAC_STATUS_ALIGN_ERR_EXP) | |
3594 | mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; | |
3595 | if (val & BRXMAC_STATUS_CRC_ERR_EXP) | |
3596 | mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; | |
3597 | if (val & BRXMAC_STATUS_LEN_ERR_EXP) | |
3598 | mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT; | |
3599 | ||
3600 | val = nr64_mac(BMAC_CTRL_STATUS); | |
3601 | if (val & BMAC_CTRL_STATUS_NOPAUSE) | |
3602 | mp->pause_off_state++; | |
3603 | if (val & BMAC_CTRL_STATUS_PAUSE) | |
3604 | mp->pause_on_state++; | |
3605 | if (val & BMAC_CTRL_STATUS_PAUSE_RECV) | |
3606 | mp->pause_received++; | |
3607 | } | |
3608 | ||
3609 | static int niu_mac_interrupt(struct niu *np) | |
3610 | { | |
3611 | if (np->flags & NIU_FLAGS_XMAC) | |
3612 | niu_xmac_interrupt(np); | |
3613 | else | |
3614 | niu_bmac_interrupt(np); | |
3615 | ||
3616 | return 0; | |
3617 | } | |
3618 | ||
3619 | static void niu_log_device_error(struct niu *np, u64 stat) | |
3620 | { | |
3621 | dev_err(np->device, PFX "%s: Core device errors ( ", | |
3622 | np->dev->name); | |
3623 | ||
3624 | if (stat & SYS_ERR_MASK_META2) | |
3625 | printk("META2 "); | |
3626 | if (stat & SYS_ERR_MASK_META1) | |
3627 | printk("META1 "); | |
3628 | if (stat & SYS_ERR_MASK_PEU) | |
3629 | printk("PEU "); | |
3630 | if (stat & SYS_ERR_MASK_TXC) | |
3631 | printk("TXC "); | |
3632 | if (stat & SYS_ERR_MASK_RDMC) | |
3633 | printk("RDMC "); | |
3634 | if (stat & SYS_ERR_MASK_TDMC) | |
3635 | printk("TDMC "); | |
3636 | if (stat & SYS_ERR_MASK_ZCP) | |
3637 | printk("ZCP "); | |
3638 | if (stat & SYS_ERR_MASK_FFLP) | |
3639 | printk("FFLP "); | |
3640 | if (stat & SYS_ERR_MASK_IPP) | |
3641 | printk("IPP "); | |
3642 | if (stat & SYS_ERR_MASK_MAC) | |
3643 | printk("MAC "); | |
3644 | if (stat & SYS_ERR_MASK_SMX) | |
3645 | printk("SMX "); | |
3646 | ||
3647 | printk(")\n"); | |
3648 | } | |
3649 | ||
3650 | static int niu_device_error(struct niu *np) | |
3651 | { | |
3652 | u64 stat = nr64(SYS_ERR_STAT); | |
3653 | ||
3654 | dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n", | |
3655 | np->dev->name, (unsigned long long) stat); | |
3656 | ||
3657 | niu_log_device_error(np, stat); | |
3658 | ||
3659 | return -ENODEV; | |
3660 | } | |
3661 | ||
406f353c MW |
3662 | static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp, |
3663 | u64 v0, u64 v1, u64 v2) | |
a3138df9 | 3664 | { |
406f353c | 3665 | |
a3138df9 DM |
3666 | int i, err = 0; |
3667 | ||
406f353c MW |
3668 | lp->v0 = v0; |
3669 | lp->v1 = v1; | |
3670 | lp->v2 = v2; | |
3671 | ||
a3138df9 DM |
3672 | if (v1 & 0x00000000ffffffffULL) { |
3673 | u32 rx_vec = (v1 & 0xffffffff); | |
3674 | ||
3675 | for (i = 0; i < np->num_rx_rings; i++) { | |
3676 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
3677 | ||
3678 | if (rx_vec & (1 << rp->rx_channel)) { | |
3679 | int r = niu_rx_error(np, rp); | |
406f353c | 3680 | if (r) { |
a3138df9 | 3681 | err = r; |
406f353c MW |
3682 | } else { |
3683 | if (!v0) | |
3684 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), | |
3685 | RX_DMA_CTL_STAT_MEX); | |
3686 | } | |
a3138df9 DM |
3687 | } |
3688 | } | |
3689 | } | |
3690 | if (v1 & 0x7fffffff00000000ULL) { | |
3691 | u32 tx_vec = (v1 >> 32) & 0x7fffffff; | |
3692 | ||
3693 | for (i = 0; i < np->num_tx_rings; i++) { | |
3694 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
3695 | ||
3696 | if (tx_vec & (1 << rp->tx_channel)) { | |
3697 | int r = niu_tx_error(np, rp); | |
3698 | if (r) | |
3699 | err = r; | |
3700 | } | |
3701 | } | |
3702 | } | |
3703 | if ((v0 | v1) & 0x8000000000000000ULL) { | |
3704 | int r = niu_mif_interrupt(np); | |
3705 | if (r) | |
3706 | err = r; | |
3707 | } | |
3708 | if (v2) { | |
3709 | if (v2 & 0x01ef) { | |
3710 | int r = niu_mac_interrupt(np); | |
3711 | if (r) | |
3712 | err = r; | |
3713 | } | |
3714 | if (v2 & 0x0210) { | |
3715 | int r = niu_device_error(np); | |
3716 | if (r) | |
3717 | err = r; | |
3718 | } | |
3719 | } | |
3720 | ||
3721 | if (err) | |
3722 | niu_enable_interrupts(np, 0); | |
3723 | ||
406f353c | 3724 | return err; |
a3138df9 DM |
3725 | } |
3726 | ||
3727 | static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp, | |
3728 | int ldn) | |
3729 | { | |
3730 | struct rxdma_mailbox *mbox = rp->mbox; | |
3731 | u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); | |
3732 | ||
3733 | stat_write = (RX_DMA_CTL_STAT_RCRTHRES | | |
3734 | RX_DMA_CTL_STAT_RCRTO); | |
3735 | nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write); | |
3736 | ||
3737 | niudbg(INTR, "%s: rxchan_intr stat[%llx]\n", | |
3738 | np->dev->name, (unsigned long long) stat); | |
3739 | } | |
3740 | ||
3741 | static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp, | |
3742 | int ldn) | |
3743 | { | |
3744 | rp->tx_cs = nr64(TX_CS(rp->tx_channel)); | |
3745 | ||
3746 | niudbg(INTR, "%s: txchan_intr cs[%llx]\n", | |
3747 | np->dev->name, (unsigned long long) rp->tx_cs); | |
3748 | } | |
3749 | ||
3750 | static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0) | |
3751 | { | |
3752 | struct niu_parent *parent = np->parent; | |
3753 | u32 rx_vec, tx_vec; | |
3754 | int i; | |
3755 | ||
3756 | tx_vec = (v0 >> 32); | |
3757 | rx_vec = (v0 & 0xffffffff); | |
3758 | ||
3759 | for (i = 0; i < np->num_rx_rings; i++) { | |
3760 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
3761 | int ldn = LDN_RXDMA(rp->rx_channel); | |
3762 | ||
3763 | if (parent->ldg_map[ldn] != ldg) | |
3764 | continue; | |
3765 | ||
3766 | nw64(LD_IM0(ldn), LD_IM0_MASK); | |
3767 | if (rx_vec & (1 << rp->rx_channel)) | |
3768 | niu_rxchan_intr(np, rp, ldn); | |
3769 | } | |
3770 | ||
3771 | for (i = 0; i < np->num_tx_rings; i++) { | |
3772 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
3773 | int ldn = LDN_TXDMA(rp->tx_channel); | |
3774 | ||
3775 | if (parent->ldg_map[ldn] != ldg) | |
3776 | continue; | |
3777 | ||
3778 | nw64(LD_IM0(ldn), LD_IM0_MASK); | |
3779 | if (tx_vec & (1 << rp->tx_channel)) | |
3780 | niu_txchan_intr(np, rp, ldn); | |
3781 | } | |
3782 | } | |
3783 | ||
3784 | static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp, | |
3785 | u64 v0, u64 v1, u64 v2) | |
3786 | { | |
3787 | if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) { | |
3788 | lp->v0 = v0; | |
3789 | lp->v1 = v1; | |
3790 | lp->v2 = v2; | |
3791 | __niu_fastpath_interrupt(np, lp->ldg_num, v0); | |
3792 | __netif_rx_schedule(np->dev, &lp->napi); | |
3793 | } | |
3794 | } | |
3795 | ||
3796 | static irqreturn_t niu_interrupt(int irq, void *dev_id) | |
3797 | { | |
3798 | struct niu_ldg *lp = dev_id; | |
3799 | struct niu *np = lp->np; | |
3800 | int ldg = lp->ldg_num; | |
3801 | unsigned long flags; | |
3802 | u64 v0, v1, v2; | |
3803 | ||
3804 | if (netif_msg_intr(np)) | |
3805 | printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ", | |
3806 | lp, ldg); | |
3807 | ||
3808 | spin_lock_irqsave(&np->lock, flags); | |
3809 | ||
3810 | v0 = nr64(LDSV0(ldg)); | |
3811 | v1 = nr64(LDSV1(ldg)); | |
3812 | v2 = nr64(LDSV2(ldg)); | |
3813 | ||
3814 | if (netif_msg_intr(np)) | |
3815 | printk("v0[%llx] v1[%llx] v2[%llx]\n", | |
3816 | (unsigned long long) v0, | |
3817 | (unsigned long long) v1, | |
3818 | (unsigned long long) v2); | |
3819 | ||
3820 | if (unlikely(!v0 && !v1 && !v2)) { | |
3821 | spin_unlock_irqrestore(&np->lock, flags); | |
3822 | return IRQ_NONE; | |
3823 | } | |
3824 | ||
3825 | if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) { | |
406f353c | 3826 | int err = niu_slowpath_interrupt(np, lp, v0, v1, v2); |
a3138df9 DM |
3827 | if (err) |
3828 | goto out; | |
3829 | } | |
3830 | if (likely(v0 & ~((u64)1 << LDN_MIF))) | |
3831 | niu_schedule_napi(np, lp, v0, v1, v2); | |
3832 | else | |
3833 | niu_ldg_rearm(np, lp, 1); | |
3834 | out: | |
3835 | spin_unlock_irqrestore(&np->lock, flags); | |
3836 | ||
3837 | return IRQ_HANDLED; | |
3838 | } | |
3839 | ||
3840 | static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp) | |
3841 | { | |
3842 | if (rp->mbox) { | |
3843 | np->ops->free_coherent(np->device, | |
3844 | sizeof(struct rxdma_mailbox), | |
3845 | rp->mbox, rp->mbox_dma); | |
3846 | rp->mbox = NULL; | |
3847 | } | |
3848 | if (rp->rcr) { | |
3849 | np->ops->free_coherent(np->device, | |
3850 | MAX_RCR_RING_SIZE * sizeof(__le64), | |
3851 | rp->rcr, rp->rcr_dma); | |
3852 | rp->rcr = NULL; | |
3853 | rp->rcr_table_size = 0; | |
3854 | rp->rcr_index = 0; | |
3855 | } | |
3856 | if (rp->rbr) { | |
3857 | niu_rbr_free(np, rp); | |
3858 | ||
3859 | np->ops->free_coherent(np->device, | |
3860 | MAX_RBR_RING_SIZE * sizeof(__le32), | |
3861 | rp->rbr, rp->rbr_dma); | |
3862 | rp->rbr = NULL; | |
3863 | rp->rbr_table_size = 0; | |
3864 | rp->rbr_index = 0; | |
3865 | } | |
3866 | kfree(rp->rxhash); | |
3867 | rp->rxhash = NULL; | |
3868 | } | |
3869 | ||
3870 | static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp) | |
3871 | { | |
3872 | if (rp->mbox) { | |
3873 | np->ops->free_coherent(np->device, | |
3874 | sizeof(struct txdma_mailbox), | |
3875 | rp->mbox, rp->mbox_dma); | |
3876 | rp->mbox = NULL; | |
3877 | } | |
3878 | if (rp->descr) { | |
3879 | int i; | |
3880 | ||
3881 | for (i = 0; i < MAX_TX_RING_SIZE; i++) { | |
3882 | if (rp->tx_buffs[i].skb) | |
3883 | (void) release_tx_packet(np, rp, i); | |
3884 | } | |
3885 | ||
3886 | np->ops->free_coherent(np->device, | |
3887 | MAX_TX_RING_SIZE * sizeof(__le64), | |
3888 | rp->descr, rp->descr_dma); | |
3889 | rp->descr = NULL; | |
3890 | rp->pending = 0; | |
3891 | rp->prod = 0; | |
3892 | rp->cons = 0; | |
3893 | rp->wrap_bit = 0; | |
3894 | } | |
3895 | } | |
3896 | ||
3897 | static void niu_free_channels(struct niu *np) | |
3898 | { | |
3899 | int i; | |
3900 | ||
3901 | if (np->rx_rings) { | |
3902 | for (i = 0; i < np->num_rx_rings; i++) { | |
3903 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
3904 | ||
3905 | niu_free_rx_ring_info(np, rp); | |
3906 | } | |
3907 | kfree(np->rx_rings); | |
3908 | np->rx_rings = NULL; | |
3909 | np->num_rx_rings = 0; | |
3910 | } | |
3911 | ||
3912 | if (np->tx_rings) { | |
3913 | for (i = 0; i < np->num_tx_rings; i++) { | |
3914 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
3915 | ||
3916 | niu_free_tx_ring_info(np, rp); | |
3917 | } | |
3918 | kfree(np->tx_rings); | |
3919 | np->tx_rings = NULL; | |
3920 | np->num_tx_rings = 0; | |
3921 | } | |
3922 | } | |
3923 | ||
3924 | static int niu_alloc_rx_ring_info(struct niu *np, | |
3925 | struct rx_ring_info *rp) | |
3926 | { | |
3927 | BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64); | |
3928 | ||
3929 | rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *), | |
3930 | GFP_KERNEL); | |
3931 | if (!rp->rxhash) | |
3932 | return -ENOMEM; | |
3933 | ||
3934 | rp->mbox = np->ops->alloc_coherent(np->device, | |
3935 | sizeof(struct rxdma_mailbox), | |
3936 | &rp->mbox_dma, GFP_KERNEL); | |
3937 | if (!rp->mbox) | |
3938 | return -ENOMEM; | |
3939 | if ((unsigned long)rp->mbox & (64UL - 1)) { | |
3940 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " | |
3941 | "RXDMA mailbox %p\n", np->dev->name, rp->mbox); | |
3942 | return -EINVAL; | |
3943 | } | |
3944 | ||
3945 | rp->rcr = np->ops->alloc_coherent(np->device, | |
3946 | MAX_RCR_RING_SIZE * sizeof(__le64), | |
3947 | &rp->rcr_dma, GFP_KERNEL); | |
3948 | if (!rp->rcr) | |
3949 | return -ENOMEM; | |
3950 | if ((unsigned long)rp->rcr & (64UL - 1)) { | |
3951 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " | |
3952 | "RXDMA RCR table %p\n", np->dev->name, rp->rcr); | |
3953 | return -EINVAL; | |
3954 | } | |
3955 | rp->rcr_table_size = MAX_RCR_RING_SIZE; | |
3956 | rp->rcr_index = 0; | |
3957 | ||
3958 | rp->rbr = np->ops->alloc_coherent(np->device, | |
3959 | MAX_RBR_RING_SIZE * sizeof(__le32), | |
3960 | &rp->rbr_dma, GFP_KERNEL); | |
3961 | if (!rp->rbr) | |
3962 | return -ENOMEM; | |
3963 | if ((unsigned long)rp->rbr & (64UL - 1)) { | |
3964 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " | |
3965 | "RXDMA RBR table %p\n", np->dev->name, rp->rbr); | |
3966 | return -EINVAL; | |
3967 | } | |
3968 | rp->rbr_table_size = MAX_RBR_RING_SIZE; | |
3969 | rp->rbr_index = 0; | |
3970 | rp->rbr_pending = 0; | |
3971 | ||
3972 | return 0; | |
3973 | } | |
3974 | ||
3975 | static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp) | |
3976 | { | |
3977 | int mtu = np->dev->mtu; | |
3978 | ||
3979 | /* These values are recommended by the HW designers for fair | |
3980 | * utilization of DRR amongst the rings. | |
3981 | */ | |
3982 | rp->max_burst = mtu + 32; | |
3983 | if (rp->max_burst > 4096) | |
3984 | rp->max_burst = 4096; | |
3985 | } | |
3986 | ||
3987 | static int niu_alloc_tx_ring_info(struct niu *np, | |
3988 | struct tx_ring_info *rp) | |
3989 | { | |
3990 | BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64); | |
3991 | ||
3992 | rp->mbox = np->ops->alloc_coherent(np->device, | |
3993 | sizeof(struct txdma_mailbox), | |
3994 | &rp->mbox_dma, GFP_KERNEL); | |
3995 | if (!rp->mbox) | |
3996 | return -ENOMEM; | |
3997 | if ((unsigned long)rp->mbox & (64UL - 1)) { | |
3998 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " | |
3999 | "TXDMA mailbox %p\n", np->dev->name, rp->mbox); | |
4000 | return -EINVAL; | |
4001 | } | |
4002 | ||
4003 | rp->descr = np->ops->alloc_coherent(np->device, | |
4004 | MAX_TX_RING_SIZE * sizeof(__le64), | |
4005 | &rp->descr_dma, GFP_KERNEL); | |
4006 | if (!rp->descr) | |
4007 | return -ENOMEM; | |
4008 | if ((unsigned long)rp->descr & (64UL - 1)) { | |
4009 | dev_err(np->device, PFX "%s: Coherent alloc gives misaligned " | |
4010 | "TXDMA descr table %p\n", np->dev->name, rp->descr); | |
4011 | return -EINVAL; | |
4012 | } | |
4013 | ||
4014 | rp->pending = MAX_TX_RING_SIZE; | |
4015 | rp->prod = 0; | |
4016 | rp->cons = 0; | |
4017 | rp->wrap_bit = 0; | |
4018 | ||
4019 | /* XXX make these configurable... XXX */ | |
4020 | rp->mark_freq = rp->pending / 4; | |
4021 | ||
4022 | niu_set_max_burst(np, rp); | |
4023 | ||
4024 | return 0; | |
4025 | } | |
4026 | ||
4027 | static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp) | |
4028 | { | |
81429973 | 4029 | u16 bss; |
a3138df9 | 4030 | |
81429973 | 4031 | bss = min(PAGE_SHIFT, 15); |
a3138df9 | 4032 | |
81429973 OJ |
4033 | rp->rbr_block_size = 1 << bss; |
4034 | rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss); | |
a3138df9 DM |
4035 | |
4036 | rp->rbr_sizes[0] = 256; | |
4037 | rp->rbr_sizes[1] = 1024; | |
4038 | if (np->dev->mtu > ETH_DATA_LEN) { | |
4039 | switch (PAGE_SIZE) { | |
4040 | case 4 * 1024: | |
4041 | rp->rbr_sizes[2] = 4096; | |
4042 | break; | |
4043 | ||
4044 | default: | |
4045 | rp->rbr_sizes[2] = 8192; | |
4046 | break; | |
4047 | } | |
4048 | } else { | |
4049 | rp->rbr_sizes[2] = 2048; | |
4050 | } | |
4051 | rp->rbr_sizes[3] = rp->rbr_block_size; | |
4052 | } | |
4053 | ||
4054 | static int niu_alloc_channels(struct niu *np) | |
4055 | { | |
4056 | struct niu_parent *parent = np->parent; | |
4057 | int first_rx_channel, first_tx_channel; | |
4058 | int i, port, err; | |
4059 | ||
4060 | port = np->port; | |
4061 | first_rx_channel = first_tx_channel = 0; | |
4062 | for (i = 0; i < port; i++) { | |
4063 | first_rx_channel += parent->rxchan_per_port[i]; | |
4064 | first_tx_channel += parent->txchan_per_port[i]; | |
4065 | } | |
4066 | ||
4067 | np->num_rx_rings = parent->rxchan_per_port[port]; | |
4068 | np->num_tx_rings = parent->txchan_per_port[port]; | |
4069 | ||
4070 | np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info), | |
4071 | GFP_KERNEL); | |
4072 | err = -ENOMEM; | |
4073 | if (!np->rx_rings) | |
4074 | goto out_err; | |
4075 | ||
4076 | for (i = 0; i < np->num_rx_rings; i++) { | |
4077 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
4078 | ||
4079 | rp->np = np; | |
4080 | rp->rx_channel = first_rx_channel + i; | |
4081 | ||
4082 | err = niu_alloc_rx_ring_info(np, rp); | |
4083 | if (err) | |
4084 | goto out_err; | |
4085 | ||
4086 | niu_size_rbr(np, rp); | |
4087 | ||
4088 | /* XXX better defaults, configurable, etc... XXX */ | |
4089 | rp->nonsyn_window = 64; | |
4090 | rp->nonsyn_threshold = rp->rcr_table_size - 64; | |
4091 | rp->syn_window = 64; | |
4092 | rp->syn_threshold = rp->rcr_table_size - 64; | |
4093 | rp->rcr_pkt_threshold = 16; | |
4094 | rp->rcr_timeout = 8; | |
4095 | rp->rbr_kick_thresh = RBR_REFILL_MIN; | |
4096 | if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page) | |
4097 | rp->rbr_kick_thresh = rp->rbr_blocks_per_page; | |
4098 | ||
4099 | err = niu_rbr_fill(np, rp, GFP_KERNEL); | |
4100 | if (err) | |
4101 | return err; | |
4102 | } | |
4103 | ||
4104 | np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info), | |
4105 | GFP_KERNEL); | |
4106 | err = -ENOMEM; | |
4107 | if (!np->tx_rings) | |
4108 | goto out_err; | |
4109 | ||
4110 | for (i = 0; i < np->num_tx_rings; i++) { | |
4111 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
4112 | ||
4113 | rp->np = np; | |
4114 | rp->tx_channel = first_tx_channel + i; | |
4115 | ||
4116 | err = niu_alloc_tx_ring_info(np, rp); | |
4117 | if (err) | |
4118 | goto out_err; | |
4119 | } | |
4120 | ||
4121 | return 0; | |
4122 | ||
4123 | out_err: | |
4124 | niu_free_channels(np); | |
4125 | return err; | |
4126 | } | |
4127 | ||
4128 | static int niu_tx_cs_sng_poll(struct niu *np, int channel) | |
4129 | { | |
4130 | int limit = 1000; | |
4131 | ||
4132 | while (--limit > 0) { | |
4133 | u64 val = nr64(TX_CS(channel)); | |
4134 | if (val & TX_CS_SNG_STATE) | |
4135 | return 0; | |
4136 | } | |
4137 | return -ENODEV; | |
4138 | } | |
4139 | ||
4140 | static int niu_tx_channel_stop(struct niu *np, int channel) | |
4141 | { | |
4142 | u64 val = nr64(TX_CS(channel)); | |
4143 | ||
4144 | val |= TX_CS_STOP_N_GO; | |
4145 | nw64(TX_CS(channel), val); | |
4146 | ||
4147 | return niu_tx_cs_sng_poll(np, channel); | |
4148 | } | |
4149 | ||
4150 | static int niu_tx_cs_reset_poll(struct niu *np, int channel) | |
4151 | { | |
4152 | int limit = 1000; | |
4153 | ||
4154 | while (--limit > 0) { | |
4155 | u64 val = nr64(TX_CS(channel)); | |
4156 | if (!(val & TX_CS_RST)) | |
4157 | return 0; | |
4158 | } | |
4159 | return -ENODEV; | |
4160 | } | |
4161 | ||
4162 | static int niu_tx_channel_reset(struct niu *np, int channel) | |
4163 | { | |
4164 | u64 val = nr64(TX_CS(channel)); | |
4165 | int err; | |
4166 | ||
4167 | val |= TX_CS_RST; | |
4168 | nw64(TX_CS(channel), val); | |
4169 | ||
4170 | err = niu_tx_cs_reset_poll(np, channel); | |
4171 | if (!err) | |
4172 | nw64(TX_RING_KICK(channel), 0); | |
4173 | ||
4174 | return err; | |
4175 | } | |
4176 | ||
4177 | static int niu_tx_channel_lpage_init(struct niu *np, int channel) | |
4178 | { | |
4179 | u64 val; | |
4180 | ||
4181 | nw64(TX_LOG_MASK1(channel), 0); | |
4182 | nw64(TX_LOG_VAL1(channel), 0); | |
4183 | nw64(TX_LOG_MASK2(channel), 0); | |
4184 | nw64(TX_LOG_VAL2(channel), 0); | |
4185 | nw64(TX_LOG_PAGE_RELO1(channel), 0); | |
4186 | nw64(TX_LOG_PAGE_RELO2(channel), 0); | |
4187 | nw64(TX_LOG_PAGE_HDL(channel), 0); | |
4188 | ||
4189 | val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT; | |
4190 | val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1); | |
4191 | nw64(TX_LOG_PAGE_VLD(channel), val); | |
4192 | ||
4193 | /* XXX TXDMA 32bit mode? XXX */ | |
4194 | ||
4195 | return 0; | |
4196 | } | |
4197 | ||
4198 | static void niu_txc_enable_port(struct niu *np, int on) | |
4199 | { | |
4200 | unsigned long flags; | |
4201 | u64 val, mask; | |
4202 | ||
4203 | niu_lock_parent(np, flags); | |
4204 | val = nr64(TXC_CONTROL); | |
4205 | mask = (u64)1 << np->port; | |
4206 | if (on) { | |
4207 | val |= TXC_CONTROL_ENABLE | mask; | |
4208 | } else { | |
4209 | val &= ~mask; | |
4210 | if ((val & ~TXC_CONTROL_ENABLE) == 0) | |
4211 | val &= ~TXC_CONTROL_ENABLE; | |
4212 | } | |
4213 | nw64(TXC_CONTROL, val); | |
4214 | niu_unlock_parent(np, flags); | |
4215 | } | |
4216 | ||
4217 | static void niu_txc_set_imask(struct niu *np, u64 imask) | |
4218 | { | |
4219 | unsigned long flags; | |
4220 | u64 val; | |
4221 | ||
4222 | niu_lock_parent(np, flags); | |
4223 | val = nr64(TXC_INT_MASK); | |
4224 | val &= ~TXC_INT_MASK_VAL(np->port); | |
4225 | val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port)); | |
4226 | niu_unlock_parent(np, flags); | |
4227 | } | |
4228 | ||
4229 | static void niu_txc_port_dma_enable(struct niu *np, int on) | |
4230 | { | |
4231 | u64 val = 0; | |
4232 | ||
4233 | if (on) { | |
4234 | int i; | |
4235 | ||
4236 | for (i = 0; i < np->num_tx_rings; i++) | |
4237 | val |= (1 << np->tx_rings[i].tx_channel); | |
4238 | } | |
4239 | nw64(TXC_PORT_DMA(np->port), val); | |
4240 | } | |
4241 | ||
4242 | static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp) | |
4243 | { | |
4244 | int err, channel = rp->tx_channel; | |
4245 | u64 val, ring_len; | |
4246 | ||
4247 | err = niu_tx_channel_stop(np, channel); | |
4248 | if (err) | |
4249 | return err; | |
4250 | ||
4251 | err = niu_tx_channel_reset(np, channel); | |
4252 | if (err) | |
4253 | return err; | |
4254 | ||
4255 | err = niu_tx_channel_lpage_init(np, channel); | |
4256 | if (err) | |
4257 | return err; | |
4258 | ||
4259 | nw64(TXC_DMA_MAX(channel), rp->max_burst); | |
4260 | nw64(TX_ENT_MSK(channel), 0); | |
4261 | ||
4262 | if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE | | |
4263 | TX_RNG_CFIG_STADDR)) { | |
4264 | dev_err(np->device, PFX "%s: TX ring channel %d " | |
4265 | "DMA addr (%llx) is not aligned.\n", | |
4266 | np->dev->name, channel, | |
4267 | (unsigned long long) rp->descr_dma); | |
4268 | return -EINVAL; | |
4269 | } | |
4270 | ||
4271 | /* The length field in TX_RNG_CFIG is measured in 64-byte | |
4272 | * blocks. rp->pending is the number of TX descriptors in | |
4273 | * our ring, 8 bytes each, thus we divide by 8 bytes more | |
4274 | * to get the proper value the chip wants. | |
4275 | */ | |
4276 | ring_len = (rp->pending / 8); | |
4277 | ||
4278 | val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) | | |
4279 | rp->descr_dma); | |
4280 | nw64(TX_RNG_CFIG(channel), val); | |
4281 | ||
4282 | if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) || | |
4283 | ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) { | |
4284 | dev_err(np->device, PFX "%s: TX ring channel %d " | |
4285 | "MBOX addr (%llx) is has illegal bits.\n", | |
4286 | np->dev->name, channel, | |
4287 | (unsigned long long) rp->mbox_dma); | |
4288 | return -EINVAL; | |
4289 | } | |
4290 | nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32); | |
4291 | nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR); | |
4292 | ||
4293 | nw64(TX_CS(channel), 0); | |
4294 | ||
4295 | rp->last_pkt_cnt = 0; | |
4296 | ||
4297 | return 0; | |
4298 | } | |
4299 | ||
4300 | static void niu_init_rdc_groups(struct niu *np) | |
4301 | { | |
4302 | struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port]; | |
4303 | int i, first_table_num = tp->first_table_num; | |
4304 | ||
4305 | for (i = 0; i < tp->num_tables; i++) { | |
4306 | struct rdc_table *tbl = &tp->tables[i]; | |
4307 | int this_table = first_table_num + i; | |
4308 | int slot; | |
4309 | ||
4310 | for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) | |
4311 | nw64(RDC_TBL(this_table, slot), | |
4312 | tbl->rxdma_channel[slot]); | |
4313 | } | |
4314 | ||
4315 | nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]); | |
4316 | } | |
4317 | ||
4318 | static void niu_init_drr_weight(struct niu *np) | |
4319 | { | |
4320 | int type = phy_decode(np->parent->port_phy, np->port); | |
4321 | u64 val; | |
4322 | ||
4323 | switch (type) { | |
4324 | case PORT_TYPE_10G: | |
4325 | val = PT_DRR_WEIGHT_DEFAULT_10G; | |
4326 | break; | |
4327 | ||
4328 | case PORT_TYPE_1G: | |
4329 | default: | |
4330 | val = PT_DRR_WEIGHT_DEFAULT_1G; | |
4331 | break; | |
4332 | } | |
4333 | nw64(PT_DRR_WT(np->port), val); | |
4334 | } | |
4335 | ||
4336 | static int niu_init_hostinfo(struct niu *np) | |
4337 | { | |
4338 | struct niu_parent *parent = np->parent; | |
4339 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; | |
4340 | int i, err, num_alt = niu_num_alt_addr(np); | |
4341 | int first_rdc_table = tp->first_table_num; | |
4342 | ||
4343 | err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); | |
4344 | if (err) | |
4345 | return err; | |
4346 | ||
4347 | err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); | |
4348 | if (err) | |
4349 | return err; | |
4350 | ||
4351 | for (i = 0; i < num_alt; i++) { | |
4352 | err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1); | |
4353 | if (err) | |
4354 | return err; | |
4355 | } | |
4356 | ||
4357 | return 0; | |
4358 | } | |
4359 | ||
4360 | static int niu_rx_channel_reset(struct niu *np, int channel) | |
4361 | { | |
4362 | return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel), | |
4363 | RXDMA_CFIG1_RST, 1000, 10, | |
4364 | "RXDMA_CFIG1"); | |
4365 | } | |
4366 | ||
4367 | static int niu_rx_channel_lpage_init(struct niu *np, int channel) | |
4368 | { | |
4369 | u64 val; | |
4370 | ||
4371 | nw64(RX_LOG_MASK1(channel), 0); | |
4372 | nw64(RX_LOG_VAL1(channel), 0); | |
4373 | nw64(RX_LOG_MASK2(channel), 0); | |
4374 | nw64(RX_LOG_VAL2(channel), 0); | |
4375 | nw64(RX_LOG_PAGE_RELO1(channel), 0); | |
4376 | nw64(RX_LOG_PAGE_RELO2(channel), 0); | |
4377 | nw64(RX_LOG_PAGE_HDL(channel), 0); | |
4378 | ||
4379 | val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT; | |
4380 | val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1); | |
4381 | nw64(RX_LOG_PAGE_VLD(channel), val); | |
4382 | ||
4383 | return 0; | |
4384 | } | |
4385 | ||
4386 | static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp) | |
4387 | { | |
4388 | u64 val; | |
4389 | ||
4390 | val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) | | |
4391 | ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) | | |
4392 | ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) | | |
4393 | ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT)); | |
4394 | nw64(RDC_RED_PARA(rp->rx_channel), val); | |
4395 | } | |
4396 | ||
4397 | static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret) | |
4398 | { | |
4399 | u64 val = 0; | |
4400 | ||
4401 | switch (rp->rbr_block_size) { | |
4402 | case 4 * 1024: | |
4403 | val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT); | |
4404 | break; | |
4405 | case 8 * 1024: | |
4406 | val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT); | |
4407 | break; | |
4408 | case 16 * 1024: | |
4409 | val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT); | |
4410 | break; | |
4411 | case 32 * 1024: | |
4412 | val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT); | |
4413 | break; | |
4414 | default: | |
4415 | return -EINVAL; | |
4416 | } | |
4417 | val |= RBR_CFIG_B_VLD2; | |
4418 | switch (rp->rbr_sizes[2]) { | |
4419 | case 2 * 1024: | |
4420 | val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT); | |
4421 | break; | |
4422 | case 4 * 1024: | |
4423 | val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT); | |
4424 | break; | |
4425 | case 8 * 1024: | |
4426 | val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT); | |
4427 | break; | |
4428 | case 16 * 1024: | |
4429 | val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT); | |
4430 | break; | |
4431 | ||
4432 | default: | |
4433 | return -EINVAL; | |
4434 | } | |
4435 | val |= RBR_CFIG_B_VLD1; | |
4436 | switch (rp->rbr_sizes[1]) { | |
4437 | case 1 * 1024: | |
4438 | val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT); | |
4439 | break; | |
4440 | case 2 * 1024: | |
4441 | val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT); | |
4442 | break; | |
4443 | case 4 * 1024: | |
4444 | val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT); | |
4445 | break; | |
4446 | case 8 * 1024: | |
4447 | val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT); | |
4448 | break; | |
4449 | ||
4450 | default: | |
4451 | return -EINVAL; | |
4452 | } | |
4453 | val |= RBR_CFIG_B_VLD0; | |
4454 | switch (rp->rbr_sizes[0]) { | |
4455 | case 256: | |
4456 | val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT); | |
4457 | break; | |
4458 | case 512: | |
4459 | val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT); | |
4460 | break; | |
4461 | case 1 * 1024: | |
4462 | val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT); | |
4463 | break; | |
4464 | case 2 * 1024: | |
4465 | val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT); | |
4466 | break; | |
4467 | ||
4468 | default: | |
4469 | return -EINVAL; | |
4470 | } | |
4471 | ||
4472 | *ret = val; | |
4473 | return 0; | |
4474 | } | |
4475 | ||
4476 | static int niu_enable_rx_channel(struct niu *np, int channel, int on) | |
4477 | { | |
4478 | u64 val = nr64(RXDMA_CFIG1(channel)); | |
4479 | int limit; | |
4480 | ||
4481 | if (on) | |
4482 | val |= RXDMA_CFIG1_EN; | |
4483 | else | |
4484 | val &= ~RXDMA_CFIG1_EN; | |
4485 | nw64(RXDMA_CFIG1(channel), val); | |
4486 | ||
4487 | limit = 1000; | |
4488 | while (--limit > 0) { | |
4489 | if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST) | |
4490 | break; | |
4491 | udelay(10); | |
4492 | } | |
4493 | if (limit <= 0) | |
4494 | return -ENODEV; | |
4495 | return 0; | |
4496 | } | |
4497 | ||
4498 | static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp) | |
4499 | { | |
4500 | int err, channel = rp->rx_channel; | |
4501 | u64 val; | |
4502 | ||
4503 | err = niu_rx_channel_reset(np, channel); | |
4504 | if (err) | |
4505 | return err; | |
4506 | ||
4507 | err = niu_rx_channel_lpage_init(np, channel); | |
4508 | if (err) | |
4509 | return err; | |
4510 | ||
4511 | niu_rx_channel_wred_init(np, rp); | |
4512 | ||
4513 | nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY); | |
4514 | nw64(RX_DMA_CTL_STAT(channel), | |
4515 | (RX_DMA_CTL_STAT_MEX | | |
4516 | RX_DMA_CTL_STAT_RCRTHRES | | |
4517 | RX_DMA_CTL_STAT_RCRTO | | |
4518 | RX_DMA_CTL_STAT_RBR_EMPTY)); | |
4519 | nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32); | |
4520 | nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0)); | |
4521 | nw64(RBR_CFIG_A(channel), | |
4522 | ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) | | |
4523 | (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR))); | |
4524 | err = niu_compute_rbr_cfig_b(rp, &val); | |
4525 | if (err) | |
4526 | return err; | |
4527 | nw64(RBR_CFIG_B(channel), val); | |
4528 | nw64(RCRCFIG_A(channel), | |
4529 | ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) | | |
4530 | (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR))); | |
4531 | nw64(RCRCFIG_B(channel), | |
4532 | ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) | | |
4533 | RCRCFIG_B_ENTOUT | | |
4534 | ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT)); | |
4535 | ||
4536 | err = niu_enable_rx_channel(np, channel, 1); | |
4537 | if (err) | |
4538 | return err; | |
4539 | ||
4540 | nw64(RBR_KICK(channel), rp->rbr_index); | |
4541 | ||
4542 | val = nr64(RX_DMA_CTL_STAT(channel)); | |
4543 | val |= RX_DMA_CTL_STAT_RBR_EMPTY; | |
4544 | nw64(RX_DMA_CTL_STAT(channel), val); | |
4545 | ||
4546 | return 0; | |
4547 | } | |
4548 | ||
4549 | static int niu_init_rx_channels(struct niu *np) | |
4550 | { | |
4551 | unsigned long flags; | |
4552 | u64 seed = jiffies_64; | |
4553 | int err, i; | |
4554 | ||
4555 | niu_lock_parent(np, flags); | |
4556 | nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider); | |
4557 | nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL)); | |
4558 | niu_unlock_parent(np, flags); | |
4559 | ||
4560 | /* XXX RXDMA 32bit mode? XXX */ | |
4561 | ||
4562 | niu_init_rdc_groups(np); | |
4563 | niu_init_drr_weight(np); | |
4564 | ||
4565 | err = niu_init_hostinfo(np); | |
4566 | if (err) | |
4567 | return err; | |
4568 | ||
4569 | for (i = 0; i < np->num_rx_rings; i++) { | |
4570 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
4571 | ||
4572 | err = niu_init_one_rx_channel(np, rp); | |
4573 | if (err) | |
4574 | return err; | |
4575 | } | |
4576 | ||
4577 | return 0; | |
4578 | } | |
4579 | ||
4580 | static int niu_set_ip_frag_rule(struct niu *np) | |
4581 | { | |
4582 | struct niu_parent *parent = np->parent; | |
4583 | struct niu_classifier *cp = &np->clas; | |
4584 | struct niu_tcam_entry *tp; | |
4585 | int index, err; | |
4586 | ||
4587 | /* XXX fix this allocation scheme XXX */ | |
4588 | index = cp->tcam_index; | |
4589 | tp = &parent->tcam[index]; | |
4590 | ||
4591 | /* Note that the noport bit is the same in both ipv4 and | |
4592 | * ipv6 format TCAM entries. | |
4593 | */ | |
4594 | memset(tp, 0, sizeof(*tp)); | |
4595 | tp->key[1] = TCAM_V4KEY1_NOPORT; | |
4596 | tp->key_mask[1] = TCAM_V4KEY1_NOPORT; | |
4597 | tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | | |
4598 | ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT)); | |
4599 | err = tcam_write(np, index, tp->key, tp->key_mask); | |
4600 | if (err) | |
4601 | return err; | |
4602 | err = tcam_assoc_write(np, index, tp->assoc_data); | |
4603 | if (err) | |
4604 | return err; | |
4605 | ||
4606 | return 0; | |
4607 | } | |
4608 | ||
4609 | static int niu_init_classifier_hw(struct niu *np) | |
4610 | { | |
4611 | struct niu_parent *parent = np->parent; | |
4612 | struct niu_classifier *cp = &np->clas; | |
4613 | int i, err; | |
4614 | ||
4615 | nw64(H1POLY, cp->h1_init); | |
4616 | nw64(H2POLY, cp->h2_init); | |
4617 | ||
4618 | err = niu_init_hostinfo(np); | |
4619 | if (err) | |
4620 | return err; | |
4621 | ||
4622 | for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) { | |
4623 | struct niu_vlan_rdc *vp = &cp->vlan_mappings[i]; | |
4624 | ||
4625 | vlan_tbl_write(np, i, np->port, | |
4626 | vp->vlan_pref, vp->rdc_num); | |
4627 | } | |
4628 | ||
4629 | for (i = 0; i < cp->num_alt_mac_mappings; i++) { | |
4630 | struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i]; | |
4631 | ||
4632 | err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num, | |
4633 | ap->rdc_num, ap->mac_pref); | |
4634 | if (err) | |
4635 | return err; | |
4636 | } | |
4637 | ||
4638 | for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { | |
4639 | int index = i - CLASS_CODE_USER_PROG1; | |
4640 | ||
4641 | err = niu_set_tcam_key(np, i, parent->tcam_key[index]); | |
4642 | if (err) | |
4643 | return err; | |
4644 | err = niu_set_flow_key(np, i, parent->flow_key[index]); | |
4645 | if (err) | |
4646 | return err; | |
4647 | } | |
4648 | ||
4649 | err = niu_set_ip_frag_rule(np); | |
4650 | if (err) | |
4651 | return err; | |
4652 | ||
4653 | tcam_enable(np, 1); | |
4654 | ||
4655 | return 0; | |
4656 | } | |
4657 | ||
4658 | static int niu_zcp_write(struct niu *np, int index, u64 *data) | |
4659 | { | |
4660 | nw64(ZCP_RAM_DATA0, data[0]); | |
4661 | nw64(ZCP_RAM_DATA1, data[1]); | |
4662 | nw64(ZCP_RAM_DATA2, data[2]); | |
4663 | nw64(ZCP_RAM_DATA3, data[3]); | |
4664 | nw64(ZCP_RAM_DATA4, data[4]); | |
4665 | nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL); | |
4666 | nw64(ZCP_RAM_ACC, | |
4667 | (ZCP_RAM_ACC_WRITE | | |
4668 | (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | | |
4669 | (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); | |
4670 | ||
4671 | return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, | |
4672 | 1000, 100); | |
4673 | } | |
4674 | ||
4675 | static int niu_zcp_read(struct niu *np, int index, u64 *data) | |
4676 | { | |
4677 | int err; | |
4678 | ||
4679 | err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, | |
4680 | 1000, 100); | |
4681 | if (err) { | |
4682 | dev_err(np->device, PFX "%s: ZCP read busy won't clear, " | |
4683 | "ZCP_RAM_ACC[%llx]\n", np->dev->name, | |
4684 | (unsigned long long) nr64(ZCP_RAM_ACC)); | |
4685 | return err; | |
4686 | } | |
4687 | ||
4688 | nw64(ZCP_RAM_ACC, | |
4689 | (ZCP_RAM_ACC_READ | | |
4690 | (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | | |
4691 | (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); | |
4692 | ||
4693 | err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, | |
4694 | 1000, 100); | |
4695 | if (err) { | |
4696 | dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, " | |
4697 | "ZCP_RAM_ACC[%llx]\n", np->dev->name, | |
4698 | (unsigned long long) nr64(ZCP_RAM_ACC)); | |
4699 | return err; | |
4700 | } | |
4701 | ||
4702 | data[0] = nr64(ZCP_RAM_DATA0); | |
4703 | data[1] = nr64(ZCP_RAM_DATA1); | |
4704 | data[2] = nr64(ZCP_RAM_DATA2); | |
4705 | data[3] = nr64(ZCP_RAM_DATA3); | |
4706 | data[4] = nr64(ZCP_RAM_DATA4); | |
4707 | ||
4708 | return 0; | |
4709 | } | |
4710 | ||
4711 | static void niu_zcp_cfifo_reset(struct niu *np) | |
4712 | { | |
4713 | u64 val = nr64(RESET_CFIFO); | |
4714 | ||
4715 | val |= RESET_CFIFO_RST(np->port); | |
4716 | nw64(RESET_CFIFO, val); | |
4717 | udelay(10); | |
4718 | ||
4719 | val &= ~RESET_CFIFO_RST(np->port); | |
4720 | nw64(RESET_CFIFO, val); | |
4721 | } | |
4722 | ||
4723 | static int niu_init_zcp(struct niu *np) | |
4724 | { | |
4725 | u64 data[5], rbuf[5]; | |
4726 | int i, max, err; | |
4727 | ||
4728 | if (np->parent->plat_type != PLAT_TYPE_NIU) { | |
4729 | if (np->port == 0 || np->port == 1) | |
4730 | max = ATLAS_P0_P1_CFIFO_ENTRIES; | |
4731 | else | |
4732 | max = ATLAS_P2_P3_CFIFO_ENTRIES; | |
4733 | } else | |
4734 | max = NIU_CFIFO_ENTRIES; | |
4735 | ||
4736 | data[0] = 0; | |
4737 | data[1] = 0; | |
4738 | data[2] = 0; | |
4739 | data[3] = 0; | |
4740 | data[4] = 0; | |
4741 | ||
4742 | for (i = 0; i < max; i++) { | |
4743 | err = niu_zcp_write(np, i, data); | |
4744 | if (err) | |
4745 | return err; | |
4746 | err = niu_zcp_read(np, i, rbuf); | |
4747 | if (err) | |
4748 | return err; | |
4749 | } | |
4750 | ||
4751 | niu_zcp_cfifo_reset(np); | |
4752 | nw64(CFIFO_ECC(np->port), 0); | |
4753 | nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL); | |
4754 | (void) nr64(ZCP_INT_STAT); | |
4755 | nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL); | |
4756 | ||
4757 | return 0; | |
4758 | } | |
4759 | ||
4760 | static void niu_ipp_write(struct niu *np, int index, u64 *data) | |
4761 | { | |
4762 | u64 val = nr64_ipp(IPP_CFIG); | |
4763 | ||
4764 | nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W); | |
4765 | nw64_ipp(IPP_DFIFO_WR_PTR, index); | |
4766 | nw64_ipp(IPP_DFIFO_WR0, data[0]); | |
4767 | nw64_ipp(IPP_DFIFO_WR1, data[1]); | |
4768 | nw64_ipp(IPP_DFIFO_WR2, data[2]); | |
4769 | nw64_ipp(IPP_DFIFO_WR3, data[3]); | |
4770 | nw64_ipp(IPP_DFIFO_WR4, data[4]); | |
4771 | nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W); | |
4772 | } | |
4773 | ||
4774 | static void niu_ipp_read(struct niu *np, int index, u64 *data) | |
4775 | { | |
4776 | nw64_ipp(IPP_DFIFO_RD_PTR, index); | |
4777 | data[0] = nr64_ipp(IPP_DFIFO_RD0); | |
4778 | data[1] = nr64_ipp(IPP_DFIFO_RD1); | |
4779 | data[2] = nr64_ipp(IPP_DFIFO_RD2); | |
4780 | data[3] = nr64_ipp(IPP_DFIFO_RD3); | |
4781 | data[4] = nr64_ipp(IPP_DFIFO_RD4); | |
4782 | } | |
4783 | ||
4784 | static int niu_ipp_reset(struct niu *np) | |
4785 | { | |
4786 | return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST, | |
4787 | 1000, 100, "IPP_CFIG"); | |
4788 | } | |
4789 | ||
4790 | static int niu_init_ipp(struct niu *np) | |
4791 | { | |
4792 | u64 data[5], rbuf[5], val; | |
4793 | int i, max, err; | |
4794 | ||
4795 | if (np->parent->plat_type != PLAT_TYPE_NIU) { | |
4796 | if (np->port == 0 || np->port == 1) | |
4797 | max = ATLAS_P0_P1_DFIFO_ENTRIES; | |
4798 | else | |
4799 | max = ATLAS_P2_P3_DFIFO_ENTRIES; | |
4800 | } else | |
4801 | max = NIU_DFIFO_ENTRIES; | |
4802 | ||
4803 | data[0] = 0; | |
4804 | data[1] = 0; | |
4805 | data[2] = 0; | |
4806 | data[3] = 0; | |
4807 | data[4] = 0; | |
4808 | ||
4809 | for (i = 0; i < max; i++) { | |
4810 | niu_ipp_write(np, i, data); | |
4811 | niu_ipp_read(np, i, rbuf); | |
4812 | } | |
4813 | ||
4814 | (void) nr64_ipp(IPP_INT_STAT); | |
4815 | (void) nr64_ipp(IPP_INT_STAT); | |
4816 | ||
4817 | err = niu_ipp_reset(np); | |
4818 | if (err) | |
4819 | return err; | |
4820 | ||
4821 | (void) nr64_ipp(IPP_PKT_DIS); | |
4822 | (void) nr64_ipp(IPP_BAD_CS_CNT); | |
4823 | (void) nr64_ipp(IPP_ECC); | |
4824 | ||
4825 | (void) nr64_ipp(IPP_INT_STAT); | |
4826 | ||
4827 | nw64_ipp(IPP_MSK, ~IPP_MSK_ALL); | |
4828 | ||
4829 | val = nr64_ipp(IPP_CFIG); | |
4830 | val &= ~IPP_CFIG_IP_MAX_PKT; | |
4831 | val |= (IPP_CFIG_IPP_ENABLE | | |
4832 | IPP_CFIG_DFIFO_ECC_EN | | |
4833 | IPP_CFIG_DROP_BAD_CRC | | |
4834 | IPP_CFIG_CKSUM_EN | | |
4835 | (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT)); | |
4836 | nw64_ipp(IPP_CFIG, val); | |
4837 | ||
4838 | return 0; | |
4839 | } | |
4840 | ||
0c3b091b | 4841 | static void niu_handle_led(struct niu *np, int status) |
a3138df9 | 4842 | { |
a3138df9 | 4843 | u64 val; |
a3138df9 DM |
4844 | val = nr64_mac(XMAC_CONFIG); |
4845 | ||
4846 | if ((np->flags & NIU_FLAGS_10G) != 0 && | |
4847 | (np->flags & NIU_FLAGS_FIBER) != 0) { | |
0c3b091b | 4848 | if (status) { |
a3138df9 DM |
4849 | val |= XMAC_CONFIG_LED_POLARITY; |
4850 | val &= ~XMAC_CONFIG_FORCE_LED_ON; | |
4851 | } else { | |
4852 | val |= XMAC_CONFIG_FORCE_LED_ON; | |
4853 | val &= ~XMAC_CONFIG_LED_POLARITY; | |
4854 | } | |
4855 | } | |
4856 | ||
0c3b091b ML |
4857 | nw64_mac(XMAC_CONFIG, val); |
4858 | } | |
4859 | ||
4860 | static void niu_init_xif_xmac(struct niu *np) | |
4861 | { | |
4862 | struct niu_link_config *lp = &np->link_config; | |
4863 | u64 val; | |
4864 | ||
5fbd7e24 MW |
4865 | if (np->flags & NIU_FLAGS_XCVR_SERDES) { |
4866 | val = nr64(MIF_CONFIG); | |
4867 | val |= MIF_CONFIG_ATCA_GE; | |
4868 | nw64(MIF_CONFIG, val); | |
4869 | } | |
4870 | ||
0c3b091b | 4871 | val = nr64_mac(XMAC_CONFIG); |
a3138df9 DM |
4872 | val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; |
4873 | ||
4874 | val |= XMAC_CONFIG_TX_OUTPUT_EN; | |
4875 | ||
4876 | if (lp->loopback_mode == LOOPBACK_MAC) { | |
4877 | val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; | |
4878 | val |= XMAC_CONFIG_LOOPBACK; | |
4879 | } else { | |
4880 | val &= ~XMAC_CONFIG_LOOPBACK; | |
4881 | } | |
4882 | ||
4883 | if (np->flags & NIU_FLAGS_10G) { | |
4884 | val &= ~XMAC_CONFIG_LFS_DISABLE; | |
4885 | } else { | |
4886 | val |= XMAC_CONFIG_LFS_DISABLE; | |
5fbd7e24 MW |
4887 | if (!(np->flags & NIU_FLAGS_FIBER) && |
4888 | !(np->flags & NIU_FLAGS_XCVR_SERDES)) | |
a3138df9 DM |
4889 | val |= XMAC_CONFIG_1G_PCS_BYPASS; |
4890 | else | |
4891 | val &= ~XMAC_CONFIG_1G_PCS_BYPASS; | |
4892 | } | |
4893 | ||
4894 | val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; | |
4895 | ||
4896 | if (lp->active_speed == SPEED_100) | |
4897 | val |= XMAC_CONFIG_SEL_CLK_25MHZ; | |
4898 | else | |
4899 | val &= ~XMAC_CONFIG_SEL_CLK_25MHZ; | |
4900 | ||
4901 | nw64_mac(XMAC_CONFIG, val); | |
4902 | ||
4903 | val = nr64_mac(XMAC_CONFIG); | |
4904 | val &= ~XMAC_CONFIG_MODE_MASK; | |
4905 | if (np->flags & NIU_FLAGS_10G) { | |
4906 | val |= XMAC_CONFIG_MODE_XGMII; | |
4907 | } else { | |
4908 | if (lp->active_speed == SPEED_100) | |
4909 | val |= XMAC_CONFIG_MODE_MII; | |
4910 | else | |
4911 | val |= XMAC_CONFIG_MODE_GMII; | |
4912 | } | |
4913 | ||
4914 | nw64_mac(XMAC_CONFIG, val); | |
4915 | } | |
4916 | ||
4917 | static void niu_init_xif_bmac(struct niu *np) | |
4918 | { | |
4919 | struct niu_link_config *lp = &np->link_config; | |
4920 | u64 val; | |
4921 | ||
4922 | val = BMAC_XIF_CONFIG_TX_OUTPUT_EN; | |
4923 | ||
4924 | if (lp->loopback_mode == LOOPBACK_MAC) | |
4925 | val |= BMAC_XIF_CONFIG_MII_LOOPBACK; | |
4926 | else | |
4927 | val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK; | |
4928 | ||
4929 | if (lp->active_speed == SPEED_1000) | |
4930 | val |= BMAC_XIF_CONFIG_GMII_MODE; | |
4931 | else | |
4932 | val &= ~BMAC_XIF_CONFIG_GMII_MODE; | |
4933 | ||
4934 | val &= ~(BMAC_XIF_CONFIG_LINK_LED | | |
4935 | BMAC_XIF_CONFIG_LED_POLARITY); | |
4936 | ||
4937 | if (!(np->flags & NIU_FLAGS_10G) && | |
4938 | !(np->flags & NIU_FLAGS_FIBER) && | |
4939 | lp->active_speed == SPEED_100) | |
4940 | val |= BMAC_XIF_CONFIG_25MHZ_CLOCK; | |
4941 | else | |
4942 | val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK; | |
4943 | ||
4944 | nw64_mac(BMAC_XIF_CONFIG, val); | |
4945 | } | |
4946 | ||
4947 | static void niu_init_xif(struct niu *np) | |
4948 | { | |
4949 | if (np->flags & NIU_FLAGS_XMAC) | |
4950 | niu_init_xif_xmac(np); | |
4951 | else | |
4952 | niu_init_xif_bmac(np); | |
4953 | } | |
4954 | ||
4955 | static void niu_pcs_mii_reset(struct niu *np) | |
4956 | { | |
5fbd7e24 | 4957 | int limit = 1000; |
a3138df9 DM |
4958 | u64 val = nr64_pcs(PCS_MII_CTL); |
4959 | val |= PCS_MII_CTL_RST; | |
4960 | nw64_pcs(PCS_MII_CTL, val); | |
5fbd7e24 MW |
4961 | while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) { |
4962 | udelay(100); | |
4963 | val = nr64_pcs(PCS_MII_CTL); | |
4964 | } | |
a3138df9 DM |
4965 | } |
4966 | ||
4967 | static void niu_xpcs_reset(struct niu *np) | |
4968 | { | |
5fbd7e24 | 4969 | int limit = 1000; |
a3138df9 DM |
4970 | u64 val = nr64_xpcs(XPCS_CONTROL1); |
4971 | val |= XPCS_CONTROL1_RESET; | |
4972 | nw64_xpcs(XPCS_CONTROL1, val); | |
5fbd7e24 MW |
4973 | while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) { |
4974 | udelay(100); | |
4975 | val = nr64_xpcs(XPCS_CONTROL1); | |
4976 | } | |
a3138df9 DM |
4977 | } |
4978 | ||
4979 | static int niu_init_pcs(struct niu *np) | |
4980 | { | |
4981 | struct niu_link_config *lp = &np->link_config; | |
4982 | u64 val; | |
4983 | ||
5fbd7e24 MW |
4984 | switch (np->flags & (NIU_FLAGS_10G | |
4985 | NIU_FLAGS_FIBER | | |
4986 | NIU_FLAGS_XCVR_SERDES)) { | |
a3138df9 DM |
4987 | case NIU_FLAGS_FIBER: |
4988 | /* 1G fiber */ | |
4989 | nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); | |
4990 | nw64_pcs(PCS_DPATH_MODE, 0); | |
4991 | niu_pcs_mii_reset(np); | |
4992 | break; | |
4993 | ||
4994 | case NIU_FLAGS_10G: | |
4995 | case NIU_FLAGS_10G | NIU_FLAGS_FIBER: | |
5fbd7e24 MW |
4996 | case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: |
4997 | /* 10G SERDES */ | |
a3138df9 DM |
4998 | if (!(np->flags & NIU_FLAGS_XMAC)) |
4999 | return -EINVAL; | |
5000 | ||
5001 | /* 10G copper or fiber */ | |
5002 | val = nr64_mac(XMAC_CONFIG); | |
5003 | val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; | |
5004 | nw64_mac(XMAC_CONFIG, val); | |
5005 | ||
5006 | niu_xpcs_reset(np); | |
5007 | ||
5008 | val = nr64_xpcs(XPCS_CONTROL1); | |
5009 | if (lp->loopback_mode == LOOPBACK_PHY) | |
5010 | val |= XPCS_CONTROL1_LOOPBACK; | |
5011 | else | |
5012 | val &= ~XPCS_CONTROL1_LOOPBACK; | |
5013 | nw64_xpcs(XPCS_CONTROL1, val); | |
5014 | ||
5015 | nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0); | |
5016 | (void) nr64_xpcs(XPCS_SYMERR_CNT01); | |
5017 | (void) nr64_xpcs(XPCS_SYMERR_CNT23); | |
5018 | break; | |
5019 | ||
5fbd7e24 MW |
5020 | |
5021 | case NIU_FLAGS_XCVR_SERDES: | |
5022 | /* 1G SERDES */ | |
5023 | niu_pcs_mii_reset(np); | |
5024 | nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); | |
5025 | nw64_pcs(PCS_DPATH_MODE, 0); | |
5026 | break; | |
5027 | ||
a3138df9 DM |
5028 | case 0: |
5029 | /* 1G copper */ | |
5fbd7e24 MW |
5030 | case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: |
5031 | /* 1G RGMII FIBER */ | |
a3138df9 DM |
5032 | nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII); |
5033 | niu_pcs_mii_reset(np); | |
5034 | break; | |
5035 | ||
5036 | default: | |
5037 | return -EINVAL; | |
5038 | } | |
5039 | ||
5040 | return 0; | |
5041 | } | |
5042 | ||
5043 | static int niu_reset_tx_xmac(struct niu *np) | |
5044 | { | |
5045 | return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST, | |
5046 | (XTXMAC_SW_RST_REG_RS | | |
5047 | XTXMAC_SW_RST_SOFT_RST), | |
5048 | 1000, 100, "XTXMAC_SW_RST"); | |
5049 | } | |
5050 | ||
5051 | static int niu_reset_tx_bmac(struct niu *np) | |
5052 | { | |
5053 | int limit; | |
5054 | ||
5055 | nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET); | |
5056 | limit = 1000; | |
5057 | while (--limit >= 0) { | |
5058 | if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET)) | |
5059 | break; | |
5060 | udelay(100); | |
5061 | } | |
5062 | if (limit < 0) { | |
5063 | dev_err(np->device, PFX "Port %u TX BMAC would not reset, " | |
5064 | "BTXMAC_SW_RST[%llx]\n", | |
5065 | np->port, | |
5066 | (unsigned long long) nr64_mac(BTXMAC_SW_RST)); | |
5067 | return -ENODEV; | |
5068 | } | |
5069 | ||
5070 | return 0; | |
5071 | } | |
5072 | ||
5073 | static int niu_reset_tx_mac(struct niu *np) | |
5074 | { | |
5075 | if (np->flags & NIU_FLAGS_XMAC) | |
5076 | return niu_reset_tx_xmac(np); | |
5077 | else | |
5078 | return niu_reset_tx_bmac(np); | |
5079 | } | |
5080 | ||
5081 | static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max) | |
5082 | { | |
5083 | u64 val; | |
5084 | ||
5085 | val = nr64_mac(XMAC_MIN); | |
5086 | val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE | | |
5087 | XMAC_MIN_RX_MIN_PKT_SIZE); | |
5088 | val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT); | |
5089 | val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT); | |
5090 | nw64_mac(XMAC_MIN, val); | |
5091 | ||
5092 | nw64_mac(XMAC_MAX, max); | |
5093 | ||
5094 | nw64_mac(XTXMAC_STAT_MSK, ~(u64)0); | |
5095 | ||
5096 | val = nr64_mac(XMAC_IPG); | |
5097 | if (np->flags & NIU_FLAGS_10G) { | |
5098 | val &= ~XMAC_IPG_IPG_XGMII; | |
5099 | val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT); | |
5100 | } else { | |
5101 | val &= ~XMAC_IPG_IPG_MII_GMII; | |
5102 | val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT); | |
5103 | } | |
5104 | nw64_mac(XMAC_IPG, val); | |
5105 | ||
5106 | val = nr64_mac(XMAC_CONFIG); | |
5107 | val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC | | |
5108 | XMAC_CONFIG_STRETCH_MODE | | |
5109 | XMAC_CONFIG_VAR_MIN_IPG_EN | | |
5110 | XMAC_CONFIG_TX_ENABLE); | |
5111 | nw64_mac(XMAC_CONFIG, val); | |
5112 | ||
5113 | nw64_mac(TXMAC_FRM_CNT, 0); | |
5114 | nw64_mac(TXMAC_BYTE_CNT, 0); | |
5115 | } | |
5116 | ||
5117 | static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max) | |
5118 | { | |
5119 | u64 val; | |
5120 | ||
5121 | nw64_mac(BMAC_MIN_FRAME, min); | |
5122 | nw64_mac(BMAC_MAX_FRAME, max); | |
5123 | ||
5124 | nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0); | |
5125 | nw64_mac(BMAC_CTRL_TYPE, 0x8808); | |
5126 | nw64_mac(BMAC_PREAMBLE_SIZE, 7); | |
5127 | ||
5128 | val = nr64_mac(BTXMAC_CONFIG); | |
5129 | val &= ~(BTXMAC_CONFIG_FCS_DISABLE | | |
5130 | BTXMAC_CONFIG_ENABLE); | |
5131 | nw64_mac(BTXMAC_CONFIG, val); | |
5132 | } | |
5133 | ||
5134 | static void niu_init_tx_mac(struct niu *np) | |
5135 | { | |
5136 | u64 min, max; | |
5137 | ||
5138 | min = 64; | |
5139 | if (np->dev->mtu > ETH_DATA_LEN) | |
5140 | max = 9216; | |
5141 | else | |
5142 | max = 1522; | |
5143 | ||
5144 | /* The XMAC_MIN register only accepts values for TX min which | |
5145 | * have the low 3 bits cleared. | |
5146 | */ | |
5147 | BUILD_BUG_ON(min & 0x7); | |
5148 | ||
5149 | if (np->flags & NIU_FLAGS_XMAC) | |
5150 | niu_init_tx_xmac(np, min, max); | |
5151 | else | |
5152 | niu_init_tx_bmac(np, min, max); | |
5153 | } | |
5154 | ||
5155 | static int niu_reset_rx_xmac(struct niu *np) | |
5156 | { | |
5157 | int limit; | |
5158 | ||
5159 | nw64_mac(XRXMAC_SW_RST, | |
5160 | XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST); | |
5161 | limit = 1000; | |
5162 | while (--limit >= 0) { | |
5163 | if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS | | |
5164 | XRXMAC_SW_RST_SOFT_RST))) | |
5165 | break; | |
5166 | udelay(100); | |
5167 | } | |
5168 | if (limit < 0) { | |
5169 | dev_err(np->device, PFX "Port %u RX XMAC would not reset, " | |
5170 | "XRXMAC_SW_RST[%llx]\n", | |
5171 | np->port, | |
5172 | (unsigned long long) nr64_mac(XRXMAC_SW_RST)); | |
5173 | return -ENODEV; | |
5174 | } | |
5175 | ||
5176 | return 0; | |
5177 | } | |
5178 | ||
5179 | static int niu_reset_rx_bmac(struct niu *np) | |
5180 | { | |
5181 | int limit; | |
5182 | ||
5183 | nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET); | |
5184 | limit = 1000; | |
5185 | while (--limit >= 0) { | |
5186 | if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET)) | |
5187 | break; | |
5188 | udelay(100); | |
5189 | } | |
5190 | if (limit < 0) { | |
5191 | dev_err(np->device, PFX "Port %u RX BMAC would not reset, " | |
5192 | "BRXMAC_SW_RST[%llx]\n", | |
5193 | np->port, | |
5194 | (unsigned long long) nr64_mac(BRXMAC_SW_RST)); | |
5195 | return -ENODEV; | |
5196 | } | |
5197 | ||
5198 | return 0; | |
5199 | } | |
5200 | ||
5201 | static int niu_reset_rx_mac(struct niu *np) | |
5202 | { | |
5203 | if (np->flags & NIU_FLAGS_XMAC) | |
5204 | return niu_reset_rx_xmac(np); | |
5205 | else | |
5206 | return niu_reset_rx_bmac(np); | |
5207 | } | |
5208 | ||
5209 | static void niu_init_rx_xmac(struct niu *np) | |
5210 | { | |
5211 | struct niu_parent *parent = np->parent; | |
5212 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; | |
5213 | int first_rdc_table = tp->first_table_num; | |
5214 | unsigned long i; | |
5215 | u64 val; | |
5216 | ||
5217 | nw64_mac(XMAC_ADD_FILT0, 0); | |
5218 | nw64_mac(XMAC_ADD_FILT1, 0); | |
5219 | nw64_mac(XMAC_ADD_FILT2, 0); | |
5220 | nw64_mac(XMAC_ADD_FILT12_MASK, 0); | |
5221 | nw64_mac(XMAC_ADD_FILT00_MASK, 0); | |
5222 | for (i = 0; i < MAC_NUM_HASH; i++) | |
5223 | nw64_mac(XMAC_HASH_TBL(i), 0); | |
5224 | nw64_mac(XRXMAC_STAT_MSK, ~(u64)0); | |
5225 | niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); | |
5226 | niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); | |
5227 | ||
5228 | val = nr64_mac(XMAC_CONFIG); | |
5229 | val &= ~(XMAC_CONFIG_RX_MAC_ENABLE | | |
5230 | XMAC_CONFIG_PROMISCUOUS | | |
5231 | XMAC_CONFIG_PROMISC_GROUP | | |
5232 | XMAC_CONFIG_ERR_CHK_DIS | | |
5233 | XMAC_CONFIG_RX_CRC_CHK_DIS | | |
5234 | XMAC_CONFIG_RESERVED_MULTICAST | | |
5235 | XMAC_CONFIG_RX_CODEV_CHK_DIS | | |
5236 | XMAC_CONFIG_ADDR_FILTER_EN | | |
5237 | XMAC_CONFIG_RCV_PAUSE_ENABLE | | |
5238 | XMAC_CONFIG_STRIP_CRC | | |
5239 | XMAC_CONFIG_PASS_FLOW_CTRL | | |
5240 | XMAC_CONFIG_MAC2IPP_PKT_CNT_EN); | |
5241 | val |= (XMAC_CONFIG_HASH_FILTER_EN); | |
5242 | nw64_mac(XMAC_CONFIG, val); | |
5243 | ||
5244 | nw64_mac(RXMAC_BT_CNT, 0); | |
5245 | nw64_mac(RXMAC_BC_FRM_CNT, 0); | |
5246 | nw64_mac(RXMAC_MC_FRM_CNT, 0); | |
5247 | nw64_mac(RXMAC_FRAG_CNT, 0); | |
5248 | nw64_mac(RXMAC_HIST_CNT1, 0); | |
5249 | nw64_mac(RXMAC_HIST_CNT2, 0); | |
5250 | nw64_mac(RXMAC_HIST_CNT3, 0); | |
5251 | nw64_mac(RXMAC_HIST_CNT4, 0); | |
5252 | nw64_mac(RXMAC_HIST_CNT5, 0); | |
5253 | nw64_mac(RXMAC_HIST_CNT6, 0); | |
5254 | nw64_mac(RXMAC_HIST_CNT7, 0); | |
5255 | nw64_mac(RXMAC_MPSZER_CNT, 0); | |
5256 | nw64_mac(RXMAC_CRC_ER_CNT, 0); | |
5257 | nw64_mac(RXMAC_CD_VIO_CNT, 0); | |
5258 | nw64_mac(LINK_FAULT_CNT, 0); | |
5259 | } | |
5260 | ||
5261 | static void niu_init_rx_bmac(struct niu *np) | |
5262 | { | |
5263 | struct niu_parent *parent = np->parent; | |
5264 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; | |
5265 | int first_rdc_table = tp->first_table_num; | |
5266 | unsigned long i; | |
5267 | u64 val; | |
5268 | ||
5269 | nw64_mac(BMAC_ADD_FILT0, 0); | |
5270 | nw64_mac(BMAC_ADD_FILT1, 0); | |
5271 | nw64_mac(BMAC_ADD_FILT2, 0); | |
5272 | nw64_mac(BMAC_ADD_FILT12_MASK, 0); | |
5273 | nw64_mac(BMAC_ADD_FILT00_MASK, 0); | |
5274 | for (i = 0; i < MAC_NUM_HASH; i++) | |
5275 | nw64_mac(BMAC_HASH_TBL(i), 0); | |
5276 | niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); | |
5277 | niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); | |
5278 | nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0); | |
5279 | ||
5280 | val = nr64_mac(BRXMAC_CONFIG); | |
5281 | val &= ~(BRXMAC_CONFIG_ENABLE | | |
5282 | BRXMAC_CONFIG_STRIP_PAD | | |
5283 | BRXMAC_CONFIG_STRIP_FCS | | |
5284 | BRXMAC_CONFIG_PROMISC | | |
5285 | BRXMAC_CONFIG_PROMISC_GRP | | |
5286 | BRXMAC_CONFIG_ADDR_FILT_EN | | |
5287 | BRXMAC_CONFIG_DISCARD_DIS); | |
5288 | val |= (BRXMAC_CONFIG_HASH_FILT_EN); | |
5289 | nw64_mac(BRXMAC_CONFIG, val); | |
5290 | ||
5291 | val = nr64_mac(BMAC_ADDR_CMPEN); | |
5292 | val |= BMAC_ADDR_CMPEN_EN0; | |
5293 | nw64_mac(BMAC_ADDR_CMPEN, val); | |
5294 | } | |
5295 | ||
5296 | static void niu_init_rx_mac(struct niu *np) | |
5297 | { | |
5298 | niu_set_primary_mac(np, np->dev->dev_addr); | |
5299 | ||
5300 | if (np->flags & NIU_FLAGS_XMAC) | |
5301 | niu_init_rx_xmac(np); | |
5302 | else | |
5303 | niu_init_rx_bmac(np); | |
5304 | } | |
5305 | ||
5306 | static void niu_enable_tx_xmac(struct niu *np, int on) | |
5307 | { | |
5308 | u64 val = nr64_mac(XMAC_CONFIG); | |
5309 | ||
5310 | if (on) | |
5311 | val |= XMAC_CONFIG_TX_ENABLE; | |
5312 | else | |
5313 | val &= ~XMAC_CONFIG_TX_ENABLE; | |
5314 | nw64_mac(XMAC_CONFIG, val); | |
5315 | } | |
5316 | ||
5317 | static void niu_enable_tx_bmac(struct niu *np, int on) | |
5318 | { | |
5319 | u64 val = nr64_mac(BTXMAC_CONFIG); | |
5320 | ||
5321 | if (on) | |
5322 | val |= BTXMAC_CONFIG_ENABLE; | |
5323 | else | |
5324 | val &= ~BTXMAC_CONFIG_ENABLE; | |
5325 | nw64_mac(BTXMAC_CONFIG, val); | |
5326 | } | |
5327 | ||
5328 | static void niu_enable_tx_mac(struct niu *np, int on) | |
5329 | { | |
5330 | if (np->flags & NIU_FLAGS_XMAC) | |
5331 | niu_enable_tx_xmac(np, on); | |
5332 | else | |
5333 | niu_enable_tx_bmac(np, on); | |
5334 | } | |
5335 | ||
5336 | static void niu_enable_rx_xmac(struct niu *np, int on) | |
5337 | { | |
5338 | u64 val = nr64_mac(XMAC_CONFIG); | |
5339 | ||
5340 | val &= ~(XMAC_CONFIG_HASH_FILTER_EN | | |
5341 | XMAC_CONFIG_PROMISCUOUS); | |
5342 | ||
5343 | if (np->flags & NIU_FLAGS_MCAST) | |
5344 | val |= XMAC_CONFIG_HASH_FILTER_EN; | |
5345 | if (np->flags & NIU_FLAGS_PROMISC) | |
5346 | val |= XMAC_CONFIG_PROMISCUOUS; | |
5347 | ||
5348 | if (on) | |
5349 | val |= XMAC_CONFIG_RX_MAC_ENABLE; | |
5350 | else | |
5351 | val &= ~XMAC_CONFIG_RX_MAC_ENABLE; | |
5352 | nw64_mac(XMAC_CONFIG, val); | |
5353 | } | |
5354 | ||
5355 | static void niu_enable_rx_bmac(struct niu *np, int on) | |
5356 | { | |
5357 | u64 val = nr64_mac(BRXMAC_CONFIG); | |
5358 | ||
5359 | val &= ~(BRXMAC_CONFIG_HASH_FILT_EN | | |
5360 | BRXMAC_CONFIG_PROMISC); | |
5361 | ||
5362 | if (np->flags & NIU_FLAGS_MCAST) | |
5363 | val |= BRXMAC_CONFIG_HASH_FILT_EN; | |
5364 | if (np->flags & NIU_FLAGS_PROMISC) | |
5365 | val |= BRXMAC_CONFIG_PROMISC; | |
5366 | ||
5367 | if (on) | |
5368 | val |= BRXMAC_CONFIG_ENABLE; | |
5369 | else | |
5370 | val &= ~BRXMAC_CONFIG_ENABLE; | |
5371 | nw64_mac(BRXMAC_CONFIG, val); | |
5372 | } | |
5373 | ||
5374 | static void niu_enable_rx_mac(struct niu *np, int on) | |
5375 | { | |
5376 | if (np->flags & NIU_FLAGS_XMAC) | |
5377 | niu_enable_rx_xmac(np, on); | |
5378 | else | |
5379 | niu_enable_rx_bmac(np, on); | |
5380 | } | |
5381 | ||
5382 | static int niu_init_mac(struct niu *np) | |
5383 | { | |
5384 | int err; | |
5385 | ||
5386 | niu_init_xif(np); | |
5387 | err = niu_init_pcs(np); | |
5388 | if (err) | |
5389 | return err; | |
5390 | ||
5391 | err = niu_reset_tx_mac(np); | |
5392 | if (err) | |
5393 | return err; | |
5394 | niu_init_tx_mac(np); | |
5395 | err = niu_reset_rx_mac(np); | |
5396 | if (err) | |
5397 | return err; | |
5398 | niu_init_rx_mac(np); | |
5399 | ||
5400 | /* This looks hookey but the RX MAC reset we just did will | |
5401 | * undo some of the state we setup in niu_init_tx_mac() so we | |
5402 | * have to call it again. In particular, the RX MAC reset will | |
5403 | * set the XMAC_MAX register back to it's default value. | |
5404 | */ | |
5405 | niu_init_tx_mac(np); | |
5406 | niu_enable_tx_mac(np, 1); | |
5407 | ||
5408 | niu_enable_rx_mac(np, 1); | |
5409 | ||
5410 | return 0; | |
5411 | } | |
5412 | ||
5413 | static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp) | |
5414 | { | |
5415 | (void) niu_tx_channel_stop(np, rp->tx_channel); | |
5416 | } | |
5417 | ||
5418 | static void niu_stop_tx_channels(struct niu *np) | |
5419 | { | |
5420 | int i; | |
5421 | ||
5422 | for (i = 0; i < np->num_tx_rings; i++) { | |
5423 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
5424 | ||
5425 | niu_stop_one_tx_channel(np, rp); | |
5426 | } | |
5427 | } | |
5428 | ||
5429 | static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp) | |
5430 | { | |
5431 | (void) niu_tx_channel_reset(np, rp->tx_channel); | |
5432 | } | |
5433 | ||
5434 | static void niu_reset_tx_channels(struct niu *np) | |
5435 | { | |
5436 | int i; | |
5437 | ||
5438 | for (i = 0; i < np->num_tx_rings; i++) { | |
5439 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
5440 | ||
5441 | niu_reset_one_tx_channel(np, rp); | |
5442 | } | |
5443 | } | |
5444 | ||
5445 | static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp) | |
5446 | { | |
5447 | (void) niu_enable_rx_channel(np, rp->rx_channel, 0); | |
5448 | } | |
5449 | ||
5450 | static void niu_stop_rx_channels(struct niu *np) | |
5451 | { | |
5452 | int i; | |
5453 | ||
5454 | for (i = 0; i < np->num_rx_rings; i++) { | |
5455 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
5456 | ||
5457 | niu_stop_one_rx_channel(np, rp); | |
5458 | } | |
5459 | } | |
5460 | ||
5461 | static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp) | |
5462 | { | |
5463 | int channel = rp->rx_channel; | |
5464 | ||
5465 | (void) niu_rx_channel_reset(np, channel); | |
5466 | nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL); | |
5467 | nw64(RX_DMA_CTL_STAT(channel), 0); | |
5468 | (void) niu_enable_rx_channel(np, channel, 0); | |
5469 | } | |
5470 | ||
5471 | static void niu_reset_rx_channels(struct niu *np) | |
5472 | { | |
5473 | int i; | |
5474 | ||
5475 | for (i = 0; i < np->num_rx_rings; i++) { | |
5476 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
5477 | ||
5478 | niu_reset_one_rx_channel(np, rp); | |
5479 | } | |
5480 | } | |
5481 | ||
5482 | static void niu_disable_ipp(struct niu *np) | |
5483 | { | |
5484 | u64 rd, wr, val; | |
5485 | int limit; | |
5486 | ||
5487 | rd = nr64_ipp(IPP_DFIFO_RD_PTR); | |
5488 | wr = nr64_ipp(IPP_DFIFO_WR_PTR); | |
5489 | limit = 100; | |
5490 | while (--limit >= 0 && (rd != wr)) { | |
5491 | rd = nr64_ipp(IPP_DFIFO_RD_PTR); | |
5492 | wr = nr64_ipp(IPP_DFIFO_WR_PTR); | |
5493 | } | |
5494 | if (limit < 0 && | |
5495 | (rd != 0 && wr != 1)) { | |
5496 | dev_err(np->device, PFX "%s: IPP would not quiesce, " | |
5497 | "rd_ptr[%llx] wr_ptr[%llx]\n", | |
5498 | np->dev->name, | |
5499 | (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR), | |
5500 | (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR)); | |
5501 | } | |
5502 | ||
5503 | val = nr64_ipp(IPP_CFIG); | |
5504 | val &= ~(IPP_CFIG_IPP_ENABLE | | |
5505 | IPP_CFIG_DFIFO_ECC_EN | | |
5506 | IPP_CFIG_DROP_BAD_CRC | | |
5507 | IPP_CFIG_CKSUM_EN); | |
5508 | nw64_ipp(IPP_CFIG, val); | |
5509 | ||
5510 | (void) niu_ipp_reset(np); | |
5511 | } | |
5512 | ||
5513 | static int niu_init_hw(struct niu *np) | |
5514 | { | |
5515 | int i, err; | |
5516 | ||
5517 | niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name); | |
5518 | niu_txc_enable_port(np, 1); | |
5519 | niu_txc_port_dma_enable(np, 1); | |
5520 | niu_txc_set_imask(np, 0); | |
5521 | ||
5522 | niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name); | |
5523 | for (i = 0; i < np->num_tx_rings; i++) { | |
5524 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
5525 | ||
5526 | err = niu_init_one_tx_channel(np, rp); | |
5527 | if (err) | |
5528 | return err; | |
5529 | } | |
5530 | ||
5531 | niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name); | |
5532 | err = niu_init_rx_channels(np); | |
5533 | if (err) | |
5534 | goto out_uninit_tx_channels; | |
5535 | ||
5536 | niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name); | |
5537 | err = niu_init_classifier_hw(np); | |
5538 | if (err) | |
5539 | goto out_uninit_rx_channels; | |
5540 | ||
5541 | niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name); | |
5542 | err = niu_init_zcp(np); | |
5543 | if (err) | |
5544 | goto out_uninit_rx_channels; | |
5545 | ||
5546 | niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name); | |
5547 | err = niu_init_ipp(np); | |
5548 | if (err) | |
5549 | goto out_uninit_rx_channels; | |
5550 | ||
5551 | niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name); | |
5552 | err = niu_init_mac(np); | |
5553 | if (err) | |
5554 | goto out_uninit_ipp; | |
5555 | ||
5556 | return 0; | |
5557 | ||
5558 | out_uninit_ipp: | |
5559 | niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name); | |
5560 | niu_disable_ipp(np); | |
5561 | ||
5562 | out_uninit_rx_channels: | |
5563 | niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name); | |
5564 | niu_stop_rx_channels(np); | |
5565 | niu_reset_rx_channels(np); | |
5566 | ||
5567 | out_uninit_tx_channels: | |
5568 | niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name); | |
5569 | niu_stop_tx_channels(np); | |
5570 | niu_reset_tx_channels(np); | |
5571 | ||
5572 | return err; | |
5573 | } | |
5574 | ||
5575 | static void niu_stop_hw(struct niu *np) | |
5576 | { | |
5577 | niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name); | |
5578 | niu_enable_interrupts(np, 0); | |
5579 | ||
5580 | niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name); | |
5581 | niu_enable_rx_mac(np, 0); | |
5582 | ||
5583 | niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name); | |
5584 | niu_disable_ipp(np); | |
5585 | ||
5586 | niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name); | |
5587 | niu_stop_tx_channels(np); | |
5588 | ||
5589 | niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name); | |
5590 | niu_stop_rx_channels(np); | |
5591 | ||
5592 | niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name); | |
5593 | niu_reset_tx_channels(np); | |
5594 | ||
5595 | niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name); | |
5596 | niu_reset_rx_channels(np); | |
5597 | } | |
5598 | ||
5599 | static int niu_request_irq(struct niu *np) | |
5600 | { | |
5601 | int i, j, err; | |
5602 | ||
5603 | err = 0; | |
5604 | for (i = 0; i < np->num_ldg; i++) { | |
5605 | struct niu_ldg *lp = &np->ldg[i]; | |
5606 | ||
5607 | err = request_irq(lp->irq, niu_interrupt, | |
5608 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, | |
5609 | np->dev->name, lp); | |
5610 | if (err) | |
5611 | goto out_free_irqs; | |
5612 | ||
5613 | } | |
5614 | ||
5615 | return 0; | |
5616 | ||
5617 | out_free_irqs: | |
5618 | for (j = 0; j < i; j++) { | |
5619 | struct niu_ldg *lp = &np->ldg[j]; | |
5620 | ||
5621 | free_irq(lp->irq, lp); | |
5622 | } | |
5623 | return err; | |
5624 | } | |
5625 | ||
5626 | static void niu_free_irq(struct niu *np) | |
5627 | { | |
5628 | int i; | |
5629 | ||
5630 | for (i = 0; i < np->num_ldg; i++) { | |
5631 | struct niu_ldg *lp = &np->ldg[i]; | |
5632 | ||
5633 | free_irq(lp->irq, lp); | |
5634 | } | |
5635 | } | |
5636 | ||
5637 | static void niu_enable_napi(struct niu *np) | |
5638 | { | |
5639 | int i; | |
5640 | ||
5641 | for (i = 0; i < np->num_ldg; i++) | |
5642 | napi_enable(&np->ldg[i].napi); | |
5643 | } | |
5644 | ||
5645 | static void niu_disable_napi(struct niu *np) | |
5646 | { | |
5647 | int i; | |
5648 | ||
5649 | for (i = 0; i < np->num_ldg; i++) | |
5650 | napi_disable(&np->ldg[i].napi); | |
5651 | } | |
5652 | ||
5653 | static int niu_open(struct net_device *dev) | |
5654 | { | |
5655 | struct niu *np = netdev_priv(dev); | |
5656 | int err; | |
5657 | ||
5658 | netif_carrier_off(dev); | |
5659 | ||
5660 | err = niu_alloc_channels(np); | |
5661 | if (err) | |
5662 | goto out_err; | |
5663 | ||
5664 | err = niu_enable_interrupts(np, 0); | |
5665 | if (err) | |
5666 | goto out_free_channels; | |
5667 | ||
5668 | err = niu_request_irq(np); | |
5669 | if (err) | |
5670 | goto out_free_channels; | |
5671 | ||
5672 | niu_enable_napi(np); | |
5673 | ||
5674 | spin_lock_irq(&np->lock); | |
5675 | ||
5676 | err = niu_init_hw(np); | |
5677 | if (!err) { | |
5678 | init_timer(&np->timer); | |
5679 | np->timer.expires = jiffies + HZ; | |
5680 | np->timer.data = (unsigned long) np; | |
5681 | np->timer.function = niu_timer; | |
5682 | ||
5683 | err = niu_enable_interrupts(np, 1); | |
5684 | if (err) | |
5685 | niu_stop_hw(np); | |
5686 | } | |
5687 | ||
5688 | spin_unlock_irq(&np->lock); | |
5689 | ||
5690 | if (err) { | |
5691 | niu_disable_napi(np); | |
5692 | goto out_free_irq; | |
5693 | } | |
5694 | ||
5695 | netif_start_queue(dev); | |
5696 | ||
5697 | if (np->link_config.loopback_mode != LOOPBACK_DISABLED) | |
5698 | netif_carrier_on(dev); | |
5699 | ||
5700 | add_timer(&np->timer); | |
5701 | ||
5702 | return 0; | |
5703 | ||
5704 | out_free_irq: | |
5705 | niu_free_irq(np); | |
5706 | ||
5707 | out_free_channels: | |
5708 | niu_free_channels(np); | |
5709 | ||
5710 | out_err: | |
5711 | return err; | |
5712 | } | |
5713 | ||
5714 | static void niu_full_shutdown(struct niu *np, struct net_device *dev) | |
5715 | { | |
5716 | cancel_work_sync(&np->reset_task); | |
5717 | ||
5718 | niu_disable_napi(np); | |
5719 | netif_stop_queue(dev); | |
5720 | ||
5721 | del_timer_sync(&np->timer); | |
5722 | ||
5723 | spin_lock_irq(&np->lock); | |
5724 | ||
5725 | niu_stop_hw(np); | |
5726 | ||
5727 | spin_unlock_irq(&np->lock); | |
5728 | } | |
5729 | ||
5730 | static int niu_close(struct net_device *dev) | |
5731 | { | |
5732 | struct niu *np = netdev_priv(dev); | |
5733 | ||
5734 | niu_full_shutdown(np, dev); | |
5735 | ||
5736 | niu_free_irq(np); | |
5737 | ||
5738 | niu_free_channels(np); | |
5739 | ||
0c3b091b ML |
5740 | niu_handle_led(np, 0); |
5741 | ||
a3138df9 DM |
5742 | return 0; |
5743 | } | |
5744 | ||
5745 | static void niu_sync_xmac_stats(struct niu *np) | |
5746 | { | |
5747 | struct niu_xmac_stats *mp = &np->mac_stats.xmac; | |
5748 | ||
5749 | mp->tx_frames += nr64_mac(TXMAC_FRM_CNT); | |
5750 | mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT); | |
5751 | ||
5752 | mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT); | |
5753 | mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT); | |
5754 | mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT); | |
5755 | mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT); | |
5756 | mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT); | |
5757 | mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1); | |
5758 | mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2); | |
5759 | mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3); | |
5760 | mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4); | |
5761 | mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5); | |
5762 | mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6); | |
5763 | mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7); | |
5764 | mp->rx_octets += nr64_mac(RXMAC_BT_CNT); | |
5765 | mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT); | |
5766 | mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT); | |
5767 | mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT); | |
5768 | } | |
5769 | ||
5770 | static void niu_sync_bmac_stats(struct niu *np) | |
5771 | { | |
5772 | struct niu_bmac_stats *mp = &np->mac_stats.bmac; | |
5773 | ||
5774 | mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT); | |
5775 | mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT); | |
5776 | ||
5777 | mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT); | |
5778 | mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); | |
5779 | mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); | |
5780 | mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT); | |
5781 | } | |
5782 | ||
5783 | static void niu_sync_mac_stats(struct niu *np) | |
5784 | { | |
5785 | if (np->flags & NIU_FLAGS_XMAC) | |
5786 | niu_sync_xmac_stats(np); | |
5787 | else | |
5788 | niu_sync_bmac_stats(np); | |
5789 | } | |
5790 | ||
5791 | static void niu_get_rx_stats(struct niu *np) | |
5792 | { | |
5793 | unsigned long pkts, dropped, errors, bytes; | |
5794 | int i; | |
5795 | ||
5796 | pkts = dropped = errors = bytes = 0; | |
5797 | for (i = 0; i < np->num_rx_rings; i++) { | |
5798 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
5799 | ||
5800 | pkts += rp->rx_packets; | |
5801 | bytes += rp->rx_bytes; | |
5802 | dropped += rp->rx_dropped; | |
5803 | errors += rp->rx_errors; | |
5804 | } | |
5805 | np->net_stats.rx_packets = pkts; | |
5806 | np->net_stats.rx_bytes = bytes; | |
5807 | np->net_stats.rx_dropped = dropped; | |
5808 | np->net_stats.rx_errors = errors; | |
5809 | } | |
5810 | ||
5811 | static void niu_get_tx_stats(struct niu *np) | |
5812 | { | |
5813 | unsigned long pkts, errors, bytes; | |
5814 | int i; | |
5815 | ||
5816 | pkts = errors = bytes = 0; | |
5817 | for (i = 0; i < np->num_tx_rings; i++) { | |
5818 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
5819 | ||
5820 | pkts += rp->tx_packets; | |
5821 | bytes += rp->tx_bytes; | |
5822 | errors += rp->tx_errors; | |
5823 | } | |
5824 | np->net_stats.tx_packets = pkts; | |
5825 | np->net_stats.tx_bytes = bytes; | |
5826 | np->net_stats.tx_errors = errors; | |
5827 | } | |
5828 | ||
5829 | static struct net_device_stats *niu_get_stats(struct net_device *dev) | |
5830 | { | |
5831 | struct niu *np = netdev_priv(dev); | |
5832 | ||
5833 | niu_get_rx_stats(np); | |
5834 | niu_get_tx_stats(np); | |
5835 | ||
5836 | return &np->net_stats; | |
5837 | } | |
5838 | ||
5839 | static void niu_load_hash_xmac(struct niu *np, u16 *hash) | |
5840 | { | |
5841 | int i; | |
5842 | ||
5843 | for (i = 0; i < 16; i++) | |
5844 | nw64_mac(XMAC_HASH_TBL(i), hash[i]); | |
5845 | } | |
5846 | ||
5847 | static void niu_load_hash_bmac(struct niu *np, u16 *hash) | |
5848 | { | |
5849 | int i; | |
5850 | ||
5851 | for (i = 0; i < 16; i++) | |
5852 | nw64_mac(BMAC_HASH_TBL(i), hash[i]); | |
5853 | } | |
5854 | ||
5855 | static void niu_load_hash(struct niu *np, u16 *hash) | |
5856 | { | |
5857 | if (np->flags & NIU_FLAGS_XMAC) | |
5858 | niu_load_hash_xmac(np, hash); | |
5859 | else | |
5860 | niu_load_hash_bmac(np, hash); | |
5861 | } | |
5862 | ||
5863 | static void niu_set_rx_mode(struct net_device *dev) | |
5864 | { | |
5865 | struct niu *np = netdev_priv(dev); | |
5866 | int i, alt_cnt, err; | |
5867 | struct dev_addr_list *addr; | |
5868 | unsigned long flags; | |
5869 | u16 hash[16] = { 0, }; | |
5870 | ||
5871 | spin_lock_irqsave(&np->lock, flags); | |
5872 | niu_enable_rx_mac(np, 0); | |
5873 | ||
5874 | np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC); | |
5875 | if (dev->flags & IFF_PROMISC) | |
5876 | np->flags |= NIU_FLAGS_PROMISC; | |
5877 | if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0)) | |
5878 | np->flags |= NIU_FLAGS_MCAST; | |
5879 | ||
5880 | alt_cnt = dev->uc_count; | |
5881 | if (alt_cnt > niu_num_alt_addr(np)) { | |
5882 | alt_cnt = 0; | |
5883 | np->flags |= NIU_FLAGS_PROMISC; | |
5884 | } | |
5885 | ||
5886 | if (alt_cnt) { | |
5887 | int index = 0; | |
5888 | ||
5889 | for (addr = dev->uc_list; addr; addr = addr->next) { | |
5890 | err = niu_set_alt_mac(np, index, | |
5891 | addr->da_addr); | |
5892 | if (err) | |
5893 | printk(KERN_WARNING PFX "%s: Error %d " | |
5894 | "adding alt mac %d\n", | |
5895 | dev->name, err, index); | |
5896 | err = niu_enable_alt_mac(np, index, 1); | |
5897 | if (err) | |
5898 | printk(KERN_WARNING PFX "%s: Error %d " | |
5899 | "enabling alt mac %d\n", | |
5900 | dev->name, err, index); | |
5901 | ||
5902 | index++; | |
5903 | } | |
5904 | } else { | |
3b5bcede MW |
5905 | int alt_start; |
5906 | if (np->flags & NIU_FLAGS_XMAC) | |
5907 | alt_start = 0; | |
5908 | else | |
5909 | alt_start = 1; | |
5910 | for (i = alt_start; i < niu_num_alt_addr(np); i++) { | |
a3138df9 DM |
5911 | err = niu_enable_alt_mac(np, i, 0); |
5912 | if (err) | |
5913 | printk(KERN_WARNING PFX "%s: Error %d " | |
5914 | "disabling alt mac %d\n", | |
5915 | dev->name, err, i); | |
5916 | } | |
5917 | } | |
5918 | if (dev->flags & IFF_ALLMULTI) { | |
5919 | for (i = 0; i < 16; i++) | |
5920 | hash[i] = 0xffff; | |
5921 | } else if (dev->mc_count > 0) { | |
5922 | for (addr = dev->mc_list; addr; addr = addr->next) { | |
5923 | u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr); | |
5924 | ||
5925 | crc >>= 24; | |
5926 | hash[crc >> 4] |= (1 << (15 - (crc & 0xf))); | |
5927 | } | |
5928 | } | |
5929 | ||
5930 | if (np->flags & NIU_FLAGS_MCAST) | |
5931 | niu_load_hash(np, hash); | |
5932 | ||
5933 | niu_enable_rx_mac(np, 1); | |
5934 | spin_unlock_irqrestore(&np->lock, flags); | |
5935 | } | |
5936 | ||
5937 | static int niu_set_mac_addr(struct net_device *dev, void *p) | |
5938 | { | |
5939 | struct niu *np = netdev_priv(dev); | |
5940 | struct sockaddr *addr = p; | |
5941 | unsigned long flags; | |
5942 | ||
5943 | if (!is_valid_ether_addr(addr->sa_data)) | |
5944 | return -EINVAL; | |
5945 | ||
5946 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); | |
5947 | ||
5948 | if (!netif_running(dev)) | |
5949 | return 0; | |
5950 | ||
5951 | spin_lock_irqsave(&np->lock, flags); | |
5952 | niu_enable_rx_mac(np, 0); | |
5953 | niu_set_primary_mac(np, dev->dev_addr); | |
5954 | niu_enable_rx_mac(np, 1); | |
5955 | spin_unlock_irqrestore(&np->lock, flags); | |
5956 | ||
5957 | return 0; | |
5958 | } | |
5959 | ||
5960 | static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
5961 | { | |
5962 | return -EOPNOTSUPP; | |
5963 | } | |
5964 | ||
5965 | static void niu_netif_stop(struct niu *np) | |
5966 | { | |
5967 | np->dev->trans_start = jiffies; /* prevent tx timeout */ | |
5968 | ||
5969 | niu_disable_napi(np); | |
5970 | ||
5971 | netif_tx_disable(np->dev); | |
5972 | } | |
5973 | ||
5974 | static void niu_netif_start(struct niu *np) | |
5975 | { | |
5976 | /* NOTE: unconditional netif_wake_queue is only appropriate | |
5977 | * so long as all callers are assured to have free tx slots | |
5978 | * (such as after niu_init_hw). | |
5979 | */ | |
5980 | netif_wake_queue(np->dev); | |
5981 | ||
5982 | niu_enable_napi(np); | |
5983 | ||
5984 | niu_enable_interrupts(np, 1); | |
5985 | } | |
5986 | ||
5987 | static void niu_reset_task(struct work_struct *work) | |
5988 | { | |
5989 | struct niu *np = container_of(work, struct niu, reset_task); | |
5990 | unsigned long flags; | |
5991 | int err; | |
5992 | ||
5993 | spin_lock_irqsave(&np->lock, flags); | |
5994 | if (!netif_running(np->dev)) { | |
5995 | spin_unlock_irqrestore(&np->lock, flags); | |
5996 | return; | |
5997 | } | |
5998 | ||
5999 | spin_unlock_irqrestore(&np->lock, flags); | |
6000 | ||
6001 | del_timer_sync(&np->timer); | |
6002 | ||
6003 | niu_netif_stop(np); | |
6004 | ||
6005 | spin_lock_irqsave(&np->lock, flags); | |
6006 | ||
6007 | niu_stop_hw(np); | |
6008 | ||
6009 | err = niu_init_hw(np); | |
6010 | if (!err) { | |
6011 | np->timer.expires = jiffies + HZ; | |
6012 | add_timer(&np->timer); | |
6013 | niu_netif_start(np); | |
6014 | } | |
6015 | ||
6016 | spin_unlock_irqrestore(&np->lock, flags); | |
6017 | } | |
6018 | ||
6019 | static void niu_tx_timeout(struct net_device *dev) | |
6020 | { | |
6021 | struct niu *np = netdev_priv(dev); | |
6022 | ||
6023 | dev_err(np->device, PFX "%s: Transmit timed out, resetting\n", | |
6024 | dev->name); | |
6025 | ||
6026 | schedule_work(&np->reset_task); | |
6027 | } | |
6028 | ||
6029 | static void niu_set_txd(struct tx_ring_info *rp, int index, | |
6030 | u64 mapping, u64 len, u64 mark, | |
6031 | u64 n_frags) | |
6032 | { | |
6033 | __le64 *desc = &rp->descr[index]; | |
6034 | ||
6035 | *desc = cpu_to_le64(mark | | |
6036 | (n_frags << TX_DESC_NUM_PTR_SHIFT) | | |
6037 | (len << TX_DESC_TR_LEN_SHIFT) | | |
6038 | (mapping & TX_DESC_SAD)); | |
6039 | } | |
6040 | ||
6041 | static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr, | |
6042 | u64 pad_bytes, u64 len) | |
6043 | { | |
6044 | u16 eth_proto, eth_proto_inner; | |
6045 | u64 csum_bits, l3off, ihl, ret; | |
6046 | u8 ip_proto; | |
6047 | int ipv6; | |
6048 | ||
6049 | eth_proto = be16_to_cpu(ehdr->h_proto); | |
6050 | eth_proto_inner = eth_proto; | |
6051 | if (eth_proto == ETH_P_8021Q) { | |
6052 | struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr; | |
6053 | __be16 val = vp->h_vlan_encapsulated_proto; | |
6054 | ||
6055 | eth_proto_inner = be16_to_cpu(val); | |
6056 | } | |
6057 | ||
6058 | ipv6 = ihl = 0; | |
6059 | switch (skb->protocol) { | |
6060 | case __constant_htons(ETH_P_IP): | |
6061 | ip_proto = ip_hdr(skb)->protocol; | |
6062 | ihl = ip_hdr(skb)->ihl; | |
6063 | break; | |
6064 | case __constant_htons(ETH_P_IPV6): | |
6065 | ip_proto = ipv6_hdr(skb)->nexthdr; | |
6066 | ihl = (40 >> 2); | |
6067 | ipv6 = 1; | |
6068 | break; | |
6069 | default: | |
6070 | ip_proto = ihl = 0; | |
6071 | break; | |
6072 | } | |
6073 | ||
6074 | csum_bits = TXHDR_CSUM_NONE; | |
6075 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
6076 | u64 start, stuff; | |
6077 | ||
6078 | csum_bits = (ip_proto == IPPROTO_TCP ? | |
6079 | TXHDR_CSUM_TCP : | |
6080 | (ip_proto == IPPROTO_UDP ? | |
6081 | TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP)); | |
6082 | ||
6083 | start = skb_transport_offset(skb) - | |
6084 | (pad_bytes + sizeof(struct tx_pkt_hdr)); | |
6085 | stuff = start + skb->csum_offset; | |
6086 | ||
6087 | csum_bits |= (start / 2) << TXHDR_L4START_SHIFT; | |
6088 | csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT; | |
6089 | } | |
6090 | ||
6091 | l3off = skb_network_offset(skb) - | |
6092 | (pad_bytes + sizeof(struct tx_pkt_hdr)); | |
6093 | ||
6094 | ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) | | |
6095 | (len << TXHDR_LEN_SHIFT) | | |
6096 | ((l3off / 2) << TXHDR_L3START_SHIFT) | | |
6097 | (ihl << TXHDR_IHL_SHIFT) | | |
6098 | ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) | | |
6099 | ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) | | |
6100 | (ipv6 ? TXHDR_IP_VER : 0) | | |
6101 | csum_bits); | |
6102 | ||
6103 | return ret; | |
6104 | } | |
6105 | ||
6106 | static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb) | |
6107 | { | |
6108 | return &np->tx_rings[0]; | |
6109 | } | |
6110 | ||
6111 | static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
6112 | { | |
6113 | struct niu *np = netdev_priv(dev); | |
6114 | unsigned long align, headroom; | |
6115 | struct tx_ring_info *rp; | |
6116 | struct tx_pkt_hdr *tp; | |
6117 | unsigned int len, nfg; | |
6118 | struct ethhdr *ehdr; | |
6119 | int prod, i, tlen; | |
6120 | u64 mapping, mrk; | |
6121 | ||
6122 | rp = tx_ring_select(np, skb); | |
6123 | ||
6124 | if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) { | |
6125 | netif_stop_queue(dev); | |
6126 | dev_err(np->device, PFX "%s: BUG! Tx ring full when " | |
6127 | "queue awake!\n", dev->name); | |
6128 | rp->tx_errors++; | |
6129 | return NETDEV_TX_BUSY; | |
6130 | } | |
6131 | ||
6132 | if (skb->len < ETH_ZLEN) { | |
6133 | unsigned int pad_bytes = ETH_ZLEN - skb->len; | |
6134 | ||
6135 | if (skb_pad(skb, pad_bytes)) | |
6136 | goto out; | |
6137 | skb_put(skb, pad_bytes); | |
6138 | } | |
6139 | ||
6140 | len = sizeof(struct tx_pkt_hdr) + 15; | |
6141 | if (skb_headroom(skb) < len) { | |
6142 | struct sk_buff *skb_new; | |
6143 | ||
6144 | skb_new = skb_realloc_headroom(skb, len); | |
6145 | if (!skb_new) { | |
6146 | rp->tx_errors++; | |
6147 | goto out_drop; | |
6148 | } | |
6149 | kfree_skb(skb); | |
6150 | skb = skb_new; | |
3ebebccf DM |
6151 | } else |
6152 | skb_orphan(skb); | |
a3138df9 DM |
6153 | |
6154 | align = ((unsigned long) skb->data & (16 - 1)); | |
6155 | headroom = align + sizeof(struct tx_pkt_hdr); | |
6156 | ||
6157 | ehdr = (struct ethhdr *) skb->data; | |
6158 | tp = (struct tx_pkt_hdr *) skb_push(skb, headroom); | |
6159 | ||
6160 | len = skb->len - sizeof(struct tx_pkt_hdr); | |
6161 | tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len)); | |
6162 | tp->resv = 0; | |
6163 | ||
6164 | len = skb_headlen(skb); | |
6165 | mapping = np->ops->map_single(np->device, skb->data, | |
6166 | len, DMA_TO_DEVICE); | |
6167 | ||
6168 | prod = rp->prod; | |
6169 | ||
6170 | rp->tx_buffs[prod].skb = skb; | |
6171 | rp->tx_buffs[prod].mapping = mapping; | |
6172 | ||
6173 | mrk = TX_DESC_SOP; | |
6174 | if (++rp->mark_counter == rp->mark_freq) { | |
6175 | rp->mark_counter = 0; | |
6176 | mrk |= TX_DESC_MARK; | |
6177 | rp->mark_pending++; | |
6178 | } | |
6179 | ||
6180 | tlen = len; | |
6181 | nfg = skb_shinfo(skb)->nr_frags; | |
6182 | while (tlen > 0) { | |
6183 | tlen -= MAX_TX_DESC_LEN; | |
6184 | nfg++; | |
6185 | } | |
6186 | ||
6187 | while (len > 0) { | |
6188 | unsigned int this_len = len; | |
6189 | ||
6190 | if (this_len > MAX_TX_DESC_LEN) | |
6191 | this_len = MAX_TX_DESC_LEN; | |
6192 | ||
6193 | niu_set_txd(rp, prod, mapping, this_len, mrk, nfg); | |
6194 | mrk = nfg = 0; | |
6195 | ||
6196 | prod = NEXT_TX(rp, prod); | |
6197 | mapping += this_len; | |
6198 | len -= this_len; | |
6199 | } | |
6200 | ||
6201 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6202 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6203 | ||
6204 | len = frag->size; | |
6205 | mapping = np->ops->map_page(np->device, frag->page, | |
6206 | frag->page_offset, len, | |
6207 | DMA_TO_DEVICE); | |
6208 | ||
6209 | rp->tx_buffs[prod].skb = NULL; | |
6210 | rp->tx_buffs[prod].mapping = mapping; | |
6211 | ||
6212 | niu_set_txd(rp, prod, mapping, len, 0, 0); | |
6213 | ||
6214 | prod = NEXT_TX(rp, prod); | |
6215 | } | |
6216 | ||
6217 | if (prod < rp->prod) | |
6218 | rp->wrap_bit ^= TX_RING_KICK_WRAP; | |
6219 | rp->prod = prod; | |
6220 | ||
6221 | nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3)); | |
6222 | ||
6223 | if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) { | |
6224 | netif_stop_queue(dev); | |
6225 | if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)) | |
6226 | netif_wake_queue(dev); | |
6227 | } | |
6228 | ||
6229 | dev->trans_start = jiffies; | |
6230 | ||
6231 | out: | |
6232 | return NETDEV_TX_OK; | |
6233 | ||
6234 | out_drop: | |
6235 | rp->tx_errors++; | |
6236 | kfree_skb(skb); | |
6237 | goto out; | |
6238 | } | |
6239 | ||
6240 | static int niu_change_mtu(struct net_device *dev, int new_mtu) | |
6241 | { | |
6242 | struct niu *np = netdev_priv(dev); | |
6243 | int err, orig_jumbo, new_jumbo; | |
6244 | ||
6245 | if (new_mtu < 68 || new_mtu > NIU_MAX_MTU) | |
6246 | return -EINVAL; | |
6247 | ||
6248 | orig_jumbo = (dev->mtu > ETH_DATA_LEN); | |
6249 | new_jumbo = (new_mtu > ETH_DATA_LEN); | |
6250 | ||
6251 | dev->mtu = new_mtu; | |
6252 | ||
6253 | if (!netif_running(dev) || | |
6254 | (orig_jumbo == new_jumbo)) | |
6255 | return 0; | |
6256 | ||
6257 | niu_full_shutdown(np, dev); | |
6258 | ||
6259 | niu_free_channels(np); | |
6260 | ||
6261 | niu_enable_napi(np); | |
6262 | ||
6263 | err = niu_alloc_channels(np); | |
6264 | if (err) | |
6265 | return err; | |
6266 | ||
6267 | spin_lock_irq(&np->lock); | |
6268 | ||
6269 | err = niu_init_hw(np); | |
6270 | if (!err) { | |
6271 | init_timer(&np->timer); | |
6272 | np->timer.expires = jiffies + HZ; | |
6273 | np->timer.data = (unsigned long) np; | |
6274 | np->timer.function = niu_timer; | |
6275 | ||
6276 | err = niu_enable_interrupts(np, 1); | |
6277 | if (err) | |
6278 | niu_stop_hw(np); | |
6279 | } | |
6280 | ||
6281 | spin_unlock_irq(&np->lock); | |
6282 | ||
6283 | if (!err) { | |
6284 | netif_start_queue(dev); | |
6285 | if (np->link_config.loopback_mode != LOOPBACK_DISABLED) | |
6286 | netif_carrier_on(dev); | |
6287 | ||
6288 | add_timer(&np->timer); | |
6289 | } | |
6290 | ||
6291 | return err; | |
6292 | } | |
6293 | ||
6294 | static void niu_get_drvinfo(struct net_device *dev, | |
6295 | struct ethtool_drvinfo *info) | |
6296 | { | |
6297 | struct niu *np = netdev_priv(dev); | |
6298 | struct niu_vpd *vpd = &np->vpd; | |
6299 | ||
6300 | strcpy(info->driver, DRV_MODULE_NAME); | |
6301 | strcpy(info->version, DRV_MODULE_VERSION); | |
6302 | sprintf(info->fw_version, "%d.%d", | |
6303 | vpd->fcode_major, vpd->fcode_minor); | |
6304 | if (np->parent->plat_type != PLAT_TYPE_NIU) | |
6305 | strcpy(info->bus_info, pci_name(np->pdev)); | |
6306 | } | |
6307 | ||
6308 | static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
6309 | { | |
6310 | struct niu *np = netdev_priv(dev); | |
6311 | struct niu_link_config *lp; | |
6312 | ||
6313 | lp = &np->link_config; | |
6314 | ||
6315 | memset(cmd, 0, sizeof(*cmd)); | |
6316 | cmd->phy_address = np->phy_addr; | |
6317 | cmd->supported = lp->supported; | |
6318 | cmd->advertising = lp->advertising; | |
6319 | cmd->autoneg = lp->autoneg; | |
6320 | cmd->speed = lp->active_speed; | |
6321 | cmd->duplex = lp->active_duplex; | |
6322 | ||
6323 | return 0; | |
6324 | } | |
6325 | ||
6326 | static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
6327 | { | |
6328 | return -EINVAL; | |
6329 | } | |
6330 | ||
6331 | static u32 niu_get_msglevel(struct net_device *dev) | |
6332 | { | |
6333 | struct niu *np = netdev_priv(dev); | |
6334 | return np->msg_enable; | |
6335 | } | |
6336 | ||
6337 | static void niu_set_msglevel(struct net_device *dev, u32 value) | |
6338 | { | |
6339 | struct niu *np = netdev_priv(dev); | |
6340 | np->msg_enable = value; | |
6341 | } | |
6342 | ||
6343 | static int niu_get_eeprom_len(struct net_device *dev) | |
6344 | { | |
6345 | struct niu *np = netdev_priv(dev); | |
6346 | ||
6347 | return np->eeprom_len; | |
6348 | } | |
6349 | ||
6350 | static int niu_get_eeprom(struct net_device *dev, | |
6351 | struct ethtool_eeprom *eeprom, u8 *data) | |
6352 | { | |
6353 | struct niu *np = netdev_priv(dev); | |
6354 | u32 offset, len, val; | |
6355 | ||
6356 | offset = eeprom->offset; | |
6357 | len = eeprom->len; | |
6358 | ||
6359 | if (offset + len < offset) | |
6360 | return -EINVAL; | |
6361 | if (offset >= np->eeprom_len) | |
6362 | return -EINVAL; | |
6363 | if (offset + len > np->eeprom_len) | |
6364 | len = eeprom->len = np->eeprom_len - offset; | |
6365 | ||
6366 | if (offset & 3) { | |
6367 | u32 b_offset, b_count; | |
6368 | ||
6369 | b_offset = offset & 3; | |
6370 | b_count = 4 - b_offset; | |
6371 | if (b_count > len) | |
6372 | b_count = len; | |
6373 | ||
6374 | val = nr64(ESPC_NCR((offset - b_offset) / 4)); | |
6375 | memcpy(data, ((char *)&val) + b_offset, b_count); | |
6376 | data += b_count; | |
6377 | len -= b_count; | |
6378 | offset += b_count; | |
6379 | } | |
6380 | while (len >= 4) { | |
6381 | val = nr64(ESPC_NCR(offset / 4)); | |
6382 | memcpy(data, &val, 4); | |
6383 | data += 4; | |
6384 | len -= 4; | |
6385 | offset += 4; | |
6386 | } | |
6387 | if (len) { | |
6388 | val = nr64(ESPC_NCR(offset / 4)); | |
6389 | memcpy(data, &val, len); | |
6390 | } | |
6391 | return 0; | |
6392 | } | |
6393 | ||
6394 | static const struct { | |
6395 | const char string[ETH_GSTRING_LEN]; | |
6396 | } niu_xmac_stat_keys[] = { | |
6397 | { "tx_frames" }, | |
6398 | { "tx_bytes" }, | |
6399 | { "tx_fifo_errors" }, | |
6400 | { "tx_overflow_errors" }, | |
6401 | { "tx_max_pkt_size_errors" }, | |
6402 | { "tx_underflow_errors" }, | |
6403 | { "rx_local_faults" }, | |
6404 | { "rx_remote_faults" }, | |
6405 | { "rx_link_faults" }, | |
6406 | { "rx_align_errors" }, | |
6407 | { "rx_frags" }, | |
6408 | { "rx_mcasts" }, | |
6409 | { "rx_bcasts" }, | |
6410 | { "rx_hist_cnt1" }, | |
6411 | { "rx_hist_cnt2" }, | |
6412 | { "rx_hist_cnt3" }, | |
6413 | { "rx_hist_cnt4" }, | |
6414 | { "rx_hist_cnt5" }, | |
6415 | { "rx_hist_cnt6" }, | |
6416 | { "rx_hist_cnt7" }, | |
6417 | { "rx_octets" }, | |
6418 | { "rx_code_violations" }, | |
6419 | { "rx_len_errors" }, | |
6420 | { "rx_crc_errors" }, | |
6421 | { "rx_underflows" }, | |
6422 | { "rx_overflows" }, | |
6423 | { "pause_off_state" }, | |
6424 | { "pause_on_state" }, | |
6425 | { "pause_received" }, | |
6426 | }; | |
6427 | ||
6428 | #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys) | |
6429 | ||
6430 | static const struct { | |
6431 | const char string[ETH_GSTRING_LEN]; | |
6432 | } niu_bmac_stat_keys[] = { | |
6433 | { "tx_underflow_errors" }, | |
6434 | { "tx_max_pkt_size_errors" }, | |
6435 | { "tx_bytes" }, | |
6436 | { "tx_frames" }, | |
6437 | { "rx_overflows" }, | |
6438 | { "rx_frames" }, | |
6439 | { "rx_align_errors" }, | |
6440 | { "rx_crc_errors" }, | |
6441 | { "rx_len_errors" }, | |
6442 | { "pause_off_state" }, | |
6443 | { "pause_on_state" }, | |
6444 | { "pause_received" }, | |
6445 | }; | |
6446 | ||
6447 | #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys) | |
6448 | ||
6449 | static const struct { | |
6450 | const char string[ETH_GSTRING_LEN]; | |
6451 | } niu_rxchan_stat_keys[] = { | |
6452 | { "rx_channel" }, | |
6453 | { "rx_packets" }, | |
6454 | { "rx_bytes" }, | |
6455 | { "rx_dropped" }, | |
6456 | { "rx_errors" }, | |
6457 | }; | |
6458 | ||
6459 | #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys) | |
6460 | ||
6461 | static const struct { | |
6462 | const char string[ETH_GSTRING_LEN]; | |
6463 | } niu_txchan_stat_keys[] = { | |
6464 | { "tx_channel" }, | |
6465 | { "tx_packets" }, | |
6466 | { "tx_bytes" }, | |
6467 | { "tx_errors" }, | |
6468 | }; | |
6469 | ||
6470 | #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys) | |
6471 | ||
6472 | static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
6473 | { | |
6474 | struct niu *np = netdev_priv(dev); | |
6475 | int i; | |
6476 | ||
6477 | if (stringset != ETH_SS_STATS) | |
6478 | return; | |
6479 | ||
6480 | if (np->flags & NIU_FLAGS_XMAC) { | |
6481 | memcpy(data, niu_xmac_stat_keys, | |
6482 | sizeof(niu_xmac_stat_keys)); | |
6483 | data += sizeof(niu_xmac_stat_keys); | |
6484 | } else { | |
6485 | memcpy(data, niu_bmac_stat_keys, | |
6486 | sizeof(niu_bmac_stat_keys)); | |
6487 | data += sizeof(niu_bmac_stat_keys); | |
6488 | } | |
6489 | for (i = 0; i < np->num_rx_rings; i++) { | |
6490 | memcpy(data, niu_rxchan_stat_keys, | |
6491 | sizeof(niu_rxchan_stat_keys)); | |
6492 | data += sizeof(niu_rxchan_stat_keys); | |
6493 | } | |
6494 | for (i = 0; i < np->num_tx_rings; i++) { | |
6495 | memcpy(data, niu_txchan_stat_keys, | |
6496 | sizeof(niu_txchan_stat_keys)); | |
6497 | data += sizeof(niu_txchan_stat_keys); | |
6498 | } | |
6499 | } | |
6500 | ||
6501 | static int niu_get_stats_count(struct net_device *dev) | |
6502 | { | |
6503 | struct niu *np = netdev_priv(dev); | |
6504 | ||
6505 | return ((np->flags & NIU_FLAGS_XMAC ? | |
6506 | NUM_XMAC_STAT_KEYS : | |
6507 | NUM_BMAC_STAT_KEYS) + | |
6508 | (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) + | |
6509 | (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS)); | |
6510 | } | |
6511 | ||
6512 | static void niu_get_ethtool_stats(struct net_device *dev, | |
6513 | struct ethtool_stats *stats, u64 *data) | |
6514 | { | |
6515 | struct niu *np = netdev_priv(dev); | |
6516 | int i; | |
6517 | ||
6518 | niu_sync_mac_stats(np); | |
6519 | if (np->flags & NIU_FLAGS_XMAC) { | |
6520 | memcpy(data, &np->mac_stats.xmac, | |
6521 | sizeof(struct niu_xmac_stats)); | |
6522 | data += (sizeof(struct niu_xmac_stats) / sizeof(u64)); | |
6523 | } else { | |
6524 | memcpy(data, &np->mac_stats.bmac, | |
6525 | sizeof(struct niu_bmac_stats)); | |
6526 | data += (sizeof(struct niu_bmac_stats) / sizeof(u64)); | |
6527 | } | |
6528 | for (i = 0; i < np->num_rx_rings; i++) { | |
6529 | struct rx_ring_info *rp = &np->rx_rings[i]; | |
6530 | ||
6531 | data[0] = rp->rx_channel; | |
6532 | data[1] = rp->rx_packets; | |
6533 | data[2] = rp->rx_bytes; | |
6534 | data[3] = rp->rx_dropped; | |
6535 | data[4] = rp->rx_errors; | |
6536 | data += 5; | |
6537 | } | |
6538 | for (i = 0; i < np->num_tx_rings; i++) { | |
6539 | struct tx_ring_info *rp = &np->tx_rings[i]; | |
6540 | ||
6541 | data[0] = rp->tx_channel; | |
6542 | data[1] = rp->tx_packets; | |
6543 | data[2] = rp->tx_bytes; | |
6544 | data[3] = rp->tx_errors; | |
6545 | data += 4; | |
6546 | } | |
6547 | } | |
6548 | ||
6549 | static u64 niu_led_state_save(struct niu *np) | |
6550 | { | |
6551 | if (np->flags & NIU_FLAGS_XMAC) | |
6552 | return nr64_mac(XMAC_CONFIG); | |
6553 | else | |
6554 | return nr64_mac(BMAC_XIF_CONFIG); | |
6555 | } | |
6556 | ||
6557 | static void niu_led_state_restore(struct niu *np, u64 val) | |
6558 | { | |
6559 | if (np->flags & NIU_FLAGS_XMAC) | |
6560 | nw64_mac(XMAC_CONFIG, val); | |
6561 | else | |
6562 | nw64_mac(BMAC_XIF_CONFIG, val); | |
6563 | } | |
6564 | ||
6565 | static void niu_force_led(struct niu *np, int on) | |
6566 | { | |
6567 | u64 val, reg, bit; | |
6568 | ||
6569 | if (np->flags & NIU_FLAGS_XMAC) { | |
6570 | reg = XMAC_CONFIG; | |
6571 | bit = XMAC_CONFIG_FORCE_LED_ON; | |
6572 | } else { | |
6573 | reg = BMAC_XIF_CONFIG; | |
6574 | bit = BMAC_XIF_CONFIG_LINK_LED; | |
6575 | } | |
6576 | ||
6577 | val = nr64_mac(reg); | |
6578 | if (on) | |
6579 | val |= bit; | |
6580 | else | |
6581 | val &= ~bit; | |
6582 | nw64_mac(reg, val); | |
6583 | } | |
6584 | ||
6585 | static int niu_phys_id(struct net_device *dev, u32 data) | |
6586 | { | |
6587 | struct niu *np = netdev_priv(dev); | |
6588 | u64 orig_led_state; | |
6589 | int i; | |
6590 | ||
6591 | if (!netif_running(dev)) | |
6592 | return -EAGAIN; | |
6593 | ||
6594 | if (data == 0) | |
6595 | data = 2; | |
6596 | ||
6597 | orig_led_state = niu_led_state_save(np); | |
6598 | for (i = 0; i < (data * 2); i++) { | |
6599 | int on = ((i % 2) == 0); | |
6600 | ||
6601 | niu_force_led(np, on); | |
6602 | ||
6603 | if (msleep_interruptible(500)) | |
6604 | break; | |
6605 | } | |
6606 | niu_led_state_restore(np, orig_led_state); | |
6607 | ||
6608 | return 0; | |
6609 | } | |
6610 | ||
6611 | static const struct ethtool_ops niu_ethtool_ops = { | |
6612 | .get_drvinfo = niu_get_drvinfo, | |
6613 | .get_link = ethtool_op_get_link, | |
6614 | .get_msglevel = niu_get_msglevel, | |
6615 | .set_msglevel = niu_set_msglevel, | |
6616 | .get_eeprom_len = niu_get_eeprom_len, | |
6617 | .get_eeprom = niu_get_eeprom, | |
6618 | .get_settings = niu_get_settings, | |
6619 | .set_settings = niu_set_settings, | |
6620 | .get_strings = niu_get_strings, | |
6621 | .get_stats_count = niu_get_stats_count, | |
6622 | .get_ethtool_stats = niu_get_ethtool_stats, | |
6623 | .phys_id = niu_phys_id, | |
6624 | }; | |
6625 | ||
6626 | static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent, | |
6627 | int ldg, int ldn) | |
6628 | { | |
6629 | if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) | |
6630 | return -EINVAL; | |
6631 | if (ldn < 0 || ldn > LDN_MAX) | |
6632 | return -EINVAL; | |
6633 | ||
6634 | parent->ldg_map[ldn] = ldg; | |
6635 | ||
6636 | if (np->parent->plat_type == PLAT_TYPE_NIU) { | |
6637 | /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by | |
6638 | * the firmware, and we're not supposed to change them. | |
6639 | * Validate the mapping, because if it's wrong we probably | |
6640 | * won't get any interrupts and that's painful to debug. | |
6641 | */ | |
6642 | if (nr64(LDG_NUM(ldn)) != ldg) { | |
6643 | dev_err(np->device, PFX "Port %u, mis-matched " | |
6644 | "LDG assignment " | |
6645 | "for ldn %d, should be %d is %llu\n", | |
6646 | np->port, ldn, ldg, | |
6647 | (unsigned long long) nr64(LDG_NUM(ldn))); | |
6648 | return -EINVAL; | |
6649 | } | |
6650 | } else | |
6651 | nw64(LDG_NUM(ldn), ldg); | |
6652 | ||
6653 | return 0; | |
6654 | } | |
6655 | ||
6656 | static int niu_set_ldg_timer_res(struct niu *np, int res) | |
6657 | { | |
6658 | if (res < 0 || res > LDG_TIMER_RES_VAL) | |
6659 | return -EINVAL; | |
6660 | ||
6661 | ||
6662 | nw64(LDG_TIMER_RES, res); | |
6663 | ||
6664 | return 0; | |
6665 | } | |
6666 | ||
6667 | static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector) | |
6668 | { | |
6669 | if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) || | |
6670 | (func < 0 || func > 3) || | |
6671 | (vector < 0 || vector > 0x1f)) | |
6672 | return -EINVAL; | |
6673 | ||
6674 | nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector); | |
6675 | ||
6676 | return 0; | |
6677 | } | |
6678 | ||
6679 | static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr) | |
6680 | { | |
6681 | u64 frame, frame_base = (ESPC_PIO_STAT_READ_START | | |
6682 | (addr << ESPC_PIO_STAT_ADDR_SHIFT)); | |
6683 | int limit; | |
6684 | ||
6685 | if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT)) | |
6686 | return -EINVAL; | |
6687 | ||
6688 | frame = frame_base; | |
6689 | nw64(ESPC_PIO_STAT, frame); | |
6690 | limit = 64; | |
6691 | do { | |
6692 | udelay(5); | |
6693 | frame = nr64(ESPC_PIO_STAT); | |
6694 | if (frame & ESPC_PIO_STAT_READ_END) | |
6695 | break; | |
6696 | } while (limit--); | |
6697 | if (!(frame & ESPC_PIO_STAT_READ_END)) { | |
6698 | dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n", | |
6699 | (unsigned long long) frame); | |
6700 | return -ENODEV; | |
6701 | } | |
6702 | ||
6703 | frame = frame_base; | |
6704 | nw64(ESPC_PIO_STAT, frame); | |
6705 | limit = 64; | |
6706 | do { | |
6707 | udelay(5); | |
6708 | frame = nr64(ESPC_PIO_STAT); | |
6709 | if (frame & ESPC_PIO_STAT_READ_END) | |
6710 | break; | |
6711 | } while (limit--); | |
6712 | if (!(frame & ESPC_PIO_STAT_READ_END)) { | |
6713 | dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n", | |
6714 | (unsigned long long) frame); | |
6715 | return -ENODEV; | |
6716 | } | |
6717 | ||
6718 | frame = nr64(ESPC_PIO_STAT); | |
6719 | return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT; | |
6720 | } | |
6721 | ||
6722 | static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off) | |
6723 | { | |
6724 | int err = niu_pci_eeprom_read(np, off); | |
6725 | u16 val; | |
6726 | ||
6727 | if (err < 0) | |
6728 | return err; | |
6729 | val = (err << 8); | |
6730 | err = niu_pci_eeprom_read(np, off + 1); | |
6731 | if (err < 0) | |
6732 | return err; | |
6733 | val |= (err & 0xff); | |
6734 | ||
6735 | return val; | |
6736 | } | |
6737 | ||
6738 | static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off) | |
6739 | { | |
6740 | int err = niu_pci_eeprom_read(np, off); | |
6741 | u16 val; | |
6742 | ||
6743 | if (err < 0) | |
6744 | return err; | |
6745 | ||
6746 | val = (err & 0xff); | |
6747 | err = niu_pci_eeprom_read(np, off + 1); | |
6748 | if (err < 0) | |
6749 | return err; | |
6750 | ||
6751 | val |= (err & 0xff) << 8; | |
6752 | ||
6753 | return val; | |
6754 | } | |
6755 | ||
6756 | static int __devinit niu_pci_vpd_get_propname(struct niu *np, | |
6757 | u32 off, | |
6758 | char *namebuf, | |
6759 | int namebuf_len) | |
6760 | { | |
6761 | int i; | |
6762 | ||
6763 | for (i = 0; i < namebuf_len; i++) { | |
6764 | int err = niu_pci_eeprom_read(np, off + i); | |
6765 | if (err < 0) | |
6766 | return err; | |
6767 | *namebuf++ = err; | |
6768 | if (!err) | |
6769 | break; | |
6770 | } | |
6771 | if (i >= namebuf_len) | |
6772 | return -EINVAL; | |
6773 | ||
6774 | return i + 1; | |
6775 | } | |
6776 | ||
6777 | static void __devinit niu_vpd_parse_version(struct niu *np) | |
6778 | { | |
6779 | struct niu_vpd *vpd = &np->vpd; | |
6780 | int len = strlen(vpd->version) + 1; | |
6781 | const char *s = vpd->version; | |
6782 | int i; | |
6783 | ||
6784 | for (i = 0; i < len - 5; i++) { | |
6785 | if (!strncmp(s + i, "FCode ", 5)) | |
6786 | break; | |
6787 | } | |
6788 | if (i >= len - 5) | |
6789 | return; | |
6790 | ||
6791 | s += i + 5; | |
6792 | sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor); | |
6793 | ||
6794 | niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n", | |
6795 | vpd->fcode_major, vpd->fcode_minor); | |
6796 | if (vpd->fcode_major > NIU_VPD_MIN_MAJOR || | |
6797 | (vpd->fcode_major == NIU_VPD_MIN_MAJOR && | |
6798 | vpd->fcode_minor >= NIU_VPD_MIN_MINOR)) | |
6799 | np->flags |= NIU_FLAGS_VPD_VALID; | |
6800 | } | |
6801 | ||
6802 | /* ESPC_PIO_EN_ENABLE must be set */ | |
6803 | static int __devinit niu_pci_vpd_scan_props(struct niu *np, | |
6804 | u32 start, u32 end) | |
6805 | { | |
6806 | unsigned int found_mask = 0; | |
6807 | #define FOUND_MASK_MODEL 0x00000001 | |
6808 | #define FOUND_MASK_BMODEL 0x00000002 | |
6809 | #define FOUND_MASK_VERS 0x00000004 | |
6810 | #define FOUND_MASK_MAC 0x00000008 | |
6811 | #define FOUND_MASK_NMAC 0x00000010 | |
6812 | #define FOUND_MASK_PHY 0x00000020 | |
6813 | #define FOUND_MASK_ALL 0x0000003f | |
6814 | ||
6815 | niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n", | |
6816 | start, end); | |
6817 | while (start < end) { | |
6818 | int len, err, instance, type, prop_len; | |
6819 | char namebuf[64]; | |
6820 | u8 *prop_buf; | |
6821 | int max_len; | |
6822 | ||
6823 | if (found_mask == FOUND_MASK_ALL) { | |
6824 | niu_vpd_parse_version(np); | |
6825 | return 1; | |
6826 | } | |
6827 | ||
6828 | err = niu_pci_eeprom_read(np, start + 2); | |
6829 | if (err < 0) | |
6830 | return err; | |
6831 | len = err; | |
6832 | start += 3; | |
6833 | ||
6834 | instance = niu_pci_eeprom_read(np, start); | |
6835 | type = niu_pci_eeprom_read(np, start + 3); | |
6836 | prop_len = niu_pci_eeprom_read(np, start + 4); | |
6837 | err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64); | |
6838 | if (err < 0) | |
6839 | return err; | |
6840 | ||
6841 | prop_buf = NULL; | |
6842 | max_len = 0; | |
6843 | if (!strcmp(namebuf, "model")) { | |
6844 | prop_buf = np->vpd.model; | |
6845 | max_len = NIU_VPD_MODEL_MAX; | |
6846 | found_mask |= FOUND_MASK_MODEL; | |
6847 | } else if (!strcmp(namebuf, "board-model")) { | |
6848 | prop_buf = np->vpd.board_model; | |
6849 | max_len = NIU_VPD_BD_MODEL_MAX; | |
6850 | found_mask |= FOUND_MASK_BMODEL; | |
6851 | } else if (!strcmp(namebuf, "version")) { | |
6852 | prop_buf = np->vpd.version; | |
6853 | max_len = NIU_VPD_VERSION_MAX; | |
6854 | found_mask |= FOUND_MASK_VERS; | |
6855 | } else if (!strcmp(namebuf, "local-mac-address")) { | |
6856 | prop_buf = np->vpd.local_mac; | |
6857 | max_len = ETH_ALEN; | |
6858 | found_mask |= FOUND_MASK_MAC; | |
6859 | } else if (!strcmp(namebuf, "num-mac-addresses")) { | |
6860 | prop_buf = &np->vpd.mac_num; | |
6861 | max_len = 1; | |
6862 | found_mask |= FOUND_MASK_NMAC; | |
6863 | } else if (!strcmp(namebuf, "phy-type")) { | |
6864 | prop_buf = np->vpd.phy_type; | |
6865 | max_len = NIU_VPD_PHY_TYPE_MAX; | |
6866 | found_mask |= FOUND_MASK_PHY; | |
6867 | } | |
6868 | ||
6869 | if (max_len && prop_len > max_len) { | |
6870 | dev_err(np->device, PFX "Property '%s' length (%d) is " | |
6871 | "too long.\n", namebuf, prop_len); | |
6872 | return -EINVAL; | |
6873 | } | |
6874 | ||
6875 | if (prop_buf) { | |
6876 | u32 off = start + 5 + err; | |
6877 | int i; | |
6878 | ||
6879 | niudbg(PROBE, "VPD_SCAN: Reading in property [%s] " | |
6880 | "len[%d]\n", namebuf, prop_len); | |
6881 | for (i = 0; i < prop_len; i++) | |
6882 | *prop_buf++ = niu_pci_eeprom_read(np, off + i); | |
6883 | } | |
6884 | ||
6885 | start += len; | |
6886 | } | |
6887 | ||
6888 | return 0; | |
6889 | } | |
6890 | ||
6891 | /* ESPC_PIO_EN_ENABLE must be set */ | |
6892 | static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start) | |
6893 | { | |
6894 | u32 offset; | |
6895 | int err; | |
6896 | ||
6897 | err = niu_pci_eeprom_read16_swp(np, start + 1); | |
6898 | if (err < 0) | |
6899 | return; | |
6900 | ||
6901 | offset = err + 3; | |
6902 | ||
6903 | while (start + offset < ESPC_EEPROM_SIZE) { | |
6904 | u32 here = start + offset; | |
6905 | u32 end; | |
6906 | ||
6907 | err = niu_pci_eeprom_read(np, here); | |
6908 | if (err != 0x90) | |
6909 | return; | |
6910 | ||
6911 | err = niu_pci_eeprom_read16_swp(np, here + 1); | |
6912 | if (err < 0) | |
6913 | return; | |
6914 | ||
6915 | here = start + offset + 3; | |
6916 | end = start + offset + err; | |
6917 | ||
6918 | offset += err; | |
6919 | ||
6920 | err = niu_pci_vpd_scan_props(np, here, end); | |
6921 | if (err < 0 || err == 1) | |
6922 | return; | |
6923 | } | |
6924 | } | |
6925 | ||
6926 | /* ESPC_PIO_EN_ENABLE must be set */ | |
6927 | static u32 __devinit niu_pci_vpd_offset(struct niu *np) | |
6928 | { | |
6929 | u32 start = 0, end = ESPC_EEPROM_SIZE, ret; | |
6930 | int err; | |
6931 | ||
6932 | while (start < end) { | |
6933 | ret = start; | |
6934 | ||
6935 | /* ROM header signature? */ | |
6936 | err = niu_pci_eeprom_read16(np, start + 0); | |
6937 | if (err != 0x55aa) | |
6938 | return 0; | |
6939 | ||
6940 | /* Apply offset to PCI data structure. */ | |
6941 | err = niu_pci_eeprom_read16(np, start + 23); | |
6942 | if (err < 0) | |
6943 | return 0; | |
6944 | start += err; | |
6945 | ||
6946 | /* Check for "PCIR" signature. */ | |
6947 | err = niu_pci_eeprom_read16(np, start + 0); | |
6948 | if (err != 0x5043) | |
6949 | return 0; | |
6950 | err = niu_pci_eeprom_read16(np, start + 2); | |
6951 | if (err != 0x4952) | |
6952 | return 0; | |
6953 | ||
6954 | /* Check for OBP image type. */ | |
6955 | err = niu_pci_eeprom_read(np, start + 20); | |
6956 | if (err < 0) | |
6957 | return 0; | |
6958 | if (err != 0x01) { | |
6959 | err = niu_pci_eeprom_read(np, ret + 2); | |
6960 | if (err < 0) | |
6961 | return 0; | |
6962 | ||
6963 | start = ret + (err * 512); | |
6964 | continue; | |
6965 | } | |
6966 | ||
6967 | err = niu_pci_eeprom_read16_swp(np, start + 8); | |
6968 | if (err < 0) | |
6969 | return err; | |
6970 | ret += err; | |
6971 | ||
6972 | err = niu_pci_eeprom_read(np, ret + 0); | |
6973 | if (err != 0x82) | |
6974 | return 0; | |
6975 | ||
6976 | return ret; | |
6977 | } | |
6978 | ||
6979 | return 0; | |
6980 | } | |
6981 | ||
6982 | static int __devinit niu_phy_type_prop_decode(struct niu *np, | |
6983 | const char *phy_prop) | |
6984 | { | |
6985 | if (!strcmp(phy_prop, "mif")) { | |
6986 | /* 1G copper, MII */ | |
6987 | np->flags &= ~(NIU_FLAGS_FIBER | | |
6988 | NIU_FLAGS_10G); | |
6989 | np->mac_xcvr = MAC_XCVR_MII; | |
6990 | } else if (!strcmp(phy_prop, "xgf")) { | |
6991 | /* 10G fiber, XPCS */ | |
6992 | np->flags |= (NIU_FLAGS_10G | | |
6993 | NIU_FLAGS_FIBER); | |
6994 | np->mac_xcvr = MAC_XCVR_XPCS; | |
6995 | } else if (!strcmp(phy_prop, "pcs")) { | |
6996 | /* 1G fiber, PCS */ | |
6997 | np->flags &= ~NIU_FLAGS_10G; | |
6998 | np->flags |= NIU_FLAGS_FIBER; | |
6999 | np->mac_xcvr = MAC_XCVR_PCS; | |
7000 | } else if (!strcmp(phy_prop, "xgc")) { | |
7001 | /* 10G copper, XPCS */ | |
7002 | np->flags |= NIU_FLAGS_10G; | |
7003 | np->flags &= ~NIU_FLAGS_FIBER; | |
7004 | np->mac_xcvr = MAC_XCVR_XPCS; | |
7005 | } else { | |
7006 | return -EINVAL; | |
7007 | } | |
7008 | return 0; | |
7009 | } | |
7010 | ||
7f7c4072 MW |
7011 | /* niu board models have a trailing dash version incremented |
7012 | * with HW rev change. Need to ingnore the dash version while | |
7013 | * checking for match | |
7014 | * | |
7015 | * for example, for the 10G card the current vpd.board_model | |
7016 | * is 501-5283-04, of which -04 is the dash version and have | |
7017 | * to be ignored | |
7018 | */ | |
7019 | static int niu_board_model_match(struct niu *np, const char *model) | |
7020 | { | |
7021 | return !strncmp(np->vpd.board_model, model, strlen(model)); | |
7022 | } | |
7023 | ||
7024 | static int niu_pci_vpd_get_nports(struct niu *np) | |
7025 | { | |
7026 | int ports = 0; | |
7027 | ||
7028 | if ((niu_board_model_match(np, NIU_QGC_LP_BM_STR)) || | |
7029 | (niu_board_model_match(np, NIU_QGC_PEM_BM_STR)) || | |
7030 | (niu_board_model_match(np, NIU_ALONSO_BM_STR))) { | |
7031 | ports = 4; | |
7032 | } else if ((niu_board_model_match(np, NIU_2XGF_LP_BM_STR)) || | |
7033 | (niu_board_model_match(np, NIU_2XGF_PEM_BM_STR)) || | |
7034 | (niu_board_model_match(np, NIU_FOXXY_BM_STR)) || | |
7035 | (niu_board_model_match(np, NIU_2XGF_MRVL_BM_STR))) { | |
7036 | ports = 2; | |
7037 | } | |
7038 | ||
7039 | return ports; | |
7040 | } | |
7041 | ||
a3138df9 DM |
7042 | static void __devinit niu_pci_vpd_validate(struct niu *np) |
7043 | { | |
7044 | struct net_device *dev = np->dev; | |
7045 | struct niu_vpd *vpd = &np->vpd; | |
7046 | u8 val8; | |
7047 | ||
7048 | if (!is_valid_ether_addr(&vpd->local_mac[0])) { | |
7049 | dev_err(np->device, PFX "VPD MAC invalid, " | |
7050 | "falling back to SPROM.\n"); | |
7051 | ||
7052 | np->flags &= ~NIU_FLAGS_VPD_VALID; | |
7053 | return; | |
7054 | } | |
7055 | ||
5fbd7e24 MW |
7056 | if (!strcmp(np->vpd.model, "SUNW,CP3220") || |
7057 | !strcmp(np->vpd.model, "SUNW,CP3260")) { | |
7058 | np->flags |= NIU_FLAGS_10G; | |
7059 | np->flags &= ~NIU_FLAGS_FIBER; | |
7060 | np->flags |= NIU_FLAGS_XCVR_SERDES; | |
7061 | np->mac_xcvr = MAC_XCVR_PCS; | |
7062 | if (np->port > 1) { | |
7063 | np->flags |= NIU_FLAGS_FIBER; | |
7064 | np->flags &= ~NIU_FLAGS_10G; | |
7065 | } | |
7066 | if (np->flags & NIU_FLAGS_10G) | |
7067 | np->mac_xcvr = MAC_XCVR_XPCS; | |
a5d6ab56 MW |
7068 | } else if (niu_board_model_match(np, NIU_FOXXY_BM_STR)) { |
7069 | np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | | |
7070 | NIU_FLAGS_HOTPLUG_PHY); | |
5fbd7e24 | 7071 | } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { |
a3138df9 DM |
7072 | dev_err(np->device, PFX "Illegal phy string [%s].\n", |
7073 | np->vpd.phy_type); | |
7074 | dev_err(np->device, PFX "Falling back to SPROM.\n"); | |
7075 | np->flags &= ~NIU_FLAGS_VPD_VALID; | |
7076 | return; | |
7077 | } | |
7078 | ||
7079 | memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN); | |
7080 | ||
7081 | val8 = dev->perm_addr[5]; | |
7082 | dev->perm_addr[5] += np->port; | |
7083 | if (dev->perm_addr[5] < val8) | |
7084 | dev->perm_addr[4]++; | |
7085 | ||
7086 | memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); | |
7087 | } | |
7088 | ||
7089 | static int __devinit niu_pci_probe_sprom(struct niu *np) | |
7090 | { | |
7091 | struct net_device *dev = np->dev; | |
7092 | int len, i; | |
7093 | u64 val, sum; | |
7094 | u8 val8; | |
7095 | ||
7096 | val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ); | |
7097 | val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT; | |
7098 | len = val / 4; | |
7099 | ||
7100 | np->eeprom_len = len; | |
7101 | ||
7102 | niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val); | |
7103 | ||
7104 | sum = 0; | |
7105 | for (i = 0; i < len; i++) { | |
7106 | val = nr64(ESPC_NCR(i)); | |
7107 | sum += (val >> 0) & 0xff; | |
7108 | sum += (val >> 8) & 0xff; | |
7109 | sum += (val >> 16) & 0xff; | |
7110 | sum += (val >> 24) & 0xff; | |
7111 | } | |
7112 | niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff)); | |
7113 | if ((sum & 0xff) != 0xab) { | |
7114 | dev_err(np->device, PFX "Bad SPROM checksum " | |
7115 | "(%x, should be 0xab)\n", (int) (sum & 0xff)); | |
7116 | return -EINVAL; | |
7117 | } | |
7118 | ||
7119 | val = nr64(ESPC_PHY_TYPE); | |
7120 | switch (np->port) { | |
7121 | case 0: | |
a9d41192 | 7122 | val8 = (val & ESPC_PHY_TYPE_PORT0) >> |
a3138df9 DM |
7123 | ESPC_PHY_TYPE_PORT0_SHIFT; |
7124 | break; | |
7125 | case 1: | |
a9d41192 | 7126 | val8 = (val & ESPC_PHY_TYPE_PORT1) >> |
a3138df9 DM |
7127 | ESPC_PHY_TYPE_PORT1_SHIFT; |
7128 | break; | |
7129 | case 2: | |
a9d41192 | 7130 | val8 = (val & ESPC_PHY_TYPE_PORT2) >> |
a3138df9 DM |
7131 | ESPC_PHY_TYPE_PORT2_SHIFT; |
7132 | break; | |
7133 | case 3: | |
a9d41192 | 7134 | val8 = (val & ESPC_PHY_TYPE_PORT3) >> |
a3138df9 DM |
7135 | ESPC_PHY_TYPE_PORT3_SHIFT; |
7136 | break; | |
7137 | default: | |
7138 | dev_err(np->device, PFX "Bogus port number %u\n", | |
7139 | np->port); | |
7140 | return -EINVAL; | |
7141 | } | |
a9d41192 | 7142 | niudbg(PROBE, "SPROM: PHY type %x\n", val8); |
a3138df9 | 7143 | |
a9d41192 | 7144 | switch (val8) { |
a3138df9 DM |
7145 | case ESPC_PHY_TYPE_1G_COPPER: |
7146 | /* 1G copper, MII */ | |
7147 | np->flags &= ~(NIU_FLAGS_FIBER | | |
7148 | NIU_FLAGS_10G); | |
7149 | np->mac_xcvr = MAC_XCVR_MII; | |
7150 | break; | |
7151 | ||
7152 | case ESPC_PHY_TYPE_1G_FIBER: | |
7153 | /* 1G fiber, PCS */ | |
7154 | np->flags &= ~NIU_FLAGS_10G; | |
7155 | np->flags |= NIU_FLAGS_FIBER; | |
7156 | np->mac_xcvr = MAC_XCVR_PCS; | |
7157 | break; | |
7158 | ||
7159 | case ESPC_PHY_TYPE_10G_COPPER: | |
7160 | /* 10G copper, XPCS */ | |
7161 | np->flags |= NIU_FLAGS_10G; | |
7162 | np->flags &= ~NIU_FLAGS_FIBER; | |
7163 | np->mac_xcvr = MAC_XCVR_XPCS; | |
7164 | break; | |
7165 | ||
7166 | case ESPC_PHY_TYPE_10G_FIBER: | |
7167 | /* 10G fiber, XPCS */ | |
7168 | np->flags |= (NIU_FLAGS_10G | | |
7169 | NIU_FLAGS_FIBER); | |
7170 | np->mac_xcvr = MAC_XCVR_XPCS; | |
7171 | break; | |
7172 | ||
7173 | default: | |
a9d41192 | 7174 | dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8); |
a3138df9 DM |
7175 | return -EINVAL; |
7176 | } | |
7177 | ||
7178 | val = nr64(ESPC_MAC_ADDR0); | |
7179 | niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n", | |
7180 | (unsigned long long) val); | |
7181 | dev->perm_addr[0] = (val >> 0) & 0xff; | |
7182 | dev->perm_addr[1] = (val >> 8) & 0xff; | |
7183 | dev->perm_addr[2] = (val >> 16) & 0xff; | |
7184 | dev->perm_addr[3] = (val >> 24) & 0xff; | |
7185 | ||
7186 | val = nr64(ESPC_MAC_ADDR1); | |
7187 | niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n", | |
7188 | (unsigned long long) val); | |
7189 | dev->perm_addr[4] = (val >> 0) & 0xff; | |
7190 | dev->perm_addr[5] = (val >> 8) & 0xff; | |
7191 | ||
7192 | if (!is_valid_ether_addr(&dev->perm_addr[0])) { | |
7193 | dev_err(np->device, PFX "SPROM MAC address invalid\n"); | |
7194 | dev_err(np->device, PFX "[ \n"); | |
7195 | for (i = 0; i < 6; i++) | |
7196 | printk("%02x ", dev->perm_addr[i]); | |
7197 | printk("]\n"); | |
7198 | return -EINVAL; | |
7199 | } | |
7200 | ||
7201 | val8 = dev->perm_addr[5]; | |
7202 | dev->perm_addr[5] += np->port; | |
7203 | if (dev->perm_addr[5] < val8) | |
7204 | dev->perm_addr[4]++; | |
7205 | ||
7206 | memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); | |
7207 | ||
7208 | val = nr64(ESPC_MOD_STR_LEN); | |
7209 | niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n", | |
7210 | (unsigned long long) val); | |
e6a5fdf5 | 7211 | if (val >= 8 * 4) |
a3138df9 DM |
7212 | return -EINVAL; |
7213 | ||
7214 | for (i = 0; i < val; i += 4) { | |
7215 | u64 tmp = nr64(ESPC_NCR(5 + (i / 4))); | |
7216 | ||
7217 | np->vpd.model[i + 3] = (tmp >> 0) & 0xff; | |
7218 | np->vpd.model[i + 2] = (tmp >> 8) & 0xff; | |
7219 | np->vpd.model[i + 1] = (tmp >> 16) & 0xff; | |
7220 | np->vpd.model[i + 0] = (tmp >> 24) & 0xff; | |
7221 | } | |
7222 | np->vpd.model[val] = '\0'; | |
7223 | ||
7224 | val = nr64(ESPC_BD_MOD_STR_LEN); | |
7225 | niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n", | |
7226 | (unsigned long long) val); | |
e6a5fdf5 | 7227 | if (val >= 4 * 4) |
a3138df9 DM |
7228 | return -EINVAL; |
7229 | ||
7230 | for (i = 0; i < val; i += 4) { | |
7231 | u64 tmp = nr64(ESPC_NCR(14 + (i / 4))); | |
7232 | ||
7233 | np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff; | |
7234 | np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff; | |
7235 | np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff; | |
7236 | np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff; | |
7237 | } | |
7238 | np->vpd.board_model[val] = '\0'; | |
7239 | ||
7240 | np->vpd.mac_num = | |
7241 | nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL; | |
7242 | niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n", | |
7243 | np->vpd.mac_num); | |
7244 | ||
7245 | return 0; | |
7246 | } | |
7247 | ||
7248 | static int __devinit niu_get_and_validate_port(struct niu *np) | |
7249 | { | |
7250 | struct niu_parent *parent = np->parent; | |
7251 | ||
7252 | if (np->port <= 1) | |
7253 | np->flags |= NIU_FLAGS_XMAC; | |
7254 | ||
7255 | if (!parent->num_ports) { | |
7256 | if (parent->plat_type == PLAT_TYPE_NIU) { | |
7257 | parent->num_ports = 2; | |
7258 | } else { | |
7f7c4072 MW |
7259 | parent->num_ports = niu_pci_vpd_get_nports(np); |
7260 | if (!parent->num_ports) { | |
7261 | /* Fall back to SPROM as last resort. | |
7262 | * This will fail on most cards. | |
7263 | */ | |
7264 | parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) & | |
7265 | ESPC_NUM_PORTS_MACS_VAL; | |
7266 | ||
7267 | if (!parent->num_ports) | |
7268 | return -ENODEV; | |
7269 | } | |
a3138df9 DM |
7270 | } |
7271 | } | |
7272 | ||
7273 | niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n", | |
7274 | np->port, parent->num_ports); | |
7275 | if (np->port >= parent->num_ports) | |
7276 | return -ENODEV; | |
7277 | ||
7278 | return 0; | |
7279 | } | |
7280 | ||
7281 | static int __devinit phy_record(struct niu_parent *parent, | |
7282 | struct phy_probe_info *p, | |
7283 | int dev_id_1, int dev_id_2, u8 phy_port, | |
7284 | int type) | |
7285 | { | |
7286 | u32 id = (dev_id_1 << 16) | dev_id_2; | |
7287 | u8 idx; | |
7288 | ||
7289 | if (dev_id_1 < 0 || dev_id_2 < 0) | |
7290 | return 0; | |
7291 | if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) { | |
b0de8e40 | 7292 | if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) && |
a5d6ab56 MW |
7293 | ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) && |
7294 | ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706)) | |
a3138df9 DM |
7295 | return 0; |
7296 | } else { | |
7297 | if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R) | |
7298 | return 0; | |
7299 | } | |
7300 | ||
7301 | pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n", | |
7302 | parent->index, id, | |
7303 | (type == PHY_TYPE_PMA_PMD ? | |
7304 | "PMA/PMD" : | |
7305 | (type == PHY_TYPE_PCS ? | |
7306 | "PCS" : "MII")), | |
7307 | phy_port); | |
7308 | ||
7309 | if (p->cur[type] >= NIU_MAX_PORTS) { | |
7310 | printk(KERN_ERR PFX "Too many PHY ports.\n"); | |
7311 | return -EINVAL; | |
7312 | } | |
7313 | idx = p->cur[type]; | |
7314 | p->phy_id[type][idx] = id; | |
7315 | p->phy_port[type][idx] = phy_port; | |
7316 | p->cur[type] = idx + 1; | |
7317 | return 0; | |
7318 | } | |
7319 | ||
7320 | static int __devinit port_has_10g(struct phy_probe_info *p, int port) | |
7321 | { | |
7322 | int i; | |
7323 | ||
7324 | for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) { | |
7325 | if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port) | |
7326 | return 1; | |
7327 | } | |
7328 | for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) { | |
7329 | if (p->phy_port[PHY_TYPE_PCS][i] == port) | |
7330 | return 1; | |
7331 | } | |
7332 | ||
7333 | return 0; | |
7334 | } | |
7335 | ||
7336 | static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest) | |
7337 | { | |
7338 | int port, cnt; | |
7339 | ||
7340 | cnt = 0; | |
7341 | *lowest = 32; | |
7342 | for (port = 8; port < 32; port++) { | |
7343 | if (port_has_10g(p, port)) { | |
7344 | if (!cnt) | |
7345 | *lowest = port; | |
7346 | cnt++; | |
7347 | } | |
7348 | } | |
7349 | ||
7350 | return cnt; | |
7351 | } | |
7352 | ||
7353 | static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest) | |
7354 | { | |
7355 | *lowest = 32; | |
7356 | if (p->cur[PHY_TYPE_MII]) | |
7357 | *lowest = p->phy_port[PHY_TYPE_MII][0]; | |
7358 | ||
7359 | return p->cur[PHY_TYPE_MII]; | |
7360 | } | |
7361 | ||
7362 | static void __devinit niu_n2_divide_channels(struct niu_parent *parent) | |
7363 | { | |
7364 | int num_ports = parent->num_ports; | |
7365 | int i; | |
7366 | ||
7367 | for (i = 0; i < num_ports; i++) { | |
7368 | parent->rxchan_per_port[i] = (16 / num_ports); | |
7369 | parent->txchan_per_port[i] = (16 / num_ports); | |
7370 | ||
7371 | pr_info(PFX "niu%d: Port %u [%u RX chans] " | |
7372 | "[%u TX chans]\n", | |
7373 | parent->index, i, | |
7374 | parent->rxchan_per_port[i], | |
7375 | parent->txchan_per_port[i]); | |
7376 | } | |
7377 | } | |
7378 | ||
7379 | static void __devinit niu_divide_channels(struct niu_parent *parent, | |
7380 | int num_10g, int num_1g) | |
7381 | { | |
7382 | int num_ports = parent->num_ports; | |
7383 | int rx_chans_per_10g, rx_chans_per_1g; | |
7384 | int tx_chans_per_10g, tx_chans_per_1g; | |
7385 | int i, tot_rx, tot_tx; | |
7386 | ||
7387 | if (!num_10g || !num_1g) { | |
7388 | rx_chans_per_10g = rx_chans_per_1g = | |
7389 | (NIU_NUM_RXCHAN / num_ports); | |
7390 | tx_chans_per_10g = tx_chans_per_1g = | |
7391 | (NIU_NUM_TXCHAN / num_ports); | |
7392 | } else { | |
7393 | rx_chans_per_1g = NIU_NUM_RXCHAN / 8; | |
7394 | rx_chans_per_10g = (NIU_NUM_RXCHAN - | |
7395 | (rx_chans_per_1g * num_1g)) / | |
7396 | num_10g; | |
7397 | ||
7398 | tx_chans_per_1g = NIU_NUM_TXCHAN / 6; | |
7399 | tx_chans_per_10g = (NIU_NUM_TXCHAN - | |
7400 | (tx_chans_per_1g * num_1g)) / | |
7401 | num_10g; | |
7402 | } | |
7403 | ||
7404 | tot_rx = tot_tx = 0; | |
7405 | for (i = 0; i < num_ports; i++) { | |
7406 | int type = phy_decode(parent->port_phy, i); | |
7407 | ||
7408 | if (type == PORT_TYPE_10G) { | |
7409 | parent->rxchan_per_port[i] = rx_chans_per_10g; | |
7410 | parent->txchan_per_port[i] = tx_chans_per_10g; | |
7411 | } else { | |
7412 | parent->rxchan_per_port[i] = rx_chans_per_1g; | |
7413 | parent->txchan_per_port[i] = tx_chans_per_1g; | |
7414 | } | |
7415 | pr_info(PFX "niu%d: Port %u [%u RX chans] " | |
7416 | "[%u TX chans]\n", | |
7417 | parent->index, i, | |
7418 | parent->rxchan_per_port[i], | |
7419 | parent->txchan_per_port[i]); | |
7420 | tot_rx += parent->rxchan_per_port[i]; | |
7421 | tot_tx += parent->txchan_per_port[i]; | |
7422 | } | |
7423 | ||
7424 | if (tot_rx > NIU_NUM_RXCHAN) { | |
7425 | printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), " | |
7426 | "resetting to one per port.\n", | |
7427 | parent->index, tot_rx); | |
7428 | for (i = 0; i < num_ports; i++) | |
7429 | parent->rxchan_per_port[i] = 1; | |
7430 | } | |
7431 | if (tot_tx > NIU_NUM_TXCHAN) { | |
7432 | printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), " | |
7433 | "resetting to one per port.\n", | |
7434 | parent->index, tot_tx); | |
7435 | for (i = 0; i < num_ports; i++) | |
7436 | parent->txchan_per_port[i] = 1; | |
7437 | } | |
7438 | if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) { | |
7439 | printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, " | |
7440 | "RX[%d] TX[%d]\n", | |
7441 | parent->index, tot_rx, tot_tx); | |
7442 | } | |
7443 | } | |
7444 | ||
7445 | static void __devinit niu_divide_rdc_groups(struct niu_parent *parent, | |
7446 | int num_10g, int num_1g) | |
7447 | { | |
7448 | int i, num_ports = parent->num_ports; | |
7449 | int rdc_group, rdc_groups_per_port; | |
7450 | int rdc_channel_base; | |
7451 | ||
7452 | rdc_group = 0; | |
7453 | rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports; | |
7454 | ||
7455 | rdc_channel_base = 0; | |
7456 | ||
7457 | for (i = 0; i < num_ports; i++) { | |
7458 | struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i]; | |
7459 | int grp, num_channels = parent->rxchan_per_port[i]; | |
7460 | int this_channel_offset; | |
7461 | ||
7462 | tp->first_table_num = rdc_group; | |
7463 | tp->num_tables = rdc_groups_per_port; | |
7464 | this_channel_offset = 0; | |
7465 | for (grp = 0; grp < tp->num_tables; grp++) { | |
7466 | struct rdc_table *rt = &tp->tables[grp]; | |
7467 | int slot; | |
7468 | ||
7469 | pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ", | |
7470 | parent->index, i, tp->first_table_num + grp); | |
7471 | for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) { | |
7472 | rt->rxdma_channel[slot] = | |
7473 | rdc_channel_base + this_channel_offset; | |
7474 | ||
7475 | printk("%d ", rt->rxdma_channel[slot]); | |
7476 | ||
7477 | if (++this_channel_offset == num_channels) | |
7478 | this_channel_offset = 0; | |
7479 | } | |
7480 | printk("]\n"); | |
7481 | } | |
7482 | ||
7483 | parent->rdc_default[i] = rdc_channel_base; | |
7484 | ||
7485 | rdc_channel_base += num_channels; | |
7486 | rdc_group += rdc_groups_per_port; | |
7487 | } | |
7488 | } | |
7489 | ||
7490 | static int __devinit fill_phy_probe_info(struct niu *np, | |
7491 | struct niu_parent *parent, | |
7492 | struct phy_probe_info *info) | |
7493 | { | |
7494 | unsigned long flags; | |
7495 | int port, err; | |
7496 | ||
7497 | memset(info, 0, sizeof(*info)); | |
7498 | ||
7499 | /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */ | |
7500 | niu_lock_parent(np, flags); | |
7501 | err = 0; | |
7502 | for (port = 8; port < 32; port++) { | |
7503 | int dev_id_1, dev_id_2; | |
7504 | ||
7505 | dev_id_1 = mdio_read(np, port, | |
7506 | NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1); | |
7507 | dev_id_2 = mdio_read(np, port, | |
7508 | NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2); | |
7509 | err = phy_record(parent, info, dev_id_1, dev_id_2, port, | |
7510 | PHY_TYPE_PMA_PMD); | |
7511 | if (err) | |
7512 | break; | |
7513 | dev_id_1 = mdio_read(np, port, | |
7514 | NIU_PCS_DEV_ADDR, MII_PHYSID1); | |
7515 | dev_id_2 = mdio_read(np, port, | |
7516 | NIU_PCS_DEV_ADDR, MII_PHYSID2); | |
7517 | err = phy_record(parent, info, dev_id_1, dev_id_2, port, | |
7518 | PHY_TYPE_PCS); | |
7519 | if (err) | |
7520 | break; | |
7521 | dev_id_1 = mii_read(np, port, MII_PHYSID1); | |
7522 | dev_id_2 = mii_read(np, port, MII_PHYSID2); | |
7523 | err = phy_record(parent, info, dev_id_1, dev_id_2, port, | |
7524 | PHY_TYPE_MII); | |
7525 | if (err) | |
7526 | break; | |
7527 | } | |
7528 | niu_unlock_parent(np, flags); | |
7529 | ||
7530 | return err; | |
7531 | } | |
7532 | ||
7533 | static int __devinit walk_phys(struct niu *np, struct niu_parent *parent) | |
7534 | { | |
7535 | struct phy_probe_info *info = &parent->phy_probe_info; | |
7536 | int lowest_10g, lowest_1g; | |
7537 | int num_10g, num_1g; | |
7538 | u32 val; | |
7539 | int err; | |
7540 | ||
5fbd7e24 MW |
7541 | if (!strcmp(np->vpd.model, "SUNW,CP3220") || |
7542 | !strcmp(np->vpd.model, "SUNW,CP3260")) { | |
7543 | num_10g = 0; | |
7544 | num_1g = 2; | |
7545 | parent->plat_type = PLAT_TYPE_ATCA_CP3220; | |
7546 | parent->num_ports = 4; | |
7547 | val = (phy_encode(PORT_TYPE_1G, 0) | | |
7548 | phy_encode(PORT_TYPE_1G, 1) | | |
a3138df9 DM |
7549 | phy_encode(PORT_TYPE_1G, 2) | |
7550 | phy_encode(PORT_TYPE_1G, 3)); | |
a5d6ab56 MW |
7551 | } else if (niu_board_model_match(np, NIU_FOXXY_BM_STR)) { |
7552 | num_10g = 2; | |
7553 | num_1g = 0; | |
7554 | parent->num_ports = 2; | |
7555 | val = (phy_encode(PORT_TYPE_10G, 0) | | |
7556 | phy_encode(PORT_TYPE_10G, 1)); | |
5fbd7e24 MW |
7557 | } else { |
7558 | err = fill_phy_probe_info(np, parent, info); | |
7559 | if (err) | |
7560 | return err; | |
a3138df9 | 7561 | |
5fbd7e24 MW |
7562 | num_10g = count_10g_ports(info, &lowest_10g); |
7563 | num_1g = count_1g_ports(info, &lowest_1g); | |
a3138df9 | 7564 | |
5fbd7e24 MW |
7565 | switch ((num_10g << 4) | num_1g) { |
7566 | case 0x24: | |
7567 | if (lowest_1g == 10) | |
7568 | parent->plat_type = PLAT_TYPE_VF_P0; | |
7569 | else if (lowest_1g == 26) | |
7570 | parent->plat_type = PLAT_TYPE_VF_P1; | |
7571 | else | |
7572 | goto unknown_vg_1g_port; | |
a3138df9 | 7573 | |
5fbd7e24 MW |
7574 | /* fallthru */ |
7575 | case 0x22: | |
a3138df9 | 7576 | val = (phy_encode(PORT_TYPE_10G, 0) | |
a3138df9 DM |
7577 | phy_encode(PORT_TYPE_10G, 1) | |
7578 | phy_encode(PORT_TYPE_1G, 2) | | |
7579 | phy_encode(PORT_TYPE_1G, 3)); | |
5fbd7e24 | 7580 | break; |
a3138df9 | 7581 | |
5fbd7e24 MW |
7582 | case 0x20: |
7583 | val = (phy_encode(PORT_TYPE_10G, 0) | | |
7584 | phy_encode(PORT_TYPE_10G, 1)); | |
7585 | break; | |
a3138df9 | 7586 | |
5fbd7e24 MW |
7587 | case 0x10: |
7588 | val = phy_encode(PORT_TYPE_10G, np->port); | |
7589 | break; | |
a3138df9 | 7590 | |
5fbd7e24 MW |
7591 | case 0x14: |
7592 | if (lowest_1g == 10) | |
7593 | parent->plat_type = PLAT_TYPE_VF_P0; | |
7594 | else if (lowest_1g == 26) | |
7595 | parent->plat_type = PLAT_TYPE_VF_P1; | |
7596 | else | |
7597 | goto unknown_vg_1g_port; | |
7598 | ||
7599 | /* fallthru */ | |
7600 | case 0x13: | |
7601 | if ((lowest_10g & 0x7) == 0) | |
7602 | val = (phy_encode(PORT_TYPE_10G, 0) | | |
7603 | phy_encode(PORT_TYPE_1G, 1) | | |
7604 | phy_encode(PORT_TYPE_1G, 2) | | |
7605 | phy_encode(PORT_TYPE_1G, 3)); | |
7606 | else | |
7607 | val = (phy_encode(PORT_TYPE_1G, 0) | | |
7608 | phy_encode(PORT_TYPE_10G, 1) | | |
7609 | phy_encode(PORT_TYPE_1G, 2) | | |
7610 | phy_encode(PORT_TYPE_1G, 3)); | |
7611 | break; | |
7612 | ||
7613 | case 0x04: | |
7614 | if (lowest_1g == 10) | |
7615 | parent->plat_type = PLAT_TYPE_VF_P0; | |
7616 | else if (lowest_1g == 26) | |
7617 | parent->plat_type = PLAT_TYPE_VF_P1; | |
7618 | else | |
7619 | goto unknown_vg_1g_port; | |
7620 | ||
7621 | val = (phy_encode(PORT_TYPE_1G, 0) | | |
7622 | phy_encode(PORT_TYPE_1G, 1) | | |
7623 | phy_encode(PORT_TYPE_1G, 2) | | |
7624 | phy_encode(PORT_TYPE_1G, 3)); | |
7625 | break; | |
7626 | ||
7627 | default: | |
7628 | printk(KERN_ERR PFX "Unsupported port config " | |
7629 | "10G[%d] 1G[%d]\n", | |
7630 | num_10g, num_1g); | |
7631 | return -EINVAL; | |
7632 | } | |
a3138df9 DM |
7633 | } |
7634 | ||
7635 | parent->port_phy = val; | |
7636 | ||
7637 | if (parent->plat_type == PLAT_TYPE_NIU) | |
7638 | niu_n2_divide_channels(parent); | |
7639 | else | |
7640 | niu_divide_channels(parent, num_10g, num_1g); | |
7641 | ||
7642 | niu_divide_rdc_groups(parent, num_10g, num_1g); | |
7643 | ||
7644 | return 0; | |
7645 | ||
7646 | unknown_vg_1g_port: | |
7647 | printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n", | |
7648 | lowest_1g); | |
7649 | return -EINVAL; | |
7650 | } | |
7651 | ||
7652 | static int __devinit niu_probe_ports(struct niu *np) | |
7653 | { | |
7654 | struct niu_parent *parent = np->parent; | |
7655 | int err, i; | |
7656 | ||
7657 | niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n", | |
7658 | parent->port_phy); | |
7659 | ||
7660 | if (parent->port_phy == PORT_PHY_UNKNOWN) { | |
7661 | err = walk_phys(np, parent); | |
7662 | if (err) | |
7663 | return err; | |
7664 | ||
7665 | niu_set_ldg_timer_res(np, 2); | |
7666 | for (i = 0; i <= LDN_MAX; i++) | |
7667 | niu_ldn_irq_enable(np, i, 0); | |
7668 | } | |
7669 | ||
7670 | if (parent->port_phy == PORT_PHY_INVALID) | |
7671 | return -EINVAL; | |
7672 | ||
7673 | return 0; | |
7674 | } | |
7675 | ||
7676 | static int __devinit niu_classifier_swstate_init(struct niu *np) | |
7677 | { | |
7678 | struct niu_classifier *cp = &np->clas; | |
7679 | ||
7680 | niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n", | |
7681 | np->parent->tcam_num_entries); | |
7682 | ||
7683 | cp->tcam_index = (u16) np->port; | |
7684 | cp->h1_init = 0xffffffff; | |
7685 | cp->h2_init = 0xffff; | |
7686 | ||
7687 | return fflp_early_init(np); | |
7688 | } | |
7689 | ||
7690 | static void __devinit niu_link_config_init(struct niu *np) | |
7691 | { | |
7692 | struct niu_link_config *lp = &np->link_config; | |
7693 | ||
7694 | lp->advertising = (ADVERTISED_10baseT_Half | | |
7695 | ADVERTISED_10baseT_Full | | |
7696 | ADVERTISED_100baseT_Half | | |
7697 | ADVERTISED_100baseT_Full | | |
7698 | ADVERTISED_1000baseT_Half | | |
7699 | ADVERTISED_1000baseT_Full | | |
7700 | ADVERTISED_10000baseT_Full | | |
7701 | ADVERTISED_Autoneg); | |
7702 | lp->speed = lp->active_speed = SPEED_INVALID; | |
7703 | lp->duplex = lp->active_duplex = DUPLEX_INVALID; | |
7704 | #if 0 | |
7705 | lp->loopback_mode = LOOPBACK_MAC; | |
7706 | lp->active_speed = SPEED_10000; | |
7707 | lp->active_duplex = DUPLEX_FULL; | |
7708 | #else | |
7709 | lp->loopback_mode = LOOPBACK_DISABLED; | |
7710 | #endif | |
7711 | } | |
7712 | ||
7713 | static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np) | |
7714 | { | |
7715 | switch (np->port) { | |
7716 | case 0: | |
7717 | np->mac_regs = np->regs + XMAC_PORT0_OFF; | |
7718 | np->ipp_off = 0x00000; | |
7719 | np->pcs_off = 0x04000; | |
7720 | np->xpcs_off = 0x02000; | |
7721 | break; | |
7722 | ||
7723 | case 1: | |
7724 | np->mac_regs = np->regs + XMAC_PORT1_OFF; | |
7725 | np->ipp_off = 0x08000; | |
7726 | np->pcs_off = 0x0a000; | |
7727 | np->xpcs_off = 0x08000; | |
7728 | break; | |
7729 | ||
7730 | case 2: | |
7731 | np->mac_regs = np->regs + BMAC_PORT2_OFF; | |
7732 | np->ipp_off = 0x04000; | |
7733 | np->pcs_off = 0x0e000; | |
7734 | np->xpcs_off = ~0UL; | |
7735 | break; | |
7736 | ||
7737 | case 3: | |
7738 | np->mac_regs = np->regs + BMAC_PORT3_OFF; | |
7739 | np->ipp_off = 0x0c000; | |
7740 | np->pcs_off = 0x12000; | |
7741 | np->xpcs_off = ~0UL; | |
7742 | break; | |
7743 | ||
7744 | default: | |
7745 | dev_err(np->device, PFX "Port %u is invalid, cannot " | |
7746 | "compute MAC block offset.\n", np->port); | |
7747 | return -EINVAL; | |
7748 | } | |
7749 | ||
7750 | return 0; | |
7751 | } | |
7752 | ||
7753 | static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map) | |
7754 | { | |
7755 | struct msix_entry msi_vec[NIU_NUM_LDG]; | |
7756 | struct niu_parent *parent = np->parent; | |
7757 | struct pci_dev *pdev = np->pdev; | |
7758 | int i, num_irqs, err; | |
7759 | u8 first_ldg; | |
7760 | ||
7761 | first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port; | |
7762 | for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++) | |
7763 | ldg_num_map[i] = first_ldg + i; | |
7764 | ||
7765 | num_irqs = (parent->rxchan_per_port[np->port] + | |
7766 | parent->txchan_per_port[np->port] + | |
7767 | (np->port == 0 ? 3 : 1)); | |
7768 | BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports)); | |
7769 | ||
7770 | retry: | |
7771 | for (i = 0; i < num_irqs; i++) { | |
7772 | msi_vec[i].vector = 0; | |
7773 | msi_vec[i].entry = i; | |
7774 | } | |
7775 | ||
7776 | err = pci_enable_msix(pdev, msi_vec, num_irqs); | |
7777 | if (err < 0) { | |
7778 | np->flags &= ~NIU_FLAGS_MSIX; | |
7779 | return; | |
7780 | } | |
7781 | if (err > 0) { | |
7782 | num_irqs = err; | |
7783 | goto retry; | |
7784 | } | |
7785 | ||
7786 | np->flags |= NIU_FLAGS_MSIX; | |
7787 | for (i = 0; i < num_irqs; i++) | |
7788 | np->ldg[i].irq = msi_vec[i].vector; | |
7789 | np->num_ldg = num_irqs; | |
7790 | } | |
7791 | ||
7792 | static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map) | |
7793 | { | |
7794 | #ifdef CONFIG_SPARC64 | |
7795 | struct of_device *op = np->op; | |
7796 | const u32 *int_prop; | |
7797 | int i; | |
7798 | ||
7799 | int_prop = of_get_property(op->node, "interrupts", NULL); | |
7800 | if (!int_prop) | |
7801 | return -ENODEV; | |
7802 | ||
7803 | for (i = 0; i < op->num_irqs; i++) { | |
7804 | ldg_num_map[i] = int_prop[i]; | |
7805 | np->ldg[i].irq = op->irqs[i]; | |
7806 | } | |
7807 | ||
7808 | np->num_ldg = op->num_irqs; | |
7809 | ||
7810 | return 0; | |
7811 | #else | |
7812 | return -EINVAL; | |
7813 | #endif | |
7814 | } | |
7815 | ||
7816 | static int __devinit niu_ldg_init(struct niu *np) | |
7817 | { | |
7818 | struct niu_parent *parent = np->parent; | |
7819 | u8 ldg_num_map[NIU_NUM_LDG]; | |
7820 | int first_chan, num_chan; | |
7821 | int i, err, ldg_rotor; | |
7822 | u8 port; | |
7823 | ||
7824 | np->num_ldg = 1; | |
7825 | np->ldg[0].irq = np->dev->irq; | |
7826 | if (parent->plat_type == PLAT_TYPE_NIU) { | |
7827 | err = niu_n2_irq_init(np, ldg_num_map); | |
7828 | if (err) | |
7829 | return err; | |
7830 | } else | |
7831 | niu_try_msix(np, ldg_num_map); | |
7832 | ||
7833 | port = np->port; | |
7834 | for (i = 0; i < np->num_ldg; i++) { | |
7835 | struct niu_ldg *lp = &np->ldg[i]; | |
7836 | ||
7837 | netif_napi_add(np->dev, &lp->napi, niu_poll, 64); | |
7838 | ||
7839 | lp->np = np; | |
7840 | lp->ldg_num = ldg_num_map[i]; | |
7841 | lp->timer = 2; /* XXX */ | |
7842 | ||
7843 | /* On N2 NIU the firmware has setup the SID mappings so they go | |
7844 | * to the correct values that will route the LDG to the proper | |
7845 | * interrupt in the NCU interrupt table. | |
7846 | */ | |
7847 | if (np->parent->plat_type != PLAT_TYPE_NIU) { | |
7848 | err = niu_set_ldg_sid(np, lp->ldg_num, port, i); | |
7849 | if (err) | |
7850 | return err; | |
7851 | } | |
7852 | } | |
7853 | ||
7854 | /* We adopt the LDG assignment ordering used by the N2 NIU | |
7855 | * 'interrupt' properties because that simplifies a lot of | |
7856 | * things. This ordering is: | |
7857 | * | |
7858 | * MAC | |
7859 | * MIF (if port zero) | |
7860 | * SYSERR (if port zero) | |
7861 | * RX channels | |
7862 | * TX channels | |
7863 | */ | |
7864 | ||
7865 | ldg_rotor = 0; | |
7866 | ||
7867 | err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor], | |
7868 | LDN_MAC(port)); | |
7869 | if (err) | |
7870 | return err; | |
7871 | ||
7872 | ldg_rotor++; | |
7873 | if (ldg_rotor == np->num_ldg) | |
7874 | ldg_rotor = 0; | |
7875 | ||
7876 | if (port == 0) { | |
7877 | err = niu_ldg_assign_ldn(np, parent, | |
7878 | ldg_num_map[ldg_rotor], | |
7879 | LDN_MIF); | |
7880 | if (err) | |
7881 | return err; | |
7882 | ||
7883 | ldg_rotor++; | |
7884 | if (ldg_rotor == np->num_ldg) | |
7885 | ldg_rotor = 0; | |
7886 | ||
7887 | err = niu_ldg_assign_ldn(np, parent, | |
7888 | ldg_num_map[ldg_rotor], | |
7889 | LDN_DEVICE_ERROR); | |
7890 | if (err) | |
7891 | return err; | |
7892 | ||
7893 | ldg_rotor++; | |
7894 | if (ldg_rotor == np->num_ldg) | |
7895 | ldg_rotor = 0; | |
7896 | ||
7897 | } | |
7898 | ||
7899 | first_chan = 0; | |
7900 | for (i = 0; i < port; i++) | |
7901 | first_chan += parent->rxchan_per_port[port]; | |
7902 | num_chan = parent->rxchan_per_port[port]; | |
7903 | ||
7904 | for (i = first_chan; i < (first_chan + num_chan); i++) { | |
7905 | err = niu_ldg_assign_ldn(np, parent, | |
7906 | ldg_num_map[ldg_rotor], | |
7907 | LDN_RXDMA(i)); | |
7908 | if (err) | |
7909 | return err; | |
7910 | ldg_rotor++; | |
7911 | if (ldg_rotor == np->num_ldg) | |
7912 | ldg_rotor = 0; | |
7913 | } | |
7914 | ||
7915 | first_chan = 0; | |
7916 | for (i = 0; i < port; i++) | |
7917 | first_chan += parent->txchan_per_port[port]; | |
7918 | num_chan = parent->txchan_per_port[port]; | |
7919 | for (i = first_chan; i < (first_chan + num_chan); i++) { | |
7920 | err = niu_ldg_assign_ldn(np, parent, | |
7921 | ldg_num_map[ldg_rotor], | |
7922 | LDN_TXDMA(i)); | |
7923 | if (err) | |
7924 | return err; | |
7925 | ldg_rotor++; | |
7926 | if (ldg_rotor == np->num_ldg) | |
7927 | ldg_rotor = 0; | |
7928 | } | |
7929 | ||
7930 | return 0; | |
7931 | } | |
7932 | ||
7933 | static void __devexit niu_ldg_free(struct niu *np) | |
7934 | { | |
7935 | if (np->flags & NIU_FLAGS_MSIX) | |
7936 | pci_disable_msix(np->pdev); | |
7937 | } | |
7938 | ||
7939 | static int __devinit niu_get_of_props(struct niu *np) | |
7940 | { | |
7941 | #ifdef CONFIG_SPARC64 | |
7942 | struct net_device *dev = np->dev; | |
7943 | struct device_node *dp; | |
7944 | const char *phy_type; | |
7945 | const u8 *mac_addr; | |
7946 | int prop_len; | |
7947 | ||
7948 | if (np->parent->plat_type == PLAT_TYPE_NIU) | |
7949 | dp = np->op->node; | |
7950 | else | |
7951 | dp = pci_device_to_OF_node(np->pdev); | |
7952 | ||
7953 | phy_type = of_get_property(dp, "phy-type", &prop_len); | |
7954 | if (!phy_type) { | |
7955 | dev_err(np->device, PFX "%s: OF node lacks " | |
7956 | "phy-type property\n", | |
7957 | dp->full_name); | |
7958 | return -EINVAL; | |
7959 | } | |
7960 | ||
7961 | if (!strcmp(phy_type, "none")) | |
7962 | return -ENODEV; | |
7963 | ||
7964 | strcpy(np->vpd.phy_type, phy_type); | |
7965 | ||
7966 | if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { | |
7967 | dev_err(np->device, PFX "%s: Illegal phy string [%s].\n", | |
7968 | dp->full_name, np->vpd.phy_type); | |
7969 | return -EINVAL; | |
7970 | } | |
7971 | ||
7972 | mac_addr = of_get_property(dp, "local-mac-address", &prop_len); | |
7973 | if (!mac_addr) { | |
7974 | dev_err(np->device, PFX "%s: OF node lacks " | |
7975 | "local-mac-address property\n", | |
7976 | dp->full_name); | |
7977 | return -EINVAL; | |
7978 | } | |
7979 | if (prop_len != dev->addr_len) { | |
7980 | dev_err(np->device, PFX "%s: OF MAC address prop len (%d) " | |
7981 | "is wrong.\n", | |
7982 | dp->full_name, prop_len); | |
7983 | } | |
7984 | memcpy(dev->perm_addr, mac_addr, dev->addr_len); | |
7985 | if (!is_valid_ether_addr(&dev->perm_addr[0])) { | |
7986 | int i; | |
7987 | ||
7988 | dev_err(np->device, PFX "%s: OF MAC address is invalid\n", | |
7989 | dp->full_name); | |
7990 | dev_err(np->device, PFX "%s: [ \n", | |
7991 | dp->full_name); | |
7992 | for (i = 0; i < 6; i++) | |
7993 | printk("%02x ", dev->perm_addr[i]); | |
7994 | printk("]\n"); | |
7995 | return -EINVAL; | |
7996 | } | |
7997 | ||
7998 | memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); | |
7999 | ||
8000 | return 0; | |
8001 | #else | |
8002 | return -EINVAL; | |
8003 | #endif | |
8004 | } | |
8005 | ||
8006 | static int __devinit niu_get_invariants(struct niu *np) | |
8007 | { | |
8008 | int err, have_props; | |
8009 | u32 offset; | |
8010 | ||
8011 | err = niu_get_of_props(np); | |
8012 | if (err == -ENODEV) | |
8013 | return err; | |
8014 | ||
8015 | have_props = !err; | |
8016 | ||
a3138df9 DM |
8017 | err = niu_init_mac_ipp_pcs_base(np); |
8018 | if (err) | |
8019 | return err; | |
8020 | ||
7f7c4072 MW |
8021 | if (have_props) { |
8022 | err = niu_get_and_validate_port(np); | |
8023 | if (err) | |
8024 | return err; | |
8025 | ||
8026 | } else { | |
a3138df9 DM |
8027 | if (np->parent->plat_type == PLAT_TYPE_NIU) |
8028 | return -EINVAL; | |
8029 | ||
8030 | nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE); | |
8031 | offset = niu_pci_vpd_offset(np); | |
8032 | niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n", | |
8033 | offset); | |
8034 | if (offset) | |
8035 | niu_pci_vpd_fetch(np, offset); | |
8036 | nw64(ESPC_PIO_EN, 0); | |
8037 | ||
7f7c4072 | 8038 | if (np->flags & NIU_FLAGS_VPD_VALID) { |
a3138df9 | 8039 | niu_pci_vpd_validate(np); |
7f7c4072 MW |
8040 | err = niu_get_and_validate_port(np); |
8041 | if (err) | |
8042 | return err; | |
8043 | } | |
a3138df9 DM |
8044 | |
8045 | if (!(np->flags & NIU_FLAGS_VPD_VALID)) { | |
7f7c4072 MW |
8046 | err = niu_get_and_validate_port(np); |
8047 | if (err) | |
8048 | return err; | |
a3138df9 DM |
8049 | err = niu_pci_probe_sprom(np); |
8050 | if (err) | |
8051 | return err; | |
8052 | } | |
8053 | } | |
8054 | ||
8055 | err = niu_probe_ports(np); | |
8056 | if (err) | |
8057 | return err; | |
8058 | ||
8059 | niu_ldg_init(np); | |
8060 | ||
8061 | niu_classifier_swstate_init(np); | |
8062 | niu_link_config_init(np); | |
8063 | ||
8064 | err = niu_determine_phy_disposition(np); | |
8065 | if (!err) | |
8066 | err = niu_init_link(np); | |
8067 | ||
8068 | return err; | |
8069 | } | |
8070 | ||
8071 | static LIST_HEAD(niu_parent_list); | |
8072 | static DEFINE_MUTEX(niu_parent_lock); | |
8073 | static int niu_parent_index; | |
8074 | ||
8075 | static ssize_t show_port_phy(struct device *dev, | |
8076 | struct device_attribute *attr, char *buf) | |
8077 | { | |
8078 | struct platform_device *plat_dev = to_platform_device(dev); | |
8079 | struct niu_parent *p = plat_dev->dev.platform_data; | |
8080 | u32 port_phy = p->port_phy; | |
8081 | char *orig_buf = buf; | |
8082 | int i; | |
8083 | ||
8084 | if (port_phy == PORT_PHY_UNKNOWN || | |
8085 | port_phy == PORT_PHY_INVALID) | |
8086 | return 0; | |
8087 | ||
8088 | for (i = 0; i < p->num_ports; i++) { | |
8089 | const char *type_str; | |
8090 | int type; | |
8091 | ||
8092 | type = phy_decode(port_phy, i); | |
8093 | if (type == PORT_TYPE_10G) | |
8094 | type_str = "10G"; | |
8095 | else | |
8096 | type_str = "1G"; | |
8097 | buf += sprintf(buf, | |
8098 | (i == 0) ? "%s" : " %s", | |
8099 | type_str); | |
8100 | } | |
8101 | buf += sprintf(buf, "\n"); | |
8102 | return buf - orig_buf; | |
8103 | } | |
8104 | ||
8105 | static ssize_t show_plat_type(struct device *dev, | |
8106 | struct device_attribute *attr, char *buf) | |
8107 | { | |
8108 | struct platform_device *plat_dev = to_platform_device(dev); | |
8109 | struct niu_parent *p = plat_dev->dev.platform_data; | |
8110 | const char *type_str; | |
8111 | ||
8112 | switch (p->plat_type) { | |
8113 | case PLAT_TYPE_ATLAS: | |
8114 | type_str = "atlas"; | |
8115 | break; | |
8116 | case PLAT_TYPE_NIU: | |
8117 | type_str = "niu"; | |
8118 | break; | |
8119 | case PLAT_TYPE_VF_P0: | |
8120 | type_str = "vf_p0"; | |
8121 | break; | |
8122 | case PLAT_TYPE_VF_P1: | |
8123 | type_str = "vf_p1"; | |
8124 | break; | |
8125 | default: | |
8126 | type_str = "unknown"; | |
8127 | break; | |
8128 | } | |
8129 | ||
8130 | return sprintf(buf, "%s\n", type_str); | |
8131 | } | |
8132 | ||
8133 | static ssize_t __show_chan_per_port(struct device *dev, | |
8134 | struct device_attribute *attr, char *buf, | |
8135 | int rx) | |
8136 | { | |
8137 | struct platform_device *plat_dev = to_platform_device(dev); | |
8138 | struct niu_parent *p = plat_dev->dev.platform_data; | |
8139 | char *orig_buf = buf; | |
8140 | u8 *arr; | |
8141 | int i; | |
8142 | ||
8143 | arr = (rx ? p->rxchan_per_port : p->txchan_per_port); | |
8144 | ||
8145 | for (i = 0; i < p->num_ports; i++) { | |
8146 | buf += sprintf(buf, | |
8147 | (i == 0) ? "%d" : " %d", | |
8148 | arr[i]); | |
8149 | } | |
8150 | buf += sprintf(buf, "\n"); | |
8151 | ||
8152 | return buf - orig_buf; | |
8153 | } | |
8154 | ||
8155 | static ssize_t show_rxchan_per_port(struct device *dev, | |
8156 | struct device_attribute *attr, char *buf) | |
8157 | { | |
8158 | return __show_chan_per_port(dev, attr, buf, 1); | |
8159 | } | |
8160 | ||
8161 | static ssize_t show_txchan_per_port(struct device *dev, | |
8162 | struct device_attribute *attr, char *buf) | |
8163 | { | |
8164 | return __show_chan_per_port(dev, attr, buf, 1); | |
8165 | } | |
8166 | ||
8167 | static ssize_t show_num_ports(struct device *dev, | |
8168 | struct device_attribute *attr, char *buf) | |
8169 | { | |
8170 | struct platform_device *plat_dev = to_platform_device(dev); | |
8171 | struct niu_parent *p = plat_dev->dev.platform_data; | |
8172 | ||
8173 | return sprintf(buf, "%d\n", p->num_ports); | |
8174 | } | |
8175 | ||
8176 | static struct device_attribute niu_parent_attributes[] = { | |
8177 | __ATTR(port_phy, S_IRUGO, show_port_phy, NULL), | |
8178 | __ATTR(plat_type, S_IRUGO, show_plat_type, NULL), | |
8179 | __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL), | |
8180 | __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL), | |
8181 | __ATTR(num_ports, S_IRUGO, show_num_ports, NULL), | |
8182 | {} | |
8183 | }; | |
8184 | ||
8185 | static struct niu_parent * __devinit niu_new_parent(struct niu *np, | |
8186 | union niu_parent_id *id, | |
8187 | u8 ptype) | |
8188 | { | |
8189 | struct platform_device *plat_dev; | |
8190 | struct niu_parent *p; | |
8191 | int i; | |
8192 | ||
8193 | niudbg(PROBE, "niu_new_parent: Creating new parent.\n"); | |
8194 | ||
8195 | plat_dev = platform_device_register_simple("niu", niu_parent_index, | |
8196 | NULL, 0); | |
8197 | if (!plat_dev) | |
8198 | return NULL; | |
8199 | ||
8200 | for (i = 0; attr_name(niu_parent_attributes[i]); i++) { | |
8201 | int err = device_create_file(&plat_dev->dev, | |
8202 | &niu_parent_attributes[i]); | |
8203 | if (err) | |
8204 | goto fail_unregister; | |
8205 | } | |
8206 | ||
8207 | p = kzalloc(sizeof(*p), GFP_KERNEL); | |
8208 | if (!p) | |
8209 | goto fail_unregister; | |
8210 | ||
8211 | p->index = niu_parent_index++; | |
8212 | ||
8213 | plat_dev->dev.platform_data = p; | |
8214 | p->plat_dev = plat_dev; | |
8215 | ||
8216 | memcpy(&p->id, id, sizeof(*id)); | |
8217 | p->plat_type = ptype; | |
8218 | INIT_LIST_HEAD(&p->list); | |
8219 | atomic_set(&p->refcnt, 0); | |
8220 | list_add(&p->list, &niu_parent_list); | |
8221 | spin_lock_init(&p->lock); | |
8222 | ||
8223 | p->rxdma_clock_divider = 7500; | |
8224 | ||
8225 | p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES; | |
8226 | if (p->plat_type == PLAT_TYPE_NIU) | |
8227 | p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES; | |
8228 | ||
8229 | for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { | |
8230 | int index = i - CLASS_CODE_USER_PROG1; | |
8231 | ||
8232 | p->tcam_key[index] = TCAM_KEY_TSEL; | |
8233 | p->flow_key[index] = (FLOW_KEY_IPSA | | |
8234 | FLOW_KEY_IPDA | | |
8235 | FLOW_KEY_PROTO | | |
8236 | (FLOW_KEY_L4_BYTE12 << | |
8237 | FLOW_KEY_L4_0_SHIFT) | | |
8238 | (FLOW_KEY_L4_BYTE12 << | |
8239 | FLOW_KEY_L4_1_SHIFT)); | |
8240 | } | |
8241 | ||
8242 | for (i = 0; i < LDN_MAX + 1; i++) | |
8243 | p->ldg_map[i] = LDG_INVALID; | |
8244 | ||
8245 | return p; | |
8246 | ||
8247 | fail_unregister: | |
8248 | platform_device_unregister(plat_dev); | |
8249 | return NULL; | |
8250 | } | |
8251 | ||
8252 | static struct niu_parent * __devinit niu_get_parent(struct niu *np, | |
8253 | union niu_parent_id *id, | |
8254 | u8 ptype) | |
8255 | { | |
8256 | struct niu_parent *p, *tmp; | |
8257 | int port = np->port; | |
8258 | ||
8259 | niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n", | |
8260 | ptype, port); | |
8261 | ||
8262 | mutex_lock(&niu_parent_lock); | |
8263 | p = NULL; | |
8264 | list_for_each_entry(tmp, &niu_parent_list, list) { | |
8265 | if (!memcmp(id, &tmp->id, sizeof(*id))) { | |
8266 | p = tmp; | |
8267 | break; | |
8268 | } | |
8269 | } | |
8270 | if (!p) | |
8271 | p = niu_new_parent(np, id, ptype); | |
8272 | ||
8273 | if (p) { | |
8274 | char port_name[6]; | |
8275 | int err; | |
8276 | ||
8277 | sprintf(port_name, "port%d", port); | |
8278 | err = sysfs_create_link(&p->plat_dev->dev.kobj, | |
8279 | &np->device->kobj, | |
8280 | port_name); | |
8281 | if (!err) { | |
8282 | p->ports[port] = np; | |
8283 | atomic_inc(&p->refcnt); | |
8284 | } | |
8285 | } | |
8286 | mutex_unlock(&niu_parent_lock); | |
8287 | ||
8288 | return p; | |
8289 | } | |
8290 | ||
8291 | static void niu_put_parent(struct niu *np) | |
8292 | { | |
8293 | struct niu_parent *p = np->parent; | |
8294 | u8 port = np->port; | |
8295 | char port_name[6]; | |
8296 | ||
8297 | BUG_ON(!p || p->ports[port] != np); | |
8298 | ||
8299 | niudbg(PROBE, "niu_put_parent: port[%u]\n", port); | |
8300 | ||
8301 | sprintf(port_name, "port%d", port); | |
8302 | ||
8303 | mutex_lock(&niu_parent_lock); | |
8304 | ||
8305 | sysfs_remove_link(&p->plat_dev->dev.kobj, port_name); | |
8306 | ||
8307 | p->ports[port] = NULL; | |
8308 | np->parent = NULL; | |
8309 | ||
8310 | if (atomic_dec_and_test(&p->refcnt)) { | |
8311 | list_del(&p->list); | |
8312 | platform_device_unregister(p->plat_dev); | |
8313 | } | |
8314 | ||
8315 | mutex_unlock(&niu_parent_lock); | |
8316 | } | |
8317 | ||
8318 | static void *niu_pci_alloc_coherent(struct device *dev, size_t size, | |
8319 | u64 *handle, gfp_t flag) | |
8320 | { | |
8321 | dma_addr_t dh; | |
8322 | void *ret; | |
8323 | ||
8324 | ret = dma_alloc_coherent(dev, size, &dh, flag); | |
8325 | if (ret) | |
8326 | *handle = dh; | |
8327 | return ret; | |
8328 | } | |
8329 | ||
8330 | static void niu_pci_free_coherent(struct device *dev, size_t size, | |
8331 | void *cpu_addr, u64 handle) | |
8332 | { | |
8333 | dma_free_coherent(dev, size, cpu_addr, handle); | |
8334 | } | |
8335 | ||
8336 | static u64 niu_pci_map_page(struct device *dev, struct page *page, | |
8337 | unsigned long offset, size_t size, | |
8338 | enum dma_data_direction direction) | |
8339 | { | |
8340 | return dma_map_page(dev, page, offset, size, direction); | |
8341 | } | |
8342 | ||
8343 | static void niu_pci_unmap_page(struct device *dev, u64 dma_address, | |
8344 | size_t size, enum dma_data_direction direction) | |
8345 | { | |
8346 | return dma_unmap_page(dev, dma_address, size, direction); | |
8347 | } | |
8348 | ||
8349 | static u64 niu_pci_map_single(struct device *dev, void *cpu_addr, | |
8350 | size_t size, | |
8351 | enum dma_data_direction direction) | |
8352 | { | |
8353 | return dma_map_single(dev, cpu_addr, size, direction); | |
8354 | } | |
8355 | ||
8356 | static void niu_pci_unmap_single(struct device *dev, u64 dma_address, | |
8357 | size_t size, | |
8358 | enum dma_data_direction direction) | |
8359 | { | |
8360 | dma_unmap_single(dev, dma_address, size, direction); | |
8361 | } | |
8362 | ||
8363 | static const struct niu_ops niu_pci_ops = { | |
8364 | .alloc_coherent = niu_pci_alloc_coherent, | |
8365 | .free_coherent = niu_pci_free_coherent, | |
8366 | .map_page = niu_pci_map_page, | |
8367 | .unmap_page = niu_pci_unmap_page, | |
8368 | .map_single = niu_pci_map_single, | |
8369 | .unmap_single = niu_pci_unmap_single, | |
8370 | }; | |
8371 | ||
8372 | static void __devinit niu_driver_version(void) | |
8373 | { | |
8374 | static int niu_version_printed; | |
8375 | ||
8376 | if (niu_version_printed++ == 0) | |
8377 | pr_info("%s", version); | |
8378 | } | |
8379 | ||
8380 | static struct net_device * __devinit niu_alloc_and_init( | |
8381 | struct device *gen_dev, struct pci_dev *pdev, | |
8382 | struct of_device *op, const struct niu_ops *ops, | |
8383 | u8 port) | |
8384 | { | |
8385 | struct net_device *dev = alloc_etherdev(sizeof(struct niu)); | |
8386 | struct niu *np; | |
8387 | ||
8388 | if (!dev) { | |
8389 | dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n"); | |
8390 | return NULL; | |
8391 | } | |
8392 | ||
8393 | SET_NETDEV_DEV(dev, gen_dev); | |
8394 | ||
8395 | np = netdev_priv(dev); | |
8396 | np->dev = dev; | |
8397 | np->pdev = pdev; | |
8398 | np->op = op; | |
8399 | np->device = gen_dev; | |
8400 | np->ops = ops; | |
8401 | ||
8402 | np->msg_enable = niu_debug; | |
8403 | ||
8404 | spin_lock_init(&np->lock); | |
8405 | INIT_WORK(&np->reset_task, niu_reset_task); | |
8406 | ||
8407 | np->port = port; | |
8408 | ||
8409 | return dev; | |
8410 | } | |
8411 | ||
8412 | static void __devinit niu_assign_netdev_ops(struct net_device *dev) | |
8413 | { | |
8414 | dev->open = niu_open; | |
8415 | dev->stop = niu_close; | |
8416 | dev->get_stats = niu_get_stats; | |
8417 | dev->set_multicast_list = niu_set_rx_mode; | |
8418 | dev->set_mac_address = niu_set_mac_addr; | |
8419 | dev->do_ioctl = niu_ioctl; | |
8420 | dev->tx_timeout = niu_tx_timeout; | |
8421 | dev->hard_start_xmit = niu_start_xmit; | |
8422 | dev->ethtool_ops = &niu_ethtool_ops; | |
8423 | dev->watchdog_timeo = NIU_TX_TIMEOUT; | |
8424 | dev->change_mtu = niu_change_mtu; | |
8425 | } | |
8426 | ||
8427 | static void __devinit niu_device_announce(struct niu *np) | |
8428 | { | |
8429 | struct net_device *dev = np->dev; | |
2caf62f6 | 8430 | DECLARE_MAC_BUF(mac); |
a3138df9 | 8431 | |
2caf62f6 JP |
8432 | pr_info("%s: NIU Ethernet %s\n", |
8433 | dev->name, print_mac(mac, dev->dev_addr)); | |
a3138df9 | 8434 | |
5fbd7e24 MW |
8435 | if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) { |
8436 | pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", | |
8437 | dev->name, | |
8438 | (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), | |
8439 | (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), | |
8440 | (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"), | |
8441 | (np->mac_xcvr == MAC_XCVR_MII ? "MII" : | |
8442 | (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), | |
8443 | np->vpd.phy_type); | |
8444 | } else { | |
8445 | pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", | |
8446 | dev->name, | |
8447 | (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), | |
8448 | (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), | |
8449 | (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"), | |
8450 | (np->mac_xcvr == MAC_XCVR_MII ? "MII" : | |
8451 | (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), | |
8452 | np->vpd.phy_type); | |
8453 | } | |
a3138df9 DM |
8454 | } |
8455 | ||
8456 | static int __devinit niu_pci_init_one(struct pci_dev *pdev, | |
8457 | const struct pci_device_id *ent) | |
8458 | { | |
8459 | unsigned long niureg_base, niureg_len; | |
8460 | union niu_parent_id parent_id; | |
8461 | struct net_device *dev; | |
8462 | struct niu *np; | |
8463 | int err, pos; | |
8464 | u64 dma_mask; | |
8465 | u16 val16; | |
8466 | ||
8467 | niu_driver_version(); | |
8468 | ||
8469 | err = pci_enable_device(pdev); | |
8470 | if (err) { | |
8471 | dev_err(&pdev->dev, PFX "Cannot enable PCI device, " | |
8472 | "aborting.\n"); | |
8473 | return err; | |
8474 | } | |
8475 | ||
8476 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || | |
8477 | !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
8478 | dev_err(&pdev->dev, PFX "Cannot find proper PCI device " | |
8479 | "base addresses, aborting.\n"); | |
8480 | err = -ENODEV; | |
8481 | goto err_out_disable_pdev; | |
8482 | } | |
8483 | ||
8484 | err = pci_request_regions(pdev, DRV_MODULE_NAME); | |
8485 | if (err) { | |
8486 | dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, " | |
8487 | "aborting.\n"); | |
8488 | goto err_out_disable_pdev; | |
8489 | } | |
8490 | ||
8491 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
8492 | if (pos <= 0) { | |
8493 | dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, " | |
8494 | "aborting.\n"); | |
8495 | goto err_out_free_res; | |
8496 | } | |
8497 | ||
8498 | dev = niu_alloc_and_init(&pdev->dev, pdev, NULL, | |
8499 | &niu_pci_ops, PCI_FUNC(pdev->devfn)); | |
8500 | if (!dev) { | |
8501 | err = -ENOMEM; | |
8502 | goto err_out_free_res; | |
8503 | } | |
8504 | np = netdev_priv(dev); | |
8505 | ||
8506 | memset(&parent_id, 0, sizeof(parent_id)); | |
8507 | parent_id.pci.domain = pci_domain_nr(pdev->bus); | |
8508 | parent_id.pci.bus = pdev->bus->number; | |
8509 | parent_id.pci.device = PCI_SLOT(pdev->devfn); | |
8510 | ||
8511 | np->parent = niu_get_parent(np, &parent_id, | |
8512 | PLAT_TYPE_ATLAS); | |
8513 | if (!np->parent) { | |
8514 | err = -ENOMEM; | |
8515 | goto err_out_free_dev; | |
8516 | } | |
8517 | ||
8518 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16); | |
8519 | val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; | |
8520 | val16 |= (PCI_EXP_DEVCTL_CERE | | |
8521 | PCI_EXP_DEVCTL_NFERE | | |
8522 | PCI_EXP_DEVCTL_FERE | | |
8523 | PCI_EXP_DEVCTL_URRE | | |
8524 | PCI_EXP_DEVCTL_RELAX_EN); | |
8525 | pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16); | |
8526 | ||
8527 | dma_mask = DMA_44BIT_MASK; | |
8528 | err = pci_set_dma_mask(pdev, dma_mask); | |
8529 | if (!err) { | |
8530 | dev->features |= NETIF_F_HIGHDMA; | |
8531 | err = pci_set_consistent_dma_mask(pdev, dma_mask); | |
8532 | if (err) { | |
8533 | dev_err(&pdev->dev, PFX "Unable to obtain 44 bit " | |
8534 | "DMA for consistent allocations, " | |
8535 | "aborting.\n"); | |
8536 | goto err_out_release_parent; | |
8537 | } | |
8538 | } | |
8539 | if (err || dma_mask == DMA_32BIT_MASK) { | |
8540 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
8541 | if (err) { | |
8542 | dev_err(&pdev->dev, PFX "No usable DMA configuration, " | |
8543 | "aborting.\n"); | |
8544 | goto err_out_release_parent; | |
8545 | } | |
8546 | } | |
8547 | ||
8548 | dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM); | |
8549 | ||
8550 | niureg_base = pci_resource_start(pdev, 0); | |
8551 | niureg_len = pci_resource_len(pdev, 0); | |
8552 | ||
8553 | np->regs = ioremap_nocache(niureg_base, niureg_len); | |
8554 | if (!np->regs) { | |
8555 | dev_err(&pdev->dev, PFX "Cannot map device registers, " | |
8556 | "aborting.\n"); | |
8557 | err = -ENOMEM; | |
8558 | goto err_out_release_parent; | |
8559 | } | |
8560 | ||
8561 | pci_set_master(pdev); | |
8562 | pci_save_state(pdev); | |
8563 | ||
8564 | dev->irq = pdev->irq; | |
8565 | ||
8566 | niu_assign_netdev_ops(dev); | |
8567 | ||
8568 | err = niu_get_invariants(np); | |
8569 | if (err) { | |
8570 | if (err != -ENODEV) | |
8571 | dev_err(&pdev->dev, PFX "Problem fetching invariants " | |
8572 | "of chip, aborting.\n"); | |
8573 | goto err_out_iounmap; | |
8574 | } | |
8575 | ||
8576 | err = register_netdev(dev); | |
8577 | if (err) { | |
8578 | dev_err(&pdev->dev, PFX "Cannot register net device, " | |
8579 | "aborting.\n"); | |
8580 | goto err_out_iounmap; | |
8581 | } | |
8582 | ||
8583 | pci_set_drvdata(pdev, dev); | |
8584 | ||
8585 | niu_device_announce(np); | |
8586 | ||
8587 | return 0; | |
8588 | ||
8589 | err_out_iounmap: | |
8590 | if (np->regs) { | |
8591 | iounmap(np->regs); | |
8592 | np->regs = NULL; | |
8593 | } | |
8594 | ||
8595 | err_out_release_parent: | |
8596 | niu_put_parent(np); | |
8597 | ||
8598 | err_out_free_dev: | |
8599 | free_netdev(dev); | |
8600 | ||
8601 | err_out_free_res: | |
8602 | pci_release_regions(pdev); | |
8603 | ||
8604 | err_out_disable_pdev: | |
8605 | pci_disable_device(pdev); | |
8606 | pci_set_drvdata(pdev, NULL); | |
8607 | ||
8608 | return err; | |
8609 | } | |
8610 | ||
8611 | static void __devexit niu_pci_remove_one(struct pci_dev *pdev) | |
8612 | { | |
8613 | struct net_device *dev = pci_get_drvdata(pdev); | |
8614 | ||
8615 | if (dev) { | |
8616 | struct niu *np = netdev_priv(dev); | |
8617 | ||
8618 | unregister_netdev(dev); | |
8619 | if (np->regs) { | |
8620 | iounmap(np->regs); | |
8621 | np->regs = NULL; | |
8622 | } | |
8623 | ||
8624 | niu_ldg_free(np); | |
8625 | ||
8626 | niu_put_parent(np); | |
8627 | ||
8628 | free_netdev(dev); | |
8629 | pci_release_regions(pdev); | |
8630 | pci_disable_device(pdev); | |
8631 | pci_set_drvdata(pdev, NULL); | |
8632 | } | |
8633 | } | |
8634 | ||
8635 | static int niu_suspend(struct pci_dev *pdev, pm_message_t state) | |
8636 | { | |
8637 | struct net_device *dev = pci_get_drvdata(pdev); | |
8638 | struct niu *np = netdev_priv(dev); | |
8639 | unsigned long flags; | |
8640 | ||
8641 | if (!netif_running(dev)) | |
8642 | return 0; | |
8643 | ||
8644 | flush_scheduled_work(); | |
8645 | niu_netif_stop(np); | |
8646 | ||
8647 | del_timer_sync(&np->timer); | |
8648 | ||
8649 | spin_lock_irqsave(&np->lock, flags); | |
8650 | niu_enable_interrupts(np, 0); | |
8651 | spin_unlock_irqrestore(&np->lock, flags); | |
8652 | ||
8653 | netif_device_detach(dev); | |
8654 | ||
8655 | spin_lock_irqsave(&np->lock, flags); | |
8656 | niu_stop_hw(np); | |
8657 | spin_unlock_irqrestore(&np->lock, flags); | |
8658 | ||
8659 | pci_save_state(pdev); | |
8660 | ||
8661 | return 0; | |
8662 | } | |
8663 | ||
8664 | static int niu_resume(struct pci_dev *pdev) | |
8665 | { | |
8666 | struct net_device *dev = pci_get_drvdata(pdev); | |
8667 | struct niu *np = netdev_priv(dev); | |
8668 | unsigned long flags; | |
8669 | int err; | |
8670 | ||
8671 | if (!netif_running(dev)) | |
8672 | return 0; | |
8673 | ||
8674 | pci_restore_state(pdev); | |
8675 | ||
8676 | netif_device_attach(dev); | |
8677 | ||
8678 | spin_lock_irqsave(&np->lock, flags); | |
8679 | ||
8680 | err = niu_init_hw(np); | |
8681 | if (!err) { | |
8682 | np->timer.expires = jiffies + HZ; | |
8683 | add_timer(&np->timer); | |
8684 | niu_netif_start(np); | |
8685 | } | |
8686 | ||
8687 | spin_unlock_irqrestore(&np->lock, flags); | |
8688 | ||
8689 | return err; | |
8690 | } | |
8691 | ||
8692 | static struct pci_driver niu_pci_driver = { | |
8693 | .name = DRV_MODULE_NAME, | |
8694 | .id_table = niu_pci_tbl, | |
8695 | .probe = niu_pci_init_one, | |
8696 | .remove = __devexit_p(niu_pci_remove_one), | |
8697 | .suspend = niu_suspend, | |
8698 | .resume = niu_resume, | |
8699 | }; | |
8700 | ||
8701 | #ifdef CONFIG_SPARC64 | |
8702 | static void *niu_phys_alloc_coherent(struct device *dev, size_t size, | |
8703 | u64 *dma_addr, gfp_t flag) | |
8704 | { | |
8705 | unsigned long order = get_order(size); | |
8706 | unsigned long page = __get_free_pages(flag, order); | |
8707 | ||
8708 | if (page == 0UL) | |
8709 | return NULL; | |
8710 | memset((char *)page, 0, PAGE_SIZE << order); | |
8711 | *dma_addr = __pa(page); | |
8712 | ||
8713 | return (void *) page; | |
8714 | } | |
8715 | ||
8716 | static void niu_phys_free_coherent(struct device *dev, size_t size, | |
8717 | void *cpu_addr, u64 handle) | |
8718 | { | |
8719 | unsigned long order = get_order(size); | |
8720 | ||
8721 | free_pages((unsigned long) cpu_addr, order); | |
8722 | } | |
8723 | ||
8724 | static u64 niu_phys_map_page(struct device *dev, struct page *page, | |
8725 | unsigned long offset, size_t size, | |
8726 | enum dma_data_direction direction) | |
8727 | { | |
8728 | return page_to_phys(page) + offset; | |
8729 | } | |
8730 | ||
8731 | static void niu_phys_unmap_page(struct device *dev, u64 dma_address, | |
8732 | size_t size, enum dma_data_direction direction) | |
8733 | { | |
8734 | /* Nothing to do. */ | |
8735 | } | |
8736 | ||
8737 | static u64 niu_phys_map_single(struct device *dev, void *cpu_addr, | |
8738 | size_t size, | |
8739 | enum dma_data_direction direction) | |
8740 | { | |
8741 | return __pa(cpu_addr); | |
8742 | } | |
8743 | ||
8744 | static void niu_phys_unmap_single(struct device *dev, u64 dma_address, | |
8745 | size_t size, | |
8746 | enum dma_data_direction direction) | |
8747 | { | |
8748 | /* Nothing to do. */ | |
8749 | } | |
8750 | ||
8751 | static const struct niu_ops niu_phys_ops = { | |
8752 | .alloc_coherent = niu_phys_alloc_coherent, | |
8753 | .free_coherent = niu_phys_free_coherent, | |
8754 | .map_page = niu_phys_map_page, | |
8755 | .unmap_page = niu_phys_unmap_page, | |
8756 | .map_single = niu_phys_map_single, | |
8757 | .unmap_single = niu_phys_unmap_single, | |
8758 | }; | |
8759 | ||
8760 | static unsigned long res_size(struct resource *r) | |
8761 | { | |
8762 | return r->end - r->start + 1UL; | |
8763 | } | |
8764 | ||
8765 | static int __devinit niu_of_probe(struct of_device *op, | |
8766 | const struct of_device_id *match) | |
8767 | { | |
8768 | union niu_parent_id parent_id; | |
8769 | struct net_device *dev; | |
8770 | struct niu *np; | |
8771 | const u32 *reg; | |
8772 | int err; | |
8773 | ||
8774 | niu_driver_version(); | |
8775 | ||
8776 | reg = of_get_property(op->node, "reg", NULL); | |
8777 | if (!reg) { | |
8778 | dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n", | |
8779 | op->node->full_name); | |
8780 | return -ENODEV; | |
8781 | } | |
8782 | ||
8783 | dev = niu_alloc_and_init(&op->dev, NULL, op, | |
8784 | &niu_phys_ops, reg[0] & 0x1); | |
8785 | if (!dev) { | |
8786 | err = -ENOMEM; | |
8787 | goto err_out; | |
8788 | } | |
8789 | np = netdev_priv(dev); | |
8790 | ||
8791 | memset(&parent_id, 0, sizeof(parent_id)); | |
8792 | parent_id.of = of_get_parent(op->node); | |
8793 | ||
8794 | np->parent = niu_get_parent(np, &parent_id, | |
8795 | PLAT_TYPE_NIU); | |
8796 | if (!np->parent) { | |
8797 | err = -ENOMEM; | |
8798 | goto err_out_free_dev; | |
8799 | } | |
8800 | ||
8801 | dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM); | |
8802 | ||
8803 | np->regs = of_ioremap(&op->resource[1], 0, | |
8804 | res_size(&op->resource[1]), | |
8805 | "niu regs"); | |
8806 | if (!np->regs) { | |
8807 | dev_err(&op->dev, PFX "Cannot map device registers, " | |
8808 | "aborting.\n"); | |
8809 | err = -ENOMEM; | |
8810 | goto err_out_release_parent; | |
8811 | } | |
8812 | ||
8813 | np->vir_regs_1 = of_ioremap(&op->resource[2], 0, | |
8814 | res_size(&op->resource[2]), | |
8815 | "niu vregs-1"); | |
8816 | if (!np->vir_regs_1) { | |
8817 | dev_err(&op->dev, PFX "Cannot map device vir registers 1, " | |
8818 | "aborting.\n"); | |
8819 | err = -ENOMEM; | |
8820 | goto err_out_iounmap; | |
8821 | } | |
8822 | ||
8823 | np->vir_regs_2 = of_ioremap(&op->resource[3], 0, | |
8824 | res_size(&op->resource[3]), | |
8825 | "niu vregs-2"); | |
8826 | if (!np->vir_regs_2) { | |
8827 | dev_err(&op->dev, PFX "Cannot map device vir registers 2, " | |
8828 | "aborting.\n"); | |
8829 | err = -ENOMEM; | |
8830 | goto err_out_iounmap; | |
8831 | } | |
8832 | ||
8833 | niu_assign_netdev_ops(dev); | |
8834 | ||
8835 | err = niu_get_invariants(np); | |
8836 | if (err) { | |
8837 | if (err != -ENODEV) | |
8838 | dev_err(&op->dev, PFX "Problem fetching invariants " | |
8839 | "of chip, aborting.\n"); | |
8840 | goto err_out_iounmap; | |
8841 | } | |
8842 | ||
8843 | err = register_netdev(dev); | |
8844 | if (err) { | |
8845 | dev_err(&op->dev, PFX "Cannot register net device, " | |
8846 | "aborting.\n"); | |
8847 | goto err_out_iounmap; | |
8848 | } | |
8849 | ||
8850 | dev_set_drvdata(&op->dev, dev); | |
8851 | ||
8852 | niu_device_announce(np); | |
8853 | ||
8854 | return 0; | |
8855 | ||
8856 | err_out_iounmap: | |
8857 | if (np->vir_regs_1) { | |
8858 | of_iounmap(&op->resource[2], np->vir_regs_1, | |
8859 | res_size(&op->resource[2])); | |
8860 | np->vir_regs_1 = NULL; | |
8861 | } | |
8862 | ||
8863 | if (np->vir_regs_2) { | |
8864 | of_iounmap(&op->resource[3], np->vir_regs_2, | |
8865 | res_size(&op->resource[3])); | |
8866 | np->vir_regs_2 = NULL; | |
8867 | } | |
8868 | ||
8869 | if (np->regs) { | |
8870 | of_iounmap(&op->resource[1], np->regs, | |
8871 | res_size(&op->resource[1])); | |
8872 | np->regs = NULL; | |
8873 | } | |
8874 | ||
8875 | err_out_release_parent: | |
8876 | niu_put_parent(np); | |
8877 | ||
8878 | err_out_free_dev: | |
8879 | free_netdev(dev); | |
8880 | ||
8881 | err_out: | |
8882 | return err; | |
8883 | } | |
8884 | ||
8885 | static int __devexit niu_of_remove(struct of_device *op) | |
8886 | { | |
8887 | struct net_device *dev = dev_get_drvdata(&op->dev); | |
8888 | ||
8889 | if (dev) { | |
8890 | struct niu *np = netdev_priv(dev); | |
8891 | ||
8892 | unregister_netdev(dev); | |
8893 | ||
8894 | if (np->vir_regs_1) { | |
8895 | of_iounmap(&op->resource[2], np->vir_regs_1, | |
8896 | res_size(&op->resource[2])); | |
8897 | np->vir_regs_1 = NULL; | |
8898 | } | |
8899 | ||
8900 | if (np->vir_regs_2) { | |
8901 | of_iounmap(&op->resource[3], np->vir_regs_2, | |
8902 | res_size(&op->resource[3])); | |
8903 | np->vir_regs_2 = NULL; | |
8904 | } | |
8905 | ||
8906 | if (np->regs) { | |
8907 | of_iounmap(&op->resource[1], np->regs, | |
8908 | res_size(&op->resource[1])); | |
8909 | np->regs = NULL; | |
8910 | } | |
8911 | ||
8912 | niu_ldg_free(np); | |
8913 | ||
8914 | niu_put_parent(np); | |
8915 | ||
8916 | free_netdev(dev); | |
8917 | dev_set_drvdata(&op->dev, NULL); | |
8918 | } | |
8919 | return 0; | |
8920 | } | |
8921 | ||
8922 | static struct of_device_id niu_match[] = { | |
8923 | { | |
8924 | .name = "network", | |
8925 | .compatible = "SUNW,niusl", | |
8926 | }, | |
8927 | {}, | |
8928 | }; | |
8929 | MODULE_DEVICE_TABLE(of, niu_match); | |
8930 | ||
8931 | static struct of_platform_driver niu_of_driver = { | |
8932 | .name = "niu", | |
8933 | .match_table = niu_match, | |
8934 | .probe = niu_of_probe, | |
8935 | .remove = __devexit_p(niu_of_remove), | |
8936 | }; | |
8937 | ||
8938 | #endif /* CONFIG_SPARC64 */ | |
8939 | ||
8940 | static int __init niu_init(void) | |
8941 | { | |
8942 | int err = 0; | |
8943 | ||
81429973 | 8944 | BUILD_BUG_ON(PAGE_SIZE < 4 * 1024); |
a3138df9 DM |
8945 | |
8946 | niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT); | |
8947 | ||
8948 | #ifdef CONFIG_SPARC64 | |
8949 | err = of_register_driver(&niu_of_driver, &of_bus_type); | |
8950 | #endif | |
8951 | ||
8952 | if (!err) { | |
8953 | err = pci_register_driver(&niu_pci_driver); | |
8954 | #ifdef CONFIG_SPARC64 | |
8955 | if (err) | |
8956 | of_unregister_driver(&niu_of_driver); | |
8957 | #endif | |
8958 | } | |
8959 | ||
8960 | return err; | |
8961 | } | |
8962 | ||
8963 | static void __exit niu_exit(void) | |
8964 | { | |
8965 | pci_unregister_driver(&niu_pci_driver); | |
8966 | #ifdef CONFIG_SPARC64 | |
8967 | of_unregister_driver(&niu_of_driver); | |
8968 | #endif | |
8969 | } | |
8970 | ||
8971 | module_init(niu_init); | |
8972 | module_exit(niu_exit); |