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Commit | Line | Data |
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f5cd7872 OJ |
1 | /* |
2 | * Copyright (C) 2006-2007 PA Semi, Inc | |
3 | * | |
4 | * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/netdevice.h> | |
27 | #include <linux/etherdevice.h> | |
28 | #include <asm/dma-mapping.h> | |
29 | #include <linux/in.h> | |
30 | #include <linux/skbuff.h> | |
31 | ||
32 | #include <linux/ip.h> | |
33 | #include <linux/tcp.h> | |
34 | #include <net/checksum.h> | |
28ae79f5 | 35 | #include <linux/inet_lro.h> |
f5cd7872 | 36 | |
771f7404 | 37 | #include <asm/irq.h> |
af289e80 | 38 | #include <asm/firmware.h> |
40afa531 | 39 | #include <asm/pasemi_dma.h> |
771f7404 | 40 | |
f5cd7872 OJ |
41 | #include "pasemi_mac.h" |
42 | ||
8dc121a4 OJ |
43 | /* We have our own align, since ppc64 in general has it at 0 because |
44 | * of design flaws in some of the server bridge chips. However, for | |
45 | * PWRficient doing the unaligned copies is more expensive than doing | |
46 | * unaligned DMA, so make sure the data is aligned instead. | |
47 | */ | |
48 | #define LOCAL_SKB_ALIGN 2 | |
f5cd7872 OJ |
49 | |
50 | /* TODO list | |
51 | * | |
f5cd7872 OJ |
52 | * - Multicast support |
53 | * - Large MTU support | |
7ddeae2c OJ |
54 | * - SW LRO |
55 | * - Multiqueue RX/TX | |
f5cd7872 OJ |
56 | */ |
57 | ||
58 | ||
59 | /* Must be a power of two */ | |
28ae79f5 | 60 | #define RX_RING_SIZE 2048 |
ad5da10a | 61 | #define TX_RING_SIZE 4096 |
f5cd7872 | 62 | |
28ae79f5 OJ |
63 | #define LRO_MAX_AGGR 64 |
64 | ||
ef1ea0b4 OJ |
65 | #define PE_MIN_MTU 64 |
66 | #define PE_MAX_MTU 1500 | |
67 | #define PE_DEF_MTU ETH_DATA_LEN | |
68 | ||
ceb51361 OJ |
69 | #define DEFAULT_MSG_ENABLE \ |
70 | (NETIF_MSG_DRV | \ | |
71 | NETIF_MSG_PROBE | \ | |
72 | NETIF_MSG_LINK | \ | |
73 | NETIF_MSG_TIMER | \ | |
74 | NETIF_MSG_IFDOWN | \ | |
75 | NETIF_MSG_IFUP | \ | |
76 | NETIF_MSG_RX_ERR | \ | |
77 | NETIF_MSG_TX_ERR) | |
78 | ||
34c20624 | 79 | #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) |
72b05b99 | 80 | #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) |
34c20624 | 81 | #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) |
72b05b99 OJ |
82 | #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) |
83 | #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) | |
f5cd7872 | 84 | |
021fa22e OJ |
85 | #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \ |
86 | & ((ring)->size - 1)) | |
87 | #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring)) | |
88 | ||
ceb51361 OJ |
89 | MODULE_LICENSE("GPL"); |
90 | MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); | |
91 | MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver"); | |
92 | ||
93 | static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */ | |
94 | module_param(debug, int, 0); | |
95 | MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); | |
f5cd7872 | 96 | |
af289e80 OJ |
97 | static int translation_enabled(void) |
98 | { | |
99 | #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) | |
100 | return 1; | |
101 | #else | |
102 | return firmware_has_feature(FW_FEATURE_LPAR); | |
103 | #endif | |
104 | } | |
105 | ||
34c20624 | 106 | static void write_iob_reg(unsigned int reg, unsigned int val) |
a85b9422 | 107 | { |
34c20624 | 108 | pasemi_write_iob_reg(reg, val); |
a85b9422 OJ |
109 | } |
110 | ||
5c15332b | 111 | static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg) |
a85b9422 | 112 | { |
34c20624 | 113 | return pasemi_read_mac_reg(mac->dma_if, reg); |
a85b9422 OJ |
114 | } |
115 | ||
5c15332b | 116 | static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg, |
a85b9422 OJ |
117 | unsigned int val) |
118 | { | |
34c20624 | 119 | pasemi_write_mac_reg(mac->dma_if, reg, val); |
a85b9422 OJ |
120 | } |
121 | ||
34c20624 | 122 | static unsigned int read_dma_reg(unsigned int reg) |
a85b9422 | 123 | { |
34c20624 | 124 | return pasemi_read_dma_reg(reg); |
a85b9422 OJ |
125 | } |
126 | ||
34c20624 | 127 | static void write_dma_reg(unsigned int reg, unsigned int val) |
a85b9422 | 128 | { |
34c20624 | 129 | pasemi_write_dma_reg(reg, val); |
a85b9422 OJ |
130 | } |
131 | ||
5c15332b | 132 | static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
133 | { |
134 | return mac->rx; | |
135 | } | |
136 | ||
5c15332b | 137 | static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
138 | { |
139 | return mac->tx; | |
140 | } | |
141 | ||
5c15332b OJ |
142 | static inline void prefetch_skb(const struct sk_buff *skb) |
143 | { | |
144 | const void *d = skb; | |
145 | ||
146 | prefetch(d); | |
147 | prefetch(d+64); | |
148 | prefetch(d+128); | |
149 | prefetch(d+192); | |
150 | } | |
151 | ||
34c20624 OJ |
152 | static int mac_to_intf(struct pasemi_mac *mac) |
153 | { | |
154 | struct pci_dev *pdev = mac->pdev; | |
155 | u32 tmp; | |
156 | int nintf, off, i, j; | |
157 | int devfn = pdev->devfn; | |
158 | ||
159 | tmp = read_dma_reg(PAS_DMA_CAP_IFI); | |
160 | nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S; | |
161 | off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S; | |
162 | ||
163 | /* IOFF contains the offset to the registers containing the | |
164 | * DMA interface-to-MAC-pci-id mappings, and NIN contains number | |
165 | * of total interfaces. Each register contains 4 devfns. | |
166 | * Just do a linear search until we find the devfn of the MAC | |
167 | * we're trying to look up. | |
168 | */ | |
169 | ||
170 | for (i = 0; i < (nintf+3)/4; i++) { | |
171 | tmp = read_dma_reg(off+4*i); | |
172 | for (j = 0; j < 4; j++) { | |
173 | if (((tmp >> (8*j)) & 0xff) == devfn) | |
174 | return i*4 + j; | |
175 | } | |
176 | } | |
177 | return -1; | |
178 | } | |
179 | ||
ef1ea0b4 OJ |
180 | static void pasemi_mac_intf_disable(struct pasemi_mac *mac) |
181 | { | |
182 | unsigned int flags; | |
183 | ||
184 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); | |
185 | flags &= ~PAS_MAC_CFG_PCFG_PE; | |
186 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
187 | } | |
188 | ||
189 | static void pasemi_mac_intf_enable(struct pasemi_mac *mac) | |
190 | { | |
191 | unsigned int flags; | |
192 | ||
193 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); | |
194 | flags |= PAS_MAC_CFG_PCFG_PE; | |
195 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
196 | } | |
197 | ||
f5cd7872 OJ |
198 | static int pasemi_get_mac_addr(struct pasemi_mac *mac) |
199 | { | |
200 | struct pci_dev *pdev = mac->pdev; | |
201 | struct device_node *dn = pci_device_to_OF_node(pdev); | |
1af7f056 | 202 | int len; |
f5cd7872 OJ |
203 | const u8 *maddr; |
204 | u8 addr[6]; | |
205 | ||
206 | if (!dn) { | |
207 | dev_dbg(&pdev->dev, | |
208 | "No device node for mac, not configuring\n"); | |
209 | return -ENOENT; | |
210 | } | |
211 | ||
1af7f056 | 212 | maddr = of_get_property(dn, "local-mac-address", &len); |
213 | ||
214 | if (maddr && len == 6) { | |
215 | memcpy(mac->mac_addr, maddr, 6); | |
216 | return 0; | |
217 | } | |
218 | ||
219 | /* Some old versions of firmware mistakenly uses mac-address | |
220 | * (and as a string) instead of a byte array in local-mac-address. | |
221 | */ | |
a5fd22eb | 222 | |
a5fd22eb | 223 | if (maddr == NULL) |
9028780a | 224 | maddr = of_get_property(dn, "mac-address", NULL); |
a5fd22eb | 225 | |
f5cd7872 OJ |
226 | if (maddr == NULL) { |
227 | dev_warn(&pdev->dev, | |
228 | "no mac address in device tree, not configuring\n"); | |
229 | return -ENOENT; | |
230 | } | |
231 | ||
232 | if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0], | |
233 | &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) { | |
234 | dev_warn(&pdev->dev, | |
235 | "can't parse mac address, not configuring\n"); | |
236 | return -EINVAL; | |
237 | } | |
238 | ||
1af7f056 | 239 | memcpy(mac->mac_addr, addr, 6); |
240 | ||
f5cd7872 OJ |
241 | return 0; |
242 | } | |
243 | ||
5cea73b0 OJ |
244 | static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p) |
245 | { | |
246 | struct pasemi_mac *mac = netdev_priv(dev); | |
247 | struct sockaddr *addr = p; | |
248 | unsigned int adr0, adr1; | |
249 | ||
250 | if (!is_valid_ether_addr(addr->sa_data)) | |
251 | return -EINVAL; | |
252 | ||
253 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
254 | ||
255 | adr0 = dev->dev_addr[2] << 24 | | |
256 | dev->dev_addr[3] << 16 | | |
257 | dev->dev_addr[4] << 8 | | |
258 | dev->dev_addr[5]; | |
259 | adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1); | |
260 | adr1 &= ~0xffff; | |
261 | adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1]; | |
262 | ||
263 | pasemi_mac_intf_disable(mac); | |
264 | write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0); | |
265 | write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1); | |
266 | pasemi_mac_intf_enable(mac); | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
28ae79f5 OJ |
271 | static int get_skb_hdr(struct sk_buff *skb, void **iphdr, |
272 | void **tcph, u64 *hdr_flags, void *data) | |
273 | { | |
274 | u64 macrx = (u64) data; | |
275 | unsigned int ip_len; | |
276 | struct iphdr *iph; | |
277 | ||
278 | /* IPv4 header checksum failed */ | |
279 | if ((macrx & XCT_MACRX_HTY_M) != XCT_MACRX_HTY_IPV4_OK) | |
280 | return -1; | |
281 | ||
282 | /* non tcp packet */ | |
283 | skb_reset_network_header(skb); | |
284 | iph = ip_hdr(skb); | |
285 | if (iph->protocol != IPPROTO_TCP) | |
286 | return -1; | |
287 | ||
288 | ip_len = ip_hdrlen(skb); | |
289 | skb_set_transport_header(skb, ip_len); | |
290 | *tcph = tcp_hdr(skb); | |
291 | ||
292 | /* check if ip header and tcp header are complete */ | |
293 | if (iph->tot_len < ip_len + tcp_hdrlen(skb)) | |
294 | return -1; | |
295 | ||
296 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
297 | *iphdr = iph; | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
ad3c20d1 | 302 | static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac, |
7e9916e9 | 303 | const int nfrags, |
ad3c20d1 | 304 | struct sk_buff *skb, |
5c15332b | 305 | const dma_addr_t *dmas) |
ad3c20d1 OJ |
306 | { |
307 | int f; | |
5c15332b | 308 | struct pci_dev *pdev = mac->dma_pdev; |
ad3c20d1 | 309 | |
5c15332b | 310 | pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
311 | |
312 | for (f = 0; f < nfrags; f++) { | |
313 | skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; | |
314 | ||
5c15332b | 315 | pci_unmap_page(pdev, dmas[f+1], frag->size, PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
316 | } |
317 | dev_kfree_skb_irq(skb); | |
318 | ||
319 | /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs, | |
320 | * aligned up to a power of 2 | |
321 | */ | |
322 | return (nfrags + 3) & ~1; | |
323 | } | |
324 | ||
5c15332b | 325 | static int pasemi_mac_setup_rx_resources(const struct net_device *dev) |
f5cd7872 OJ |
326 | { |
327 | struct pasemi_mac_rxring *ring; | |
328 | struct pasemi_mac *mac = netdev_priv(dev); | |
34c20624 | 329 | int chno; |
af289e80 | 330 | unsigned int cfg; |
f5cd7872 | 331 | |
34c20624 OJ |
332 | ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring), |
333 | offsetof(struct pasemi_mac_rxring, chan)); | |
f5cd7872 | 334 | |
34c20624 OJ |
335 | if (!ring) { |
336 | dev_err(&mac->pdev->dev, "Can't allocate RX channel\n"); | |
337 | goto out_chan; | |
338 | } | |
339 | chno = ring->chan.chno; | |
f5cd7872 OJ |
340 | |
341 | spin_lock_init(&ring->lock); | |
342 | ||
021fa22e | 343 | ring->size = RX_RING_SIZE; |
fc9e4d2a | 344 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 OJ |
345 | RX_RING_SIZE, GFP_KERNEL); |
346 | ||
fc9e4d2a OJ |
347 | if (!ring->ring_info) |
348 | goto out_ring_info; | |
f5cd7872 OJ |
349 | |
350 | /* Allocate descriptors */ | |
34c20624 | 351 | if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE)) |
fc9e4d2a | 352 | goto out_ring_desc; |
f5cd7872 | 353 | |
f5cd7872 OJ |
354 | ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev, |
355 | RX_RING_SIZE * sizeof(u64), | |
356 | &ring->buf_dma, GFP_KERNEL); | |
357 | if (!ring->buffers) | |
34c20624 | 358 | goto out_ring_desc; |
f5cd7872 OJ |
359 | |
360 | memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64)); | |
361 | ||
34c20624 OJ |
362 | write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno), |
363 | PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
f5cd7872 | 364 | |
34c20624 OJ |
365 | write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno), |
366 | PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) | | |
367 | PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 368 | |
5c15332b | 369 | cfg = PAS_DMA_RXCHAN_CFG_HBU(2); |
af289e80 OJ |
370 | |
371 | if (translation_enabled()) | |
372 | cfg |= PAS_DMA_RXCHAN_CFG_CTR; | |
373 | ||
34c20624 | 374 | write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg); |
f5cd7872 | 375 | |
34c20624 OJ |
376 | write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if), |
377 | PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma)); | |
f5cd7872 | 378 | |
34c20624 OJ |
379 | write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if), |
380 | PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) | | |
381 | PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 382 | |
5c15332b | 383 | cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 | |
af289e80 OJ |
384 | PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP | |
385 | PAS_DMA_RXINT_CFG_HEN; | |
386 | ||
387 | if (translation_enabled()) | |
388 | cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR; | |
389 | ||
34c20624 | 390 | write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg); |
c0efd52b | 391 | |
f5cd7872 OJ |
392 | ring->next_to_fill = 0; |
393 | ring->next_to_clean = 0; | |
72b05b99 | 394 | ring->mac = mac; |
f5cd7872 OJ |
395 | mac->rx = ring; |
396 | ||
397 | return 0; | |
398 | ||
fc9e4d2a OJ |
399 | out_ring_desc: |
400 | kfree(ring->ring_info); | |
401 | out_ring_info: | |
34c20624 OJ |
402 | pasemi_dma_free_chan(&ring->chan); |
403 | out_chan: | |
f5cd7872 OJ |
404 | return -ENOMEM; |
405 | } | |
406 | ||
72b05b99 | 407 | static struct pasemi_mac_txring * |
5c15332b | 408 | pasemi_mac_setup_tx_resources(const struct net_device *dev) |
f5cd7872 OJ |
409 | { |
410 | struct pasemi_mac *mac = netdev_priv(dev); | |
411 | u32 val; | |
f5cd7872 | 412 | struct pasemi_mac_txring *ring; |
af289e80 | 413 | unsigned int cfg; |
34c20624 | 414 | int chno; |
f5cd7872 | 415 | |
34c20624 OJ |
416 | ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring), |
417 | offsetof(struct pasemi_mac_txring, chan)); | |
418 | ||
419 | if (!ring) { | |
420 | dev_err(&mac->pdev->dev, "Can't allocate TX channel\n"); | |
421 | goto out_chan; | |
422 | } | |
423 | ||
424 | chno = ring->chan.chno; | |
f5cd7872 OJ |
425 | |
426 | spin_lock_init(&ring->lock); | |
427 | ||
021fa22e | 428 | ring->size = TX_RING_SIZE; |
fc9e4d2a | 429 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 | 430 | TX_RING_SIZE, GFP_KERNEL); |
fc9e4d2a OJ |
431 | if (!ring->ring_info) |
432 | goto out_ring_info; | |
f5cd7872 OJ |
433 | |
434 | /* Allocate descriptors */ | |
34c20624 | 435 | if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE)) |
fc9e4d2a | 436 | goto out_ring_desc; |
f5cd7872 | 437 | |
34c20624 OJ |
438 | write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), |
439 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
440 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); | |
fc9e4d2a | 441 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3); |
f5cd7872 | 442 | |
34c20624 | 443 | write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); |
f5cd7872 | 444 | |
af289e80 OJ |
445 | cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE | |
446 | PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | | |
447 | PAS_DMA_TXCHAN_CFG_UP | | |
448 | PAS_DMA_TXCHAN_CFG_WT(2); | |
449 | ||
450 | if (translation_enabled()) | |
451 | cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; | |
452 | ||
34c20624 | 453 | write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); |
f5cd7872 | 454 | |
021fa22e | 455 | ring->next_to_fill = 0; |
f5cd7872 | 456 | ring->next_to_clean = 0; |
72b05b99 | 457 | ring->mac = mac; |
f5cd7872 | 458 | |
72b05b99 | 459 | return ring; |
f5cd7872 | 460 | |
fc9e4d2a OJ |
461 | out_ring_desc: |
462 | kfree(ring->ring_info); | |
463 | out_ring_info: | |
34c20624 OJ |
464 | pasemi_dma_free_chan(&ring->chan); |
465 | out_chan: | |
72b05b99 | 466 | return NULL; |
f5cd7872 OJ |
467 | } |
468 | ||
72b05b99 | 469 | static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac) |
f5cd7872 | 470 | { |
72b05b99 | 471 | struct pasemi_mac_txring *txring = tx_ring(mac); |
ad3c20d1 | 472 | unsigned int i, j; |
f5cd7872 | 473 | struct pasemi_mac_buffer *info; |
ad3c20d1 | 474 | dma_addr_t dmas[MAX_SKB_FRAGS+1]; |
7e9916e9 | 475 | int freed, nfrags; |
ad5da10a | 476 | int start, limit; |
fc9e4d2a | 477 | |
72b05b99 OJ |
478 | start = txring->next_to_clean; |
479 | limit = txring->next_to_fill; | |
ad5da10a OJ |
480 | |
481 | /* Compensate for when fill has wrapped and clean has not */ | |
482 | if (start > limit) | |
483 | limit += TX_RING_SIZE; | |
484 | ||
485 | for (i = start; i < limit; i += freed) { | |
72b05b99 | 486 | info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)]; |
fc9e4d2a | 487 | if (info->dma && info->skb) { |
7e9916e9 OJ |
488 | nfrags = skb_shinfo(info->skb)->nr_frags; |
489 | for (j = 0; j <= nfrags; j++) | |
72b05b99 OJ |
490 | dmas[j] = txring->ring_info[(i+1+j) & |
491 | (TX_RING_SIZE-1)].dma; | |
7e9916e9 OJ |
492 | freed = pasemi_mac_unmap_tx_skb(mac, nfrags, |
493 | info->skb, dmas); | |
ad3c20d1 OJ |
494 | } else |
495 | freed = 2; | |
f5cd7872 OJ |
496 | } |
497 | ||
72b05b99 | 498 | kfree(txring->ring_info); |
34c20624 OJ |
499 | pasemi_dma_free_chan(&txring->chan); |
500 | ||
f5cd7872 OJ |
501 | } |
502 | ||
ef1ea0b4 | 503 | static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac) |
f5cd7872 | 504 | { |
72b05b99 | 505 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
f5cd7872 OJ |
506 | unsigned int i; |
507 | struct pasemi_mac_buffer *info; | |
f5cd7872 OJ |
508 | |
509 | for (i = 0; i < RX_RING_SIZE; i++) { | |
72b05b99 | 510 | info = &RX_DESC_INFO(rx, i); |
fc9e4d2a OJ |
511 | if (info->skb && info->dma) { |
512 | pci_unmap_single(mac->dma_pdev, | |
513 | info->dma, | |
514 | info->skb->len, | |
515 | PCI_DMA_FROMDEVICE); | |
516 | dev_kfree_skb_any(info->skb); | |
f5cd7872 | 517 | } |
fc9e4d2a OJ |
518 | info->dma = 0; |
519 | info->skb = NULL; | |
f5cd7872 OJ |
520 | } |
521 | ||
fc9e4d2a | 522 | for (i = 0; i < RX_RING_SIZE; i++) |
ef1ea0b4 OJ |
523 | RX_BUFF(rx, i) = 0; |
524 | } | |
525 | ||
526 | static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac) | |
527 | { | |
528 | pasemi_mac_free_rx_buffers(mac); | |
fc9e4d2a | 529 | |
f5cd7872 | 530 | dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64), |
72b05b99 | 531 | rx_ring(mac)->buffers, rx_ring(mac)->buf_dma); |
f5cd7872 | 532 | |
72b05b99 | 533 | kfree(rx_ring(mac)->ring_info); |
34c20624 | 534 | pasemi_dma_free_chan(&rx_ring(mac)->chan); |
f5cd7872 OJ |
535 | mac->rx = NULL; |
536 | } | |
537 | ||
5c15332b OJ |
538 | static void pasemi_mac_replenish_rx_ring(const struct net_device *dev, |
539 | const int limit) | |
f5cd7872 | 540 | { |
5c15332b | 541 | const struct pasemi_mac *mac = netdev_priv(dev); |
72b05b99 | 542 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
b5254eee | 543 | int fill, count; |
f5cd7872 | 544 | |
cd4ceb24 | 545 | if (limit <= 0) |
f5cd7872 OJ |
546 | return; |
547 | ||
72b05b99 | 548 | fill = rx_ring(mac)->next_to_fill; |
928773c2 | 549 | for (count = 0; count < limit; count++) { |
72b05b99 OJ |
550 | struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill); |
551 | u64 *buff = &RX_BUFF(rx, fill); | |
f5cd7872 OJ |
552 | struct sk_buff *skb; |
553 | dma_addr_t dma; | |
554 | ||
fc9e4d2a OJ |
555 | /* Entry in use? */ |
556 | WARN_ON(*buff); | |
557 | ||
ef1ea0b4 | 558 | skb = dev_alloc_skb(mac->bufsz); |
5d894944 | 559 | skb_reserve(skb, LOCAL_SKB_ALIGN); |
f5cd7872 | 560 | |
9f05cfe2 | 561 | if (unlikely(!skb)) |
f5cd7872 | 562 | break; |
f5cd7872 | 563 | |
8dc121a4 | 564 | dma = pci_map_single(mac->dma_pdev, skb->data, |
ef1ea0b4 | 565 | mac->bufsz - LOCAL_SKB_ALIGN, |
f5cd7872 OJ |
566 | PCI_DMA_FROMDEVICE); |
567 | ||
cd4ceb24 | 568 | if (unlikely(dma_mapping_error(dma))) { |
f5cd7872 | 569 | dev_kfree_skb_irq(info->skb); |
f5cd7872 OJ |
570 | break; |
571 | } | |
572 | ||
573 | info->skb = skb; | |
574 | info->dma = dma; | |
ef1ea0b4 | 575 | *buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma); |
fc9e4d2a | 576 | fill++; |
f5cd7872 OJ |
577 | } |
578 | ||
579 | wmb(); | |
580 | ||
34c20624 | 581 | write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count); |
f5cd7872 | 582 | |
72b05b99 | 583 | rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) & |
b5254eee | 584 | (RX_RING_SIZE - 1); |
f5cd7872 OJ |
585 | } |
586 | ||
5c15332b | 587 | static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac) |
1b0335ea | 588 | { |
906674ab | 589 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
52a94351 | 590 | unsigned int reg, pcnt; |
1b0335ea OJ |
591 | /* Re-enable packet count interrupts: finally |
592 | * ack the packet count interrupt we got in rx_intr. | |
593 | */ | |
594 | ||
906674ab | 595 | pcnt = *rx->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 596 | |
52a94351 | 597 | reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; |
1b0335ea | 598 | |
906674ab OJ |
599 | if (*rx->chan.status & PAS_STATUS_TIMER) |
600 | reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; | |
601 | ||
34c20624 | 602 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg); |
1b0335ea OJ |
603 | } |
604 | ||
5c15332b | 605 | static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac) |
1b0335ea | 606 | { |
52a94351 | 607 | unsigned int reg, pcnt; |
1b0335ea OJ |
608 | |
609 | /* Re-enable packet count interrupts */ | |
34c20624 | 610 | pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 611 | |
52a94351 | 612 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; |
1b0335ea | 613 | |
34c20624 | 614 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg); |
1b0335ea OJ |
615 | } |
616 | ||
617 | ||
5c15332b OJ |
618 | static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac, |
619 | const u64 macrx) | |
69c29d89 OJ |
620 | { |
621 | unsigned int rcmdsta, ccmdsta; | |
34c20624 | 622 | struct pasemi_dmachan *chan = &rx_ring(mac)->chan; |
69c29d89 OJ |
623 | |
624 | if (!netif_msg_rx_err(mac)) | |
625 | return; | |
626 | ||
34c20624 OJ |
627 | rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
628 | ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno)); | |
69c29d89 OJ |
629 | |
630 | printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n", | |
34c20624 | 631 | macrx, *chan->status); |
69c29d89 OJ |
632 | |
633 | printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n", | |
634 | rcmdsta, ccmdsta); | |
635 | } | |
636 | ||
5c15332b OJ |
637 | static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac, |
638 | const u64 mactx) | |
69c29d89 OJ |
639 | { |
640 | unsigned int cmdsta; | |
34c20624 | 641 | struct pasemi_dmachan *chan = &tx_ring(mac)->chan; |
69c29d89 OJ |
642 | |
643 | if (!netif_msg_tx_err(mac)) | |
644 | return; | |
645 | ||
34c20624 | 646 | cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno)); |
69c29d89 OJ |
647 | |
648 | printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\ | |
34c20624 | 649 | "tx status 0x%016lx\n", mactx, *chan->status); |
69c29d89 OJ |
650 | |
651 | printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta); | |
652 | } | |
653 | ||
5c15332b OJ |
654 | static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx, |
655 | const int limit) | |
f5cd7872 | 656 | { |
5c15332b | 657 | const struct pasemi_dmachan *chan = &rx->chan; |
72b05b99 | 658 | struct pasemi_mac *mac = rx->mac; |
5c15332b | 659 | struct pci_dev *pdev = mac->dma_pdev; |
cd4ceb24 | 660 | unsigned int n; |
5c15332b | 661 | int count, buf_index, tot_bytes, packets; |
cd4ceb24 OJ |
662 | struct pasemi_mac_buffer *info; |
663 | struct sk_buff *skb; | |
b5254eee | 664 | unsigned int len; |
5c15332b | 665 | u64 macrx, eval; |
cd4ceb24 | 666 | dma_addr_t dma; |
5c15332b OJ |
667 | |
668 | tot_bytes = 0; | |
669 | packets = 0; | |
f5cd7872 | 670 | |
72b05b99 | 671 | spin_lock(&rx->lock); |
f5cd7872 | 672 | |
72b05b99 | 673 | n = rx->next_to_clean; |
f5cd7872 | 674 | |
72b05b99 | 675 | prefetch(&RX_DESC(rx, n)); |
b5254eee OJ |
676 | |
677 | for (count = 0; count < limit; count++) { | |
72b05b99 | 678 | macrx = RX_DESC(rx, n); |
5c15332b | 679 | prefetch(&RX_DESC(rx, n+4)); |
f5cd7872 | 680 | |
69c29d89 | 681 | if ((macrx & XCT_MACRX_E) || |
34c20624 | 682 | (*chan->status & PAS_STATUS_ERROR)) |
69c29d89 OJ |
683 | pasemi_mac_rx_error(mac, macrx); |
684 | ||
cd4ceb24 | 685 | if (!(macrx & XCT_MACRX_O)) |
f5cd7872 OJ |
686 | break; |
687 | ||
f5cd7872 OJ |
688 | info = NULL; |
689 | ||
b5254eee | 690 | BUG_ON(!(macrx & XCT_MACRX_RR_8BRES)); |
f5cd7872 | 691 | |
72b05b99 | 692 | eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >> |
b5254eee OJ |
693 | XCT_RXRES_8B_EVAL_S; |
694 | buf_index = eval-1; | |
695 | ||
72b05b99 OJ |
696 | dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M); |
697 | info = &RX_DESC_INFO(rx, buf_index); | |
fc9e4d2a | 698 | |
9f05cfe2 | 699 | skb = info->skb; |
f5cd7872 | 700 | |
5c15332b | 701 | prefetch_skb(skb); |
f5cd7872 | 702 | |
cd4ceb24 | 703 | len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S; |
f5cd7872 | 704 | |
ef1ea0b4 | 705 | pci_unmap_single(pdev, dma, mac->bufsz - LOCAL_SKB_ALIGN, |
5c15332b | 706 | PCI_DMA_FROMDEVICE); |
32bee776 OJ |
707 | |
708 | if (macrx & XCT_MACRX_CRC) { | |
709 | /* CRC error flagged */ | |
710 | mac->netdev->stats.rx_errors++; | |
711 | mac->netdev->stats.rx_crc_errors++; | |
4352d826 | 712 | /* No need to free skb, it'll be reused */ |
32bee776 OJ |
713 | goto next; |
714 | } | |
715 | ||
5d894944 | 716 | info->skb = NULL; |
ad5da10a | 717 | info->dma = 0; |
fc9e4d2a | 718 | |
26fcfa95 | 719 | if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) { |
38bf3184 | 720 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
cd4ceb24 | 721 | skb->csum = (macrx & XCT_MACRX_CSUM_M) >> |
f5cd7872 OJ |
722 | XCT_MACRX_CSUM_S; |
723 | } else | |
724 | skb->ip_summed = CHECKSUM_NONE; | |
725 | ||
5c15332b OJ |
726 | packets++; |
727 | tot_bytes += len; | |
728 | ||
729 | /* Don't include CRC */ | |
730 | skb_put(skb, len-4); | |
f5cd7872 | 731 | |
26fcfa95 | 732 | skb->protocol = eth_type_trans(skb, mac->netdev); |
28ae79f5 | 733 | lro_receive_skb(&mac->lro_mgr, skb, (void *)macrx); |
f5cd7872 | 734 | |
32bee776 | 735 | next: |
72b05b99 OJ |
736 | RX_DESC(rx, n) = 0; |
737 | RX_DESC(rx, n+1) = 0; | |
cd4ceb24 | 738 | |
ad5da10a OJ |
739 | /* Need to zero it out since hardware doesn't, since the |
740 | * replenish loop uses it to tell when it's done. | |
741 | */ | |
72b05b99 | 742 | RX_BUFF(rx, buf_index) = 0; |
ad5da10a | 743 | |
b5254eee | 744 | n += 4; |
f5cd7872 OJ |
745 | } |
746 | ||
9a50bebd OJ |
747 | if (n > RX_RING_SIZE) { |
748 | /* Errata 5971 workaround: L2 target of headers */ | |
34c20624 | 749 | write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0); |
9a50bebd OJ |
750 | n &= (RX_RING_SIZE-1); |
751 | } | |
b5254eee | 752 | |
72b05b99 | 753 | rx_ring(mac)->next_to_clean = n; |
b5254eee | 754 | |
28ae79f5 OJ |
755 | lro_flush_all(&mac->lro_mgr); |
756 | ||
b5254eee OJ |
757 | /* Increase is in number of 16-byte entries, and since each descriptor |
758 | * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with | |
759 | * count*2. | |
760 | */ | |
34c20624 | 761 | write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1); |
b5254eee OJ |
762 | |
763 | pasemi_mac_replenish_rx_ring(mac->netdev, count); | |
f5cd7872 | 764 | |
5c15332b OJ |
765 | mac->netdev->stats.rx_bytes += tot_bytes; |
766 | mac->netdev->stats.rx_packets += packets; | |
767 | ||
72b05b99 | 768 | spin_unlock(&rx_ring(mac)->lock); |
f5cd7872 OJ |
769 | |
770 | return count; | |
771 | } | |
772 | ||
ad3c20d1 OJ |
773 | /* Can't make this too large or we blow the kernel stack limits */ |
774 | #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS) | |
775 | ||
72b05b99 | 776 | static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring) |
f5cd7872 | 777 | { |
34c20624 | 778 | struct pasemi_dmachan *chan = &txring->chan; |
72b05b99 | 779 | struct pasemi_mac *mac = txring->mac; |
ad3c20d1 | 780 | int i, j; |
ad5da10a OJ |
781 | unsigned int start, descr_count, buf_count, batch_limit; |
782 | unsigned int ring_limit; | |
02df6cfa | 783 | unsigned int total_count; |
ca7e235f | 784 | unsigned long flags; |
ad3c20d1 OJ |
785 | struct sk_buff *skbs[TX_CLEAN_BATCHSIZE]; |
786 | dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1]; | |
7e9916e9 OJ |
787 | int nf[TX_CLEAN_BATCHSIZE]; |
788 | int nr_frags; | |
f5cd7872 | 789 | |
02df6cfa | 790 | total_count = 0; |
ad5da10a | 791 | batch_limit = TX_CLEAN_BATCHSIZE; |
02df6cfa | 792 | restart: |
72b05b99 | 793 | spin_lock_irqsave(&txring->lock, flags); |
f5cd7872 | 794 | |
72b05b99 OJ |
795 | start = txring->next_to_clean; |
796 | ring_limit = txring->next_to_fill; | |
ad5da10a | 797 | |
7e9916e9 OJ |
798 | prefetch(&TX_DESC_INFO(txring, start+1).skb); |
799 | ||
ad5da10a OJ |
800 | /* Compensate for when fill has wrapped but clean has not */ |
801 | if (start > ring_limit) | |
802 | ring_limit += TX_RING_SIZE; | |
02df6cfa | 803 | |
ad3c20d1 OJ |
804 | buf_count = 0; |
805 | descr_count = 0; | |
f5cd7872 | 806 | |
ad3c20d1 | 807 | for (i = start; |
ad5da10a | 808 | descr_count < batch_limit && i < ring_limit; |
ad3c20d1 | 809 | i += buf_count) { |
72b05b99 | 810 | u64 mactx = TX_DESC(txring, i); |
ad5da10a | 811 | struct sk_buff *skb; |
ad3c20d1 | 812 | |
7e9916e9 OJ |
813 | skb = TX_DESC_INFO(txring, i+1).skb; |
814 | nr_frags = TX_DESC_INFO(txring, i).dma; | |
815 | ||
fc9e4d2a | 816 | if ((mactx & XCT_MACTX_E) || |
34c20624 | 817 | (*chan->status & PAS_STATUS_ERROR)) |
fc9e4d2a | 818 | pasemi_mac_tx_error(mac, mactx); |
69c29d89 | 819 | |
fc9e4d2a | 820 | if (unlikely(mactx & XCT_MACTX_O)) |
02df6cfa | 821 | /* Not yet transmitted */ |
f5cd7872 OJ |
822 | break; |
823 | ||
7e9916e9 OJ |
824 | buf_count = 2 + nr_frags; |
825 | /* Since we always fill with an even number of entries, make | |
826 | * sure we skip any unused one at the end as well. | |
827 | */ | |
828 | if (buf_count & 1) | |
829 | buf_count++; | |
ad3c20d1 | 830 | |
7e9916e9 | 831 | for (j = 0; j <= nr_frags; j++) |
72b05b99 | 832 | dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma; |
ad3c20d1 | 833 | |
7e9916e9 OJ |
834 | skbs[descr_count] = skb; |
835 | nf[descr_count] = nr_frags; | |
836 | ||
72b05b99 OJ |
837 | TX_DESC(txring, i) = 0; |
838 | TX_DESC(txring, i+1) = 0; | |
fc9e4d2a | 839 | |
ad3c20d1 | 840 | descr_count++; |
f5cd7872 | 841 | } |
72b05b99 | 842 | txring->next_to_clean = i & (TX_RING_SIZE-1); |
ad3c20d1 | 843 | |
72b05b99 | 844 | spin_unlock_irqrestore(&txring->lock, flags); |
0ce68c74 OJ |
845 | netif_wake_queue(mac->netdev); |
846 | ||
ad3c20d1 | 847 | for (i = 0; i < descr_count; i++) |
7e9916e9 | 848 | pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]); |
02df6cfa | 849 | |
ad3c20d1 | 850 | total_count += descr_count; |
02df6cfa OJ |
851 | |
852 | /* If the batch was full, try to clean more */ | |
ad5da10a | 853 | if (descr_count == batch_limit) |
02df6cfa OJ |
854 | goto restart; |
855 | ||
856 | return total_count; | |
f5cd7872 OJ |
857 | } |
858 | ||
859 | ||
860 | static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) | |
861 | { | |
5c15332b | 862 | const struct pasemi_mac_rxring *rxring = data; |
34c20624 OJ |
863 | struct pasemi_mac *mac = rxring->mac; |
864 | struct net_device *dev = mac->netdev; | |
5c15332b | 865 | const struct pasemi_dmachan *chan = &rxring->chan; |
f5cd7872 OJ |
866 | unsigned int reg; |
867 | ||
34c20624 | 868 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
869 | return IRQ_NONE; |
870 | ||
6dfa7522 OJ |
871 | /* Don't reset packet count so it won't fire again but clear |
872 | * all others. | |
873 | */ | |
874 | ||
6dfa7522 | 875 | reg = 0; |
34c20624 | 876 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 877 | reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; |
34c20624 | 878 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 879 | reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; |
f5cd7872 | 880 | |
bea3348e | 881 | netif_rx_schedule(dev, &mac->napi); |
6dfa7522 | 882 | |
34c20624 | 883 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg); |
f5cd7872 OJ |
884 | |
885 | return IRQ_HANDLED; | |
886 | } | |
887 | ||
61cec3bd OJ |
888 | #define TX_CLEAN_INTERVAL HZ |
889 | ||
890 | static void pasemi_mac_tx_timer(unsigned long data) | |
891 | { | |
892 | struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data; | |
893 | struct pasemi_mac *mac = txring->mac; | |
894 | ||
895 | pasemi_mac_clean_tx(txring); | |
896 | ||
897 | mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL); | |
898 | ||
899 | pasemi_mac_restart_tx_intr(mac); | |
900 | } | |
901 | ||
f5cd7872 OJ |
902 | static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) |
903 | { | |
72b05b99 | 904 | struct pasemi_mac_txring *txring = data; |
5c15332b | 905 | const struct pasemi_dmachan *chan = &txring->chan; |
61cec3bd OJ |
906 | struct pasemi_mac *mac = txring->mac; |
907 | unsigned int reg; | |
f5cd7872 | 908 | |
34c20624 | 909 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
910 | return IRQ_NONE; |
911 | ||
61cec3bd | 912 | reg = 0; |
6dfa7522 | 913 | |
34c20624 | 914 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 915 | reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; |
34c20624 | 916 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 917 | reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; |
f5cd7872 | 918 | |
61cec3bd OJ |
919 | mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2); |
920 | ||
921 | netif_rx_schedule(mac->netdev, &mac->napi); | |
922 | ||
923 | if (reg) | |
924 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg); | |
f5cd7872 | 925 | |
f5cd7872 OJ |
926 | return IRQ_HANDLED; |
927 | } | |
928 | ||
bb6e9590 OJ |
929 | static void pasemi_adjust_link(struct net_device *dev) |
930 | { | |
931 | struct pasemi_mac *mac = netdev_priv(dev); | |
932 | int msg; | |
933 | unsigned int flags; | |
934 | unsigned int new_flags; | |
935 | ||
936 | if (!mac->phydev->link) { | |
937 | /* If no link, MAC speed settings don't matter. Just report | |
938 | * link down and return. | |
939 | */ | |
940 | if (mac->link && netif_msg_link(mac)) | |
941 | printk(KERN_INFO "%s: Link is down.\n", dev->name); | |
942 | ||
943 | netif_carrier_off(dev); | |
b0cd2f90 | 944 | pasemi_mac_intf_disable(mac); |
bb6e9590 OJ |
945 | mac->link = 0; |
946 | ||
947 | return; | |
b0cd2f90 OJ |
948 | } else { |
949 | pasemi_mac_intf_enable(mac); | |
bb6e9590 | 950 | netif_carrier_on(dev); |
b0cd2f90 | 951 | } |
bb6e9590 | 952 | |
a85b9422 | 953 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
bb6e9590 OJ |
954 | new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | |
955 | PAS_MAC_CFG_PCFG_TSR_M); | |
956 | ||
957 | if (!mac->phydev->duplex) | |
958 | new_flags |= PAS_MAC_CFG_PCFG_HD; | |
959 | ||
960 | switch (mac->phydev->speed) { | |
961 | case 1000: | |
962 | new_flags |= PAS_MAC_CFG_PCFG_SPD_1G | | |
963 | PAS_MAC_CFG_PCFG_TSR_1G; | |
964 | break; | |
965 | case 100: | |
966 | new_flags |= PAS_MAC_CFG_PCFG_SPD_100M | | |
967 | PAS_MAC_CFG_PCFG_TSR_100M; | |
968 | break; | |
969 | case 10: | |
970 | new_flags |= PAS_MAC_CFG_PCFG_SPD_10M | | |
971 | PAS_MAC_CFG_PCFG_TSR_10M; | |
972 | break; | |
973 | default: | |
974 | printk("Unsupported speed %d\n", mac->phydev->speed); | |
975 | } | |
976 | ||
977 | /* Print on link or speed/duplex change */ | |
978 | msg = mac->link != mac->phydev->link || flags != new_flags; | |
979 | ||
980 | mac->duplex = mac->phydev->duplex; | |
981 | mac->speed = mac->phydev->speed; | |
982 | mac->link = mac->phydev->link; | |
983 | ||
984 | if (new_flags != flags) | |
a85b9422 | 985 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags); |
bb6e9590 OJ |
986 | |
987 | if (msg && netif_msg_link(mac)) | |
988 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", | |
989 | dev->name, mac->speed, mac->duplex ? "full" : "half"); | |
990 | } | |
991 | ||
992 | static int pasemi_mac_phy_init(struct net_device *dev) | |
993 | { | |
994 | struct pasemi_mac *mac = netdev_priv(dev); | |
995 | struct device_node *dn, *phy_dn; | |
996 | struct phy_device *phydev; | |
997 | unsigned int phy_id; | |
998 | const phandle *ph; | |
999 | const unsigned int *prop; | |
1000 | struct resource r; | |
1001 | int ret; | |
1002 | ||
1003 | dn = pci_device_to_OF_node(mac->pdev); | |
9028780a | 1004 | ph = of_get_property(dn, "phy-handle", NULL); |
bb6e9590 OJ |
1005 | if (!ph) |
1006 | return -ENODEV; | |
1007 | phy_dn = of_find_node_by_phandle(*ph); | |
1008 | ||
9028780a | 1009 | prop = of_get_property(phy_dn, "reg", NULL); |
bb6e9590 OJ |
1010 | ret = of_address_to_resource(phy_dn->parent, 0, &r); |
1011 | if (ret) | |
1012 | goto err; | |
1013 | ||
1014 | phy_id = *prop; | |
1015 | snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id); | |
1016 | ||
1017 | of_node_put(phy_dn); | |
1018 | ||
1019 | mac->link = 0; | |
1020 | mac->speed = 0; | |
1021 | mac->duplex = -1; | |
1022 | ||
1023 | phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII); | |
1024 | ||
1025 | if (IS_ERR(phydev)) { | |
1026 | printk(KERN_ERR "%s: Could not attach to phy\n", dev->name); | |
1027 | return PTR_ERR(phydev); | |
1028 | } | |
1029 | ||
1030 | mac->phydev = phydev; | |
1031 | ||
1032 | return 0; | |
1033 | ||
1034 | err: | |
1035 | of_node_put(phy_dn); | |
1036 | return -ENODEV; | |
1037 | } | |
1038 | ||
1039 | ||
f5cd7872 OJ |
1040 | static int pasemi_mac_open(struct net_device *dev) |
1041 | { | |
1042 | struct pasemi_mac *mac = netdev_priv(dev); | |
1043 | unsigned int flags; | |
1044 | int ret; | |
1045 | ||
f5cd7872 OJ |
1046 | flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | |
1047 | PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | | |
1048 | PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); | |
1049 | ||
a85b9422 | 1050 | write_mac_reg(mac, PAS_MAC_CFG_TXP, flags); |
f5cd7872 | 1051 | |
f5cd7872 OJ |
1052 | ret = pasemi_mac_setup_rx_resources(dev); |
1053 | if (ret) | |
1054 | goto out_rx_resources; | |
1055 | ||
34c20624 | 1056 | mac->tx = pasemi_mac_setup_tx_resources(dev); |
72b05b99 OJ |
1057 | |
1058 | if (!mac->tx) | |
1059 | goto out_tx_ring; | |
f5cd7872 | 1060 | |
906674ab OJ |
1061 | /* 0x3ff with 33MHz clock is about 31us */ |
1062 | write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG, | |
1063 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff)); | |
1064 | ||
34c20624 | 1065 | write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno), |
28ae79f5 | 1066 | PAS_IOB_DMA_RXCH_CFG_CNTTH(256)); |
34c20624 OJ |
1067 | |
1068 | write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno), | |
61cec3bd | 1069 | PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); |
34c20624 | 1070 | |
a85b9422 | 1071 | write_mac_reg(mac, PAS_MAC_IPC_CHNL, |
34c20624 OJ |
1072 | PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) | |
1073 | PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno)); | |
f5cd7872 OJ |
1074 | |
1075 | /* enable rx if */ | |
34c20624 OJ |
1076 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), |
1077 | PAS_DMA_RXINT_RCMDSTA_EN | | |
1078 | PAS_DMA_RXINT_RCMDSTA_DROPS_M | | |
1079 | PAS_DMA_RXINT_RCMDSTA_BP | | |
1080 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1081 | PAS_DMA_RXINT_RCMDSTA_BT); | |
f5cd7872 OJ |
1082 | |
1083 | /* enable rx channel */ | |
34c20624 OJ |
1084 | pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU | |
1085 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1086 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1087 | PAS_DMA_RXCHAN_CCMDSTA_DT); | |
f5cd7872 OJ |
1088 | |
1089 | /* enable tx channel */ | |
34c20624 OJ |
1090 | pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | |
1091 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
1092 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
1093 | PAS_DMA_TXCHAN_TCMDSTA_DA); | |
f5cd7872 | 1094 | |
928773c2 | 1095 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE); |
f5cd7872 | 1096 | |
34c20624 OJ |
1097 | write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno), |
1098 | RX_RING_SIZE>>1); | |
b5254eee | 1099 | |
72b05b99 OJ |
1100 | /* Clear out any residual packet count state from firmware */ |
1101 | pasemi_mac_restart_rx_intr(mac); | |
1102 | pasemi_mac_restart_tx_intr(mac); | |
1103 | ||
b0cd2f90 | 1104 | flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; |
36033766 OJ |
1105 | |
1106 | if (mac->type == MAC_TYPE_GMAC) | |
1107 | flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; | |
1108 | else | |
1109 | flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G; | |
1110 | ||
1111 | /* Enable interface in MAC */ | |
1112 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
1113 | ||
bb6e9590 | 1114 | ret = pasemi_mac_phy_init(dev); |
b0cd2f90 OJ |
1115 | if (ret) { |
1116 | /* Since we won't get link notification, just enable RX */ | |
1117 | pasemi_mac_intf_enable(mac); | |
1118 | if (mac->type == MAC_TYPE_GMAC) { | |
1119 | /* Warn for missing PHY on SGMII (1Gig) ports */ | |
1120 | dev_warn(&mac->pdev->dev, | |
1121 | "PHY init failed: %d.\n", ret); | |
1122 | dev_warn(&mac->pdev->dev, | |
1123 | "Defaulting to 1Gbit full duplex\n"); | |
1124 | } | |
8304b633 | 1125 | } |
bb6e9590 | 1126 | |
f5cd7872 | 1127 | netif_start_queue(dev); |
bea3348e | 1128 | napi_enable(&mac->napi); |
f5cd7872 | 1129 | |
72b05b99 OJ |
1130 | snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx", |
1131 | dev->name); | |
771f7404 | 1132 | |
34c20624 | 1133 | ret = request_irq(mac->tx->chan.irq, &pasemi_mac_tx_intr, IRQF_DISABLED, |
72b05b99 | 1134 | mac->tx_irq_name, mac->tx); |
f5cd7872 OJ |
1135 | if (ret) { |
1136 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1137 | mac->tx->chan.irq, ret); |
f5cd7872 OJ |
1138 | goto out_tx_int; |
1139 | } | |
1140 | ||
72b05b99 OJ |
1141 | snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx", |
1142 | dev->name); | |
1143 | ||
34c20624 OJ |
1144 | ret = request_irq(mac->rx->chan.irq, &pasemi_mac_rx_intr, IRQF_DISABLED, |
1145 | mac->rx_irq_name, mac->rx); | |
f5cd7872 OJ |
1146 | if (ret) { |
1147 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1148 | mac->rx->chan.irq, ret); |
f5cd7872 OJ |
1149 | goto out_rx_int; |
1150 | } | |
1151 | ||
bb6e9590 OJ |
1152 | if (mac->phydev) |
1153 | phy_start(mac->phydev); | |
1154 | ||
61cec3bd OJ |
1155 | init_timer(&mac->tx->clean_timer); |
1156 | mac->tx->clean_timer.function = pasemi_mac_tx_timer; | |
1157 | mac->tx->clean_timer.data = (unsigned long)mac->tx; | |
1158 | mac->tx->clean_timer.expires = jiffies+HZ; | |
1159 | add_timer(&mac->tx->clean_timer); | |
1160 | ||
f5cd7872 OJ |
1161 | return 0; |
1162 | ||
1163 | out_rx_int: | |
34c20624 | 1164 | free_irq(mac->tx->chan.irq, mac->tx); |
f5cd7872 | 1165 | out_tx_int: |
bea3348e | 1166 | napi_disable(&mac->napi); |
f5cd7872 | 1167 | netif_stop_queue(dev); |
72b05b99 OJ |
1168 | out_tx_ring: |
1169 | if (mac->tx) | |
1170 | pasemi_mac_free_tx_resources(mac); | |
1171 | pasemi_mac_free_rx_resources(mac); | |
f5cd7872 OJ |
1172 | out_rx_resources: |
1173 | ||
1174 | return ret; | |
1175 | } | |
1176 | ||
1177 | #define MAX_RETRIES 5000 | |
1178 | ||
ef1ea0b4 OJ |
1179 | static void pasemi_mac_pause_txchan(struct pasemi_mac *mac) |
1180 | { | |
1181 | unsigned int sta, retries; | |
1182 | int txch = tx_ring(mac)->chan.chno; | |
1183 | ||
1184 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), | |
1185 | PAS_DMA_TXCHAN_TCMDSTA_ST); | |
1186 | ||
1187 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1188 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); | |
1189 | if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) | |
1190 | break; | |
1191 | cond_resched(); | |
1192 | } | |
1193 | ||
1194 | if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT) | |
1195 | dev_err(&mac->dma_pdev->dev, | |
1196 | "Failed to stop tx channel, tcmdsta %08x\n", sta); | |
1197 | ||
1198 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0); | |
1199 | } | |
1200 | ||
1201 | static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac) | |
1202 | { | |
1203 | unsigned int sta, retries; | |
1204 | int rxch = rx_ring(mac)->chan.chno; | |
1205 | ||
1206 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), | |
1207 | PAS_DMA_RXCHAN_CCMDSTA_ST); | |
1208 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1209 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); | |
1210 | if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) | |
1211 | break; | |
1212 | cond_resched(); | |
1213 | } | |
1214 | ||
1215 | if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT) | |
1216 | dev_err(&mac->dma_pdev->dev, | |
1217 | "Failed to stop rx channel, ccmdsta 08%x\n", sta); | |
1218 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0); | |
1219 | } | |
1220 | ||
1221 | static void pasemi_mac_pause_rxint(struct pasemi_mac *mac) | |
1222 | { | |
1223 | unsigned int sta, retries; | |
1224 | ||
1225 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
1226 | PAS_DMA_RXINT_RCMDSTA_ST); | |
1227 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1228 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); | |
1229 | if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT)) | |
1230 | break; | |
1231 | cond_resched(); | |
1232 | } | |
1233 | ||
1234 | if (sta & PAS_DMA_RXINT_RCMDSTA_ACT) | |
1235 | dev_err(&mac->dma_pdev->dev, | |
1236 | "Failed to stop rx interface, rcmdsta %08x\n", sta); | |
1237 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); | |
1238 | } | |
1239 | ||
f5cd7872 OJ |
1240 | static int pasemi_mac_close(struct net_device *dev) |
1241 | { | |
1242 | struct pasemi_mac *mac = netdev_priv(dev); | |
9e81d331 | 1243 | unsigned int sta; |
34c20624 OJ |
1244 | int rxch, txch; |
1245 | ||
1246 | rxch = rx_ring(mac)->chan.chno; | |
1247 | txch = tx_ring(mac)->chan.chno; | |
f5cd7872 | 1248 | |
bb6e9590 OJ |
1249 | if (mac->phydev) { |
1250 | phy_stop(mac->phydev); | |
1251 | phy_disconnect(mac->phydev); | |
1252 | } | |
1253 | ||
61cec3bd OJ |
1254 | del_timer_sync(&mac->tx->clean_timer); |
1255 | ||
f5cd7872 | 1256 | netif_stop_queue(dev); |
bea3348e | 1257 | napi_disable(&mac->napi); |
f5cd7872 | 1258 | |
34c20624 | 1259 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
9e81d331 OJ |
1260 | if (sta & (PAS_DMA_RXINT_RCMDSTA_BP | |
1261 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1262 | PAS_DMA_RXINT_RCMDSTA_BT)) | |
1263 | printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta); | |
1264 | ||
34c20624 | 1265 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); |
9e81d331 OJ |
1266 | if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU | |
1267 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1268 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1269 | PAS_DMA_RXCHAN_CCMDSTA_DT)) | |
1270 | printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta); | |
1271 | ||
34c20624 | 1272 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); |
72b05b99 OJ |
1273 | if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB | |
1274 | PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA)) | |
9e81d331 OJ |
1275 | printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta); |
1276 | ||
f5cd7872 | 1277 | /* Clean out any pending buffers */ |
72b05b99 OJ |
1278 | pasemi_mac_clean_tx(tx_ring(mac)); |
1279 | pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); | |
f5cd7872 | 1280 | |
ef1ea0b4 OJ |
1281 | pasemi_mac_pause_txchan(mac); |
1282 | pasemi_mac_pause_rxint(mac); | |
1283 | pasemi_mac_pause_rxchan(mac); | |
1145d954 | 1284 | pasemi_mac_intf_disable(mac); |
f5cd7872 | 1285 | |
34c20624 OJ |
1286 | free_irq(mac->tx->chan.irq, mac->tx); |
1287 | free_irq(mac->rx->chan.irq, mac->rx); | |
f5cd7872 OJ |
1288 | |
1289 | /* Free resources */ | |
72b05b99 OJ |
1290 | pasemi_mac_free_rx_resources(mac); |
1291 | pasemi_mac_free_tx_resources(mac); | |
f5cd7872 OJ |
1292 | |
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) | |
1297 | { | |
1298 | struct pasemi_mac *mac = netdev_priv(dev); | |
1299 | struct pasemi_mac_txring *txring; | |
ad3c20d1 OJ |
1300 | u64 dflags, mactx; |
1301 | dma_addr_t map[MAX_SKB_FRAGS+1]; | |
1302 | unsigned int map_size[MAX_SKB_FRAGS+1]; | |
ca7e235f | 1303 | unsigned long flags; |
ad3c20d1 | 1304 | int i, nfrags; |
5c15332b | 1305 | int fill; |
f5cd7872 | 1306 | |
dbd62af7 | 1307 | dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD; |
f5cd7872 OJ |
1308 | |
1309 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
d56f90a7 ACM |
1310 | const unsigned char *nh = skb_network_header(skb); |
1311 | ||
eddc9ec5 | 1312 | switch (ip_hdr(skb)->protocol) { |
f5cd7872 OJ |
1313 | case IPPROTO_TCP: |
1314 | dflags |= XCT_MACTX_CSUM_TCP; | |
cfe1fc77 | 1315 | dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2); |
d56f90a7 | 1316 | dflags |= XCT_MACTX_IPO(nh - skb->data); |
f5cd7872 OJ |
1317 | break; |
1318 | case IPPROTO_UDP: | |
1319 | dflags |= XCT_MACTX_CSUM_UDP; | |
cfe1fc77 | 1320 | dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2); |
d56f90a7 | 1321 | dflags |= XCT_MACTX_IPO(nh - skb->data); |
f5cd7872 OJ |
1322 | break; |
1323 | } | |
1324 | } | |
1325 | ||
ad3c20d1 OJ |
1326 | nfrags = skb_shinfo(skb)->nr_frags; |
1327 | ||
1328 | map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb), | |
1329 | PCI_DMA_TODEVICE); | |
1330 | map_size[0] = skb_headlen(skb); | |
1331 | if (dma_mapping_error(map[0])) | |
1332 | goto out_err_nolock; | |
1333 | ||
1334 | for (i = 0; i < nfrags; i++) { | |
1335 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
f5cd7872 | 1336 | |
ad3c20d1 OJ |
1337 | map[i+1] = pci_map_page(mac->dma_pdev, frag->page, |
1338 | frag->page_offset, frag->size, | |
1339 | PCI_DMA_TODEVICE); | |
1340 | map_size[i+1] = frag->size; | |
1341 | if (dma_mapping_error(map[i+1])) { | |
1342 | nfrags = i; | |
1343 | goto out_err_nolock; | |
1344 | } | |
1345 | } | |
f5cd7872 | 1346 | |
26fcfa95 | 1347 | mactx = dflags | XCT_MACTX_LLEN(skb->len); |
26fcfa95 | 1348 | |
72b05b99 | 1349 | txring = tx_ring(mac); |
f5cd7872 OJ |
1350 | |
1351 | spin_lock_irqsave(&txring->lock, flags); | |
1352 | ||
5c15332b OJ |
1353 | fill = txring->next_to_fill; |
1354 | ||
ad5da10a OJ |
1355 | /* Avoid stepping on the same cache line that the DMA controller |
1356 | * is currently about to send, so leave at least 8 words available. | |
1357 | * Total free space needed is mactx + fragments + 8 | |
1358 | */ | |
1359 | if (RING_AVAIL(txring) < nfrags + 10) { | |
1360 | /* no room -- stop the queue and wait for tx intr */ | |
1361 | netif_stop_queue(dev); | |
1362 | goto out_err; | |
f5cd7872 OJ |
1363 | } |
1364 | ||
5c15332b | 1365 | TX_DESC(txring, fill) = mactx; |
7e9916e9 | 1366 | TX_DESC_INFO(txring, fill).dma = nfrags; |
5c15332b OJ |
1367 | fill++; |
1368 | TX_DESC_INFO(txring, fill).skb = skb; | |
ad3c20d1 | 1369 | for (i = 0; i <= nfrags; i++) { |
5c15332b | 1370 | TX_DESC(txring, fill+i) = |
72b05b99 | 1371 | XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); |
5c15332b | 1372 | TX_DESC_INFO(txring, fill+i).dma = map[i]; |
ad3c20d1 OJ |
1373 | } |
1374 | ||
1375 | /* We have to add an even number of 8-byte entries to the ring | |
1376 | * even if the last one is unused. That means always an odd number | |
1377 | * of pointers + one mactx descriptor. | |
1378 | */ | |
1379 | if (nfrags & 1) | |
1380 | nfrags++; | |
fc9e4d2a | 1381 | |
5c15332b | 1382 | txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1); |
f5cd7872 | 1383 | |
09f75cd7 JG |
1384 | dev->stats.tx_packets++; |
1385 | dev->stats.tx_bytes += skb->len; | |
f5cd7872 OJ |
1386 | |
1387 | spin_unlock_irqrestore(&txring->lock, flags); | |
1388 | ||
34c20624 | 1389 | write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1); |
f5cd7872 OJ |
1390 | |
1391 | return NETDEV_TX_OK; | |
1392 | ||
1393 | out_err: | |
1394 | spin_unlock_irqrestore(&txring->lock, flags); | |
ad3c20d1 OJ |
1395 | out_err_nolock: |
1396 | while (nfrags--) | |
1397 | pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags], | |
1398 | PCI_DMA_TODEVICE); | |
1399 | ||
f5cd7872 OJ |
1400 | return NETDEV_TX_BUSY; |
1401 | } | |
1402 | ||
f5cd7872 OJ |
1403 | static void pasemi_mac_set_rx_mode(struct net_device *dev) |
1404 | { | |
5c15332b | 1405 | const struct pasemi_mac *mac = netdev_priv(dev); |
f5cd7872 OJ |
1406 | unsigned int flags; |
1407 | ||
a85b9422 | 1408 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
f5cd7872 OJ |
1409 | |
1410 | /* Set promiscuous */ | |
1411 | if (dev->flags & IFF_PROMISC) | |
1412 | flags |= PAS_MAC_CFG_PCFG_PR; | |
1413 | else | |
1414 | flags &= ~PAS_MAC_CFG_PCFG_PR; | |
1415 | ||
a85b9422 | 1416 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); |
f5cd7872 OJ |
1417 | } |
1418 | ||
1419 | ||
bea3348e | 1420 | static int pasemi_mac_poll(struct napi_struct *napi, int budget) |
f5cd7872 | 1421 | { |
bea3348e SH |
1422 | struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi); |
1423 | struct net_device *dev = mac->netdev; | |
1424 | int pkts; | |
f5cd7872 | 1425 | |
72b05b99 OJ |
1426 | pasemi_mac_clean_tx(tx_ring(mac)); |
1427 | pkts = pasemi_mac_clean_rx(rx_ring(mac), budget); | |
bea3348e | 1428 | if (pkts < budget) { |
f5cd7872 | 1429 | /* all done, no more packets present */ |
bea3348e | 1430 | netif_rx_complete(dev, napi); |
f5cd7872 | 1431 | |
1b0335ea | 1432 | pasemi_mac_restart_rx_intr(mac); |
61cec3bd | 1433 | pasemi_mac_restart_tx_intr(mac); |
f5cd7872 | 1434 | } |
bea3348e | 1435 | return pkts; |
f5cd7872 OJ |
1436 | } |
1437 | ||
ef1ea0b4 OJ |
1438 | static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu) |
1439 | { | |
1440 | struct pasemi_mac *mac = netdev_priv(dev); | |
1441 | unsigned int reg; | |
1442 | unsigned int rcmdsta; | |
1443 | int running; | |
1444 | ||
1445 | if (new_mtu < PE_MIN_MTU || new_mtu > PE_MAX_MTU) | |
1446 | return -EINVAL; | |
1447 | ||
1448 | running = netif_running(dev); | |
1449 | ||
1450 | if (running) { | |
1451 | /* Need to stop the interface, clean out all already | |
1452 | * received buffers, free all unused buffers on the RX | |
1453 | * interface ring, then finally re-fill the rx ring with | |
1454 | * the new-size buffers and restart. | |
1455 | */ | |
1456 | ||
1457 | napi_disable(&mac->napi); | |
1458 | netif_tx_disable(dev); | |
1459 | pasemi_mac_intf_disable(mac); | |
1460 | ||
1461 | rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); | |
1462 | pasemi_mac_pause_rxint(mac); | |
1463 | pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); | |
1464 | pasemi_mac_free_rx_buffers(mac); | |
1465 | } | |
1466 | ||
1467 | /* Change maxf, i.e. what size frames are accepted. | |
1468 | * Need room for ethernet header and CRC word | |
1469 | */ | |
1470 | reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG); | |
1471 | reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M; | |
1472 | reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4); | |
1473 | write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg); | |
1474 | ||
1475 | dev->mtu = new_mtu; | |
1476 | /* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ | |
1477 | mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; | |
1478 | ||
1479 | if (running) { | |
1480 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
1481 | rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN); | |
1482 | ||
1483 | rx_ring(mac)->next_to_fill = 0; | |
1484 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1); | |
1485 | ||
1486 | napi_enable(&mac->napi); | |
1487 | netif_start_queue(dev); | |
1488 | pasemi_mac_intf_enable(mac); | |
1489 | } | |
1490 | ||
1491 | return 0; | |
1492 | } | |
1493 | ||
f5cd7872 OJ |
1494 | static int __devinit |
1495 | pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1496 | { | |
f5cd7872 OJ |
1497 | struct net_device *dev; |
1498 | struct pasemi_mac *mac; | |
1499 | int err; | |
0795af57 | 1500 | DECLARE_MAC_BUF(mac_buf); |
f5cd7872 OJ |
1501 | |
1502 | err = pci_enable_device(pdev); | |
1503 | if (err) | |
1504 | return err; | |
1505 | ||
1506 | dev = alloc_etherdev(sizeof(struct pasemi_mac)); | |
1507 | if (dev == NULL) { | |
1508 | dev_err(&pdev->dev, | |
1509 | "pasemi_mac: Could not allocate ethernet device.\n"); | |
1510 | err = -ENOMEM; | |
1511 | goto out_disable_device; | |
1512 | } | |
1513 | ||
f5cd7872 OJ |
1514 | pci_set_drvdata(pdev, dev); |
1515 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1516 | ||
1517 | mac = netdev_priv(dev); | |
1518 | ||
1519 | mac->pdev = pdev; | |
1520 | mac->netdev = dev; | |
f5cd7872 | 1521 | |
bea3348e SH |
1522 | netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64); |
1523 | ||
5c15332b OJ |
1524 | dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG | |
1525 | NETIF_F_HIGHDMA; | |
bea3348e | 1526 | |
28ae79f5 OJ |
1527 | mac->lro_mgr.max_aggr = LRO_MAX_AGGR; |
1528 | mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS; | |
1529 | mac->lro_mgr.lro_arr = mac->lro_desc; | |
1530 | mac->lro_mgr.get_skb_header = get_skb_hdr; | |
1531 | mac->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID; | |
1532 | mac->lro_mgr.dev = mac->netdev; | |
1533 | mac->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1534 | mac->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
1535 | ||
1536 | ||
34c20624 OJ |
1537 | mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); |
1538 | if (!mac->dma_pdev) { | |
1539 | dev_err(&mac->pdev->dev, "Can't find DMA Controller\n"); | |
1540 | err = -ENODEV; | |
1541 | goto out; | |
1542 | } | |
f5cd7872 | 1543 | |
34c20624 OJ |
1544 | mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); |
1545 | if (!mac->iob_pdev) { | |
1546 | dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n"); | |
1547 | err = -ENODEV; | |
1548 | goto out; | |
1549 | } | |
1550 | ||
1551 | /* get mac addr from device tree */ | |
1552 | if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) { | |
1553 | err = -ENODEV; | |
1554 | goto out; | |
1555 | } | |
1556 | memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr)); | |
1557 | ||
1558 | mac->dma_if = mac_to_intf(mac); | |
1559 | if (mac->dma_if < 0) { | |
1560 | dev_err(&mac->pdev->dev, "Can't map DMA interface\n"); | |
1561 | err = -ENODEV; | |
1562 | goto out; | |
1563 | } | |
f5cd7872 OJ |
1564 | |
1565 | switch (pdev->device) { | |
1566 | case 0xa005: | |
1567 | mac->type = MAC_TYPE_GMAC; | |
1568 | break; | |
1569 | case 0xa006: | |
1570 | mac->type = MAC_TYPE_XAUI; | |
1571 | break; | |
1572 | default: | |
1573 | err = -ENODEV; | |
1574 | goto out; | |
1575 | } | |
1576 | ||
f5cd7872 OJ |
1577 | dev->open = pasemi_mac_open; |
1578 | dev->stop = pasemi_mac_close; | |
1579 | dev->hard_start_xmit = pasemi_mac_start_tx; | |
f5cd7872 | 1580 | dev->set_multicast_list = pasemi_mac_set_rx_mode; |
5cea73b0 | 1581 | dev->set_mac_address = pasemi_mac_set_mac_addr; |
ef1ea0b4 OJ |
1582 | dev->mtu = PE_DEF_MTU; |
1583 | /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ | |
1584 | mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; | |
1585 | ||
1586 | dev->change_mtu = pasemi_mac_change_mtu; | |
f5cd7872 | 1587 | |
b6e05a1b OJ |
1588 | if (err) |
1589 | goto out; | |
f5cd7872 | 1590 | |
ceb51361 OJ |
1591 | mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
1592 | ||
bb6e9590 OJ |
1593 | /* Enable most messages by default */ |
1594 | mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1595 | ||
f5cd7872 OJ |
1596 | err = register_netdev(dev); |
1597 | ||
1598 | if (err) { | |
1599 | dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n", | |
1600 | err); | |
1601 | goto out; | |
69c29d89 | 1602 | } else if netif_msg_probe(mac) |
72b05b99 | 1603 | printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %s\n", |
f5cd7872 | 1604 | dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI", |
72b05b99 | 1605 | mac->dma_if, print_mac(mac_buf, dev->dev_addr)); |
f5cd7872 OJ |
1606 | |
1607 | return err; | |
1608 | ||
1609 | out: | |
b6e05a1b OJ |
1610 | if (mac->iob_pdev) |
1611 | pci_dev_put(mac->iob_pdev); | |
1612 | if (mac->dma_pdev) | |
1613 | pci_dev_put(mac->dma_pdev); | |
b6e05a1b | 1614 | |
f5cd7872 OJ |
1615 | free_netdev(dev); |
1616 | out_disable_device: | |
1617 | pci_disable_device(pdev); | |
1618 | return err; | |
1619 | ||
1620 | } | |
1621 | ||
1622 | static void __devexit pasemi_mac_remove(struct pci_dev *pdev) | |
1623 | { | |
1624 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1625 | struct pasemi_mac *mac; | |
1626 | ||
1627 | if (!netdev) | |
1628 | return; | |
1629 | ||
1630 | mac = netdev_priv(netdev); | |
1631 | ||
1632 | unregister_netdev(netdev); | |
1633 | ||
1634 | pci_disable_device(pdev); | |
1635 | pci_dev_put(mac->dma_pdev); | |
1636 | pci_dev_put(mac->iob_pdev); | |
1637 | ||
34c20624 OJ |
1638 | pasemi_dma_free_chan(&mac->tx->chan); |
1639 | pasemi_dma_free_chan(&mac->rx->chan); | |
b6e05a1b | 1640 | |
f5cd7872 OJ |
1641 | pci_set_drvdata(pdev, NULL); |
1642 | free_netdev(netdev); | |
1643 | } | |
1644 | ||
1645 | static struct pci_device_id pasemi_mac_pci_tbl[] = { | |
1646 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) }, | |
1647 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) }, | |
fd178254 | 1648 | { }, |
f5cd7872 OJ |
1649 | }; |
1650 | ||
1651 | MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl); | |
1652 | ||
1653 | static struct pci_driver pasemi_mac_driver = { | |
1654 | .name = "pasemi_mac", | |
1655 | .id_table = pasemi_mac_pci_tbl, | |
1656 | .probe = pasemi_mac_probe, | |
1657 | .remove = __devexit_p(pasemi_mac_remove), | |
1658 | }; | |
1659 | ||
1660 | static void __exit pasemi_mac_cleanup_module(void) | |
1661 | { | |
1662 | pci_unregister_driver(&pasemi_mac_driver); | |
f5cd7872 OJ |
1663 | } |
1664 | ||
1665 | int pasemi_mac_init_module(void) | |
1666 | { | |
34c20624 OJ |
1667 | int err; |
1668 | ||
1669 | err = pasemi_dma_init(); | |
1670 | if (err) | |
1671 | return err; | |
1672 | ||
f5cd7872 OJ |
1673 | return pci_register_driver(&pasemi_mac_driver); |
1674 | } | |
1675 | ||
f5cd7872 OJ |
1676 | module_init(pasemi_mac_init_module); |
1677 | module_exit(pasemi_mac_cleanup_module); |