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f5cd7872 OJ |
1 | /* |
2 | * Copyright (C) 2006 PA Semi, Inc | |
3 | * | |
4 | * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and | |
5 | * hardware register layouts. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #ifndef PASEMI_MAC_H | |
22 | #define PASEMI_MAC_H | |
23 | ||
24 | #include <linux/ethtool.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/spinlock.h> | |
bb6e9590 | 27 | #include <linux/phy.h> |
f5cd7872 OJ |
28 | |
29 | struct pasemi_mac_txring { | |
30 | spinlock_t lock; | |
fc9e4d2a | 31 | u64 *ring; |
f5cd7872 OJ |
32 | dma_addr_t dma; |
33 | unsigned int size; | |
021fa22e | 34 | unsigned int next_to_fill; |
f5cd7872 | 35 | unsigned int next_to_clean; |
fc9e4d2a | 36 | struct pasemi_mac_buffer *ring_info; |
f5cd7872 OJ |
37 | char irq_name[10]; /* "eth%d tx" */ |
38 | }; | |
39 | ||
40 | struct pasemi_mac_rxring { | |
41 | spinlock_t lock; | |
fc9e4d2a | 42 | u64 *ring; /* RX channel descriptor ring */ |
f5cd7872 OJ |
43 | dma_addr_t dma; |
44 | u64 *buffers; /* RX interface buffer ring */ | |
45 | dma_addr_t buf_dma; | |
46 | unsigned int size; | |
47 | unsigned int next_to_fill; | |
48 | unsigned int next_to_clean; | |
fc9e4d2a | 49 | struct pasemi_mac_buffer *ring_info; |
f5cd7872 OJ |
50 | char irq_name[10]; /* "eth%d rx" */ |
51 | }; | |
52 | ||
53 | struct pasemi_mac { | |
54 | struct net_device *netdev; | |
b6e05a1b OJ |
55 | void __iomem *regs; |
56 | void __iomem *dma_regs; | |
57 | void __iomem *iob_regs; | |
f5cd7872 OJ |
58 | struct pci_dev *pdev; |
59 | struct pci_dev *dma_pdev; | |
60 | struct pci_dev *iob_pdev; | |
bb6e9590 | 61 | struct phy_device *phydev; |
bea3348e | 62 | struct napi_struct napi; |
f5cd7872 OJ |
63 | |
64 | /* Pointer to the cacheable per-channel status registers */ | |
65 | u64 *rx_status; | |
66 | u64 *tx_status; | |
67 | ||
68 | u8 type; | |
69 | #define MAC_TYPE_GMAC 1 | |
70 | #define MAC_TYPE_XAUI 2 | |
71 | u32 dma_txch; | |
72 | u32 dma_if; | |
73 | u32 dma_rxch; | |
74 | ||
75 | u8 mac_addr[6]; | |
76 | ||
77 | struct timer_list rxtimer; | |
78 | ||
79 | struct pasemi_mac_txring *tx; | |
80 | struct pasemi_mac_rxring *rx; | |
771f7404 OJ |
81 | unsigned long tx_irq; |
82 | unsigned long rx_irq; | |
bb6e9590 OJ |
83 | int link; |
84 | int speed; | |
85 | int duplex; | |
ceb51361 OJ |
86 | |
87 | unsigned int msg_enable; | |
bb6e9590 | 88 | char phy_id[BUS_ID_SIZE]; |
f5cd7872 OJ |
89 | }; |
90 | ||
fc9e4d2a | 91 | /* Software status descriptor (ring_info) */ |
f5cd7872 OJ |
92 | struct pasemi_mac_buffer { |
93 | struct sk_buff *skb; | |
94 | dma_addr_t dma; | |
95 | }; | |
96 | ||
97 | ||
98 | /* status register layout in IOB region, at 0xfb800000 */ | |
99 | struct pasdma_status { | |
100 | u64 rx_sta[64]; | |
101 | u64 tx_sta[20]; | |
102 | }; | |
103 | ||
f5cd7872 | 104 | /* MAC CFG register offsets */ |
f5cd7872 OJ |
105 | enum { |
106 | PAS_MAC_CFG_PCFG = 0x80, | |
107 | PAS_MAC_CFG_TXP = 0x98, | |
108 | PAS_MAC_IPC_CHNL = 0x208, | |
109 | }; | |
110 | ||
111 | /* MAC CFG register fields */ | |
112 | #define PAS_MAC_CFG_PCFG_PE 0x80000000 | |
113 | #define PAS_MAC_CFG_PCFG_CE 0x40000000 | |
114 | #define PAS_MAC_CFG_PCFG_BU 0x20000000 | |
115 | #define PAS_MAC_CFG_PCFG_TT 0x10000000 | |
116 | #define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000 | |
117 | #define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000 | |
118 | #define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000 | |
119 | #define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000 | |
120 | #define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000 | |
121 | #define PAS_MAC_CFG_PCFG_T24 0x02000000 | |
122 | #define PAS_MAC_CFG_PCFG_PR 0x01000000 | |
123 | #define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000 | |
124 | #define PAS_MAC_CFG_PCFG_CRO_S 16 | |
125 | #define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00 | |
126 | #define PAS_MAC_CFG_PCFG_IPO_S 8 | |
127 | #define PAS_MAC_CFG_PCFG_S1 0x00000080 | |
128 | #define PAS_MAC_CFG_PCFG_IO_M 0x00000060 | |
129 | #define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000 | |
130 | #define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020 | |
131 | #define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040 | |
132 | #define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060 | |
133 | #define PAS_MAC_CFG_PCFG_LP 0x00000010 | |
134 | #define PAS_MAC_CFG_PCFG_TS 0x00000008 | |
135 | #define PAS_MAC_CFG_PCFG_HD 0x00000004 | |
136 | #define PAS_MAC_CFG_PCFG_SPD_M 0x00000003 | |
137 | #define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000 | |
138 | #define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001 | |
139 | #define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002 | |
140 | #define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003 | |
141 | #define PAS_MAC_CFG_TXP_FCF 0x01000000 | |
142 | #define PAS_MAC_CFG_TXP_FCE 0x00800000 | |
143 | #define PAS_MAC_CFG_TXP_FC 0x00400000 | |
144 | #define PAS_MAC_CFG_TXP_FPC_M 0x00300000 | |
145 | #define PAS_MAC_CFG_TXP_FPC_S 20 | |
146 | #define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \ | |
147 | PAS_MAC_CFG_TXP_FPC_M) | |
148 | #define PAS_MAC_CFG_TXP_RT 0x00080000 | |
149 | #define PAS_MAC_CFG_TXP_BL 0x00040000 | |
150 | #define PAS_MAC_CFG_TXP_SL_M 0x00030000 | |
151 | #define PAS_MAC_CFG_TXP_SL_S 16 | |
152 | #define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \ | |
153 | PAS_MAC_CFG_TXP_SL_M) | |
154 | #define PAS_MAC_CFG_TXP_COB_M 0x0000f000 | |
155 | #define PAS_MAC_CFG_TXP_COB_S 12 | |
156 | #define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \ | |
157 | PAS_MAC_CFG_TXP_COB_M) | |
158 | #define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00 | |
159 | #define PAS_MAC_CFG_TXP_TIFT_S 8 | |
160 | #define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \ | |
161 | PAS_MAC_CFG_TXP_TIFT_M) | |
162 | #define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff | |
163 | #define PAS_MAC_CFG_TXP_TIFG_S 0 | |
164 | #define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \ | |
165 | PAS_MAC_CFG_TXP_TIFG_M) | |
166 | ||
167 | #define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000 | |
168 | #define PAS_MAC_IPC_CHNL_DCHNO_S 16 | |
169 | #define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \ | |
170 | PAS_MAC_IPC_CHNL_DCHNO_M) | |
171 | #define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f | |
172 | #define PAS_MAC_IPC_CHNL_BCH_S 0 | |
173 | #define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \ | |
174 | PAS_MAC_IPC_CHNL_BCH_M) | |
175 | ||
176 | /* All these registers live in the PCI configuration space for the DMA PCI | |
177 | * device. Use the normal PCI config access functions for them. | |
178 | */ | |
179 | enum { | |
180 | PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ | |
181 | PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ | |
182 | PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ | |
183 | PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ | |
184 | }; | |
185 | #define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ | |
186 | #define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ | |
187 | #define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ | |
188 | #define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ | |
189 | ||
190 | ||
191 | /* Per-interface and per-channel registers */ | |
192 | #define _PAS_DMA_RXINT_STRIDE 0x20 | |
193 | #define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE) | |
194 | #define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001 | |
195 | #define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002 | |
cfa8007d OJ |
196 | #define PAS_DMA_RXINT_RCMDSTA_MBT 0x00000008 |
197 | #define PAS_DMA_RXINT_RCMDSTA_MDR 0x00000010 | |
198 | #define PAS_DMA_RXINT_RCMDSTA_MOO 0x00000020 | |
199 | #define PAS_DMA_RXINT_RCMDSTA_MBP 0x00000040 | |
f5cd7872 | 200 | #define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800 |
cfa8007d OJ |
201 | #define PAS_DMA_RXINT_RCMDSTA_DR 0x00001000 |
202 | #define PAS_DMA_RXINT_RCMDSTA_OO 0x00002000 | |
203 | #define PAS_DMA_RXINT_RCMDSTA_BP 0x00004000 | |
204 | #define PAS_DMA_RXINT_RCMDSTA_TB 0x00008000 | |
f5cd7872 OJ |
205 | #define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000 |
206 | #define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000 | |
207 | #define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17 | |
c0efd52b | 208 | #define PAS_DMA_RXINT_CFG(i) (0x204+(i)*_PAS_DMA_RXINT_STRIDE) |
b5254eee OJ |
209 | #define PAS_DMA_RXINT_CFG_RBP 0x80000000 |
210 | #define PAS_DMA_RXINT_CFG_ITRR 0x40000000 | |
c0efd52b OJ |
211 | #define PAS_DMA_RXINT_CFG_DHL_M 0x07000000 |
212 | #define PAS_DMA_RXINT_CFG_DHL_S 24 | |
213 | #define PAS_DMA_RXINT_CFG_DHL(x) (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \ | |
214 | PAS_DMA_RXINT_CFG_DHL_M) | |
af289e80 | 215 | #define PAS_DMA_RXINT_CFG_ITR 0x00400000 |
9a50bebd OJ |
216 | #define PAS_DMA_RXINT_CFG_LW 0x00200000 |
217 | #define PAS_DMA_RXINT_CFG_L2 0x00100000 | |
b5254eee | 218 | #define PAS_DMA_RXINT_CFG_HEN 0x00080000 |
c0efd52b OJ |
219 | #define PAS_DMA_RXINT_CFG_WIF 0x00000002 |
220 | #define PAS_DMA_RXINT_CFG_WIL 0x00000001 | |
221 | ||
f5cd7872 OJ |
222 | #define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE) |
223 | #define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff | |
224 | #define PAS_DMA_RXINT_INCR_INCR_S 0 | |
225 | #define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff) | |
226 | #define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE) | |
227 | #define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f) | |
228 | #define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE) | |
229 | #define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff) | |
230 | #define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */ | |
231 | #define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */ | |
232 | #define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \ | |
233 | PAS_DMA_RXINT_BASEU_SIZ_M) | |
234 | ||
235 | ||
236 | #define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ | |
237 | #define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ | |
238 | #define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ | |
239 | #define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ | |
240 | #define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ | |
241 | #define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ | |
242 | #define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ | |
243 | #define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ | |
244 | #define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) | |
245 | #define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ | |
246 | #define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ | |
247 | #define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ | |
9e81d331 OJ |
248 | #define PAS_DMA_TXCHAN_TCMDSTA_SZ 0x00000800 |
249 | #define PAS_DMA_TXCHAN_TCMDSTA_DB 0x00000400 | |
250 | #define PAS_DMA_TXCHAN_TCMDSTA_DE 0x00000200 | |
251 | #define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100 | |
f5cd7872 OJ |
252 | #define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) |
253 | #define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ | |
254 | #define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c | |
255 | #define PAS_DMA_TXCHAN_CFG_TATTR_S 2 | |
256 | #define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ | |
257 | PAS_DMA_TXCHAN_CFG_TATTR_M) | |
258 | #define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 | |
259 | #define PAS_DMA_TXCHAN_CFG_WT_S 6 | |
260 | #define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ | |
261 | PAS_DMA_TXCHAN_CFG_WT_M) | |
af289e80 OJ |
262 | #define PAS_DMA_TXCHAN_CFG_TRD 0x00010000 /* translate data */ |
263 | #define PAS_DMA_TXCHAN_CFG_TRR 0x00008000 /* translate rings */ | |
f5cd7872 | 264 | #define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ |
af289e80 OJ |
265 | #define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ |
266 | #define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ | |
f5cd7872 OJ |
267 | #define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) |
268 | #define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) | |
269 | #define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 | |
270 | #define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 | |
271 | #define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ | |
272 | PAS_DMA_TXCHAN_BASEL_BRBL_M) | |
273 | #define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) | |
274 | #define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff | |
275 | #define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 | |
276 | #define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ | |
277 | PAS_DMA_TXCHAN_BASEU_BRBH_M) | |
278 | /* # of cache lines worth of buffer ring */ | |
279 | #define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 | |
280 | #define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ | |
281 | #define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ | |
282 | PAS_DMA_TXCHAN_BASEU_SIZ_M) | |
283 | ||
284 | #define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */ | |
285 | #define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */ | |
286 | #define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */ | |
287 | #define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */ | |
288 | #define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */ | |
289 | #define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */ | |
290 | #define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */ | |
291 | #define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE) | |
292 | #define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */ | |
293 | #define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */ | |
294 | #define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */ | |
295 | #define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000 | |
9e81d331 OJ |
296 | #define PAS_DMA_RXCHAN_CCMDSTA_OD 0x00002000 |
297 | #define PAS_DMA_RXCHAN_CCMDSTA_FD 0x00001000 | |
298 | #define PAS_DMA_RXCHAN_CCMDSTA_DT 0x00000800 | |
f5cd7872 | 299 | #define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE) |
af289e80 | 300 | #define PAS_DMA_RXCHAN_CFG_CTR 0x00000400 |
f5cd7872 OJ |
301 | #define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380 |
302 | #define PAS_DMA_RXCHAN_CFG_HBU_S 7 | |
303 | #define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \ | |
304 | PAS_DMA_RXCHAN_CFG_HBU_M) | |
305 | #define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE) | |
306 | #define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE) | |
307 | #define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0 | |
308 | #define PAS_DMA_RXCHAN_BASEL_BRBL_S 0 | |
309 | #define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \ | |
310 | PAS_DMA_RXCHAN_BASEL_BRBL_M) | |
311 | #define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE) | |
312 | #define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff | |
313 | #define PAS_DMA_RXCHAN_BASEU_BRBH_S 0 | |
314 | #define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \ | |
315 | PAS_DMA_RXCHAN_BASEU_BRBH_M) | |
316 | /* # of cache lines worth of buffer ring */ | |
317 | #define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000 | |
318 | #define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ | |
319 | #define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \ | |
320 | PAS_DMA_RXCHAN_BASEU_SIZ_M) | |
321 | ||
322 | #define PAS_STATUS_PCNT_M 0x000000000000ffffull | |
323 | #define PAS_STATUS_PCNT_S 0 | |
324 | #define PAS_STATUS_DCNT_M 0x00000000ffff0000ull | |
325 | #define PAS_STATUS_DCNT_S 16 | |
326 | #define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull | |
327 | #define PAS_STATUS_BPCNT_S 32 | |
6dfa7522 | 328 | #define PAS_STATUS_CAUSE_M 0xf000000000000000ull |
f5cd7872 OJ |
329 | #define PAS_STATUS_TIMER 0x1000000000000000ull |
330 | #define PAS_STATUS_ERROR 0x2000000000000000ull | |
331 | #define PAS_STATUS_SOFT 0x4000000000000000ull | |
332 | #define PAS_STATUS_INT 0x8000000000000000ull | |
333 | ||
9a50bebd OJ |
334 | #define PAS_IOB_COM_PKTHDRCNT 0x120 |
335 | #define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M 0x0fff0000 | |
336 | #define PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S 16 | |
337 | #define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M 0x00000fff | |
338 | #define PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S 0 | |
339 | ||
f5cd7872 OJ |
340 | #define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) |
341 | #define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff | |
342 | #define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 | |
343 | #define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ | |
344 | PAS_IOB_DMA_RXCH_CFG_CNTTH_M) | |
345 | #define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) | |
346 | #define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff | |
347 | #define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 | |
348 | #define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ | |
349 | PAS_IOB_DMA_TXCH_CFG_CNTTH_M) | |
350 | #define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) | |
351 | #define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 | |
352 | #define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff | |
353 | #define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 | |
354 | #define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ | |
355 | PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) | |
356 | #define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) | |
357 | #define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 | |
358 | #define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff | |
359 | #define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 | |
360 | #define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ | |
361 | PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) | |
362 | #define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) | |
363 | #define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 | |
a54c5451 | 364 | #define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 |
f5cd7872 OJ |
365 | #define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ |
366 | PAS_IOB_DMA_RXCH_RESET_PCNT_M) | |
367 | #define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 | |
368 | #define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 | |
369 | #define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 | |
370 | #define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 | |
371 | #define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 | |
372 | #define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 | |
373 | #define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) | |
374 | #define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 | |
a54c5451 | 375 | #define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 |
f5cd7872 OJ |
376 | #define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ |
377 | PAS_IOB_DMA_TXCH_RESET_PCNT_M) | |
378 | #define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 | |
379 | #define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 | |
380 | #define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 | |
381 | #define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 | |
382 | #define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 | |
383 | #define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 | |
384 | ||
385 | #define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 | |
386 | #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff | |
387 | #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 | |
388 | #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ | |
389 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) | |
390 | ||
391 | /* Transmit descriptor fields */ | |
392 | #define XCT_MACTX_T 0x8000000000000000ull | |
393 | #define XCT_MACTX_ST 0x4000000000000000ull | |
394 | #define XCT_MACTX_NORES 0x0000000000000000ull | |
395 | #define XCT_MACTX_8BRES 0x1000000000000000ull | |
396 | #define XCT_MACTX_24BRES 0x2000000000000000ull | |
397 | #define XCT_MACTX_40BRES 0x3000000000000000ull | |
398 | #define XCT_MACTX_I 0x0800000000000000ull | |
399 | #define XCT_MACTX_O 0x0400000000000000ull | |
400 | #define XCT_MACTX_E 0x0200000000000000ull | |
401 | #define XCT_MACTX_VLAN_M 0x0180000000000000ull | |
402 | #define XCT_MACTX_VLAN_NOP 0x0000000000000000ull | |
403 | #define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull | |
404 | #define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull | |
405 | #define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull | |
406 | #define XCT_MACTX_CRC_M 0x0060000000000000ull | |
407 | #define XCT_MACTX_CRC_NOP 0x0000000000000000ull | |
408 | #define XCT_MACTX_CRC_INSERT 0x0020000000000000ull | |
409 | #define XCT_MACTX_CRC_PAD 0x0040000000000000ull | |
410 | #define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull | |
411 | #define XCT_MACTX_SS 0x0010000000000000ull | |
412 | #define XCT_MACTX_LLEN_M 0x00007fff00000000ull | |
413 | #define XCT_MACTX_LLEN_S 32ull | |
414 | #define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ | |
415 | XCT_MACTX_LLEN_M) | |
416 | #define XCT_MACTX_IPH_M 0x00000000f8000000ull | |
417 | #define XCT_MACTX_IPH_S 27ull | |
418 | #define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ | |
419 | XCT_MACTX_IPH_M) | |
420 | #define XCT_MACTX_IPO_M 0x0000000007c00000ull | |
421 | #define XCT_MACTX_IPO_S 22ull | |
422 | #define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ | |
423 | XCT_MACTX_IPO_M) | |
424 | #define XCT_MACTX_CSUM_M 0x0000000000000060ull | |
425 | #define XCT_MACTX_CSUM_NOP 0x0000000000000000ull | |
426 | #define XCT_MACTX_CSUM_TCP 0x0000000000000040ull | |
427 | #define XCT_MACTX_CSUM_UDP 0x0000000000000060ull | |
428 | #define XCT_MACTX_V6 0x0000000000000010ull | |
429 | #define XCT_MACTX_C 0x0000000000000004ull | |
430 | #define XCT_MACTX_AL2 0x0000000000000002ull | |
431 | ||
432 | /* Receive descriptor fields */ | |
433 | #define XCT_MACRX_T 0x8000000000000000ull | |
434 | #define XCT_MACRX_ST 0x4000000000000000ull | |
b5254eee OJ |
435 | #define XCT_MACRX_RR_M 0x3000000000000000ull |
436 | #define XCT_MACRX_RR_NORES 0x0000000000000000ull | |
437 | #define XCT_MACRX_RR_8BRES 0x1000000000000000ull | |
f5cd7872 OJ |
438 | #define XCT_MACRX_O 0x0400000000000000ull |
439 | #define XCT_MACRX_E 0x0200000000000000ull | |
440 | #define XCT_MACRX_FF 0x0100000000000000ull | |
441 | #define XCT_MACRX_PF 0x0080000000000000ull | |
442 | #define XCT_MACRX_OB 0x0040000000000000ull | |
443 | #define XCT_MACRX_OD 0x0020000000000000ull | |
444 | #define XCT_MACRX_FS 0x0010000000000000ull | |
445 | #define XCT_MACRX_NB_M 0x000fc00000000000ull | |
446 | #define XCT_MACRX_NB_S 46ULL | |
447 | #define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \ | |
448 | XCT_MACRX_NB_M) | |
449 | #define XCT_MACRX_LLEN_M 0x00003fff00000000ull | |
450 | #define XCT_MACRX_LLEN_S 32ULL | |
451 | #define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \ | |
452 | XCT_MACRX_LLEN_M) | |
453 | #define XCT_MACRX_CRC 0x0000000080000000ull | |
454 | #define XCT_MACRX_LEN_M 0x0000000060000000ull | |
455 | #define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull | |
456 | #define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull | |
457 | #define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull | |
458 | #define XCT_MACRX_CAST_M 0x0000000018000000ull | |
459 | #define XCT_MACRX_CAST_UNI 0x0000000000000000ull | |
460 | #define XCT_MACRX_CAST_MULTI 0x0000000008000000ull | |
461 | #define XCT_MACRX_CAST_BROAD 0x0000000010000000ull | |
462 | #define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull | |
463 | #define XCT_MACRX_VLC_M 0x0000000006000000ull | |
464 | #define XCT_MACRX_FM 0x0000000001000000ull | |
465 | #define XCT_MACRX_HTY_M 0x0000000000c00000ull | |
466 | #define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull | |
467 | #define XCT_MACRX_HTY_IPV6 0x0000000000400000ull | |
468 | #define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull | |
469 | #define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull | |
470 | #define XCT_MACRX_IPP_M 0x00000000003f0000ull | |
471 | #define XCT_MACRX_IPP_S 16 | |
472 | #define XCT_MACRX_CSUM_M 0x000000000000ffffull | |
473 | #define XCT_MACRX_CSUM_S 0 | |
474 | ||
475 | #define XCT_PTR_T 0x8000000000000000ull | |
476 | #define XCT_PTR_LEN_M 0x7ffff00000000000ull | |
477 | #define XCT_PTR_LEN_S 44 | |
478 | #define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ | |
479 | XCT_PTR_LEN_M) | |
480 | #define XCT_PTR_ADDR_M 0x00000fffffffffffull | |
481 | #define XCT_PTR_ADDR_S 0 | |
482 | #define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ | |
483 | XCT_PTR_ADDR_M) | |
484 | ||
b5254eee OJ |
485 | /* Receive interface 8byte result fields */ |
486 | #define XCT_RXRES_8B_L4O_M 0xff00000000000000ull | |
487 | #define XCT_RXRES_8B_L4O_S 56 | |
488 | #define XCT_RXRES_8B_RULE_M 0x00ffff0000000000ull | |
489 | #define XCT_RXRES_8B_RULE_S 40 | |
490 | #define XCT_RXRES_8B_EVAL_M 0x000000ffff000000ull | |
491 | #define XCT_RXRES_8B_EVAL_S 24 | |
492 | #define XCT_RXRES_8B_HTYPE_M 0x0000000000f00000ull | |
493 | #define XCT_RXRES_8B_HASH_M 0x00000000000fffffull | |
494 | #define XCT_RXRES_8B_HASH_S 0 | |
495 | ||
f5cd7872 OJ |
496 | /* Receive interface buffer fields */ |
497 | #define XCT_RXB_LEN_M 0x0ffff00000000000ull | |
498 | #define XCT_RXB_LEN_S 44 | |
499 | #define XCT_RXB_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & XCT_PTR_LEN_M) | |
500 | #define XCT_RXB_ADDR_M 0x00000fffffffffffull | |
501 | #define XCT_RXB_ADDR_S 0 | |
502 | #define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & XCT_PTR_ADDR_M) | |
503 | ||
504 | ||
505 | #endif /* PASEMI_MAC_H */ |