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1da177e4 LT |
1 | /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ |
2 | /* | |
3 | * Copyright 1996-1999 Thomas Bogendoerfer | |
4 | * | |
5 | * Derived from the lance driver written 1993,1994,1995 by Donald Becker. | |
6 | * | |
7 | * Copyright 1993 United States Government as represented by the | |
8 | * Director, National Security Agency. | |
9 | * | |
10 | * This software may be used and distributed according to the terms | |
11 | * of the GNU General Public License, incorporated herein by reference. | |
12 | * | |
13 | * This driver is for PCnet32 and PCnetPCI based ethercards | |
14 | */ | |
15 | /************************************************************************** | |
16 | * 23 Oct, 2000. | |
17 | * Fixed a few bugs, related to running the controller in 32bit mode. | |
18 | * | |
19 | * Carsten Langgaard, carstenl@mips.com | |
20 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | |
21 | * | |
22 | *************************************************************************/ | |
23 | ||
24 | #define DRV_NAME "pcnet32" | |
2964bbd7 DF |
25 | #define DRV_VERSION "1.31c" |
26 | #define DRV_RELDATE "01.Nov.2005" | |
1da177e4 LT |
27 | #define PFX DRV_NAME ": " |
28 | ||
29 | static const char *version = | |
30 | DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n"; | |
31 | ||
32 | #include <linux/module.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/errno.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/interrupt.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/init.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/mii.h> | |
44 | #include <linux/crc32.h> | |
45 | #include <linux/netdevice.h> | |
46 | #include <linux/etherdevice.h> | |
47 | #include <linux/skbuff.h> | |
48 | #include <linux/spinlock.h> | |
49 | #include <linux/moduleparam.h> | |
50 | #include <linux/bitops.h> | |
51 | ||
52 | #include <asm/dma.h> | |
53 | #include <asm/io.h> | |
54 | #include <asm/uaccess.h> | |
55 | #include <asm/irq.h> | |
56 | ||
57 | /* | |
58 | * PCI device identifiers for "new style" Linux PCI Device Drivers | |
59 | */ | |
60 | static struct pci_device_id pcnet32_pci_tbl[] = { | |
61 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
62 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
63 | /* | |
64 | * Adapters that were sold with IBM's RS/6000 or pSeries hardware have | |
65 | * the incorrect vendor id. | |
66 | */ | |
67 | { PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, | |
68 | PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, 0 }, | |
69 | { 0, } | |
70 | }; | |
71 | ||
72 | MODULE_DEVICE_TABLE (pci, pcnet32_pci_tbl); | |
73 | ||
74 | static int cards_found; | |
75 | ||
76 | /* | |
77 | * VLB I/O addresses | |
78 | */ | |
79 | static unsigned int pcnet32_portlist[] __initdata = | |
80 | { 0x300, 0x320, 0x340, 0x360, 0 }; | |
81 | ||
82 | ||
83 | ||
84 | static int pcnet32_debug = 0; | |
85 | static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ | |
86 | static int pcnet32vlb; /* check for VLB cards ? */ | |
87 | ||
88 | static struct net_device *pcnet32_dev; | |
89 | ||
90 | static int max_interrupt_work = 2; | |
91 | static int rx_copybreak = 200; | |
92 | ||
93 | #define PCNET32_PORT_AUI 0x00 | |
94 | #define PCNET32_PORT_10BT 0x01 | |
95 | #define PCNET32_PORT_GPSI 0x02 | |
96 | #define PCNET32_PORT_MII 0x03 | |
97 | ||
98 | #define PCNET32_PORT_PORTSEL 0x03 | |
99 | #define PCNET32_PORT_ASEL 0x04 | |
100 | #define PCNET32_PORT_100 0x40 | |
101 | #define PCNET32_PORT_FD 0x80 | |
102 | ||
103 | #define PCNET32_DMA_MASK 0xffffffff | |
104 | ||
105 | #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) | |
106 | #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) | |
107 | ||
108 | /* | |
109 | * table to translate option values from tulip | |
110 | * to internal options | |
111 | */ | |
112 | static unsigned char options_mapping[] = { | |
113 | PCNET32_PORT_ASEL, /* 0 Auto-select */ | |
114 | PCNET32_PORT_AUI, /* 1 BNC/AUI */ | |
115 | PCNET32_PORT_AUI, /* 2 AUI/BNC */ | |
116 | PCNET32_PORT_ASEL, /* 3 not supported */ | |
117 | PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ | |
118 | PCNET32_PORT_ASEL, /* 5 not supported */ | |
119 | PCNET32_PORT_ASEL, /* 6 not supported */ | |
120 | PCNET32_PORT_ASEL, /* 7 not supported */ | |
121 | PCNET32_PORT_ASEL, /* 8 not supported */ | |
122 | PCNET32_PORT_MII, /* 9 MII 10baseT */ | |
123 | PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ | |
124 | PCNET32_PORT_MII, /* 11 MII (autosel) */ | |
125 | PCNET32_PORT_10BT, /* 12 10BaseT */ | |
126 | PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ | |
127 | PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */ | |
128 | PCNET32_PORT_ASEL /* 15 not supported */ | |
129 | }; | |
130 | ||
131 | static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { | |
132 | "Loopback test (offline)" | |
133 | }; | |
134 | #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN) | |
135 | ||
136 | #define PCNET32_NUM_REGS 168 | |
137 | ||
138 | #define MAX_UNITS 8 /* More are supported, limit only on options */ | |
139 | static int options[MAX_UNITS]; | |
140 | static int full_duplex[MAX_UNITS]; | |
141 | static int homepna[MAX_UNITS]; | |
142 | ||
143 | /* | |
144 | * Theory of Operation | |
145 | * | |
146 | * This driver uses the same software structure as the normal lance | |
147 | * driver. So look for a verbose description in lance.c. The differences | |
148 | * to the normal lance driver is the use of the 32bit mode of PCnet32 | |
149 | * and PCnetPCI chips. Because these chips are 32bit chips, there is no | |
150 | * 16MB limitation and we don't need bounce buffers. | |
151 | */ | |
152 | ||
153 | /* | |
154 | * History: | |
155 | * v0.01: Initial version | |
156 | * only tested on Alpha Noname Board | |
157 | * v0.02: changed IRQ handling for new interrupt scheme (dev_id) | |
158 | * tested on a ASUS SP3G | |
159 | * v0.10: fixed an odd problem with the 79C974 in a Compaq Deskpro XL | |
160 | * looks like the 974 doesn't like stopping and restarting in a | |
161 | * short period of time; now we do a reinit of the lance; the | |
162 | * bug was triggered by doing ifconfig eth0 <ip> broadcast <addr> | |
163 | * and hangs the machine (thanks to Klaus Liedl for debugging) | |
164 | * v0.12: by suggestion from Donald Becker: Renamed driver to pcnet32, | |
165 | * made it standalone (no need for lance.c) | |
166 | * v0.13: added additional PCI detecting for special PCI devices (Compaq) | |
167 | * v0.14: stripped down additional PCI probe (thanks to David C Niemi | |
168 | * and sveneric@xs4all.nl for testing this on their Compaq boxes) | |
169 | * v0.15: added 79C965 (VLB) probe | |
170 | * added interrupt sharing for PCI chips | |
171 | * v0.16: fixed set_multicast_list on Alpha machines | |
172 | * v0.17: removed hack from dev.c; now pcnet32 uses ethif_probe in Space.c | |
173 | * v0.19: changed setting of autoselect bit | |
174 | * v0.20: removed additional Compaq PCI probe; there is now a working one | |
175 | * in arch/i386/bios32.c | |
176 | * v0.21: added endian conversion for ppc, from work by cort@cs.nmt.edu | |
177 | * v0.22: added printing of status to ring dump | |
178 | * v0.23: changed enet_statistics to net_devive_stats | |
179 | * v0.90: added multicast filter | |
180 | * added module support | |
181 | * changed irq probe to new style | |
182 | * added PCnetFast chip id | |
183 | * added fix for receive stalls with Intel saturn chipsets | |
184 | * added in-place rx skbs like in the tulip driver | |
185 | * minor cleanups | |
186 | * v0.91: added PCnetFast+ chip id | |
187 | * back port to 2.0.x | |
188 | * v1.00: added some stuff from Donald Becker's 2.0.34 version | |
189 | * added support for byte counters in net_dev_stats | |
190 | * v1.01: do ring dumps, only when debugging the driver | |
191 | * increased the transmit timeout | |
192 | * v1.02: fixed memory leak in pcnet32_init_ring() | |
193 | * v1.10: workaround for stopped transmitter | |
194 | * added port selection for modules | |
195 | * detect special T1/E1 WAN card and setup port selection | |
196 | * v1.11: fixed wrong checking of Tx errors | |
197 | * v1.20: added check of return value kmalloc (cpeterso@cs.washington.edu) | |
198 | * added save original kmalloc addr for freeing (mcr@solidum.com) | |
199 | * added support for PCnetHome chip (joe@MIT.EDU) | |
200 | * rewritten PCI card detection | |
201 | * added dwio mode to get driver working on some PPC machines | |
202 | * v1.21: added mii selection and mii ioctl | |
203 | * v1.22: changed pci scanning code to make PPC people happy | |
204 | * fixed switching to 32bit mode in pcnet32_open() (thanks | |
205 | * to Michael Richard <mcr@solidum.com> for noticing this one) | |
206 | * added sub vendor/device id matching (thanks again to | |
207 | * Michael Richard <mcr@solidum.com>) | |
208 | * added chip id for 79c973/975 (thanks to Zach Brown <zab@zabbo.net>) | |
209 | * v1.23 fixed small bug, when manual selecting MII speed/duplex | |
210 | * v1.24 Applied Thomas' patch to use TxStartPoint and thus decrease TxFIFO | |
211 | * underflows. Added tx_start_pt module parameter. Increased | |
212 | * TX_RING_SIZE from 16 to 32. Added #ifdef'd code to use DXSUFLO | |
213 | * for FAST[+] chipsets. <kaf@fc.hp.com> | |
214 | * v1.24ac Added SMP spinlocking - Alan Cox <alan@redhat.com> | |
215 | * v1.25kf Added No Interrupt on successful Tx for some Tx's <kaf@fc.hp.com> | |
216 | * v1.26 Converted to pci_alloc_consistent, Jamey Hicks / George France | |
217 | * <jamey@crl.dec.com> | |
218 | * - Fixed a few bugs, related to running the controller in 32bit mode. | |
219 | * 23 Oct, 2000. Carsten Langgaard, carstenl@mips.com | |
220 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | |
221 | * v1.26p Fix oops on rmmod+insmod; plug i/o resource leak - Paul Gortmaker | |
222 | * v1.27 improved CSR/PROM address detection, lots of cleanups, | |
223 | * new pcnet32vlb module option, HP-PARISC support, | |
224 | * added module parameter descriptions, | |
225 | * initial ethtool support - Helge Deller <deller@gmx.de> | |
226 | * v1.27a Sun Feb 10 2002 Go Taniguchi <go@turbolinux.co.jp> | |
227 | * use alloc_etherdev and register_netdev | |
228 | * fix pci probe not increment cards_found | |
229 | * FD auto negotiate error workaround for xSeries250 | |
230 | * clean up and using new mii module | |
231 | * v1.27b Sep 30 2002 Kent Yoder <yoder1@us.ibm.com> | |
232 | * Added timer for cable connection state changes. | |
233 | * v1.28 20 Feb 2004 Don Fry <brazilnut@us.ibm.com> | |
234 | * Jon Mason <jonmason@us.ibm.com>, Chinmay Albal <albal@in.ibm.com> | |
235 | * Now uses ethtool_ops, netif_msg_* and generic_mii_ioctl. | |
236 | * Fixes bogus 'Bus master arbitration failure', pci_[un]map_single | |
237 | * length errors, and transmit hangs. Cleans up after errors in open. | |
238 | * Jim Lewis <jklewis@us.ibm.com> added ethernet loopback test. | |
239 | * Thomas Munck Steenholdt <tmus@tmus.dk> non-mii ioctl corrections. | |
240 | * v1.29 6 Apr 2004 Jim Lewis <jklewis@us.ibm.com> added physical | |
241 | * identification code (blink led's) and register dump. | |
242 | * Don Fry added timer for 971/972 so skbufs don't remain on tx ring | |
243 | * forever. | |
244 | * v1.30 18 May 2004 Don Fry removed timer and Last Transmit Interrupt | |
245 | * (ltint) as they added complexity and didn't give good throughput. | |
246 | * v1.30a 22 May 2004 Don Fry limit frames received during interrupt. | |
247 | * v1.30b 24 May 2004 Don Fry fix bogus tx carrier errors with 79c973, | |
248 | * assisted by Bruce Penrod <bmpenrod@endruntechnologies.com>. | |
249 | * v1.30c 25 May 2004 Don Fry added netif_wake_queue after pcnet32_restart. | |
250 | * v1.30d 01 Jun 2004 Don Fry discard oversize rx packets. | |
251 | * v1.30e 11 Jun 2004 Don Fry recover after fifo error and rx hang. | |
252 | * v1.30f 16 Jun 2004 Don Fry cleanup IRQ to allow 0 and 1 for PCI, | |
253 | * expanding on suggestions from Ralf Baechle <ralf@linux-mips.org>, | |
254 | * and Brian Murphy <brian@murphy.dk>. | |
255 | * v1.30g 22 Jun 2004 Patrick Simmons <psimmons@flash.net> added option | |
256 | * homepna for selecting HomePNA mode for PCNet/Home 79C978. | |
257 | * v1.30h 24 Jun 2004 Don Fry correctly select auto, speed, duplex in bcr32. | |
258 | * v1.30i 28 Jun 2004 Don Fry change to use module_param. | |
1bcd3153 | 259 | * v1.30j 29 Apr 2005 Don Fry fix skb/map leak with loopback test. |
eabf0415 | 260 | * v1.31 02 Sep 2005 Hubert WS Lin <wslin@tw.ibm.c0m> added set_ringparam(). |
76209926 HWL |
261 | * v1.31a 12 Sep 2005 Hubert WS Lin <wslin@tw.ibm.c0m> set min ring size to 4 |
262 | * to allow loopback test to work unchanged. | |
a88c844c DF |
263 | * v1.31b 06 Oct 2005 Don Fry changed alloc_ring to show name of device |
264 | * if allocation fails | |
2964bbd7 DF |
265 | * v1.31c 01 Nov 2005 Don Fry Allied Telesyn 2700/2701 FX are 100Mbit only. |
266 | * Force 100Mbit FD if Auto (ASEL) is selected. | |
267 | * See Bugzilla 2669 and 4551. | |
1da177e4 LT |
268 | */ |
269 | ||
270 | ||
271 | /* | |
272 | * Set the number of Tx and Rx buffers, using Log_2(# buffers). | |
273 | * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. | |
274 | * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). | |
275 | */ | |
276 | #ifndef PCNET32_LOG_TX_BUFFERS | |
eabf0415 HWL |
277 | #define PCNET32_LOG_TX_BUFFERS 4 |
278 | #define PCNET32_LOG_RX_BUFFERS 5 | |
279 | #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ | |
280 | #define PCNET32_LOG_MAX_RX_BUFFERS 9 | |
1da177e4 LT |
281 | #endif |
282 | ||
283 | #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) | |
eabf0415 | 284 | #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) |
1da177e4 LT |
285 | |
286 | #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) | |
eabf0415 | 287 | #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) |
1da177e4 LT |
288 | |
289 | #define PKT_BUF_SZ 1544 | |
290 | ||
291 | /* Offsets from base I/O address. */ | |
292 | #define PCNET32_WIO_RDP 0x10 | |
293 | #define PCNET32_WIO_RAP 0x12 | |
294 | #define PCNET32_WIO_RESET 0x14 | |
295 | #define PCNET32_WIO_BDP 0x16 | |
296 | ||
297 | #define PCNET32_DWIO_RDP 0x10 | |
298 | #define PCNET32_DWIO_RAP 0x14 | |
299 | #define PCNET32_DWIO_RESET 0x18 | |
300 | #define PCNET32_DWIO_BDP 0x1C | |
301 | ||
302 | #define PCNET32_TOTAL_SIZE 0x20 | |
303 | ||
304 | /* The PCNET32 Rx and Tx ring descriptors. */ | |
305 | struct pcnet32_rx_head { | |
306 | u32 base; | |
307 | s16 buf_length; | |
308 | s16 status; | |
309 | u32 msg_length; | |
310 | u32 reserved; | |
311 | }; | |
312 | ||
313 | struct pcnet32_tx_head { | |
314 | u32 base; | |
315 | s16 length; | |
316 | s16 status; | |
317 | u32 misc; | |
318 | u32 reserved; | |
319 | }; | |
320 | ||
321 | /* The PCNET32 32-Bit initialization block, described in databook. */ | |
322 | struct pcnet32_init_block { | |
323 | u16 mode; | |
324 | u16 tlen_rlen; | |
325 | u8 phys_addr[6]; | |
326 | u16 reserved; | |
327 | u32 filter[2]; | |
328 | /* Receive and transmit ring base, along with extra bits. */ | |
329 | u32 rx_ring; | |
330 | u32 tx_ring; | |
331 | }; | |
332 | ||
333 | /* PCnet32 access functions */ | |
334 | struct pcnet32_access { | |
335 | u16 (*read_csr)(unsigned long, int); | |
336 | void (*write_csr)(unsigned long, int, u16); | |
337 | u16 (*read_bcr)(unsigned long, int); | |
338 | void (*write_bcr)(unsigned long, int, u16); | |
339 | u16 (*read_rap)(unsigned long); | |
340 | void (*write_rap)(unsigned long, u16); | |
341 | void (*reset)(unsigned long); | |
342 | }; | |
343 | ||
344 | /* | |
76209926 HWL |
345 | * The first field of pcnet32_private is read by the ethernet device |
346 | * so the structure should be allocated using pci_alloc_consistent(). | |
1da177e4 LT |
347 | */ |
348 | struct pcnet32_private { | |
76209926 | 349 | struct pcnet32_init_block init_block; |
1da177e4 | 350 | /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ |
eabf0415 HWL |
351 | struct pcnet32_rx_head *rx_ring; |
352 | struct pcnet32_tx_head *tx_ring; | |
1da177e4 LT |
353 | dma_addr_t dma_addr; /* DMA address of beginning of this |
354 | object, returned by | |
355 | pci_alloc_consistent */ | |
356 | struct pci_dev *pci_dev; /* Pointer to the associated pci device | |
357 | structure */ | |
358 | const char *name; | |
359 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ | |
eabf0415 HWL |
360 | struct sk_buff **tx_skbuff; |
361 | struct sk_buff **rx_skbuff; | |
362 | dma_addr_t *tx_dma_addr; | |
363 | dma_addr_t *rx_dma_addr; | |
1da177e4 LT |
364 | struct pcnet32_access a; |
365 | spinlock_t lock; /* Guard lock */ | |
366 | unsigned int cur_rx, cur_tx; /* The next free ring entry */ | |
eabf0415 HWL |
367 | unsigned int rx_ring_size; /* current rx ring size */ |
368 | unsigned int tx_ring_size; /* current tx ring size */ | |
369 | unsigned int rx_mod_mask; /* rx ring modular mask */ | |
370 | unsigned int tx_mod_mask; /* tx ring modular mask */ | |
371 | unsigned short rx_len_bits; | |
372 | unsigned short tx_len_bits; | |
373 | dma_addr_t rx_ring_dma_addr; | |
374 | dma_addr_t tx_ring_dma_addr; | |
1da177e4 LT |
375 | unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */ |
376 | struct net_device_stats stats; | |
377 | char tx_full; | |
378 | int options; | |
379 | unsigned int shared_irq:1, /* shared irq possible */ | |
380 | dxsuflo:1, /* disable transmit stop on uflo */ | |
381 | mii:1; /* mii port available */ | |
382 | struct net_device *next; | |
383 | struct mii_if_info mii_if; | |
384 | struct timer_list watchdog_timer; | |
385 | struct timer_list blink_timer; | |
386 | u32 msg_enable; /* debug message level */ | |
387 | }; | |
388 | ||
389 | static void pcnet32_probe_vlbus(void); | |
390 | static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); | |
391 | static int pcnet32_probe1(unsigned long, int, struct pci_dev *); | |
392 | static int pcnet32_open(struct net_device *); | |
393 | static int pcnet32_init_ring(struct net_device *); | |
394 | static int pcnet32_start_xmit(struct sk_buff *, struct net_device *); | |
395 | static int pcnet32_rx(struct net_device *); | |
396 | static void pcnet32_tx_timeout (struct net_device *dev); | |
397 | static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *); | |
398 | static int pcnet32_close(struct net_device *); | |
399 | static struct net_device_stats *pcnet32_get_stats(struct net_device *); | |
400 | static void pcnet32_load_multicast(struct net_device *dev); | |
401 | static void pcnet32_set_multicast_list(struct net_device *); | |
402 | static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); | |
403 | static void pcnet32_watchdog(struct net_device *); | |
404 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num); | |
405 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val); | |
406 | static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); | |
407 | static void pcnet32_ethtool_test(struct net_device *dev, | |
408 | struct ethtool_test *eth_test, u64 *data); | |
409 | static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1); | |
410 | static int pcnet32_phys_id(struct net_device *dev, u32 data); | |
411 | static void pcnet32_led_blink_callback(struct net_device *dev); | |
412 | static int pcnet32_get_regs_len(struct net_device *dev); | |
413 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
414 | void *ptr); | |
1bcd3153 | 415 | static void pcnet32_purge_tx_ring(struct net_device *dev); |
a88c844c | 416 | static int pcnet32_alloc_ring(struct net_device *dev, char *name); |
eabf0415 HWL |
417 | static void pcnet32_free_ring(struct net_device *dev); |
418 | ||
1da177e4 LT |
419 | |
420 | enum pci_flags_bit { | |
421 | PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4, | |
422 | PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3, | |
423 | }; | |
424 | ||
425 | ||
426 | static u16 pcnet32_wio_read_csr (unsigned long addr, int index) | |
427 | { | |
428 | outw (index, addr+PCNET32_WIO_RAP); | |
429 | return inw (addr+PCNET32_WIO_RDP); | |
430 | } | |
431 | ||
432 | static void pcnet32_wio_write_csr (unsigned long addr, int index, u16 val) | |
433 | { | |
434 | outw (index, addr+PCNET32_WIO_RAP); | |
435 | outw (val, addr+PCNET32_WIO_RDP); | |
436 | } | |
437 | ||
438 | static u16 pcnet32_wio_read_bcr (unsigned long addr, int index) | |
439 | { | |
440 | outw (index, addr+PCNET32_WIO_RAP); | |
441 | return inw (addr+PCNET32_WIO_BDP); | |
442 | } | |
443 | ||
444 | static void pcnet32_wio_write_bcr (unsigned long addr, int index, u16 val) | |
445 | { | |
446 | outw (index, addr+PCNET32_WIO_RAP); | |
447 | outw (val, addr+PCNET32_WIO_BDP); | |
448 | } | |
449 | ||
450 | static u16 pcnet32_wio_read_rap (unsigned long addr) | |
451 | { | |
452 | return inw (addr+PCNET32_WIO_RAP); | |
453 | } | |
454 | ||
455 | static void pcnet32_wio_write_rap (unsigned long addr, u16 val) | |
456 | { | |
457 | outw (val, addr+PCNET32_WIO_RAP); | |
458 | } | |
459 | ||
460 | static void pcnet32_wio_reset (unsigned long addr) | |
461 | { | |
462 | inw (addr+PCNET32_WIO_RESET); | |
463 | } | |
464 | ||
465 | static int pcnet32_wio_check (unsigned long addr) | |
466 | { | |
467 | outw (88, addr+PCNET32_WIO_RAP); | |
468 | return (inw (addr+PCNET32_WIO_RAP) == 88); | |
469 | } | |
470 | ||
471 | static struct pcnet32_access pcnet32_wio = { | |
472 | .read_csr = pcnet32_wio_read_csr, | |
473 | .write_csr = pcnet32_wio_write_csr, | |
474 | .read_bcr = pcnet32_wio_read_bcr, | |
475 | .write_bcr = pcnet32_wio_write_bcr, | |
476 | .read_rap = pcnet32_wio_read_rap, | |
477 | .write_rap = pcnet32_wio_write_rap, | |
478 | .reset = pcnet32_wio_reset | |
479 | }; | |
480 | ||
481 | static u16 pcnet32_dwio_read_csr (unsigned long addr, int index) | |
482 | { | |
483 | outl (index, addr+PCNET32_DWIO_RAP); | |
484 | return (inl (addr+PCNET32_DWIO_RDP) & 0xffff); | |
485 | } | |
486 | ||
487 | static void pcnet32_dwio_write_csr (unsigned long addr, int index, u16 val) | |
488 | { | |
489 | outl (index, addr+PCNET32_DWIO_RAP); | |
490 | outl (val, addr+PCNET32_DWIO_RDP); | |
491 | } | |
492 | ||
493 | static u16 pcnet32_dwio_read_bcr (unsigned long addr, int index) | |
494 | { | |
495 | outl (index, addr+PCNET32_DWIO_RAP); | |
496 | return (inl (addr+PCNET32_DWIO_BDP) & 0xffff); | |
497 | } | |
498 | ||
499 | static void pcnet32_dwio_write_bcr (unsigned long addr, int index, u16 val) | |
500 | { | |
501 | outl (index, addr+PCNET32_DWIO_RAP); | |
502 | outl (val, addr+PCNET32_DWIO_BDP); | |
503 | } | |
504 | ||
505 | static u16 pcnet32_dwio_read_rap (unsigned long addr) | |
506 | { | |
507 | return (inl (addr+PCNET32_DWIO_RAP) & 0xffff); | |
508 | } | |
509 | ||
510 | static void pcnet32_dwio_write_rap (unsigned long addr, u16 val) | |
511 | { | |
512 | outl (val, addr+PCNET32_DWIO_RAP); | |
513 | } | |
514 | ||
515 | static void pcnet32_dwio_reset (unsigned long addr) | |
516 | { | |
517 | inl (addr+PCNET32_DWIO_RESET); | |
518 | } | |
519 | ||
520 | static int pcnet32_dwio_check (unsigned long addr) | |
521 | { | |
522 | outl (88, addr+PCNET32_DWIO_RAP); | |
523 | return ((inl (addr+PCNET32_DWIO_RAP) & 0xffff) == 88); | |
524 | } | |
525 | ||
526 | static struct pcnet32_access pcnet32_dwio = { | |
527 | .read_csr = pcnet32_dwio_read_csr, | |
528 | .write_csr = pcnet32_dwio_write_csr, | |
529 | .read_bcr = pcnet32_dwio_read_bcr, | |
530 | .write_bcr = pcnet32_dwio_write_bcr, | |
531 | .read_rap = pcnet32_dwio_read_rap, | |
532 | .write_rap = pcnet32_dwio_write_rap, | |
533 | .reset = pcnet32_dwio_reset | |
534 | }; | |
535 | ||
536 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
537 | static void pcnet32_poll_controller(struct net_device *dev) | |
538 | { | |
539 | disable_irq(dev->irq); | |
540 | pcnet32_interrupt(0, dev, NULL); | |
541 | enable_irq(dev->irq); | |
542 | } | |
543 | #endif | |
544 | ||
545 | ||
546 | static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
547 | { | |
548 | struct pcnet32_private *lp = dev->priv; | |
549 | unsigned long flags; | |
550 | int r = -EOPNOTSUPP; | |
551 | ||
552 | if (lp->mii) { | |
553 | spin_lock_irqsave(&lp->lock, flags); | |
554 | mii_ethtool_gset(&lp->mii_if, cmd); | |
555 | spin_unlock_irqrestore(&lp->lock, flags); | |
556 | r = 0; | |
557 | } | |
558 | return r; | |
559 | } | |
560 | ||
561 | static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
562 | { | |
563 | struct pcnet32_private *lp = dev->priv; | |
564 | unsigned long flags; | |
565 | int r = -EOPNOTSUPP; | |
566 | ||
567 | if (lp->mii) { | |
568 | spin_lock_irqsave(&lp->lock, flags); | |
569 | r = mii_ethtool_sset(&lp->mii_if, cmd); | |
570 | spin_unlock_irqrestore(&lp->lock, flags); | |
571 | } | |
572 | return r; | |
573 | } | |
574 | ||
575 | static void pcnet32_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
576 | { | |
577 | struct pcnet32_private *lp = dev->priv; | |
578 | ||
579 | strcpy (info->driver, DRV_NAME); | |
580 | strcpy (info->version, DRV_VERSION); | |
581 | if (lp->pci_dev) | |
582 | strcpy (info->bus_info, pci_name(lp->pci_dev)); | |
583 | else | |
584 | sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr); | |
585 | } | |
586 | ||
587 | static u32 pcnet32_get_link(struct net_device *dev) | |
588 | { | |
589 | struct pcnet32_private *lp = dev->priv; | |
590 | unsigned long flags; | |
591 | int r; | |
592 | ||
593 | spin_lock_irqsave(&lp->lock, flags); | |
594 | if (lp->mii) { | |
595 | r = mii_link_ok(&lp->mii_if); | |
596 | } else { | |
597 | ulong ioaddr = dev->base_addr; /* card base I/O address */ | |
598 | r = (lp->a.read_bcr(ioaddr, 4) != 0xc0); | |
599 | } | |
600 | spin_unlock_irqrestore(&lp->lock, flags); | |
601 | ||
602 | return r; | |
603 | } | |
604 | ||
605 | static u32 pcnet32_get_msglevel(struct net_device *dev) | |
606 | { | |
607 | struct pcnet32_private *lp = dev->priv; | |
608 | return lp->msg_enable; | |
609 | } | |
610 | ||
611 | static void pcnet32_set_msglevel(struct net_device *dev, u32 value) | |
612 | { | |
613 | struct pcnet32_private *lp = dev->priv; | |
614 | lp->msg_enable = value; | |
615 | } | |
616 | ||
617 | static int pcnet32_nway_reset(struct net_device *dev) | |
618 | { | |
619 | struct pcnet32_private *lp = dev->priv; | |
620 | unsigned long flags; | |
621 | int r = -EOPNOTSUPP; | |
622 | ||
623 | if (lp->mii) { | |
624 | spin_lock_irqsave(&lp->lock, flags); | |
625 | r = mii_nway_restart(&lp->mii_if); | |
626 | spin_unlock_irqrestore(&lp->lock, flags); | |
627 | } | |
628 | return r; | |
629 | } | |
630 | ||
631 | static void pcnet32_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
632 | { | |
633 | struct pcnet32_private *lp = dev->priv; | |
634 | ||
eabf0415 HWL |
635 | ering->tx_max_pending = TX_MAX_RING_SIZE - 1; |
636 | ering->tx_pending = lp->tx_ring_size - 1; | |
637 | ering->rx_max_pending = RX_MAX_RING_SIZE - 1; | |
638 | ering->rx_pending = lp->rx_ring_size - 1; | |
639 | } | |
640 | ||
641 | static int pcnet32_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | |
642 | { | |
643 | struct pcnet32_private *lp = dev->priv; | |
644 | unsigned long flags; | |
645 | int i; | |
646 | ||
647 | if (ering->rx_mini_pending || ering->rx_jumbo_pending) | |
648 | return -EINVAL; | |
649 | ||
650 | if (netif_running(dev)) | |
651 | pcnet32_close(dev); | |
652 | ||
653 | spin_lock_irqsave(&lp->lock, flags); | |
654 | pcnet32_free_ring(dev); | |
655 | lp->tx_ring_size = min(ering->tx_pending, (unsigned int) TX_MAX_RING_SIZE); | |
656 | lp->rx_ring_size = min(ering->rx_pending, (unsigned int) RX_MAX_RING_SIZE); | |
657 | ||
76209926 HWL |
658 | /* set the minimum ring size to 4, to allow the loopback test to work |
659 | * unchanged. | |
660 | */ | |
661 | for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { | |
eabf0415 HWL |
662 | if (lp->tx_ring_size <= (1 << i)) |
663 | break; | |
664 | } | |
665 | lp->tx_ring_size = (1 << i); | |
666 | lp->tx_mod_mask = lp->tx_ring_size - 1; | |
667 | lp->tx_len_bits = (i << 12); | |
668 | ||
76209926 | 669 | for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { |
eabf0415 HWL |
670 | if (lp->rx_ring_size <= (1 << i)) |
671 | break; | |
672 | } | |
673 | lp->rx_ring_size = (1 << i); | |
674 | lp->rx_mod_mask = lp->rx_ring_size - 1; | |
675 | lp->rx_len_bits = (i << 4); | |
676 | ||
a88c844c | 677 | if (pcnet32_alloc_ring(dev, dev->name)) { |
eabf0415 | 678 | pcnet32_free_ring(dev); |
a88c844c | 679 | spin_unlock_irqrestore(&lp->lock, flags); |
eabf0415 HWL |
680 | return -ENOMEM; |
681 | } | |
682 | ||
683 | spin_unlock_irqrestore(&lp->lock, flags); | |
684 | ||
685 | if (pcnet32_debug & NETIF_MSG_DRV) | |
a88c844c DF |
686 | printk(KERN_INFO PFX "%s: Ring Param Settings: RX: %d, TX: %d\n", |
687 | dev->name, lp->rx_ring_size, lp->tx_ring_size); | |
eabf0415 HWL |
688 | |
689 | if (netif_running(dev)) | |
690 | pcnet32_open(dev); | |
691 | ||
692 | return 0; | |
1da177e4 LT |
693 | } |
694 | ||
695 | static void pcnet32_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
696 | { | |
697 | memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); | |
698 | } | |
699 | ||
700 | static int pcnet32_self_test_count(struct net_device *dev) | |
701 | { | |
702 | return PCNET32_TEST_LEN; | |
703 | } | |
704 | ||
705 | static void pcnet32_ethtool_test(struct net_device *dev, | |
706 | struct ethtool_test *test, u64 *data) | |
707 | { | |
708 | struct pcnet32_private *lp = dev->priv; | |
709 | int rc; | |
710 | ||
711 | if (test->flags == ETH_TEST_FL_OFFLINE) { | |
712 | rc = pcnet32_loopback_test(dev, data); | |
713 | if (rc) { | |
714 | if (netif_msg_hw(lp)) | |
715 | printk(KERN_DEBUG "%s: Loopback test failed.\n", dev->name); | |
716 | test->flags |= ETH_TEST_FL_FAILED; | |
717 | } else if (netif_msg_hw(lp)) | |
718 | printk(KERN_DEBUG "%s: Loopback test passed.\n", dev->name); | |
719 | } else if (netif_msg_hw(lp)) | |
720 | printk(KERN_DEBUG "%s: No tests to run (specify 'Offline' on ethtool).", dev->name); | |
721 | } /* end pcnet32_ethtool_test */ | |
722 | ||
723 | static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1) | |
724 | { | |
725 | struct pcnet32_private *lp = dev->priv; | |
726 | struct pcnet32_access *a = &lp->a; /* access to registers */ | |
727 | ulong ioaddr = dev->base_addr; /* card base I/O address */ | |
728 | struct sk_buff *skb; /* sk buff */ | |
729 | int x, i; /* counters */ | |
730 | int numbuffs = 4; /* number of TX/RX buffers and descs */ | |
731 | u16 status = 0x8300; /* TX ring status */ | |
732 | u16 teststatus; /* test of ring status */ | |
733 | int rc; /* return code */ | |
734 | int size; /* size of packets */ | |
735 | unsigned char *packet; /* source packet data */ | |
736 | static int data_len = 60; /* length of source packets */ | |
737 | unsigned long flags; | |
738 | unsigned long ticks; | |
739 | ||
740 | *data1 = 1; /* status of test, default to fail */ | |
741 | rc = 1; /* default to fail */ | |
742 | ||
743 | if (netif_running(dev)) | |
744 | pcnet32_close(dev); | |
745 | ||
746 | spin_lock_irqsave(&lp->lock, flags); | |
747 | ||
748 | /* Reset the PCNET32 */ | |
749 | lp->a.reset (ioaddr); | |
750 | ||
751 | /* switch pcnet32 to 32bit mode */ | |
752 | lp->a.write_bcr (ioaddr, 20, 2); | |
753 | ||
754 | lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); | |
755 | lp->init_block.filter[0] = 0; | |
756 | lp->init_block.filter[1] = 0; | |
757 | ||
758 | /* purge & init rings but don't actually restart */ | |
759 | pcnet32_restart(dev, 0x0000); | |
760 | ||
761 | lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */ | |
762 | ||
763 | /* Initialize Transmit buffers. */ | |
764 | size = data_len + 15; | |
765 | for (x=0; x<numbuffs; x++) { | |
766 | if (!(skb = dev_alloc_skb(size))) { | |
767 | if (netif_msg_hw(lp)) | |
768 | printk(KERN_DEBUG "%s: Cannot allocate skb at line: %d!\n", | |
769 | dev->name, __LINE__); | |
770 | goto clean_up; | |
771 | } else { | |
772 | packet = skb->data; | |
773 | skb_put(skb, size); /* create space for data */ | |
774 | lp->tx_skbuff[x] = skb; | |
775 | lp->tx_ring[x].length = le16_to_cpu(-skb->len); | |
776 | lp->tx_ring[x].misc = 0; | |
777 | ||
778 | /* put DA and SA into the skb */ | |
779 | for (i=0; i<6; i++) | |
780 | *packet++ = dev->dev_addr[i]; | |
781 | for (i=0; i<6; i++) | |
782 | *packet++ = dev->dev_addr[i]; | |
783 | /* type */ | |
784 | *packet++ = 0x08; | |
785 | *packet++ = 0x06; | |
786 | /* packet number */ | |
787 | *packet++ = x; | |
788 | /* fill packet with data */ | |
789 | for (i=0; i<data_len; i++) | |
790 | *packet++ = i; | |
791 | ||
792 | lp->tx_dma_addr[x] = pci_map_single(lp->pci_dev, skb->data, | |
793 | skb->len, PCI_DMA_TODEVICE); | |
794 | lp->tx_ring[x].base = (u32)le32_to_cpu(lp->tx_dma_addr[x]); | |
795 | wmb(); /* Make sure owner changes after all others are visible */ | |
796 | lp->tx_ring[x].status = le16_to_cpu(status); | |
797 | } | |
798 | } | |
799 | ||
800 | x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */ | |
801 | x = x | 0x0002; | |
802 | a->write_bcr(ioaddr, 32, x); | |
803 | ||
804 | lp->a.write_csr (ioaddr, 15, 0x0044); /* set int loopback in CSR15 */ | |
805 | ||
806 | teststatus = le16_to_cpu(0x8000); | |
807 | lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */ | |
808 | ||
809 | /* Check status of descriptors */ | |
810 | for (x=0; x<numbuffs; x++) { | |
811 | ticks = 0; | |
812 | rmb(); | |
813 | while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { | |
814 | spin_unlock_irqrestore(&lp->lock, flags); | |
815 | mdelay(1); | |
816 | spin_lock_irqsave(&lp->lock, flags); | |
817 | rmb(); | |
818 | ticks++; | |
819 | } | |
820 | if (ticks == 200) { | |
821 | if (netif_msg_hw(lp)) | |
822 | printk("%s: Desc %d failed to reset!\n",dev->name,x); | |
823 | break; | |
824 | } | |
825 | } | |
826 | ||
827 | lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */ | |
828 | wmb(); | |
829 | if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { | |
830 | printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name); | |
831 | ||
832 | for (x=0; x<numbuffs; x++) { | |
833 | printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x); | |
834 | skb = lp->rx_skbuff[x]; | |
835 | for (i=0; i<size; i++) { | |
836 | printk("%02x ", *(skb->data+i)); | |
837 | } | |
838 | printk("\n"); | |
839 | } | |
840 | } | |
841 | ||
842 | x = 0; | |
843 | rc = 0; | |
844 | while (x<numbuffs && !rc) { | |
845 | skb = lp->rx_skbuff[x]; | |
846 | packet = lp->tx_skbuff[x]->data; | |
847 | for (i=0; i<size; i++) { | |
848 | if (*(skb->data+i) != packet[i]) { | |
849 | if (netif_msg_hw(lp)) | |
850 | printk(KERN_DEBUG "%s: Error in compare! %2x - %02x %02x\n", | |
851 | dev->name, i, *(skb->data+i), packet[i]); | |
852 | rc = 1; | |
853 | break; | |
854 | } | |
855 | } | |
856 | x++; | |
857 | } | |
858 | if (!rc) { | |
859 | *data1 = 0; | |
860 | } | |
861 | ||
862 | clean_up: | |
1bcd3153 | 863 | pcnet32_purge_tx_ring(dev); |
1da177e4 LT |
864 | x = a->read_csr(ioaddr, 15) & 0xFFFF; |
865 | a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */ | |
866 | ||
867 | x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ | |
868 | x = x & ~0x0002; | |
869 | a->write_bcr(ioaddr, 32, x); | |
870 | ||
871 | spin_unlock_irqrestore(&lp->lock, flags); | |
872 | ||
873 | if (netif_running(dev)) { | |
874 | pcnet32_open(dev); | |
875 | } else { | |
876 | lp->a.write_bcr (ioaddr, 20, 4); /* return to 16bit mode */ | |
877 | } | |
878 | ||
879 | return(rc); | |
880 | } /* end pcnet32_loopback_test */ | |
881 | ||
882 | static void pcnet32_led_blink_callback(struct net_device *dev) | |
883 | { | |
884 | struct pcnet32_private *lp = dev->priv; | |
885 | struct pcnet32_access *a = &lp->a; | |
886 | ulong ioaddr = dev->base_addr; | |
887 | unsigned long flags; | |
888 | int i; | |
889 | ||
890 | spin_lock_irqsave(&lp->lock, flags); | |
891 | for (i=4; i<8; i++) { | |
892 | a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); | |
893 | } | |
894 | spin_unlock_irqrestore(&lp->lock, flags); | |
895 | ||
896 | mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT); | |
897 | } | |
898 | ||
899 | static int pcnet32_phys_id(struct net_device *dev, u32 data) | |
900 | { | |
901 | struct pcnet32_private *lp = dev->priv; | |
902 | struct pcnet32_access *a = &lp->a; | |
903 | ulong ioaddr = dev->base_addr; | |
904 | unsigned long flags; | |
905 | int i, regs[4]; | |
906 | ||
907 | if (!lp->blink_timer.function) { | |
908 | init_timer(&lp->blink_timer); | |
909 | lp->blink_timer.function = (void *) pcnet32_led_blink_callback; | |
910 | lp->blink_timer.data = (unsigned long) dev; | |
911 | } | |
912 | ||
913 | /* Save the current value of the bcrs */ | |
914 | spin_lock_irqsave(&lp->lock, flags); | |
915 | for (i=4; i<8; i++) { | |
916 | regs[i-4] = a->read_bcr(ioaddr, i); | |
917 | } | |
918 | spin_unlock_irqrestore(&lp->lock, flags); | |
919 | ||
920 | mod_timer(&lp->blink_timer, jiffies); | |
921 | set_current_state(TASK_INTERRUPTIBLE); | |
922 | ||
923 | if ((!data) || (data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))) | |
924 | data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ); | |
925 | ||
f17697a3 | 926 | msleep_interruptible(data * 1000); |
1da177e4 LT |
927 | del_timer_sync(&lp->blink_timer); |
928 | ||
929 | /* Restore the original value of the bcrs */ | |
930 | spin_lock_irqsave(&lp->lock, flags); | |
931 | for (i=4; i<8; i++) { | |
932 | a->write_bcr(ioaddr, i, regs[i-4]); | |
933 | } | |
934 | spin_unlock_irqrestore(&lp->lock, flags); | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
939 | static int pcnet32_get_regs_len(struct net_device *dev) | |
940 | { | |
941 | return(PCNET32_NUM_REGS * sizeof(u16)); | |
942 | } | |
943 | ||
944 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
945 | void *ptr) | |
946 | { | |
947 | int i, csr0; | |
948 | u16 *buff = ptr; | |
949 | struct pcnet32_private *lp = dev->priv; | |
950 | struct pcnet32_access *a = &lp->a; | |
951 | ulong ioaddr = dev->base_addr; | |
952 | int ticks; | |
953 | unsigned long flags; | |
954 | ||
955 | spin_lock_irqsave(&lp->lock, flags); | |
956 | ||
957 | csr0 = a->read_csr(ioaddr, 0); | |
958 | if (!(csr0 & 0x0004)) { /* If not stopped */ | |
959 | /* set SUSPEND (SPND) - CSR5 bit 0 */ | |
960 | a->write_csr(ioaddr, 5, 0x0001); | |
961 | ||
962 | /* poll waiting for bit to be set */ | |
963 | ticks = 0; | |
964 | while (!(a->read_csr(ioaddr, 5) & 0x0001)) { | |
965 | spin_unlock_irqrestore(&lp->lock, flags); | |
966 | mdelay(1); | |
967 | spin_lock_irqsave(&lp->lock, flags); | |
968 | ticks++; | |
969 | if (ticks > 200) { | |
970 | if (netif_msg_hw(lp)) | |
971 | printk(KERN_DEBUG "%s: Error getting into suspend!\n", | |
972 | dev->name); | |
973 | break; | |
974 | } | |
975 | } | |
976 | } | |
977 | ||
978 | /* read address PROM */ | |
979 | for (i=0; i<16; i += 2) | |
980 | *buff++ = inw(ioaddr + i); | |
981 | ||
982 | /* read control and status registers */ | |
983 | for (i=0; i<90; i++) { | |
984 | *buff++ = a->read_csr(ioaddr, i); | |
985 | } | |
986 | ||
987 | *buff++ = a->read_csr(ioaddr, 112); | |
988 | *buff++ = a->read_csr(ioaddr, 114); | |
989 | ||
990 | /* read bus configuration registers */ | |
4371dc6c DF |
991 | for (i=0; i<30; i++) { |
992 | *buff++ = a->read_bcr(ioaddr, i); | |
993 | } | |
994 | *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ | |
995 | for (i=31; i<36; i++) { | |
1da177e4 LT |
996 | *buff++ = a->read_bcr(ioaddr, i); |
997 | } | |
998 | ||
999 | /* read mii phy registers */ | |
1000 | if (lp->mii) { | |
1001 | for (i=0; i<32; i++) { | |
1002 | lp->a.write_bcr(ioaddr, 33, ((lp->mii_if.phy_id) << 5) | i); | |
1003 | *buff++ = lp->a.read_bcr(ioaddr, 34); | |
1004 | } | |
1005 | } | |
1006 | ||
1007 | if (!(csr0 & 0x0004)) { /* If not stopped */ | |
1008 | /* clear SUSPEND (SPND) - CSR5 bit 0 */ | |
1009 | a->write_csr(ioaddr, 5, 0x0000); | |
1010 | } | |
1011 | ||
1012 | i = buff - (u16 *)ptr; | |
1013 | for (; i < PCNET32_NUM_REGS; i++) | |
1014 | *buff++ = 0; | |
1015 | ||
1016 | spin_unlock_irqrestore(&lp->lock, flags); | |
1017 | } | |
1018 | ||
1019 | static struct ethtool_ops pcnet32_ethtool_ops = { | |
1020 | .get_settings = pcnet32_get_settings, | |
1021 | .set_settings = pcnet32_set_settings, | |
1022 | .get_drvinfo = pcnet32_get_drvinfo, | |
1023 | .get_msglevel = pcnet32_get_msglevel, | |
1024 | .set_msglevel = pcnet32_set_msglevel, | |
1025 | .nway_reset = pcnet32_nway_reset, | |
1026 | .get_link = pcnet32_get_link, | |
1027 | .get_ringparam = pcnet32_get_ringparam, | |
eabf0415 | 1028 | .set_ringparam = pcnet32_set_ringparam, |
1da177e4 LT |
1029 | .get_tx_csum = ethtool_op_get_tx_csum, |
1030 | .get_sg = ethtool_op_get_sg, | |
1031 | .get_tso = ethtool_op_get_tso, | |
1032 | .get_strings = pcnet32_get_strings, | |
1033 | .self_test_count = pcnet32_self_test_count, | |
1034 | .self_test = pcnet32_ethtool_test, | |
1035 | .phys_id = pcnet32_phys_id, | |
1036 | .get_regs_len = pcnet32_get_regs_len, | |
1037 | .get_regs = pcnet32_get_regs, | |
db0276b0 | 1038 | .get_perm_addr = ethtool_op_get_perm_addr, |
1da177e4 LT |
1039 | }; |
1040 | ||
1041 | /* only probes for non-PCI devices, the rest are handled by | |
1042 | * pci_register_driver via pcnet32_probe_pci */ | |
1043 | ||
1044 | static void __devinit | |
1045 | pcnet32_probe_vlbus(void) | |
1046 | { | |
1047 | unsigned int *port, ioaddr; | |
1048 | ||
1049 | /* search for PCnet32 VLB cards at known addresses */ | |
1050 | for (port = pcnet32_portlist; (ioaddr = *port); port++) { | |
1051 | if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { | |
1052 | /* check if there is really a pcnet chip on that ioaddr */ | |
1053 | if ((inb(ioaddr + 14) == 0x57) && (inb(ioaddr + 15) == 0x57)) { | |
1054 | pcnet32_probe1(ioaddr, 0, NULL); | |
1055 | } else { | |
1056 | release_region(ioaddr, PCNET32_TOTAL_SIZE); | |
1057 | } | |
1058 | } | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | ||
1063 | static int __devinit | |
1064 | pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1065 | { | |
1066 | unsigned long ioaddr; | |
1067 | int err; | |
1068 | ||
1069 | err = pci_enable_device(pdev); | |
1070 | if (err < 0) { | |
1071 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1072 | printk(KERN_ERR PFX "failed to enable device -- err=%d\n", err); | |
1073 | return err; | |
1074 | } | |
1075 | pci_set_master(pdev); | |
1076 | ||
1077 | ioaddr = pci_resource_start (pdev, 0); | |
1078 | if (!ioaddr) { | |
1079 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1080 | printk (KERN_ERR PFX "card has no PCI IO resources, aborting\n"); | |
1081 | return -ENODEV; | |
1082 | } | |
1083 | ||
1084 | if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) { | |
1085 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1086 | printk(KERN_ERR PFX "architecture does not support 32bit PCI busmaster DMA\n"); | |
1087 | return -ENODEV; | |
1088 | } | |
1089 | if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") == NULL) { | |
1090 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1091 | printk(KERN_ERR PFX "io address range already allocated\n"); | |
1092 | return -EBUSY; | |
1093 | } | |
1094 | ||
1095 | err = pcnet32_probe1(ioaddr, 1, pdev); | |
1096 | if (err < 0) { | |
1097 | pci_disable_device(pdev); | |
1098 | } | |
1099 | return err; | |
1100 | } | |
1101 | ||
1102 | ||
1103 | /* pcnet32_probe1 | |
1104 | * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. | |
1105 | * pdev will be NULL when called from pcnet32_probe_vlbus. | |
1106 | */ | |
1107 | static int __devinit | |
1108 | pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) | |
1109 | { | |
1110 | struct pcnet32_private *lp; | |
1111 | dma_addr_t lp_dma_addr; | |
1112 | int i, media; | |
1113 | int fdx, mii, fset, dxsuflo; | |
1114 | int chip_version; | |
1115 | char *chipname; | |
1116 | struct net_device *dev; | |
1117 | struct pcnet32_access *a = NULL; | |
1118 | u8 promaddr[6]; | |
1119 | int ret = -ENODEV; | |
1120 | ||
1121 | /* reset the chip */ | |
1122 | pcnet32_wio_reset(ioaddr); | |
1123 | ||
1124 | /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ | |
1125 | if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { | |
1126 | a = &pcnet32_wio; | |
1127 | } else { | |
1128 | pcnet32_dwio_reset(ioaddr); | |
1129 | if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) { | |
1130 | a = &pcnet32_dwio; | |
1131 | } else | |
1132 | goto err_release_region; | |
1133 | } | |
1134 | ||
1135 | chip_version = a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr,89) << 16); | |
1136 | if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) | |
1137 | printk(KERN_INFO " PCnet chip version is %#x.\n", chip_version); | |
1138 | if ((chip_version & 0xfff) != 0x003) { | |
1139 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1140 | printk(KERN_INFO PFX "Unsupported chip version.\n"); | |
1141 | goto err_release_region; | |
1142 | } | |
1143 | ||
1144 | /* initialize variables */ | |
1145 | fdx = mii = fset = dxsuflo = 0; | |
1146 | chip_version = (chip_version >> 12) & 0xffff; | |
1147 | ||
1148 | switch (chip_version) { | |
1149 | case 0x2420: | |
1150 | chipname = "PCnet/PCI 79C970"; /* PCI */ | |
1151 | break; | |
1152 | case 0x2430: | |
1153 | if (shared) | |
1154 | chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ | |
1155 | else | |
1156 | chipname = "PCnet/32 79C965"; /* 486/VL bus */ | |
1157 | break; | |
1158 | case 0x2621: | |
1159 | chipname = "PCnet/PCI II 79C970A"; /* PCI */ | |
1160 | fdx = 1; | |
1161 | break; | |
1162 | case 0x2623: | |
1163 | chipname = "PCnet/FAST 79C971"; /* PCI */ | |
1164 | fdx = 1; mii = 1; fset = 1; | |
1165 | break; | |
1166 | case 0x2624: | |
1167 | chipname = "PCnet/FAST+ 79C972"; /* PCI */ | |
1168 | fdx = 1; mii = 1; fset = 1; | |
1169 | break; | |
1170 | case 0x2625: | |
1171 | chipname = "PCnet/FAST III 79C973"; /* PCI */ | |
1172 | fdx = 1; mii = 1; | |
1173 | break; | |
1174 | case 0x2626: | |
1175 | chipname = "PCnet/Home 79C978"; /* PCI */ | |
1176 | fdx = 1; | |
1177 | /* | |
1178 | * This is based on specs published at www.amd.com. This section | |
1179 | * assumes that a card with a 79C978 wants to go into standard | |
1180 | * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, | |
1181 | * and the module option homepna=1 can select this instead. | |
1182 | */ | |
1183 | media = a->read_bcr(ioaddr, 49); | |
1184 | media &= ~3; /* default to 10Mb ethernet */ | |
1185 | if (cards_found < MAX_UNITS && homepna[cards_found]) | |
1186 | media |= 1; /* switch to home wiring mode */ | |
1187 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1188 | printk(KERN_DEBUG PFX "media set to %sMbit mode.\n", | |
1189 | (media & 1) ? "1" : "10"); | |
1190 | a->write_bcr(ioaddr, 49, media); | |
1191 | break; | |
1192 | case 0x2627: | |
1193 | chipname = "PCnet/FAST III 79C975"; /* PCI */ | |
1194 | fdx = 1; mii = 1; | |
1195 | break; | |
1196 | case 0x2628: | |
1197 | chipname = "PCnet/PRO 79C976"; | |
1198 | fdx = 1; mii = 1; | |
1199 | break; | |
1200 | default: | |
1201 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1202 | printk(KERN_INFO PFX "PCnet version %#x, no PCnet32 chip.\n", | |
1203 | chip_version); | |
1204 | goto err_release_region; | |
1205 | } | |
1206 | ||
1207 | /* | |
1208 | * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit | |
1209 | * starting until the packet is loaded. Strike one for reliability, lose | |
1210 | * one for latency - although on PCI this isnt a big loss. Older chips | |
1211 | * have FIFO's smaller than a packet, so you can't do this. | |
1212 | * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. | |
1213 | */ | |
1214 | ||
1215 | if (fset) { | |
1216 | a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); | |
1217 | a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); | |
1218 | dxsuflo = 1; | |
1219 | } | |
1220 | ||
1221 | dev = alloc_etherdev(0); | |
1222 | if (!dev) { | |
1223 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1224 | printk(KERN_ERR PFX "Memory allocation failed.\n"); | |
1225 | ret = -ENOMEM; | |
1226 | goto err_release_region; | |
1227 | } | |
1228 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1229 | ||
1230 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1231 | printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr); | |
1232 | ||
1233 | /* In most chips, after a chip reset, the ethernet address is read from the | |
1234 | * station address PROM at the base address and programmed into the | |
1235 | * "Physical Address Registers" CSR12-14. | |
1236 | * As a precautionary measure, we read the PROM values and complain if | |
1237 | * they disagree with the CSRs. Either way, we use the CSR values, and | |
1238 | * double check that they are valid. | |
1239 | */ | |
1240 | for (i = 0; i < 3; i++) { | |
1241 | unsigned int val; | |
1242 | val = a->read_csr(ioaddr, i+12) & 0x0ffff; | |
1243 | /* There may be endianness issues here. */ | |
1244 | dev->dev_addr[2*i] = val & 0x0ff; | |
1245 | dev->dev_addr[2*i+1] = (val >> 8) & 0x0ff; | |
1246 | } | |
1247 | ||
1248 | /* read PROM address and compare with CSR address */ | |
1249 | for (i = 0; i < 6; i++) | |
1250 | promaddr[i] = inb(ioaddr + i); | |
1251 | ||
1252 | if (memcmp(promaddr, dev->dev_addr, 6) | |
1253 | || !is_valid_ether_addr(dev->dev_addr)) { | |
1da177e4 | 1254 | if (is_valid_ether_addr(promaddr)) { |
1da177e4 LT |
1255 | if (pcnet32_debug & NETIF_MSG_PROBE) { |
1256 | printk(" warning: CSR address invalid,\n"); | |
1257 | printk(KERN_INFO " using instead PROM address of"); | |
1258 | } | |
1259 | memcpy(dev->dev_addr, promaddr, 6); | |
1260 | } | |
1261 | } | |
db0276b0 | 1262 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
1263 | |
1264 | /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ | |
db0276b0 | 1265 | if (!is_valid_ether_addr(dev->perm_addr)) |
1da177e4 LT |
1266 | memset(dev->dev_addr, 0, sizeof(dev->dev_addr)); |
1267 | ||
1268 | if (pcnet32_debug & NETIF_MSG_PROBE) { | |
1269 | for (i = 0; i < 6; i++) | |
1270 | printk(" %2.2x", dev->dev_addr[i]); | |
1271 | ||
1272 | /* Version 0x2623 and 0x2624 */ | |
1273 | if (((chip_version + 1) & 0xfffe) == 0x2624) { | |
1274 | i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ | |
1275 | printk("\n" KERN_INFO " tx_start_pt(0x%04x):",i); | |
1276 | switch(i>>10) { | |
1277 | case 0: printk(" 20 bytes,"); break; | |
1278 | case 1: printk(" 64 bytes,"); break; | |
1279 | case 2: printk(" 128 bytes,"); break; | |
1280 | case 3: printk("~220 bytes,"); break; | |
1281 | } | |
1282 | i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ | |
1283 | printk(" BCR18(%x):",i&0xffff); | |
1284 | if (i & (1<<5)) printk("BurstWrEn "); | |
1285 | if (i & (1<<6)) printk("BurstRdEn "); | |
1286 | if (i & (1<<7)) printk("DWordIO "); | |
1287 | if (i & (1<<11)) printk("NoUFlow "); | |
1288 | i = a->read_bcr(ioaddr, 25); | |
1289 | printk("\n" KERN_INFO " SRAMSIZE=0x%04x,",i<<8); | |
1290 | i = a->read_bcr(ioaddr, 26); | |
1291 | printk(" SRAM_BND=0x%04x,",i<<8); | |
1292 | i = a->read_bcr(ioaddr, 27); | |
1293 | if (i & (1<<14)) printk("LowLatRx"); | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | dev->base_addr = ioaddr; | |
1298 | /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */ | |
1299 | if ((lp = pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) { | |
1300 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1301 | printk(KERN_ERR PFX "Consistent memory allocation failed.\n"); | |
1302 | ret = -ENOMEM; | |
1303 | goto err_free_netdev; | |
1304 | } | |
1305 | ||
1306 | memset(lp, 0, sizeof(*lp)); | |
1307 | lp->dma_addr = lp_dma_addr; | |
1308 | lp->pci_dev = pdev; | |
1309 | ||
1310 | spin_lock_init(&lp->lock); | |
1311 | ||
1312 | SET_MODULE_OWNER(dev); | |
1313 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1314 | dev->priv = lp; | |
1315 | lp->name = chipname; | |
1316 | lp->shared_irq = shared; | |
eabf0415 HWL |
1317 | lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ |
1318 | lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ | |
1319 | lp->tx_mod_mask = lp->tx_ring_size - 1; | |
1320 | lp->rx_mod_mask = lp->rx_ring_size - 1; | |
1321 | lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); | |
1322 | lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); | |
1da177e4 LT |
1323 | lp->mii_if.full_duplex = fdx; |
1324 | lp->mii_if.phy_id_mask = 0x1f; | |
1325 | lp->mii_if.reg_num_mask = 0x1f; | |
1326 | lp->dxsuflo = dxsuflo; | |
1327 | lp->mii = mii; | |
1328 | lp->msg_enable = pcnet32_debug; | |
1329 | if ((cards_found >= MAX_UNITS) || (options[cards_found] > sizeof(options_mapping))) | |
1330 | lp->options = PCNET32_PORT_ASEL; | |
1331 | else | |
1332 | lp->options = options_mapping[options[cards_found]]; | |
1333 | lp->mii_if.dev = dev; | |
1334 | lp->mii_if.mdio_read = mdio_read; | |
1335 | lp->mii_if.mdio_write = mdio_write; | |
1336 | ||
1337 | if (fdx && !(lp->options & PCNET32_PORT_ASEL) && | |
1338 | ((cards_found>=MAX_UNITS) || full_duplex[cards_found])) | |
1339 | lp->options |= PCNET32_PORT_FD; | |
1340 | ||
1341 | if (!a) { | |
1342 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1343 | printk(KERN_ERR PFX "No access methods\n"); | |
1344 | ret = -ENODEV; | |
1345 | goto err_free_consistent; | |
1346 | } | |
1347 | lp->a = *a; | |
1348 | ||
a88c844c DF |
1349 | /* prior to register_netdev, dev->name is not yet correct */ |
1350 | if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { | |
eabf0415 HWL |
1351 | ret = -ENOMEM; |
1352 | goto err_free_ring; | |
1353 | } | |
1da177e4 LT |
1354 | /* detect special T1/E1 WAN card by checking for MAC address */ |
1355 | if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 | |
1356 | && dev->dev_addr[2] == 0x75) | |
1357 | lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; | |
1358 | ||
1359 | lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */ | |
eabf0415 | 1360 | lp->init_block.tlen_rlen = le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits); |
1da177e4 LT |
1361 | for (i = 0; i < 6; i++) |
1362 | lp->init_block.phys_addr[i] = dev->dev_addr[i]; | |
1363 | lp->init_block.filter[0] = 0x00000000; | |
1364 | lp->init_block.filter[1] = 0x00000000; | |
eabf0415 HWL |
1365 | lp->init_block.rx_ring = (u32)le32_to_cpu(lp->rx_ring_dma_addr); |
1366 | lp->init_block.tx_ring = (u32)le32_to_cpu(lp->tx_ring_dma_addr); | |
1da177e4 LT |
1367 | |
1368 | /* switch pcnet32 to 32bit mode */ | |
1369 | a->write_bcr(ioaddr, 20, 2); | |
1370 | ||
1371 | a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, | |
1372 | init_block)) & 0xffff); | |
1373 | a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, | |
1374 | init_block)) >> 16); | |
1375 | ||
1376 | if (pdev) { /* use the IRQ provided by PCI */ | |
1377 | dev->irq = pdev->irq; | |
1378 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1379 | printk(" assigned IRQ %d.\n", dev->irq); | |
1380 | } else { | |
1381 | unsigned long irq_mask = probe_irq_on(); | |
1382 | ||
1383 | /* | |
1384 | * To auto-IRQ we enable the initialization-done and DMA error | |
1385 | * interrupts. For ISA boards we get a DMA error, but VLB and PCI | |
1386 | * boards will work. | |
1387 | */ | |
1388 | /* Trigger an initialization just for the interrupt. */ | |
1389 | a->write_csr (ioaddr, 0, 0x41); | |
1390 | mdelay (1); | |
1391 | ||
1392 | dev->irq = probe_irq_off (irq_mask); | |
1393 | if (!dev->irq) { | |
1394 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1395 | printk(", failed to detect IRQ line.\n"); | |
1396 | ret = -ENODEV; | |
eabf0415 | 1397 | goto err_free_ring; |
1da177e4 LT |
1398 | } |
1399 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1400 | printk(", probed IRQ %d.\n", dev->irq); | |
1401 | } | |
1402 | ||
1403 | /* Set the mii phy_id so that we can query the link state */ | |
1404 | if (lp->mii) | |
1405 | lp->mii_if.phy_id = ((lp->a.read_bcr (ioaddr, 33)) >> 5) & 0x1f; | |
1406 | ||
1407 | init_timer (&lp->watchdog_timer); | |
1408 | lp->watchdog_timer.data = (unsigned long) dev; | |
1409 | lp->watchdog_timer.function = (void *) &pcnet32_watchdog; | |
1410 | ||
1411 | /* The PCNET32-specific entries in the device structure. */ | |
1412 | dev->open = &pcnet32_open; | |
1413 | dev->hard_start_xmit = &pcnet32_start_xmit; | |
1414 | dev->stop = &pcnet32_close; | |
1415 | dev->get_stats = &pcnet32_get_stats; | |
1416 | dev->set_multicast_list = &pcnet32_set_multicast_list; | |
1417 | dev->do_ioctl = &pcnet32_ioctl; | |
1418 | dev->ethtool_ops = &pcnet32_ethtool_ops; | |
1419 | dev->tx_timeout = pcnet32_tx_timeout; | |
1420 | dev->watchdog_timeo = (5*HZ); | |
1421 | ||
1422 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1423 | dev->poll_controller = pcnet32_poll_controller; | |
1424 | #endif | |
1425 | ||
1426 | /* Fill in the generic fields of the device structure. */ | |
1427 | if (register_netdev(dev)) | |
eabf0415 | 1428 | goto err_free_ring; |
1da177e4 LT |
1429 | |
1430 | if (pdev) { | |
1431 | pci_set_drvdata(pdev, dev); | |
1432 | } else { | |
1433 | lp->next = pcnet32_dev; | |
1434 | pcnet32_dev = dev; | |
1435 | } | |
1436 | ||
1437 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1438 | printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name); | |
1439 | cards_found++; | |
1440 | ||
1441 | /* enable LED writes */ | |
1442 | a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); | |
1443 | ||
1444 | return 0; | |
1445 | ||
eabf0415 HWL |
1446 | err_free_ring: |
1447 | pcnet32_free_ring(dev); | |
1da177e4 LT |
1448 | err_free_consistent: |
1449 | pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr); | |
1450 | err_free_netdev: | |
1451 | free_netdev(dev); | |
1452 | err_release_region: | |
1453 | release_region(ioaddr, PCNET32_TOTAL_SIZE); | |
1454 | return ret; | |
1455 | } | |
1456 | ||
1457 | ||
a88c844c DF |
1458 | /* if any allocation fails, caller must also call pcnet32_free_ring */ |
1459 | static int pcnet32_alloc_ring(struct net_device *dev, char *name) | |
eabf0415 HWL |
1460 | { |
1461 | struct pcnet32_private *lp = dev->priv; | |
1462 | ||
a88c844c DF |
1463 | lp->tx_ring = pci_alloc_consistent(lp->pci_dev, |
1464 | sizeof(struct pcnet32_tx_head) * lp->tx_ring_size, | |
1465 | &lp->tx_ring_dma_addr); | |
1466 | if (lp->tx_ring == NULL) { | |
eabf0415 | 1467 | if (pcnet32_debug & NETIF_MSG_DRV) |
a88c844c DF |
1468 | printk("\n" KERN_ERR PFX "%s: Consistent memory allocation failed.\n", |
1469 | name); | |
eabf0415 HWL |
1470 | return -ENOMEM; |
1471 | } | |
1472 | ||
a88c844c DF |
1473 | lp->rx_ring = pci_alloc_consistent(lp->pci_dev, |
1474 | sizeof(struct pcnet32_rx_head) * lp->rx_ring_size, | |
1475 | &lp->rx_ring_dma_addr); | |
1476 | if (lp->rx_ring == NULL) { | |
eabf0415 | 1477 | if (pcnet32_debug & NETIF_MSG_DRV) |
a88c844c DF |
1478 | printk("\n" KERN_ERR PFX "%s: Consistent memory allocation failed.\n", |
1479 | name); | |
eabf0415 HWL |
1480 | return -ENOMEM; |
1481 | } | |
1482 | ||
a88c844c DF |
1483 | lp->tx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->tx_ring_size, |
1484 | GFP_ATOMIC); | |
1485 | if (!lp->tx_dma_addr) { | |
eabf0415 | 1486 | if (pcnet32_debug & NETIF_MSG_DRV) |
a88c844c | 1487 | printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name); |
eabf0415 HWL |
1488 | return -ENOMEM; |
1489 | } | |
1490 | memset(lp->tx_dma_addr, 0, sizeof(dma_addr_t) * lp->tx_ring_size); | |
1491 | ||
a88c844c DF |
1492 | lp->rx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->rx_ring_size, |
1493 | GFP_ATOMIC); | |
1494 | if (!lp->rx_dma_addr) { | |
eabf0415 | 1495 | if (pcnet32_debug & NETIF_MSG_DRV) |
a88c844c | 1496 | printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name); |
eabf0415 HWL |
1497 | return -ENOMEM; |
1498 | } | |
1499 | memset(lp->rx_dma_addr, 0, sizeof(dma_addr_t) * lp->rx_ring_size); | |
1500 | ||
a88c844c DF |
1501 | lp->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->tx_ring_size, |
1502 | GFP_ATOMIC); | |
1503 | if (!lp->tx_skbuff) { | |
eabf0415 | 1504 | if (pcnet32_debug & NETIF_MSG_DRV) |
a88c844c | 1505 | printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name); |
eabf0415 HWL |
1506 | return -ENOMEM; |
1507 | } | |
1508 | memset(lp->tx_skbuff, 0, sizeof(struct sk_buff *) * lp->tx_ring_size); | |
1509 | ||
a88c844c DF |
1510 | lp->rx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->rx_ring_size, |
1511 | GFP_ATOMIC); | |
1512 | if (!lp->rx_skbuff) { | |
eabf0415 | 1513 | if (pcnet32_debug & NETIF_MSG_DRV) |
a88c844c | 1514 | printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name); |
eabf0415 HWL |
1515 | return -ENOMEM; |
1516 | } | |
1517 | memset(lp->rx_skbuff, 0, sizeof(struct sk_buff *) * lp->rx_ring_size); | |
1518 | ||
1519 | return 0; | |
1520 | } | |
1521 | ||
1522 | ||
1523 | static void pcnet32_free_ring(struct net_device *dev) | |
1524 | { | |
1525 | struct pcnet32_private *lp = dev->priv; | |
1526 | ||
1527 | kfree(lp->tx_skbuff); | |
1528 | lp->tx_skbuff = NULL; | |
1529 | ||
1530 | kfree(lp->rx_skbuff); | |
1531 | lp->rx_skbuff = NULL; | |
1532 | ||
1533 | kfree(lp->tx_dma_addr); | |
1534 | lp->tx_dma_addr = NULL; | |
1535 | ||
1536 | kfree(lp->rx_dma_addr); | |
1537 | lp->rx_dma_addr = NULL; | |
1538 | ||
1539 | if (lp->tx_ring) { | |
1540 | pci_free_consistent(lp->pci_dev, sizeof(struct pcnet32_tx_head) * lp->tx_ring_size, | |
1541 | lp->tx_ring, lp->tx_ring_dma_addr); | |
1542 | lp->tx_ring = NULL; | |
1543 | } | |
1544 | ||
1545 | if (lp->rx_ring) { | |
1546 | pci_free_consistent(lp->pci_dev, sizeof(struct pcnet32_rx_head) * lp->rx_ring_size, | |
1547 | lp->rx_ring, lp->rx_ring_dma_addr); | |
1548 | lp->rx_ring = NULL; | |
1549 | } | |
1550 | } | |
1551 | ||
1552 | ||
1da177e4 LT |
1553 | static int |
1554 | pcnet32_open(struct net_device *dev) | |
1555 | { | |
1556 | struct pcnet32_private *lp = dev->priv; | |
1557 | unsigned long ioaddr = dev->base_addr; | |
1558 | u16 val; | |
1559 | int i; | |
1560 | int rc; | |
1561 | unsigned long flags; | |
1562 | ||
1563 | if (request_irq(dev->irq, &pcnet32_interrupt, | |
1564 | lp->shared_irq ? SA_SHIRQ : 0, dev->name, (void *)dev)) { | |
1565 | return -EAGAIN; | |
1566 | } | |
1567 | ||
1568 | spin_lock_irqsave(&lp->lock, flags); | |
1569 | /* Check for a valid station address */ | |
1570 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
1571 | rc = -EINVAL; | |
1572 | goto err_free_irq; | |
1573 | } | |
1574 | ||
1575 | /* Reset the PCNET32 */ | |
1576 | lp->a.reset (ioaddr); | |
1577 | ||
1578 | /* switch pcnet32 to 32bit mode */ | |
1579 | lp->a.write_bcr (ioaddr, 20, 2); | |
1580 | ||
1581 | if (netif_msg_ifup(lp)) | |
1582 | printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n", | |
1583 | dev->name, dev->irq, | |
eabf0415 HWL |
1584 | (u32) (lp->tx_ring_dma_addr), |
1585 | (u32) (lp->rx_ring_dma_addr), | |
1da177e4 LT |
1586 | (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block))); |
1587 | ||
1588 | /* set/reset autoselect bit */ | |
1589 | val = lp->a.read_bcr (ioaddr, 2) & ~2; | |
1590 | if (lp->options & PCNET32_PORT_ASEL) | |
1591 | val |= 2; | |
1592 | lp->a.write_bcr (ioaddr, 2, val); | |
1593 | ||
1594 | /* handle full duplex setting */ | |
1595 | if (lp->mii_if.full_duplex) { | |
1596 | val = lp->a.read_bcr (ioaddr, 9) & ~3; | |
1597 | if (lp->options & PCNET32_PORT_FD) { | |
1598 | val |= 1; | |
1599 | if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) | |
1600 | val |= 2; | |
1601 | } else if (lp->options & PCNET32_PORT_ASEL) { | |
1602 | /* workaround of xSeries250, turn on for 79C975 only */ | |
1603 | i = ((lp->a.read_csr(ioaddr, 88) | | |
1604 | (lp->a.read_csr(ioaddr,89) << 16)) >> 12) & 0xffff; | |
1605 | if (i == 0x2627) | |
1606 | val |= 3; | |
1607 | } | |
1608 | lp->a.write_bcr (ioaddr, 9, val); | |
1609 | } | |
1610 | ||
1611 | /* set/reset GPSI bit in test register */ | |
1612 | val = lp->a.read_csr (ioaddr, 124) & ~0x10; | |
1613 | if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) | |
1614 | val |= 0x10; | |
1615 | lp->a.write_csr (ioaddr, 124, val); | |
1616 | ||
2964bbd7 | 1617 | /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ |
1da177e4 | 1618 | if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT && |
2964bbd7 DF |
1619 | (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || |
1620 | lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { | |
1621 | if (lp->options & PCNET32_PORT_ASEL) { | |
1622 | lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; | |
1623 | if (netif_msg_link(lp)) | |
1624 | printk(KERN_DEBUG "%s: Setting 100Mb-Full Duplex.\n", | |
1625 | dev->name); | |
1626 | } | |
1627 | } | |
1628 | { | |
1da177e4 LT |
1629 | /* |
1630 | * 24 Jun 2004 according AMD, in order to change the PHY, | |
1631 | * DANAS (or DISPM for 79C976) must be set; then select the speed, | |
1632 | * duplex, and/or enable auto negotiation, and clear DANAS | |
1633 | */ | |
1634 | if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { | |
1635 | lp->a.write_bcr(ioaddr, 32, | |
1636 | lp->a.read_bcr(ioaddr, 32) | 0x0080); | |
1637 | /* disable Auto Negotiation, set 10Mpbs, HD */ | |
1638 | val = lp->a.read_bcr(ioaddr, 32) & ~0xb8; | |
1639 | if (lp->options & PCNET32_PORT_FD) | |
1640 | val |= 0x10; | |
1641 | if (lp->options & PCNET32_PORT_100) | |
1642 | val |= 0x08; | |
1643 | lp->a.write_bcr (ioaddr, 32, val); | |
1644 | } else { | |
1645 | if (lp->options & PCNET32_PORT_ASEL) { | |
1646 | lp->a.write_bcr(ioaddr, 32, | |
1647 | lp->a.read_bcr(ioaddr, 32) | 0x0080); | |
1648 | /* enable auto negotiate, setup, disable fd */ | |
1649 | val = lp->a.read_bcr(ioaddr, 32) & ~0x98; | |
1650 | val |= 0x20; | |
1651 | lp->a.write_bcr(ioaddr, 32, val); | |
1652 | } | |
1653 | } | |
1654 | } | |
1655 | ||
1656 | #ifdef DO_DXSUFLO | |
1657 | if (lp->dxsuflo) { /* Disable transmit stop on underflow */ | |
1658 | val = lp->a.read_csr (ioaddr, 3); | |
1659 | val |= 0x40; | |
1660 | lp->a.write_csr (ioaddr, 3, val); | |
1661 | } | |
1662 | #endif | |
1663 | ||
1664 | lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); | |
1665 | pcnet32_load_multicast(dev); | |
1666 | ||
1667 | if (pcnet32_init_ring(dev)) { | |
1668 | rc = -ENOMEM; | |
1669 | goto err_free_ring; | |
1670 | } | |
1671 | ||
1672 | /* Re-initialize the PCNET32, and start it when done. */ | |
1673 | lp->a.write_csr (ioaddr, 1, (lp->dma_addr + | |
1674 | offsetof(struct pcnet32_private, init_block)) & 0xffff); | |
1675 | lp->a.write_csr (ioaddr, 2, (lp->dma_addr + | |
1676 | offsetof(struct pcnet32_private, init_block)) >> 16); | |
1677 | ||
1678 | lp->a.write_csr (ioaddr, 4, 0x0915); | |
1679 | lp->a.write_csr (ioaddr, 0, 0x0001); | |
1680 | ||
1681 | netif_start_queue(dev); | |
1682 | ||
1683 | /* If we have mii, print the link status and start the watchdog */ | |
1684 | if (lp->mii) { | |
1685 | mii_check_media (&lp->mii_if, netif_msg_link(lp), 1); | |
1686 | mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT); | |
1687 | } | |
1688 | ||
1689 | i = 0; | |
1690 | while (i++ < 100) | |
1691 | if (lp->a.read_csr (ioaddr, 0) & 0x0100) | |
1692 | break; | |
1693 | /* | |
1694 | * We used to clear the InitDone bit, 0x0100, here but Mark Stockton | |
1695 | * reports that doing so triggers a bug in the '974. | |
1696 | */ | |
1697 | lp->a.write_csr (ioaddr, 0, 0x0042); | |
1698 | ||
1699 | if (netif_msg_ifup(lp)) | |
1700 | printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n", | |
1701 | dev->name, i, (u32) (lp->dma_addr + | |
1702 | offsetof(struct pcnet32_private, init_block)), | |
1703 | lp->a.read_csr(ioaddr, 0)); | |
1704 | ||
1705 | spin_unlock_irqrestore(&lp->lock, flags); | |
1706 | ||
1707 | return 0; /* Always succeed */ | |
1708 | ||
1709 | err_free_ring: | |
1710 | /* free any allocated skbuffs */ | |
eabf0415 | 1711 | for (i = 0; i < lp->rx_ring_size; i++) { |
1da177e4 LT |
1712 | lp->rx_ring[i].status = 0; |
1713 | if (lp->rx_skbuff[i]) { | |
1714 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2, | |
1715 | PCI_DMA_FROMDEVICE); | |
1716 | dev_kfree_skb(lp->rx_skbuff[i]); | |
1717 | } | |
1718 | lp->rx_skbuff[i] = NULL; | |
1719 | lp->rx_dma_addr[i] = 0; | |
1720 | } | |
eabf0415 HWL |
1721 | |
1722 | pcnet32_free_ring(dev); | |
1723 | ||
1da177e4 LT |
1724 | /* |
1725 | * Switch back to 16bit mode to avoid problems with dumb | |
1726 | * DOS packet driver after a warm reboot | |
1727 | */ | |
1728 | lp->a.write_bcr (ioaddr, 20, 4); | |
1729 | ||
1730 | err_free_irq: | |
1731 | spin_unlock_irqrestore(&lp->lock, flags); | |
1732 | free_irq(dev->irq, dev); | |
1733 | return rc; | |
1734 | } | |
1735 | ||
1736 | /* | |
1737 | * The LANCE has been halted for one reason or another (busmaster memory | |
1738 | * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, | |
1739 | * etc.). Modern LANCE variants always reload their ring-buffer | |
1740 | * configuration when restarted, so we must reinitialize our ring | |
1741 | * context before restarting. As part of this reinitialization, | |
1742 | * find all packets still on the Tx ring and pretend that they had been | |
1743 | * sent (in effect, drop the packets on the floor) - the higher-level | |
1744 | * protocols will time out and retransmit. It'd be better to shuffle | |
1745 | * these skbs to a temp list and then actually re-Tx them after | |
1746 | * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com | |
1747 | */ | |
1748 | ||
1749 | static void | |
1750 | pcnet32_purge_tx_ring(struct net_device *dev) | |
1751 | { | |
1752 | struct pcnet32_private *lp = dev->priv; | |
1753 | int i; | |
1754 | ||
eabf0415 | 1755 | for (i = 0; i < lp->tx_ring_size; i++) { |
1da177e4 LT |
1756 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ |
1757 | wmb(); /* Make sure adapter sees owner change */ | |
1758 | if (lp->tx_skbuff[i]) { | |
1759 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], | |
1760 | lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE); | |
1761 | dev_kfree_skb_any(lp->tx_skbuff[i]); | |
1762 | } | |
1763 | lp->tx_skbuff[i] = NULL; | |
1764 | lp->tx_dma_addr[i] = 0; | |
1765 | } | |
1766 | } | |
1767 | ||
1768 | ||
1769 | /* Initialize the PCNET32 Rx and Tx rings. */ | |
1770 | static int | |
1771 | pcnet32_init_ring(struct net_device *dev) | |
1772 | { | |
1773 | struct pcnet32_private *lp = dev->priv; | |
1774 | int i; | |
1775 | ||
1776 | lp->tx_full = 0; | |
1777 | lp->cur_rx = lp->cur_tx = 0; | |
1778 | lp->dirty_rx = lp->dirty_tx = 0; | |
1779 | ||
eabf0415 | 1780 | for (i = 0; i < lp->rx_ring_size; i++) { |
1da177e4 LT |
1781 | struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; |
1782 | if (rx_skbuff == NULL) { | |
1783 | if (!(rx_skbuff = lp->rx_skbuff[i] = dev_alloc_skb (PKT_BUF_SZ))) { | |
1784 | /* there is not much, we can do at this point */ | |
1785 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1786 | printk(KERN_ERR "%s: pcnet32_init_ring dev_alloc_skb failed.\n", | |
1787 | dev->name); | |
1788 | return -1; | |
1789 | } | |
1790 | skb_reserve (rx_skbuff, 2); | |
1791 | } | |
1792 | ||
1793 | rmb(); | |
1794 | if (lp->rx_dma_addr[i] == 0) | |
689be439 | 1795 | lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, rx_skbuff->data, |
1da177e4 LT |
1796 | PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE); |
1797 | lp->rx_ring[i].base = (u32)le32_to_cpu(lp->rx_dma_addr[i]); | |
1798 | lp->rx_ring[i].buf_length = le16_to_cpu(2-PKT_BUF_SZ); | |
1799 | wmb(); /* Make sure owner changes after all others are visible */ | |
1800 | lp->rx_ring[i].status = le16_to_cpu(0x8000); | |
1801 | } | |
1802 | /* The Tx buffer address is filled in as needed, but we do need to clear | |
1803 | * the upper ownership bit. */ | |
eabf0415 | 1804 | for (i = 0; i < lp->tx_ring_size; i++) { |
1da177e4 LT |
1805 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ |
1806 | wmb(); /* Make sure adapter sees owner change */ | |
1807 | lp->tx_ring[i].base = 0; | |
1808 | lp->tx_dma_addr[i] = 0; | |
1809 | } | |
1810 | ||
eabf0415 | 1811 | lp->init_block.tlen_rlen = le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits); |
1da177e4 LT |
1812 | for (i = 0; i < 6; i++) |
1813 | lp->init_block.phys_addr[i] = dev->dev_addr[i]; | |
eabf0415 HWL |
1814 | lp->init_block.rx_ring = (u32)le32_to_cpu(lp->rx_ring_dma_addr); |
1815 | lp->init_block.tx_ring = (u32)le32_to_cpu(lp->tx_ring_dma_addr); | |
1da177e4 LT |
1816 | wmb(); /* Make sure all changes are visible */ |
1817 | return 0; | |
1818 | } | |
1819 | ||
1820 | /* the pcnet32 has been issued a stop or reset. Wait for the stop bit | |
1821 | * then flush the pending transmit operations, re-initialize the ring, | |
1822 | * and tell the chip to initialize. | |
1823 | */ | |
1824 | static void | |
1825 | pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) | |
1826 | { | |
1827 | struct pcnet32_private *lp = dev->priv; | |
1828 | unsigned long ioaddr = dev->base_addr; | |
1829 | int i; | |
1830 | ||
1831 | /* wait for stop */ | |
1832 | for (i=0; i<100; i++) | |
1833 | if (lp->a.read_csr(ioaddr, 0) & 0x0004) | |
1834 | break; | |
1835 | ||
1836 | if (i >= 100 && netif_msg_drv(lp)) | |
1837 | printk(KERN_ERR "%s: pcnet32_restart timed out waiting for stop.\n", | |
1838 | dev->name); | |
1839 | ||
1840 | pcnet32_purge_tx_ring(dev); | |
1841 | if (pcnet32_init_ring(dev)) | |
1842 | return; | |
1843 | ||
1844 | /* ReInit Ring */ | |
1845 | lp->a.write_csr (ioaddr, 0, 1); | |
1846 | i = 0; | |
1847 | while (i++ < 1000) | |
1848 | if (lp->a.read_csr (ioaddr, 0) & 0x0100) | |
1849 | break; | |
1850 | ||
1851 | lp->a.write_csr (ioaddr, 0, csr0_bits); | |
1852 | } | |
1853 | ||
1854 | ||
1855 | static void | |
1856 | pcnet32_tx_timeout (struct net_device *dev) | |
1857 | { | |
1858 | struct pcnet32_private *lp = dev->priv; | |
1859 | unsigned long ioaddr = dev->base_addr, flags; | |
1860 | ||
1861 | spin_lock_irqsave(&lp->lock, flags); | |
1862 | /* Transmitter timeout, serious problems. */ | |
1863 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1864 | printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n", | |
1865 | dev->name, lp->a.read_csr(ioaddr, 0)); | |
1866 | lp->a.write_csr (ioaddr, 0, 0x0004); | |
1867 | lp->stats.tx_errors++; | |
1868 | if (netif_msg_tx_err(lp)) { | |
1869 | int i; | |
1870 | printk(KERN_DEBUG " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", | |
1871 | lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", | |
1872 | lp->cur_rx); | |
eabf0415 | 1873 | for (i = 0 ; i < lp->rx_ring_size; i++) |
1da177e4 LT |
1874 | printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", |
1875 | le32_to_cpu(lp->rx_ring[i].base), | |
1876 | (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 0xffff, | |
1877 | le32_to_cpu(lp->rx_ring[i].msg_length), | |
1878 | le16_to_cpu(lp->rx_ring[i].status)); | |
eabf0415 | 1879 | for (i = 0 ; i < lp->tx_ring_size; i++) |
1da177e4 LT |
1880 | printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", |
1881 | le32_to_cpu(lp->tx_ring[i].base), | |
1882 | (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, | |
1883 | le32_to_cpu(lp->tx_ring[i].misc), | |
1884 | le16_to_cpu(lp->tx_ring[i].status)); | |
1885 | printk("\n"); | |
1886 | } | |
1887 | pcnet32_restart(dev, 0x0042); | |
1888 | ||
1889 | dev->trans_start = jiffies; | |
1890 | netif_wake_queue(dev); | |
1891 | ||
1892 | spin_unlock_irqrestore(&lp->lock, flags); | |
1893 | } | |
1894 | ||
1895 | ||
1896 | static int | |
1897 | pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1898 | { | |
1899 | struct pcnet32_private *lp = dev->priv; | |
1900 | unsigned long ioaddr = dev->base_addr; | |
1901 | u16 status; | |
1902 | int entry; | |
1903 | unsigned long flags; | |
1904 | ||
1905 | spin_lock_irqsave(&lp->lock, flags); | |
1906 | ||
1907 | if (netif_msg_tx_queued(lp)) { | |
1908 | printk(KERN_DEBUG "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n", | |
1909 | dev->name, lp->a.read_csr(ioaddr, 0)); | |
1910 | } | |
1911 | ||
1912 | /* Default status -- will not enable Successful-TxDone | |
1913 | * interrupt when that option is available to us. | |
1914 | */ | |
1915 | status = 0x8300; | |
1916 | ||
1917 | /* Fill in a Tx ring entry */ | |
1918 | ||
1919 | /* Mask to ring buffer boundary. */ | |
eabf0415 | 1920 | entry = lp->cur_tx & lp->tx_mod_mask; |
1da177e4 LT |
1921 | |
1922 | /* Caution: the write order is important here, set the status | |
1923 | * with the "ownership" bits last. */ | |
1924 | ||
1925 | lp->tx_ring[entry].length = le16_to_cpu(-skb->len); | |
1926 | ||
1927 | lp->tx_ring[entry].misc = 0x00000000; | |
1928 | ||
1929 | lp->tx_skbuff[entry] = skb; | |
1930 | lp->tx_dma_addr[entry] = pci_map_single(lp->pci_dev, skb->data, skb->len, | |
1931 | PCI_DMA_TODEVICE); | |
1932 | lp->tx_ring[entry].base = (u32)le32_to_cpu(lp->tx_dma_addr[entry]); | |
1933 | wmb(); /* Make sure owner changes after all others are visible */ | |
1934 | lp->tx_ring[entry].status = le16_to_cpu(status); | |
1935 | ||
1936 | lp->cur_tx++; | |
1937 | lp->stats.tx_bytes += skb->len; | |
1938 | ||
1939 | /* Trigger an immediate send poll. */ | |
1940 | lp->a.write_csr (ioaddr, 0, 0x0048); | |
1941 | ||
1942 | dev->trans_start = jiffies; | |
1943 | ||
eabf0415 | 1944 | if (lp->tx_ring[(entry+1) & lp->tx_mod_mask].base != 0) { |
1da177e4 LT |
1945 | lp->tx_full = 1; |
1946 | netif_stop_queue(dev); | |
1947 | } | |
1948 | spin_unlock_irqrestore(&lp->lock, flags); | |
1949 | return 0; | |
1950 | } | |
1951 | ||
1952 | /* The PCNET32 interrupt handler. */ | |
1953 | static irqreturn_t | |
1954 | pcnet32_interrupt(int irq, void *dev_id, struct pt_regs * regs) | |
1955 | { | |
1956 | struct net_device *dev = dev_id; | |
1957 | struct pcnet32_private *lp; | |
1958 | unsigned long ioaddr; | |
1959 | u16 csr0,rap; | |
1960 | int boguscnt = max_interrupt_work; | |
1961 | int must_restart; | |
1962 | ||
1963 | if (!dev) { | |
1964 | if (pcnet32_debug & NETIF_MSG_INTR) | |
1965 | printk (KERN_DEBUG "%s(): irq %d for unknown device\n", | |
1966 | __FUNCTION__, irq); | |
1967 | return IRQ_NONE; | |
1968 | } | |
1969 | ||
1970 | ioaddr = dev->base_addr; | |
1971 | lp = dev->priv; | |
1972 | ||
1973 | spin_lock(&lp->lock); | |
1974 | ||
1975 | rap = lp->a.read_rap(ioaddr); | |
1976 | while ((csr0 = lp->a.read_csr (ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) { | |
1977 | if (csr0 == 0xffff) { | |
1978 | break; /* PCMCIA remove happened */ | |
1979 | } | |
1980 | /* Acknowledge all of the current interrupt sources ASAP. */ | |
1981 | lp->a.write_csr (ioaddr, 0, csr0 & ~0x004f); | |
1982 | ||
1983 | must_restart = 0; | |
1984 | ||
1985 | if (netif_msg_intr(lp)) | |
1986 | printk(KERN_DEBUG "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n", | |
1987 | dev->name, csr0, lp->a.read_csr (ioaddr, 0)); | |
1988 | ||
1989 | if (csr0 & 0x0400) /* Rx interrupt */ | |
1990 | pcnet32_rx(dev); | |
1991 | ||
1992 | if (csr0 & 0x0200) { /* Tx-done interrupt */ | |
1993 | unsigned int dirty_tx = lp->dirty_tx; | |
1994 | int delta; | |
1995 | ||
1996 | while (dirty_tx != lp->cur_tx) { | |
eabf0415 | 1997 | int entry = dirty_tx & lp->tx_mod_mask; |
1da177e4 LT |
1998 | int status = (short)le16_to_cpu(lp->tx_ring[entry].status); |
1999 | ||
2000 | if (status < 0) | |
2001 | break; /* It still hasn't been Txed */ | |
2002 | ||
2003 | lp->tx_ring[entry].base = 0; | |
2004 | ||
2005 | if (status & 0x4000) { | |
2006 | /* There was an major error, log it. */ | |
2007 | int err_status = le32_to_cpu(lp->tx_ring[entry].misc); | |
2008 | lp->stats.tx_errors++; | |
2009 | if (netif_msg_tx_err(lp)) | |
2010 | printk(KERN_ERR "%s: Tx error status=%04x err_status=%08x\n", | |
2011 | dev->name, status, err_status); | |
2012 | if (err_status & 0x04000000) lp->stats.tx_aborted_errors++; | |
2013 | if (err_status & 0x08000000) lp->stats.tx_carrier_errors++; | |
2014 | if (err_status & 0x10000000) lp->stats.tx_window_errors++; | |
2015 | #ifndef DO_DXSUFLO | |
2016 | if (err_status & 0x40000000) { | |
2017 | lp->stats.tx_fifo_errors++; | |
2018 | /* Ackk! On FIFO errors the Tx unit is turned off! */ | |
2019 | /* Remove this verbosity later! */ | |
2020 | if (netif_msg_tx_err(lp)) | |
2021 | printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n", | |
2022 | dev->name, csr0); | |
2023 | must_restart = 1; | |
2024 | } | |
2025 | #else | |
2026 | if (err_status & 0x40000000) { | |
2027 | lp->stats.tx_fifo_errors++; | |
2028 | if (! lp->dxsuflo) { /* If controller doesn't recover ... */ | |
2029 | /* Ackk! On FIFO errors the Tx unit is turned off! */ | |
2030 | /* Remove this verbosity later! */ | |
2031 | if (netif_msg_tx_err(lp)) | |
2032 | printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n", | |
2033 | dev->name, csr0); | |
2034 | must_restart = 1; | |
2035 | } | |
2036 | } | |
2037 | #endif | |
2038 | } else { | |
2039 | if (status & 0x1800) | |
2040 | lp->stats.collisions++; | |
2041 | lp->stats.tx_packets++; | |
2042 | } | |
2043 | ||
2044 | /* We must free the original skb */ | |
2045 | if (lp->tx_skbuff[entry]) { | |
2046 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[entry], | |
2047 | lp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE); | |
2048 | dev_kfree_skb_irq(lp->tx_skbuff[entry]); | |
2049 | lp->tx_skbuff[entry] = NULL; | |
2050 | lp->tx_dma_addr[entry] = 0; | |
2051 | } | |
2052 | dirty_tx++; | |
2053 | } | |
2054 | ||
eabf0415 HWL |
2055 | delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size); |
2056 | if (delta > lp->tx_ring_size) { | |
1da177e4 LT |
2057 | if (netif_msg_drv(lp)) |
2058 | printk(KERN_ERR "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n", | |
2059 | dev->name, dirty_tx, lp->cur_tx, lp->tx_full); | |
eabf0415 HWL |
2060 | dirty_tx += lp->tx_ring_size; |
2061 | delta -= lp->tx_ring_size; | |
1da177e4 LT |
2062 | } |
2063 | ||
2064 | if (lp->tx_full && | |
2065 | netif_queue_stopped(dev) && | |
eabf0415 | 2066 | delta < lp->tx_ring_size - 2) { |
1da177e4 LT |
2067 | /* The ring is no longer full, clear tbusy. */ |
2068 | lp->tx_full = 0; | |
2069 | netif_wake_queue (dev); | |
2070 | } | |
2071 | lp->dirty_tx = dirty_tx; | |
2072 | } | |
2073 | ||
2074 | /* Log misc errors. */ | |
2075 | if (csr0 & 0x4000) lp->stats.tx_errors++; /* Tx babble. */ | |
2076 | if (csr0 & 0x1000) { | |
2077 | /* | |
2078 | * this happens when our receive ring is full. This shouldn't | |
2079 | * be a problem as we will see normal rx interrupts for the frames | |
2080 | * in the receive ring. But there are some PCI chipsets (I can | |
2081 | * reproduce this on SP3G with Intel saturn chipset) which have | |
2082 | * sometimes problems and will fill up the receive ring with | |
2083 | * error descriptors. In this situation we don't get a rx | |
2084 | * interrupt, but a missed frame interrupt sooner or later. | |
2085 | * So we try to clean up our receive ring here. | |
2086 | */ | |
2087 | pcnet32_rx(dev); | |
2088 | lp->stats.rx_errors++; /* Missed a Rx frame. */ | |
2089 | } | |
2090 | if (csr0 & 0x0800) { | |
2091 | if (netif_msg_drv(lp)) | |
2092 | printk(KERN_ERR "%s: Bus master arbitration failure, status %4.4x.\n", | |
2093 | dev->name, csr0); | |
2094 | /* unlike for the lance, there is no restart needed */ | |
2095 | } | |
2096 | ||
2097 | if (must_restart) { | |
2098 | /* reset the chip to clear the error condition, then restart */ | |
2099 | lp->a.reset(ioaddr); | |
2100 | lp->a.write_csr(ioaddr, 4, 0x0915); | |
2101 | pcnet32_restart(dev, 0x0002); | |
2102 | netif_wake_queue(dev); | |
2103 | } | |
2104 | } | |
2105 | ||
2106 | /* Set interrupt enable. */ | |
2107 | lp->a.write_csr (ioaddr, 0, 0x0040); | |
2108 | lp->a.write_rap (ioaddr,rap); | |
2109 | ||
2110 | if (netif_msg_intr(lp)) | |
2111 | printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n", | |
2112 | dev->name, lp->a.read_csr (ioaddr, 0)); | |
2113 | ||
2114 | spin_unlock(&lp->lock); | |
2115 | ||
2116 | return IRQ_HANDLED; | |
2117 | } | |
2118 | ||
2119 | static int | |
2120 | pcnet32_rx(struct net_device *dev) | |
2121 | { | |
2122 | struct pcnet32_private *lp = dev->priv; | |
eabf0415 HWL |
2123 | int entry = lp->cur_rx & lp->rx_mod_mask; |
2124 | int boguscnt = lp->rx_ring_size / 2; | |
1da177e4 LT |
2125 | |
2126 | /* If we own the next entry, it's a new packet. Send it up. */ | |
2127 | while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) { | |
2128 | int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8; | |
2129 | ||
2130 | if (status != 0x03) { /* There was an error. */ | |
2131 | /* | |
2132 | * There is a tricky error noted by John Murphy, | |
2133 | * <murf@perftech.com> to Russ Nelson: Even with full-sized | |
2134 | * buffers it's possible for a jabber packet to use two | |
2135 | * buffers, with only the last correctly noting the error. | |
2136 | */ | |
2137 | if (status & 0x01) /* Only count a general error at the */ | |
2138 | lp->stats.rx_errors++; /* end of a packet.*/ | |
2139 | if (status & 0x20) lp->stats.rx_frame_errors++; | |
2140 | if (status & 0x10) lp->stats.rx_over_errors++; | |
2141 | if (status & 0x08) lp->stats.rx_crc_errors++; | |
2142 | if (status & 0x04) lp->stats.rx_fifo_errors++; | |
2143 | lp->rx_ring[entry].status &= le16_to_cpu(0x03ff); | |
2144 | } else { | |
2145 | /* Malloc up new buffer, compatible with net-2e. */ | |
2146 | short pkt_len = (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)-4; | |
2147 | struct sk_buff *skb; | |
2148 | ||
2149 | /* Discard oversize frames. */ | |
2150 | if (unlikely(pkt_len > PKT_BUF_SZ - 2)) { | |
2151 | if (netif_msg_drv(lp)) | |
2152 | printk(KERN_ERR "%s: Impossible packet size %d!\n", | |
2153 | dev->name, pkt_len); | |
2154 | lp->stats.rx_errors++; | |
2155 | } else if (pkt_len < 60) { | |
2156 | if (netif_msg_rx_err(lp)) | |
2157 | printk(KERN_ERR "%s: Runt packet!\n", dev->name); | |
2158 | lp->stats.rx_errors++; | |
2159 | } else { | |
2160 | int rx_in_place = 0; | |
2161 | ||
2162 | if (pkt_len > rx_copybreak) { | |
2163 | struct sk_buff *newskb; | |
2164 | ||
2165 | if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) { | |
2166 | skb_reserve (newskb, 2); | |
2167 | skb = lp->rx_skbuff[entry]; | |
2168 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry], | |
2169 | PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE); | |
2170 | skb_put (skb, pkt_len); | |
2171 | lp->rx_skbuff[entry] = newskb; | |
2172 | newskb->dev = dev; | |
2173 | lp->rx_dma_addr[entry] = | |
689be439 | 2174 | pci_map_single(lp->pci_dev, newskb->data, |
1da177e4 LT |
2175 | PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE); |
2176 | lp->rx_ring[entry].base = le32_to_cpu(lp->rx_dma_addr[entry]); | |
2177 | rx_in_place = 1; | |
2178 | } else | |
2179 | skb = NULL; | |
2180 | } else { | |
2181 | skb = dev_alloc_skb(pkt_len+2); | |
2182 | } | |
2183 | ||
2184 | if (skb == NULL) { | |
2185 | int i; | |
2186 | if (netif_msg_drv(lp)) | |
2187 | printk(KERN_ERR "%s: Memory squeeze, deferring packet.\n", | |
2188 | dev->name); | |
eabf0415 | 2189 | for (i = 0; i < lp->rx_ring_size; i++) |
1da177e4 | 2190 | if ((short)le16_to_cpu(lp->rx_ring[(entry+i) |
eabf0415 | 2191 | & lp->rx_mod_mask].status) < 0) |
1da177e4 LT |
2192 | break; |
2193 | ||
eabf0415 | 2194 | if (i > lp->rx_ring_size -2) { |
1da177e4 LT |
2195 | lp->stats.rx_dropped++; |
2196 | lp->rx_ring[entry].status |= le16_to_cpu(0x8000); | |
2197 | wmb(); /* Make sure adapter sees owner change */ | |
2198 | lp->cur_rx++; | |
2199 | } | |
2200 | break; | |
2201 | } | |
2202 | skb->dev = dev; | |
2203 | if (!rx_in_place) { | |
2204 | skb_reserve(skb,2); /* 16 byte align */ | |
2205 | skb_put(skb,pkt_len); /* Make room */ | |
2206 | pci_dma_sync_single_for_cpu(lp->pci_dev, | |
2207 | lp->rx_dma_addr[entry], | |
2208 | PKT_BUF_SZ-2, | |
2209 | PCI_DMA_FROMDEVICE); | |
2210 | eth_copy_and_sum(skb, | |
689be439 | 2211 | (unsigned char *)(lp->rx_skbuff[entry]->data), |
1da177e4 LT |
2212 | pkt_len,0); |
2213 | pci_dma_sync_single_for_device(lp->pci_dev, | |
2214 | lp->rx_dma_addr[entry], | |
2215 | PKT_BUF_SZ-2, | |
2216 | PCI_DMA_FROMDEVICE); | |
2217 | } | |
2218 | lp->stats.rx_bytes += skb->len; | |
2219 | skb->protocol=eth_type_trans(skb,dev); | |
2220 | netif_rx(skb); | |
2221 | dev->last_rx = jiffies; | |
2222 | lp->stats.rx_packets++; | |
2223 | } | |
2224 | } | |
2225 | /* | |
2226 | * The docs say that the buffer length isn't touched, but Andrew Boyd | |
2227 | * of QNX reports that some revs of the 79C965 clear it. | |
2228 | */ | |
2229 | lp->rx_ring[entry].buf_length = le16_to_cpu(2-PKT_BUF_SZ); | |
2230 | wmb(); /* Make sure owner changes after all others are visible */ | |
2231 | lp->rx_ring[entry].status |= le16_to_cpu(0x8000); | |
eabf0415 | 2232 | entry = (++lp->cur_rx) & lp->rx_mod_mask; |
1da177e4 LT |
2233 | if (--boguscnt <= 0) break; /* don't stay in loop forever */ |
2234 | } | |
2235 | ||
2236 | return 0; | |
2237 | } | |
2238 | ||
2239 | static int | |
2240 | pcnet32_close(struct net_device *dev) | |
2241 | { | |
2242 | unsigned long ioaddr = dev->base_addr; | |
2243 | struct pcnet32_private *lp = dev->priv; | |
2244 | int i; | |
2245 | unsigned long flags; | |
2246 | ||
2247 | del_timer_sync(&lp->watchdog_timer); | |
2248 | ||
2249 | netif_stop_queue(dev); | |
2250 | ||
2251 | spin_lock_irqsave(&lp->lock, flags); | |
2252 | ||
2253 | lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112); | |
2254 | ||
2255 | if (netif_msg_ifdown(lp)) | |
2256 | printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n", | |
2257 | dev->name, lp->a.read_csr (ioaddr, 0)); | |
2258 | ||
2259 | /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ | |
2260 | lp->a.write_csr (ioaddr, 0, 0x0004); | |
2261 | ||
2262 | /* | |
2263 | * Switch back to 16bit mode to avoid problems with dumb | |
2264 | * DOS packet driver after a warm reboot | |
2265 | */ | |
2266 | lp->a.write_bcr (ioaddr, 20, 4); | |
2267 | ||
2268 | spin_unlock_irqrestore(&lp->lock, flags); | |
2269 | ||
2270 | free_irq(dev->irq, dev); | |
2271 | ||
2272 | spin_lock_irqsave(&lp->lock, flags); | |
2273 | ||
2274 | /* free all allocated skbuffs */ | |
eabf0415 | 2275 | for (i = 0; i < lp->rx_ring_size; i++) { |
1da177e4 LT |
2276 | lp->rx_ring[i].status = 0; |
2277 | wmb(); /* Make sure adapter sees owner change */ | |
2278 | if (lp->rx_skbuff[i]) { | |
2279 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2, | |
2280 | PCI_DMA_FROMDEVICE); | |
2281 | dev_kfree_skb(lp->rx_skbuff[i]); | |
2282 | } | |
2283 | lp->rx_skbuff[i] = NULL; | |
2284 | lp->rx_dma_addr[i] = 0; | |
2285 | } | |
2286 | ||
eabf0415 | 2287 | for (i = 0; i < lp->tx_ring_size; i++) { |
1da177e4 LT |
2288 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ |
2289 | wmb(); /* Make sure adapter sees owner change */ | |
2290 | if (lp->tx_skbuff[i]) { | |
2291 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], | |
2292 | lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE); | |
2293 | dev_kfree_skb(lp->tx_skbuff[i]); | |
2294 | } | |
2295 | lp->tx_skbuff[i] = NULL; | |
2296 | lp->tx_dma_addr[i] = 0; | |
2297 | } | |
2298 | ||
2299 | spin_unlock_irqrestore(&lp->lock, flags); | |
2300 | ||
2301 | return 0; | |
2302 | } | |
2303 | ||
2304 | static struct net_device_stats * | |
2305 | pcnet32_get_stats(struct net_device *dev) | |
2306 | { | |
2307 | struct pcnet32_private *lp = dev->priv; | |
2308 | unsigned long ioaddr = dev->base_addr; | |
2309 | u16 saved_addr; | |
2310 | unsigned long flags; | |
2311 | ||
2312 | spin_lock_irqsave(&lp->lock, flags); | |
2313 | saved_addr = lp->a.read_rap(ioaddr); | |
2314 | lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112); | |
2315 | lp->a.write_rap(ioaddr, saved_addr); | |
2316 | spin_unlock_irqrestore(&lp->lock, flags); | |
2317 | ||
2318 | return &lp->stats; | |
2319 | } | |
2320 | ||
2321 | /* taken from the sunlance driver, which it took from the depca driver */ | |
2322 | static void pcnet32_load_multicast (struct net_device *dev) | |
2323 | { | |
2324 | struct pcnet32_private *lp = dev->priv; | |
2325 | volatile struct pcnet32_init_block *ib = &lp->init_block; | |
2326 | volatile u16 *mcast_table = (u16 *)&ib->filter; | |
2327 | struct dev_mc_list *dmi=dev->mc_list; | |
2328 | char *addrs; | |
2329 | int i; | |
2330 | u32 crc; | |
2331 | ||
2332 | /* set all multicast bits */ | |
2333 | if (dev->flags & IFF_ALLMULTI) { | |
2334 | ib->filter[0] = 0xffffffff; | |
2335 | ib->filter[1] = 0xffffffff; | |
2336 | return; | |
2337 | } | |
2338 | /* clear the multicast filter */ | |
2339 | ib->filter[0] = 0; | |
2340 | ib->filter[1] = 0; | |
2341 | ||
2342 | /* Add addresses */ | |
2343 | for (i = 0; i < dev->mc_count; i++) { | |
2344 | addrs = dmi->dmi_addr; | |
2345 | dmi = dmi->next; | |
2346 | ||
2347 | /* multicast address? */ | |
2348 | if (!(*addrs & 1)) | |
2349 | continue; | |
2350 | ||
2351 | crc = ether_crc_le(6, addrs); | |
2352 | crc = crc >> 26; | |
2353 | mcast_table [crc >> 4] = le16_to_cpu( | |
2354 | le16_to_cpu(mcast_table [crc >> 4]) | (1 << (crc & 0xf))); | |
2355 | } | |
2356 | return; | |
2357 | } | |
2358 | ||
2359 | ||
2360 | /* | |
2361 | * Set or clear the multicast filter for this adaptor. | |
2362 | */ | |
2363 | static void pcnet32_set_multicast_list(struct net_device *dev) | |
2364 | { | |
2365 | unsigned long ioaddr = dev->base_addr, flags; | |
2366 | struct pcnet32_private *lp = dev->priv; | |
2367 | ||
2368 | spin_lock_irqsave(&lp->lock, flags); | |
2369 | if (dev->flags&IFF_PROMISC) { | |
2370 | /* Log any net taps. */ | |
2371 | if (netif_msg_hw(lp)) | |
2372 | printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name); | |
2373 | lp->init_block.mode = le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 7); | |
2374 | } else { | |
2375 | lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); | |
2376 | pcnet32_load_multicast (dev); | |
2377 | } | |
2378 | ||
2379 | lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */ | |
2380 | pcnet32_restart(dev, 0x0042); /* Resume normal operation */ | |
2381 | netif_wake_queue(dev); | |
2382 | ||
2383 | spin_unlock_irqrestore(&lp->lock, flags); | |
2384 | } | |
2385 | ||
2386 | /* This routine assumes that the lp->lock is held */ | |
2387 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num) | |
2388 | { | |
2389 | struct pcnet32_private *lp = dev->priv; | |
2390 | unsigned long ioaddr = dev->base_addr; | |
2391 | u16 val_out; | |
2392 | ||
2393 | if (!lp->mii) | |
2394 | return 0; | |
2395 | ||
2396 | lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); | |
2397 | val_out = lp->a.read_bcr(ioaddr, 34); | |
2398 | ||
2399 | return val_out; | |
2400 | } | |
2401 | ||
2402 | /* This routine assumes that the lp->lock is held */ | |
2403 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) | |
2404 | { | |
2405 | struct pcnet32_private *lp = dev->priv; | |
2406 | unsigned long ioaddr = dev->base_addr; | |
2407 | ||
2408 | if (!lp->mii) | |
2409 | return; | |
2410 | ||
2411 | lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); | |
2412 | lp->a.write_bcr(ioaddr, 34, val); | |
2413 | } | |
2414 | ||
2415 | static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2416 | { | |
2417 | struct pcnet32_private *lp = dev->priv; | |
2418 | int rc; | |
2419 | unsigned long flags; | |
2420 | ||
2421 | /* SIOC[GS]MIIxxx ioctls */ | |
2422 | if (lp->mii) { | |
2423 | spin_lock_irqsave(&lp->lock, flags); | |
2424 | rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); | |
2425 | spin_unlock_irqrestore(&lp->lock, flags); | |
2426 | } else { | |
2427 | rc = -EOPNOTSUPP; | |
2428 | } | |
2429 | ||
2430 | return rc; | |
2431 | } | |
2432 | ||
2433 | static void pcnet32_watchdog(struct net_device *dev) | |
2434 | { | |
2435 | struct pcnet32_private *lp = dev->priv; | |
2436 | unsigned long flags; | |
2437 | ||
2438 | /* Print the link status if it has changed */ | |
2439 | if (lp->mii) { | |
2440 | spin_lock_irqsave(&lp->lock, flags); | |
2441 | mii_check_media (&lp->mii_if, netif_msg_link(lp), 0); | |
2442 | spin_unlock_irqrestore(&lp->lock, flags); | |
2443 | } | |
2444 | ||
2445 | mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT); | |
2446 | } | |
2447 | ||
2448 | static void __devexit pcnet32_remove_one(struct pci_dev *pdev) | |
2449 | { | |
2450 | struct net_device *dev = pci_get_drvdata(pdev); | |
2451 | ||
2452 | if (dev) { | |
2453 | struct pcnet32_private *lp = dev->priv; | |
2454 | ||
2455 | unregister_netdev(dev); | |
eabf0415 | 2456 | pcnet32_free_ring(dev); |
1da177e4 LT |
2457 | release_region(dev->base_addr, PCNET32_TOTAL_SIZE); |
2458 | pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr); | |
2459 | free_netdev(dev); | |
2460 | pci_disable_device(pdev); | |
2461 | pci_set_drvdata(pdev, NULL); | |
2462 | } | |
2463 | } | |
2464 | ||
2465 | static struct pci_driver pcnet32_driver = { | |
2466 | .name = DRV_NAME, | |
2467 | .probe = pcnet32_probe_pci, | |
2468 | .remove = __devexit_p(pcnet32_remove_one), | |
2469 | .id_table = pcnet32_pci_tbl, | |
2470 | }; | |
2471 | ||
2472 | /* An additional parameter that may be passed in... */ | |
2473 | static int debug = -1; | |
2474 | static int tx_start_pt = -1; | |
2475 | static int pcnet32_have_pci; | |
2476 | ||
2477 | module_param(debug, int, 0); | |
2478 | MODULE_PARM_DESC(debug, DRV_NAME " debug level"); | |
2479 | module_param(max_interrupt_work, int, 0); | |
2480 | MODULE_PARM_DESC(max_interrupt_work, DRV_NAME " maximum events handled per interrupt"); | |
2481 | module_param(rx_copybreak, int, 0); | |
2482 | MODULE_PARM_DESC(rx_copybreak, DRV_NAME " copy breakpoint for copy-only-tiny-frames"); | |
2483 | module_param(tx_start_pt, int, 0); | |
2484 | MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); | |
2485 | module_param(pcnet32vlb, int, 0); | |
2486 | MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); | |
2487 | module_param_array(options, int, NULL, 0); | |
2488 | MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); | |
2489 | module_param_array(full_duplex, int, NULL, 0); | |
2490 | MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); | |
2491 | /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ | |
2492 | module_param_array(homepna, int, NULL, 0); | |
2493 | MODULE_PARM_DESC(homepna, DRV_NAME " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); | |
2494 | ||
2495 | MODULE_AUTHOR("Thomas Bogendoerfer"); | |
2496 | MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); | |
2497 | MODULE_LICENSE("GPL"); | |
2498 | ||
2499 | #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) | |
2500 | ||
2501 | static int __init pcnet32_init_module(void) | |
2502 | { | |
2503 | printk(KERN_INFO "%s", version); | |
2504 | ||
2505 | pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); | |
2506 | ||
2507 | if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) | |
2508 | tx_start = tx_start_pt; | |
2509 | ||
2510 | /* find the PCI devices */ | |
2511 | if (!pci_module_init(&pcnet32_driver)) | |
2512 | pcnet32_have_pci = 1; | |
2513 | ||
2514 | /* should we find any remaining VLbus devices ? */ | |
2515 | if (pcnet32vlb) | |
2516 | pcnet32_probe_vlbus(); | |
2517 | ||
2518 | if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) | |
2519 | printk(KERN_INFO PFX "%d cards_found.\n", cards_found); | |
2520 | ||
2521 | return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; | |
2522 | } | |
2523 | ||
2524 | static void __exit pcnet32_cleanup_module(void) | |
2525 | { | |
2526 | struct net_device *next_dev; | |
2527 | ||
2528 | while (pcnet32_dev) { | |
2529 | struct pcnet32_private *lp = pcnet32_dev->priv; | |
2530 | next_dev = lp->next; | |
2531 | unregister_netdev(pcnet32_dev); | |
eabf0415 | 2532 | pcnet32_free_ring(pcnet32_dev); |
1da177e4 LT |
2533 | release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); |
2534 | pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr); | |
2535 | free_netdev(pcnet32_dev); | |
2536 | pcnet32_dev = next_dev; | |
2537 | } | |
2538 | ||
2539 | if (pcnet32_have_pci) | |
2540 | pci_unregister_driver(&pcnet32_driver); | |
2541 | } | |
2542 | ||
2543 | module_init(pcnet32_init_module); | |
2544 | module_exit(pcnet32_cleanup_module); | |
2545 | ||
2546 | /* | |
2547 | * Local variables: | |
2548 | * c-indent-level: 4 | |
2549 | * tab-width: 8 | |
2550 | * End: | |
2551 | */ |