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support for USB autosuspend in the asix driver
[mirror_ubuntu-artful-kernel.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24#define DRV_NAME "pcnet32"
7de745e5
DF		 25#ifdef CONFIG_PCNET32_NAPI
26#define DRV_VERSION "1.33-NAPI"
27#else
28#define DRV_VERSION "1.33"
29#endif
30#define DRV_RELDATE "27.Jun.2006"
1da177e4
LT		 31#define PFX DRV_NAME ": "
32
4a5e8e29
JG		 33static const char *const version =
34 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/string.h>
39#include <linux/errno.h>
40#include <linux/ioport.h>
41#include <linux/slab.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/delay.h>
45#include <linux/init.h>
46#include <linux/ethtool.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/netdevice.h>
50#include <linux/etherdevice.h>
51#include <linux/skbuff.h>
52#include <linux/spinlock.h>
53#include <linux/moduleparam.h>
54#include <linux/bitops.h>
55
56#include <asm/dma.h>
57#include <asm/io.h>
58#include <asm/uaccess.h>
59#include <asm/irq.h>
60
61/*
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
63 */
64static struct pci_device_id pcnet32_pci_tbl[] = {
f2622a2b
DF		 65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 67
68 /*
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
71 */
f2622a2b
DF		 72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 74
75 { } /* terminate list */
1da177e4
LT		 76};
77
4a5e8e29 78MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 79
80static int cards_found;
81
82/*
83 * VLB I/O addresses
84 */
85static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 86 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4
LT		 87
88static int pcnet32_debug = 0;
4a5e8e29
JG		 89static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 91
92static struct net_device *pcnet32_dev;
93
94static int max_interrupt_work = 2;
95static int rx_copybreak = 200;
96
97#define PCNET32_PORT_AUI 0x00
98#define PCNET32_PORT_10BT 0x01
99#define PCNET32_PORT_GPSI 0x02
100#define PCNET32_PORT_MII 0x03
101
102#define PCNET32_PORT_PORTSEL 0x03
103#define PCNET32_PORT_ASEL 0x04
104#define PCNET32_PORT_100 0x40
105#define PCNET32_PORT_FD 0x80
106
107#define PCNET32_DMA_MASK 0xffffffff
108
109#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
111
112/*
113 * table to translate option values from tulip
114 * to internal options
115 */
f71e1309 116static const unsigned char options_mapping[] = {
4a5e8e29
JG		 117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 134};
135
136static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 137 "Loopback test (offline)"
1da177e4 138};
4a5e8e29 139
1da177e4
LT		 140#define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
141
ac62ef04 142#define PCNET32_NUM_REGS 136
1da177e4 143
4a5e8e29 144#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 145static int options[MAX_UNITS];
146static int full_duplex[MAX_UNITS];
147static int homepna[MAX_UNITS];
148
149/*
150 * Theory of Operation
151 *
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
157 */
158
1da177e4
LT		 159/*
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 */
164#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 165#define PCNET32_LOG_TX_BUFFERS 4
166#define PCNET32_LOG_RX_BUFFERS 5
167#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 169#endif
170
171#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 172#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 173
174#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 175#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4
LT		 176
177#define PKT_BUF_SZ 1544
178
179/* Offsets from base I/O address. */
180#define PCNET32_WIO_RDP 0x10
181#define PCNET32_WIO_RAP 0x12
182#define PCNET32_WIO_RESET 0x14
183#define PCNET32_WIO_BDP 0x16
184
185#define PCNET32_DWIO_RDP 0x10
186#define PCNET32_DWIO_RAP 0x14
187#define PCNET32_DWIO_RESET 0x18
188#define PCNET32_DWIO_BDP 0x1C
189
190#define PCNET32_TOTAL_SIZE 0x20
191
06c87850
DF		 192#define CSR0 0
193#define CSR0_INIT 0x1
194#define CSR0_START 0x2
195#define CSR0_STOP 0x4
196#define CSR0_TXPOLL 0x8
197#define CSR0_INTEN 0x40
198#define CSR0_IDON 0x0100
199#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200#define PCNET32_INIT_LOW 1
201#define PCNET32_INIT_HIGH 2
202#define CSR3 3
203#define CSR4 4
204#define CSR5 5
205#define CSR5_SUSPEND 0x0001
206#define CSR15 15
207#define PCNET32_MC_FILTER 8
208
8d916266
DF		 209#define PCNET32_79C970A 0x2621
210
1da177e4
LT		 211/* The PCNET32 Rx and Tx ring descriptors. */
212struct pcnet32_rx_head {
0b5bf225 213 u32 base;
b368a3fb 214 s16 buf_length; /* two`s complement of length */
0b5bf225
JG		 215 s16 status;
216 u32 msg_length;
217 u32 reserved;
1da177e4
LT		 218};
219
220struct pcnet32_tx_head {
0b5bf225 221 u32 base;
b368a3fb 222 s16 length; /* two`s complement of length */
0b5bf225
JG		 223 s16 status;
224 u32 misc;
225 u32 reserved;
1da177e4
LT		 226};
227
228/* The PCNET32 32-Bit initialization block, described in databook. */
229struct pcnet32_init_block {
0b5bf225
JG		 230 u16 mode;
231 u16 tlen_rlen;
232 u8 phys_addr[6];
233 u16 reserved;
234 u32 filter[2];
4a5e8e29 235 /* Receive and transmit ring base, along with extra bits. */
0b5bf225
JG		 236 u32 rx_ring;
237 u32 tx_ring;
1da177e4
LT		 238};
239
240/* PCnet32 access functions */
241struct pcnet32_access {
4a5e8e29
JG		 242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
1da177e4
LT		 249};
250
251/*
76209926
HWL		 252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 254 */
255struct pcnet32_private {
6ecb7667 256 struct pcnet32_init_block *init_block;
4a5e8e29 257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
6ecb7667
DF		 260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
261 returned by pci_alloc_consistent */
0b5bf225
JG		 262 struct pci_dev *pci_dev;
263 const char *name;
4a5e8e29 264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 struct pcnet32_access a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int rx_ring_size; /* current rx ring size */
273 unsigned int tx_ring_size; /* current tx ring size */
274 unsigned int rx_mod_mask; /* rx ring modular mask */
275 unsigned int tx_mod_mask; /* tx ring modular mask */
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx, /* ring entries to be freed. */
281 dirty_tx;
282
bea3348e
SH		 283 struct net_device *dev;
284 struct napi_struct napi;
0b5bf225
JG		 285 struct net_device_stats stats;
286 char tx_full;
287 char phycount; /* number of phys found */
288 int options;
289 unsigned int shared_irq:1, /* shared irq possible */
290 dxsuflo:1, /* disable transmit stop on uflo */
291 mii:1; /* mii port available */
292 struct net_device *next;
293 struct mii_if_info mii_if;
294 struct timer_list watchdog_timer;
295 struct timer_list blink_timer;
296 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 297
298 /* each bit indicates an available PHY */
0b5bf225 299 u32 phymask;
8d916266 300 unsigned short chip_version; /* which variant this is */
1da177e4
LT		 301};
302
4a5e8e29
JG		 303static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
304static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
305static int pcnet32_open(struct net_device *);
306static int pcnet32_init_ring(struct net_device *);
307static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
4a5e8e29 308static void pcnet32_tx_timeout(struct net_device *dev);
7d12e780 309static irqreturn_t pcnet32_interrupt(int, void *);
4a5e8e29 310static int pcnet32_close(struct net_device *);
1da177e4
LT		 311static struct net_device_stats *pcnet32_get_stats(struct net_device *);
312static void pcnet32_load_multicast(struct net_device *dev);
313static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 314static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 315static void pcnet32_watchdog(struct net_device *);
316static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 317static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
318 int val);
1da177e4
LT		 319static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
320static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 321 struct ethtool_test *eth_test, u64 * data);
322static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 323static int pcnet32_phys_id(struct net_device *dev, u32 data);
324static void pcnet32_led_blink_callback(struct net_device *dev);
325static int pcnet32_get_regs_len(struct net_device *dev);
326static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 327 void *ptr);
1bcd3153 328static void pcnet32_purge_tx_ring(struct net_device *dev);
a88c844c 329static int pcnet32_alloc_ring(struct net_device *dev, char *name);
eabf0415 330static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 331static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 332
4a5e8e29 333static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 334{
4a5e8e29
JG		 335 outw(index, addr + PCNET32_WIO_RAP);
336 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 337}
338
4a5e8e29 339static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 340{
4a5e8e29
JG		 341 outw(index, addr + PCNET32_WIO_RAP);
342 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 343}
344
4a5e8e29 345static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 346{
4a5e8e29
JG		 347 outw(index, addr + PCNET32_WIO_RAP);
348 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 349}
350
4a5e8e29 351static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 352{
4a5e8e29
JG		 353 outw(index, addr + PCNET32_WIO_RAP);
354 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 355}
356
4a5e8e29 357static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 358{
4a5e8e29 359 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 360}
361
4a5e8e29 362static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 363{
4a5e8e29 364 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 365}
366
4a5e8e29 367static void pcnet32_wio_reset(unsigned long addr)
1da177e4 368{
4a5e8e29 369 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 370}
371
4a5e8e29 372static int pcnet32_wio_check(unsigned long addr)
1da177e4 373{
4a5e8e29
JG		 374 outw(88, addr + PCNET32_WIO_RAP);
375 return (inw(addr + PCNET32_WIO_RAP) == 88);
1da177e4
LT		 376}
377
378static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 379 .read_csr = pcnet32_wio_read_csr,
380 .write_csr = pcnet32_wio_write_csr,
381 .read_bcr = pcnet32_wio_read_bcr,
382 .write_bcr = pcnet32_wio_write_bcr,
383 .read_rap = pcnet32_wio_read_rap,
384 .write_rap = pcnet32_wio_write_rap,
385 .reset = pcnet32_wio_reset
1da177e4
LT		 386};
387
4a5e8e29 388static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 389{
4a5e8e29
JG		 390 outl(index, addr + PCNET32_DWIO_RAP);
391 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
1da177e4
LT		 392}
393
4a5e8e29 394static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 395{
4a5e8e29
JG		 396 outl(index, addr + PCNET32_DWIO_RAP);
397 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 398}
399
4a5e8e29 400static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 401{
4a5e8e29
JG		 402 outl(index, addr + PCNET32_DWIO_RAP);
403 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
1da177e4
LT		 404}
405
4a5e8e29 406static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 407{
4a5e8e29
JG		 408 outl(index, addr + PCNET32_DWIO_RAP);
409 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 410}
411
4a5e8e29 412static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 413{
4a5e8e29 414 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
1da177e4
LT		 415}
416
4a5e8e29 417static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 418{
4a5e8e29 419 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 420}
421
4a5e8e29 422static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 423{
4a5e8e29 424 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 425}
426
4a5e8e29 427static int pcnet32_dwio_check(unsigned long addr)
1da177e4 428{
4a5e8e29
JG		 429 outl(88, addr + PCNET32_DWIO_RAP);
430 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
1da177e4
LT		 431}
432
433static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 434 .read_csr = pcnet32_dwio_read_csr,
435 .write_csr = pcnet32_dwio_write_csr,
436 .read_bcr = pcnet32_dwio_read_bcr,
437 .write_bcr = pcnet32_dwio_write_bcr,
438 .read_rap = pcnet32_dwio_read_rap,
439 .write_rap = pcnet32_dwio_write_rap,
440 .reset = pcnet32_dwio_reset
1da177e4
LT		 441};
442
06c87850
DF		 443static void pcnet32_netif_stop(struct net_device *dev)
444{
bea3348e 445 struct pcnet32_private *lp = netdev_priv(dev);
06c87850 446 dev->trans_start = jiffies;
bea3348e
SH		 447#ifdef CONFIG_PCNET32_NAPI
448 napi_disable(&lp->napi);
449#endif
06c87850
DF		 450 netif_tx_disable(dev);
451}
452
453static void pcnet32_netif_start(struct net_device *dev)
454{
bea3348e 455 struct pcnet32_private *lp = netdev_priv(dev);
06c87850 456 netif_wake_queue(dev);
bea3348e
SH		 457#ifdef CONFIG_PCNET32_NAPI
458 napi_enable(&lp->napi);
459#endif
06c87850
DF		 460}
461
462/*
463 * Allocate space for the new sized tx ring.
464 * Free old resources
465 * Save new resources.
466 * Any failure keeps old resources.
467 * Must be called with lp->lock held.
468 */
469static void pcnet32_realloc_tx_ring(struct net_device *dev,
470 struct pcnet32_private *lp,
471 unsigned int size)
472{
473 dma_addr_t new_ring_dma_addr;
474 dma_addr_t *new_dma_addr_list;
475 struct pcnet32_tx_head *new_tx_ring;
476 struct sk_buff **new_skb_list;
477
478 pcnet32_purge_tx_ring(dev);
479
480 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
481 sizeof(struct pcnet32_tx_head) *
482 (1 << size),
483 &new_ring_dma_addr);
484 if (new_tx_ring == NULL) {
485 if (netif_msg_drv(lp))
486 printk("\n" KERN_ERR
487 "%s: Consistent memory allocation failed.\n",
488 dev->name);
489 return;
490 }
491 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
492
493 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
494 GFP_ATOMIC);
495 if (!new_dma_addr_list) {
496 if (netif_msg_drv(lp))
497 printk("\n" KERN_ERR
498 "%s: Memory allocation failed.\n", dev->name);
499 goto free_new_tx_ring;
500 }
501
502 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
503 GFP_ATOMIC);
504 if (!new_skb_list) {
505 if (netif_msg_drv(lp))
506 printk("\n" KERN_ERR
507 "%s: Memory allocation failed.\n", dev->name);
508 goto free_new_lists;
509 }
510
511 kfree(lp->tx_skbuff);
512 kfree(lp->tx_dma_addr);
513 pci_free_consistent(lp->pci_dev,
514 sizeof(struct pcnet32_tx_head) *
515 lp->tx_ring_size, lp->tx_ring,
516 lp->tx_ring_dma_addr);
517
518 lp->tx_ring_size = (1 << size);
519 lp->tx_mod_mask = lp->tx_ring_size - 1;
520 lp->tx_len_bits = (size << 12);
521 lp->tx_ring = new_tx_ring;
522 lp->tx_ring_dma_addr = new_ring_dma_addr;
523 lp->tx_dma_addr = new_dma_addr_list;
524 lp->tx_skbuff = new_skb_list;
525 return;
526
527 free_new_lists:
528 kfree(new_dma_addr_list);
529 free_new_tx_ring:
530 pci_free_consistent(lp->pci_dev,
531 sizeof(struct pcnet32_tx_head) *
532 (1 << size),
533 new_tx_ring,
534 new_ring_dma_addr);
535 return;
536}
537
538/*
539 * Allocate space for the new sized rx ring.
540 * Re-use old receive buffers.
541 * alloc extra buffers
542 * free unneeded buffers
543 * free unneeded buffers
544 * Save new resources.
545 * Any failure keeps old resources.
546 * Must be called with lp->lock held.
547 */
548static void pcnet32_realloc_rx_ring(struct net_device *dev,
549 struct pcnet32_private *lp,
550 unsigned int size)
551{
552 dma_addr_t new_ring_dma_addr;
553 dma_addr_t *new_dma_addr_list;
554 struct pcnet32_rx_head *new_rx_ring;
555 struct sk_buff **new_skb_list;
556 int new, overlap;
557
558 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
559 sizeof(struct pcnet32_rx_head) *
560 (1 << size),
561 &new_ring_dma_addr);
562 if (new_rx_ring == NULL) {
563 if (netif_msg_drv(lp))
564 printk("\n" KERN_ERR
565 "%s: Consistent memory allocation failed.\n",
566 dev->name);
567 return;
568 }
569 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
570
571 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
572 GFP_ATOMIC);
573 if (!new_dma_addr_list) {
574 if (netif_msg_drv(lp))
575 printk("\n" KERN_ERR
576 "%s: Memory allocation failed.\n", dev->name);
577 goto free_new_rx_ring;
578 }
579
580 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
581 GFP_ATOMIC);
582 if (!new_skb_list) {
583 if (netif_msg_drv(lp))
584 printk("\n" KERN_ERR
585 "%s: Memory allocation failed.\n", dev->name);
586 goto free_new_lists;
587 }
588
589 /* first copy the current receive buffers */
590 overlap = min(size, lp->rx_ring_size);
591 for (new = 0; new < overlap; new++) {
592 new_rx_ring[new] = lp->rx_ring[new];
593 new_dma_addr_list[new] = lp->rx_dma_addr[new];
594 new_skb_list[new] = lp->rx_skbuff[new];
595 }
596 /* now allocate any new buffers needed */
597 for (; new < size; new++ ) {
598 struct sk_buff *rx_skbuff;
599 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
600 if (!(rx_skbuff = new_skb_list[new])) {
601 /* keep the original lists and buffers */
602 if (netif_msg_drv(lp))
603 printk(KERN_ERR
604 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
605 dev->name);
606 goto free_all_new;
607 }
608 skb_reserve(rx_skbuff, 2);
609
610 new_dma_addr_list[new] =
611 pci_map_single(lp->pci_dev, rx_skbuff->data,
612 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
613 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
614 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
615 new_rx_ring[new].status = le16_to_cpu(0x8000);
616 }
617 /* and free any unneeded buffers */
618 for (; new < lp->rx_ring_size; new++) {
619 if (lp->rx_skbuff[new]) {
620 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
621 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
622 dev_kfree_skb(lp->rx_skbuff[new]);
623 }
624 }
625
626 kfree(lp->rx_skbuff);
627 kfree(lp->rx_dma_addr);
628 pci_free_consistent(lp->pci_dev,
629 sizeof(struct pcnet32_rx_head) *
630 lp->rx_ring_size, lp->rx_ring,
631 lp->rx_ring_dma_addr);
632
633 lp->rx_ring_size = (1 << size);
634 lp->rx_mod_mask = lp->rx_ring_size - 1;
635 lp->rx_len_bits = (size << 4);
636 lp->rx_ring = new_rx_ring;
637 lp->rx_ring_dma_addr = new_ring_dma_addr;
638 lp->rx_dma_addr = new_dma_addr_list;
639 lp->rx_skbuff = new_skb_list;
640 return;
641
642 free_all_new:
643 for (; --new >= lp->rx_ring_size; ) {
644 if (new_skb_list[new]) {
645 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
646 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
647 dev_kfree_skb(new_skb_list[new]);
648 }
649 }
650 kfree(new_skb_list);
651 free_new_lists:
652 kfree(new_dma_addr_list);
653 free_new_rx_ring:
654 pci_free_consistent(lp->pci_dev,
655 sizeof(struct pcnet32_rx_head) *
656 (1 << size),
657 new_rx_ring,
658 new_ring_dma_addr);
659 return;
660}
661
ac5bfe40
DF		 662static void pcnet32_purge_rx_ring(struct net_device *dev)
663{
1e56a4b4 664 struct pcnet32_private *lp = netdev_priv(dev);
ac5bfe40
DF		 665 int i;
666
667 /* free all allocated skbuffs */
668 for (i = 0; i < lp->rx_ring_size; i++) {
669 lp->rx_ring[i].status = 0; /* CPU owns buffer */
670 wmb(); /* Make sure adapter sees owner change */
671 if (lp->rx_skbuff[i]) {
672 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
673 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
674 dev_kfree_skb_any(lp->rx_skbuff[i]);
675 }
676 lp->rx_skbuff[i] = NULL;
677 lp->rx_dma_addr[i] = 0;
678 }
679}
680
1da177e4
LT		 681#ifdef CONFIG_NET_POLL_CONTROLLER
682static void pcnet32_poll_controller(struct net_device *dev)
683{
4a5e8e29 684 disable_irq(dev->irq);
7d12e780 685 pcnet32_interrupt(0, dev);
4a5e8e29 686 enable_irq(dev->irq);
1da177e4
LT		 687}
688#endif
689
1da177e4
LT		 690static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
691{
1e56a4b4 692 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 693 unsigned long flags;
694 int r = -EOPNOTSUPP;
1da177e4 695
4a5e8e29
JG		 696 if (lp->mii) {
697 spin_lock_irqsave(&lp->lock, flags);
698 mii_ethtool_gset(&lp->mii_if, cmd);
699 spin_unlock_irqrestore(&lp->lock, flags);
700 r = 0;
701 }
702 return r;
1da177e4
LT		 703}
704
705static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
706{
1e56a4b4 707 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 708 unsigned long flags;
709 int r = -EOPNOTSUPP;
1da177e4 710
4a5e8e29
JG		 711 if (lp->mii) {
712 spin_lock_irqsave(&lp->lock, flags);
713 r = mii_ethtool_sset(&lp->mii_if, cmd);
714 spin_unlock_irqrestore(&lp->lock, flags);
715 }
716 return r;
1da177e4
LT		 717}
718
4a5e8e29
JG		 719static void pcnet32_get_drvinfo(struct net_device *dev,
720 struct ethtool_drvinfo *info)
1da177e4 721{
1e56a4b4 722 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 723
724 strcpy(info->driver, DRV_NAME);
725 strcpy(info->version, DRV_VERSION);
726 if (lp->pci_dev)
727 strcpy(info->bus_info, pci_name(lp->pci_dev));
728 else
729 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 730}
731
732static u32 pcnet32_get_link(struct net_device *dev)
733{
1e56a4b4 734 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 735 unsigned long flags;
736 int r;
1da177e4 737
4a5e8e29
JG		 738 spin_lock_irqsave(&lp->lock, flags);
739 if (lp->mii) {
740 r = mii_link_ok(&lp->mii_if);
8d916266 741 } else if (lp->chip_version >= PCNET32_79C970A) {
4a5e8e29
JG		 742 ulong ioaddr = dev->base_addr; /* card base I/O address */
743 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
8d916266
DF		 744 } else { /* can not detect link on really old chips */
745 r = 1;
4a5e8e29
JG		 746 }
747 spin_unlock_irqrestore(&lp->lock, flags);
748
749 return r;
1da177e4
LT		 750}
751
752static u32 pcnet32_get_msglevel(struct net_device *dev)
753{
1e56a4b4 754 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 755 return lp->msg_enable;
1da177e4
LT		 756}
757
758static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
759{
1e56a4b4 760 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 761 lp->msg_enable = value;
1da177e4
LT		 762}
763
764static int pcnet32_nway_reset(struct net_device *dev)
765{
1e56a4b4 766 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 767 unsigned long flags;
768 int r = -EOPNOTSUPP;
1da177e4 769
4a5e8e29
JG		 770 if (lp->mii) {
771 spin_lock_irqsave(&lp->lock, flags);
772 r = mii_nway_restart(&lp->mii_if);
773 spin_unlock_irqrestore(&lp->lock, flags);
774 }
775 return r;
1da177e4
LT		 776}
777
4a5e8e29
JG		 778static void pcnet32_get_ringparam(struct net_device *dev,
779 struct ethtool_ringparam *ering)
1da177e4 780{
1e56a4b4 781 struct pcnet32_private *lp = netdev_priv(dev);
1da177e4 782
6dcd60c2
DF		 783 ering->tx_max_pending = TX_MAX_RING_SIZE;
784 ering->tx_pending = lp->tx_ring_size;
785 ering->rx_max_pending = RX_MAX_RING_SIZE;
786 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 787}
788
4a5e8e29
JG		 789static int pcnet32_set_ringparam(struct net_device *dev,
790 struct ethtool_ringparam *ering)
eabf0415 791{
1e56a4b4 792 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 793 unsigned long flags;
06c87850
DF		 794 unsigned int size;
795 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 796 int i;
797
798 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
799 return -EINVAL;
800
801 if (netif_running(dev))
06c87850 802 pcnet32_netif_stop(dev);
4a5e8e29
JG		 803
804 spin_lock_irqsave(&lp->lock, flags);
06c87850
DF		 805 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
806
807 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 808
809 /* set the minimum ring size to 4, to allow the loopback test to work
810 * unchanged.
811 */
812 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 813 if (size <= (1 << i))
4a5e8e29
JG		 814 break;
815 }
06c87850
DF		 816 if ((1 << i) != lp->tx_ring_size)
817 pcnet32_realloc_tx_ring(dev, lp, i);
b368a3fb 818
06c87850 819 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 820 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 821 if (size <= (1 << i))
4a5e8e29
JG		 822 break;
823 }
06c87850
DF		 824 if ((1 << i) != lp->rx_ring_size)
825 pcnet32_realloc_rx_ring(dev, lp, i);
b368a3fb 826
bea3348e 827 lp->napi.weight = lp->rx_ring_size / 2;
06c87850
DF		 828
829 if (netif_running(dev)) {
830 pcnet32_netif_start(dev);
831 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 832 }
eabf0415 833
4a5e8e29 834 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 835
06c87850
DF		 836 if (netif_msg_drv(lp))
837 printk(KERN_INFO
4a5e8e29
JG		 838 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
839 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 840
4a5e8e29 841 return 0;
1da177e4
LT		 842}
843
4a5e8e29
JG		 844static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
845 u8 * data)
1da177e4 846{
4a5e8e29 847 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 848}
849
850static int pcnet32_self_test_count(struct net_device *dev)
851{
4a5e8e29 852 return PCNET32_TEST_LEN;
1da177e4
LT		 853}
854
855static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 856 struct ethtool_test *test, u64 * data)
1da177e4 857{
1e56a4b4 858 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 859 int rc;
860
861 if (test->flags == ETH_TEST_FL_OFFLINE) {
862 rc = pcnet32_loopback_test(dev, data);
863 if (rc) {
864 if (netif_msg_hw(lp))
865 printk(KERN_DEBUG "%s: Loopback test failed.\n",
866 dev->name);
867 test->flags |= ETH_TEST_FL_FAILED;
868 } else if (netif_msg_hw(lp))
869 printk(KERN_DEBUG "%s: Loopback test passed.\n",
870 dev->name);
1da177e4 871 } else if (netif_msg_hw(lp))
4a5e8e29
JG		 872 printk(KERN_DEBUG
873 "%s: No tests to run (specify 'Offline' on ethtool).",
874 dev->name);
875} /* end pcnet32_ethtool_test */
1da177e4 876
4a5e8e29 877static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 878{
1e56a4b4 879 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 880 struct pcnet32_access *a = &lp->a; /* access to registers */
881 ulong ioaddr = dev->base_addr; /* card base I/O address */
882 struct sk_buff *skb; /* sk buff */
883 int x, i; /* counters */
884 int numbuffs = 4; /* number of TX/RX buffers and descs */
885 u16 status = 0x8300; /* TX ring status */
886 u16 teststatus; /* test of ring status */
887 int rc; /* return code */
888 int size; /* size of packets */
889 unsigned char *packet; /* source packet data */
890 static const int data_len = 60; /* length of source packets */
891 unsigned long flags;
892 unsigned long ticks;
893
4a5e8e29
JG		 894 rc = 1; /* default to fail */
895
896 if (netif_running(dev))
7de745e5
DF		 897#ifdef CONFIG_PCNET32_NAPI
898 pcnet32_netif_stop(dev);
899#else
4a5e8e29 900 pcnet32_close(dev);
7de745e5 901#endif
4a5e8e29
JG		 902
903 spin_lock_irqsave(&lp->lock, flags);
ac5bfe40
DF		 904 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
905
906 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
4a5e8e29
JG		 907
908 /* Reset the PCNET32 */
909 lp->a.reset(ioaddr);
b368a3fb 910 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
4a5e8e29
JG		 911
912 /* switch pcnet32 to 32bit mode */
913 lp->a.write_bcr(ioaddr, 20, 2);
914
4a5e8e29
JG		 915 /* purge & init rings but don't actually restart */
916 pcnet32_restart(dev, 0x0000);
917
ac5bfe40 918 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 919
920 /* Initialize Transmit buffers. */
921 size = data_len + 15;
922 for (x = 0; x < numbuffs; x++) {
923 if (!(skb = dev_alloc_skb(size))) {
924 if (netif_msg_hw(lp))
925 printk(KERN_DEBUG
926 "%s: Cannot allocate skb at line: %d!\n",
927 dev->name, __LINE__);
928 goto clean_up;
929 } else {
930 packet = skb->data;
931 skb_put(skb, size); /* create space for data */
932 lp->tx_skbuff[x] = skb;
933 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
934 lp->tx_ring[x].misc = 0;
935
936 /* put DA and SA into the skb */
937 for (i = 0; i < 6; i++)
938 *packet++ = dev->dev_addr[i];
939 for (i = 0; i < 6; i++)
940 *packet++ = dev->dev_addr[i];
941 /* type */
942 *packet++ = 0x08;
943 *packet++ = 0x06;
944 /* packet number */
945 *packet++ = x;
946 /* fill packet with data */
947 for (i = 0; i < data_len; i++)
948 *packet++ = i;
949
950 lp->tx_dma_addr[x] =
951 pci_map_single(lp->pci_dev, skb->data, skb->len,
952 PCI_DMA_TODEVICE);
953 lp->tx_ring[x].base =
954 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
955 wmb(); /* Make sure owner changes after all others are visible */
956 lp->tx_ring[x].status = le16_to_cpu(status);
957 }
1da177e4 958 }
1da177e4 959
ac5bfe40
DF		 960 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
961 a->write_bcr(ioaddr, 32, x | 0x0002);
4a5e8e29 962
ac5bfe40
DF		 963 /* set int loopback in CSR15 */
964 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
965 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
4a5e8e29
JG		 966
967 teststatus = le16_to_cpu(0x8000);
ac5bfe40 968 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
4a5e8e29
JG		 969
970 /* Check status of descriptors */
971 for (x = 0; x < numbuffs; x++) {
972 ticks = 0;
973 rmb();
974 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
975 spin_unlock_irqrestore(&lp->lock, flags);
ac5bfe40 976 msleep(1);
4a5e8e29
JG		 977 spin_lock_irqsave(&lp->lock, flags);
978 rmb();
979 ticks++;
980 }
981 if (ticks == 200) {
982 if (netif_msg_hw(lp))
983 printk("%s: Desc %d failed to reset!\n",
984 dev->name, x);
985 break;
986 }
987 }
988
ac5bfe40 989 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 990 wmb();
991 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
992 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
993
994 for (x = 0; x < numbuffs; x++) {
995 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
996 skb = lp->rx_skbuff[x];
997 for (i = 0; i < size; i++) {
998 printk("%02x ", *(skb->data + i));
999 }
1000 printk("\n");
1001 }
1002 }
1da177e4 1003
4a5e8e29
JG		 1004 x = 0;
1005 rc = 0;
1006 while (x < numbuffs && !rc) {
1007 skb = lp->rx_skbuff[x];
1008 packet = lp->tx_skbuff[x]->data;
1009 for (i = 0; i < size; i++) {
1010 if (*(skb->data + i) != packet[i]) {
1011 if (netif_msg_hw(lp))
1012 printk(KERN_DEBUG
1013 "%s: Error in compare! %2x - %02x %02x\n",
1014 dev->name, i, *(skb->data + i),
1015 packet[i]);
1016 rc = 1;
1017 break;
1018 }
1019 }
1020 x++;
1021 }
1da177e4 1022
4a5e8e29 1023 clean_up:
ac5bfe40 1024 *data1 = rc;
4a5e8e29 1025 pcnet32_purge_tx_ring(dev);
1da177e4 1026
ac5bfe40
DF		 1027 x = a->read_csr(ioaddr, CSR15);
1028 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 1029
ac5bfe40
DF		 1030 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1031 a->write_bcr(ioaddr, 32, (x & ~0x0002));
4a5e8e29 1032
7de745e5
DF		 1033#ifdef CONFIG_PCNET32_NAPI
1034 if (netif_running(dev)) {
1035 pcnet32_netif_start(dev);
1036 pcnet32_restart(dev, CSR0_NORMAL);
1037 } else {
1038 pcnet32_purge_rx_ring(dev);
1039 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1040 }
1041 spin_unlock_irqrestore(&lp->lock, flags);
1042#else
4a5e8e29 1043 if (netif_running(dev)) {
ac5bfe40 1044 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29
JG		 1045 pcnet32_open(dev);
1046 } else {
ac5bfe40 1047 pcnet32_purge_rx_ring(dev);
4a5e8e29 1048 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
ac5bfe40 1049 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29 1050 }
7de745e5 1051#endif
4a5e8e29
JG		 1052
1053 return (rc);
1054} /* end pcnet32_loopback_test */
1da177e4
LT		 1055
1056static void pcnet32_led_blink_callback(struct net_device *dev)
1057{
1e56a4b4 1058 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1059 struct pcnet32_access *a = &lp->a;
1060 ulong ioaddr = dev->base_addr;
1061 unsigned long flags;
1062 int i;
1063
1064 spin_lock_irqsave(&lp->lock, flags);
1065 for (i = 4; i < 8; i++) {
1066 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1067 }
1068 spin_unlock_irqrestore(&lp->lock, flags);
1069
1070 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 1071}
1072
1073static int pcnet32_phys_id(struct net_device *dev, u32 data)
1074{
1e56a4b4 1075 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1076 struct pcnet32_access *a = &lp->a;
1077 ulong ioaddr = dev->base_addr;
1078 unsigned long flags;
1079 int i, regs[4];
1080
1081 if (!lp->blink_timer.function) {
1082 init_timer(&lp->blink_timer);
1083 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1084 lp->blink_timer.data = (unsigned long)dev;
1085 }
1086
1087 /* Save the current value of the bcrs */
1088 spin_lock_irqsave(&lp->lock, flags);
1089 for (i = 4; i < 8; i++) {
1090 regs[i - 4] = a->read_bcr(ioaddr, i);
1091 }
1092 spin_unlock_irqrestore(&lp->lock, flags);
1093
1094 mod_timer(&lp->blink_timer, jiffies);
1095 set_current_state(TASK_INTERRUPTIBLE);
1096
1097 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1098 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1099
1100 msleep_interruptible(data * 1000);
1101 del_timer_sync(&lp->blink_timer);
1102
1103 /* Restore the original value of the bcrs */
1104 spin_lock_irqsave(&lp->lock, flags);
1105 for (i = 4; i < 8; i++) {
1106 a->write_bcr(ioaddr, i, regs[i - 4]);
1107 }
1108 spin_unlock_irqrestore(&lp->lock, flags);
1109
1110 return 0;
1da177e4
LT		 1111}
1112
df27f4a6
DF		 1113/*
1114 * lp->lock must be held.
1115 */
1116static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1117 int can_sleep)
1118{
1119 int csr5;
1e56a4b4 1120 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6
DF		 1121 struct pcnet32_access *a = &lp->a;
1122 ulong ioaddr = dev->base_addr;
1123 int ticks;
1124
8d916266
DF		 1125 /* really old chips have to be stopped. */
1126 if (lp->chip_version < PCNET32_79C970A)
1127 return 0;
1128
df27f4a6
DF		 1129 /* set SUSPEND (SPND) - CSR5 bit 0 */
1130 csr5 = a->read_csr(ioaddr, CSR5);
1131 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1132
1133 /* poll waiting for bit to be set */
1134 ticks = 0;
1135 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1136 spin_unlock_irqrestore(&lp->lock, *flags);
1137 if (can_sleep)
1138 msleep(1);
1139 else
1140 mdelay(1);
1141 spin_lock_irqsave(&lp->lock, *flags);
1142 ticks++;
1143 if (ticks > 200) {
1144 if (netif_msg_hw(lp))
1145 printk(KERN_DEBUG
1146 "%s: Error getting into suspend!\n",
1147 dev->name);
1148 return 0;
1149 }
1150 }
1151 return 1;
1152}
1153
3904c324
DF		 1154/*
1155 * process one receive descriptor entry
1156 */
1157
1158static void pcnet32_rx_entry(struct net_device *dev,
1159 struct pcnet32_private *lp,
1160 struct pcnet32_rx_head *rxp,
1161 int entry)
1162{
1163 int status = (short)le16_to_cpu(rxp->status) >> 8;
1164 int rx_in_place = 0;
1165 struct sk_buff *skb;
1166 short pkt_len;
1167
1168 if (status != 0x03) { /* There was an error. */
1169 /*
1170 * There is a tricky error noted by John Murphy,
1171 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1172 * buffers it's possible for a jabber packet to use two
1173 * buffers, with only the last correctly noting the error.
1174 */
1175 if (status & 0x01) /* Only count a general error at the */
1176 lp->stats.rx_errors++; /* end of a packet. */
1177 if (status & 0x20)
1178 lp->stats.rx_frame_errors++;
1179 if (status & 0x10)
1180 lp->stats.rx_over_errors++;
1181 if (status & 0x08)
1182 lp->stats.rx_crc_errors++;
1183 if (status & 0x04)
1184 lp->stats.rx_fifo_errors++;
1185 return;
1186 }
1187
1188 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1189
1190 /* Discard oversize frames. */
1191 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1192 if (netif_msg_drv(lp))
1193 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1194 dev->name, pkt_len);
1195 lp->stats.rx_errors++;
1196 return;
1197 }
1198 if (pkt_len < 60) {
1199 if (netif_msg_rx_err(lp))
1200 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1201 lp->stats.rx_errors++;
1202 return;
1203 }
1204
1205 if (pkt_len > rx_copybreak) {
1206 struct sk_buff *newskb;
1207
1208 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1209 skb_reserve(newskb, 2);
1210 skb = lp->rx_skbuff[entry];
1211 pci_unmap_single(lp->pci_dev,
1212 lp->rx_dma_addr[entry],
1213 PKT_BUF_SZ - 2,
1214 PCI_DMA_FROMDEVICE);
1215 skb_put(skb, pkt_len);
1216 lp->rx_skbuff[entry] = newskb;
3904c324
DF		 1217 lp->rx_dma_addr[entry] =
1218 pci_map_single(lp->pci_dev,
1219 newskb->data,
1220 PKT_BUF_SZ - 2,
1221 PCI_DMA_FROMDEVICE);
1222 rxp->base = le32_to_cpu(lp->rx_dma_addr[entry]);
1223 rx_in_place = 1;
1224 } else
1225 skb = NULL;
1226 } else {
1227 skb = dev_alloc_skb(pkt_len + 2);
1228 }
1229
1230 if (skb == NULL) {
1231 if (netif_msg_drv(lp))
1232 printk(KERN_ERR
1233 "%s: Memory squeeze, dropping packet.\n",
1234 dev->name);
1235 lp->stats.rx_dropped++;
1236 return;
1237 }
1238 skb->dev = dev;
1239 if (!rx_in_place) {
1240 skb_reserve(skb, 2); /* 16 byte align */
1241 skb_put(skb, pkt_len); /* Make room */
1242 pci_dma_sync_single_for_cpu(lp->pci_dev,
1243 lp->rx_dma_addr[entry],
b2cbbd8e 1244 pkt_len,
3904c324 1245 PCI_DMA_FROMDEVICE);
8c7b7faa 1246 skb_copy_to_linear_data(skb,
3904c324 1247 (unsigned char *)(lp->rx_skbuff[entry]->data),
8c7b7faa 1248 pkt_len);
3904c324
DF		 1249 pci_dma_sync_single_for_device(lp->pci_dev,
1250 lp->rx_dma_addr[entry],
b2cbbd8e 1251 pkt_len,
3904c324
DF		 1252 PCI_DMA_FROMDEVICE);
1253 }
1254 lp->stats.rx_bytes += skb->len;
1255 skb->protocol = eth_type_trans(skb, dev);
7de745e5
DF		 1256#ifdef CONFIG_PCNET32_NAPI
1257 netif_receive_skb(skb);
1258#else
3904c324 1259 netif_rx(skb);
7de745e5 1260#endif
3904c324
DF		 1261 dev->last_rx = jiffies;
1262 lp->stats.rx_packets++;
1263 return;
1264}
1265
bea3348e 1266static int pcnet32_rx(struct net_device *dev, int budget)
9691edd2 1267{
1e56a4b4 1268 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2 1269 int entry = lp->cur_rx & lp->rx_mod_mask;
3904c324
DF		 1270 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1271 int npackets = 0;
9691edd2
DF		 1272
1273 /* If we own the next entry, it's a new packet. Send it up. */
bea3348e 1274 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
3904c324
DF		 1275 pcnet32_rx_entry(dev, lp, rxp, entry);
1276 npackets += 1;
9691edd2 1277 /*
3904c324
DF		 1278 * The docs say that the buffer length isn't touched, but Andrew
1279 * Boyd of QNX reports that some revs of the 79C965 clear it.
9691edd2 1280 */
3904c324
DF		 1281 rxp->buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
1282 wmb(); /* Make sure owner changes after others are visible */
1283 rxp->status = le16_to_cpu(0x8000);
9691edd2 1284 entry = (++lp->cur_rx) & lp->rx_mod_mask;
3904c324 1285 rxp = &lp->rx_ring[entry];
9691edd2
DF		 1286 }
1287
7de745e5 1288 return npackets;
9691edd2
DF		 1289}
1290
7de745e5 1291static int pcnet32_tx(struct net_device *dev)
9691edd2 1292{
1e56a4b4 1293 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2
DF		 1294 unsigned int dirty_tx = lp->dirty_tx;
1295 int delta;
1296 int must_restart = 0;
1297
1298 while (dirty_tx != lp->cur_tx) {
1299 int entry = dirty_tx & lp->tx_mod_mask;
1300 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1301
1302 if (status < 0)
1303 break; /* It still hasn't been Txed */
1304
1305 lp->tx_ring[entry].base = 0;
1306
1307 if (status & 0x4000) {
3904c324 1308 /* There was a major error, log it. */
9691edd2
DF		 1309 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1310 lp->stats.tx_errors++;
1311 if (netif_msg_tx_err(lp))
1312 printk(KERN_ERR
1313 "%s: Tx error status=%04x err_status=%08x\n",
1314 dev->name, status,
1315 err_status);
1316 if (err_status & 0x04000000)
1317 lp->stats.tx_aborted_errors++;
1318 if (err_status & 0x08000000)
1319 lp->stats.tx_carrier_errors++;
1320 if (err_status & 0x10000000)
1321 lp->stats.tx_window_errors++;
1322#ifndef DO_DXSUFLO
1323 if (err_status & 0x40000000) {
1324 lp->stats.tx_fifo_errors++;
1325 /* Ackk! On FIFO errors the Tx unit is turned off! */
1326 /* Remove this verbosity later! */
1327 if (netif_msg_tx_err(lp))
1328 printk(KERN_ERR
7de745e5
DF		 1329 "%s: Tx FIFO error!\n",
1330 dev->name);
9691edd2
DF		 1331 must_restart = 1;
1332 }
1333#else
1334 if (err_status & 0x40000000) {
1335 lp->stats.tx_fifo_errors++;
1336 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1337 /* Ackk! On FIFO errors the Tx unit is turned off! */
1338 /* Remove this verbosity later! */
3904c324 1339 if (netif_msg_tx_err(lp))
9691edd2 1340 printk(KERN_ERR
7de745e5
DF		 1341 "%s: Tx FIFO error!\n",
1342 dev->name);
9691edd2
DF		 1343 must_restart = 1;
1344 }
1345 }
1346#endif
1347 } else {
1348 if (status & 0x1800)
1349 lp->stats.collisions++;
1350 lp->stats.tx_packets++;
1351 }
1352
1353 /* We must free the original skb */
1354 if (lp->tx_skbuff[entry]) {
1355 pci_unmap_single(lp->pci_dev,
1356 lp->tx_dma_addr[entry],
1357 lp->tx_skbuff[entry]->
1358 len, PCI_DMA_TODEVICE);
3904c324 1359 dev_kfree_skb_any(lp->tx_skbuff[entry]);
9691edd2
DF		 1360 lp->tx_skbuff[entry] = NULL;
1361 lp->tx_dma_addr[entry] = 0;
1362 }
1363 dirty_tx++;
1364 }
1365
3904c324 1366 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
9691edd2
DF		 1367 if (delta > lp->tx_ring_size) {
1368 if (netif_msg_drv(lp))
1369 printk(KERN_ERR
1370 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1371 dev->name, dirty_tx, lp->cur_tx,
1372 lp->tx_full);
1373 dirty_tx += lp->tx_ring_size;
1374 delta -= lp->tx_ring_size;
1375 }
1376
1377 if (lp->tx_full &&
1378 netif_queue_stopped(dev) &&
1379 delta < lp->tx_ring_size - 2) {
1380 /* The ring is no longer full, clear tbusy. */
1381 lp->tx_full = 0;
1382 netif_wake_queue(dev);
1383 }
1384 lp->dirty_tx = dirty_tx;
1385
1386 return must_restart;
1387}
1388
7de745e5 1389#ifdef CONFIG_PCNET32_NAPI
bea3348e 1390static int pcnet32_poll(struct napi_struct *napi, int budget)
7de745e5 1391{
bea3348e
SH		 1392 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1393 struct net_device *dev = lp->dev;
7de745e5
DF		 1394 unsigned long ioaddr = dev->base_addr;
1395 unsigned long flags;
bea3348e 1396 int work_done;
7de745e5
DF		 1397 u16 val;
1398
bea3348e 1399 work_done = pcnet32_rx(dev, budget);
7de745e5
DF		 1400
1401 spin_lock_irqsave(&lp->lock, flags);
1402 if (pcnet32_tx(dev)) {
1403 /* reset the chip to clear the error condition, then restart */
1404 lp->a.reset(ioaddr);
1405 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1406 pcnet32_restart(dev, CSR0_START);
1407 netif_wake_queue(dev);
1408 }
1409 spin_unlock_irqrestore(&lp->lock, flags);
1410
bea3348e
SH		 1411 if (work_done < budget) {
1412 spin_lock_irqsave(&lp->lock, flags);
7de745e5 1413
bea3348e 1414 __netif_rx_complete(dev, napi);
7de745e5 1415
bea3348e
SH		 1416 /* clear interrupt masks */
1417 val = lp->a.read_csr(ioaddr, CSR3);
1418 val &= 0x00ff;
1419 lp->a.write_csr(ioaddr, CSR3, val);
7de745e5 1420
bea3348e
SH		 1421 /* Set interrupt enable. */
1422 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1423 mmiowb();
1424 spin_unlock_irqrestore(&lp->lock, flags);
1425 }
1426 return work_done;
7de745e5
DF		 1427}
1428#endif
1429
ac62ef04
DF		 1430#define PCNET32_REGS_PER_PHY 32
1431#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1432static int pcnet32_get_regs_len(struct net_device *dev)
1433{
1e56a4b4 1434 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 1435 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1436
4a5e8e29 1437 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1da177e4
LT		 1438}
1439
1440static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1441 void *ptr)
1da177e4 1442{
4a5e8e29
JG		 1443 int i, csr0;
1444 u16 *buff = ptr;
1e56a4b4 1445 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1446 struct pcnet32_access *a = &lp->a;
1447 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1448 unsigned long flags;
1449
1450 spin_lock_irqsave(&lp->lock, flags);
1451
df27f4a6
DF		 1452 csr0 = a->read_csr(ioaddr, CSR0);
1453 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1454 pcnet32_suspend(dev, &flags, 1);
1da177e4 1455
4a5e8e29
JG		 1456 /* read address PROM */
1457 for (i = 0; i < 16; i += 2)
1458 *buff++ = inw(ioaddr + i);
1459
1460 /* read control and status registers */
1461 for (i = 0; i < 90; i++) {
1462 *buff++ = a->read_csr(ioaddr, i);
1463 }
1464
1465 *buff++ = a->read_csr(ioaddr, 112);
1466 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1467
4a5e8e29
JG		 1468 /* read bus configuration registers */
1469 for (i = 0; i < 30; i++) {
1470 *buff++ = a->read_bcr(ioaddr, i);
1471 }
1472 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1473 for (i = 31; i < 36; i++) {
1474 *buff++ = a->read_bcr(ioaddr, i);
1475 }
1476
1477 /* read mii phy registers */
1478 if (lp->mii) {
1479 int j;
1480 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1481 if (lp->phymask & (1 << j)) {
1482 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1483 lp->a.write_bcr(ioaddr, 33,
1484 (j << 5) | i);
1485 *buff++ = lp->a.read_bcr(ioaddr, 34);
1486 }
1487 }
1488 }
1489 }
1490
df27f4a6
DF		 1491 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1492 int csr5;
1493
4a5e8e29 1494 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1495 csr5 = a->read_csr(ioaddr, CSR5);
1496 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1497 }
1498
1499 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1500}
1501
7282d491 1502static const struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1503 .get_settings = pcnet32_get_settings,
1504 .set_settings = pcnet32_set_settings,
1505 .get_drvinfo = pcnet32_get_drvinfo,
1506 .get_msglevel = pcnet32_get_msglevel,
1507 .set_msglevel = pcnet32_set_msglevel,
1508 .nway_reset = pcnet32_nway_reset,
1509 .get_link = pcnet32_get_link,
1510 .get_ringparam = pcnet32_get_ringparam,
1511 .set_ringparam = pcnet32_set_ringparam,
1512 .get_tx_csum = ethtool_op_get_tx_csum,
1513 .get_sg = ethtool_op_get_sg,
1514 .get_tso = ethtool_op_get_tso,
1515 .get_strings = pcnet32_get_strings,
1516 .self_test_count = pcnet32_self_test_count,
1517 .self_test = pcnet32_ethtool_test,
1518 .phys_id = pcnet32_phys_id,
1519 .get_regs_len = pcnet32_get_regs_len,
1520 .get_regs = pcnet32_get_regs,
1da177e4
LT		 1521};
1522
1523/* only probes for non-PCI devices, the rest are handled by
1524 * pci_register_driver via pcnet32_probe_pci */
1525
dcaf9769 1526static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1527{
4a5e8e29
JG		 1528 unsigned int *port, ioaddr;
1529
1530 /* search for PCnet32 VLB cards at known addresses */
1531 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1532 if (request_region
1533 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1534 /* check if there is really a pcnet chip on that ioaddr */
1535 if ((inb(ioaddr + 14) == 0x57)
1536 && (inb(ioaddr + 15) == 0x57)) {
1537 pcnet32_probe1(ioaddr, 0, NULL);
1538 } else {
1539 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1540 }
1541 }
1542 }
1da177e4
LT		 1543}
1544
1da177e4
LT		 1545static int __devinit
1546pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1547{
4a5e8e29
JG		 1548 unsigned long ioaddr;
1549 int err;
1550
1551 err = pci_enable_device(pdev);
1552 if (err < 0) {
1553 if (pcnet32_debug & NETIF_MSG_PROBE)
1554 printk(KERN_ERR PFX
1555 "failed to enable device -- err=%d\n", err);
1556 return err;
1557 }
1558 pci_set_master(pdev);
1559
1560 ioaddr = pci_resource_start(pdev, 0);
1561 if (!ioaddr) {
1562 if (pcnet32_debug & NETIF_MSG_PROBE)
1563 printk(KERN_ERR PFX
1564 "card has no PCI IO resources, aborting\n");
1565 return -ENODEV;
1566 }
1da177e4 1567
4a5e8e29
JG		 1568 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1569 if (pcnet32_debug & NETIF_MSG_PROBE)
1570 printk(KERN_ERR PFX
1571 "architecture does not support 32bit PCI busmaster DMA\n");
1572 return -ENODEV;
1573 }
1574 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1575 NULL) {
1576 if (pcnet32_debug & NETIF_MSG_PROBE)
1577 printk(KERN_ERR PFX
1578 "io address range already allocated\n");
1579 return -EBUSY;
1580 }
1da177e4 1581
4a5e8e29
JG		 1582 err = pcnet32_probe1(ioaddr, 1, pdev);
1583 if (err < 0) {
1584 pci_disable_device(pdev);
1585 }
1586 return err;
1da177e4
LT		 1587}
1588
1da177e4
LT		 1589/* pcnet32_probe1
1590 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1591 * pdev will be NULL when called from pcnet32_probe_vlbus.
1592 */
1593static int __devinit
1594pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1595{
4a5e8e29 1596 struct pcnet32_private *lp;
4a5e8e29
JG		 1597 int i, media;
1598 int fdx, mii, fset, dxsuflo;
1599 int chip_version;
1600 char *chipname;
1601 struct net_device *dev;
1602 struct pcnet32_access *a = NULL;
1603 u8 promaddr[6];
1604 int ret = -ENODEV;
1605
1606 /* reset the chip */
1607 pcnet32_wio_reset(ioaddr);
1608
1609 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1610 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1611 a = &pcnet32_wio;
1612 } else {
1613 pcnet32_dwio_reset(ioaddr);
1614 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1615 && pcnet32_dwio_check(ioaddr)) {
1616 a = &pcnet32_dwio;
1617 } else
1618 goto err_release_region;
1619 }
1620
1621 chip_version =
1622 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1623 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1624 printk(KERN_INFO " PCnet chip version is %#x.\n",
1625 chip_version);
1626 if ((chip_version & 0xfff) != 0x003) {
1627 if (pcnet32_debug & NETIF_MSG_PROBE)
1628 printk(KERN_INFO PFX "Unsupported chip version.\n");
1629 goto err_release_region;
1630 }
1631
1632 /* initialize variables */
1633 fdx = mii = fset = dxsuflo = 0;
1634 chip_version = (chip_version >> 12) & 0xffff;
1635
1636 switch (chip_version) {
1637 case 0x2420:
1638 chipname = "PCnet/PCI 79C970"; /* PCI */
1639 break;
1640 case 0x2430:
1641 if (shared)
1642 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1643 else
1644 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1645 break;
1646 case 0x2621:
1647 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1648 fdx = 1;
1649 break;
1650 case 0x2623:
1651 chipname = "PCnet/FAST 79C971"; /* PCI */
1652 fdx = 1;
1653 mii = 1;
1654 fset = 1;
1655 break;
1656 case 0x2624:
1657 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1658 fdx = 1;
1659 mii = 1;
1660 fset = 1;
1661 break;
1662 case 0x2625:
1663 chipname = "PCnet/FAST III 79C973"; /* PCI */
1664 fdx = 1;
1665 mii = 1;
1666 break;
1667 case 0x2626:
1668 chipname = "PCnet/Home 79C978"; /* PCI */
1669 fdx = 1;
1670 /*
1671 * This is based on specs published at www.amd.com. This section
1672 * assumes that a card with a 79C978 wants to go into standard
1673 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1674 * and the module option homepna=1 can select this instead.
1675 */
1676 media = a->read_bcr(ioaddr, 49);
1677 media &= ~3; /* default to 10Mb ethernet */
1678 if (cards_found < MAX_UNITS && homepna[cards_found])
1679 media |= 1; /* switch to home wiring mode */
1680 if (pcnet32_debug & NETIF_MSG_PROBE)
1681 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1682 (media & 1) ? "1" : "10");
1683 a->write_bcr(ioaddr, 49, media);
1684 break;
1685 case 0x2627:
1686 chipname = "PCnet/FAST III 79C975"; /* PCI */
1687 fdx = 1;
1688 mii = 1;
1689 break;
1690 case 0x2628:
1691 chipname = "PCnet/PRO 79C976";
1692 fdx = 1;
1693 mii = 1;
1694 break;
1695 default:
1696 if (pcnet32_debug & NETIF_MSG_PROBE)
1697 printk(KERN_INFO PFX
1698 "PCnet version %#x, no PCnet32 chip.\n",
1699 chip_version);
1700 goto err_release_region;
1701 }
1702
1da177e4 1703 /*
4a5e8e29
JG		 1704 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1705 * starting until the packet is loaded. Strike one for reliability, lose
1706 * one for latency - although on PCI this isnt a big loss. Older chips
1707 * have FIFO's smaller than a packet, so you can't do this.
1708 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1709 */
4a5e8e29
JG		 1710
1711 if (fset) {
1712 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1713 a->write_csr(ioaddr, 80,
1714 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1715 dxsuflo = 1;
1716 }
1717
6ecb7667 1718 dev = alloc_etherdev(sizeof(*lp));
4a5e8e29
JG		 1719 if (!dev) {
1720 if (pcnet32_debug & NETIF_MSG_PROBE)
1721 printk(KERN_ERR PFX "Memory allocation failed.\n");
1722 ret = -ENOMEM;
1723 goto err_release_region;
1724 }
1725 SET_NETDEV_DEV(dev, &pdev->dev);
1726
1da177e4 1727 if (pcnet32_debug & NETIF_MSG_PROBE)
4a5e8e29
JG		 1728 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1729
1730 /* In most chips, after a chip reset, the ethernet address is read from the
1731 * station address PROM at the base address and programmed into the
1732 * "Physical Address Registers" CSR12-14.
1733 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1734 * they disagree with the CSRs. If they miscompare, and the PROM addr
1735 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1736 */
1737 for (i = 0; i < 3; i++) {
1738 unsigned int val;
1739 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1740 /* There may be endianness issues here. */
1741 dev->dev_addr[2 * i] = val & 0x0ff;
1742 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1743 }
1744
1745 /* read PROM address and compare with CSR address */
1da177e4 1746 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1747 promaddr[i] = inb(ioaddr + i);
1748
1749 if (memcmp(promaddr, dev->dev_addr, 6)
1750 || !is_valid_ether_addr(dev->dev_addr)) {
1751 if (is_valid_ether_addr(promaddr)) {
1752 if (pcnet32_debug & NETIF_MSG_PROBE) {
1753 printk(" warning: CSR address invalid,\n");
1754 printk(KERN_INFO
1755 " using instead PROM address of");
1756 }
1757 memcpy(dev->dev_addr, promaddr, 6);
1758 }
1759 }
1760 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1761
1762 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1763 if (!is_valid_ether_addr(dev->perm_addr))
1764 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1765
1766 if (pcnet32_debug & NETIF_MSG_PROBE) {
1767 for (i = 0; i < 6; i++)
1768 printk(" %2.2x", dev->dev_addr[i]);
1769
1770 /* Version 0x2623 and 0x2624 */
1771 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1772 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1773 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1774 switch (i >> 10) {
1775 case 0:
1776 printk(" 20 bytes,");
1777 break;
1778 case 1:
1779 printk(" 64 bytes,");
1780 break;
1781 case 2:
1782 printk(" 128 bytes,");
1783 break;
1784 case 3:
1785 printk("~220 bytes,");
1786 break;
1787 }
1788 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1789 printk(" BCR18(%x):", i & 0xffff);
1790 if (i & (1 << 5))
1791 printk("BurstWrEn ");
1792 if (i & (1 << 6))
1793 printk("BurstRdEn ");
1794 if (i & (1 << 7))
1795 printk("DWordIO ");
1796 if (i & (1 << 11))
1797 printk("NoUFlow ");
1798 i = a->read_bcr(ioaddr, 25);
1799 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1800 i = a->read_bcr(ioaddr, 26);
1801 printk(" SRAM_BND=0x%04x,", i << 8);
1802 i = a->read_bcr(ioaddr, 27);
1803 if (i & (1 << 14))
1804 printk("LowLatRx");
1805 }
1806 }
1807
1808 dev->base_addr = ioaddr;
1e56a4b4 1809 lp = netdev_priv(dev);
4a5e8e29 1810 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
6ecb7667
DF		 1811 if ((lp->init_block =
1812 pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
4a5e8e29
JG		 1813 if (pcnet32_debug & NETIF_MSG_PROBE)
1814 printk(KERN_ERR PFX
1815 "Consistent memory allocation failed.\n");
1816 ret = -ENOMEM;
1817 goto err_free_netdev;
1818 }
4a5e8e29
JG		 1819 lp->pci_dev = pdev;
1820
bea3348e
SH		 1821 lp->dev = dev;
1822
4a5e8e29
JG		 1823 spin_lock_init(&lp->lock);
1824
1825 SET_MODULE_OWNER(dev);
1826 SET_NETDEV_DEV(dev, &pdev->dev);
4a5e8e29
JG		 1827 lp->name = chipname;
1828 lp->shared_irq = shared;
1829 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1830 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1831 lp->tx_mod_mask = lp->tx_ring_size - 1;
1832 lp->rx_mod_mask = lp->rx_ring_size - 1;
1833 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1834 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1835 lp->mii_if.full_duplex = fdx;
1836 lp->mii_if.phy_id_mask = 0x1f;
1837 lp->mii_if.reg_num_mask = 0x1f;
1838 lp->dxsuflo = dxsuflo;
1839 lp->mii = mii;
8d916266 1840 lp->chip_version = chip_version;
4a5e8e29
JG		 1841 lp->msg_enable = pcnet32_debug;
1842 if ((cards_found >= MAX_UNITS)
1843 || (options[cards_found] > sizeof(options_mapping)))
1844 lp->options = PCNET32_PORT_ASEL;
1845 else
1846 lp->options = options_mapping[options[cards_found]];
1847 lp->mii_if.dev = dev;
1848 lp->mii_if.mdio_read = mdio_read;
1849 lp->mii_if.mdio_write = mdio_write;
1850
bea3348e
SH		 1851#ifdef CONFIG_PCNET32_NAPI
1852 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1853#endif
1854
4a5e8e29
JG		 1855 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1856 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1857 lp->options |= PCNET32_PORT_FD;
1858
1859 if (!a) {
1860 if (pcnet32_debug & NETIF_MSG_PROBE)
1861 printk(KERN_ERR PFX "No access methods\n");
1862 ret = -ENODEV;
1863 goto err_free_consistent;
1864 }
1865 lp->a = *a;
1866
1867 /* prior to register_netdev, dev->name is not yet correct */
1868 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1869 ret = -ENOMEM;
1870 goto err_free_ring;
1871 }
1872 /* detect special T1/E1 WAN card by checking for MAC address */
1873 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1da177e4 1874 && dev->dev_addr[2] == 0x75)
4a5e8e29 1875 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1876
6ecb7667
DF		 1877 lp->init_block->mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1878 lp->init_block->tlen_rlen =
4a5e8e29
JG		 1879 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1880 for (i = 0; i < 6; i++)
6ecb7667
DF		 1881 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1882 lp->init_block->filter[0] = 0x00000000;
1883 lp->init_block->filter[1] = 0x00000000;
1884 lp->init_block->rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1885 lp->init_block->tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
4a5e8e29
JG		 1886
1887 /* switch pcnet32 to 32bit mode */
1888 a->write_bcr(ioaddr, 20, 2);
1889
6ecb7667
DF		 1890 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1891 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29
JG		 1892
1893 if (pdev) { /* use the IRQ provided by PCI */
1894 dev->irq = pdev->irq;
1895 if (pcnet32_debug & NETIF_MSG_PROBE)
1896 printk(" assigned IRQ %d.\n", dev->irq);
1897 } else {
1898 unsigned long irq_mask = probe_irq_on();
1899
1900 /*
1901 * To auto-IRQ we enable the initialization-done and DMA error
1902 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1903 * boards will work.
1904 */
1905 /* Trigger an initialization just for the interrupt. */
b368a3fb 1906 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
4a5e8e29
JG		 1907 mdelay(1);
1908
1909 dev->irq = probe_irq_off(irq_mask);
1910 if (!dev->irq) {
1911 if (pcnet32_debug & NETIF_MSG_PROBE)
1912 printk(", failed to detect IRQ line.\n");
1913 ret = -ENODEV;
1914 goto err_free_ring;
1915 }
1916 if (pcnet32_debug & NETIF_MSG_PROBE)
1917 printk(", probed IRQ %d.\n", dev->irq);
1918 }
1da177e4 1919
4a5e8e29
JG		 1920 /* Set the mii phy_id so that we can query the link state */
1921 if (lp->mii) {
1922 /* lp->phycount and lp->phymask are set to 0 by memset above */
1923
1924 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1925 /* scan for PHYs */
1926 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1927 unsigned short id1, id2;
1928
1929 id1 = mdio_read(dev, i, MII_PHYSID1);
1930 if (id1 == 0xffff)
1931 continue;
1932 id2 = mdio_read(dev, i, MII_PHYSID2);
1933 if (id2 == 0xffff)
1934 continue;
1935 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1936 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1937 lp->phycount++;
1938 lp->phymask |= (1 << i);
1939 lp->mii_if.phy_id = i;
1940 if (pcnet32_debug & NETIF_MSG_PROBE)
1941 printk(KERN_INFO PFX
1942 "Found PHY %04x:%04x at address %d.\n",
1943 id1, id2, i);
1944 }
1945 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1946 if (lp->phycount > 1) {
1947 lp->options |= PCNET32_PORT_MII;
1948 }
1da177e4 1949 }
4a5e8e29
JG		 1950
1951 init_timer(&lp->watchdog_timer);
1952 lp->watchdog_timer.data = (unsigned long)dev;
1953 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1954
1955 /* The PCNET32-specific entries in the device structure. */
1956 dev->open = &pcnet32_open;
1957 dev->hard_start_xmit = &pcnet32_start_xmit;
1958 dev->stop = &pcnet32_close;
1959 dev->get_stats = &pcnet32_get_stats;
1960 dev->set_multicast_list = &pcnet32_set_multicast_list;
1961 dev->do_ioctl = &pcnet32_ioctl;
1962 dev->ethtool_ops = &pcnet32_ethtool_ops;
1963 dev->tx_timeout = pcnet32_tx_timeout;
1964 dev->watchdog_timeo = (5 * HZ);
1da177e4
LT		 1965
1966#ifdef CONFIG_NET_POLL_CONTROLLER
4a5e8e29 1967 dev->poll_controller = pcnet32_poll_controller;
1da177e4
LT		 1968#endif
1969
4a5e8e29
JG		 1970 /* Fill in the generic fields of the device structure. */
1971 if (register_netdev(dev))
1972 goto err_free_ring;
1973
1974 if (pdev) {
1975 pci_set_drvdata(pdev, dev);
1976 } else {
1977 lp->next = pcnet32_dev;
1978 pcnet32_dev = dev;
1979 }
1980
1981 if (pcnet32_debug & NETIF_MSG_PROBE)
1982 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1983 cards_found++;
1984
1985 /* enable LED writes */
1986 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1987
4a5e8e29
JG		 1988 return 0;
1989
1990 err_free_ring:
1991 pcnet32_free_ring(dev);
1992 err_free_consistent:
6ecb7667
DF		 1993 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1994 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 1995 err_free_netdev:
1996 free_netdev(dev);
1997 err_release_region:
1998 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1999 return ret;
2000}
1da177e4 2001
a88c844c
DF		 2002/* if any allocation fails, caller must also call pcnet32_free_ring */
2003static int pcnet32_alloc_ring(struct net_device *dev, char *name)
eabf0415 2004{
1e56a4b4 2005 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 2006
4a5e8e29
JG		 2007 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2008 sizeof(struct pcnet32_tx_head) *
2009 lp->tx_ring_size,
2010 &lp->tx_ring_dma_addr);
2011 if (lp->tx_ring == NULL) {
12fa30f3 2012 if (netif_msg_drv(lp))
4a5e8e29
JG		 2013 printk("\n" KERN_ERR PFX
2014 "%s: Consistent memory allocation failed.\n",
2015 name);
2016 return -ENOMEM;
2017 }
eabf0415 2018
4a5e8e29
JG		 2019 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2020 sizeof(struct pcnet32_rx_head) *
2021 lp->rx_ring_size,
2022 &lp->rx_ring_dma_addr);
2023 if (lp->rx_ring == NULL) {
12fa30f3 2024 if (netif_msg_drv(lp))
4a5e8e29
JG		 2025 printk("\n" KERN_ERR PFX
2026 "%s: Consistent memory allocation failed.\n",
2027 name);
2028 return -ENOMEM;
2029 }
eabf0415 2030
12fa30f3 2031 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2032 GFP_ATOMIC);
2033 if (!lp->tx_dma_addr) {
12fa30f3 2034 if (netif_msg_drv(lp))
4a5e8e29
JG		 2035 printk("\n" KERN_ERR PFX
2036 "%s: Memory allocation failed.\n", name);
2037 return -ENOMEM;
2038 }
4a5e8e29 2039
12fa30f3 2040 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2041 GFP_ATOMIC);
2042 if (!lp->rx_dma_addr) {
12fa30f3 2043 if (netif_msg_drv(lp))
4a5e8e29
JG		 2044 printk("\n" KERN_ERR PFX
2045 "%s: Memory allocation failed.\n", name);
2046 return -ENOMEM;
2047 }
4a5e8e29 2048
12fa30f3 2049 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2050 GFP_ATOMIC);
2051 if (!lp->tx_skbuff) {
12fa30f3 2052 if (netif_msg_drv(lp))
4a5e8e29
JG		 2053 printk("\n" KERN_ERR PFX
2054 "%s: Memory allocation failed.\n", name);
2055 return -ENOMEM;
2056 }
4a5e8e29 2057
12fa30f3 2058 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2059 GFP_ATOMIC);
2060 if (!lp->rx_skbuff) {
12fa30f3 2061 if (netif_msg_drv(lp))
4a5e8e29
JG		 2062 printk("\n" KERN_ERR PFX
2063 "%s: Memory allocation failed.\n", name);
2064 return -ENOMEM;
2065 }
4a5e8e29
JG		 2066
2067 return 0;
2068}
eabf0415
HWL		 2069
2070static void pcnet32_free_ring(struct net_device *dev)
2071{
1e56a4b4 2072 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 2073
4a5e8e29
JG		 2074 kfree(lp->tx_skbuff);
2075 lp->tx_skbuff = NULL;
eabf0415 2076
4a5e8e29
JG		 2077 kfree(lp->rx_skbuff);
2078 lp->rx_skbuff = NULL;
eabf0415 2079
4a5e8e29
JG		 2080 kfree(lp->tx_dma_addr);
2081 lp->tx_dma_addr = NULL;
eabf0415 2082
4a5e8e29
JG		 2083 kfree(lp->rx_dma_addr);
2084 lp->rx_dma_addr = NULL;
eabf0415 2085
4a5e8e29
JG		 2086 if (lp->tx_ring) {
2087 pci_free_consistent(lp->pci_dev,
2088 sizeof(struct pcnet32_tx_head) *
2089 lp->tx_ring_size, lp->tx_ring,
2090 lp->tx_ring_dma_addr);
2091 lp->tx_ring = NULL;
2092 }
eabf0415 2093
4a5e8e29
JG		 2094 if (lp->rx_ring) {
2095 pci_free_consistent(lp->pci_dev,
2096 sizeof(struct pcnet32_rx_head) *
2097 lp->rx_ring_size, lp->rx_ring,
2098 lp->rx_ring_dma_addr);
2099 lp->rx_ring = NULL;
2100 }
eabf0415
HWL		 2101}
2102
4a5e8e29 2103static int pcnet32_open(struct net_device *dev)
1da177e4 2104{
1e56a4b4 2105 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2106 unsigned long ioaddr = dev->base_addr;
2107 u16 val;
2108 int i;
2109 int rc;
2110 unsigned long flags;
2111
2112 if (request_irq(dev->irq, &pcnet32_interrupt,
1fb9df5d 2113 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 2114 (void *)dev)) {
2115 return -EAGAIN;
2116 }
2117
2118 spin_lock_irqsave(&lp->lock, flags);
2119 /* Check for a valid station address */
2120 if (!is_valid_ether_addr(dev->dev_addr)) {
2121 rc = -EINVAL;
2122 goto err_free_irq;
2123 }
2124
2125 /* Reset the PCNET32 */
2126 lp->a.reset(ioaddr);
2127
2128 /* switch pcnet32 to 32bit mode */
2129 lp->a.write_bcr(ioaddr, 20, 2);
2130
2131 if (netif_msg_ifup(lp))
2132 printk(KERN_DEBUG
2133 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2134 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2135 (u32) (lp->rx_ring_dma_addr),
6ecb7667 2136 (u32) (lp->init_dma_addr));
4a5e8e29
JG		 2137
2138 /* set/reset autoselect bit */
2139 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2140 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 2141 val |= 2;
4a5e8e29
JG		 2142 lp->a.write_bcr(ioaddr, 2, val);
2143
2144 /* handle full duplex setting */
2145 if (lp->mii_if.full_duplex) {
2146 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2147 if (lp->options & PCNET32_PORT_FD) {
2148 val |= 1;
2149 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2150 val |= 2;
2151 } else if (lp->options & PCNET32_PORT_ASEL) {
2152 /* workaround of xSeries250, turn on for 79C975 only */
8d916266 2153 if (lp->chip_version == 0x2627)
4a5e8e29
JG		 2154 val |= 3;
2155 }
2156 lp->a.write_bcr(ioaddr, 9, val);
2157 }
2158
2159 /* set/reset GPSI bit in test register */
2160 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2161 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2162 val |= 0x10;
2163 lp->a.write_csr(ioaddr, 124, val);
2164
2165 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2166 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2964bbd7
DF		 2167 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2168 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 2169 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29
JG		 2170 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2171 if (netif_msg_link(lp))
2172 printk(KERN_DEBUG
2173 "%s: Setting 100Mb-Full Duplex.\n",
2174 dev->name);
2175 }
2176 }
2177 if (lp->phycount < 2) {
2178 /*
2179 * 24 Jun 2004 according AMD, in order to change the PHY,
2180 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2181 * duplex, and/or enable auto negotiation, and clear DANAS
2182 */
2183 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2184 lp->a.write_bcr(ioaddr, 32,
2185 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2186 /* disable Auto Negotiation, set 10Mpbs, HD */
2187 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2188 if (lp->options & PCNET32_PORT_FD)
2189 val |= 0x10;
2190 if (lp->options & PCNET32_PORT_100)
2191 val |= 0x08;
2192 lp->a.write_bcr(ioaddr, 32, val);
2193 } else {
2194 if (lp->options & PCNET32_PORT_ASEL) {
2195 lp->a.write_bcr(ioaddr, 32,
2196 lp->a.read_bcr(ioaddr,
2197 32) | 0x0080);
2198 /* enable auto negotiate, setup, disable fd */
2199 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2200 val |= 0x20;
2201 lp->a.write_bcr(ioaddr, 32, val);
2202 }
2203 }
2204 } else {
2205 int first_phy = -1;
2206 u16 bmcr;
2207 u32 bcr9;
2208 struct ethtool_cmd ecmd;
2209
2210 /*
2211 * There is really no good other way to handle multiple PHYs
2212 * other than turning off all automatics
2213 */
2214 val = lp->a.read_bcr(ioaddr, 2);
2215 lp->a.write_bcr(ioaddr, 2, val & ~2);
2216 val = lp->a.read_bcr(ioaddr, 32);
2217 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2218
2219 if (!(lp->options & PCNET32_PORT_ASEL)) {
2220 /* setup ecmd */
2221 ecmd.port = PORT_MII;
2222 ecmd.transceiver = XCVR_INTERNAL;
2223 ecmd.autoneg = AUTONEG_DISABLE;
2224 ecmd.speed =
2225 lp->
2226 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2227 bcr9 = lp->a.read_bcr(ioaddr, 9);
2228
2229 if (lp->options & PCNET32_PORT_FD) {
2230 ecmd.duplex = DUPLEX_FULL;
2231 bcr9 |= (1 << 0);
2232 } else {
2233 ecmd.duplex = DUPLEX_HALF;
2234 bcr9 |= ~(1 << 0);
2235 }
2236 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 2237 }
4a5e8e29
JG		 2238
2239 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2240 if (lp->phymask & (1 << i)) {
2241 /* isolate all but the first PHY */
2242 bmcr = mdio_read(dev, i, MII_BMCR);
2243 if (first_phy == -1) {
2244 first_phy = i;
2245 mdio_write(dev, i, MII_BMCR,
2246 bmcr & ~BMCR_ISOLATE);
2247 } else {
2248 mdio_write(dev, i, MII_BMCR,
2249 bmcr | BMCR_ISOLATE);
2250 }
2251 /* use mii_ethtool_sset to setup PHY */
2252 lp->mii_if.phy_id = i;
2253 ecmd.phy_address = i;
2254 if (lp->options & PCNET32_PORT_ASEL) {
2255 mii_ethtool_gset(&lp->mii_if, &ecmd);
2256 ecmd.autoneg = AUTONEG_ENABLE;
2257 }
2258 mii_ethtool_sset(&lp->mii_if, &ecmd);
2259 }
2260 }
2261 lp->mii_if.phy_id = first_phy;
2262 if (netif_msg_link(lp))
2263 printk(KERN_INFO "%s: Using PHY number %d.\n",
2264 dev->name, first_phy);
2265 }
1da177e4
LT		 2266
2267#ifdef DO_DXSUFLO
4a5e8e29 2268 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
b368a3fb 2269 val = lp->a.read_csr(ioaddr, CSR3);
4a5e8e29 2270 val |= 0x40;
b368a3fb 2271 lp->a.write_csr(ioaddr, CSR3, val);
4a5e8e29 2272 }
1da177e4
LT		 2273#endif
2274
6ecb7667 2275 lp->init_block->mode =
4a5e8e29
JG		 2276 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2277 pcnet32_load_multicast(dev);
2278
2279 if (pcnet32_init_ring(dev)) {
2280 rc = -ENOMEM;
2281 goto err_free_ring;
2282 }
2283
bea3348e
SH		 2284#ifdef CONFIG_PCNET32_NAPI
2285 napi_enable(&lp->napi);
2286#endif
2287
4a5e8e29 2288 /* Re-initialize the PCNET32, and start it when done. */
6ecb7667
DF		 2289 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2290 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29 2291
b368a3fb
DF		 2292 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2293 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2294
2295 netif_start_queue(dev);
2296
8d916266
DF		 2297 if (lp->chip_version >= PCNET32_79C970A) {
2298 /* Print the link status and start the watchdog */
2299 pcnet32_check_media(dev, 1);
2300 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2301 }
4a5e8e29
JG		 2302
2303 i = 0;
2304 while (i++ < 100)
b368a3fb 2305 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29
JG		 2306 break;
2307 /*
2308 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2309 * reports that doing so triggers a bug in the '974.
2310 */
b368a3fb 2311 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
4a5e8e29
JG		 2312
2313 if (netif_msg_ifup(lp))
2314 printk(KERN_DEBUG
2315 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2316 dev->name, i,
6ecb7667 2317 (u32) (lp->init_dma_addr),
b368a3fb 2318 lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2319
2320 spin_unlock_irqrestore(&lp->lock, flags);
2321
2322 return 0; /* Always succeed */
2323
2324 err_free_ring:
2325 /* free any allocated skbuffs */
ac5bfe40 2326 pcnet32_purge_rx_ring(dev);
4a5e8e29 2327
4a5e8e29
JG		 2328 /*
2329 * Switch back to 16bit mode to avoid problems with dumb
2330 * DOS packet driver after a warm reboot
2331 */
2332 lp->a.write_bcr(ioaddr, 20, 4);
2333
2334 err_free_irq:
2335 spin_unlock_irqrestore(&lp->lock, flags);
2336 free_irq(dev->irq, dev);
2337 return rc;
1da177e4
LT		 2338}
2339
2340/*
2341 * The LANCE has been halted for one reason or another (busmaster memory
2342 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2343 * etc.). Modern LANCE variants always reload their ring-buffer
2344 * configuration when restarted, so we must reinitialize our ring
2345 * context before restarting. As part of this reinitialization,
2346 * find all packets still on the Tx ring and pretend that they had been
2347 * sent (in effect, drop the packets on the floor) - the higher-level
2348 * protocols will time out and retransmit. It'd be better to shuffle
2349 * these skbs to a temp list and then actually re-Tx them after
2350 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2351 */
2352
4a5e8e29 2353static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2354{
1e56a4b4 2355 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2356 int i;
1da177e4 2357
4a5e8e29
JG		 2358 for (i = 0; i < lp->tx_ring_size; i++) {
2359 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2360 wmb(); /* Make sure adapter sees owner change */
2361 if (lp->tx_skbuff[i]) {
2362 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2363 lp->tx_skbuff[i]->len,
2364 PCI_DMA_TODEVICE);
2365 dev_kfree_skb_any(lp->tx_skbuff[i]);
2366 }
2367 lp->tx_skbuff[i] = NULL;
2368 lp->tx_dma_addr[i] = 0;
2369 }
2370}
1da177e4
LT		 2371
2372/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2373static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2374{
1e56a4b4 2375 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2376 int i;
2377
2378 lp->tx_full = 0;
2379 lp->cur_rx = lp->cur_tx = 0;
2380 lp->dirty_rx = lp->dirty_tx = 0;
2381
2382 for (i = 0; i < lp->rx_ring_size; i++) {
2383 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2384 if (rx_skbuff == NULL) {
2385 if (!
2386 (rx_skbuff = lp->rx_skbuff[i] =
2387 dev_alloc_skb(PKT_BUF_SZ))) {
2388 /* there is not much, we can do at this point */
b368a3fb 2389 if (netif_msg_drv(lp))
4a5e8e29
JG		 2390 printk(KERN_ERR
2391 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2392 dev->name);
2393 return -1;
2394 }
2395 skb_reserve(rx_skbuff, 2);
2396 }
2397
2398 rmb();
2399 if (lp->rx_dma_addr[i] == 0)
2400 lp->rx_dma_addr[i] =
2401 pci_map_single(lp->pci_dev, rx_skbuff->data,
2402 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2403 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
2404 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2405 wmb(); /* Make sure owner changes after all others are visible */
2406 lp->rx_ring[i].status = le16_to_cpu(0x8000);
2407 }
2408 /* The Tx buffer address is filled in as needed, but we do need to clear
2409 * the upper ownership bit. */
2410 for (i = 0; i < lp->tx_ring_size; i++) {
2411 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2412 wmb(); /* Make sure adapter sees owner change */
2413 lp->tx_ring[i].base = 0;
2414 lp->tx_dma_addr[i] = 0;
2415 }
2416
6ecb7667 2417 lp->init_block->tlen_rlen =
4a5e8e29
JG		 2418 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
2419 for (i = 0; i < 6; i++)
6ecb7667
DF		 2420 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2421 lp->init_block->rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
2422 lp->init_block->tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
4a5e8e29
JG		 2423 wmb(); /* Make sure all changes are visible */
2424 return 0;
1da177e4
LT		 2425}
2426
2427/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2428 * then flush the pending transmit operations, re-initialize the ring,
2429 * and tell the chip to initialize.
2430 */
4a5e8e29 2431static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2432{
1e56a4b4 2433 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2434 unsigned long ioaddr = dev->base_addr;
2435 int i;
1da177e4 2436
4a5e8e29
JG		 2437 /* wait for stop */
2438 for (i = 0; i < 100; i++)
b368a3fb 2439 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
4a5e8e29 2440 break;
1da177e4 2441
4a5e8e29
JG		 2442 if (i >= 100 && netif_msg_drv(lp))
2443 printk(KERN_ERR
2444 "%s: pcnet32_restart timed out waiting for stop.\n",
2445 dev->name);
1da177e4 2446
4a5e8e29
JG		 2447 pcnet32_purge_tx_ring(dev);
2448 if (pcnet32_init_ring(dev))
2449 return;
1da177e4 2450
4a5e8e29 2451 /* ReInit Ring */
b368a3fb 2452 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2453 i = 0;
2454 while (i++ < 1000)
b368a3fb 2455 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29 2456 break;
1da177e4 2457
b368a3fb 2458 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
1da177e4
LT		 2459}
2460
4a5e8e29 2461static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2462{
1e56a4b4 2463 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2464 unsigned long ioaddr = dev->base_addr, flags;
2465
2466 spin_lock_irqsave(&lp->lock, flags);
2467 /* Transmitter timeout, serious problems. */
2468 if (pcnet32_debug & NETIF_MSG_DRV)
2469 printk(KERN_ERR
2470 "%s: transmit timed out, status %4.4x, resetting.\n",
b368a3fb
DF		 2471 dev->name, lp->a.read_csr(ioaddr, CSR0));
2472 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
4a5e8e29
JG		 2473 lp->stats.tx_errors++;
2474 if (netif_msg_tx_err(lp)) {
2475 int i;
2476 printk(KERN_DEBUG
2477 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2478 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2479 lp->cur_rx);
2480 for (i = 0; i < lp->rx_ring_size; i++)
2481 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2482 le32_to_cpu(lp->rx_ring[i].base),
2483 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2484 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2485 le16_to_cpu(lp->rx_ring[i].status));
2486 for (i = 0; i < lp->tx_ring_size; i++)
2487 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2488 le32_to_cpu(lp->tx_ring[i].base),
2489 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2490 le32_to_cpu(lp->tx_ring[i].misc),
2491 le16_to_cpu(lp->tx_ring[i].status));
2492 printk("\n");
2493 }
b368a3fb 2494 pcnet32_restart(dev, CSR0_NORMAL);
1da177e4 2495
4a5e8e29
JG		 2496 dev->trans_start = jiffies;
2497 netif_wake_queue(dev);
1da177e4 2498
4a5e8e29
JG		 2499 spin_unlock_irqrestore(&lp->lock, flags);
2500}
2501
2502static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 2503{
1e56a4b4 2504 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2505 unsigned long ioaddr = dev->base_addr;
2506 u16 status;
2507 int entry;
2508 unsigned long flags;
1da177e4 2509
4a5e8e29 2510 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2511
4a5e8e29
JG		 2512 if (netif_msg_tx_queued(lp)) {
2513 printk(KERN_DEBUG
2514 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
b368a3fb 2515 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2516 }
1da177e4 2517
4a5e8e29
JG		 2518 /* Default status -- will not enable Successful-TxDone
2519 * interrupt when that option is available to us.
2520 */
2521 status = 0x8300;
1da177e4 2522
4a5e8e29 2523 /* Fill in a Tx ring entry */
1da177e4 2524
4a5e8e29
JG		 2525 /* Mask to ring buffer boundary. */
2526 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2527
4a5e8e29
JG		 2528 /* Caution: the write order is important here, set the status
2529 * with the "ownership" bits last. */
1da177e4 2530
4a5e8e29 2531 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1da177e4 2532
4a5e8e29 2533 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2534
4a5e8e29
JG		 2535 lp->tx_skbuff[entry] = skb;
2536 lp->tx_dma_addr[entry] =
2537 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2538 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
2539 wmb(); /* Make sure owner changes after all others are visible */
2540 lp->tx_ring[entry].status = le16_to_cpu(status);
1da177e4 2541
4a5e8e29
JG		 2542 lp->cur_tx++;
2543 lp->stats.tx_bytes += skb->len;
1da177e4 2544
4a5e8e29 2545 /* Trigger an immediate send poll. */
b368a3fb 2546 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
1da177e4 2547
4a5e8e29 2548 dev->trans_start = jiffies;
1da177e4 2549
4a5e8e29
JG		 2550 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2551 lp->tx_full = 1;
2552 netif_stop_queue(dev);
2553 }
2554 spin_unlock_irqrestore(&lp->lock, flags);
2555 return 0;
1da177e4
LT		 2556}
2557
2558/* The PCNET32 interrupt handler. */
2559static irqreturn_t
7d12e780 2560pcnet32_interrupt(int irq, void *dev_id)
1da177e4 2561{
4a5e8e29
JG		 2562 struct net_device *dev = dev_id;
2563 struct pcnet32_private *lp;
2564 unsigned long ioaddr;
5c99346a 2565 u16 csr0;
4a5e8e29 2566 int boguscnt = max_interrupt_work;
4a5e8e29 2567
4a5e8e29 2568 ioaddr = dev->base_addr;
1e56a4b4 2569 lp = netdev_priv(dev);
1da177e4 2570
4a5e8e29
JG		 2571 spin_lock(&lp->lock);
2572
3904c324
DF		 2573 csr0 = lp->a.read_csr(ioaddr, CSR0);
2574 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
4a5e8e29
JG		 2575 if (csr0 == 0xffff) {
2576 break; /* PCMCIA remove happened */
2577 }
2578 /* Acknowledge all of the current interrupt sources ASAP. */
3904c324 2579 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
4a5e8e29 2580
4a5e8e29
JG		 2581 if (netif_msg_intr(lp))
2582 printk(KERN_DEBUG
2583 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
3904c324 2584 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2585
4a5e8e29
JG		 2586 /* Log misc errors. */
2587 if (csr0 & 0x4000)
2588 lp->stats.tx_errors++; /* Tx babble. */
2589 if (csr0 & 0x1000) {
2590 /*
3904c324
DF		 2591 * This happens when our receive ring is full. This
2592 * shouldn't be a problem as we will see normal rx
2593 * interrupts for the frames in the receive ring. But
2594 * there are some PCI chipsets (I can reproduce this
2595 * on SP3G with Intel saturn chipset) which have
2596 * sometimes problems and will fill up the receive
2597 * ring with error descriptors. In this situation we
2598 * don't get a rx interrupt, but a missed frame
7de745e5 2599 * interrupt sooner or later.
4a5e8e29 2600 */
4a5e8e29
JG		 2601 lp->stats.rx_errors++; /* Missed a Rx frame. */
2602 }
2603 if (csr0 & 0x0800) {
2604 if (netif_msg_drv(lp))
2605 printk(KERN_ERR
2606 "%s: Bus master arbitration failure, status %4.4x.\n",
2607 dev->name, csr0);
2608 /* unlike for the lance, there is no restart needed */
1da177e4 2609 }
7de745e5 2610#ifdef CONFIG_PCNET32_NAPI
bea3348e 2611 if (netif_rx_schedule_prep(dev, &lp->napi)) {
7de745e5
DF		 2612 u16 val;
2613 /* set interrupt masks */
2614 val = lp->a.read_csr(ioaddr, CSR3);
2615 val |= 0x5f00;
2616 lp->a.write_csr(ioaddr, CSR3, val);
2617 mmiowb();
bea3348e 2618 __netif_rx_schedule(dev, &lp->napi);
7de745e5
DF		 2619 break;
2620 }
2621#else
bea3348e 2622 pcnet32_rx(dev, lp->napi.weight);
7de745e5 2623 if (pcnet32_tx(dev)) {
4a5e8e29
JG		 2624 /* reset the chip to clear the error condition, then restart */
2625 lp->a.reset(ioaddr);
7de745e5 2626 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
b368a3fb 2627 pcnet32_restart(dev, CSR0_START);
4a5e8e29 2628 netif_wake_queue(dev);
1da177e4 2629 }
7de745e5 2630#endif
3904c324 2631 csr0 = lp->a.read_csr(ioaddr, CSR0);
4a5e8e29
JG		 2632 }
2633
7de745e5 2634#ifndef CONFIG_PCNET32_NAPI
4a5e8e29 2635 /* Set interrupt enable. */
b368a3fb 2636 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
7de745e5 2637#endif
4a5e8e29
JG		 2638
2639 if (netif_msg_intr(lp))
2640 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
b368a3fb 2641 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2642
2643 spin_unlock(&lp->lock);
2644
2645 return IRQ_HANDLED;
1da177e4
LT		 2646}
2647
4a5e8e29 2648static int pcnet32_close(struct net_device *dev)
1da177e4 2649{
4a5e8e29 2650 unsigned long ioaddr = dev->base_addr;
1e56a4b4 2651 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2652 unsigned long flags;
1da177e4 2653
4a5e8e29 2654 del_timer_sync(&lp->watchdog_timer);
1da177e4 2655
4a5e8e29 2656 netif_stop_queue(dev);
bea3348e
SH		 2657#ifdef CONFIG_PCNET32_NAPI
2658 napi_disable(&lp->napi);
2659#endif
1da177e4 2660
4a5e8e29 2661 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2662
4a5e8e29 2663 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2664
4a5e8e29
JG		 2665 if (netif_msg_ifdown(lp))
2666 printk(KERN_DEBUG
2667 "%s: Shutting down ethercard, status was %2.2x.\n",
b368a3fb 2668 dev->name, lp->a.read_csr(ioaddr, CSR0));
1da177e4 2669
4a5e8e29 2670 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
b368a3fb 2671 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
1da177e4 2672
4a5e8e29
JG		 2673 /*
2674 * Switch back to 16bit mode to avoid problems with dumb
2675 * DOS packet driver after a warm reboot
2676 */
2677 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2678
4a5e8e29 2679 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2680
4a5e8e29 2681 free_irq(dev->irq, dev);
1da177e4 2682
4a5e8e29 2683 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2684
ac5bfe40
DF		 2685 pcnet32_purge_rx_ring(dev);
2686 pcnet32_purge_tx_ring(dev);
1da177e4 2687
4a5e8e29 2688 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2689
4a5e8e29 2690 return 0;
1da177e4
LT		 2691}
2692
4a5e8e29 2693static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2694{
1e56a4b4 2695 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2696 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2697 unsigned long flags;
2698
2699 spin_lock_irqsave(&lp->lock, flags);
4a5e8e29 2700 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
4a5e8e29
JG		 2701 spin_unlock_irqrestore(&lp->lock, flags);
2702
2703 return &lp->stats;
1da177e4
LT		 2704}
2705
2706/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2707static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2708{
1e56a4b4 2709 struct pcnet32_private *lp = netdev_priv(dev);
6ecb7667 2710 volatile struct pcnet32_init_block *ib = lp->init_block;
4a5e8e29
JG		 2711 volatile u16 *mcast_table = (u16 *) & ib->filter;
2712 struct dev_mc_list *dmi = dev->mc_list;
df27f4a6 2713 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2714 char *addrs;
2715 int i;
2716 u32 crc;
2717
2718 /* set all multicast bits */
2719 if (dev->flags & IFF_ALLMULTI) {
2720 ib->filter[0] = 0xffffffff;
2721 ib->filter[1] = 0xffffffff;
df27f4a6
DF		 2722 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2723 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2724 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2725 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2726 return;
2727 }
2728 /* clear the multicast filter */
2729 ib->filter[0] = 0;
2730 ib->filter[1] = 0;
2731
2732 /* Add addresses */
2733 for (i = 0; i < dev->mc_count; i++) {
2734 addrs = dmi->dmi_addr;
2735 dmi = dmi->next;
2736
2737 /* multicast address? */
2738 if (!(*addrs & 1))
2739 continue;
2740
2741 crc = ether_crc_le(6, addrs);
2742 crc = crc >> 26;
2743 mcast_table[crc >> 4] =
2744 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2745 (1 << (crc & 0xf)));
2746 }
df27f4a6
DF		 2747 for (i = 0; i < 4; i++)
2748 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2749 le16_to_cpu(mcast_table[i]));
1da177e4 2750 return;
1da177e4
LT		 2751}
2752
1da177e4
LT		 2753/*
2754 * Set or clear the multicast filter for this adaptor.
2755 */
2756static void pcnet32_set_multicast_list(struct net_device *dev)
2757{
4a5e8e29 2758 unsigned long ioaddr = dev->base_addr, flags;
1e56a4b4 2759 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6 2760 int csr15, suspended;
4a5e8e29
JG		 2761
2762 spin_lock_irqsave(&lp->lock, flags);
df27f4a6
DF		 2763 suspended = pcnet32_suspend(dev, &flags, 0);
2764 csr15 = lp->a.read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2765 if (dev->flags & IFF_PROMISC) {
2766 /* Log any net taps. */
2767 if (netif_msg_hw(lp))
2768 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2769 dev->name);
6ecb7667 2770 lp->init_block->mode =
4a5e8e29
JG		 2771 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2772 7);
df27f4a6 2773 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29 2774 } else {
6ecb7667 2775 lp->init_block->mode =
4a5e8e29 2776 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
df27f4a6 2777 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2778 pcnet32_load_multicast(dev);
2779 }
2780
df27f4a6
DF		 2781 if (suspended) {
2782 int csr5;
2783 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2784 csr5 = lp->a.read_csr(ioaddr, CSR5);
2785 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
b368a3fb 2786 } else {
df27f4a6
DF		 2787 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2788 pcnet32_restart(dev, CSR0_NORMAL);
2789 netif_wake_queue(dev);
2790 }
4a5e8e29
JG		 2791
2792 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2793}
2794
2795/* This routine assumes that the lp->lock is held */
2796static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2797{
1e56a4b4 2798 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2799 unsigned long ioaddr = dev->base_addr;
2800 u16 val_out;
1da177e4 2801
4a5e8e29
JG		 2802 if (!lp->mii)
2803 return 0;
1da177e4 2804
4a5e8e29
JG		 2805 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2806 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2807
4a5e8e29 2808 return val_out;
1da177e4
LT		 2809}
2810
2811/* This routine assumes that the lp->lock is held */
2812static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2813{
1e56a4b4 2814 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2815 unsigned long ioaddr = dev->base_addr;
1da177e4 2816
4a5e8e29
JG		 2817 if (!lp->mii)
2818 return;
1da177e4 2819
4a5e8e29
JG		 2820 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2821 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2822}
2823
2824static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2825{
1e56a4b4 2826 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2827 int rc;
2828 unsigned long flags;
1da177e4 2829
4a5e8e29
JG		 2830 /* SIOC[GS]MIIxxx ioctls */
2831 if (lp->mii) {
2832 spin_lock_irqsave(&lp->lock, flags);
2833 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2834 spin_unlock_irqrestore(&lp->lock, flags);
2835 } else {
2836 rc = -EOPNOTSUPP;
2837 }
1da177e4 2838
4a5e8e29 2839 return rc;
1da177e4
LT		 2840}
2841
ac62ef04
DF		 2842static int pcnet32_check_otherphy(struct net_device *dev)
2843{
1e56a4b4 2844 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2845 struct mii_if_info mii = lp->mii_if;
2846 u16 bmcr;
2847 int i;
ac62ef04 2848
4a5e8e29
JG		 2849 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2850 if (i == lp->mii_if.phy_id)
2851 continue; /* skip active phy */
2852 if (lp->phymask & (1 << i)) {
2853 mii.phy_id = i;
2854 if (mii_link_ok(&mii)) {
2855 /* found PHY with active link */
2856 if (netif_msg_link(lp))
2857 printk(KERN_INFO
2858 "%s: Using PHY number %d.\n",
2859 dev->name, i);
2860
2861 /* isolate inactive phy */
2862 bmcr =
2863 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2864 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2865 bmcr | BMCR_ISOLATE);
2866
2867 /* de-isolate new phy */
2868 bmcr = mdio_read(dev, i, MII_BMCR);
2869 mdio_write(dev, i, MII_BMCR,
2870 bmcr & ~BMCR_ISOLATE);
2871
2872 /* set new phy address */
2873 lp->mii_if.phy_id = i;
2874 return 1;
2875 }
2876 }
ac62ef04 2877 }
4a5e8e29 2878 return 0;
ac62ef04
DF		 2879}
2880
2881/*
2882 * Show the status of the media. Similar to mii_check_media however it
2883 * correctly shows the link speed for all (tested) pcnet32 variants.
2884 * Devices with no mii just report link state without speed.
2885 *
2886 * Caller is assumed to hold and release the lp->lock.
2887 */
2888
2889static void pcnet32_check_media(struct net_device *dev, int verbose)
2890{
1e56a4b4 2891 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2892 int curr_link;
2893 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2894 u32 bcr9;
2895
ac62ef04 2896 if (lp->mii) {
4a5e8e29 2897 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2898 } else {
4a5e8e29
JG		 2899 ulong ioaddr = dev->base_addr; /* card base I/O address */
2900 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2901 }
2902 if (!curr_link) {
2903 if (prev_link || verbose) {
2904 netif_carrier_off(dev);
2905 if (netif_msg_link(lp))
2906 printk(KERN_INFO "%s: link down\n", dev->name);
2907 }
2908 if (lp->phycount > 1) {
2909 curr_link = pcnet32_check_otherphy(dev);
2910 prev_link = 0;
2911 }
2912 } else if (verbose || !prev_link) {
2913 netif_carrier_on(dev);
2914 if (lp->mii) {
2915 if (netif_msg_link(lp)) {
2916 struct ethtool_cmd ecmd;
2917 mii_ethtool_gset(&lp->mii_if, &ecmd);
2918 printk(KERN_INFO
2919 "%s: link up, %sMbps, %s-duplex\n",
2920 dev->name,
2921 (ecmd.speed == SPEED_100) ? "100" : "10",
2922 (ecmd.duplex ==
2923 DUPLEX_FULL) ? "full" : "half");
2924 }
2925 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2926 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2927 if (lp->mii_if.full_duplex)
2928 bcr9 |= (1 << 0);
2929 else
2930 bcr9 &= ~(1 << 0);
2931 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2932 }
2933 } else {
2934 if (netif_msg_link(lp))
2935 printk(KERN_INFO "%s: link up\n", dev->name);
2936 }
ac62ef04 2937 }
ac62ef04
DF		 2938}
2939
2940/*
2941 * Check for loss of link and link establishment.
2942 * Can not use mii_check_media because it does nothing if mode is forced.
2943 */
2944
1da177e4
LT		 2945static void pcnet32_watchdog(struct net_device *dev)
2946{
1e56a4b4 2947 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2948 unsigned long flags;
1da177e4 2949
4a5e8e29
JG		 2950 /* Print the link status if it has changed */
2951 spin_lock_irqsave(&lp->lock, flags);
2952 pcnet32_check_media(dev, 0);
2953 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2954
4a5e8e29 2955 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1da177e4
LT		 2956}
2957
2958static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2959{
4a5e8e29
JG		 2960 struct net_device *dev = pci_get_drvdata(pdev);
2961
2962 if (dev) {
1e56a4b4 2963 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2964
2965 unregister_netdev(dev);
2966 pcnet32_free_ring(dev);
2967 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
6ecb7667
DF		 2968 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2969 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2970 free_netdev(dev);
2971 pci_disable_device(pdev);
2972 pci_set_drvdata(pdev, NULL);
2973 }
1da177e4
LT		 2974}
2975
2976static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2977 .name = DRV_NAME,
2978 .probe = pcnet32_probe_pci,
2979 .remove = __devexit_p(pcnet32_remove_one),
2980 .id_table = pcnet32_pci_tbl,
1da177e4
LT		 2981};
2982
2983/* An additional parameter that may be passed in... */
2984static int debug = -1;
2985static int tx_start_pt = -1;
2986static int pcnet32_have_pci;
2987
2988module_param(debug, int, 0);
2989MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2990module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2991MODULE_PARM_DESC(max_interrupt_work,
2992 DRV_NAME " maximum events handled per interrupt");
1da177e4 2993module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2994MODULE_PARM_DESC(rx_copybreak,
2995 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2996module_param(tx_start_pt, int, 0);
2997MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2998module_param(pcnet32vlb, int, 0);
2999MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
3000module_param_array(options, int, NULL, 0);
3001MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
3002module_param_array(full_duplex, int, NULL, 0);
3003MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
3004/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3005module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 3006MODULE_PARM_DESC(homepna,
3007 DRV_NAME
3008 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 3009
3010MODULE_AUTHOR("Thomas Bogendoerfer");
3011MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3012MODULE_LICENSE("GPL");
3013
3014#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3015
3016static int __init pcnet32_init_module(void)
3017{
4a5e8e29 3018 printk(KERN_INFO "%s", version);
1da177e4 3019
4a5e8e29 3020 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 3021
4a5e8e29
JG		 3022 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3023 tx_start = tx_start_pt;
1da177e4 3024
4a5e8e29 3025 /* find the PCI devices */
29917620 3026 if (!pci_register_driver(&pcnet32_driver))
4a5e8e29 3027 pcnet32_have_pci = 1;
1da177e4 3028
4a5e8e29
JG		 3029 /* should we find any remaining VLbus devices ? */
3030 if (pcnet32vlb)
dcaf9769 3031 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 3032
4a5e8e29
JG		 3033 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3034 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1da177e4 3035
4a5e8e29 3036 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 3037}
3038
3039static void __exit pcnet32_cleanup_module(void)
3040{
4a5e8e29
JG		 3041 struct net_device *next_dev;
3042
3043 while (pcnet32_dev) {
1e56a4b4 3044 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
4a5e8e29
JG		 3045 next_dev = lp->next;
3046 unregister_netdev(pcnet32_dev);
3047 pcnet32_free_ring(pcnet32_dev);
3048 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
6ecb7667
DF		 3049 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3050 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 3051 free_netdev(pcnet32_dev);
3052 pcnet32_dev = next_dev;
3053 }
1da177e4 3054
4a5e8e29
JG		 3055 if (pcnet32_have_pci)
3056 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 3057}
3058
3059module_init(pcnet32_init_module);
3060module_exit(pcnet32_cleanup_module);
3061
3062/*
3063 * Local variables:
3064 * c-indent-level: 4
3065 * tab-width: 8
3066 * End:
3067 */
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