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[PATCH] pcnet32: magic number cleanup
[mirror_ubuntu-artful-kernel.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24#define DRV_NAME "pcnet32"
ac62ef04
DF		 25#define DRV_VERSION "1.32"
26#define DRV_RELDATE "18.Mar.2006"
1da177e4
LT		 27#define PFX DRV_NAME ": "
28
4a5e8e29
JG		 29static const char *const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 31
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/string.h>
35#include <linux/errno.h>
36#include <linux/ioport.h>
37#include <linux/slab.h>
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41#include <linux/init.h>
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/crc32.h>
45#include <linux/netdevice.h>
46#include <linux/etherdevice.h>
47#include <linux/skbuff.h>
48#include <linux/spinlock.h>
49#include <linux/moduleparam.h>
50#include <linux/bitops.h>
51
52#include <asm/dma.h>
53#include <asm/io.h>
54#include <asm/uaccess.h>
55#include <asm/irq.h>
56
57/*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60static struct pci_device_id pcnet32_pci_tbl[] = {
f2622a2b
DF		 61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 63
64 /*
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
67 */
f2622a2b
DF		 68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 70
71 { } /* terminate list */
1da177e4
LT		 72};
73
4a5e8e29 74MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 75
76static int cards_found;
77
78/*
79 * VLB I/O addresses
80 */
81static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 82 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4
LT		 83
84static int pcnet32_debug = 0;
4a5e8e29
JG		 85static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 87
88static struct net_device *pcnet32_dev;
89
90static int max_interrupt_work = 2;
91static int rx_copybreak = 200;
92
93#define PCNET32_PORT_AUI 0x00
94#define PCNET32_PORT_10BT 0x01
95#define PCNET32_PORT_GPSI 0x02
96#define PCNET32_PORT_MII 0x03
97
98#define PCNET32_PORT_PORTSEL 0x03
99#define PCNET32_PORT_ASEL 0x04
100#define PCNET32_PORT_100 0x40
101#define PCNET32_PORT_FD 0x80
102
103#define PCNET32_DMA_MASK 0xffffffff
104
105#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108/*
109 * table to translate option values from tulip
110 * to internal options
111 */
f71e1309 112static const unsigned char options_mapping[] = {
4a5e8e29
JG		 113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
129 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 130};
131
132static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 133 "Loopback test (offline)"
1da177e4 134};
4a5e8e29 135
1da177e4
LT		 136#define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
137
ac62ef04 138#define PCNET32_NUM_REGS 136
1da177e4 139
4a5e8e29 140#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 141static int options[MAX_UNITS];
142static int full_duplex[MAX_UNITS];
143static int homepna[MAX_UNITS];
144
145/*
146 * Theory of Operation
147 *
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
153 */
154
1da177e4
LT		 155/*
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
159 */
160#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 161#define PCNET32_LOG_TX_BUFFERS 4
162#define PCNET32_LOG_RX_BUFFERS 5
163#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 165#endif
166
167#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 168#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 169
170#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 171#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4
LT		 172
173#define PKT_BUF_SZ 1544
174
175/* Offsets from base I/O address. */
176#define PCNET32_WIO_RDP 0x10
177#define PCNET32_WIO_RAP 0x12
178#define PCNET32_WIO_RESET 0x14
179#define PCNET32_WIO_BDP 0x16
180
181#define PCNET32_DWIO_RDP 0x10
182#define PCNET32_DWIO_RAP 0x14
183#define PCNET32_DWIO_RESET 0x18
184#define PCNET32_DWIO_BDP 0x1C
185
186#define PCNET32_TOTAL_SIZE 0x20
187
06c87850
DF		 188#define CSR0 0
189#define CSR0_INIT 0x1
190#define CSR0_START 0x2
191#define CSR0_STOP 0x4
192#define CSR0_TXPOLL 0x8
193#define CSR0_INTEN 0x40
194#define CSR0_IDON 0x0100
195#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
196#define PCNET32_INIT_LOW 1
197#define PCNET32_INIT_HIGH 2
198#define CSR3 3
199#define CSR4 4
200#define CSR5 5
201#define CSR5_SUSPEND 0x0001
202#define CSR15 15
203#define PCNET32_MC_FILTER 8
204
8d916266
DF		 205#define PCNET32_79C970A 0x2621
206
1da177e4
LT		 207/* The PCNET32 Rx and Tx ring descriptors. */
208struct pcnet32_rx_head {
0b5bf225 209 u32 base;
b368a3fb 210 s16 buf_length; /* two`s complement of length */
0b5bf225
JG		 211 s16 status;
212 u32 msg_length;
213 u32 reserved;
1da177e4
LT		 214};
215
216struct pcnet32_tx_head {
0b5bf225 217 u32 base;
b368a3fb 218 s16 length; /* two`s complement of length */
0b5bf225
JG		 219 s16 status;
220 u32 misc;
221 u32 reserved;
1da177e4
LT		 222};
223
224/* The PCNET32 32-Bit initialization block, described in databook. */
225struct pcnet32_init_block {
0b5bf225
JG		 226 u16 mode;
227 u16 tlen_rlen;
228 u8 phys_addr[6];
229 u16 reserved;
230 u32 filter[2];
4a5e8e29 231 /* Receive and transmit ring base, along with extra bits. */
0b5bf225
JG		 232 u32 rx_ring;
233 u32 tx_ring;
1da177e4
LT		 234};
235
236/* PCnet32 access functions */
237struct pcnet32_access {
4a5e8e29
JG		 238 u16 (*read_csr) (unsigned long, int);
239 void (*write_csr) (unsigned long, int, u16);
240 u16 (*read_bcr) (unsigned long, int);
241 void (*write_bcr) (unsigned long, int, u16);
242 u16 (*read_rap) (unsigned long);
243 void (*write_rap) (unsigned long, u16);
244 void (*reset) (unsigned long);
1da177e4
LT		 245};
246
247/*
76209926
HWL		 248 * The first field of pcnet32_private is read by the ethernet device
249 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 250 */
251struct pcnet32_private {
4a5e8e29
JG		 252 struct pcnet32_init_block init_block;
253 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 254 struct pcnet32_rx_head *rx_ring;
255 struct pcnet32_tx_head *tx_ring;
256 dma_addr_t dma_addr;/* DMA address of beginning of this
257 object, returned by pci_alloc_consistent */
258 struct pci_dev *pci_dev;
259 const char *name;
4a5e8e29 260 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 261 struct sk_buff **tx_skbuff;
262 struct sk_buff **rx_skbuff;
263 dma_addr_t *tx_dma_addr;
264 dma_addr_t *rx_dma_addr;
265 struct pcnet32_access a;
266 spinlock_t lock; /* Guard lock */
267 unsigned int cur_rx, cur_tx; /* The next free ring entry */
268 unsigned int rx_ring_size; /* current rx ring size */
269 unsigned int tx_ring_size; /* current tx ring size */
270 unsigned int rx_mod_mask; /* rx ring modular mask */
271 unsigned int tx_mod_mask; /* tx ring modular mask */
272 unsigned short rx_len_bits;
273 unsigned short tx_len_bits;
274 dma_addr_t rx_ring_dma_addr;
275 dma_addr_t tx_ring_dma_addr;
276 unsigned int dirty_rx, /* ring entries to be freed. */
277 dirty_tx;
278
279 struct net_device_stats stats;
280 char tx_full;
281 char phycount; /* number of phys found */
282 int options;
283 unsigned int shared_irq:1, /* shared irq possible */
284 dxsuflo:1, /* disable transmit stop on uflo */
285 mii:1; /* mii port available */
286 struct net_device *next;
287 struct mii_if_info mii_if;
288 struct timer_list watchdog_timer;
289 struct timer_list blink_timer;
290 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 291
292 /* each bit indicates an available PHY */
0b5bf225 293 u32 phymask;
8d916266 294 unsigned short chip_version; /* which variant this is */
1da177e4
LT		 295};
296
4a5e8e29
JG		 297static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
298static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
299static int pcnet32_open(struct net_device *);
300static int pcnet32_init_ring(struct net_device *);
301static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
302static int pcnet32_rx(struct net_device *);
303static void pcnet32_tx_timeout(struct net_device *dev);
1da177e4 304static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
4a5e8e29 305static int pcnet32_close(struct net_device *);
1da177e4
LT		 306static struct net_device_stats *pcnet32_get_stats(struct net_device *);
307static void pcnet32_load_multicast(struct net_device *dev);
308static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 309static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 310static void pcnet32_watchdog(struct net_device *);
311static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 312static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
313 int val);
1da177e4
LT		 314static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
315static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 316 struct ethtool_test *eth_test, u64 * data);
317static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 318static int pcnet32_phys_id(struct net_device *dev, u32 data);
319static void pcnet32_led_blink_callback(struct net_device *dev);
320static int pcnet32_get_regs_len(struct net_device *dev);
321static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 322 void *ptr);
1bcd3153 323static void pcnet32_purge_tx_ring(struct net_device *dev);
a88c844c 324static int pcnet32_alloc_ring(struct net_device *dev, char *name);
eabf0415 325static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 326static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 327
4a5e8e29 328static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 329{
4a5e8e29
JG		 330 outw(index, addr + PCNET32_WIO_RAP);
331 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 332}
333
4a5e8e29 334static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 335{
4a5e8e29
JG		 336 outw(index, addr + PCNET32_WIO_RAP);
337 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 338}
339
4a5e8e29 340static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 341{
4a5e8e29
JG		 342 outw(index, addr + PCNET32_WIO_RAP);
343 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 344}
345
4a5e8e29 346static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 347{
4a5e8e29
JG		 348 outw(index, addr + PCNET32_WIO_RAP);
349 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 350}
351
4a5e8e29 352static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 353{
4a5e8e29 354 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 355}
356
4a5e8e29 357static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 358{
4a5e8e29 359 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 360}
361
4a5e8e29 362static void pcnet32_wio_reset(unsigned long addr)
1da177e4 363{
4a5e8e29 364 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 365}
366
4a5e8e29 367static int pcnet32_wio_check(unsigned long addr)
1da177e4 368{
4a5e8e29
JG		 369 outw(88, addr + PCNET32_WIO_RAP);
370 return (inw(addr + PCNET32_WIO_RAP) == 88);
1da177e4
LT		 371}
372
373static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 374 .read_csr = pcnet32_wio_read_csr,
375 .write_csr = pcnet32_wio_write_csr,
376 .read_bcr = pcnet32_wio_read_bcr,
377 .write_bcr = pcnet32_wio_write_bcr,
378 .read_rap = pcnet32_wio_read_rap,
379 .write_rap = pcnet32_wio_write_rap,
380 .reset = pcnet32_wio_reset
1da177e4
LT		 381};
382
4a5e8e29 383static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 384{
4a5e8e29
JG		 385 outl(index, addr + PCNET32_DWIO_RAP);
386 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
1da177e4
LT		 387}
388
4a5e8e29 389static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 390{
4a5e8e29
JG		 391 outl(index, addr + PCNET32_DWIO_RAP);
392 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 393}
394
4a5e8e29 395static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 396{
4a5e8e29
JG		 397 outl(index, addr + PCNET32_DWIO_RAP);
398 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
1da177e4
LT		 399}
400
4a5e8e29 401static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 402{
4a5e8e29
JG		 403 outl(index, addr + PCNET32_DWIO_RAP);
404 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 405}
406
4a5e8e29 407static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 408{
4a5e8e29 409 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
1da177e4
LT		 410}
411
4a5e8e29 412static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 413{
4a5e8e29 414 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 415}
416
4a5e8e29 417static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 418{
4a5e8e29 419 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 420}
421
4a5e8e29 422static int pcnet32_dwio_check(unsigned long addr)
1da177e4 423{
4a5e8e29
JG		 424 outl(88, addr + PCNET32_DWIO_RAP);
425 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
1da177e4
LT		 426}
427
428static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 429 .read_csr = pcnet32_dwio_read_csr,
430 .write_csr = pcnet32_dwio_write_csr,
431 .read_bcr = pcnet32_dwio_read_bcr,
432 .write_bcr = pcnet32_dwio_write_bcr,
433 .read_rap = pcnet32_dwio_read_rap,
434 .write_rap = pcnet32_dwio_write_rap,
435 .reset = pcnet32_dwio_reset
1da177e4
LT		 436};
437
06c87850
DF		 438static void pcnet32_netif_stop(struct net_device *dev)
439{
440 dev->trans_start = jiffies;
441 netif_poll_disable(dev);
442 netif_tx_disable(dev);
443}
444
445static void pcnet32_netif_start(struct net_device *dev)
446{
447 netif_wake_queue(dev);
448 netif_poll_enable(dev);
449}
450
451/*
452 * Allocate space for the new sized tx ring.
453 * Free old resources
454 * Save new resources.
455 * Any failure keeps old resources.
456 * Must be called with lp->lock held.
457 */
458static void pcnet32_realloc_tx_ring(struct net_device *dev,
459 struct pcnet32_private *lp,
460 unsigned int size)
461{
462 dma_addr_t new_ring_dma_addr;
463 dma_addr_t *new_dma_addr_list;
464 struct pcnet32_tx_head *new_tx_ring;
465 struct sk_buff **new_skb_list;
466
467 pcnet32_purge_tx_ring(dev);
468
469 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
470 sizeof(struct pcnet32_tx_head) *
471 (1 << size),
472 &new_ring_dma_addr);
473 if (new_tx_ring == NULL) {
474 if (netif_msg_drv(lp))
475 printk("\n" KERN_ERR
476 "%s: Consistent memory allocation failed.\n",
477 dev->name);
478 return;
479 }
480 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
481
482 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
483 GFP_ATOMIC);
484 if (!new_dma_addr_list) {
485 if (netif_msg_drv(lp))
486 printk("\n" KERN_ERR
487 "%s: Memory allocation failed.\n", dev->name);
488 goto free_new_tx_ring;
489 }
490
491 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
492 GFP_ATOMIC);
493 if (!new_skb_list) {
494 if (netif_msg_drv(lp))
495 printk("\n" KERN_ERR
496 "%s: Memory allocation failed.\n", dev->name);
497 goto free_new_lists;
498 }
499
500 kfree(lp->tx_skbuff);
501 kfree(lp->tx_dma_addr);
502 pci_free_consistent(lp->pci_dev,
503 sizeof(struct pcnet32_tx_head) *
504 lp->tx_ring_size, lp->tx_ring,
505 lp->tx_ring_dma_addr);
506
507 lp->tx_ring_size = (1 << size);
508 lp->tx_mod_mask = lp->tx_ring_size - 1;
509 lp->tx_len_bits = (size << 12);
510 lp->tx_ring = new_tx_ring;
511 lp->tx_ring_dma_addr = new_ring_dma_addr;
512 lp->tx_dma_addr = new_dma_addr_list;
513 lp->tx_skbuff = new_skb_list;
514 return;
515
516 free_new_lists:
517 kfree(new_dma_addr_list);
518 free_new_tx_ring:
519 pci_free_consistent(lp->pci_dev,
520 sizeof(struct pcnet32_tx_head) *
521 (1 << size),
522 new_tx_ring,
523 new_ring_dma_addr);
524 return;
525}
526
527/*
528 * Allocate space for the new sized rx ring.
529 * Re-use old receive buffers.
530 * alloc extra buffers
531 * free unneeded buffers
532 * free unneeded buffers
533 * Save new resources.
534 * Any failure keeps old resources.
535 * Must be called with lp->lock held.
536 */
537static void pcnet32_realloc_rx_ring(struct net_device *dev,
538 struct pcnet32_private *lp,
539 unsigned int size)
540{
541 dma_addr_t new_ring_dma_addr;
542 dma_addr_t *new_dma_addr_list;
543 struct pcnet32_rx_head *new_rx_ring;
544 struct sk_buff **new_skb_list;
545 int new, overlap;
546
547 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
548 sizeof(struct pcnet32_rx_head) *
549 (1 << size),
550 &new_ring_dma_addr);
551 if (new_rx_ring == NULL) {
552 if (netif_msg_drv(lp))
553 printk("\n" KERN_ERR
554 "%s: Consistent memory allocation failed.\n",
555 dev->name);
556 return;
557 }
558 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
559
560 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
561 GFP_ATOMIC);
562 if (!new_dma_addr_list) {
563 if (netif_msg_drv(lp))
564 printk("\n" KERN_ERR
565 "%s: Memory allocation failed.\n", dev->name);
566 goto free_new_rx_ring;
567 }
568
569 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
570 GFP_ATOMIC);
571 if (!new_skb_list) {
572 if (netif_msg_drv(lp))
573 printk("\n" KERN_ERR
574 "%s: Memory allocation failed.\n", dev->name);
575 goto free_new_lists;
576 }
577
578 /* first copy the current receive buffers */
579 overlap = min(size, lp->rx_ring_size);
580 for (new = 0; new < overlap; new++) {
581 new_rx_ring[new] = lp->rx_ring[new];
582 new_dma_addr_list[new] = lp->rx_dma_addr[new];
583 new_skb_list[new] = lp->rx_skbuff[new];
584 }
585 /* now allocate any new buffers needed */
586 for (; new < size; new++ ) {
587 struct sk_buff *rx_skbuff;
588 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
589 if (!(rx_skbuff = new_skb_list[new])) {
590 /* keep the original lists and buffers */
591 if (netif_msg_drv(lp))
592 printk(KERN_ERR
593 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
594 dev->name);
595 goto free_all_new;
596 }
597 skb_reserve(rx_skbuff, 2);
598
599 new_dma_addr_list[new] =
600 pci_map_single(lp->pci_dev, rx_skbuff->data,
601 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
602 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
603 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
604 new_rx_ring[new].status = le16_to_cpu(0x8000);
605 }
606 /* and free any unneeded buffers */
607 for (; new < lp->rx_ring_size; new++) {
608 if (lp->rx_skbuff[new]) {
609 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
610 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
611 dev_kfree_skb(lp->rx_skbuff[new]);
612 }
613 }
614
615 kfree(lp->rx_skbuff);
616 kfree(lp->rx_dma_addr);
617 pci_free_consistent(lp->pci_dev,
618 sizeof(struct pcnet32_rx_head) *
619 lp->rx_ring_size, lp->rx_ring,
620 lp->rx_ring_dma_addr);
621
622 lp->rx_ring_size = (1 << size);
623 lp->rx_mod_mask = lp->rx_ring_size - 1;
624 lp->rx_len_bits = (size << 4);
625 lp->rx_ring = new_rx_ring;
626 lp->rx_ring_dma_addr = new_ring_dma_addr;
627 lp->rx_dma_addr = new_dma_addr_list;
628 lp->rx_skbuff = new_skb_list;
629 return;
630
631 free_all_new:
632 for (; --new >= lp->rx_ring_size; ) {
633 if (new_skb_list[new]) {
634 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
635 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
636 dev_kfree_skb(new_skb_list[new]);
637 }
638 }
639 kfree(new_skb_list);
640 free_new_lists:
641 kfree(new_dma_addr_list);
642 free_new_rx_ring:
643 pci_free_consistent(lp->pci_dev,
644 sizeof(struct pcnet32_rx_head) *
645 (1 << size),
646 new_rx_ring,
647 new_ring_dma_addr);
648 return;
649}
650
ac5bfe40
DF		 651static void pcnet32_purge_rx_ring(struct net_device *dev)
652{
653 struct pcnet32_private *lp = dev->priv;
654 int i;
655
656 /* free all allocated skbuffs */
657 for (i = 0; i < lp->rx_ring_size; i++) {
658 lp->rx_ring[i].status = 0; /* CPU owns buffer */
659 wmb(); /* Make sure adapter sees owner change */
660 if (lp->rx_skbuff[i]) {
661 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
662 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
663 dev_kfree_skb_any(lp->rx_skbuff[i]);
664 }
665 lp->rx_skbuff[i] = NULL;
666 lp->rx_dma_addr[i] = 0;
667 }
668}
669
1da177e4
LT		 670#ifdef CONFIG_NET_POLL_CONTROLLER
671static void pcnet32_poll_controller(struct net_device *dev)
672{
4a5e8e29
JG		 673 disable_irq(dev->irq);
674 pcnet32_interrupt(0, dev, NULL);
675 enable_irq(dev->irq);
1da177e4
LT		 676}
677#endif
678
1da177e4
LT		 679static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
680{
4a5e8e29
JG		 681 struct pcnet32_private *lp = dev->priv;
682 unsigned long flags;
683 int r = -EOPNOTSUPP;
1da177e4 684
4a5e8e29
JG		 685 if (lp->mii) {
686 spin_lock_irqsave(&lp->lock, flags);
687 mii_ethtool_gset(&lp->mii_if, cmd);
688 spin_unlock_irqrestore(&lp->lock, flags);
689 r = 0;
690 }
691 return r;
1da177e4
LT		 692}
693
694static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
695{
4a5e8e29
JG		 696 struct pcnet32_private *lp = dev->priv;
697 unsigned long flags;
698 int r = -EOPNOTSUPP;
1da177e4 699
4a5e8e29
JG		 700 if (lp->mii) {
701 spin_lock_irqsave(&lp->lock, flags);
702 r = mii_ethtool_sset(&lp->mii_if, cmd);
703 spin_unlock_irqrestore(&lp->lock, flags);
704 }
705 return r;
1da177e4
LT		 706}
707
4a5e8e29
JG		 708static void pcnet32_get_drvinfo(struct net_device *dev,
709 struct ethtool_drvinfo *info)
1da177e4 710{
4a5e8e29
JG		 711 struct pcnet32_private *lp = dev->priv;
712
713 strcpy(info->driver, DRV_NAME);
714 strcpy(info->version, DRV_VERSION);
715 if (lp->pci_dev)
716 strcpy(info->bus_info, pci_name(lp->pci_dev));
717 else
718 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 719}
720
721static u32 pcnet32_get_link(struct net_device *dev)
722{
4a5e8e29
JG		 723 struct pcnet32_private *lp = dev->priv;
724 unsigned long flags;
725 int r;
1da177e4 726
4a5e8e29
JG		 727 spin_lock_irqsave(&lp->lock, flags);
728 if (lp->mii) {
729 r = mii_link_ok(&lp->mii_if);
8d916266 730 } else if (lp->chip_version >= PCNET32_79C970A) {
4a5e8e29
JG		 731 ulong ioaddr = dev->base_addr; /* card base I/O address */
732 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
8d916266
DF		 733 } else { /* can not detect link on really old chips */
734 r = 1;
4a5e8e29
JG		 735 }
736 spin_unlock_irqrestore(&lp->lock, flags);
737
738 return r;
1da177e4
LT		 739}
740
741static u32 pcnet32_get_msglevel(struct net_device *dev)
742{
4a5e8e29
JG		 743 struct pcnet32_private *lp = dev->priv;
744 return lp->msg_enable;
1da177e4
LT		 745}
746
747static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
748{
4a5e8e29
JG		 749 struct pcnet32_private *lp = dev->priv;
750 lp->msg_enable = value;
1da177e4
LT		 751}
752
753static int pcnet32_nway_reset(struct net_device *dev)
754{
4a5e8e29
JG		 755 struct pcnet32_private *lp = dev->priv;
756 unsigned long flags;
757 int r = -EOPNOTSUPP;
1da177e4 758
4a5e8e29
JG		 759 if (lp->mii) {
760 spin_lock_irqsave(&lp->lock, flags);
761 r = mii_nway_restart(&lp->mii_if);
762 spin_unlock_irqrestore(&lp->lock, flags);
763 }
764 return r;
1da177e4
LT		 765}
766
4a5e8e29
JG		 767static void pcnet32_get_ringparam(struct net_device *dev,
768 struct ethtool_ringparam *ering)
1da177e4 769{
4a5e8e29 770 struct pcnet32_private *lp = dev->priv;
1da177e4 771
6dcd60c2
DF		 772 ering->tx_max_pending = TX_MAX_RING_SIZE;
773 ering->tx_pending = lp->tx_ring_size;
774 ering->rx_max_pending = RX_MAX_RING_SIZE;
775 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 776}
777
4a5e8e29
JG		 778static int pcnet32_set_ringparam(struct net_device *dev,
779 struct ethtool_ringparam *ering)
eabf0415 780{
4a5e8e29
JG		 781 struct pcnet32_private *lp = dev->priv;
782 unsigned long flags;
06c87850
DF		 783 unsigned int size;
784 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 785 int i;
786
787 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
788 return -EINVAL;
789
790 if (netif_running(dev))
06c87850 791 pcnet32_netif_stop(dev);
4a5e8e29
JG		 792
793 spin_lock_irqsave(&lp->lock, flags);
06c87850
DF		 794 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
795
796 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 797
798 /* set the minimum ring size to 4, to allow the loopback test to work
799 * unchanged.
800 */
801 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 802 if (size <= (1 << i))
4a5e8e29
JG		 803 break;
804 }
06c87850
DF		 805 if ((1 << i) != lp->tx_ring_size)
806 pcnet32_realloc_tx_ring(dev, lp, i);
b368a3fb 807
06c87850 808 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 809 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 810 if (size <= (1 << i))
4a5e8e29
JG		 811 break;
812 }
06c87850
DF		 813 if ((1 << i) != lp->rx_ring_size)
814 pcnet32_realloc_rx_ring(dev, lp, i);
b368a3fb 815
06c87850
DF		 816 dev->weight = lp->rx_ring_size / 2;
817
818 if (netif_running(dev)) {
819 pcnet32_netif_start(dev);
820 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 821 }
eabf0415 822
4a5e8e29 823 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 824
06c87850
DF		 825 if (netif_msg_drv(lp))
826 printk(KERN_INFO
4a5e8e29
JG		 827 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
828 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 829
4a5e8e29 830 return 0;
1da177e4
LT		 831}
832
4a5e8e29
JG		 833static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
834 u8 * data)
1da177e4 835{
4a5e8e29 836 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 837}
838
839static int pcnet32_self_test_count(struct net_device *dev)
840{
4a5e8e29 841 return PCNET32_TEST_LEN;
1da177e4
LT		 842}
843
844static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 845 struct ethtool_test *test, u64 * data)
1da177e4 846{
4a5e8e29
JG		 847 struct pcnet32_private *lp = dev->priv;
848 int rc;
849
850 if (test->flags == ETH_TEST_FL_OFFLINE) {
851 rc = pcnet32_loopback_test(dev, data);
852 if (rc) {
853 if (netif_msg_hw(lp))
854 printk(KERN_DEBUG "%s: Loopback test failed.\n",
855 dev->name);
856 test->flags |= ETH_TEST_FL_FAILED;
857 } else if (netif_msg_hw(lp))
858 printk(KERN_DEBUG "%s: Loopback test passed.\n",
859 dev->name);
1da177e4 860 } else if (netif_msg_hw(lp))
4a5e8e29
JG		 861 printk(KERN_DEBUG
862 "%s: No tests to run (specify 'Offline' on ethtool).",
863 dev->name);
864} /* end pcnet32_ethtool_test */
1da177e4 865
4a5e8e29 866static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 867{
4a5e8e29
JG		 868 struct pcnet32_private *lp = dev->priv;
869 struct pcnet32_access *a = &lp->a; /* access to registers */
870 ulong ioaddr = dev->base_addr; /* card base I/O address */
871 struct sk_buff *skb; /* sk buff */
872 int x, i; /* counters */
873 int numbuffs = 4; /* number of TX/RX buffers and descs */
874 u16 status = 0x8300; /* TX ring status */
875 u16 teststatus; /* test of ring status */
876 int rc; /* return code */
877 int size; /* size of packets */
878 unsigned char *packet; /* source packet data */
879 static const int data_len = 60; /* length of source packets */
880 unsigned long flags;
881 unsigned long ticks;
882
4a5e8e29
JG		 883 rc = 1; /* default to fail */
884
885 if (netif_running(dev))
886 pcnet32_close(dev);
887
888 spin_lock_irqsave(&lp->lock, flags);
ac5bfe40
DF		 889 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
890
891 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
4a5e8e29
JG		 892
893 /* Reset the PCNET32 */
894 lp->a.reset(ioaddr);
b368a3fb 895 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
4a5e8e29
JG		 896
897 /* switch pcnet32 to 32bit mode */
898 lp->a.write_bcr(ioaddr, 20, 2);
899
4a5e8e29
JG		 900 /* purge & init rings but don't actually restart */
901 pcnet32_restart(dev, 0x0000);
902
ac5bfe40 903 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 904
905 /* Initialize Transmit buffers. */
906 size = data_len + 15;
907 for (x = 0; x < numbuffs; x++) {
908 if (!(skb = dev_alloc_skb(size))) {
909 if (netif_msg_hw(lp))
910 printk(KERN_DEBUG
911 "%s: Cannot allocate skb at line: %d!\n",
912 dev->name, __LINE__);
913 goto clean_up;
914 } else {
915 packet = skb->data;
916 skb_put(skb, size); /* create space for data */
917 lp->tx_skbuff[x] = skb;
918 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
919 lp->tx_ring[x].misc = 0;
920
921 /* put DA and SA into the skb */
922 for (i = 0; i < 6; i++)
923 *packet++ = dev->dev_addr[i];
924 for (i = 0; i < 6; i++)
925 *packet++ = dev->dev_addr[i];
926 /* type */
927 *packet++ = 0x08;
928 *packet++ = 0x06;
929 /* packet number */
930 *packet++ = x;
931 /* fill packet with data */
932 for (i = 0; i < data_len; i++)
933 *packet++ = i;
934
935 lp->tx_dma_addr[x] =
936 pci_map_single(lp->pci_dev, skb->data, skb->len,
937 PCI_DMA_TODEVICE);
938 lp->tx_ring[x].base =
939 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
940 wmb(); /* Make sure owner changes after all others are visible */
941 lp->tx_ring[x].status = le16_to_cpu(status);
942 }
1da177e4 943 }
1da177e4 944
ac5bfe40
DF		 945 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
946 a->write_bcr(ioaddr, 32, x | 0x0002);
4a5e8e29 947
ac5bfe40
DF		 948 /* set int loopback in CSR15 */
949 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
950 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
4a5e8e29
JG		 951
952 teststatus = le16_to_cpu(0x8000);
ac5bfe40 953 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
4a5e8e29
JG		 954
955 /* Check status of descriptors */
956 for (x = 0; x < numbuffs; x++) {
957 ticks = 0;
958 rmb();
959 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
960 spin_unlock_irqrestore(&lp->lock, flags);
ac5bfe40 961 msleep(1);
4a5e8e29
JG		 962 spin_lock_irqsave(&lp->lock, flags);
963 rmb();
964 ticks++;
965 }
966 if (ticks == 200) {
967 if (netif_msg_hw(lp))
968 printk("%s: Desc %d failed to reset!\n",
969 dev->name, x);
970 break;
971 }
972 }
973
ac5bfe40 974 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 975 wmb();
976 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
977 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
978
979 for (x = 0; x < numbuffs; x++) {
980 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
981 skb = lp->rx_skbuff[x];
982 for (i = 0; i < size; i++) {
983 printk("%02x ", *(skb->data + i));
984 }
985 printk("\n");
986 }
987 }
1da177e4 988
4a5e8e29
JG		 989 x = 0;
990 rc = 0;
991 while (x < numbuffs && !rc) {
992 skb = lp->rx_skbuff[x];
993 packet = lp->tx_skbuff[x]->data;
994 for (i = 0; i < size; i++) {
995 if (*(skb->data + i) != packet[i]) {
996 if (netif_msg_hw(lp))
997 printk(KERN_DEBUG
998 "%s: Error in compare! %2x - %02x %02x\n",
999 dev->name, i, *(skb->data + i),
1000 packet[i]);
1001 rc = 1;
1002 break;
1003 }
1004 }
1005 x++;
1006 }
1da177e4 1007
4a5e8e29 1008 clean_up:
ac5bfe40 1009 *data1 = rc;
4a5e8e29 1010 pcnet32_purge_tx_ring(dev);
1da177e4 1011
ac5bfe40
DF		 1012 x = a->read_csr(ioaddr, CSR15);
1013 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 1014
ac5bfe40
DF		 1015 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1016 a->write_bcr(ioaddr, 32, (x & ~0x0002));
4a5e8e29
JG		 1017
1018 if (netif_running(dev)) {
ac5bfe40 1019 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29
JG		 1020 pcnet32_open(dev);
1021 } else {
ac5bfe40 1022 pcnet32_purge_rx_ring(dev);
4a5e8e29 1023 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
ac5bfe40 1024 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29
JG		 1025 }
1026
1027 return (rc);
1028} /* end pcnet32_loopback_test */
1da177e4
LT		 1029
1030static void pcnet32_led_blink_callback(struct net_device *dev)
1031{
4a5e8e29
JG		 1032 struct pcnet32_private *lp = dev->priv;
1033 struct pcnet32_access *a = &lp->a;
1034 ulong ioaddr = dev->base_addr;
1035 unsigned long flags;
1036 int i;
1037
1038 spin_lock_irqsave(&lp->lock, flags);
1039 for (i = 4; i < 8; i++) {
1040 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1041 }
1042 spin_unlock_irqrestore(&lp->lock, flags);
1043
1044 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 1045}
1046
1047static int pcnet32_phys_id(struct net_device *dev, u32 data)
1048{
4a5e8e29
JG		 1049 struct pcnet32_private *lp = dev->priv;
1050 struct pcnet32_access *a = &lp->a;
1051 ulong ioaddr = dev->base_addr;
1052 unsigned long flags;
1053 int i, regs[4];
1054
1055 if (!lp->blink_timer.function) {
1056 init_timer(&lp->blink_timer);
1057 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1058 lp->blink_timer.data = (unsigned long)dev;
1059 }
1060
1061 /* Save the current value of the bcrs */
1062 spin_lock_irqsave(&lp->lock, flags);
1063 for (i = 4; i < 8; i++) {
1064 regs[i - 4] = a->read_bcr(ioaddr, i);
1065 }
1066 spin_unlock_irqrestore(&lp->lock, flags);
1067
1068 mod_timer(&lp->blink_timer, jiffies);
1069 set_current_state(TASK_INTERRUPTIBLE);
1070
1071 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1072 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1073
1074 msleep_interruptible(data * 1000);
1075 del_timer_sync(&lp->blink_timer);
1076
1077 /* Restore the original value of the bcrs */
1078 spin_lock_irqsave(&lp->lock, flags);
1079 for (i = 4; i < 8; i++) {
1080 a->write_bcr(ioaddr, i, regs[i - 4]);
1081 }
1082 spin_unlock_irqrestore(&lp->lock, flags);
1083
1084 return 0;
1da177e4
LT		 1085}
1086
df27f4a6
DF		 1087/*
1088 * lp->lock must be held.
1089 */
1090static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1091 int can_sleep)
1092{
1093 int csr5;
1094 struct pcnet32_private *lp = dev->priv;
1095 struct pcnet32_access *a = &lp->a;
1096 ulong ioaddr = dev->base_addr;
1097 int ticks;
1098
8d916266
DF		 1099 /* really old chips have to be stopped. */
1100 if (lp->chip_version < PCNET32_79C970A)
1101 return 0;
1102
df27f4a6
DF		 1103 /* set SUSPEND (SPND) - CSR5 bit 0 */
1104 csr5 = a->read_csr(ioaddr, CSR5);
1105 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1106
1107 /* poll waiting for bit to be set */
1108 ticks = 0;
1109 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1110 spin_unlock_irqrestore(&lp->lock, *flags);
1111 if (can_sleep)
1112 msleep(1);
1113 else
1114 mdelay(1);
1115 spin_lock_irqsave(&lp->lock, *flags);
1116 ticks++;
1117 if (ticks > 200) {
1118 if (netif_msg_hw(lp))
1119 printk(KERN_DEBUG
1120 "%s: Error getting into suspend!\n",
1121 dev->name);
1122 return 0;
1123 }
1124 }
1125 return 1;
1126}
1127
ac62ef04
DF		 1128#define PCNET32_REGS_PER_PHY 32
1129#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1130static int pcnet32_get_regs_len(struct net_device *dev)
1131{
4a5e8e29
JG		 1132 struct pcnet32_private *lp = dev->priv;
1133 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1134
4a5e8e29 1135 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1da177e4
LT		 1136}
1137
1138static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1139 void *ptr)
1da177e4 1140{
4a5e8e29
JG		 1141 int i, csr0;
1142 u16 *buff = ptr;
1143 struct pcnet32_private *lp = dev->priv;
1144 struct pcnet32_access *a = &lp->a;
1145 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1146 unsigned long flags;
1147
1148 spin_lock_irqsave(&lp->lock, flags);
1149
df27f4a6
DF		 1150 csr0 = a->read_csr(ioaddr, CSR0);
1151 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1152 pcnet32_suspend(dev, &flags, 1);
1da177e4 1153
4a5e8e29
JG		 1154 /* read address PROM */
1155 for (i = 0; i < 16; i += 2)
1156 *buff++ = inw(ioaddr + i);
1157
1158 /* read control and status registers */
1159 for (i = 0; i < 90; i++) {
1160 *buff++ = a->read_csr(ioaddr, i);
1161 }
1162
1163 *buff++ = a->read_csr(ioaddr, 112);
1164 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1165
4a5e8e29
JG		 1166 /* read bus configuration registers */
1167 for (i = 0; i < 30; i++) {
1168 *buff++ = a->read_bcr(ioaddr, i);
1169 }
1170 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1171 for (i = 31; i < 36; i++) {
1172 *buff++ = a->read_bcr(ioaddr, i);
1173 }
1174
1175 /* read mii phy registers */
1176 if (lp->mii) {
1177 int j;
1178 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1179 if (lp->phymask & (1 << j)) {
1180 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1181 lp->a.write_bcr(ioaddr, 33,
1182 (j << 5) | i);
1183 *buff++ = lp->a.read_bcr(ioaddr, 34);
1184 }
1185 }
1186 }
1187 }
1188
df27f4a6
DF		 1189 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1190 int csr5;
1191
4a5e8e29 1192 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1193 csr5 = a->read_csr(ioaddr, CSR5);
1194 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1195 }
1196
1197 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1198}
1199
1200static struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1201 .get_settings = pcnet32_get_settings,
1202 .set_settings = pcnet32_set_settings,
1203 .get_drvinfo = pcnet32_get_drvinfo,
1204 .get_msglevel = pcnet32_get_msglevel,
1205 .set_msglevel = pcnet32_set_msglevel,
1206 .nway_reset = pcnet32_nway_reset,
1207 .get_link = pcnet32_get_link,
1208 .get_ringparam = pcnet32_get_ringparam,
1209 .set_ringparam = pcnet32_set_ringparam,
1210 .get_tx_csum = ethtool_op_get_tx_csum,
1211 .get_sg = ethtool_op_get_sg,
1212 .get_tso = ethtool_op_get_tso,
1213 .get_strings = pcnet32_get_strings,
1214 .self_test_count = pcnet32_self_test_count,
1215 .self_test = pcnet32_ethtool_test,
1216 .phys_id = pcnet32_phys_id,
1217 .get_regs_len = pcnet32_get_regs_len,
1218 .get_regs = pcnet32_get_regs,
1219 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1220};
1221
1222/* only probes for non-PCI devices, the rest are handled by
1223 * pci_register_driver via pcnet32_probe_pci */
1224
dcaf9769 1225static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1226{
4a5e8e29
JG		 1227 unsigned int *port, ioaddr;
1228
1229 /* search for PCnet32 VLB cards at known addresses */
1230 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1231 if (request_region
1232 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1233 /* check if there is really a pcnet chip on that ioaddr */
1234 if ((inb(ioaddr + 14) == 0x57)
1235 && (inb(ioaddr + 15) == 0x57)) {
1236 pcnet32_probe1(ioaddr, 0, NULL);
1237 } else {
1238 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1239 }
1240 }
1241 }
1da177e4
LT		 1242}
1243
1da177e4
LT		 1244static int __devinit
1245pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1246{
4a5e8e29
JG		 1247 unsigned long ioaddr;
1248 int err;
1249
1250 err = pci_enable_device(pdev);
1251 if (err < 0) {
1252 if (pcnet32_debug & NETIF_MSG_PROBE)
1253 printk(KERN_ERR PFX
1254 "failed to enable device -- err=%d\n", err);
1255 return err;
1256 }
1257 pci_set_master(pdev);
1258
1259 ioaddr = pci_resource_start(pdev, 0);
1260 if (!ioaddr) {
1261 if (pcnet32_debug & NETIF_MSG_PROBE)
1262 printk(KERN_ERR PFX
1263 "card has no PCI IO resources, aborting\n");
1264 return -ENODEV;
1265 }
1da177e4 1266
4a5e8e29
JG		 1267 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1268 if (pcnet32_debug & NETIF_MSG_PROBE)
1269 printk(KERN_ERR PFX
1270 "architecture does not support 32bit PCI busmaster DMA\n");
1271 return -ENODEV;
1272 }
1273 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1274 NULL) {
1275 if (pcnet32_debug & NETIF_MSG_PROBE)
1276 printk(KERN_ERR PFX
1277 "io address range already allocated\n");
1278 return -EBUSY;
1279 }
1da177e4 1280
4a5e8e29
JG		 1281 err = pcnet32_probe1(ioaddr, 1, pdev);
1282 if (err < 0) {
1283 pci_disable_device(pdev);
1284 }
1285 return err;
1da177e4
LT		 1286}
1287
1da177e4
LT		 1288/* pcnet32_probe1
1289 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1290 * pdev will be NULL when called from pcnet32_probe_vlbus.
1291 */
1292static int __devinit
1293pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1294{
4a5e8e29
JG		 1295 struct pcnet32_private *lp;
1296 dma_addr_t lp_dma_addr;
1297 int i, media;
1298 int fdx, mii, fset, dxsuflo;
1299 int chip_version;
1300 char *chipname;
1301 struct net_device *dev;
1302 struct pcnet32_access *a = NULL;
1303 u8 promaddr[6];
1304 int ret = -ENODEV;
1305
1306 /* reset the chip */
1307 pcnet32_wio_reset(ioaddr);
1308
1309 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1310 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1311 a = &pcnet32_wio;
1312 } else {
1313 pcnet32_dwio_reset(ioaddr);
1314 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1315 && pcnet32_dwio_check(ioaddr)) {
1316 a = &pcnet32_dwio;
1317 } else
1318 goto err_release_region;
1319 }
1320
1321 chip_version =
1322 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1323 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1324 printk(KERN_INFO " PCnet chip version is %#x.\n",
1325 chip_version);
1326 if ((chip_version & 0xfff) != 0x003) {
1327 if (pcnet32_debug & NETIF_MSG_PROBE)
1328 printk(KERN_INFO PFX "Unsupported chip version.\n");
1329 goto err_release_region;
1330 }
1331
1332 /* initialize variables */
1333 fdx = mii = fset = dxsuflo = 0;
1334 chip_version = (chip_version >> 12) & 0xffff;
1335
1336 switch (chip_version) {
1337 case 0x2420:
1338 chipname = "PCnet/PCI 79C970"; /* PCI */
1339 break;
1340 case 0x2430:
1341 if (shared)
1342 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1343 else
1344 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1345 break;
1346 case 0x2621:
1347 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1348 fdx = 1;
1349 break;
1350 case 0x2623:
1351 chipname = "PCnet/FAST 79C971"; /* PCI */
1352 fdx = 1;
1353 mii = 1;
1354 fset = 1;
1355 break;
1356 case 0x2624:
1357 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1358 fdx = 1;
1359 mii = 1;
1360 fset = 1;
1361 break;
1362 case 0x2625:
1363 chipname = "PCnet/FAST III 79C973"; /* PCI */
1364 fdx = 1;
1365 mii = 1;
1366 break;
1367 case 0x2626:
1368 chipname = "PCnet/Home 79C978"; /* PCI */
1369 fdx = 1;
1370 /*
1371 * This is based on specs published at www.amd.com. This section
1372 * assumes that a card with a 79C978 wants to go into standard
1373 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1374 * and the module option homepna=1 can select this instead.
1375 */
1376 media = a->read_bcr(ioaddr, 49);
1377 media &= ~3; /* default to 10Mb ethernet */
1378 if (cards_found < MAX_UNITS && homepna[cards_found])
1379 media |= 1; /* switch to home wiring mode */
1380 if (pcnet32_debug & NETIF_MSG_PROBE)
1381 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1382 (media & 1) ? "1" : "10");
1383 a->write_bcr(ioaddr, 49, media);
1384 break;
1385 case 0x2627:
1386 chipname = "PCnet/FAST III 79C975"; /* PCI */
1387 fdx = 1;
1388 mii = 1;
1389 break;
1390 case 0x2628:
1391 chipname = "PCnet/PRO 79C976";
1392 fdx = 1;
1393 mii = 1;
1394 break;
1395 default:
1396 if (pcnet32_debug & NETIF_MSG_PROBE)
1397 printk(KERN_INFO PFX
1398 "PCnet version %#x, no PCnet32 chip.\n",
1399 chip_version);
1400 goto err_release_region;
1401 }
1402
1da177e4 1403 /*
4a5e8e29
JG		 1404 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1405 * starting until the packet is loaded. Strike one for reliability, lose
1406 * one for latency - although on PCI this isnt a big loss. Older chips
1407 * have FIFO's smaller than a packet, so you can't do this.
1408 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1409 */
4a5e8e29
JG		 1410
1411 if (fset) {
1412 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1413 a->write_csr(ioaddr, 80,
1414 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1415 dxsuflo = 1;
1416 }
1417
1418 dev = alloc_etherdev(0);
1419 if (!dev) {
1420 if (pcnet32_debug & NETIF_MSG_PROBE)
1421 printk(KERN_ERR PFX "Memory allocation failed.\n");
1422 ret = -ENOMEM;
1423 goto err_release_region;
1424 }
1425 SET_NETDEV_DEV(dev, &pdev->dev);
1426
1da177e4 1427 if (pcnet32_debug & NETIF_MSG_PROBE)
4a5e8e29
JG		 1428 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1429
1430 /* In most chips, after a chip reset, the ethernet address is read from the
1431 * station address PROM at the base address and programmed into the
1432 * "Physical Address Registers" CSR12-14.
1433 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1434 * they disagree with the CSRs. If they miscompare, and the PROM addr
1435 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1436 */
1437 for (i = 0; i < 3; i++) {
1438 unsigned int val;
1439 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1440 /* There may be endianness issues here. */
1441 dev->dev_addr[2 * i] = val & 0x0ff;
1442 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1443 }
1444
1445 /* read PROM address and compare with CSR address */
1da177e4 1446 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1447 promaddr[i] = inb(ioaddr + i);
1448
1449 if (memcmp(promaddr, dev->dev_addr, 6)
1450 || !is_valid_ether_addr(dev->dev_addr)) {
1451 if (is_valid_ether_addr(promaddr)) {
1452 if (pcnet32_debug & NETIF_MSG_PROBE) {
1453 printk(" warning: CSR address invalid,\n");
1454 printk(KERN_INFO
1455 " using instead PROM address of");
1456 }
1457 memcpy(dev->dev_addr, promaddr, 6);
1458 }
1459 }
1460 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1461
1462 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1463 if (!is_valid_ether_addr(dev->perm_addr))
1464 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1465
1466 if (pcnet32_debug & NETIF_MSG_PROBE) {
1467 for (i = 0; i < 6; i++)
1468 printk(" %2.2x", dev->dev_addr[i]);
1469
1470 /* Version 0x2623 and 0x2624 */
1471 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1472 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1473 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1474 switch (i >> 10) {
1475 case 0:
1476 printk(" 20 bytes,");
1477 break;
1478 case 1:
1479 printk(" 64 bytes,");
1480 break;
1481 case 2:
1482 printk(" 128 bytes,");
1483 break;
1484 case 3:
1485 printk("~220 bytes,");
1486 break;
1487 }
1488 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1489 printk(" BCR18(%x):", i & 0xffff);
1490 if (i & (1 << 5))
1491 printk("BurstWrEn ");
1492 if (i & (1 << 6))
1493 printk("BurstRdEn ");
1494 if (i & (1 << 7))
1495 printk("DWordIO ");
1496 if (i & (1 << 11))
1497 printk("NoUFlow ");
1498 i = a->read_bcr(ioaddr, 25);
1499 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1500 i = a->read_bcr(ioaddr, 26);
1501 printk(" SRAM_BND=0x%04x,", i << 8);
1502 i = a->read_bcr(ioaddr, 27);
1503 if (i & (1 << 14))
1504 printk("LowLatRx");
1505 }
1506 }
1507
1508 dev->base_addr = ioaddr;
1509 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1510 if ((lp =
1511 pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1512 if (pcnet32_debug & NETIF_MSG_PROBE)
1513 printk(KERN_ERR PFX
1514 "Consistent memory allocation failed.\n");
1515 ret = -ENOMEM;
1516 goto err_free_netdev;
1517 }
1518
1519 memset(lp, 0, sizeof(*lp));
1520 lp->dma_addr = lp_dma_addr;
1521 lp->pci_dev = pdev;
1522
1523 spin_lock_init(&lp->lock);
1524
1525 SET_MODULE_OWNER(dev);
1526 SET_NETDEV_DEV(dev, &pdev->dev);
1527 dev->priv = lp;
1528 lp->name = chipname;
1529 lp->shared_irq = shared;
1530 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1531 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1532 lp->tx_mod_mask = lp->tx_ring_size - 1;
1533 lp->rx_mod_mask = lp->rx_ring_size - 1;
1534 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1535 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1536 lp->mii_if.full_duplex = fdx;
1537 lp->mii_if.phy_id_mask = 0x1f;
1538 lp->mii_if.reg_num_mask = 0x1f;
1539 lp->dxsuflo = dxsuflo;
1540 lp->mii = mii;
8d916266 1541 lp->chip_version = chip_version;
4a5e8e29
JG		 1542 lp->msg_enable = pcnet32_debug;
1543 if ((cards_found >= MAX_UNITS)
1544 || (options[cards_found] > sizeof(options_mapping)))
1545 lp->options = PCNET32_PORT_ASEL;
1546 else
1547 lp->options = options_mapping[options[cards_found]];
1548 lp->mii_if.dev = dev;
1549 lp->mii_if.mdio_read = mdio_read;
1550 lp->mii_if.mdio_write = mdio_write;
1551
1552 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1553 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1554 lp->options |= PCNET32_PORT_FD;
1555
1556 if (!a) {
1557 if (pcnet32_debug & NETIF_MSG_PROBE)
1558 printk(KERN_ERR PFX "No access methods\n");
1559 ret = -ENODEV;
1560 goto err_free_consistent;
1561 }
1562 lp->a = *a;
1563
1564 /* prior to register_netdev, dev->name is not yet correct */
1565 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1566 ret = -ENOMEM;
1567 goto err_free_ring;
1568 }
1569 /* detect special T1/E1 WAN card by checking for MAC address */
1570 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1da177e4 1571 && dev->dev_addr[2] == 0x75)
4a5e8e29 1572 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1573
4a5e8e29
JG		 1574 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1575 lp->init_block.tlen_rlen =
1576 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1577 for (i = 0; i < 6; i++)
1578 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1579 lp->init_block.filter[0] = 0x00000000;
1580 lp->init_block.filter[1] = 0x00000000;
1581 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1582 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
1583
1584 /* switch pcnet32 to 32bit mode */
1585 a->write_bcr(ioaddr, 20, 2);
1586
1587 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1588 init_block)) & 0xffff);
1589 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1590 init_block)) >> 16);
1591
1592 if (pdev) { /* use the IRQ provided by PCI */
1593 dev->irq = pdev->irq;
1594 if (pcnet32_debug & NETIF_MSG_PROBE)
1595 printk(" assigned IRQ %d.\n", dev->irq);
1596 } else {
1597 unsigned long irq_mask = probe_irq_on();
1598
1599 /*
1600 * To auto-IRQ we enable the initialization-done and DMA error
1601 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1602 * boards will work.
1603 */
1604 /* Trigger an initialization just for the interrupt. */
b368a3fb 1605 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
4a5e8e29
JG		 1606 mdelay(1);
1607
1608 dev->irq = probe_irq_off(irq_mask);
1609 if (!dev->irq) {
1610 if (pcnet32_debug & NETIF_MSG_PROBE)
1611 printk(", failed to detect IRQ line.\n");
1612 ret = -ENODEV;
1613 goto err_free_ring;
1614 }
1615 if (pcnet32_debug & NETIF_MSG_PROBE)
1616 printk(", probed IRQ %d.\n", dev->irq);
1617 }
1da177e4 1618
4a5e8e29
JG		 1619 /* Set the mii phy_id so that we can query the link state */
1620 if (lp->mii) {
1621 /* lp->phycount and lp->phymask are set to 0 by memset above */
1622
1623 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1624 /* scan for PHYs */
1625 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1626 unsigned short id1, id2;
1627
1628 id1 = mdio_read(dev, i, MII_PHYSID1);
1629 if (id1 == 0xffff)
1630 continue;
1631 id2 = mdio_read(dev, i, MII_PHYSID2);
1632 if (id2 == 0xffff)
1633 continue;
1634 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1635 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1636 lp->phycount++;
1637 lp->phymask |= (1 << i);
1638 lp->mii_if.phy_id = i;
1639 if (pcnet32_debug & NETIF_MSG_PROBE)
1640 printk(KERN_INFO PFX
1641 "Found PHY %04x:%04x at address %d.\n",
1642 id1, id2, i);
1643 }
1644 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1645 if (lp->phycount > 1) {
1646 lp->options |= PCNET32_PORT_MII;
1647 }
1da177e4 1648 }
4a5e8e29
JG		 1649
1650 init_timer(&lp->watchdog_timer);
1651 lp->watchdog_timer.data = (unsigned long)dev;
1652 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1653
1654 /* The PCNET32-specific entries in the device structure. */
1655 dev->open = &pcnet32_open;
1656 dev->hard_start_xmit = &pcnet32_start_xmit;
1657 dev->stop = &pcnet32_close;
1658 dev->get_stats = &pcnet32_get_stats;
1659 dev->set_multicast_list = &pcnet32_set_multicast_list;
1660 dev->do_ioctl = &pcnet32_ioctl;
1661 dev->ethtool_ops = &pcnet32_ethtool_ops;
1662 dev->tx_timeout = pcnet32_tx_timeout;
1663 dev->watchdog_timeo = (5 * HZ);
1da177e4
LT		 1664
1665#ifdef CONFIG_NET_POLL_CONTROLLER
4a5e8e29 1666 dev->poll_controller = pcnet32_poll_controller;
1da177e4
LT		 1667#endif
1668
4a5e8e29
JG		 1669 /* Fill in the generic fields of the device structure. */
1670 if (register_netdev(dev))
1671 goto err_free_ring;
1672
1673 if (pdev) {
1674 pci_set_drvdata(pdev, dev);
1675 } else {
1676 lp->next = pcnet32_dev;
1677 pcnet32_dev = dev;
1678 }
1679
1680 if (pcnet32_debug & NETIF_MSG_PROBE)
1681 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1682 cards_found++;
1683
1684 /* enable LED writes */
1685 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1686
4a5e8e29
JG		 1687 return 0;
1688
1689 err_free_ring:
1690 pcnet32_free_ring(dev);
1691 err_free_consistent:
1692 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1693 err_free_netdev:
1694 free_netdev(dev);
1695 err_release_region:
1696 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1697 return ret;
1698}
1da177e4 1699
a88c844c
DF		 1700/* if any allocation fails, caller must also call pcnet32_free_ring */
1701static int pcnet32_alloc_ring(struct net_device *dev, char *name)
eabf0415 1702{
4a5e8e29 1703 struct pcnet32_private *lp = dev->priv;
eabf0415 1704
4a5e8e29
JG		 1705 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1706 sizeof(struct pcnet32_tx_head) *
1707 lp->tx_ring_size,
1708 &lp->tx_ring_dma_addr);
1709 if (lp->tx_ring == NULL) {
12fa30f3 1710 if (netif_msg_drv(lp))
4a5e8e29
JG		 1711 printk("\n" KERN_ERR PFX
1712 "%s: Consistent memory allocation failed.\n",
1713 name);
1714 return -ENOMEM;
1715 }
eabf0415 1716
4a5e8e29
JG		 1717 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1718 sizeof(struct pcnet32_rx_head) *
1719 lp->rx_ring_size,
1720 &lp->rx_ring_dma_addr);
1721 if (lp->rx_ring == NULL) {
12fa30f3 1722 if (netif_msg_drv(lp))
4a5e8e29
JG		 1723 printk("\n" KERN_ERR PFX
1724 "%s: Consistent memory allocation failed.\n",
1725 name);
1726 return -ENOMEM;
1727 }
eabf0415 1728
12fa30f3 1729 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 1730 GFP_ATOMIC);
1731 if (!lp->tx_dma_addr) {
12fa30f3 1732 if (netif_msg_drv(lp))
4a5e8e29
JG		 1733 printk("\n" KERN_ERR PFX
1734 "%s: Memory allocation failed.\n", name);
1735 return -ENOMEM;
1736 }
4a5e8e29 1737
12fa30f3 1738 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 1739 GFP_ATOMIC);
1740 if (!lp->rx_dma_addr) {
12fa30f3 1741 if (netif_msg_drv(lp))
4a5e8e29
JG		 1742 printk("\n" KERN_ERR PFX
1743 "%s: Memory allocation failed.\n", name);
1744 return -ENOMEM;
1745 }
4a5e8e29 1746
12fa30f3 1747 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 1748 GFP_ATOMIC);
1749 if (!lp->tx_skbuff) {
12fa30f3 1750 if (netif_msg_drv(lp))
4a5e8e29
JG		 1751 printk("\n" KERN_ERR PFX
1752 "%s: Memory allocation failed.\n", name);
1753 return -ENOMEM;
1754 }
4a5e8e29 1755
12fa30f3 1756 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 1757 GFP_ATOMIC);
1758 if (!lp->rx_skbuff) {
12fa30f3 1759 if (netif_msg_drv(lp))
4a5e8e29
JG		 1760 printk("\n" KERN_ERR PFX
1761 "%s: Memory allocation failed.\n", name);
1762 return -ENOMEM;
1763 }
4a5e8e29
JG		 1764
1765 return 0;
1766}
eabf0415
HWL		 1767
1768static void pcnet32_free_ring(struct net_device *dev)
1769{
4a5e8e29 1770 struct pcnet32_private *lp = dev->priv;
eabf0415 1771
4a5e8e29
JG		 1772 kfree(lp->tx_skbuff);
1773 lp->tx_skbuff = NULL;
eabf0415 1774
4a5e8e29
JG		 1775 kfree(lp->rx_skbuff);
1776 lp->rx_skbuff = NULL;
eabf0415 1777
4a5e8e29
JG		 1778 kfree(lp->tx_dma_addr);
1779 lp->tx_dma_addr = NULL;
eabf0415 1780
4a5e8e29
JG		 1781 kfree(lp->rx_dma_addr);
1782 lp->rx_dma_addr = NULL;
eabf0415 1783
4a5e8e29
JG		 1784 if (lp->tx_ring) {
1785 pci_free_consistent(lp->pci_dev,
1786 sizeof(struct pcnet32_tx_head) *
1787 lp->tx_ring_size, lp->tx_ring,
1788 lp->tx_ring_dma_addr);
1789 lp->tx_ring = NULL;
1790 }
eabf0415 1791
4a5e8e29
JG		 1792 if (lp->rx_ring) {
1793 pci_free_consistent(lp->pci_dev,
1794 sizeof(struct pcnet32_rx_head) *
1795 lp->rx_ring_size, lp->rx_ring,
1796 lp->rx_ring_dma_addr);
1797 lp->rx_ring = NULL;
1798 }
eabf0415
HWL		 1799}
1800
4a5e8e29 1801static int pcnet32_open(struct net_device *dev)
1da177e4 1802{
4a5e8e29
JG		 1803 struct pcnet32_private *lp = dev->priv;
1804 unsigned long ioaddr = dev->base_addr;
1805 u16 val;
1806 int i;
1807 int rc;
1808 unsigned long flags;
1809
1810 if (request_irq(dev->irq, &pcnet32_interrupt,
1fb9df5d 1811 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 1812 (void *)dev)) {
1813 return -EAGAIN;
1814 }
1815
1816 spin_lock_irqsave(&lp->lock, flags);
1817 /* Check for a valid station address */
1818 if (!is_valid_ether_addr(dev->dev_addr)) {
1819 rc = -EINVAL;
1820 goto err_free_irq;
1821 }
1822
1823 /* Reset the PCNET32 */
1824 lp->a.reset(ioaddr);
1825
1826 /* switch pcnet32 to 32bit mode */
1827 lp->a.write_bcr(ioaddr, 20, 2);
1828
1829 if (netif_msg_ifup(lp))
1830 printk(KERN_DEBUG
1831 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1832 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
1833 (u32) (lp->rx_ring_dma_addr),
1834 (u32) (lp->dma_addr +
1835 offsetof(struct pcnet32_private, init_block)));
1836
1837 /* set/reset autoselect bit */
1838 val = lp->a.read_bcr(ioaddr, 2) & ~2;
1839 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 1840 val |= 2;
4a5e8e29
JG		 1841 lp->a.write_bcr(ioaddr, 2, val);
1842
1843 /* handle full duplex setting */
1844 if (lp->mii_if.full_duplex) {
1845 val = lp->a.read_bcr(ioaddr, 9) & ~3;
1846 if (lp->options & PCNET32_PORT_FD) {
1847 val |= 1;
1848 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
1849 val |= 2;
1850 } else if (lp->options & PCNET32_PORT_ASEL) {
1851 /* workaround of xSeries250, turn on for 79C975 only */
8d916266 1852 if (lp->chip_version == 0x2627)
4a5e8e29
JG		 1853 val |= 3;
1854 }
1855 lp->a.write_bcr(ioaddr, 9, val);
1856 }
1857
1858 /* set/reset GPSI bit in test register */
1859 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
1860 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
1861 val |= 0x10;
1862 lp->a.write_csr(ioaddr, 124, val);
1863
1864 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
1865 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2964bbd7
DF		 1866 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
1867 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 1868 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29
JG		 1869 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
1870 if (netif_msg_link(lp))
1871 printk(KERN_DEBUG
1872 "%s: Setting 100Mb-Full Duplex.\n",
1873 dev->name);
1874 }
1875 }
1876 if (lp->phycount < 2) {
1877 /*
1878 * 24 Jun 2004 according AMD, in order to change the PHY,
1879 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1880 * duplex, and/or enable auto negotiation, and clear DANAS
1881 */
1882 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1883 lp->a.write_bcr(ioaddr, 32,
1884 lp->a.read_bcr(ioaddr, 32) | 0x0080);
1885 /* disable Auto Negotiation, set 10Mpbs, HD */
1886 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
1887 if (lp->options & PCNET32_PORT_FD)
1888 val |= 0x10;
1889 if (lp->options & PCNET32_PORT_100)
1890 val |= 0x08;
1891 lp->a.write_bcr(ioaddr, 32, val);
1892 } else {
1893 if (lp->options & PCNET32_PORT_ASEL) {
1894 lp->a.write_bcr(ioaddr, 32,
1895 lp->a.read_bcr(ioaddr,
1896 32) | 0x0080);
1897 /* enable auto negotiate, setup, disable fd */
1898 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
1899 val |= 0x20;
1900 lp->a.write_bcr(ioaddr, 32, val);
1901 }
1902 }
1903 } else {
1904 int first_phy = -1;
1905 u16 bmcr;
1906 u32 bcr9;
1907 struct ethtool_cmd ecmd;
1908
1909 /*
1910 * There is really no good other way to handle multiple PHYs
1911 * other than turning off all automatics
1912 */
1913 val = lp->a.read_bcr(ioaddr, 2);
1914 lp->a.write_bcr(ioaddr, 2, val & ~2);
1915 val = lp->a.read_bcr(ioaddr, 32);
1916 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
1917
1918 if (!(lp->options & PCNET32_PORT_ASEL)) {
1919 /* setup ecmd */
1920 ecmd.port = PORT_MII;
1921 ecmd.transceiver = XCVR_INTERNAL;
1922 ecmd.autoneg = AUTONEG_DISABLE;
1923 ecmd.speed =
1924 lp->
1925 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
1926 bcr9 = lp->a.read_bcr(ioaddr, 9);
1927
1928 if (lp->options & PCNET32_PORT_FD) {
1929 ecmd.duplex = DUPLEX_FULL;
1930 bcr9 |= (1 << 0);
1931 } else {
1932 ecmd.duplex = DUPLEX_HALF;
1933 bcr9 |= ~(1 << 0);
1934 }
1935 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 1936 }
4a5e8e29
JG		 1937
1938 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1939 if (lp->phymask & (1 << i)) {
1940 /* isolate all but the first PHY */
1941 bmcr = mdio_read(dev, i, MII_BMCR);
1942 if (first_phy == -1) {
1943 first_phy = i;
1944 mdio_write(dev, i, MII_BMCR,
1945 bmcr & ~BMCR_ISOLATE);
1946 } else {
1947 mdio_write(dev, i, MII_BMCR,
1948 bmcr | BMCR_ISOLATE);
1949 }
1950 /* use mii_ethtool_sset to setup PHY */
1951 lp->mii_if.phy_id = i;
1952 ecmd.phy_address = i;
1953 if (lp->options & PCNET32_PORT_ASEL) {
1954 mii_ethtool_gset(&lp->mii_if, &ecmd);
1955 ecmd.autoneg = AUTONEG_ENABLE;
1956 }
1957 mii_ethtool_sset(&lp->mii_if, &ecmd);
1958 }
1959 }
1960 lp->mii_if.phy_id = first_phy;
1961 if (netif_msg_link(lp))
1962 printk(KERN_INFO "%s: Using PHY number %d.\n",
1963 dev->name, first_phy);
1964 }
1da177e4
LT		 1965
1966#ifdef DO_DXSUFLO
4a5e8e29 1967 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
b368a3fb 1968 val = lp->a.read_csr(ioaddr, CSR3);
4a5e8e29 1969 val |= 0x40;
b368a3fb 1970 lp->a.write_csr(ioaddr, CSR3, val);
4a5e8e29 1971 }
1da177e4
LT		 1972#endif
1973
4a5e8e29
JG		 1974 lp->init_block.mode =
1975 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1976 pcnet32_load_multicast(dev);
1977
1978 if (pcnet32_init_ring(dev)) {
1979 rc = -ENOMEM;
1980 goto err_free_ring;
1981 }
1982
1983 /* Re-initialize the PCNET32, and start it when done. */
1984 lp->a.write_csr(ioaddr, 1, (lp->dma_addr +
1985 offsetof(struct pcnet32_private,
1986 init_block)) & 0xffff);
1987 lp->a.write_csr(ioaddr, 2,
1988 (lp->dma_addr +
1989 offsetof(struct pcnet32_private, init_block)) >> 16);
1990
b368a3fb
DF		 1991 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1992 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 1993
1994 netif_start_queue(dev);
1995
8d916266
DF		 1996 if (lp->chip_version >= PCNET32_79C970A) {
1997 /* Print the link status and start the watchdog */
1998 pcnet32_check_media(dev, 1);
1999 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2000 }
4a5e8e29
JG		 2001
2002 i = 0;
2003 while (i++ < 100)
b368a3fb 2004 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29
JG		 2005 break;
2006 /*
2007 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2008 * reports that doing so triggers a bug in the '974.
2009 */
b368a3fb 2010 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
4a5e8e29
JG		 2011
2012 if (netif_msg_ifup(lp))
2013 printk(KERN_DEBUG
2014 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2015 dev->name, i,
2016 (u32) (lp->dma_addr +
2017 offsetof(struct pcnet32_private, init_block)),
b368a3fb 2018 lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2019
2020 spin_unlock_irqrestore(&lp->lock, flags);
2021
2022 return 0; /* Always succeed */
2023
2024 err_free_ring:
2025 /* free any allocated skbuffs */
ac5bfe40 2026 pcnet32_purge_rx_ring(dev);
4a5e8e29 2027
4a5e8e29
JG		 2028 /*
2029 * Switch back to 16bit mode to avoid problems with dumb
2030 * DOS packet driver after a warm reboot
2031 */
2032 lp->a.write_bcr(ioaddr, 20, 4);
2033
2034 err_free_irq:
2035 spin_unlock_irqrestore(&lp->lock, flags);
2036 free_irq(dev->irq, dev);
2037 return rc;
1da177e4
LT		 2038}
2039
2040/*
2041 * The LANCE has been halted for one reason or another (busmaster memory
2042 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2043 * etc.). Modern LANCE variants always reload their ring-buffer
2044 * configuration when restarted, so we must reinitialize our ring
2045 * context before restarting. As part of this reinitialization,
2046 * find all packets still on the Tx ring and pretend that they had been
2047 * sent (in effect, drop the packets on the floor) - the higher-level
2048 * protocols will time out and retransmit. It'd be better to shuffle
2049 * these skbs to a temp list and then actually re-Tx them after
2050 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2051 */
2052
4a5e8e29 2053static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2054{
4a5e8e29
JG		 2055 struct pcnet32_private *lp = dev->priv;
2056 int i;
1da177e4 2057
4a5e8e29
JG		 2058 for (i = 0; i < lp->tx_ring_size; i++) {
2059 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2060 wmb(); /* Make sure adapter sees owner change */
2061 if (lp->tx_skbuff[i]) {
2062 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2063 lp->tx_skbuff[i]->len,
2064 PCI_DMA_TODEVICE);
2065 dev_kfree_skb_any(lp->tx_skbuff[i]);
2066 }
2067 lp->tx_skbuff[i] = NULL;
2068 lp->tx_dma_addr[i] = 0;
2069 }
2070}
1da177e4
LT		 2071
2072/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2073static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2074{
4a5e8e29
JG		 2075 struct pcnet32_private *lp = dev->priv;
2076 int i;
2077
2078 lp->tx_full = 0;
2079 lp->cur_rx = lp->cur_tx = 0;
2080 lp->dirty_rx = lp->dirty_tx = 0;
2081
2082 for (i = 0; i < lp->rx_ring_size; i++) {
2083 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2084 if (rx_skbuff == NULL) {
2085 if (!
2086 (rx_skbuff = lp->rx_skbuff[i] =
2087 dev_alloc_skb(PKT_BUF_SZ))) {
2088 /* there is not much, we can do at this point */
b368a3fb 2089 if (netif_msg_drv(lp))
4a5e8e29
JG		 2090 printk(KERN_ERR
2091 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2092 dev->name);
2093 return -1;
2094 }
2095 skb_reserve(rx_skbuff, 2);
2096 }
2097
2098 rmb();
2099 if (lp->rx_dma_addr[i] == 0)
2100 lp->rx_dma_addr[i] =
2101 pci_map_single(lp->pci_dev, rx_skbuff->data,
2102 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2103 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
2104 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2105 wmb(); /* Make sure owner changes after all others are visible */
2106 lp->rx_ring[i].status = le16_to_cpu(0x8000);
2107 }
2108 /* The Tx buffer address is filled in as needed, but we do need to clear
2109 * the upper ownership bit. */
2110 for (i = 0; i < lp->tx_ring_size; i++) {
2111 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2112 wmb(); /* Make sure adapter sees owner change */
2113 lp->tx_ring[i].base = 0;
2114 lp->tx_dma_addr[i] = 0;
2115 }
2116
2117 lp->init_block.tlen_rlen =
2118 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
2119 for (i = 0; i < 6; i++)
2120 lp->init_block.phys_addr[i] = dev->dev_addr[i];
2121 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
2122 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
2123 wmb(); /* Make sure all changes are visible */
2124 return 0;
1da177e4
LT		 2125}
2126
2127/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2128 * then flush the pending transmit operations, re-initialize the ring,
2129 * and tell the chip to initialize.
2130 */
4a5e8e29 2131static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2132{
4a5e8e29
JG		 2133 struct pcnet32_private *lp = dev->priv;
2134 unsigned long ioaddr = dev->base_addr;
2135 int i;
1da177e4 2136
4a5e8e29
JG		 2137 /* wait for stop */
2138 for (i = 0; i < 100; i++)
b368a3fb 2139 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
4a5e8e29 2140 break;
1da177e4 2141
4a5e8e29
JG		 2142 if (i >= 100 && netif_msg_drv(lp))
2143 printk(KERN_ERR
2144 "%s: pcnet32_restart timed out waiting for stop.\n",
2145 dev->name);
1da177e4 2146
4a5e8e29
JG		 2147 pcnet32_purge_tx_ring(dev);
2148 if (pcnet32_init_ring(dev))
2149 return;
1da177e4 2150
4a5e8e29 2151 /* ReInit Ring */
b368a3fb 2152 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2153 i = 0;
2154 while (i++ < 1000)
b368a3fb 2155 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29 2156 break;
1da177e4 2157
b368a3fb 2158 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
1da177e4
LT		 2159}
2160
4a5e8e29 2161static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2162{
4a5e8e29
JG		 2163 struct pcnet32_private *lp = dev->priv;
2164 unsigned long ioaddr = dev->base_addr, flags;
2165
2166 spin_lock_irqsave(&lp->lock, flags);
2167 /* Transmitter timeout, serious problems. */
2168 if (pcnet32_debug & NETIF_MSG_DRV)
2169 printk(KERN_ERR
2170 "%s: transmit timed out, status %4.4x, resetting.\n",
b368a3fb
DF		 2171 dev->name, lp->a.read_csr(ioaddr, CSR0));
2172 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
4a5e8e29
JG		 2173 lp->stats.tx_errors++;
2174 if (netif_msg_tx_err(lp)) {
2175 int i;
2176 printk(KERN_DEBUG
2177 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2178 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2179 lp->cur_rx);
2180 for (i = 0; i < lp->rx_ring_size; i++)
2181 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2182 le32_to_cpu(lp->rx_ring[i].base),
2183 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2184 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2185 le16_to_cpu(lp->rx_ring[i].status));
2186 for (i = 0; i < lp->tx_ring_size; i++)
2187 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2188 le32_to_cpu(lp->tx_ring[i].base),
2189 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2190 le32_to_cpu(lp->tx_ring[i].misc),
2191 le16_to_cpu(lp->tx_ring[i].status));
2192 printk("\n");
2193 }
b368a3fb 2194 pcnet32_restart(dev, CSR0_NORMAL);
1da177e4 2195
4a5e8e29
JG		 2196 dev->trans_start = jiffies;
2197 netif_wake_queue(dev);
1da177e4 2198
4a5e8e29
JG		 2199 spin_unlock_irqrestore(&lp->lock, flags);
2200}
2201
2202static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 2203{
4a5e8e29
JG		 2204 struct pcnet32_private *lp = dev->priv;
2205 unsigned long ioaddr = dev->base_addr;
2206 u16 status;
2207 int entry;
2208 unsigned long flags;
1da177e4 2209
4a5e8e29 2210 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2211
4a5e8e29
JG		 2212 if (netif_msg_tx_queued(lp)) {
2213 printk(KERN_DEBUG
2214 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
b368a3fb 2215 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2216 }
1da177e4 2217
4a5e8e29
JG		 2218 /* Default status -- will not enable Successful-TxDone
2219 * interrupt when that option is available to us.
2220 */
2221 status = 0x8300;
1da177e4 2222
4a5e8e29 2223 /* Fill in a Tx ring entry */
1da177e4 2224
4a5e8e29
JG		 2225 /* Mask to ring buffer boundary. */
2226 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2227
4a5e8e29
JG		 2228 /* Caution: the write order is important here, set the status
2229 * with the "ownership" bits last. */
1da177e4 2230
4a5e8e29 2231 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1da177e4 2232
4a5e8e29 2233 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2234
4a5e8e29
JG		 2235 lp->tx_skbuff[entry] = skb;
2236 lp->tx_dma_addr[entry] =
2237 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2238 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
2239 wmb(); /* Make sure owner changes after all others are visible */
2240 lp->tx_ring[entry].status = le16_to_cpu(status);
1da177e4 2241
4a5e8e29
JG		 2242 lp->cur_tx++;
2243 lp->stats.tx_bytes += skb->len;
1da177e4 2244
4a5e8e29 2245 /* Trigger an immediate send poll. */
b368a3fb 2246 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
1da177e4 2247
4a5e8e29 2248 dev->trans_start = jiffies;
1da177e4 2249
4a5e8e29
JG		 2250 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2251 lp->tx_full = 1;
2252 netif_stop_queue(dev);
2253 }
2254 spin_unlock_irqrestore(&lp->lock, flags);
2255 return 0;
1da177e4
LT		 2256}
2257
2258/* The PCNET32 interrupt handler. */
2259static irqreturn_t
4a5e8e29 2260pcnet32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1da177e4 2261{
4a5e8e29
JG		 2262 struct net_device *dev = dev_id;
2263 struct pcnet32_private *lp;
2264 unsigned long ioaddr;
5c99346a 2265 u16 csr0;
4a5e8e29
JG		 2266 int boguscnt = max_interrupt_work;
2267 int must_restart;
2268
2269 if (!dev) {
2270 if (pcnet32_debug & NETIF_MSG_INTR)
2271 printk(KERN_DEBUG "%s(): irq %d for unknown device\n",
2272 __FUNCTION__, irq);
2273 return IRQ_NONE;
1da177e4 2274 }
1da177e4 2275
4a5e8e29
JG		 2276 ioaddr = dev->base_addr;
2277 lp = dev->priv;
1da177e4 2278
4a5e8e29
JG		 2279 spin_lock(&lp->lock);
2280
4a5e8e29
JG		 2281 while ((csr0 = lp->a.read_csr(ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) {
2282 if (csr0 == 0xffff) {
2283 break; /* PCMCIA remove happened */
2284 }
2285 /* Acknowledge all of the current interrupt sources ASAP. */
2286 lp->a.write_csr(ioaddr, 0, csr0 & ~0x004f);
2287
2288 must_restart = 0;
2289
2290 if (netif_msg_intr(lp))
2291 printk(KERN_DEBUG
2292 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2293 dev->name, csr0, lp->a.read_csr(ioaddr, 0));
2294
2295 if (csr0 & 0x0400) /* Rx interrupt */
2296 pcnet32_rx(dev);
2297
2298 if (csr0 & 0x0200) { /* Tx-done interrupt */
2299 unsigned int dirty_tx = lp->dirty_tx;
2300 int delta;
2301
2302 while (dirty_tx != lp->cur_tx) {
2303 int entry = dirty_tx & lp->tx_mod_mask;
2304 int status =
2305 (short)le16_to_cpu(lp->tx_ring[entry].
2306 status);
2307
2308 if (status < 0)
2309 break; /* It still hasn't been Txed */
2310
2311 lp->tx_ring[entry].base = 0;
2312
2313 if (status & 0x4000) {
2314 /* There was an major error, log it. */
2315 int err_status =
2316 le32_to_cpu(lp->tx_ring[entry].
2317 misc);
2318 lp->stats.tx_errors++;
2319 if (netif_msg_tx_err(lp))
2320 printk(KERN_ERR
2321 "%s: Tx error status=%04x err_status=%08x\n",
2322 dev->name, status,
2323 err_status);
2324 if (err_status & 0x04000000)
2325 lp->stats.tx_aborted_errors++;
2326 if (err_status & 0x08000000)
2327 lp->stats.tx_carrier_errors++;
2328 if (err_status & 0x10000000)
2329 lp->stats.tx_window_errors++;
1da177e4 2330#ifndef DO_DXSUFLO
4a5e8e29
JG		 2331 if (err_status & 0x40000000) {
2332 lp->stats.tx_fifo_errors++;
2333 /* Ackk! On FIFO errors the Tx unit is turned off! */
2334 /* Remove this verbosity later! */
2335 if (netif_msg_tx_err(lp))
2336 printk(KERN_ERR
2337 "%s: Tx FIFO error! CSR0=%4.4x\n",
2338 dev->name, csr0);
2339 must_restart = 1;
2340 }
1da177e4 2341#else
4a5e8e29
JG		 2342 if (err_status & 0x40000000) {
2343 lp->stats.tx_fifo_errors++;
2344 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
2345 /* Ackk! On FIFO errors the Tx unit is turned off! */
2346 /* Remove this verbosity later! */
2347 if (netif_msg_tx_err
2348 (lp))
2349 printk(KERN_ERR
2350 "%s: Tx FIFO error! CSR0=%4.4x\n",
2351 dev->
2352 name,
2353 csr0);
2354 must_restart = 1;
2355 }
2356 }
1da177e4 2357#endif
4a5e8e29
JG		 2358 } else {
2359 if (status & 0x1800)
2360 lp->stats.collisions++;
2361 lp->stats.tx_packets++;
2362 }
2363
2364 /* We must free the original skb */
2365 if (lp->tx_skbuff[entry]) {
2366 pci_unmap_single(lp->pci_dev,
2367 lp->tx_dma_addr[entry],
2368 lp->tx_skbuff[entry]->
2369 len, PCI_DMA_TODEVICE);
2370 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
2371 lp->tx_skbuff[entry] = NULL;
2372 lp->tx_dma_addr[entry] = 0;
2373 }
2374 dirty_tx++;
2375 }
2376
2377 delta =
2378 (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask +
2379 lp->tx_ring_size);
2380 if (delta > lp->tx_ring_size) {
2381 if (netif_msg_drv(lp))
2382 printk(KERN_ERR
2383 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
2384 dev->name, dirty_tx, lp->cur_tx,
2385 lp->tx_full);
2386 dirty_tx += lp->tx_ring_size;
2387 delta -= lp->tx_ring_size;
2388 }
2389
2390 if (lp->tx_full &&
2391 netif_queue_stopped(dev) &&
2392 delta < lp->tx_ring_size - 2) {
2393 /* The ring is no longer full, clear tbusy. */
2394 lp->tx_full = 0;
2395 netif_wake_queue(dev);
2396 }
2397 lp->dirty_tx = dirty_tx;
2398 }
2399
2400 /* Log misc errors. */
2401 if (csr0 & 0x4000)
2402 lp->stats.tx_errors++; /* Tx babble. */
2403 if (csr0 & 0x1000) {
2404 /*
2405 * this happens when our receive ring is full. This shouldn't
2406 * be a problem as we will see normal rx interrupts for the frames
2407 * in the receive ring. But there are some PCI chipsets (I can
2408 * reproduce this on SP3G with Intel saturn chipset) which have
2409 * sometimes problems and will fill up the receive ring with
2410 * error descriptors. In this situation we don't get a rx
2411 * interrupt, but a missed frame interrupt sooner or later.
2412 * So we try to clean up our receive ring here.
2413 */
2414 pcnet32_rx(dev);
2415 lp->stats.rx_errors++; /* Missed a Rx frame. */
2416 }
2417 if (csr0 & 0x0800) {
2418 if (netif_msg_drv(lp))
2419 printk(KERN_ERR
2420 "%s: Bus master arbitration failure, status %4.4x.\n",
2421 dev->name, csr0);
2422 /* unlike for the lance, there is no restart needed */
1da177e4
LT		 2423 }
2424
4a5e8e29
JG		 2425 if (must_restart) {
2426 /* reset the chip to clear the error condition, then restart */
2427 lp->a.reset(ioaddr);
b368a3fb
DF		 2428 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2429 pcnet32_restart(dev, CSR0_START);
4a5e8e29 2430 netif_wake_queue(dev);
1da177e4 2431 }
4a5e8e29
JG		 2432 }
2433
2434 /* Set interrupt enable. */
b368a3fb 2435 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
4a5e8e29
JG		 2436
2437 if (netif_msg_intr(lp))
2438 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
b368a3fb 2439 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2440
2441 spin_unlock(&lp->lock);
2442
2443 return IRQ_HANDLED;
1da177e4
LT		 2444}
2445
4a5e8e29 2446static int pcnet32_rx(struct net_device *dev)
1da177e4 2447{
4a5e8e29
JG		 2448 struct pcnet32_private *lp = dev->priv;
2449 int entry = lp->cur_rx & lp->rx_mod_mask;
2450 int boguscnt = lp->rx_ring_size / 2;
2451
2452 /* If we own the next entry, it's a new packet. Send it up. */
2453 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
2454 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
2455
2456 if (status != 0x03) { /* There was an error. */
2457 /*
2458 * There is a tricky error noted by John Murphy,
2459 * <murf@perftech.com> to Russ Nelson: Even with full-sized
2460 * buffers it's possible for a jabber packet to use two
2461 * buffers, with only the last correctly noting the error.
2462 */
2463 if (status & 0x01) /* Only count a general error at the */
2464 lp->stats.rx_errors++; /* end of a packet. */
2465 if (status & 0x20)
2466 lp->stats.rx_frame_errors++;
2467 if (status & 0x10)
2468 lp->stats.rx_over_errors++;
2469 if (status & 0x08)
2470 lp->stats.rx_crc_errors++;
2471 if (status & 0x04)
2472 lp->stats.rx_fifo_errors++;
2473 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1da177e4 2474 } else {
4a5e8e29
JG		 2475 /* Malloc up new buffer, compatible with net-2e. */
2476 short pkt_len =
2477 (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)
2478 - 4;
2479 struct sk_buff *skb;
2480
2481 /* Discard oversize frames. */
2482 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
2483 if (netif_msg_drv(lp))
2484 printk(KERN_ERR
2485 "%s: Impossible packet size %d!\n",
2486 dev->name, pkt_len);
2487 lp->stats.rx_errors++;
2488 } else if (pkt_len < 60) {
2489 if (netif_msg_rx_err(lp))
2490 printk(KERN_ERR "%s: Runt packet!\n",
2491 dev->name);
2492 lp->stats.rx_errors++;
2493 } else {
2494 int rx_in_place = 0;
2495
2496 if (pkt_len > rx_copybreak) {
2497 struct sk_buff *newskb;
2498
2499 if ((newskb =
2500 dev_alloc_skb(PKT_BUF_SZ))) {
2501 skb_reserve(newskb, 2);
2502 skb = lp->rx_skbuff[entry];
2503 pci_unmap_single(lp->pci_dev,
2504 lp->
2505 rx_dma_addr
2506 [entry],
2507 PKT_BUF_SZ - 2,
2508 PCI_DMA_FROMDEVICE);
2509 skb_put(skb, pkt_len);
2510 lp->rx_skbuff[entry] = newskb;
2511 newskb->dev = dev;
2512 lp->rx_dma_addr[entry] =
2513 pci_map_single(lp->pci_dev,
2514 newskb->data,
2515 PKT_BUF_SZ -
2516 2,
2517 PCI_DMA_FROMDEVICE);
2518 lp->rx_ring[entry].base =
2519 le32_to_cpu(lp->
2520 rx_dma_addr
2521 [entry]);
2522 rx_in_place = 1;
2523 } else
2524 skb = NULL;
2525 } else {
2526 skb = dev_alloc_skb(pkt_len + 2);
2527 }
2528
2529 if (skb == NULL) {
2530 int i;
2531 if (netif_msg_drv(lp))
2532 printk(KERN_ERR
2533 "%s: Memory squeeze, deferring packet.\n",
2534 dev->name);
2535 for (i = 0; i < lp->rx_ring_size; i++)
2536 if ((short)
2537 le16_to_cpu(lp->
2538 rx_ring[(entry +
2539 i)
2540 & lp->
2541 rx_mod_mask].
2542 status) < 0)
2543 break;
2544
2545 if (i > lp->rx_ring_size - 2) {
2546 lp->stats.rx_dropped++;
2547 lp->rx_ring[entry].status |=
2548 le16_to_cpu(0x8000);
2549 wmb(); /* Make sure adapter sees owner change */
2550 lp->cur_rx++;
2551 }
2552 break;
2553 }
2554 skb->dev = dev;
2555 if (!rx_in_place) {
2556 skb_reserve(skb, 2); /* 16 byte align */
2557 skb_put(skb, pkt_len); /* Make room */
2558 pci_dma_sync_single_for_cpu(lp->pci_dev,
2559 lp->
2560 rx_dma_addr
2561 [entry],
2562 PKT_BUF_SZ -
2563 2,
2564 PCI_DMA_FROMDEVICE);
2565 eth_copy_and_sum(skb,
2566 (unsigned char *)(lp->
2567 rx_skbuff
2568 [entry]->
2569 data),
2570 pkt_len, 0);
2571 pci_dma_sync_single_for_device(lp->
2572 pci_dev,
2573 lp->
2574 rx_dma_addr
2575 [entry],
2576 PKT_BUF_SZ
2577 - 2,
2578 PCI_DMA_FROMDEVICE);
2579 }
2580 lp->stats.rx_bytes += skb->len;
2581 skb->protocol = eth_type_trans(skb, dev);
2582 netif_rx(skb);
2583 dev->last_rx = jiffies;
2584 lp->stats.rx_packets++;
2585 }
1da177e4 2586 }
4a5e8e29
JG		 2587 /*
2588 * The docs say that the buffer length isn't touched, but Andrew Boyd
2589 * of QNX reports that some revs of the 79C965 clear it.
2590 */
2591 lp->rx_ring[entry].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2592 wmb(); /* Make sure owner changes after all others are visible */
2593 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2594 entry = (++lp->cur_rx) & lp->rx_mod_mask;
2595 if (--boguscnt <= 0)
2596 break; /* don't stay in loop forever */
1da177e4 2597 }
4a5e8e29
JG		 2598
2599 return 0;
1da177e4
LT		 2600}
2601
4a5e8e29 2602static int pcnet32_close(struct net_device *dev)
1da177e4 2603{
4a5e8e29
JG		 2604 unsigned long ioaddr = dev->base_addr;
2605 struct pcnet32_private *lp = dev->priv;
4a5e8e29 2606 unsigned long flags;
1da177e4 2607
4a5e8e29 2608 del_timer_sync(&lp->watchdog_timer);
1da177e4 2609
4a5e8e29 2610 netif_stop_queue(dev);
1da177e4 2611
4a5e8e29 2612 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2613
4a5e8e29 2614 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2615
4a5e8e29
JG		 2616 if (netif_msg_ifdown(lp))
2617 printk(KERN_DEBUG
2618 "%s: Shutting down ethercard, status was %2.2x.\n",
b368a3fb 2619 dev->name, lp->a.read_csr(ioaddr, CSR0));
1da177e4 2620
4a5e8e29 2621 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
b368a3fb 2622 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
1da177e4 2623
4a5e8e29
JG		 2624 /*
2625 * Switch back to 16bit mode to avoid problems with dumb
2626 * DOS packet driver after a warm reboot
2627 */
2628 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2629
4a5e8e29 2630 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2631
4a5e8e29 2632 free_irq(dev->irq, dev);
1da177e4 2633
4a5e8e29 2634 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2635
ac5bfe40
DF		 2636 pcnet32_purge_rx_ring(dev);
2637 pcnet32_purge_tx_ring(dev);
1da177e4 2638
4a5e8e29 2639 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2640
4a5e8e29 2641 return 0;
1da177e4
LT		 2642}
2643
4a5e8e29 2644static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2645{
4a5e8e29
JG		 2646 struct pcnet32_private *lp = dev->priv;
2647 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2648 unsigned long flags;
2649
2650 spin_lock_irqsave(&lp->lock, flags);
4a5e8e29 2651 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
4a5e8e29
JG		 2652 spin_unlock_irqrestore(&lp->lock, flags);
2653
2654 return &lp->stats;
1da177e4
LT		 2655}
2656
2657/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2658static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2659{
4a5e8e29
JG		 2660 struct pcnet32_private *lp = dev->priv;
2661 volatile struct pcnet32_init_block *ib = &lp->init_block;
2662 volatile u16 *mcast_table = (u16 *) & ib->filter;
2663 struct dev_mc_list *dmi = dev->mc_list;
df27f4a6 2664 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2665 char *addrs;
2666 int i;
2667 u32 crc;
2668
2669 /* set all multicast bits */
2670 if (dev->flags & IFF_ALLMULTI) {
2671 ib->filter[0] = 0xffffffff;
2672 ib->filter[1] = 0xffffffff;
df27f4a6
DF		 2673 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2674 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2675 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2676 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2677 return;
2678 }
2679 /* clear the multicast filter */
2680 ib->filter[0] = 0;
2681 ib->filter[1] = 0;
2682
2683 /* Add addresses */
2684 for (i = 0; i < dev->mc_count; i++) {
2685 addrs = dmi->dmi_addr;
2686 dmi = dmi->next;
2687
2688 /* multicast address? */
2689 if (!(*addrs & 1))
2690 continue;
2691
2692 crc = ether_crc_le(6, addrs);
2693 crc = crc >> 26;
2694 mcast_table[crc >> 4] =
2695 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2696 (1 << (crc & 0xf)));
2697 }
df27f4a6
DF		 2698 for (i = 0; i < 4; i++)
2699 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2700 le16_to_cpu(mcast_table[i]));
1da177e4 2701 return;
1da177e4
LT		 2702}
2703
1da177e4
LT		 2704/*
2705 * Set or clear the multicast filter for this adaptor.
2706 */
2707static void pcnet32_set_multicast_list(struct net_device *dev)
2708{
4a5e8e29
JG		 2709 unsigned long ioaddr = dev->base_addr, flags;
2710 struct pcnet32_private *lp = dev->priv;
df27f4a6 2711 int csr15, suspended;
4a5e8e29
JG		 2712
2713 spin_lock_irqsave(&lp->lock, flags);
df27f4a6
DF		 2714 suspended = pcnet32_suspend(dev, &flags, 0);
2715 csr15 = lp->a.read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2716 if (dev->flags & IFF_PROMISC) {
2717 /* Log any net taps. */
2718 if (netif_msg_hw(lp))
2719 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2720 dev->name);
2721 lp->init_block.mode =
2722 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2723 7);
df27f4a6 2724 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29
JG		 2725 } else {
2726 lp->init_block.mode =
2727 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
df27f4a6 2728 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2729 pcnet32_load_multicast(dev);
2730 }
2731
df27f4a6
DF		 2732 if (suspended) {
2733 int csr5;
2734 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2735 csr5 = lp->a.read_csr(ioaddr, CSR5);
2736 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
b368a3fb 2737 } else {
df27f4a6
DF		 2738 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2739 pcnet32_restart(dev, CSR0_NORMAL);
2740 netif_wake_queue(dev);
2741 }
4a5e8e29
JG		 2742
2743 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2744}
2745
2746/* This routine assumes that the lp->lock is held */
2747static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2748{
4a5e8e29
JG		 2749 struct pcnet32_private *lp = dev->priv;
2750 unsigned long ioaddr = dev->base_addr;
2751 u16 val_out;
1da177e4 2752
4a5e8e29
JG		 2753 if (!lp->mii)
2754 return 0;
1da177e4 2755
4a5e8e29
JG		 2756 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2757 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2758
4a5e8e29 2759 return val_out;
1da177e4
LT		 2760}
2761
2762/* This routine assumes that the lp->lock is held */
2763static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2764{
4a5e8e29
JG		 2765 struct pcnet32_private *lp = dev->priv;
2766 unsigned long ioaddr = dev->base_addr;
1da177e4 2767
4a5e8e29
JG		 2768 if (!lp->mii)
2769 return;
1da177e4 2770
4a5e8e29
JG		 2771 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2772 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2773}
2774
2775static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2776{
4a5e8e29
JG		 2777 struct pcnet32_private *lp = dev->priv;
2778 int rc;
2779 unsigned long flags;
1da177e4 2780
4a5e8e29
JG		 2781 /* SIOC[GS]MIIxxx ioctls */
2782 if (lp->mii) {
2783 spin_lock_irqsave(&lp->lock, flags);
2784 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2785 spin_unlock_irqrestore(&lp->lock, flags);
2786 } else {
2787 rc = -EOPNOTSUPP;
2788 }
1da177e4 2789
4a5e8e29 2790 return rc;
1da177e4
LT		 2791}
2792
ac62ef04
DF		 2793static int pcnet32_check_otherphy(struct net_device *dev)
2794{
4a5e8e29
JG		 2795 struct pcnet32_private *lp = dev->priv;
2796 struct mii_if_info mii = lp->mii_if;
2797 u16 bmcr;
2798 int i;
ac62ef04 2799
4a5e8e29
JG		 2800 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2801 if (i == lp->mii_if.phy_id)
2802 continue; /* skip active phy */
2803 if (lp->phymask & (1 << i)) {
2804 mii.phy_id = i;
2805 if (mii_link_ok(&mii)) {
2806 /* found PHY with active link */
2807 if (netif_msg_link(lp))
2808 printk(KERN_INFO
2809 "%s: Using PHY number %d.\n",
2810 dev->name, i);
2811
2812 /* isolate inactive phy */
2813 bmcr =
2814 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2815 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2816 bmcr | BMCR_ISOLATE);
2817
2818 /* de-isolate new phy */
2819 bmcr = mdio_read(dev, i, MII_BMCR);
2820 mdio_write(dev, i, MII_BMCR,
2821 bmcr & ~BMCR_ISOLATE);
2822
2823 /* set new phy address */
2824 lp->mii_if.phy_id = i;
2825 return 1;
2826 }
2827 }
ac62ef04 2828 }
4a5e8e29 2829 return 0;
ac62ef04
DF		 2830}
2831
2832/*
2833 * Show the status of the media. Similar to mii_check_media however it
2834 * correctly shows the link speed for all (tested) pcnet32 variants.
2835 * Devices with no mii just report link state without speed.
2836 *
2837 * Caller is assumed to hold and release the lp->lock.
2838 */
2839
2840static void pcnet32_check_media(struct net_device *dev, int verbose)
2841{
4a5e8e29
JG		 2842 struct pcnet32_private *lp = dev->priv;
2843 int curr_link;
2844 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2845 u32 bcr9;
2846
ac62ef04 2847 if (lp->mii) {
4a5e8e29 2848 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2849 } else {
4a5e8e29
JG		 2850 ulong ioaddr = dev->base_addr; /* card base I/O address */
2851 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2852 }
2853 if (!curr_link) {
2854 if (prev_link || verbose) {
2855 netif_carrier_off(dev);
2856 if (netif_msg_link(lp))
2857 printk(KERN_INFO "%s: link down\n", dev->name);
2858 }
2859 if (lp->phycount > 1) {
2860 curr_link = pcnet32_check_otherphy(dev);
2861 prev_link = 0;
2862 }
2863 } else if (verbose || !prev_link) {
2864 netif_carrier_on(dev);
2865 if (lp->mii) {
2866 if (netif_msg_link(lp)) {
2867 struct ethtool_cmd ecmd;
2868 mii_ethtool_gset(&lp->mii_if, &ecmd);
2869 printk(KERN_INFO
2870 "%s: link up, %sMbps, %s-duplex\n",
2871 dev->name,
2872 (ecmd.speed == SPEED_100) ? "100" : "10",
2873 (ecmd.duplex ==
2874 DUPLEX_FULL) ? "full" : "half");
2875 }
2876 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2877 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2878 if (lp->mii_if.full_duplex)
2879 bcr9 |= (1 << 0);
2880 else
2881 bcr9 &= ~(1 << 0);
2882 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2883 }
2884 } else {
2885 if (netif_msg_link(lp))
2886 printk(KERN_INFO "%s: link up\n", dev->name);
2887 }
ac62ef04 2888 }
ac62ef04
DF		 2889}
2890
2891/*
2892 * Check for loss of link and link establishment.
2893 * Can not use mii_check_media because it does nothing if mode is forced.
2894 */
2895
1da177e4
LT		 2896static void pcnet32_watchdog(struct net_device *dev)
2897{
4a5e8e29
JG		 2898 struct pcnet32_private *lp = dev->priv;
2899 unsigned long flags;
1da177e4 2900
4a5e8e29
JG		 2901 /* Print the link status if it has changed */
2902 spin_lock_irqsave(&lp->lock, flags);
2903 pcnet32_check_media(dev, 0);
2904 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2905
4a5e8e29 2906 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1da177e4
LT		 2907}
2908
2909static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2910{
4a5e8e29
JG		 2911 struct net_device *dev = pci_get_drvdata(pdev);
2912
2913 if (dev) {
2914 struct pcnet32_private *lp = dev->priv;
2915
2916 unregister_netdev(dev);
2917 pcnet32_free_ring(dev);
2918 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2919 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2920 free_netdev(dev);
2921 pci_disable_device(pdev);
2922 pci_set_drvdata(pdev, NULL);
2923 }
1da177e4
LT		 2924}
2925
2926static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2927 .name = DRV_NAME,
2928 .probe = pcnet32_probe_pci,
2929 .remove = __devexit_p(pcnet32_remove_one),
2930 .id_table = pcnet32_pci_tbl,
1da177e4
LT		 2931};
2932
2933/* An additional parameter that may be passed in... */
2934static int debug = -1;
2935static int tx_start_pt = -1;
2936static int pcnet32_have_pci;
2937
2938module_param(debug, int, 0);
2939MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2940module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2941MODULE_PARM_DESC(max_interrupt_work,
2942 DRV_NAME " maximum events handled per interrupt");
1da177e4 2943module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2944MODULE_PARM_DESC(rx_copybreak,
2945 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2946module_param(tx_start_pt, int, 0);
2947MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2948module_param(pcnet32vlb, int, 0);
2949MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2950module_param_array(options, int, NULL, 0);
2951MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2952module_param_array(full_duplex, int, NULL, 0);
2953MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2954/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2955module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 2956MODULE_PARM_DESC(homepna,
2957 DRV_NAME
2958 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 2959
2960MODULE_AUTHOR("Thomas Bogendoerfer");
2961MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2962MODULE_LICENSE("GPL");
2963
2964#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2965
2966static int __init pcnet32_init_module(void)
2967{
4a5e8e29 2968 printk(KERN_INFO "%s", version);
1da177e4 2969
4a5e8e29 2970 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 2971
4a5e8e29
JG		 2972 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2973 tx_start = tx_start_pt;
1da177e4 2974
4a5e8e29 2975 /* find the PCI devices */
29917620 2976 if (!pci_register_driver(&pcnet32_driver))
4a5e8e29 2977 pcnet32_have_pci = 1;
1da177e4 2978
4a5e8e29
JG		 2979 /* should we find any remaining VLbus devices ? */
2980 if (pcnet32vlb)
dcaf9769 2981 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 2982
4a5e8e29
JG		 2983 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2984 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1da177e4 2985
4a5e8e29 2986 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 2987}
2988
2989static void __exit pcnet32_cleanup_module(void)
2990{
4a5e8e29
JG		 2991 struct net_device *next_dev;
2992
2993 while (pcnet32_dev) {
2994 struct pcnet32_private *lp = pcnet32_dev->priv;
2995 next_dev = lp->next;
2996 unregister_netdev(pcnet32_dev);
2997 pcnet32_free_ring(pcnet32_dev);
2998 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2999 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
3000 free_netdev(pcnet32_dev);
3001 pcnet32_dev = next_dev;
3002 }
1da177e4 3003
4a5e8e29
JG		 3004 if (pcnet32_have_pci)
3005 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 3006}
3007
3008module_init(pcnet32_init_module);
3009module_exit(pcnet32_cleanup_module);
3010
3011/*
3012 * Local variables:
3013 * c-indent-level: 4
3014 * tab-width: 8
3015 * End:
3016 */
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