]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ |
2 | /* | |
3 | * Copyright 1996-1999 Thomas Bogendoerfer | |
4 | * | |
5 | * Derived from the lance driver written 1993,1994,1995 by Donald Becker. | |
6 | * | |
7 | * Copyright 1993 United States Government as represented by the | |
8 | * Director, National Security Agency. | |
9 | * | |
10 | * This software may be used and distributed according to the terms | |
11 | * of the GNU General Public License, incorporated herein by reference. | |
12 | * | |
13 | * This driver is for PCnet32 and PCnetPCI based ethercards | |
14 | */ | |
15 | /************************************************************************** | |
16 | * 23 Oct, 2000. | |
17 | * Fixed a few bugs, related to running the controller in 32bit mode. | |
18 | * | |
19 | * Carsten Langgaard, carstenl@mips.com | |
20 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | |
21 | * | |
22 | *************************************************************************/ | |
23 | ||
24 | #define DRV_NAME "pcnet32" | |
ac62ef04 DF |
25 | #define DRV_VERSION "1.32" |
26 | #define DRV_RELDATE "18.Mar.2006" | |
1da177e4 LT |
27 | #define PFX DRV_NAME ": " |
28 | ||
4a5e8e29 JG |
29 | static const char *const version = |
30 | DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n"; | |
1da177e4 LT |
31 | |
32 | #include <linux/module.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/errno.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/interrupt.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/init.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/mii.h> | |
44 | #include <linux/crc32.h> | |
45 | #include <linux/netdevice.h> | |
46 | #include <linux/etherdevice.h> | |
47 | #include <linux/skbuff.h> | |
48 | #include <linux/spinlock.h> | |
49 | #include <linux/moduleparam.h> | |
50 | #include <linux/bitops.h> | |
51 | ||
52 | #include <asm/dma.h> | |
53 | #include <asm/io.h> | |
54 | #include <asm/uaccess.h> | |
55 | #include <asm/irq.h> | |
56 | ||
57 | /* | |
58 | * PCI device identifiers for "new style" Linux PCI Device Drivers | |
59 | */ | |
60 | static struct pci_device_id pcnet32_pci_tbl[] = { | |
4a5e8e29 JG |
61 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, |
62 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
63 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, | |
64 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
65 | ||
66 | /* | |
67 | * Adapters that were sold with IBM's RS/6000 or pSeries hardware have | |
68 | * the incorrect vendor id. | |
69 | */ | |
70 | { PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE, | |
71 | PCI_ANY_ID, PCI_ANY_ID, | |
72 | PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, 0}, | |
73 | ||
74 | { } /* terminate list */ | |
1da177e4 LT |
75 | }; |
76 | ||
4a5e8e29 | 77 | MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl); |
1da177e4 LT |
78 | |
79 | static int cards_found; | |
80 | ||
81 | /* | |
82 | * VLB I/O addresses | |
83 | */ | |
84 | static unsigned int pcnet32_portlist[] __initdata = | |
4a5e8e29 | 85 | { 0x300, 0x320, 0x340, 0x360, 0 }; |
1da177e4 LT |
86 | |
87 | static int pcnet32_debug = 0; | |
4a5e8e29 JG |
88 | static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ |
89 | static int pcnet32vlb; /* check for VLB cards ? */ | |
1da177e4 LT |
90 | |
91 | static struct net_device *pcnet32_dev; | |
92 | ||
93 | static int max_interrupt_work = 2; | |
94 | static int rx_copybreak = 200; | |
95 | ||
96 | #define PCNET32_PORT_AUI 0x00 | |
97 | #define PCNET32_PORT_10BT 0x01 | |
98 | #define PCNET32_PORT_GPSI 0x02 | |
99 | #define PCNET32_PORT_MII 0x03 | |
100 | ||
101 | #define PCNET32_PORT_PORTSEL 0x03 | |
102 | #define PCNET32_PORT_ASEL 0x04 | |
103 | #define PCNET32_PORT_100 0x40 | |
104 | #define PCNET32_PORT_FD 0x80 | |
105 | ||
106 | #define PCNET32_DMA_MASK 0xffffffff | |
107 | ||
108 | #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) | |
109 | #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) | |
110 | ||
111 | /* | |
112 | * table to translate option values from tulip | |
113 | * to internal options | |
114 | */ | |
f71e1309 | 115 | static const unsigned char options_mapping[] = { |
4a5e8e29 JG |
116 | PCNET32_PORT_ASEL, /* 0 Auto-select */ |
117 | PCNET32_PORT_AUI, /* 1 BNC/AUI */ | |
118 | PCNET32_PORT_AUI, /* 2 AUI/BNC */ | |
119 | PCNET32_PORT_ASEL, /* 3 not supported */ | |
120 | PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ | |
121 | PCNET32_PORT_ASEL, /* 5 not supported */ | |
122 | PCNET32_PORT_ASEL, /* 6 not supported */ | |
123 | PCNET32_PORT_ASEL, /* 7 not supported */ | |
124 | PCNET32_PORT_ASEL, /* 8 not supported */ | |
125 | PCNET32_PORT_MII, /* 9 MII 10baseT */ | |
126 | PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ | |
127 | PCNET32_PORT_MII, /* 11 MII (autosel) */ | |
128 | PCNET32_PORT_10BT, /* 12 10BaseT */ | |
129 | PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ | |
130 | /* 14 MII 100BaseTx-FD */ | |
131 | PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, | |
132 | PCNET32_PORT_ASEL /* 15 not supported */ | |
1da177e4 LT |
133 | }; |
134 | ||
135 | static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { | |
4a5e8e29 | 136 | "Loopback test (offline)" |
1da177e4 | 137 | }; |
4a5e8e29 | 138 | |
1da177e4 LT |
139 | #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN) |
140 | ||
ac62ef04 | 141 | #define PCNET32_NUM_REGS 136 |
1da177e4 | 142 | |
4a5e8e29 | 143 | #define MAX_UNITS 8 /* More are supported, limit only on options */ |
1da177e4 LT |
144 | static int options[MAX_UNITS]; |
145 | static int full_duplex[MAX_UNITS]; | |
146 | static int homepna[MAX_UNITS]; | |
147 | ||
148 | /* | |
149 | * Theory of Operation | |
150 | * | |
151 | * This driver uses the same software structure as the normal lance | |
152 | * driver. So look for a verbose description in lance.c. The differences | |
153 | * to the normal lance driver is the use of the 32bit mode of PCnet32 | |
154 | * and PCnetPCI chips. Because these chips are 32bit chips, there is no | |
155 | * 16MB limitation and we don't need bounce buffers. | |
156 | */ | |
157 | ||
1da177e4 LT |
158 | /* |
159 | * Set the number of Tx and Rx buffers, using Log_2(# buffers). | |
160 | * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. | |
161 | * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). | |
162 | */ | |
163 | #ifndef PCNET32_LOG_TX_BUFFERS | |
eabf0415 HWL |
164 | #define PCNET32_LOG_TX_BUFFERS 4 |
165 | #define PCNET32_LOG_RX_BUFFERS 5 | |
166 | #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ | |
167 | #define PCNET32_LOG_MAX_RX_BUFFERS 9 | |
1da177e4 LT |
168 | #endif |
169 | ||
170 | #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) | |
eabf0415 | 171 | #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) |
1da177e4 LT |
172 | |
173 | #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) | |
eabf0415 | 174 | #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) |
1da177e4 LT |
175 | |
176 | #define PKT_BUF_SZ 1544 | |
177 | ||
178 | /* Offsets from base I/O address. */ | |
179 | #define PCNET32_WIO_RDP 0x10 | |
180 | #define PCNET32_WIO_RAP 0x12 | |
181 | #define PCNET32_WIO_RESET 0x14 | |
182 | #define PCNET32_WIO_BDP 0x16 | |
183 | ||
184 | #define PCNET32_DWIO_RDP 0x10 | |
185 | #define PCNET32_DWIO_RAP 0x14 | |
186 | #define PCNET32_DWIO_RESET 0x18 | |
187 | #define PCNET32_DWIO_BDP 0x1C | |
188 | ||
189 | #define PCNET32_TOTAL_SIZE 0x20 | |
190 | ||
191 | /* The PCNET32 Rx and Tx ring descriptors. */ | |
192 | struct pcnet32_rx_head { | |
0b5bf225 JG |
193 | u32 base; |
194 | s16 buf_length; | |
195 | s16 status; | |
196 | u32 msg_length; | |
197 | u32 reserved; | |
1da177e4 LT |
198 | }; |
199 | ||
200 | struct pcnet32_tx_head { | |
0b5bf225 JG |
201 | u32 base; |
202 | s16 length; | |
203 | s16 status; | |
204 | u32 misc; | |
205 | u32 reserved; | |
1da177e4 LT |
206 | }; |
207 | ||
208 | /* The PCNET32 32-Bit initialization block, described in databook. */ | |
209 | struct pcnet32_init_block { | |
0b5bf225 JG |
210 | u16 mode; |
211 | u16 tlen_rlen; | |
212 | u8 phys_addr[6]; | |
213 | u16 reserved; | |
214 | u32 filter[2]; | |
4a5e8e29 | 215 | /* Receive and transmit ring base, along with extra bits. */ |
0b5bf225 JG |
216 | u32 rx_ring; |
217 | u32 tx_ring; | |
1da177e4 LT |
218 | }; |
219 | ||
220 | /* PCnet32 access functions */ | |
221 | struct pcnet32_access { | |
4a5e8e29 JG |
222 | u16 (*read_csr) (unsigned long, int); |
223 | void (*write_csr) (unsigned long, int, u16); | |
224 | u16 (*read_bcr) (unsigned long, int); | |
225 | void (*write_bcr) (unsigned long, int, u16); | |
226 | u16 (*read_rap) (unsigned long); | |
227 | void (*write_rap) (unsigned long, u16); | |
228 | void (*reset) (unsigned long); | |
1da177e4 LT |
229 | }; |
230 | ||
231 | /* | |
76209926 HWL |
232 | * The first field of pcnet32_private is read by the ethernet device |
233 | * so the structure should be allocated using pci_alloc_consistent(). | |
1da177e4 LT |
234 | */ |
235 | struct pcnet32_private { | |
4a5e8e29 JG |
236 | struct pcnet32_init_block init_block; |
237 | /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ | |
0b5bf225 JG |
238 | struct pcnet32_rx_head *rx_ring; |
239 | struct pcnet32_tx_head *tx_ring; | |
240 | dma_addr_t dma_addr;/* DMA address of beginning of this | |
241 | object, returned by pci_alloc_consistent */ | |
242 | struct pci_dev *pci_dev; | |
243 | const char *name; | |
4a5e8e29 | 244 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
0b5bf225 JG |
245 | struct sk_buff **tx_skbuff; |
246 | struct sk_buff **rx_skbuff; | |
247 | dma_addr_t *tx_dma_addr; | |
248 | dma_addr_t *rx_dma_addr; | |
249 | struct pcnet32_access a; | |
250 | spinlock_t lock; /* Guard lock */ | |
251 | unsigned int cur_rx, cur_tx; /* The next free ring entry */ | |
252 | unsigned int rx_ring_size; /* current rx ring size */ | |
253 | unsigned int tx_ring_size; /* current tx ring size */ | |
254 | unsigned int rx_mod_mask; /* rx ring modular mask */ | |
255 | unsigned int tx_mod_mask; /* tx ring modular mask */ | |
256 | unsigned short rx_len_bits; | |
257 | unsigned short tx_len_bits; | |
258 | dma_addr_t rx_ring_dma_addr; | |
259 | dma_addr_t tx_ring_dma_addr; | |
260 | unsigned int dirty_rx, /* ring entries to be freed. */ | |
261 | dirty_tx; | |
262 | ||
263 | struct net_device_stats stats; | |
264 | char tx_full; | |
265 | char phycount; /* number of phys found */ | |
266 | int options; | |
267 | unsigned int shared_irq:1, /* shared irq possible */ | |
268 | dxsuflo:1, /* disable transmit stop on uflo */ | |
269 | mii:1; /* mii port available */ | |
270 | struct net_device *next; | |
271 | struct mii_if_info mii_if; | |
272 | struct timer_list watchdog_timer; | |
273 | struct timer_list blink_timer; | |
274 | u32 msg_enable; /* debug message level */ | |
4a5e8e29 JG |
275 | |
276 | /* each bit indicates an available PHY */ | |
0b5bf225 | 277 | u32 phymask; |
1da177e4 LT |
278 | }; |
279 | ||
4a5e8e29 JG |
280 | static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); |
281 | static int pcnet32_probe1(unsigned long, int, struct pci_dev *); | |
282 | static int pcnet32_open(struct net_device *); | |
283 | static int pcnet32_init_ring(struct net_device *); | |
284 | static int pcnet32_start_xmit(struct sk_buff *, struct net_device *); | |
285 | static int pcnet32_rx(struct net_device *); | |
286 | static void pcnet32_tx_timeout(struct net_device *dev); | |
1da177e4 | 287 | static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *); |
4a5e8e29 | 288 | static int pcnet32_close(struct net_device *); |
1da177e4 LT |
289 | static struct net_device_stats *pcnet32_get_stats(struct net_device *); |
290 | static void pcnet32_load_multicast(struct net_device *dev); | |
291 | static void pcnet32_set_multicast_list(struct net_device *); | |
4a5e8e29 | 292 | static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); |
1da177e4 LT |
293 | static void pcnet32_watchdog(struct net_device *); |
294 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num); | |
4a5e8e29 JG |
295 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, |
296 | int val); | |
1da177e4 LT |
297 | static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); |
298 | static void pcnet32_ethtool_test(struct net_device *dev, | |
4a5e8e29 JG |
299 | struct ethtool_test *eth_test, u64 * data); |
300 | static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1); | |
1da177e4 LT |
301 | static int pcnet32_phys_id(struct net_device *dev, u32 data); |
302 | static void pcnet32_led_blink_callback(struct net_device *dev); | |
303 | static int pcnet32_get_regs_len(struct net_device *dev); | |
304 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
4a5e8e29 | 305 | void *ptr); |
1bcd3153 | 306 | static void pcnet32_purge_tx_ring(struct net_device *dev); |
a88c844c | 307 | static int pcnet32_alloc_ring(struct net_device *dev, char *name); |
eabf0415 | 308 | static void pcnet32_free_ring(struct net_device *dev); |
ac62ef04 | 309 | static void pcnet32_check_media(struct net_device *dev, int verbose); |
eabf0415 | 310 | |
4a5e8e29 | 311 | static u16 pcnet32_wio_read_csr(unsigned long addr, int index) |
1da177e4 | 312 | { |
4a5e8e29 JG |
313 | outw(index, addr + PCNET32_WIO_RAP); |
314 | return inw(addr + PCNET32_WIO_RDP); | |
1da177e4 LT |
315 | } |
316 | ||
4a5e8e29 | 317 | static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) |
1da177e4 | 318 | { |
4a5e8e29 JG |
319 | outw(index, addr + PCNET32_WIO_RAP); |
320 | outw(val, addr + PCNET32_WIO_RDP); | |
1da177e4 LT |
321 | } |
322 | ||
4a5e8e29 | 323 | static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) |
1da177e4 | 324 | { |
4a5e8e29 JG |
325 | outw(index, addr + PCNET32_WIO_RAP); |
326 | return inw(addr + PCNET32_WIO_BDP); | |
1da177e4 LT |
327 | } |
328 | ||
4a5e8e29 | 329 | static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) |
1da177e4 | 330 | { |
4a5e8e29 JG |
331 | outw(index, addr + PCNET32_WIO_RAP); |
332 | outw(val, addr + PCNET32_WIO_BDP); | |
1da177e4 LT |
333 | } |
334 | ||
4a5e8e29 | 335 | static u16 pcnet32_wio_read_rap(unsigned long addr) |
1da177e4 | 336 | { |
4a5e8e29 | 337 | return inw(addr + PCNET32_WIO_RAP); |
1da177e4 LT |
338 | } |
339 | ||
4a5e8e29 | 340 | static void pcnet32_wio_write_rap(unsigned long addr, u16 val) |
1da177e4 | 341 | { |
4a5e8e29 | 342 | outw(val, addr + PCNET32_WIO_RAP); |
1da177e4 LT |
343 | } |
344 | ||
4a5e8e29 | 345 | static void pcnet32_wio_reset(unsigned long addr) |
1da177e4 | 346 | { |
4a5e8e29 | 347 | inw(addr + PCNET32_WIO_RESET); |
1da177e4 LT |
348 | } |
349 | ||
4a5e8e29 | 350 | static int pcnet32_wio_check(unsigned long addr) |
1da177e4 | 351 | { |
4a5e8e29 JG |
352 | outw(88, addr + PCNET32_WIO_RAP); |
353 | return (inw(addr + PCNET32_WIO_RAP) == 88); | |
1da177e4 LT |
354 | } |
355 | ||
356 | static struct pcnet32_access pcnet32_wio = { | |
4a5e8e29 JG |
357 | .read_csr = pcnet32_wio_read_csr, |
358 | .write_csr = pcnet32_wio_write_csr, | |
359 | .read_bcr = pcnet32_wio_read_bcr, | |
360 | .write_bcr = pcnet32_wio_write_bcr, | |
361 | .read_rap = pcnet32_wio_read_rap, | |
362 | .write_rap = pcnet32_wio_write_rap, | |
363 | .reset = pcnet32_wio_reset | |
1da177e4 LT |
364 | }; |
365 | ||
4a5e8e29 | 366 | static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) |
1da177e4 | 367 | { |
4a5e8e29 JG |
368 | outl(index, addr + PCNET32_DWIO_RAP); |
369 | return (inl(addr + PCNET32_DWIO_RDP) & 0xffff); | |
1da177e4 LT |
370 | } |
371 | ||
4a5e8e29 | 372 | static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) |
1da177e4 | 373 | { |
4a5e8e29 JG |
374 | outl(index, addr + PCNET32_DWIO_RAP); |
375 | outl(val, addr + PCNET32_DWIO_RDP); | |
1da177e4 LT |
376 | } |
377 | ||
4a5e8e29 | 378 | static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) |
1da177e4 | 379 | { |
4a5e8e29 JG |
380 | outl(index, addr + PCNET32_DWIO_RAP); |
381 | return (inl(addr + PCNET32_DWIO_BDP) & 0xffff); | |
1da177e4 LT |
382 | } |
383 | ||
4a5e8e29 | 384 | static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) |
1da177e4 | 385 | { |
4a5e8e29 JG |
386 | outl(index, addr + PCNET32_DWIO_RAP); |
387 | outl(val, addr + PCNET32_DWIO_BDP); | |
1da177e4 LT |
388 | } |
389 | ||
4a5e8e29 | 390 | static u16 pcnet32_dwio_read_rap(unsigned long addr) |
1da177e4 | 391 | { |
4a5e8e29 | 392 | return (inl(addr + PCNET32_DWIO_RAP) & 0xffff); |
1da177e4 LT |
393 | } |
394 | ||
4a5e8e29 | 395 | static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) |
1da177e4 | 396 | { |
4a5e8e29 | 397 | outl(val, addr + PCNET32_DWIO_RAP); |
1da177e4 LT |
398 | } |
399 | ||
4a5e8e29 | 400 | static void pcnet32_dwio_reset(unsigned long addr) |
1da177e4 | 401 | { |
4a5e8e29 | 402 | inl(addr + PCNET32_DWIO_RESET); |
1da177e4 LT |
403 | } |
404 | ||
4a5e8e29 | 405 | static int pcnet32_dwio_check(unsigned long addr) |
1da177e4 | 406 | { |
4a5e8e29 JG |
407 | outl(88, addr + PCNET32_DWIO_RAP); |
408 | return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88); | |
1da177e4 LT |
409 | } |
410 | ||
411 | static struct pcnet32_access pcnet32_dwio = { | |
4a5e8e29 JG |
412 | .read_csr = pcnet32_dwio_read_csr, |
413 | .write_csr = pcnet32_dwio_write_csr, | |
414 | .read_bcr = pcnet32_dwio_read_bcr, | |
415 | .write_bcr = pcnet32_dwio_write_bcr, | |
416 | .read_rap = pcnet32_dwio_read_rap, | |
417 | .write_rap = pcnet32_dwio_write_rap, | |
418 | .reset = pcnet32_dwio_reset | |
1da177e4 LT |
419 | }; |
420 | ||
421 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
422 | static void pcnet32_poll_controller(struct net_device *dev) | |
423 | { | |
4a5e8e29 JG |
424 | disable_irq(dev->irq); |
425 | pcnet32_interrupt(0, dev, NULL); | |
426 | enable_irq(dev->irq); | |
1da177e4 LT |
427 | } |
428 | #endif | |
429 | ||
1da177e4 LT |
430 | static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
431 | { | |
4a5e8e29 JG |
432 | struct pcnet32_private *lp = dev->priv; |
433 | unsigned long flags; | |
434 | int r = -EOPNOTSUPP; | |
1da177e4 | 435 | |
4a5e8e29 JG |
436 | if (lp->mii) { |
437 | spin_lock_irqsave(&lp->lock, flags); | |
438 | mii_ethtool_gset(&lp->mii_if, cmd); | |
439 | spin_unlock_irqrestore(&lp->lock, flags); | |
440 | r = 0; | |
441 | } | |
442 | return r; | |
1da177e4 LT |
443 | } |
444 | ||
445 | static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
446 | { | |
4a5e8e29 JG |
447 | struct pcnet32_private *lp = dev->priv; |
448 | unsigned long flags; | |
449 | int r = -EOPNOTSUPP; | |
1da177e4 | 450 | |
4a5e8e29 JG |
451 | if (lp->mii) { |
452 | spin_lock_irqsave(&lp->lock, flags); | |
453 | r = mii_ethtool_sset(&lp->mii_if, cmd); | |
454 | spin_unlock_irqrestore(&lp->lock, flags); | |
455 | } | |
456 | return r; | |
1da177e4 LT |
457 | } |
458 | ||
4a5e8e29 JG |
459 | static void pcnet32_get_drvinfo(struct net_device *dev, |
460 | struct ethtool_drvinfo *info) | |
1da177e4 | 461 | { |
4a5e8e29 JG |
462 | struct pcnet32_private *lp = dev->priv; |
463 | ||
464 | strcpy(info->driver, DRV_NAME); | |
465 | strcpy(info->version, DRV_VERSION); | |
466 | if (lp->pci_dev) | |
467 | strcpy(info->bus_info, pci_name(lp->pci_dev)); | |
468 | else | |
469 | sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr); | |
1da177e4 LT |
470 | } |
471 | ||
472 | static u32 pcnet32_get_link(struct net_device *dev) | |
473 | { | |
4a5e8e29 JG |
474 | struct pcnet32_private *lp = dev->priv; |
475 | unsigned long flags; | |
476 | int r; | |
1da177e4 | 477 | |
4a5e8e29 JG |
478 | spin_lock_irqsave(&lp->lock, flags); |
479 | if (lp->mii) { | |
480 | r = mii_link_ok(&lp->mii_if); | |
481 | } else { | |
482 | ulong ioaddr = dev->base_addr; /* card base I/O address */ | |
483 | r = (lp->a.read_bcr(ioaddr, 4) != 0xc0); | |
484 | } | |
485 | spin_unlock_irqrestore(&lp->lock, flags); | |
486 | ||
487 | return r; | |
1da177e4 LT |
488 | } |
489 | ||
490 | static u32 pcnet32_get_msglevel(struct net_device *dev) | |
491 | { | |
4a5e8e29 JG |
492 | struct pcnet32_private *lp = dev->priv; |
493 | return lp->msg_enable; | |
1da177e4 LT |
494 | } |
495 | ||
496 | static void pcnet32_set_msglevel(struct net_device *dev, u32 value) | |
497 | { | |
4a5e8e29 JG |
498 | struct pcnet32_private *lp = dev->priv; |
499 | lp->msg_enable = value; | |
1da177e4 LT |
500 | } |
501 | ||
502 | static int pcnet32_nway_reset(struct net_device *dev) | |
503 | { | |
4a5e8e29 JG |
504 | struct pcnet32_private *lp = dev->priv; |
505 | unsigned long flags; | |
506 | int r = -EOPNOTSUPP; | |
1da177e4 | 507 | |
4a5e8e29 JG |
508 | if (lp->mii) { |
509 | spin_lock_irqsave(&lp->lock, flags); | |
510 | r = mii_nway_restart(&lp->mii_if); | |
511 | spin_unlock_irqrestore(&lp->lock, flags); | |
512 | } | |
513 | return r; | |
1da177e4 LT |
514 | } |
515 | ||
4a5e8e29 JG |
516 | static void pcnet32_get_ringparam(struct net_device *dev, |
517 | struct ethtool_ringparam *ering) | |
1da177e4 | 518 | { |
4a5e8e29 | 519 | struct pcnet32_private *lp = dev->priv; |
1da177e4 | 520 | |
4a5e8e29 JG |
521 | ering->tx_max_pending = TX_MAX_RING_SIZE - 1; |
522 | ering->tx_pending = lp->tx_ring_size - 1; | |
523 | ering->rx_max_pending = RX_MAX_RING_SIZE - 1; | |
524 | ering->rx_pending = lp->rx_ring_size - 1; | |
eabf0415 HWL |
525 | } |
526 | ||
4a5e8e29 JG |
527 | static int pcnet32_set_ringparam(struct net_device *dev, |
528 | struct ethtool_ringparam *ering) | |
eabf0415 | 529 | { |
4a5e8e29 JG |
530 | struct pcnet32_private *lp = dev->priv; |
531 | unsigned long flags; | |
532 | int i; | |
533 | ||
534 | if (ering->rx_mini_pending || ering->rx_jumbo_pending) | |
535 | return -EINVAL; | |
536 | ||
537 | if (netif_running(dev)) | |
538 | pcnet32_close(dev); | |
539 | ||
540 | spin_lock_irqsave(&lp->lock, flags); | |
eabf0415 | 541 | pcnet32_free_ring(dev); |
4a5e8e29 JG |
542 | lp->tx_ring_size = |
543 | min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); | |
544 | lp->rx_ring_size = | |
545 | min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE); | |
546 | ||
547 | /* set the minimum ring size to 4, to allow the loopback test to work | |
548 | * unchanged. | |
549 | */ | |
550 | for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { | |
551 | if (lp->tx_ring_size <= (1 << i)) | |
552 | break; | |
553 | } | |
554 | lp->tx_ring_size = (1 << i); | |
555 | lp->tx_mod_mask = lp->tx_ring_size - 1; | |
556 | lp->tx_len_bits = (i << 12); | |
eabf0415 | 557 | |
4a5e8e29 JG |
558 | for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { |
559 | if (lp->rx_ring_size <= (1 << i)) | |
560 | break; | |
561 | } | |
562 | lp->rx_ring_size = (1 << i); | |
563 | lp->rx_mod_mask = lp->rx_ring_size - 1; | |
564 | lp->rx_len_bits = (i << 4); | |
565 | ||
566 | if (pcnet32_alloc_ring(dev, dev->name)) { | |
567 | pcnet32_free_ring(dev); | |
568 | spin_unlock_irqrestore(&lp->lock, flags); | |
569 | return -ENOMEM; | |
570 | } | |
eabf0415 | 571 | |
4a5e8e29 | 572 | spin_unlock_irqrestore(&lp->lock, flags); |
eabf0415 | 573 | |
4a5e8e29 JG |
574 | if (pcnet32_debug & NETIF_MSG_DRV) |
575 | printk(KERN_INFO PFX | |
576 | "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name, | |
577 | lp->rx_ring_size, lp->tx_ring_size); | |
eabf0415 | 578 | |
4a5e8e29 JG |
579 | if (netif_running(dev)) |
580 | pcnet32_open(dev); | |
581 | ||
582 | return 0; | |
1da177e4 LT |
583 | } |
584 | ||
4a5e8e29 JG |
585 | static void pcnet32_get_strings(struct net_device *dev, u32 stringset, |
586 | u8 * data) | |
1da177e4 | 587 | { |
4a5e8e29 | 588 | memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); |
1da177e4 LT |
589 | } |
590 | ||
591 | static int pcnet32_self_test_count(struct net_device *dev) | |
592 | { | |
4a5e8e29 | 593 | return PCNET32_TEST_LEN; |
1da177e4 LT |
594 | } |
595 | ||
596 | static void pcnet32_ethtool_test(struct net_device *dev, | |
4a5e8e29 | 597 | struct ethtool_test *test, u64 * data) |
1da177e4 | 598 | { |
4a5e8e29 JG |
599 | struct pcnet32_private *lp = dev->priv; |
600 | int rc; | |
601 | ||
602 | if (test->flags == ETH_TEST_FL_OFFLINE) { | |
603 | rc = pcnet32_loopback_test(dev, data); | |
604 | if (rc) { | |
605 | if (netif_msg_hw(lp)) | |
606 | printk(KERN_DEBUG "%s: Loopback test failed.\n", | |
607 | dev->name); | |
608 | test->flags |= ETH_TEST_FL_FAILED; | |
609 | } else if (netif_msg_hw(lp)) | |
610 | printk(KERN_DEBUG "%s: Loopback test passed.\n", | |
611 | dev->name); | |
1da177e4 | 612 | } else if (netif_msg_hw(lp)) |
4a5e8e29 JG |
613 | printk(KERN_DEBUG |
614 | "%s: No tests to run (specify 'Offline' on ethtool).", | |
615 | dev->name); | |
616 | } /* end pcnet32_ethtool_test */ | |
1da177e4 | 617 | |
4a5e8e29 | 618 | static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1) |
1da177e4 | 619 | { |
4a5e8e29 JG |
620 | struct pcnet32_private *lp = dev->priv; |
621 | struct pcnet32_access *a = &lp->a; /* access to registers */ | |
622 | ulong ioaddr = dev->base_addr; /* card base I/O address */ | |
623 | struct sk_buff *skb; /* sk buff */ | |
624 | int x, i; /* counters */ | |
625 | int numbuffs = 4; /* number of TX/RX buffers and descs */ | |
626 | u16 status = 0x8300; /* TX ring status */ | |
627 | u16 teststatus; /* test of ring status */ | |
628 | int rc; /* return code */ | |
629 | int size; /* size of packets */ | |
630 | unsigned char *packet; /* source packet data */ | |
631 | static const int data_len = 60; /* length of source packets */ | |
632 | unsigned long flags; | |
633 | unsigned long ticks; | |
634 | ||
635 | *data1 = 1; /* status of test, default to fail */ | |
636 | rc = 1; /* default to fail */ | |
637 | ||
638 | if (netif_running(dev)) | |
639 | pcnet32_close(dev); | |
640 | ||
641 | spin_lock_irqsave(&lp->lock, flags); | |
642 | ||
643 | /* Reset the PCNET32 */ | |
644 | lp->a.reset(ioaddr); | |
645 | ||
646 | /* switch pcnet32 to 32bit mode */ | |
647 | lp->a.write_bcr(ioaddr, 20, 2); | |
648 | ||
649 | lp->init_block.mode = | |
650 | le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); | |
651 | lp->init_block.filter[0] = 0; | |
652 | lp->init_block.filter[1] = 0; | |
653 | ||
654 | /* purge & init rings but don't actually restart */ | |
655 | pcnet32_restart(dev, 0x0000); | |
656 | ||
657 | lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */ | |
658 | ||
659 | /* Initialize Transmit buffers. */ | |
660 | size = data_len + 15; | |
661 | for (x = 0; x < numbuffs; x++) { | |
662 | if (!(skb = dev_alloc_skb(size))) { | |
663 | if (netif_msg_hw(lp)) | |
664 | printk(KERN_DEBUG | |
665 | "%s: Cannot allocate skb at line: %d!\n", | |
666 | dev->name, __LINE__); | |
667 | goto clean_up; | |
668 | } else { | |
669 | packet = skb->data; | |
670 | skb_put(skb, size); /* create space for data */ | |
671 | lp->tx_skbuff[x] = skb; | |
672 | lp->tx_ring[x].length = le16_to_cpu(-skb->len); | |
673 | lp->tx_ring[x].misc = 0; | |
674 | ||
675 | /* put DA and SA into the skb */ | |
676 | for (i = 0; i < 6; i++) | |
677 | *packet++ = dev->dev_addr[i]; | |
678 | for (i = 0; i < 6; i++) | |
679 | *packet++ = dev->dev_addr[i]; | |
680 | /* type */ | |
681 | *packet++ = 0x08; | |
682 | *packet++ = 0x06; | |
683 | /* packet number */ | |
684 | *packet++ = x; | |
685 | /* fill packet with data */ | |
686 | for (i = 0; i < data_len; i++) | |
687 | *packet++ = i; | |
688 | ||
689 | lp->tx_dma_addr[x] = | |
690 | pci_map_single(lp->pci_dev, skb->data, skb->len, | |
691 | PCI_DMA_TODEVICE); | |
692 | lp->tx_ring[x].base = | |
693 | (u32) le32_to_cpu(lp->tx_dma_addr[x]); | |
694 | wmb(); /* Make sure owner changes after all others are visible */ | |
695 | lp->tx_ring[x].status = le16_to_cpu(status); | |
696 | } | |
1da177e4 | 697 | } |
1da177e4 | 698 | |
4a5e8e29 JG |
699 | x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */ |
700 | x = x | 0x0002; | |
701 | a->write_bcr(ioaddr, 32, x); | |
702 | ||
703 | lp->a.write_csr(ioaddr, 15, 0x0044); /* set int loopback in CSR15 */ | |
704 | ||
705 | teststatus = le16_to_cpu(0x8000); | |
706 | lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */ | |
707 | ||
708 | /* Check status of descriptors */ | |
709 | for (x = 0; x < numbuffs; x++) { | |
710 | ticks = 0; | |
711 | rmb(); | |
712 | while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { | |
713 | spin_unlock_irqrestore(&lp->lock, flags); | |
714 | mdelay(1); | |
715 | spin_lock_irqsave(&lp->lock, flags); | |
716 | rmb(); | |
717 | ticks++; | |
718 | } | |
719 | if (ticks == 200) { | |
720 | if (netif_msg_hw(lp)) | |
721 | printk("%s: Desc %d failed to reset!\n", | |
722 | dev->name, x); | |
723 | break; | |
724 | } | |
725 | } | |
726 | ||
727 | lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */ | |
728 | wmb(); | |
729 | if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { | |
730 | printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name); | |
731 | ||
732 | for (x = 0; x < numbuffs; x++) { | |
733 | printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x); | |
734 | skb = lp->rx_skbuff[x]; | |
735 | for (i = 0; i < size; i++) { | |
736 | printk("%02x ", *(skb->data + i)); | |
737 | } | |
738 | printk("\n"); | |
739 | } | |
740 | } | |
1da177e4 | 741 | |
4a5e8e29 JG |
742 | x = 0; |
743 | rc = 0; | |
744 | while (x < numbuffs && !rc) { | |
745 | skb = lp->rx_skbuff[x]; | |
746 | packet = lp->tx_skbuff[x]->data; | |
747 | for (i = 0; i < size; i++) { | |
748 | if (*(skb->data + i) != packet[i]) { | |
749 | if (netif_msg_hw(lp)) | |
750 | printk(KERN_DEBUG | |
751 | "%s: Error in compare! %2x - %02x %02x\n", | |
752 | dev->name, i, *(skb->data + i), | |
753 | packet[i]); | |
754 | rc = 1; | |
755 | break; | |
756 | } | |
757 | } | |
758 | x++; | |
759 | } | |
760 | if (!rc) { | |
761 | *data1 = 0; | |
762 | } | |
1da177e4 | 763 | |
4a5e8e29 JG |
764 | clean_up: |
765 | pcnet32_purge_tx_ring(dev); | |
766 | x = a->read_csr(ioaddr, 15) & 0xFFFF; | |
767 | a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */ | |
1da177e4 | 768 | |
4a5e8e29 JG |
769 | x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ |
770 | x = x & ~0x0002; | |
771 | a->write_bcr(ioaddr, 32, x); | |
1da177e4 | 772 | |
4a5e8e29 JG |
773 | spin_unlock_irqrestore(&lp->lock, flags); |
774 | ||
775 | if (netif_running(dev)) { | |
776 | pcnet32_open(dev); | |
777 | } else { | |
778 | lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ | |
779 | } | |
780 | ||
781 | return (rc); | |
782 | } /* end pcnet32_loopback_test */ | |
1da177e4 LT |
783 | |
784 | static void pcnet32_led_blink_callback(struct net_device *dev) | |
785 | { | |
4a5e8e29 JG |
786 | struct pcnet32_private *lp = dev->priv; |
787 | struct pcnet32_access *a = &lp->a; | |
788 | ulong ioaddr = dev->base_addr; | |
789 | unsigned long flags; | |
790 | int i; | |
791 | ||
792 | spin_lock_irqsave(&lp->lock, flags); | |
793 | for (i = 4; i < 8; i++) { | |
794 | a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); | |
795 | } | |
796 | spin_unlock_irqrestore(&lp->lock, flags); | |
797 | ||
798 | mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT); | |
1da177e4 LT |
799 | } |
800 | ||
801 | static int pcnet32_phys_id(struct net_device *dev, u32 data) | |
802 | { | |
4a5e8e29 JG |
803 | struct pcnet32_private *lp = dev->priv; |
804 | struct pcnet32_access *a = &lp->a; | |
805 | ulong ioaddr = dev->base_addr; | |
806 | unsigned long flags; | |
807 | int i, regs[4]; | |
808 | ||
809 | if (!lp->blink_timer.function) { | |
810 | init_timer(&lp->blink_timer); | |
811 | lp->blink_timer.function = (void *)pcnet32_led_blink_callback; | |
812 | lp->blink_timer.data = (unsigned long)dev; | |
813 | } | |
814 | ||
815 | /* Save the current value of the bcrs */ | |
816 | spin_lock_irqsave(&lp->lock, flags); | |
817 | for (i = 4; i < 8; i++) { | |
818 | regs[i - 4] = a->read_bcr(ioaddr, i); | |
819 | } | |
820 | spin_unlock_irqrestore(&lp->lock, flags); | |
821 | ||
822 | mod_timer(&lp->blink_timer, jiffies); | |
823 | set_current_state(TASK_INTERRUPTIBLE); | |
824 | ||
825 | if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))) | |
826 | data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ); | |
827 | ||
828 | msleep_interruptible(data * 1000); | |
829 | del_timer_sync(&lp->blink_timer); | |
830 | ||
831 | /* Restore the original value of the bcrs */ | |
832 | spin_lock_irqsave(&lp->lock, flags); | |
833 | for (i = 4; i < 8; i++) { | |
834 | a->write_bcr(ioaddr, i, regs[i - 4]); | |
835 | } | |
836 | spin_unlock_irqrestore(&lp->lock, flags); | |
837 | ||
838 | return 0; | |
1da177e4 LT |
839 | } |
840 | ||
ac62ef04 DF |
841 | #define PCNET32_REGS_PER_PHY 32 |
842 | #define PCNET32_MAX_PHYS 32 | |
1da177e4 LT |
843 | static int pcnet32_get_regs_len(struct net_device *dev) |
844 | { | |
4a5e8e29 JG |
845 | struct pcnet32_private *lp = dev->priv; |
846 | int j = lp->phycount * PCNET32_REGS_PER_PHY; | |
ac62ef04 | 847 | |
4a5e8e29 | 848 | return ((PCNET32_NUM_REGS + j) * sizeof(u16)); |
1da177e4 LT |
849 | } |
850 | ||
851 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
4a5e8e29 | 852 | void *ptr) |
1da177e4 | 853 | { |
4a5e8e29 JG |
854 | int i, csr0; |
855 | u16 *buff = ptr; | |
856 | struct pcnet32_private *lp = dev->priv; | |
857 | struct pcnet32_access *a = &lp->a; | |
858 | ulong ioaddr = dev->base_addr; | |
859 | int ticks; | |
860 | unsigned long flags; | |
861 | ||
862 | spin_lock_irqsave(&lp->lock, flags); | |
863 | ||
864 | csr0 = a->read_csr(ioaddr, 0); | |
865 | if (!(csr0 & 0x0004)) { /* If not stopped */ | |
866 | /* set SUSPEND (SPND) - CSR5 bit 0 */ | |
867 | a->write_csr(ioaddr, 5, 0x0001); | |
868 | ||
869 | /* poll waiting for bit to be set */ | |
870 | ticks = 0; | |
871 | while (!(a->read_csr(ioaddr, 5) & 0x0001)) { | |
872 | spin_unlock_irqrestore(&lp->lock, flags); | |
873 | mdelay(1); | |
874 | spin_lock_irqsave(&lp->lock, flags); | |
875 | ticks++; | |
876 | if (ticks > 200) { | |
877 | if (netif_msg_hw(lp)) | |
878 | printk(KERN_DEBUG | |
879 | "%s: Error getting into suspend!\n", | |
880 | dev->name); | |
881 | break; | |
882 | } | |
ac62ef04 | 883 | } |
1da177e4 | 884 | } |
1da177e4 | 885 | |
4a5e8e29 JG |
886 | /* read address PROM */ |
887 | for (i = 0; i < 16; i += 2) | |
888 | *buff++ = inw(ioaddr + i); | |
889 | ||
890 | /* read control and status registers */ | |
891 | for (i = 0; i < 90; i++) { | |
892 | *buff++ = a->read_csr(ioaddr, i); | |
893 | } | |
894 | ||
895 | *buff++ = a->read_csr(ioaddr, 112); | |
896 | *buff++ = a->read_csr(ioaddr, 114); | |
1da177e4 | 897 | |
4a5e8e29 JG |
898 | /* read bus configuration registers */ |
899 | for (i = 0; i < 30; i++) { | |
900 | *buff++ = a->read_bcr(ioaddr, i); | |
901 | } | |
902 | *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ | |
903 | for (i = 31; i < 36; i++) { | |
904 | *buff++ = a->read_bcr(ioaddr, i); | |
905 | } | |
906 | ||
907 | /* read mii phy registers */ | |
908 | if (lp->mii) { | |
909 | int j; | |
910 | for (j = 0; j < PCNET32_MAX_PHYS; j++) { | |
911 | if (lp->phymask & (1 << j)) { | |
912 | for (i = 0; i < PCNET32_REGS_PER_PHY; i++) { | |
913 | lp->a.write_bcr(ioaddr, 33, | |
914 | (j << 5) | i); | |
915 | *buff++ = lp->a.read_bcr(ioaddr, 34); | |
916 | } | |
917 | } | |
918 | } | |
919 | } | |
920 | ||
921 | if (!(csr0 & 0x0004)) { /* If not stopped */ | |
922 | /* clear SUSPEND (SPND) - CSR5 bit 0 */ | |
923 | a->write_csr(ioaddr, 5, 0x0000); | |
924 | } | |
925 | ||
926 | spin_unlock_irqrestore(&lp->lock, flags); | |
1da177e4 LT |
927 | } |
928 | ||
929 | static struct ethtool_ops pcnet32_ethtool_ops = { | |
4a5e8e29 JG |
930 | .get_settings = pcnet32_get_settings, |
931 | .set_settings = pcnet32_set_settings, | |
932 | .get_drvinfo = pcnet32_get_drvinfo, | |
933 | .get_msglevel = pcnet32_get_msglevel, | |
934 | .set_msglevel = pcnet32_set_msglevel, | |
935 | .nway_reset = pcnet32_nway_reset, | |
936 | .get_link = pcnet32_get_link, | |
937 | .get_ringparam = pcnet32_get_ringparam, | |
938 | .set_ringparam = pcnet32_set_ringparam, | |
939 | .get_tx_csum = ethtool_op_get_tx_csum, | |
940 | .get_sg = ethtool_op_get_sg, | |
941 | .get_tso = ethtool_op_get_tso, | |
942 | .get_strings = pcnet32_get_strings, | |
943 | .self_test_count = pcnet32_self_test_count, | |
944 | .self_test = pcnet32_ethtool_test, | |
945 | .phys_id = pcnet32_phys_id, | |
946 | .get_regs_len = pcnet32_get_regs_len, | |
947 | .get_regs = pcnet32_get_regs, | |
948 | .get_perm_addr = ethtool_op_get_perm_addr, | |
1da177e4 LT |
949 | }; |
950 | ||
951 | /* only probes for non-PCI devices, the rest are handled by | |
952 | * pci_register_driver via pcnet32_probe_pci */ | |
953 | ||
dcaf9769 | 954 | static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist) |
1da177e4 | 955 | { |
4a5e8e29 JG |
956 | unsigned int *port, ioaddr; |
957 | ||
958 | /* search for PCnet32 VLB cards at known addresses */ | |
959 | for (port = pcnet32_portlist; (ioaddr = *port); port++) { | |
960 | if (request_region | |
961 | (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { | |
962 | /* check if there is really a pcnet chip on that ioaddr */ | |
963 | if ((inb(ioaddr + 14) == 0x57) | |
964 | && (inb(ioaddr + 15) == 0x57)) { | |
965 | pcnet32_probe1(ioaddr, 0, NULL); | |
966 | } else { | |
967 | release_region(ioaddr, PCNET32_TOTAL_SIZE); | |
968 | } | |
969 | } | |
970 | } | |
1da177e4 LT |
971 | } |
972 | ||
1da177e4 LT |
973 | static int __devinit |
974 | pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) | |
975 | { | |
4a5e8e29 JG |
976 | unsigned long ioaddr; |
977 | int err; | |
978 | ||
979 | err = pci_enable_device(pdev); | |
980 | if (err < 0) { | |
981 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
982 | printk(KERN_ERR PFX | |
983 | "failed to enable device -- err=%d\n", err); | |
984 | return err; | |
985 | } | |
986 | pci_set_master(pdev); | |
987 | ||
988 | ioaddr = pci_resource_start(pdev, 0); | |
989 | if (!ioaddr) { | |
990 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
991 | printk(KERN_ERR PFX | |
992 | "card has no PCI IO resources, aborting\n"); | |
993 | return -ENODEV; | |
994 | } | |
1da177e4 | 995 | |
4a5e8e29 JG |
996 | if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) { |
997 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
998 | printk(KERN_ERR PFX | |
999 | "architecture does not support 32bit PCI busmaster DMA\n"); | |
1000 | return -ENODEV; | |
1001 | } | |
1002 | if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") == | |
1003 | NULL) { | |
1004 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1005 | printk(KERN_ERR PFX | |
1006 | "io address range already allocated\n"); | |
1007 | return -EBUSY; | |
1008 | } | |
1da177e4 | 1009 | |
4a5e8e29 JG |
1010 | err = pcnet32_probe1(ioaddr, 1, pdev); |
1011 | if (err < 0) { | |
1012 | pci_disable_device(pdev); | |
1013 | } | |
1014 | return err; | |
1da177e4 LT |
1015 | } |
1016 | ||
1da177e4 LT |
1017 | /* pcnet32_probe1 |
1018 | * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. | |
1019 | * pdev will be NULL when called from pcnet32_probe_vlbus. | |
1020 | */ | |
1021 | static int __devinit | |
1022 | pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) | |
1023 | { | |
4a5e8e29 JG |
1024 | struct pcnet32_private *lp; |
1025 | dma_addr_t lp_dma_addr; | |
1026 | int i, media; | |
1027 | int fdx, mii, fset, dxsuflo; | |
1028 | int chip_version; | |
1029 | char *chipname; | |
1030 | struct net_device *dev; | |
1031 | struct pcnet32_access *a = NULL; | |
1032 | u8 promaddr[6]; | |
1033 | int ret = -ENODEV; | |
1034 | ||
1035 | /* reset the chip */ | |
1036 | pcnet32_wio_reset(ioaddr); | |
1037 | ||
1038 | /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ | |
1039 | if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { | |
1040 | a = &pcnet32_wio; | |
1041 | } else { | |
1042 | pcnet32_dwio_reset(ioaddr); | |
1043 | if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 | |
1044 | && pcnet32_dwio_check(ioaddr)) { | |
1045 | a = &pcnet32_dwio; | |
1046 | } else | |
1047 | goto err_release_region; | |
1048 | } | |
1049 | ||
1050 | chip_version = | |
1051 | a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); | |
1052 | if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) | |
1053 | printk(KERN_INFO " PCnet chip version is %#x.\n", | |
1054 | chip_version); | |
1055 | if ((chip_version & 0xfff) != 0x003) { | |
1056 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1057 | printk(KERN_INFO PFX "Unsupported chip version.\n"); | |
1058 | goto err_release_region; | |
1059 | } | |
1060 | ||
1061 | /* initialize variables */ | |
1062 | fdx = mii = fset = dxsuflo = 0; | |
1063 | chip_version = (chip_version >> 12) & 0xffff; | |
1064 | ||
1065 | switch (chip_version) { | |
1066 | case 0x2420: | |
1067 | chipname = "PCnet/PCI 79C970"; /* PCI */ | |
1068 | break; | |
1069 | case 0x2430: | |
1070 | if (shared) | |
1071 | chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ | |
1072 | else | |
1073 | chipname = "PCnet/32 79C965"; /* 486/VL bus */ | |
1074 | break; | |
1075 | case 0x2621: | |
1076 | chipname = "PCnet/PCI II 79C970A"; /* PCI */ | |
1077 | fdx = 1; | |
1078 | break; | |
1079 | case 0x2623: | |
1080 | chipname = "PCnet/FAST 79C971"; /* PCI */ | |
1081 | fdx = 1; | |
1082 | mii = 1; | |
1083 | fset = 1; | |
1084 | break; | |
1085 | case 0x2624: | |
1086 | chipname = "PCnet/FAST+ 79C972"; /* PCI */ | |
1087 | fdx = 1; | |
1088 | mii = 1; | |
1089 | fset = 1; | |
1090 | break; | |
1091 | case 0x2625: | |
1092 | chipname = "PCnet/FAST III 79C973"; /* PCI */ | |
1093 | fdx = 1; | |
1094 | mii = 1; | |
1095 | break; | |
1096 | case 0x2626: | |
1097 | chipname = "PCnet/Home 79C978"; /* PCI */ | |
1098 | fdx = 1; | |
1099 | /* | |
1100 | * This is based on specs published at www.amd.com. This section | |
1101 | * assumes that a card with a 79C978 wants to go into standard | |
1102 | * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, | |
1103 | * and the module option homepna=1 can select this instead. | |
1104 | */ | |
1105 | media = a->read_bcr(ioaddr, 49); | |
1106 | media &= ~3; /* default to 10Mb ethernet */ | |
1107 | if (cards_found < MAX_UNITS && homepna[cards_found]) | |
1108 | media |= 1; /* switch to home wiring mode */ | |
1109 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1110 | printk(KERN_DEBUG PFX "media set to %sMbit mode.\n", | |
1111 | (media & 1) ? "1" : "10"); | |
1112 | a->write_bcr(ioaddr, 49, media); | |
1113 | break; | |
1114 | case 0x2627: | |
1115 | chipname = "PCnet/FAST III 79C975"; /* PCI */ | |
1116 | fdx = 1; | |
1117 | mii = 1; | |
1118 | break; | |
1119 | case 0x2628: | |
1120 | chipname = "PCnet/PRO 79C976"; | |
1121 | fdx = 1; | |
1122 | mii = 1; | |
1123 | break; | |
1124 | default: | |
1125 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1126 | printk(KERN_INFO PFX | |
1127 | "PCnet version %#x, no PCnet32 chip.\n", | |
1128 | chip_version); | |
1129 | goto err_release_region; | |
1130 | } | |
1131 | ||
1da177e4 | 1132 | /* |
4a5e8e29 JG |
1133 | * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit |
1134 | * starting until the packet is loaded. Strike one for reliability, lose | |
1135 | * one for latency - although on PCI this isnt a big loss. Older chips | |
1136 | * have FIFO's smaller than a packet, so you can't do this. | |
1137 | * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. | |
1da177e4 | 1138 | */ |
4a5e8e29 JG |
1139 | |
1140 | if (fset) { | |
1141 | a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); | |
1142 | a->write_csr(ioaddr, 80, | |
1143 | (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); | |
1144 | dxsuflo = 1; | |
1145 | } | |
1146 | ||
1147 | dev = alloc_etherdev(0); | |
1148 | if (!dev) { | |
1149 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1150 | printk(KERN_ERR PFX "Memory allocation failed.\n"); | |
1151 | ret = -ENOMEM; | |
1152 | goto err_release_region; | |
1153 | } | |
1154 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1155 | ||
1da177e4 | 1156 | if (pcnet32_debug & NETIF_MSG_PROBE) |
4a5e8e29 JG |
1157 | printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr); |
1158 | ||
1159 | /* In most chips, after a chip reset, the ethernet address is read from the | |
1160 | * station address PROM at the base address and programmed into the | |
1161 | * "Physical Address Registers" CSR12-14. | |
1162 | * As a precautionary measure, we read the PROM values and complain if | |
bc0e1fc9 LV |
1163 | * they disagree with the CSRs. If they miscompare, and the PROM addr |
1164 | * is valid, then the PROM addr is used. | |
4a5e8e29 JG |
1165 | */ |
1166 | for (i = 0; i < 3; i++) { | |
1167 | unsigned int val; | |
1168 | val = a->read_csr(ioaddr, i + 12) & 0x0ffff; | |
1169 | /* There may be endianness issues here. */ | |
1170 | dev->dev_addr[2 * i] = val & 0x0ff; | |
1171 | dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff; | |
1172 | } | |
1173 | ||
1174 | /* read PROM address and compare with CSR address */ | |
1da177e4 | 1175 | for (i = 0; i < 6; i++) |
4a5e8e29 JG |
1176 | promaddr[i] = inb(ioaddr + i); |
1177 | ||
1178 | if (memcmp(promaddr, dev->dev_addr, 6) | |
1179 | || !is_valid_ether_addr(dev->dev_addr)) { | |
1180 | if (is_valid_ether_addr(promaddr)) { | |
1181 | if (pcnet32_debug & NETIF_MSG_PROBE) { | |
1182 | printk(" warning: CSR address invalid,\n"); | |
1183 | printk(KERN_INFO | |
1184 | " using instead PROM address of"); | |
1185 | } | |
1186 | memcpy(dev->dev_addr, promaddr, 6); | |
1187 | } | |
1188 | } | |
1189 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
1190 | ||
1191 | /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ | |
1192 | if (!is_valid_ether_addr(dev->perm_addr)) | |
1193 | memset(dev->dev_addr, 0, sizeof(dev->dev_addr)); | |
1194 | ||
1195 | if (pcnet32_debug & NETIF_MSG_PROBE) { | |
1196 | for (i = 0; i < 6; i++) | |
1197 | printk(" %2.2x", dev->dev_addr[i]); | |
1198 | ||
1199 | /* Version 0x2623 and 0x2624 */ | |
1200 | if (((chip_version + 1) & 0xfffe) == 0x2624) { | |
1201 | i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ | |
1202 | printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i); | |
1203 | switch (i >> 10) { | |
1204 | case 0: | |
1205 | printk(" 20 bytes,"); | |
1206 | break; | |
1207 | case 1: | |
1208 | printk(" 64 bytes,"); | |
1209 | break; | |
1210 | case 2: | |
1211 | printk(" 128 bytes,"); | |
1212 | break; | |
1213 | case 3: | |
1214 | printk("~220 bytes,"); | |
1215 | break; | |
1216 | } | |
1217 | i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ | |
1218 | printk(" BCR18(%x):", i & 0xffff); | |
1219 | if (i & (1 << 5)) | |
1220 | printk("BurstWrEn "); | |
1221 | if (i & (1 << 6)) | |
1222 | printk("BurstRdEn "); | |
1223 | if (i & (1 << 7)) | |
1224 | printk("DWordIO "); | |
1225 | if (i & (1 << 11)) | |
1226 | printk("NoUFlow "); | |
1227 | i = a->read_bcr(ioaddr, 25); | |
1228 | printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8); | |
1229 | i = a->read_bcr(ioaddr, 26); | |
1230 | printk(" SRAM_BND=0x%04x,", i << 8); | |
1231 | i = a->read_bcr(ioaddr, 27); | |
1232 | if (i & (1 << 14)) | |
1233 | printk("LowLatRx"); | |
1234 | } | |
1235 | } | |
1236 | ||
1237 | dev->base_addr = ioaddr; | |
1238 | /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */ | |
1239 | if ((lp = | |
1240 | pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) { | |
1241 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1242 | printk(KERN_ERR PFX | |
1243 | "Consistent memory allocation failed.\n"); | |
1244 | ret = -ENOMEM; | |
1245 | goto err_free_netdev; | |
1246 | } | |
1247 | ||
1248 | memset(lp, 0, sizeof(*lp)); | |
1249 | lp->dma_addr = lp_dma_addr; | |
1250 | lp->pci_dev = pdev; | |
1251 | ||
1252 | spin_lock_init(&lp->lock); | |
1253 | ||
1254 | SET_MODULE_OWNER(dev); | |
1255 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1256 | dev->priv = lp; | |
1257 | lp->name = chipname; | |
1258 | lp->shared_irq = shared; | |
1259 | lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ | |
1260 | lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ | |
1261 | lp->tx_mod_mask = lp->tx_ring_size - 1; | |
1262 | lp->rx_mod_mask = lp->rx_ring_size - 1; | |
1263 | lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); | |
1264 | lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); | |
1265 | lp->mii_if.full_duplex = fdx; | |
1266 | lp->mii_if.phy_id_mask = 0x1f; | |
1267 | lp->mii_if.reg_num_mask = 0x1f; | |
1268 | lp->dxsuflo = dxsuflo; | |
1269 | lp->mii = mii; | |
1270 | lp->msg_enable = pcnet32_debug; | |
1271 | if ((cards_found >= MAX_UNITS) | |
1272 | || (options[cards_found] > sizeof(options_mapping))) | |
1273 | lp->options = PCNET32_PORT_ASEL; | |
1274 | else | |
1275 | lp->options = options_mapping[options[cards_found]]; | |
1276 | lp->mii_if.dev = dev; | |
1277 | lp->mii_if.mdio_read = mdio_read; | |
1278 | lp->mii_if.mdio_write = mdio_write; | |
1279 | ||
1280 | if (fdx && !(lp->options & PCNET32_PORT_ASEL) && | |
1281 | ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) | |
1282 | lp->options |= PCNET32_PORT_FD; | |
1283 | ||
1284 | if (!a) { | |
1285 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1286 | printk(KERN_ERR PFX "No access methods\n"); | |
1287 | ret = -ENODEV; | |
1288 | goto err_free_consistent; | |
1289 | } | |
1290 | lp->a = *a; | |
1291 | ||
1292 | /* prior to register_netdev, dev->name is not yet correct */ | |
1293 | if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { | |
1294 | ret = -ENOMEM; | |
1295 | goto err_free_ring; | |
1296 | } | |
1297 | /* detect special T1/E1 WAN card by checking for MAC address */ | |
1298 | if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 | |
1da177e4 | 1299 | && dev->dev_addr[2] == 0x75) |
4a5e8e29 | 1300 | lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; |
1da177e4 | 1301 | |
4a5e8e29 JG |
1302 | lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */ |
1303 | lp->init_block.tlen_rlen = | |
1304 | le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits); | |
1305 | for (i = 0; i < 6; i++) | |
1306 | lp->init_block.phys_addr[i] = dev->dev_addr[i]; | |
1307 | lp->init_block.filter[0] = 0x00000000; | |
1308 | lp->init_block.filter[1] = 0x00000000; | |
1309 | lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr); | |
1310 | lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr); | |
1311 | ||
1312 | /* switch pcnet32 to 32bit mode */ | |
1313 | a->write_bcr(ioaddr, 20, 2); | |
1314 | ||
1315 | a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, | |
1316 | init_block)) & 0xffff); | |
1317 | a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, | |
1318 | init_block)) >> 16); | |
1319 | ||
1320 | if (pdev) { /* use the IRQ provided by PCI */ | |
1321 | dev->irq = pdev->irq; | |
1322 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1323 | printk(" assigned IRQ %d.\n", dev->irq); | |
1324 | } else { | |
1325 | unsigned long irq_mask = probe_irq_on(); | |
1326 | ||
1327 | /* | |
1328 | * To auto-IRQ we enable the initialization-done and DMA error | |
1329 | * interrupts. For ISA boards we get a DMA error, but VLB and PCI | |
1330 | * boards will work. | |
1331 | */ | |
1332 | /* Trigger an initialization just for the interrupt. */ | |
1333 | a->write_csr(ioaddr, 0, 0x41); | |
1334 | mdelay(1); | |
1335 | ||
1336 | dev->irq = probe_irq_off(irq_mask); | |
1337 | if (!dev->irq) { | |
1338 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1339 | printk(", failed to detect IRQ line.\n"); | |
1340 | ret = -ENODEV; | |
1341 | goto err_free_ring; | |
1342 | } | |
1343 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1344 | printk(", probed IRQ %d.\n", dev->irq); | |
1345 | } | |
1da177e4 | 1346 | |
4a5e8e29 JG |
1347 | /* Set the mii phy_id so that we can query the link state */ |
1348 | if (lp->mii) { | |
1349 | /* lp->phycount and lp->phymask are set to 0 by memset above */ | |
1350 | ||
1351 | lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f; | |
1352 | /* scan for PHYs */ | |
1353 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { | |
1354 | unsigned short id1, id2; | |
1355 | ||
1356 | id1 = mdio_read(dev, i, MII_PHYSID1); | |
1357 | if (id1 == 0xffff) | |
1358 | continue; | |
1359 | id2 = mdio_read(dev, i, MII_PHYSID2); | |
1360 | if (id2 == 0xffff) | |
1361 | continue; | |
1362 | if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624) | |
1363 | continue; /* 79C971 & 79C972 have phantom phy at id 31 */ | |
1364 | lp->phycount++; | |
1365 | lp->phymask |= (1 << i); | |
1366 | lp->mii_if.phy_id = i; | |
1367 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1368 | printk(KERN_INFO PFX | |
1369 | "Found PHY %04x:%04x at address %d.\n", | |
1370 | id1, id2, i); | |
1371 | } | |
1372 | lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5); | |
1373 | if (lp->phycount > 1) { | |
1374 | lp->options |= PCNET32_PORT_MII; | |
1375 | } | |
1da177e4 | 1376 | } |
4a5e8e29 JG |
1377 | |
1378 | init_timer(&lp->watchdog_timer); | |
1379 | lp->watchdog_timer.data = (unsigned long)dev; | |
1380 | lp->watchdog_timer.function = (void *)&pcnet32_watchdog; | |
1381 | ||
1382 | /* The PCNET32-specific entries in the device structure. */ | |
1383 | dev->open = &pcnet32_open; | |
1384 | dev->hard_start_xmit = &pcnet32_start_xmit; | |
1385 | dev->stop = &pcnet32_close; | |
1386 | dev->get_stats = &pcnet32_get_stats; | |
1387 | dev->set_multicast_list = &pcnet32_set_multicast_list; | |
1388 | dev->do_ioctl = &pcnet32_ioctl; | |
1389 | dev->ethtool_ops = &pcnet32_ethtool_ops; | |
1390 | dev->tx_timeout = pcnet32_tx_timeout; | |
1391 | dev->watchdog_timeo = (5 * HZ); | |
1da177e4 LT |
1392 | |
1393 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4a5e8e29 | 1394 | dev->poll_controller = pcnet32_poll_controller; |
1da177e4 LT |
1395 | #endif |
1396 | ||
4a5e8e29 JG |
1397 | /* Fill in the generic fields of the device structure. */ |
1398 | if (register_netdev(dev)) | |
1399 | goto err_free_ring; | |
1400 | ||
1401 | if (pdev) { | |
1402 | pci_set_drvdata(pdev, dev); | |
1403 | } else { | |
1404 | lp->next = pcnet32_dev; | |
1405 | pcnet32_dev = dev; | |
1406 | } | |
1407 | ||
1408 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1409 | printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name); | |
1410 | cards_found++; | |
1411 | ||
1412 | /* enable LED writes */ | |
1413 | a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); | |
1da177e4 | 1414 | |
4a5e8e29 JG |
1415 | return 0; |
1416 | ||
1417 | err_free_ring: | |
1418 | pcnet32_free_ring(dev); | |
1419 | err_free_consistent: | |
1420 | pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr); | |
1421 | err_free_netdev: | |
1422 | free_netdev(dev); | |
1423 | err_release_region: | |
1424 | release_region(ioaddr, PCNET32_TOTAL_SIZE); | |
1425 | return ret; | |
1426 | } | |
1da177e4 | 1427 | |
a88c844c DF |
1428 | /* if any allocation fails, caller must also call pcnet32_free_ring */ |
1429 | static int pcnet32_alloc_ring(struct net_device *dev, char *name) | |
eabf0415 | 1430 | { |
4a5e8e29 | 1431 | struct pcnet32_private *lp = dev->priv; |
eabf0415 | 1432 | |
4a5e8e29 JG |
1433 | lp->tx_ring = pci_alloc_consistent(lp->pci_dev, |
1434 | sizeof(struct pcnet32_tx_head) * | |
1435 | lp->tx_ring_size, | |
1436 | &lp->tx_ring_dma_addr); | |
1437 | if (lp->tx_ring == NULL) { | |
1438 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1439 | printk("\n" KERN_ERR PFX | |
1440 | "%s: Consistent memory allocation failed.\n", | |
1441 | name); | |
1442 | return -ENOMEM; | |
1443 | } | |
eabf0415 | 1444 | |
4a5e8e29 JG |
1445 | lp->rx_ring = pci_alloc_consistent(lp->pci_dev, |
1446 | sizeof(struct pcnet32_rx_head) * | |
1447 | lp->rx_ring_size, | |
1448 | &lp->rx_ring_dma_addr); | |
1449 | if (lp->rx_ring == NULL) { | |
1450 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1451 | printk("\n" KERN_ERR PFX | |
1452 | "%s: Consistent memory allocation failed.\n", | |
1453 | name); | |
1454 | return -ENOMEM; | |
1455 | } | |
eabf0415 | 1456 | |
4a5e8e29 JG |
1457 | lp->tx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->tx_ring_size, |
1458 | GFP_ATOMIC); | |
1459 | if (!lp->tx_dma_addr) { | |
1460 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1461 | printk("\n" KERN_ERR PFX | |
1462 | "%s: Memory allocation failed.\n", name); | |
1463 | return -ENOMEM; | |
1464 | } | |
1465 | memset(lp->tx_dma_addr, 0, sizeof(dma_addr_t) * lp->tx_ring_size); | |
1466 | ||
1467 | lp->rx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->rx_ring_size, | |
1468 | GFP_ATOMIC); | |
1469 | if (!lp->rx_dma_addr) { | |
1470 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1471 | printk("\n" KERN_ERR PFX | |
1472 | "%s: Memory allocation failed.\n", name); | |
1473 | return -ENOMEM; | |
1474 | } | |
1475 | memset(lp->rx_dma_addr, 0, sizeof(dma_addr_t) * lp->rx_ring_size); | |
1476 | ||
1477 | lp->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->tx_ring_size, | |
1478 | GFP_ATOMIC); | |
1479 | if (!lp->tx_skbuff) { | |
1480 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1481 | printk("\n" KERN_ERR PFX | |
1482 | "%s: Memory allocation failed.\n", name); | |
1483 | return -ENOMEM; | |
1484 | } | |
1485 | memset(lp->tx_skbuff, 0, sizeof(struct sk_buff *) * lp->tx_ring_size); | |
1486 | ||
1487 | lp->rx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->rx_ring_size, | |
1488 | GFP_ATOMIC); | |
1489 | if (!lp->rx_skbuff) { | |
1490 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1491 | printk("\n" KERN_ERR PFX | |
1492 | "%s: Memory allocation failed.\n", name); | |
1493 | return -ENOMEM; | |
1494 | } | |
1495 | memset(lp->rx_skbuff, 0, sizeof(struct sk_buff *) * lp->rx_ring_size); | |
1496 | ||
1497 | return 0; | |
1498 | } | |
eabf0415 HWL |
1499 | |
1500 | static void pcnet32_free_ring(struct net_device *dev) | |
1501 | { | |
4a5e8e29 | 1502 | struct pcnet32_private *lp = dev->priv; |
eabf0415 | 1503 | |
4a5e8e29 JG |
1504 | kfree(lp->tx_skbuff); |
1505 | lp->tx_skbuff = NULL; | |
eabf0415 | 1506 | |
4a5e8e29 JG |
1507 | kfree(lp->rx_skbuff); |
1508 | lp->rx_skbuff = NULL; | |
eabf0415 | 1509 | |
4a5e8e29 JG |
1510 | kfree(lp->tx_dma_addr); |
1511 | lp->tx_dma_addr = NULL; | |
eabf0415 | 1512 | |
4a5e8e29 JG |
1513 | kfree(lp->rx_dma_addr); |
1514 | lp->rx_dma_addr = NULL; | |
eabf0415 | 1515 | |
4a5e8e29 JG |
1516 | if (lp->tx_ring) { |
1517 | pci_free_consistent(lp->pci_dev, | |
1518 | sizeof(struct pcnet32_tx_head) * | |
1519 | lp->tx_ring_size, lp->tx_ring, | |
1520 | lp->tx_ring_dma_addr); | |
1521 | lp->tx_ring = NULL; | |
1522 | } | |
eabf0415 | 1523 | |
4a5e8e29 JG |
1524 | if (lp->rx_ring) { |
1525 | pci_free_consistent(lp->pci_dev, | |
1526 | sizeof(struct pcnet32_rx_head) * | |
1527 | lp->rx_ring_size, lp->rx_ring, | |
1528 | lp->rx_ring_dma_addr); | |
1529 | lp->rx_ring = NULL; | |
1530 | } | |
eabf0415 HWL |
1531 | } |
1532 | ||
4a5e8e29 | 1533 | static int pcnet32_open(struct net_device *dev) |
1da177e4 | 1534 | { |
4a5e8e29 JG |
1535 | struct pcnet32_private *lp = dev->priv; |
1536 | unsigned long ioaddr = dev->base_addr; | |
1537 | u16 val; | |
1538 | int i; | |
1539 | int rc; | |
1540 | unsigned long flags; | |
1541 | ||
1542 | if (request_irq(dev->irq, &pcnet32_interrupt, | |
1fb9df5d | 1543 | lp->shared_irq ? IRQF_SHARED : 0, dev->name, |
4a5e8e29 JG |
1544 | (void *)dev)) { |
1545 | return -EAGAIN; | |
1546 | } | |
1547 | ||
1548 | spin_lock_irqsave(&lp->lock, flags); | |
1549 | /* Check for a valid station address */ | |
1550 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
1551 | rc = -EINVAL; | |
1552 | goto err_free_irq; | |
1553 | } | |
1554 | ||
1555 | /* Reset the PCNET32 */ | |
1556 | lp->a.reset(ioaddr); | |
1557 | ||
1558 | /* switch pcnet32 to 32bit mode */ | |
1559 | lp->a.write_bcr(ioaddr, 20, 2); | |
1560 | ||
1561 | if (netif_msg_ifup(lp)) | |
1562 | printk(KERN_DEBUG | |
1563 | "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n", | |
1564 | dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr), | |
1565 | (u32) (lp->rx_ring_dma_addr), | |
1566 | (u32) (lp->dma_addr + | |
1567 | offsetof(struct pcnet32_private, init_block))); | |
1568 | ||
1569 | /* set/reset autoselect bit */ | |
1570 | val = lp->a.read_bcr(ioaddr, 2) & ~2; | |
1571 | if (lp->options & PCNET32_PORT_ASEL) | |
1da177e4 | 1572 | val |= 2; |
4a5e8e29 JG |
1573 | lp->a.write_bcr(ioaddr, 2, val); |
1574 | ||
1575 | /* handle full duplex setting */ | |
1576 | if (lp->mii_if.full_duplex) { | |
1577 | val = lp->a.read_bcr(ioaddr, 9) & ~3; | |
1578 | if (lp->options & PCNET32_PORT_FD) { | |
1579 | val |= 1; | |
1580 | if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) | |
1581 | val |= 2; | |
1582 | } else if (lp->options & PCNET32_PORT_ASEL) { | |
1583 | /* workaround of xSeries250, turn on for 79C975 only */ | |
1584 | i = ((lp->a.read_csr(ioaddr, 88) | | |
1585 | (lp->a. | |
1586 | read_csr(ioaddr, 89) << 16)) >> 12) & 0xffff; | |
1587 | if (i == 0x2627) | |
1588 | val |= 3; | |
1589 | } | |
1590 | lp->a.write_bcr(ioaddr, 9, val); | |
1591 | } | |
1592 | ||
1593 | /* set/reset GPSI bit in test register */ | |
1594 | val = lp->a.read_csr(ioaddr, 124) & ~0x10; | |
1595 | if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) | |
1596 | val |= 0x10; | |
1597 | lp->a.write_csr(ioaddr, 124, val); | |
1598 | ||
1599 | /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ | |
1600 | if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT && | |
2964bbd7 DF |
1601 | (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || |
1602 | lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { | |
ac62ef04 | 1603 | if (lp->options & PCNET32_PORT_ASEL) { |
4a5e8e29 JG |
1604 | lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; |
1605 | if (netif_msg_link(lp)) | |
1606 | printk(KERN_DEBUG | |
1607 | "%s: Setting 100Mb-Full Duplex.\n", | |
1608 | dev->name); | |
1609 | } | |
1610 | } | |
1611 | if (lp->phycount < 2) { | |
1612 | /* | |
1613 | * 24 Jun 2004 according AMD, in order to change the PHY, | |
1614 | * DANAS (or DISPM for 79C976) must be set; then select the speed, | |
1615 | * duplex, and/or enable auto negotiation, and clear DANAS | |
1616 | */ | |
1617 | if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { | |
1618 | lp->a.write_bcr(ioaddr, 32, | |
1619 | lp->a.read_bcr(ioaddr, 32) | 0x0080); | |
1620 | /* disable Auto Negotiation, set 10Mpbs, HD */ | |
1621 | val = lp->a.read_bcr(ioaddr, 32) & ~0xb8; | |
1622 | if (lp->options & PCNET32_PORT_FD) | |
1623 | val |= 0x10; | |
1624 | if (lp->options & PCNET32_PORT_100) | |
1625 | val |= 0x08; | |
1626 | lp->a.write_bcr(ioaddr, 32, val); | |
1627 | } else { | |
1628 | if (lp->options & PCNET32_PORT_ASEL) { | |
1629 | lp->a.write_bcr(ioaddr, 32, | |
1630 | lp->a.read_bcr(ioaddr, | |
1631 | 32) | 0x0080); | |
1632 | /* enable auto negotiate, setup, disable fd */ | |
1633 | val = lp->a.read_bcr(ioaddr, 32) & ~0x98; | |
1634 | val |= 0x20; | |
1635 | lp->a.write_bcr(ioaddr, 32, val); | |
1636 | } | |
1637 | } | |
1638 | } else { | |
1639 | int first_phy = -1; | |
1640 | u16 bmcr; | |
1641 | u32 bcr9; | |
1642 | struct ethtool_cmd ecmd; | |
1643 | ||
1644 | /* | |
1645 | * There is really no good other way to handle multiple PHYs | |
1646 | * other than turning off all automatics | |
1647 | */ | |
1648 | val = lp->a.read_bcr(ioaddr, 2); | |
1649 | lp->a.write_bcr(ioaddr, 2, val & ~2); | |
1650 | val = lp->a.read_bcr(ioaddr, 32); | |
1651 | lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ | |
1652 | ||
1653 | if (!(lp->options & PCNET32_PORT_ASEL)) { | |
1654 | /* setup ecmd */ | |
1655 | ecmd.port = PORT_MII; | |
1656 | ecmd.transceiver = XCVR_INTERNAL; | |
1657 | ecmd.autoneg = AUTONEG_DISABLE; | |
1658 | ecmd.speed = | |
1659 | lp-> | |
1660 | options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10; | |
1661 | bcr9 = lp->a.read_bcr(ioaddr, 9); | |
1662 | ||
1663 | if (lp->options & PCNET32_PORT_FD) { | |
1664 | ecmd.duplex = DUPLEX_FULL; | |
1665 | bcr9 |= (1 << 0); | |
1666 | } else { | |
1667 | ecmd.duplex = DUPLEX_HALF; | |
1668 | bcr9 |= ~(1 << 0); | |
1669 | } | |
1670 | lp->a.write_bcr(ioaddr, 9, bcr9); | |
ac62ef04 | 1671 | } |
4a5e8e29 JG |
1672 | |
1673 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { | |
1674 | if (lp->phymask & (1 << i)) { | |
1675 | /* isolate all but the first PHY */ | |
1676 | bmcr = mdio_read(dev, i, MII_BMCR); | |
1677 | if (first_phy == -1) { | |
1678 | first_phy = i; | |
1679 | mdio_write(dev, i, MII_BMCR, | |
1680 | bmcr & ~BMCR_ISOLATE); | |
1681 | } else { | |
1682 | mdio_write(dev, i, MII_BMCR, | |
1683 | bmcr | BMCR_ISOLATE); | |
1684 | } | |
1685 | /* use mii_ethtool_sset to setup PHY */ | |
1686 | lp->mii_if.phy_id = i; | |
1687 | ecmd.phy_address = i; | |
1688 | if (lp->options & PCNET32_PORT_ASEL) { | |
1689 | mii_ethtool_gset(&lp->mii_if, &ecmd); | |
1690 | ecmd.autoneg = AUTONEG_ENABLE; | |
1691 | } | |
1692 | mii_ethtool_sset(&lp->mii_if, &ecmd); | |
1693 | } | |
1694 | } | |
1695 | lp->mii_if.phy_id = first_phy; | |
1696 | if (netif_msg_link(lp)) | |
1697 | printk(KERN_INFO "%s: Using PHY number %d.\n", | |
1698 | dev->name, first_phy); | |
1699 | } | |
1da177e4 LT |
1700 | |
1701 | #ifdef DO_DXSUFLO | |
4a5e8e29 JG |
1702 | if (lp->dxsuflo) { /* Disable transmit stop on underflow */ |
1703 | val = lp->a.read_csr(ioaddr, 3); | |
1704 | val |= 0x40; | |
1705 | lp->a.write_csr(ioaddr, 3, val); | |
1706 | } | |
1da177e4 LT |
1707 | #endif |
1708 | ||
4a5e8e29 JG |
1709 | lp->init_block.mode = |
1710 | le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); | |
1711 | pcnet32_load_multicast(dev); | |
1712 | ||
1713 | if (pcnet32_init_ring(dev)) { | |
1714 | rc = -ENOMEM; | |
1715 | goto err_free_ring; | |
1716 | } | |
1717 | ||
1718 | /* Re-initialize the PCNET32, and start it when done. */ | |
1719 | lp->a.write_csr(ioaddr, 1, (lp->dma_addr + | |
1720 | offsetof(struct pcnet32_private, | |
1721 | init_block)) & 0xffff); | |
1722 | lp->a.write_csr(ioaddr, 2, | |
1723 | (lp->dma_addr + | |
1724 | offsetof(struct pcnet32_private, init_block)) >> 16); | |
1725 | ||
1726 | lp->a.write_csr(ioaddr, 4, 0x0915); | |
1727 | lp->a.write_csr(ioaddr, 0, 0x0001); | |
1728 | ||
1729 | netif_start_queue(dev); | |
1730 | ||
1731 | /* Print the link status and start the watchdog */ | |
1732 | pcnet32_check_media(dev, 1); | |
1733 | mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT); | |
1734 | ||
1735 | i = 0; | |
1736 | while (i++ < 100) | |
1737 | if (lp->a.read_csr(ioaddr, 0) & 0x0100) | |
1738 | break; | |
1739 | /* | |
1740 | * We used to clear the InitDone bit, 0x0100, here but Mark Stockton | |
1741 | * reports that doing so triggers a bug in the '974. | |
1742 | */ | |
1743 | lp->a.write_csr(ioaddr, 0, 0x0042); | |
1744 | ||
1745 | if (netif_msg_ifup(lp)) | |
1746 | printk(KERN_DEBUG | |
1747 | "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n", | |
1748 | dev->name, i, | |
1749 | (u32) (lp->dma_addr + | |
1750 | offsetof(struct pcnet32_private, init_block)), | |
1751 | lp->a.read_csr(ioaddr, 0)); | |
1752 | ||
1753 | spin_unlock_irqrestore(&lp->lock, flags); | |
1754 | ||
1755 | return 0; /* Always succeed */ | |
1756 | ||
1757 | err_free_ring: | |
1758 | /* free any allocated skbuffs */ | |
1759 | for (i = 0; i < lp->rx_ring_size; i++) { | |
1760 | lp->rx_ring[i].status = 0; | |
1761 | if (lp->rx_skbuff[i]) { | |
1762 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], | |
1763 | PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE); | |
1764 | dev_kfree_skb(lp->rx_skbuff[i]); | |
1765 | } | |
1766 | lp->rx_skbuff[i] = NULL; | |
1767 | lp->rx_dma_addr[i] = 0; | |
1768 | } | |
1769 | ||
4a5e8e29 JG |
1770 | /* |
1771 | * Switch back to 16bit mode to avoid problems with dumb | |
1772 | * DOS packet driver after a warm reboot | |
1773 | */ | |
1774 | lp->a.write_bcr(ioaddr, 20, 4); | |
1775 | ||
1776 | err_free_irq: | |
1777 | spin_unlock_irqrestore(&lp->lock, flags); | |
1778 | free_irq(dev->irq, dev); | |
1779 | return rc; | |
1da177e4 LT |
1780 | } |
1781 | ||
1782 | /* | |
1783 | * The LANCE has been halted for one reason or another (busmaster memory | |
1784 | * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, | |
1785 | * etc.). Modern LANCE variants always reload their ring-buffer | |
1786 | * configuration when restarted, so we must reinitialize our ring | |
1787 | * context before restarting. As part of this reinitialization, | |
1788 | * find all packets still on the Tx ring and pretend that they had been | |
1789 | * sent (in effect, drop the packets on the floor) - the higher-level | |
1790 | * protocols will time out and retransmit. It'd be better to shuffle | |
1791 | * these skbs to a temp list and then actually re-Tx them after | |
1792 | * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com | |
1793 | */ | |
1794 | ||
4a5e8e29 | 1795 | static void pcnet32_purge_tx_ring(struct net_device *dev) |
1da177e4 | 1796 | { |
4a5e8e29 JG |
1797 | struct pcnet32_private *lp = dev->priv; |
1798 | int i; | |
1da177e4 | 1799 | |
4a5e8e29 JG |
1800 | for (i = 0; i < lp->tx_ring_size; i++) { |
1801 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ | |
1802 | wmb(); /* Make sure adapter sees owner change */ | |
1803 | if (lp->tx_skbuff[i]) { | |
1804 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], | |
1805 | lp->tx_skbuff[i]->len, | |
1806 | PCI_DMA_TODEVICE); | |
1807 | dev_kfree_skb_any(lp->tx_skbuff[i]); | |
1808 | } | |
1809 | lp->tx_skbuff[i] = NULL; | |
1810 | lp->tx_dma_addr[i] = 0; | |
1811 | } | |
1812 | } | |
1da177e4 LT |
1813 | |
1814 | /* Initialize the PCNET32 Rx and Tx rings. */ | |
4a5e8e29 | 1815 | static int pcnet32_init_ring(struct net_device *dev) |
1da177e4 | 1816 | { |
4a5e8e29 JG |
1817 | struct pcnet32_private *lp = dev->priv; |
1818 | int i; | |
1819 | ||
1820 | lp->tx_full = 0; | |
1821 | lp->cur_rx = lp->cur_tx = 0; | |
1822 | lp->dirty_rx = lp->dirty_tx = 0; | |
1823 | ||
1824 | for (i = 0; i < lp->rx_ring_size; i++) { | |
1825 | struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; | |
1826 | if (rx_skbuff == NULL) { | |
1827 | if (! | |
1828 | (rx_skbuff = lp->rx_skbuff[i] = | |
1829 | dev_alloc_skb(PKT_BUF_SZ))) { | |
1830 | /* there is not much, we can do at this point */ | |
1831 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1832 | printk(KERN_ERR | |
1833 | "%s: pcnet32_init_ring dev_alloc_skb failed.\n", | |
1834 | dev->name); | |
1835 | return -1; | |
1836 | } | |
1837 | skb_reserve(rx_skbuff, 2); | |
1838 | } | |
1839 | ||
1840 | rmb(); | |
1841 | if (lp->rx_dma_addr[i] == 0) | |
1842 | lp->rx_dma_addr[i] = | |
1843 | pci_map_single(lp->pci_dev, rx_skbuff->data, | |
1844 | PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE); | |
1845 | lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]); | |
1846 | lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ); | |
1847 | wmb(); /* Make sure owner changes after all others are visible */ | |
1848 | lp->rx_ring[i].status = le16_to_cpu(0x8000); | |
1849 | } | |
1850 | /* The Tx buffer address is filled in as needed, but we do need to clear | |
1851 | * the upper ownership bit. */ | |
1852 | for (i = 0; i < lp->tx_ring_size; i++) { | |
1853 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ | |
1854 | wmb(); /* Make sure adapter sees owner change */ | |
1855 | lp->tx_ring[i].base = 0; | |
1856 | lp->tx_dma_addr[i] = 0; | |
1857 | } | |
1858 | ||
1859 | lp->init_block.tlen_rlen = | |
1860 | le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits); | |
1861 | for (i = 0; i < 6; i++) | |
1862 | lp->init_block.phys_addr[i] = dev->dev_addr[i]; | |
1863 | lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr); | |
1864 | lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr); | |
1865 | wmb(); /* Make sure all changes are visible */ | |
1866 | return 0; | |
1da177e4 LT |
1867 | } |
1868 | ||
1869 | /* the pcnet32 has been issued a stop or reset. Wait for the stop bit | |
1870 | * then flush the pending transmit operations, re-initialize the ring, | |
1871 | * and tell the chip to initialize. | |
1872 | */ | |
4a5e8e29 | 1873 | static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) |
1da177e4 | 1874 | { |
4a5e8e29 JG |
1875 | struct pcnet32_private *lp = dev->priv; |
1876 | unsigned long ioaddr = dev->base_addr; | |
1877 | int i; | |
1da177e4 | 1878 | |
4a5e8e29 JG |
1879 | /* wait for stop */ |
1880 | for (i = 0; i < 100; i++) | |
1881 | if (lp->a.read_csr(ioaddr, 0) & 0x0004) | |
1882 | break; | |
1da177e4 | 1883 | |
4a5e8e29 JG |
1884 | if (i >= 100 && netif_msg_drv(lp)) |
1885 | printk(KERN_ERR | |
1886 | "%s: pcnet32_restart timed out waiting for stop.\n", | |
1887 | dev->name); | |
1da177e4 | 1888 | |
4a5e8e29 JG |
1889 | pcnet32_purge_tx_ring(dev); |
1890 | if (pcnet32_init_ring(dev)) | |
1891 | return; | |
1da177e4 | 1892 | |
4a5e8e29 JG |
1893 | /* ReInit Ring */ |
1894 | lp->a.write_csr(ioaddr, 0, 1); | |
1895 | i = 0; | |
1896 | while (i++ < 1000) | |
1897 | if (lp->a.read_csr(ioaddr, 0) & 0x0100) | |
1898 | break; | |
1da177e4 | 1899 | |
4a5e8e29 | 1900 | lp->a.write_csr(ioaddr, 0, csr0_bits); |
1da177e4 LT |
1901 | } |
1902 | ||
4a5e8e29 | 1903 | static void pcnet32_tx_timeout(struct net_device *dev) |
1da177e4 | 1904 | { |
4a5e8e29 JG |
1905 | struct pcnet32_private *lp = dev->priv; |
1906 | unsigned long ioaddr = dev->base_addr, flags; | |
1907 | ||
1908 | spin_lock_irqsave(&lp->lock, flags); | |
1909 | /* Transmitter timeout, serious problems. */ | |
1910 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1911 | printk(KERN_ERR | |
1912 | "%s: transmit timed out, status %4.4x, resetting.\n", | |
1913 | dev->name, lp->a.read_csr(ioaddr, 0)); | |
1914 | lp->a.write_csr(ioaddr, 0, 0x0004); | |
1915 | lp->stats.tx_errors++; | |
1916 | if (netif_msg_tx_err(lp)) { | |
1917 | int i; | |
1918 | printk(KERN_DEBUG | |
1919 | " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", | |
1920 | lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", | |
1921 | lp->cur_rx); | |
1922 | for (i = 0; i < lp->rx_ring_size; i++) | |
1923 | printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", | |
1924 | le32_to_cpu(lp->rx_ring[i].base), | |
1925 | (-le16_to_cpu(lp->rx_ring[i].buf_length)) & | |
1926 | 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length), | |
1927 | le16_to_cpu(lp->rx_ring[i].status)); | |
1928 | for (i = 0; i < lp->tx_ring_size; i++) | |
1929 | printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", | |
1930 | le32_to_cpu(lp->tx_ring[i].base), | |
1931 | (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, | |
1932 | le32_to_cpu(lp->tx_ring[i].misc), | |
1933 | le16_to_cpu(lp->tx_ring[i].status)); | |
1934 | printk("\n"); | |
1935 | } | |
1936 | pcnet32_restart(dev, 0x0042); | |
1da177e4 | 1937 | |
4a5e8e29 JG |
1938 | dev->trans_start = jiffies; |
1939 | netif_wake_queue(dev); | |
1da177e4 | 1940 | |
4a5e8e29 JG |
1941 | spin_unlock_irqrestore(&lp->lock, flags); |
1942 | } | |
1943 | ||
1944 | static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1da177e4 | 1945 | { |
4a5e8e29 JG |
1946 | struct pcnet32_private *lp = dev->priv; |
1947 | unsigned long ioaddr = dev->base_addr; | |
1948 | u16 status; | |
1949 | int entry; | |
1950 | unsigned long flags; | |
1da177e4 | 1951 | |
4a5e8e29 | 1952 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 1953 | |
4a5e8e29 JG |
1954 | if (netif_msg_tx_queued(lp)) { |
1955 | printk(KERN_DEBUG | |
1956 | "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n", | |
1957 | dev->name, lp->a.read_csr(ioaddr, 0)); | |
1958 | } | |
1da177e4 | 1959 | |
4a5e8e29 JG |
1960 | /* Default status -- will not enable Successful-TxDone |
1961 | * interrupt when that option is available to us. | |
1962 | */ | |
1963 | status = 0x8300; | |
1da177e4 | 1964 | |
4a5e8e29 | 1965 | /* Fill in a Tx ring entry */ |
1da177e4 | 1966 | |
4a5e8e29 JG |
1967 | /* Mask to ring buffer boundary. */ |
1968 | entry = lp->cur_tx & lp->tx_mod_mask; | |
1da177e4 | 1969 | |
4a5e8e29 JG |
1970 | /* Caution: the write order is important here, set the status |
1971 | * with the "ownership" bits last. */ | |
1da177e4 | 1972 | |
4a5e8e29 | 1973 | lp->tx_ring[entry].length = le16_to_cpu(-skb->len); |
1da177e4 | 1974 | |
4a5e8e29 | 1975 | lp->tx_ring[entry].misc = 0x00000000; |
1da177e4 | 1976 | |
4a5e8e29 JG |
1977 | lp->tx_skbuff[entry] = skb; |
1978 | lp->tx_dma_addr[entry] = | |
1979 | pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); | |
1980 | lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]); | |
1981 | wmb(); /* Make sure owner changes after all others are visible */ | |
1982 | lp->tx_ring[entry].status = le16_to_cpu(status); | |
1da177e4 | 1983 | |
4a5e8e29 JG |
1984 | lp->cur_tx++; |
1985 | lp->stats.tx_bytes += skb->len; | |
1da177e4 | 1986 | |
4a5e8e29 JG |
1987 | /* Trigger an immediate send poll. */ |
1988 | lp->a.write_csr(ioaddr, 0, 0x0048); | |
1da177e4 | 1989 | |
4a5e8e29 | 1990 | dev->trans_start = jiffies; |
1da177e4 | 1991 | |
4a5e8e29 JG |
1992 | if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { |
1993 | lp->tx_full = 1; | |
1994 | netif_stop_queue(dev); | |
1995 | } | |
1996 | spin_unlock_irqrestore(&lp->lock, flags); | |
1997 | return 0; | |
1da177e4 LT |
1998 | } |
1999 | ||
2000 | /* The PCNET32 interrupt handler. */ | |
2001 | static irqreturn_t | |
4a5e8e29 | 2002 | pcnet32_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
1da177e4 | 2003 | { |
4a5e8e29 JG |
2004 | struct net_device *dev = dev_id; |
2005 | struct pcnet32_private *lp; | |
2006 | unsigned long ioaddr; | |
2007 | u16 csr0, rap; | |
2008 | int boguscnt = max_interrupt_work; | |
2009 | int must_restart; | |
2010 | ||
2011 | if (!dev) { | |
2012 | if (pcnet32_debug & NETIF_MSG_INTR) | |
2013 | printk(KERN_DEBUG "%s(): irq %d for unknown device\n", | |
2014 | __FUNCTION__, irq); | |
2015 | return IRQ_NONE; | |
1da177e4 | 2016 | } |
1da177e4 | 2017 | |
4a5e8e29 JG |
2018 | ioaddr = dev->base_addr; |
2019 | lp = dev->priv; | |
1da177e4 | 2020 | |
4a5e8e29 JG |
2021 | spin_lock(&lp->lock); |
2022 | ||
2023 | rap = lp->a.read_rap(ioaddr); | |
2024 | while ((csr0 = lp->a.read_csr(ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) { | |
2025 | if (csr0 == 0xffff) { | |
2026 | break; /* PCMCIA remove happened */ | |
2027 | } | |
2028 | /* Acknowledge all of the current interrupt sources ASAP. */ | |
2029 | lp->a.write_csr(ioaddr, 0, csr0 & ~0x004f); | |
2030 | ||
2031 | must_restart = 0; | |
2032 | ||
2033 | if (netif_msg_intr(lp)) | |
2034 | printk(KERN_DEBUG | |
2035 | "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n", | |
2036 | dev->name, csr0, lp->a.read_csr(ioaddr, 0)); | |
2037 | ||
2038 | if (csr0 & 0x0400) /* Rx interrupt */ | |
2039 | pcnet32_rx(dev); | |
2040 | ||
2041 | if (csr0 & 0x0200) { /* Tx-done interrupt */ | |
2042 | unsigned int dirty_tx = lp->dirty_tx; | |
2043 | int delta; | |
2044 | ||
2045 | while (dirty_tx != lp->cur_tx) { | |
2046 | int entry = dirty_tx & lp->tx_mod_mask; | |
2047 | int status = | |
2048 | (short)le16_to_cpu(lp->tx_ring[entry]. | |
2049 | status); | |
2050 | ||
2051 | if (status < 0) | |
2052 | break; /* It still hasn't been Txed */ | |
2053 | ||
2054 | lp->tx_ring[entry].base = 0; | |
2055 | ||
2056 | if (status & 0x4000) { | |
2057 | /* There was an major error, log it. */ | |
2058 | int err_status = | |
2059 | le32_to_cpu(lp->tx_ring[entry]. | |
2060 | misc); | |
2061 | lp->stats.tx_errors++; | |
2062 | if (netif_msg_tx_err(lp)) | |
2063 | printk(KERN_ERR | |
2064 | "%s: Tx error status=%04x err_status=%08x\n", | |
2065 | dev->name, status, | |
2066 | err_status); | |
2067 | if (err_status & 0x04000000) | |
2068 | lp->stats.tx_aborted_errors++; | |
2069 | if (err_status & 0x08000000) | |
2070 | lp->stats.tx_carrier_errors++; | |
2071 | if (err_status & 0x10000000) | |
2072 | lp->stats.tx_window_errors++; | |
1da177e4 | 2073 | #ifndef DO_DXSUFLO |
4a5e8e29 JG |
2074 | if (err_status & 0x40000000) { |
2075 | lp->stats.tx_fifo_errors++; | |
2076 | /* Ackk! On FIFO errors the Tx unit is turned off! */ | |
2077 | /* Remove this verbosity later! */ | |
2078 | if (netif_msg_tx_err(lp)) | |
2079 | printk(KERN_ERR | |
2080 | "%s: Tx FIFO error! CSR0=%4.4x\n", | |
2081 | dev->name, csr0); | |
2082 | must_restart = 1; | |
2083 | } | |
1da177e4 | 2084 | #else |
4a5e8e29 JG |
2085 | if (err_status & 0x40000000) { |
2086 | lp->stats.tx_fifo_errors++; | |
2087 | if (!lp->dxsuflo) { /* If controller doesn't recover ... */ | |
2088 | /* Ackk! On FIFO errors the Tx unit is turned off! */ | |
2089 | /* Remove this verbosity later! */ | |
2090 | if (netif_msg_tx_err | |
2091 | (lp)) | |
2092 | printk(KERN_ERR | |
2093 | "%s: Tx FIFO error! CSR0=%4.4x\n", | |
2094 | dev-> | |
2095 | name, | |
2096 | csr0); | |
2097 | must_restart = 1; | |
2098 | } | |
2099 | } | |
1da177e4 | 2100 | #endif |
4a5e8e29 JG |
2101 | } else { |
2102 | if (status & 0x1800) | |
2103 | lp->stats.collisions++; | |
2104 | lp->stats.tx_packets++; | |
2105 | } | |
2106 | ||
2107 | /* We must free the original skb */ | |
2108 | if (lp->tx_skbuff[entry]) { | |
2109 | pci_unmap_single(lp->pci_dev, | |
2110 | lp->tx_dma_addr[entry], | |
2111 | lp->tx_skbuff[entry]-> | |
2112 | len, PCI_DMA_TODEVICE); | |
2113 | dev_kfree_skb_irq(lp->tx_skbuff[entry]); | |
2114 | lp->tx_skbuff[entry] = NULL; | |
2115 | lp->tx_dma_addr[entry] = 0; | |
2116 | } | |
2117 | dirty_tx++; | |
2118 | } | |
2119 | ||
2120 | delta = | |
2121 | (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + | |
2122 | lp->tx_ring_size); | |
2123 | if (delta > lp->tx_ring_size) { | |
2124 | if (netif_msg_drv(lp)) | |
2125 | printk(KERN_ERR | |
2126 | "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n", | |
2127 | dev->name, dirty_tx, lp->cur_tx, | |
2128 | lp->tx_full); | |
2129 | dirty_tx += lp->tx_ring_size; | |
2130 | delta -= lp->tx_ring_size; | |
2131 | } | |
2132 | ||
2133 | if (lp->tx_full && | |
2134 | netif_queue_stopped(dev) && | |
2135 | delta < lp->tx_ring_size - 2) { | |
2136 | /* The ring is no longer full, clear tbusy. */ | |
2137 | lp->tx_full = 0; | |
2138 | netif_wake_queue(dev); | |
2139 | } | |
2140 | lp->dirty_tx = dirty_tx; | |
2141 | } | |
2142 | ||
2143 | /* Log misc errors. */ | |
2144 | if (csr0 & 0x4000) | |
2145 | lp->stats.tx_errors++; /* Tx babble. */ | |
2146 | if (csr0 & 0x1000) { | |
2147 | /* | |
2148 | * this happens when our receive ring is full. This shouldn't | |
2149 | * be a problem as we will see normal rx interrupts for the frames | |
2150 | * in the receive ring. But there are some PCI chipsets (I can | |
2151 | * reproduce this on SP3G with Intel saturn chipset) which have | |
2152 | * sometimes problems and will fill up the receive ring with | |
2153 | * error descriptors. In this situation we don't get a rx | |
2154 | * interrupt, but a missed frame interrupt sooner or later. | |
2155 | * So we try to clean up our receive ring here. | |
2156 | */ | |
2157 | pcnet32_rx(dev); | |
2158 | lp->stats.rx_errors++; /* Missed a Rx frame. */ | |
2159 | } | |
2160 | if (csr0 & 0x0800) { | |
2161 | if (netif_msg_drv(lp)) | |
2162 | printk(KERN_ERR | |
2163 | "%s: Bus master arbitration failure, status %4.4x.\n", | |
2164 | dev->name, csr0); | |
2165 | /* unlike for the lance, there is no restart needed */ | |
1da177e4 LT |
2166 | } |
2167 | ||
4a5e8e29 JG |
2168 | if (must_restart) { |
2169 | /* reset the chip to clear the error condition, then restart */ | |
2170 | lp->a.reset(ioaddr); | |
2171 | lp->a.write_csr(ioaddr, 4, 0x0915); | |
2172 | pcnet32_restart(dev, 0x0002); | |
2173 | netif_wake_queue(dev); | |
1da177e4 | 2174 | } |
4a5e8e29 JG |
2175 | } |
2176 | ||
2177 | /* Set interrupt enable. */ | |
2178 | lp->a.write_csr(ioaddr, 0, 0x0040); | |
2179 | lp->a.write_rap(ioaddr, rap); | |
2180 | ||
2181 | if (netif_msg_intr(lp)) | |
2182 | printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n", | |
2183 | dev->name, lp->a.read_csr(ioaddr, 0)); | |
2184 | ||
2185 | spin_unlock(&lp->lock); | |
2186 | ||
2187 | return IRQ_HANDLED; | |
1da177e4 LT |
2188 | } |
2189 | ||
4a5e8e29 | 2190 | static int pcnet32_rx(struct net_device *dev) |
1da177e4 | 2191 | { |
4a5e8e29 JG |
2192 | struct pcnet32_private *lp = dev->priv; |
2193 | int entry = lp->cur_rx & lp->rx_mod_mask; | |
2194 | int boguscnt = lp->rx_ring_size / 2; | |
2195 | ||
2196 | /* If we own the next entry, it's a new packet. Send it up. */ | |
2197 | while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) { | |
2198 | int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8; | |
2199 | ||
2200 | if (status != 0x03) { /* There was an error. */ | |
2201 | /* | |
2202 | * There is a tricky error noted by John Murphy, | |
2203 | * <murf@perftech.com> to Russ Nelson: Even with full-sized | |
2204 | * buffers it's possible for a jabber packet to use two | |
2205 | * buffers, with only the last correctly noting the error. | |
2206 | */ | |
2207 | if (status & 0x01) /* Only count a general error at the */ | |
2208 | lp->stats.rx_errors++; /* end of a packet. */ | |
2209 | if (status & 0x20) | |
2210 | lp->stats.rx_frame_errors++; | |
2211 | if (status & 0x10) | |
2212 | lp->stats.rx_over_errors++; | |
2213 | if (status & 0x08) | |
2214 | lp->stats.rx_crc_errors++; | |
2215 | if (status & 0x04) | |
2216 | lp->stats.rx_fifo_errors++; | |
2217 | lp->rx_ring[entry].status &= le16_to_cpu(0x03ff); | |
1da177e4 | 2218 | } else { |
4a5e8e29 JG |
2219 | /* Malloc up new buffer, compatible with net-2e. */ |
2220 | short pkt_len = | |
2221 | (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff) | |
2222 | - 4; | |
2223 | struct sk_buff *skb; | |
2224 | ||
2225 | /* Discard oversize frames. */ | |
2226 | if (unlikely(pkt_len > PKT_BUF_SZ - 2)) { | |
2227 | if (netif_msg_drv(lp)) | |
2228 | printk(KERN_ERR | |
2229 | "%s: Impossible packet size %d!\n", | |
2230 | dev->name, pkt_len); | |
2231 | lp->stats.rx_errors++; | |
2232 | } else if (pkt_len < 60) { | |
2233 | if (netif_msg_rx_err(lp)) | |
2234 | printk(KERN_ERR "%s: Runt packet!\n", | |
2235 | dev->name); | |
2236 | lp->stats.rx_errors++; | |
2237 | } else { | |
2238 | int rx_in_place = 0; | |
2239 | ||
2240 | if (pkt_len > rx_copybreak) { | |
2241 | struct sk_buff *newskb; | |
2242 | ||
2243 | if ((newskb = | |
2244 | dev_alloc_skb(PKT_BUF_SZ))) { | |
2245 | skb_reserve(newskb, 2); | |
2246 | skb = lp->rx_skbuff[entry]; | |
2247 | pci_unmap_single(lp->pci_dev, | |
2248 | lp-> | |
2249 | rx_dma_addr | |
2250 | [entry], | |
2251 | PKT_BUF_SZ - 2, | |
2252 | PCI_DMA_FROMDEVICE); | |
2253 | skb_put(skb, pkt_len); | |
2254 | lp->rx_skbuff[entry] = newskb; | |
2255 | newskb->dev = dev; | |
2256 | lp->rx_dma_addr[entry] = | |
2257 | pci_map_single(lp->pci_dev, | |
2258 | newskb->data, | |
2259 | PKT_BUF_SZ - | |
2260 | 2, | |
2261 | PCI_DMA_FROMDEVICE); | |
2262 | lp->rx_ring[entry].base = | |
2263 | le32_to_cpu(lp-> | |
2264 | rx_dma_addr | |
2265 | [entry]); | |
2266 | rx_in_place = 1; | |
2267 | } else | |
2268 | skb = NULL; | |
2269 | } else { | |
2270 | skb = dev_alloc_skb(pkt_len + 2); | |
2271 | } | |
2272 | ||
2273 | if (skb == NULL) { | |
2274 | int i; | |
2275 | if (netif_msg_drv(lp)) | |
2276 | printk(KERN_ERR | |
2277 | "%s: Memory squeeze, deferring packet.\n", | |
2278 | dev->name); | |
2279 | for (i = 0; i < lp->rx_ring_size; i++) | |
2280 | if ((short) | |
2281 | le16_to_cpu(lp-> | |
2282 | rx_ring[(entry + | |
2283 | i) | |
2284 | & lp-> | |
2285 | rx_mod_mask]. | |
2286 | status) < 0) | |
2287 | break; | |
2288 | ||
2289 | if (i > lp->rx_ring_size - 2) { | |
2290 | lp->stats.rx_dropped++; | |
2291 | lp->rx_ring[entry].status |= | |
2292 | le16_to_cpu(0x8000); | |
2293 | wmb(); /* Make sure adapter sees owner change */ | |
2294 | lp->cur_rx++; | |
2295 | } | |
2296 | break; | |
2297 | } | |
2298 | skb->dev = dev; | |
2299 | if (!rx_in_place) { | |
2300 | skb_reserve(skb, 2); /* 16 byte align */ | |
2301 | skb_put(skb, pkt_len); /* Make room */ | |
2302 | pci_dma_sync_single_for_cpu(lp->pci_dev, | |
2303 | lp-> | |
2304 | rx_dma_addr | |
2305 | [entry], | |
2306 | PKT_BUF_SZ - | |
2307 | 2, | |
2308 | PCI_DMA_FROMDEVICE); | |
2309 | eth_copy_and_sum(skb, | |
2310 | (unsigned char *)(lp-> | |
2311 | rx_skbuff | |
2312 | [entry]-> | |
2313 | data), | |
2314 | pkt_len, 0); | |
2315 | pci_dma_sync_single_for_device(lp-> | |
2316 | pci_dev, | |
2317 | lp-> | |
2318 | rx_dma_addr | |
2319 | [entry], | |
2320 | PKT_BUF_SZ | |
2321 | - 2, | |
2322 | PCI_DMA_FROMDEVICE); | |
2323 | } | |
2324 | lp->stats.rx_bytes += skb->len; | |
2325 | skb->protocol = eth_type_trans(skb, dev); | |
2326 | netif_rx(skb); | |
2327 | dev->last_rx = jiffies; | |
2328 | lp->stats.rx_packets++; | |
2329 | } | |
1da177e4 | 2330 | } |
4a5e8e29 JG |
2331 | /* |
2332 | * The docs say that the buffer length isn't touched, but Andrew Boyd | |
2333 | * of QNX reports that some revs of the 79C965 clear it. | |
2334 | */ | |
2335 | lp->rx_ring[entry].buf_length = le16_to_cpu(2 - PKT_BUF_SZ); | |
2336 | wmb(); /* Make sure owner changes after all others are visible */ | |
2337 | lp->rx_ring[entry].status |= le16_to_cpu(0x8000); | |
2338 | entry = (++lp->cur_rx) & lp->rx_mod_mask; | |
2339 | if (--boguscnt <= 0) | |
2340 | break; /* don't stay in loop forever */ | |
1da177e4 | 2341 | } |
4a5e8e29 JG |
2342 | |
2343 | return 0; | |
1da177e4 LT |
2344 | } |
2345 | ||
4a5e8e29 | 2346 | static int pcnet32_close(struct net_device *dev) |
1da177e4 | 2347 | { |
4a5e8e29 JG |
2348 | unsigned long ioaddr = dev->base_addr; |
2349 | struct pcnet32_private *lp = dev->priv; | |
2350 | int i; | |
2351 | unsigned long flags; | |
1da177e4 | 2352 | |
4a5e8e29 | 2353 | del_timer_sync(&lp->watchdog_timer); |
1da177e4 | 2354 | |
4a5e8e29 | 2355 | netif_stop_queue(dev); |
1da177e4 | 2356 | |
4a5e8e29 | 2357 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 2358 | |
4a5e8e29 | 2359 | lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112); |
1da177e4 | 2360 | |
4a5e8e29 JG |
2361 | if (netif_msg_ifdown(lp)) |
2362 | printk(KERN_DEBUG | |
2363 | "%s: Shutting down ethercard, status was %2.2x.\n", | |
2364 | dev->name, lp->a.read_csr(ioaddr, 0)); | |
1da177e4 | 2365 | |
4a5e8e29 JG |
2366 | /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ |
2367 | lp->a.write_csr(ioaddr, 0, 0x0004); | |
1da177e4 | 2368 | |
4a5e8e29 JG |
2369 | /* |
2370 | * Switch back to 16bit mode to avoid problems with dumb | |
2371 | * DOS packet driver after a warm reboot | |
2372 | */ | |
2373 | lp->a.write_bcr(ioaddr, 20, 4); | |
1da177e4 | 2374 | |
4a5e8e29 | 2375 | spin_unlock_irqrestore(&lp->lock, flags); |
1da177e4 | 2376 | |
4a5e8e29 | 2377 | free_irq(dev->irq, dev); |
1da177e4 | 2378 | |
4a5e8e29 | 2379 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 2380 | |
4a5e8e29 JG |
2381 | /* free all allocated skbuffs */ |
2382 | for (i = 0; i < lp->rx_ring_size; i++) { | |
2383 | lp->rx_ring[i].status = 0; | |
2384 | wmb(); /* Make sure adapter sees owner change */ | |
2385 | if (lp->rx_skbuff[i]) { | |
2386 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], | |
2387 | PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE); | |
2388 | dev_kfree_skb(lp->rx_skbuff[i]); | |
2389 | } | |
2390 | lp->rx_skbuff[i] = NULL; | |
2391 | lp->rx_dma_addr[i] = 0; | |
1da177e4 | 2392 | } |
1da177e4 | 2393 | |
4a5e8e29 JG |
2394 | for (i = 0; i < lp->tx_ring_size; i++) { |
2395 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ | |
2396 | wmb(); /* Make sure adapter sees owner change */ | |
2397 | if (lp->tx_skbuff[i]) { | |
2398 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], | |
2399 | lp->tx_skbuff[i]->len, | |
2400 | PCI_DMA_TODEVICE); | |
2401 | dev_kfree_skb(lp->tx_skbuff[i]); | |
2402 | } | |
2403 | lp->tx_skbuff[i] = NULL; | |
2404 | lp->tx_dma_addr[i] = 0; | |
1da177e4 | 2405 | } |
1da177e4 | 2406 | |
4a5e8e29 | 2407 | spin_unlock_irqrestore(&lp->lock, flags); |
1da177e4 | 2408 | |
4a5e8e29 | 2409 | return 0; |
1da177e4 LT |
2410 | } |
2411 | ||
4a5e8e29 | 2412 | static struct net_device_stats *pcnet32_get_stats(struct net_device *dev) |
1da177e4 | 2413 | { |
4a5e8e29 JG |
2414 | struct pcnet32_private *lp = dev->priv; |
2415 | unsigned long ioaddr = dev->base_addr; | |
2416 | u16 saved_addr; | |
2417 | unsigned long flags; | |
2418 | ||
2419 | spin_lock_irqsave(&lp->lock, flags); | |
2420 | saved_addr = lp->a.read_rap(ioaddr); | |
2421 | lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112); | |
2422 | lp->a.write_rap(ioaddr, saved_addr); | |
2423 | spin_unlock_irqrestore(&lp->lock, flags); | |
2424 | ||
2425 | return &lp->stats; | |
1da177e4 LT |
2426 | } |
2427 | ||
2428 | /* taken from the sunlance driver, which it took from the depca driver */ | |
4a5e8e29 | 2429 | static void pcnet32_load_multicast(struct net_device *dev) |
1da177e4 | 2430 | { |
4a5e8e29 JG |
2431 | struct pcnet32_private *lp = dev->priv; |
2432 | volatile struct pcnet32_init_block *ib = &lp->init_block; | |
2433 | volatile u16 *mcast_table = (u16 *) & ib->filter; | |
2434 | struct dev_mc_list *dmi = dev->mc_list; | |
2435 | char *addrs; | |
2436 | int i; | |
2437 | u32 crc; | |
2438 | ||
2439 | /* set all multicast bits */ | |
2440 | if (dev->flags & IFF_ALLMULTI) { | |
2441 | ib->filter[0] = 0xffffffff; | |
2442 | ib->filter[1] = 0xffffffff; | |
2443 | return; | |
2444 | } | |
2445 | /* clear the multicast filter */ | |
2446 | ib->filter[0] = 0; | |
2447 | ib->filter[1] = 0; | |
2448 | ||
2449 | /* Add addresses */ | |
2450 | for (i = 0; i < dev->mc_count; i++) { | |
2451 | addrs = dmi->dmi_addr; | |
2452 | dmi = dmi->next; | |
2453 | ||
2454 | /* multicast address? */ | |
2455 | if (!(*addrs & 1)) | |
2456 | continue; | |
2457 | ||
2458 | crc = ether_crc_le(6, addrs); | |
2459 | crc = crc >> 26; | |
2460 | mcast_table[crc >> 4] = | |
2461 | le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) | | |
2462 | (1 << (crc & 0xf))); | |
2463 | } | |
1da177e4 | 2464 | return; |
1da177e4 LT |
2465 | } |
2466 | ||
1da177e4 LT |
2467 | /* |
2468 | * Set or clear the multicast filter for this adaptor. | |
2469 | */ | |
2470 | static void pcnet32_set_multicast_list(struct net_device *dev) | |
2471 | { | |
4a5e8e29 JG |
2472 | unsigned long ioaddr = dev->base_addr, flags; |
2473 | struct pcnet32_private *lp = dev->priv; | |
2474 | ||
2475 | spin_lock_irqsave(&lp->lock, flags); | |
2476 | if (dev->flags & IFF_PROMISC) { | |
2477 | /* Log any net taps. */ | |
2478 | if (netif_msg_hw(lp)) | |
2479 | printk(KERN_INFO "%s: Promiscuous mode enabled.\n", | |
2480 | dev->name); | |
2481 | lp->init_block.mode = | |
2482 | le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << | |
2483 | 7); | |
2484 | } else { | |
2485 | lp->init_block.mode = | |
2486 | le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); | |
2487 | pcnet32_load_multicast(dev); | |
2488 | } | |
2489 | ||
2490 | lp->a.write_csr(ioaddr, 0, 0x0004); /* Temporarily stop the lance. */ | |
2491 | pcnet32_restart(dev, 0x0042); /* Resume normal operation */ | |
2492 | netif_wake_queue(dev); | |
2493 | ||
2494 | spin_unlock_irqrestore(&lp->lock, flags); | |
1da177e4 LT |
2495 | } |
2496 | ||
2497 | /* This routine assumes that the lp->lock is held */ | |
2498 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num) | |
2499 | { | |
4a5e8e29 JG |
2500 | struct pcnet32_private *lp = dev->priv; |
2501 | unsigned long ioaddr = dev->base_addr; | |
2502 | u16 val_out; | |
1da177e4 | 2503 | |
4a5e8e29 JG |
2504 | if (!lp->mii) |
2505 | return 0; | |
1da177e4 | 2506 | |
4a5e8e29 JG |
2507 | lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); |
2508 | val_out = lp->a.read_bcr(ioaddr, 34); | |
1da177e4 | 2509 | |
4a5e8e29 | 2510 | return val_out; |
1da177e4 LT |
2511 | } |
2512 | ||
2513 | /* This routine assumes that the lp->lock is held */ | |
2514 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) | |
2515 | { | |
4a5e8e29 JG |
2516 | struct pcnet32_private *lp = dev->priv; |
2517 | unsigned long ioaddr = dev->base_addr; | |
1da177e4 | 2518 | |
4a5e8e29 JG |
2519 | if (!lp->mii) |
2520 | return; | |
1da177e4 | 2521 | |
4a5e8e29 JG |
2522 | lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); |
2523 | lp->a.write_bcr(ioaddr, 34, val); | |
1da177e4 LT |
2524 | } |
2525 | ||
2526 | static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2527 | { | |
4a5e8e29 JG |
2528 | struct pcnet32_private *lp = dev->priv; |
2529 | int rc; | |
2530 | unsigned long flags; | |
1da177e4 | 2531 | |
4a5e8e29 JG |
2532 | /* SIOC[GS]MIIxxx ioctls */ |
2533 | if (lp->mii) { | |
2534 | spin_lock_irqsave(&lp->lock, flags); | |
2535 | rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); | |
2536 | spin_unlock_irqrestore(&lp->lock, flags); | |
2537 | } else { | |
2538 | rc = -EOPNOTSUPP; | |
2539 | } | |
1da177e4 | 2540 | |
4a5e8e29 | 2541 | return rc; |
1da177e4 LT |
2542 | } |
2543 | ||
ac62ef04 DF |
2544 | static int pcnet32_check_otherphy(struct net_device *dev) |
2545 | { | |
4a5e8e29 JG |
2546 | struct pcnet32_private *lp = dev->priv; |
2547 | struct mii_if_info mii = lp->mii_if; | |
2548 | u16 bmcr; | |
2549 | int i; | |
ac62ef04 | 2550 | |
4a5e8e29 JG |
2551 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { |
2552 | if (i == lp->mii_if.phy_id) | |
2553 | continue; /* skip active phy */ | |
2554 | if (lp->phymask & (1 << i)) { | |
2555 | mii.phy_id = i; | |
2556 | if (mii_link_ok(&mii)) { | |
2557 | /* found PHY with active link */ | |
2558 | if (netif_msg_link(lp)) | |
2559 | printk(KERN_INFO | |
2560 | "%s: Using PHY number %d.\n", | |
2561 | dev->name, i); | |
2562 | ||
2563 | /* isolate inactive phy */ | |
2564 | bmcr = | |
2565 | mdio_read(dev, lp->mii_if.phy_id, MII_BMCR); | |
2566 | mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, | |
2567 | bmcr | BMCR_ISOLATE); | |
2568 | ||
2569 | /* de-isolate new phy */ | |
2570 | bmcr = mdio_read(dev, i, MII_BMCR); | |
2571 | mdio_write(dev, i, MII_BMCR, | |
2572 | bmcr & ~BMCR_ISOLATE); | |
2573 | ||
2574 | /* set new phy address */ | |
2575 | lp->mii_if.phy_id = i; | |
2576 | return 1; | |
2577 | } | |
2578 | } | |
ac62ef04 | 2579 | } |
4a5e8e29 | 2580 | return 0; |
ac62ef04 DF |
2581 | } |
2582 | ||
2583 | /* | |
2584 | * Show the status of the media. Similar to mii_check_media however it | |
2585 | * correctly shows the link speed for all (tested) pcnet32 variants. | |
2586 | * Devices with no mii just report link state without speed. | |
2587 | * | |
2588 | * Caller is assumed to hold and release the lp->lock. | |
2589 | */ | |
2590 | ||
2591 | static void pcnet32_check_media(struct net_device *dev, int verbose) | |
2592 | { | |
4a5e8e29 JG |
2593 | struct pcnet32_private *lp = dev->priv; |
2594 | int curr_link; | |
2595 | int prev_link = netif_carrier_ok(dev) ? 1 : 0; | |
2596 | u32 bcr9; | |
2597 | ||
ac62ef04 | 2598 | if (lp->mii) { |
4a5e8e29 | 2599 | curr_link = mii_link_ok(&lp->mii_if); |
ac62ef04 | 2600 | } else { |
4a5e8e29 JG |
2601 | ulong ioaddr = dev->base_addr; /* card base I/O address */ |
2602 | curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0); | |
2603 | } | |
2604 | if (!curr_link) { | |
2605 | if (prev_link || verbose) { | |
2606 | netif_carrier_off(dev); | |
2607 | if (netif_msg_link(lp)) | |
2608 | printk(KERN_INFO "%s: link down\n", dev->name); | |
2609 | } | |
2610 | if (lp->phycount > 1) { | |
2611 | curr_link = pcnet32_check_otherphy(dev); | |
2612 | prev_link = 0; | |
2613 | } | |
2614 | } else if (verbose || !prev_link) { | |
2615 | netif_carrier_on(dev); | |
2616 | if (lp->mii) { | |
2617 | if (netif_msg_link(lp)) { | |
2618 | struct ethtool_cmd ecmd; | |
2619 | mii_ethtool_gset(&lp->mii_if, &ecmd); | |
2620 | printk(KERN_INFO | |
2621 | "%s: link up, %sMbps, %s-duplex\n", | |
2622 | dev->name, | |
2623 | (ecmd.speed == SPEED_100) ? "100" : "10", | |
2624 | (ecmd.duplex == | |
2625 | DUPLEX_FULL) ? "full" : "half"); | |
2626 | } | |
2627 | bcr9 = lp->a.read_bcr(dev->base_addr, 9); | |
2628 | if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) { | |
2629 | if (lp->mii_if.full_duplex) | |
2630 | bcr9 |= (1 << 0); | |
2631 | else | |
2632 | bcr9 &= ~(1 << 0); | |
2633 | lp->a.write_bcr(dev->base_addr, 9, bcr9); | |
2634 | } | |
2635 | } else { | |
2636 | if (netif_msg_link(lp)) | |
2637 | printk(KERN_INFO "%s: link up\n", dev->name); | |
2638 | } | |
ac62ef04 | 2639 | } |
ac62ef04 DF |
2640 | } |
2641 | ||
2642 | /* | |
2643 | * Check for loss of link and link establishment. | |
2644 | * Can not use mii_check_media because it does nothing if mode is forced. | |
2645 | */ | |
2646 | ||
1da177e4 LT |
2647 | static void pcnet32_watchdog(struct net_device *dev) |
2648 | { | |
4a5e8e29 JG |
2649 | struct pcnet32_private *lp = dev->priv; |
2650 | unsigned long flags; | |
1da177e4 | 2651 | |
4a5e8e29 JG |
2652 | /* Print the link status if it has changed */ |
2653 | spin_lock_irqsave(&lp->lock, flags); | |
2654 | pcnet32_check_media(dev, 0); | |
2655 | spin_unlock_irqrestore(&lp->lock, flags); | |
1da177e4 | 2656 | |
4a5e8e29 | 2657 | mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT); |
1da177e4 LT |
2658 | } |
2659 | ||
2660 | static void __devexit pcnet32_remove_one(struct pci_dev *pdev) | |
2661 | { | |
4a5e8e29 JG |
2662 | struct net_device *dev = pci_get_drvdata(pdev); |
2663 | ||
2664 | if (dev) { | |
2665 | struct pcnet32_private *lp = dev->priv; | |
2666 | ||
2667 | unregister_netdev(dev); | |
2668 | pcnet32_free_ring(dev); | |
2669 | release_region(dev->base_addr, PCNET32_TOTAL_SIZE); | |
2670 | pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr); | |
2671 | free_netdev(dev); | |
2672 | pci_disable_device(pdev); | |
2673 | pci_set_drvdata(pdev, NULL); | |
2674 | } | |
1da177e4 LT |
2675 | } |
2676 | ||
2677 | static struct pci_driver pcnet32_driver = { | |
4a5e8e29 JG |
2678 | .name = DRV_NAME, |
2679 | .probe = pcnet32_probe_pci, | |
2680 | .remove = __devexit_p(pcnet32_remove_one), | |
2681 | .id_table = pcnet32_pci_tbl, | |
1da177e4 LT |
2682 | }; |
2683 | ||
2684 | /* An additional parameter that may be passed in... */ | |
2685 | static int debug = -1; | |
2686 | static int tx_start_pt = -1; | |
2687 | static int pcnet32_have_pci; | |
2688 | ||
2689 | module_param(debug, int, 0); | |
2690 | MODULE_PARM_DESC(debug, DRV_NAME " debug level"); | |
2691 | module_param(max_interrupt_work, int, 0); | |
4a5e8e29 JG |
2692 | MODULE_PARM_DESC(max_interrupt_work, |
2693 | DRV_NAME " maximum events handled per interrupt"); | |
1da177e4 | 2694 | module_param(rx_copybreak, int, 0); |
4a5e8e29 JG |
2695 | MODULE_PARM_DESC(rx_copybreak, |
2696 | DRV_NAME " copy breakpoint for copy-only-tiny-frames"); | |
1da177e4 LT |
2697 | module_param(tx_start_pt, int, 0); |
2698 | MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); | |
2699 | module_param(pcnet32vlb, int, 0); | |
2700 | MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); | |
2701 | module_param_array(options, int, NULL, 0); | |
2702 | MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); | |
2703 | module_param_array(full_duplex, int, NULL, 0); | |
2704 | MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); | |
2705 | /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ | |
2706 | module_param_array(homepna, int, NULL, 0); | |
4a5e8e29 JG |
2707 | MODULE_PARM_DESC(homepna, |
2708 | DRV_NAME | |
2709 | " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); | |
1da177e4 LT |
2710 | |
2711 | MODULE_AUTHOR("Thomas Bogendoerfer"); | |
2712 | MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); | |
2713 | MODULE_LICENSE("GPL"); | |
2714 | ||
2715 | #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) | |
2716 | ||
2717 | static int __init pcnet32_init_module(void) | |
2718 | { | |
4a5e8e29 | 2719 | printk(KERN_INFO "%s", version); |
1da177e4 | 2720 | |
4a5e8e29 | 2721 | pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); |
1da177e4 | 2722 | |
4a5e8e29 JG |
2723 | if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) |
2724 | tx_start = tx_start_pt; | |
1da177e4 | 2725 | |
4a5e8e29 JG |
2726 | /* find the PCI devices */ |
2727 | if (!pci_module_init(&pcnet32_driver)) | |
2728 | pcnet32_have_pci = 1; | |
1da177e4 | 2729 | |
4a5e8e29 JG |
2730 | /* should we find any remaining VLbus devices ? */ |
2731 | if (pcnet32vlb) | |
dcaf9769 | 2732 | pcnet32_probe_vlbus(pcnet32_portlist); |
1da177e4 | 2733 | |
4a5e8e29 JG |
2734 | if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) |
2735 | printk(KERN_INFO PFX "%d cards_found.\n", cards_found); | |
1da177e4 | 2736 | |
4a5e8e29 | 2737 | return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; |
1da177e4 LT |
2738 | } |
2739 | ||
2740 | static void __exit pcnet32_cleanup_module(void) | |
2741 | { | |
4a5e8e29 JG |
2742 | struct net_device *next_dev; |
2743 | ||
2744 | while (pcnet32_dev) { | |
2745 | struct pcnet32_private *lp = pcnet32_dev->priv; | |
2746 | next_dev = lp->next; | |
2747 | unregister_netdev(pcnet32_dev); | |
2748 | pcnet32_free_ring(pcnet32_dev); | |
2749 | release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); | |
2750 | pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr); | |
2751 | free_netdev(pcnet32_dev); | |
2752 | pcnet32_dev = next_dev; | |
2753 | } | |
1da177e4 | 2754 | |
4a5e8e29 JG |
2755 | if (pcnet32_have_pci) |
2756 | pci_unregister_driver(&pcnet32_driver); | |
1da177e4 LT |
2757 | } |
2758 | ||
2759 | module_init(pcnet32_init_module); | |
2760 | module_exit(pcnet32_cleanup_module); | |
2761 | ||
2762 | /* | |
2763 | * Local variables: | |
2764 | * c-indent-level: 4 | |
2765 | * tab-width: 8 | |
2766 | * End: | |
2767 | */ |