[mirror_ubuntu-artful-kernel.git] / drivers / net / phy / bcm7xxx.c

/*
 * Broadcom BCM7xxx internal transceivers support.
 *
 * Copyright (C) 2014, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/phy.h>
#include <linux/delay.h>
#include "bcm-phy-lib.h"
#include <linux/bitops.h>
#include <linux/brcmphy.h>
#include <linux/mdio.h>

/* Broadcom BCM7xxx internal PHY registers */

/* 40nm only register definitions */
#define MII_BCM7XXX_100TX_AUX_CTL	0x10
#define MII_BCM7XXX_100TX_FALSE_CAR	0x13
#define MII_BCM7XXX_100TX_DISC		0x14
#define MII_BCM7XXX_AUX_MODE		0x1d
#define  MII_BCM7XXX_64CLK_MDIO		BIT(12)
#define MII_BCM7XXX_TEST		0x1f
#define  MII_BCM7XXX_SHD_MODE_2		BIT(2)

/* 28nm only register definitions */
#define MISC_ADDR(base, channel)	base, channel

#define DSP_TAP10			MISC_ADDR(0x0a, 0)
#define PLL_PLLCTRL_1			MISC_ADDR(0x32, 1)
#define PLL_PLLCTRL_2			MISC_ADDR(0x32, 2)
#define PLL_PLLCTRL_4			MISC_ADDR(0x33, 0)

#define AFE_RXCONFIG_0			MISC_ADDR(0x38, 0)
#define AFE_RXCONFIG_1			MISC_ADDR(0x38, 1)
#define AFE_RXCONFIG_2			MISC_ADDR(0x38, 2)
#define AFE_RX_LP_COUNTER		MISC_ADDR(0x38, 3)
#define AFE_TX_CONFIG			MISC_ADDR(0x39, 0)
#define AFE_VDCA_ICTRL_0		MISC_ADDR(0x39, 1)
#define AFE_VDAC_OTHERS_0		MISC_ADDR(0x39, 3)
#define AFE_HPF_TRIM_OTHERS		MISC_ADDR(0x3a, 0)

struct bcm7xxx_phy_priv {
	u64	*stats;
};

static void r_rc_cal_reset(struct phy_device *phydev)
{
	/* Reset R_CAL/RC_CAL Engine */
	bcm_phy_write_exp(phydev, 0x00b0, 0x0010);

	/* Disable Reset R_AL/RC_CAL Engine */
	bcm_phy_write_exp(phydev, 0x00b0, 0x0000);
}

static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
{
	/* Increase VCO range to prevent unlocking problem of PLL at low
	 * temp
	 */
	bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);

	/* Change Ki to 011 */
	bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);

	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
	 * to 111
	 */
	bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);

	/* Adjust bias current trim by -3 */
	bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);

	/* Switch to CORE_BASE1E */
	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);

	r_rc_cal_reset(phydev);

	/* write AFE_RXCONFIG_0 */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);

	/* write AFE_RXCONFIG_1 */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);

	/* write AFE_RX_LP_COUNTER */
	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);

	/* write AFE_HPF_TRIM_OTHERS */
	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);

	/* write AFTE_TX_CONFIG */
	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);

	return 0;
}

static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
{
	/* AFE_RXCONFIG_0 */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);

	/* AFE_RXCONFIG_1 */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);

	/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);

	/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);

	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);

	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);

	/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
	bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);

	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	 * offset for HT=0 code
	 */
	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);

	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);

	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);

	/* Reset R_CAL/RC_CAL engine */
	r_rc_cal_reset(phydev);

	return 0;
}

static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
{
	/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);

	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);

	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);

	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	 * offset for HT=0 code
	 */
	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);

	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);

	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);

	/* Reset R_CAL/RC_CAL engine */
	r_rc_cal_reset(phydev);

	return 0;
}

static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
{
	/* +1 RC_CAL codes for RL centering for both LT and HT conditions */
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);

	/* Cut master bias current by 2% to compensate for RC_CAL offset */
	bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);

	/* Improve hybrid leakage */
	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);

	/* Change rx_on_tune 8 to 0xf */
	bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);

	/* Change 100Tx EEE bandwidth */
	bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);

	/* Enable ffe zero detection for Vitesse interoperability */
	bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);

	r_rc_cal_reset(phydev);

	return 0;
}

static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
{
	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
	u8 count;
	int ret = 0;

	/* Newer devices have moved the revision information back into a
	 * standard location in MII_PHYS_ID[23]
	 */
	if (rev == 0)
		rev = phydev->phy_id & ~phydev->drv->phy_id_mask;

	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
		     phydev_name(phydev), phydev->drv->name, rev, patch);

	/* Dummy read to a register to workaround an issue upon reset where the
	 * internal inverter may not allow the first MDIO transaction to pass
	 * the MDIO management controller and make us return 0xffff for such
	 * reads.
	 */
	phy_read(phydev, MII_BMSR);

	switch (rev) {
	case 0xb0:
		ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
		break;
	case 0xd0:
		ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
		break;
	case 0xe0:
	case 0xf0:
	/* Rev G0 introduces a roll over */
	case 0x10:
		ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
		break;
	case 0x01:
		ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
		break;
	default:
		break;
	}

	if (ret)
		return ret;

	ret = bcm_phy_downshift_get(phydev, &count);
	if (ret)
		return ret;

	/* Only enable EEE if Wirespeed/downshift is disabled */
	ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
	if (ret)
		return ret;

	return bcm_phy_enable_apd(phydev, true);
}

static int bcm7xxx_28nm_resume(struct phy_device *phydev)
{
	int ret;

	/* Re-apply workarounds coming out suspend/resume */
	ret = bcm7xxx_28nm_config_init(phydev);
	if (ret)
		return ret;

	/* 28nm Gigabit PHYs come out of reset without any half-duplex
	 * or "hub" compliant advertised mode, fix that. This does not
	 * cause any problems with the PHY library since genphy_config_aneg()
	 * gracefully handles auto-negotiated and forced modes.
	 */
	return genphy_config_aneg(phydev);
}

static int phy_set_clr_bits(struct phy_device *dev, int location,
					int set_mask, int clr_mask)
{
	int v, ret;

	v = phy_read(dev, location);
	if (v < 0)
		return v;

	v &= ~clr_mask;
	v |= set_mask;

	ret = phy_write(dev, location, v);
	if (ret < 0)
		return ret;

	return v;
}

static int bcm7xxx_config_init(struct phy_device *phydev)
{
	int ret;

	/* Enable 64 clock MDIO */
	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
	phy_read(phydev, MII_BCM7XXX_AUX_MODE);

	/* set shadow mode 2 */
	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
			MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
	if (ret < 0)
		return ret;

	/* set iddq_clkbias */
	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
	udelay(10);

	/* reset iddq_clkbias */
	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);

	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);

	/* reset shadow mode 2 */
	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
	if (ret < 0)
		return ret;

	return 0;
}

/* Workaround for putting the PHY in IDDQ mode, required
 * for all BCM7XXX 40nm and 65nm PHYs
 */
static int bcm7xxx_suspend(struct phy_device *phydev)
{
	int ret;
	const struct bcm7xxx_regs {
		int reg;
		u16 value;
	} bcm7xxx_suspend_cfg[] = {
		{ MII_BCM7XXX_TEST, 0x008b },
		{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
		{ MII_BCM7XXX_100TX_DISC, 0x7000 },
		{ MII_BCM7XXX_TEST, 0x000f },
		{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
		{ MII_BCM7XXX_TEST, 0x000b },
	};
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
		ret = phy_write(phydev,
				bcm7xxx_suspend_cfg[i].reg,
				bcm7xxx_suspend_cfg[i].value);
		if (ret)
			return ret;
	}

	return 0;
}

static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev,
				    struct ethtool_tunable *tuna,
				    void *data)
{
	switch (tuna->id) {
	case ETHTOOL_PHY_DOWNSHIFT:
		return bcm_phy_downshift_get(phydev, (u8 *)data);
	default:
		return -EOPNOTSUPP;
	}
}

static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev,
				    struct ethtool_tunable *tuna,
				    const void *data)
{
	u8 count = *(u8 *)data;
	int ret;

	switch (tuna->id) {
	case ETHTOOL_PHY_DOWNSHIFT:
		ret = bcm_phy_downshift_set(phydev, count);
		break;
	default:
		return -EOPNOTSUPP;
	}

	if (ret)
		return ret;

	/* Disable EEE advertisment since this prevents the PHY
	 * from successfully linking up, trigger auto-negotiation restart
	 * to let the MAC decide what to do.
	 */
	ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
	if (ret)
		return ret;

	return genphy_restart_aneg(phydev);
}

static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev,
				       struct ethtool_stats *stats, u64 *data)
{
	struct bcm7xxx_phy_priv *priv = phydev->priv;

	bcm_phy_get_stats(phydev, priv->stats, stats, data);
}

static int bcm7xxx_28nm_probe(struct phy_device *phydev)
{
	struct bcm7xxx_phy_priv *priv;

	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	phydev->priv = priv;

	priv->stats = devm_kcalloc(&phydev->mdio.dev,
				   bcm_phy_get_sset_count(phydev), sizeof(u64),
				   GFP_KERNEL);
	if (!priv->stats)
		return -ENOMEM;

	return 0;
}

#define BCM7XXX_28NM_GPHY(_oui, _name)					\
{									\
	.phy_id		= (_oui),					\
	.phy_id_mask	= 0xfffffff0,					\
	.name		= _name,					\
	.features	= PHY_GBIT_FEATURES,				\
	.flags		= PHY_IS_INTERNAL,				\
	.config_init	= bcm7xxx_28nm_config_init,			\
	.config_aneg	= genphy_config_aneg,				\
	.read_status	= genphy_read_status,				\
	.resume		= bcm7xxx_28nm_resume,				\
	.get_tunable	= bcm7xxx_28nm_get_tunable,			\
	.set_tunable	= bcm7xxx_28nm_set_tunable,			\
	.get_sset_count	= bcm_phy_get_sset_count,			\
	.get_strings	= bcm_phy_get_strings,				\
	.get_stats	= bcm7xxx_28nm_get_phy_stats,			\
	.probe		= bcm7xxx_28nm_probe,				\
}

#define BCM7XXX_40NM_EPHY(_oui, _name)					\
{									\
	.phy_id         = (_oui),					\
	.phy_id_mask    = 0xfffffff0,					\
	.name           = _name,					\
	.features       = PHY_BASIC_FEATURES,				\
	.flags          = PHY_IS_INTERNAL,				\
	.config_init    = bcm7xxx_config_init,				\
	.config_aneg    = genphy_config_aneg,				\
	.read_status    = genphy_read_status,				\
	.suspend        = bcm7xxx_suspend,				\
	.resume         = bcm7xxx_config_init,				\
}

static struct phy_driver bcm7xxx_driver[] = {
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM74371, "Broadcom BCM74371"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
	BCM7XXX_40NM_EPHY(PHY_ID_BCM7346, "Broadcom BCM7346"),
	BCM7XXX_40NM_EPHY(PHY_ID_BCM7362, "Broadcom BCM7362"),
	BCM7XXX_40NM_EPHY(PHY_ID_BCM7425, "Broadcom BCM7425"),
	BCM7XXX_40NM_EPHY(PHY_ID_BCM7429, "Broadcom BCM7429"),
	BCM7XXX_40NM_EPHY(PHY_ID_BCM7435, "Broadcom BCM7435"),
};

static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
	{ PHY_ID_BCM7250, 0xfffffff0, },
	{ PHY_ID_BCM7278, 0xfffffff0, },
	{ PHY_ID_BCM7364, 0xfffffff0, },
	{ PHY_ID_BCM7366, 0xfffffff0, },
	{ PHY_ID_BCM7346, 0xfffffff0, },
	{ PHY_ID_BCM7362, 0xfffffff0, },
	{ PHY_ID_BCM7425, 0xfffffff0, },
	{ PHY_ID_BCM7429, 0xfffffff0, },
	{ PHY_ID_BCM74371, 0xfffffff0, },
	{ PHY_ID_BCM7439, 0xfffffff0, },
	{ PHY_ID_BCM7435, 0xfffffff0, },
	{ PHY_ID_BCM7445, 0xfffffff0, },
	{ }
};

module_phy_driver(bcm7xxx_driver);

MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);

MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Broadcom Corporation");
Commit	Line	Data
b560a58c FF	1	/*
	2	* Broadcom BCM7xxx internal transceivers support.
	3	*
	4	* Copyright (C) 2014, Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/phy.h>
	14	#include <linux/delay.h>
a1cba561	15	#include "bcm-phy-lib.h"
b560a58c FF	16	#include <linux/bitops.h>
b560a58c FF	17	#include <linux/brcmphy.h>
b8f9a029	18	#include <linux/mdio.h>
b560a58c FF	19
b560a58c FF	20	/* Broadcom BCM7xxx internal PHY registers */
b560a58c FF	21
	22	/* 40nm only register definitions */
	23	#define MII_BCM7XXX_100TX_AUX_CTL 0x10
	24	#define MII_BCM7XXX_100TX_FALSE_CAR 0x13
	25	#define MII_BCM7XXX_100TX_DISC 0x14
	26	#define MII_BCM7XXX_AUX_MODE 0x1d
3ccc3055	27	#define MII_BCM7XXX_64CLK_MDIO BIT(12)
b560a58c FF	28	#define MII_BCM7XXX_TEST 0x1f
	29	#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
	30
a3622f2c FF	31	/* 28nm only register definitions */
	32	#define MISC_ADDR(base, channel) base, channel
	33
	34	#define DSP_TAP10 MISC_ADDR(0x0a, 0)
	35	#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
	36	#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
	37	#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
	38
	39	#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
	40	#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
a490631f	41	#define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
a3622f2c FF	42	#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
a3622f2c FF	43	#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
a490631f FF	44	#define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
a490631f FF	45	#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
a3622f2c FF	46	#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
a3622f2c FF	47
b23ce9e8 FF	48	struct bcm7xxx_phy_priv {
	49	u64 *stats;
	50	};
	51
9c41f2ba FF	52	static void r_rc_cal_reset(struct phy_device *phydev)
	53	{
	54	/* Reset R_CAL/RC_CAL Engine */
a1cba561	55	bcm_phy_write_exp(phydev, 0x00b0, 0x0010);
9c41f2ba FF	56
9c41f2ba FF	57	/* Disable Reset R_AL/RC_CAL Engine */
a1cba561	58	bcm_phy_write_exp(phydev, 0x00b0, 0x0000);
9c41f2ba FF	59	}
9c41f2ba FF	60
2a9df742	61	static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
b560a58c	62	{
b560a58c FF	63	/* Increase VCO range to prevent unlocking problem of PLL at low
	64	* temp
	65	*/
a1cba561	66	bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
b560a58c FF	67
b560a58c FF	68	/* Change Ki to 011 */
a1cba561	69	bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
b560a58c FF	70
	71	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
	72	* to 111
	73	*/
a1cba561	74	bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
b560a58c FF	75
b560a58c FF	76	/* Adjust bias current trim by -3 */
a1cba561	77	bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
b560a58c FF	78
b560a58c FF	79	/* Switch to CORE_BASE1E */
9200c27a	80	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
b560a58c	81
9c41f2ba	82	r_rc_cal_reset(phydev);
b560a58c	83
9918542e	84	/* write AFE_RXCONFIG_0 */
a1cba561	85	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
9918542e FF	86
9918542e FF	87	/* write AFE_RXCONFIG_1 */
a1cba561	88	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
9918542e FF	89
9918542e FF	90	/* write AFE_RX_LP_COUNTER */
a1cba561	91	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
9918542e FF	92
9918542e FF	93	/* write AFE_HPF_TRIM_OTHERS */
a1cba561	94	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
9918542e FF	95
9918542e FF	96	/* write AFTE_TX_CONFIG */
a1cba561	97	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
9918542e	98
b560a58c FF	99	return 0;
	100	}
	101
a490631f FF	102	static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
	103	{
	104	/* AFE_RXCONFIG_0 */
a1cba561	105	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
a490631f FF	106
a490631f FF	107	/* AFE_RXCONFIG_1 */
a1cba561	108	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
a490631f FF	109
a490631f FF	110	/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
a1cba561	111	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
a490631f FF	112
a490631f FF	113	/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
a1cba561	114	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
a490631f	115
6da8253b	116	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
a1cba561	117	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
a490631f FF	118
a490631f FF	119	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
a1cba561	120	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
a490631f FF	121
a490631f FF	122	/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
a1cba561	123	bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
a490631f FF	124
	125	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	126	* offset for HT=0 code
	127	*/
a1cba561	128	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
a490631f FF	129
a490631f FF	130	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
9200c27a	131	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
a490631f FF	132
a490631f FF	133	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
a1cba561	134	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
a490631f FF	135
	136	/* Reset R_CAL/RC_CAL engine */
	137	r_rc_cal_reset(phydev);
	138
	139	return 0;
	140	}
	141
0c2fdc25 FF	142	static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
	143	{
	144	/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
a1cba561	145	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
0c2fdc25	146
6da8253b	147	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
a1cba561	148	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
6da8253b	149
0c2fdc25	150	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
a1cba561	151	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
0c2fdc25 FF	152
	153	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	154	* offset for HT=0 code
	155	*/
a1cba561	156	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
0c2fdc25 FF	157
0c2fdc25 FF	158	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
9200c27a	159	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
0c2fdc25 FF	160
0c2fdc25 FF	161	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
a1cba561	162	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
0c2fdc25 FF	163
	164	/* Reset R_CAL/RC_CAL engine */
	165	r_rc_cal_reset(phydev);
	166
	167	return 0;
	168	}
	169
039a7b85 FF	170	static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
	171	{
	172	/* +1 RC_CAL codes for RL centering for both LT and HT conditions */
	173	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
	174
	175	/* Cut master bias current by 2% to compensate for RC_CAL offset */
	176	bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
	177
	178	/* Improve hybrid leakage */
	179	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
	180
	181	/* Change rx_on_tune 8 to 0xf */
	182	bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
	183
	184	/* Change 100Tx EEE bandwidth */
	185	bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
	186
	187	/* Enable ffe zero detection for Vitesse interoperability */
	188	bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
	189
	190	r_rc_cal_reset(phydev);
	191
	192	return 0;
	193	}
	194
b560a58c FF	195	static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
b560a58c FF	196	{
d8ebfed3 FF	197	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
d8ebfed3 FF	198	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
db88816b	199	u8 count;
d8ebfed3 FF	200	int ret = 0;
d8ebfed3 FF	201
039a7b85 FF	202	/* Newer devices have moved the revision information back into a
	203	* standard location in MII_PHYS_ID[23]
	204	*/
	205	if (rev == 0)
	206	rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
	207
6ec259c1	208	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
84eff6d1	209	phydev_name(phydev), phydev->drv->name, rev, patch);
d8ebfed3	210
8e346e15 FF	211	/* Dummy read to a register to workaround an issue upon reset where the
	212	* internal inverter may not allow the first MDIO transaction to pass
	213	* the MDIO management controller and make us return 0xffff for such
	214	* reads.
	215	*/
	216	phy_read(phydev, MII_BMSR);
	217
d8ebfed3	218	switch (rev) {
d8ebfed3	219	case 0xb0:
2a9df742	220	ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
d8ebfed3	221	break;
a490631f FF	222	case 0xd0:
	223	ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
	224	break;
0c2fdc25 FF	225	case 0xe0:
0c2fdc25 FF	226	case 0xf0:
60efff0c FF	227	/* Rev G0 introduces a roll over */
60efff0c FF	228	case 0x10:
0c2fdc25 FF	229	ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
0c2fdc25 FF	230	break;
039a7b85 FF	231	case 0x01:
	232	ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
	233	break;
d8ebfed3	234	default:
d8ebfed3 FF	235	break;
d8ebfed3 FF	236	}
b560a58c	237
9df54dda FF	238	if (ret)
	239	return ret;
	240
db88816b FF	241	ret = bcm_phy_downshift_get(phydev, &count);
	242	if (ret)
	243	return ret;
	244
	245	/* Only enable EEE if Wirespeed/downshift is disabled */
	246	ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
b8f9a029 FF	247	if (ret)
	248	return ret;
	249
a1cba561	250	return bcm_phy_enable_apd(phydev, true);
b560a58c FF	251	}
b560a58c FF	252
4fd14e0b FF	253	static int bcm7xxx_28nm_resume(struct phy_device *phydev)
	254	{
	255	int ret;
	256
	257	/* Re-apply workarounds coming out suspend/resume */
	258	ret = bcm7xxx_28nm_config_init(phydev);
	259	if (ret)
	260	return ret;
	261
	262	/* 28nm Gigabit PHYs come out of reset without any half-duplex
	263	* or "hub" compliant advertised mode, fix that. This does not
	264	* cause any problems with the PHY library since genphy_config_aneg()
	265	* gracefully handles auto-negotiated and forced modes.
	266	*/
	267	return genphy_config_aneg(phydev);
	268	}
	269
b560a58c FF	270	static int phy_set_clr_bits(struct phy_device *dev, int location,
	271	int set_mask, int clr_mask)
	272	{
	273	int v, ret;
	274
	275	v = phy_read(dev, location);
	276	if (v < 0)
	277	return v;
	278
	279	v &= ~clr_mask;
	280	v \|= set_mask;
	281
	282	ret = phy_write(dev, location, v);
	283	if (ret < 0)
	284	return ret;
	285
	286	return v;
	287	}
	288
	289	static int bcm7xxx_config_init(struct phy_device *phydev)
	290	{
	291	int ret;
	292
	293	/* Enable 64 clock MDIO */
3ccc3055	294	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
b560a58c FF	295	phy_read(phydev, MII_BCM7XXX_AUX_MODE);
b560a58c FF	296
b560a58c FF	297	/* set shadow mode 2 */
	298	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
	299	MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
	300	if (ret < 0)
	301	return ret;
	302
	303	/* set iddq_clkbias */
	304	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
	305	udelay(10);
	306
	307	/* reset iddq_clkbias */
	308	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
	309
	310	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
	311
	312	/* reset shadow mode 2 */
50d89980	313	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
b560a58c FF	314	if (ret < 0)
	315	return ret;
	316
	317	return 0;
	318	}
	319
	320	/* Workaround for putting the PHY in IDDQ mode, required
82c084f5	321	* for all BCM7XXX 40nm and 65nm PHYs
b560a58c FF	322	*/
	323	static int bcm7xxx_suspend(struct phy_device *phydev)
	324	{
	325	int ret;
	326	const struct bcm7xxx_regs {
	327	int reg;
	328	u16 value;
	329	} bcm7xxx_suspend_cfg[] = {
	330	{ MII_BCM7XXX_TEST, 0x008b },
	331	{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
	332	{ MII_BCM7XXX_100TX_DISC, 0x7000 },
	333	{ MII_BCM7XXX_TEST, 0x000f },
	334	{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
	335	{ MII_BCM7XXX_TEST, 0x000b },
	336	};
	337	unsigned int i;
	338
	339	for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
	340	ret = phy_write(phydev,
	341	bcm7xxx_suspend_cfg[i].reg,
	342	bcm7xxx_suspend_cfg[i].value);
	343	if (ret)
	344	return ret;
	345	}
	346
	347	return 0;
	348	}
	349
db88816b FF	350	static int bcm7xxx_28nm_get_tunable(struct phy_device *phydev,
	351	struct ethtool_tunable *tuna,
	352	void *data)
	353	{
	354	switch (tuna->id) {
	355	case ETHTOOL_PHY_DOWNSHIFT:
	356	return bcm_phy_downshift_get(phydev, (u8 *)data);
	357	default:
	358	return -EOPNOTSUPP;
	359	}
	360	}
	361
	362	static int bcm7xxx_28nm_set_tunable(struct phy_device *phydev,
	363	struct ethtool_tunable *tuna,
	364	const void *data)
	365	{
	366	u8 count = (u8 )data;
	367	int ret;
	368
	369	switch (tuna->id) {
	370	case ETHTOOL_PHY_DOWNSHIFT:
	371	ret = bcm_phy_downshift_set(phydev, count);
	372	break;
	373	default:
	374	return -EOPNOTSUPP;
	375	}
	376
	377	if (ret)
	378	return ret;
	379
	380	/* Disable EEE advertisment since this prevents the PHY
	381	* from successfully linking up, trigger auto-negotiation restart
	382	* to let the MAC decide what to do.
	383	*/
	384	ret = bcm_phy_set_eee(phydev, count == DOWNSHIFT_DEV_DISABLE);
	385	if (ret)
	386	return ret;
	387
	388	return genphy_restart_aneg(phydev);
	389	}
	390
b23ce9e8 FF	391	static void bcm7xxx_28nm_get_phy_stats(struct phy_device *phydev,
	392	struct ethtool_stats stats, u64 data)
	393	{
	394	struct bcm7xxx_phy_priv *priv = phydev->priv;
	395
	396	bcm_phy_get_stats(phydev, priv->stats, stats, data);
	397	}
	398
	399	static int bcm7xxx_28nm_probe(struct phy_device *phydev)
	400	{
	401	struct bcm7xxx_phy_priv *priv;
	402
	403	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
	404	if (!priv)
	405	return -ENOMEM;
	406
	407	phydev->priv = priv;
	408
	409	priv->stats = devm_kcalloc(&phydev->mdio.dev,
	410	bcm_phy_get_sset_count(phydev), sizeof(u64),
	411	GFP_KERNEL);
	412	if (!priv->stats)
	413	return -ENOMEM;
	414
	415	return 0;
	416	}
	417
153df3c7 FF	418	#define BCM7XXX_28NM_GPHY(_oui, _name) \
	419	{ \
	420	.phy_id = (_oui), \
	421	.phy_id_mask = 0xfffffff0, \
	422	.name = _name, \
529ed127	423	.features = PHY_GBIT_FEATURES, \
153df3c7	424	.flags = PHY_IS_INTERNAL, \
2a9df742	425	.config_init = bcm7xxx_28nm_config_init, \
153df3c7 FF	426	.config_aneg = genphy_config_aneg, \
	427	.read_status = genphy_read_status, \
	428	.resume = bcm7xxx_28nm_resume, \
db88816b FF	429	.get_tunable = bcm7xxx_28nm_get_tunable, \
db88816b FF	430	.set_tunable = bcm7xxx_28nm_set_tunable, \
b23ce9e8 FF	431	.get_sset_count = bcm_phy_get_sset_count, \
	432	.get_strings = bcm_phy_get_strings, \
	433	.get_stats = bcm7xxx_28nm_get_phy_stats, \
	434	.probe = bcm7xxx_28nm_probe, \
153df3c7 FF	435	}
153df3c7 FF	436
3125c081 FF	437	#define BCM7XXX_40NM_EPHY(_oui, _name) \
	438	{ \
	439	.phy_id = (_oui), \
	440	.phy_id_mask = 0xfffffff0, \
	441	.name = _name, \
529ed127	442	.features = PHY_BASIC_FEATURES, \
3125c081 FF	443	.flags = PHY_IS_INTERNAL, \
	444	.config_init = bcm7xxx_config_init, \
	445	.config_aneg = genphy_config_aneg, \
	446	.read_status = genphy_read_status, \
	447	.suspend = bcm7xxx_suspend, \
	448	.resume = bcm7xxx_config_init, \
	449	}
	450
b560a58c	451	static struct phy_driver bcm7xxx_driver[] = {
430ad68f	452	BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
582d0ac3	453	BCM7XXX_28NM_GPHY(PHY_ID_BCM7278, "Broadcom BCM7278"),
430ad68f	454	BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
153df3c7	455	BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
b08d46b0	456	BCM7XXX_28NM_GPHY(PHY_ID_BCM74371, "Broadcom BCM74371"),
153df3c7	457	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
59e33c2b	458	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
153df3c7	459	BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
4cef191d JS	460	BCM7XXX_40NM_EPHY(PHY_ID_BCM7346, "Broadcom BCM7346"),
4cef191d JS	461	BCM7XXX_40NM_EPHY(PHY_ID_BCM7362, "Broadcom BCM7362"),
3125c081 FF	462	BCM7XXX_40NM_EPHY(PHY_ID_BCM7425, "Broadcom BCM7425"),
	463	BCM7XXX_40NM_EPHY(PHY_ID_BCM7429, "Broadcom BCM7429"),
	464	BCM7XXX_40NM_EPHY(PHY_ID_BCM7435, "Broadcom BCM7435"),
b6333531	465	};
b560a58c FF	466
b560a58c FF	467	static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
430ad68f	468	{ PHY_ID_BCM7250, 0xfffffff0, },
582d0ac3	469	{ PHY_ID_BCM7278, 0xfffffff0, },
430ad68f	470	{ PHY_ID_BCM7364, 0xfffffff0, },
b560a58c	471	{ PHY_ID_BCM7366, 0xfffffff0, },
4cef191d JS	472	{ PHY_ID_BCM7346, 0xfffffff0, },
4cef191d JS	473	{ PHY_ID_BCM7362, 0xfffffff0, },
d068b02c PG	474	{ PHY_ID_BCM7425, 0xfffffff0, },
d068b02c PG	475	{ PHY_ID_BCM7429, 0xfffffff0, },
b08d46b0	476	{ PHY_ID_BCM74371, 0xfffffff0, },
b560a58c	477	{ PHY_ID_BCM7439, 0xfffffff0, },
9458ceab	478	{ PHY_ID_BCM7435, 0xfffffff0, },
b560a58c	479	{ PHY_ID_BCM7445, 0xfffffff0, },
b560a58c FF	480	{ }
	481	};
	482
50fd7150	483	module_phy_driver(bcm7xxx_driver);
b560a58c FF	484
	485	MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
	486
	487	MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
	488	MODULE_LICENSE("GPL");
	489	MODULE_AUTHOR("Broadcom Corporation");