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00db8189 AF |
1 | /* |
2 | * drivers/net/phy/davicom.c | |
3 | * | |
4 | * Driver for Davicom PHYs | |
5 | * | |
6 | * Author: Andy Fleming | |
7 | * | |
8 | * Copyright (c) 2004 Freescale Semiconductor, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | * | |
15 | */ | |
00db8189 AF |
16 | #include <linux/kernel.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/unistd.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/skbuff.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/module.h> | |
00db8189 AF |
31 | #include <linux/mii.h> |
32 | #include <linux/ethtool.h> | |
33 | #include <linux/phy.h> | |
34 | ||
35 | #include <asm/io.h> | |
36 | #include <asm/irq.h> | |
37 | #include <asm/uaccess.h> | |
38 | ||
39 | #define MII_DM9161_SCR 0x10 | |
40 | #define MII_DM9161_SCR_INIT 0x0610 | |
41 | ||
42 | /* DM9161 Interrupt Register */ | |
43 | #define MII_DM9161_INTR 0x15 | |
44 | #define MII_DM9161_INTR_PEND 0x8000 | |
45 | #define MII_DM9161_INTR_DPLX_MASK 0x0800 | |
46 | #define MII_DM9161_INTR_SPD_MASK 0x0400 | |
47 | #define MII_DM9161_INTR_LINK_MASK 0x0200 | |
48 | #define MII_DM9161_INTR_MASK 0x0100 | |
49 | #define MII_DM9161_INTR_DPLX_CHANGE 0x0010 | |
50 | #define MII_DM9161_INTR_SPD_CHANGE 0x0008 | |
51 | #define MII_DM9161_INTR_LINK_CHANGE 0x0004 | |
52 | #define MII_DM9161_INTR_INIT 0x0000 | |
53 | #define MII_DM9161_INTR_STOP \ | |
54 | (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \ | |
55 | | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK) | |
56 | ||
57 | /* DM9161 10BT Configuration/Status */ | |
58 | #define MII_DM9161_10BTCSR 0x12 | |
59 | #define MII_DM9161_10BTCSR_INIT 0x7800 | |
60 | ||
61 | MODULE_DESCRIPTION("Davicom PHY driver"); | |
62 | MODULE_AUTHOR("Andy Fleming"); | |
63 | MODULE_LICENSE("GPL"); | |
64 | ||
65 | ||
66 | #define DM9161_DELAY 1 | |
67 | static int dm9161_config_intr(struct phy_device *phydev) | |
68 | { | |
69 | int temp; | |
70 | ||
71 | temp = phy_read(phydev, MII_DM9161_INTR); | |
72 | ||
73 | if (temp < 0) | |
74 | return temp; | |
75 | ||
76 | if(PHY_INTERRUPT_ENABLED == phydev->interrupts ) | |
77 | temp &= ~(MII_DM9161_INTR_STOP); | |
78 | else | |
79 | temp |= MII_DM9161_INTR_STOP; | |
80 | ||
81 | temp = phy_write(phydev, MII_DM9161_INTR, temp); | |
82 | ||
83 | return temp; | |
84 | } | |
85 | ||
86 | static int dm9161_config_aneg(struct phy_device *phydev) | |
87 | { | |
88 | int err; | |
89 | ||
90 | /* Isolate the PHY */ | |
91 | err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); | |
92 | ||
93 | if (err < 0) | |
94 | return err; | |
95 | ||
96 | /* Configure the new settings */ | |
97 | err = genphy_config_aneg(phydev); | |
98 | ||
99 | if (err < 0) | |
100 | return err; | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
105 | static int dm9161_config_init(struct phy_device *phydev) | |
106 | { | |
107 | int err; | |
108 | ||
109 | /* Isolate the PHY */ | |
110 | err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); | |
111 | ||
112 | if (err < 0) | |
113 | return err; | |
114 | ||
115 | /* Do not bypass the scrambler/descrambler */ | |
116 | err = phy_write(phydev, MII_DM9161_SCR, MII_DM9161_SCR_INIT); | |
117 | ||
118 | if (err < 0) | |
119 | return err; | |
120 | ||
121 | /* Clear 10BTCSR to default */ | |
122 | err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); | |
123 | ||
124 | if (err < 0) | |
125 | return err; | |
126 | ||
127 | /* Reconnect the PHY, and enable Autonegotiation */ | |
128 | err = phy_write(phydev, MII_BMCR, BMCR_ANENABLE); | |
129 | ||
130 | if (err < 0) | |
131 | return err; | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | static int dm9161_ack_interrupt(struct phy_device *phydev) | |
137 | { | |
138 | int err = phy_read(phydev, MII_DM9161_INTR); | |
139 | ||
140 | return (err < 0) ? err : 0; | |
141 | } | |
142 | ||
143 | static struct phy_driver dm9161_driver = { | |
144 | .phy_id = 0x0181b880, | |
145 | .name = "Davicom DM9161E", | |
146 | .phy_id_mask = 0x0ffffff0, | |
147 | .features = PHY_BASIC_FEATURES, | |
148 | .config_init = dm9161_config_init, | |
149 | .config_aneg = dm9161_config_aneg, | |
150 | .read_status = genphy_read_status, | |
151 | .driver = { .owner = THIS_MODULE,}, | |
152 | }; | |
153 | ||
154 | static struct phy_driver dm9131_driver = { | |
155 | .phy_id = 0x00181b80, | |
156 | .name = "Davicom DM9131", | |
157 | .phy_id_mask = 0x0ffffff0, | |
158 | .features = PHY_BASIC_FEATURES, | |
159 | .flags = PHY_HAS_INTERRUPT, | |
160 | .config_aneg = genphy_config_aneg, | |
161 | .read_status = genphy_read_status, | |
162 | .ack_interrupt = dm9161_ack_interrupt, | |
163 | .config_intr = dm9161_config_intr, | |
164 | .driver = { .owner = THIS_MODULE,}, | |
165 | }; | |
166 | ||
167 | static int __init davicom_init(void) | |
168 | { | |
169 | int ret; | |
170 | ||
171 | ret = phy_driver_register(&dm9161_driver); | |
172 | if (ret) | |
173 | goto err1; | |
174 | ||
175 | ret = phy_driver_register(&dm9131_driver); | |
176 | if (ret) | |
177 | goto err2; | |
178 | return 0; | |
179 | ||
180 | err2: | |
181 | phy_driver_unregister(&dm9161_driver); | |
182 | err1: | |
183 | return ret; | |
184 | } | |
185 | ||
186 | static void __exit davicom_exit(void) | |
187 | { | |
188 | phy_driver_unregister(&dm9161_driver); | |
189 | phy_driver_unregister(&dm9131_driver); | |
190 | } | |
191 | ||
192 | module_init(davicom_init); | |
193 | module_exit(davicom_exit); |