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cb646e2b RC |
1 | /* |
2 | * Driver for the National Semiconductor DP83640 PHYTER | |
3 | * | |
4 | * Copyright (C) 2010 OMICRON electronics GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
8d242488 JP |
20 | |
21 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
22 | ||
539e44d2 | 23 | #include <linux/crc32.h> |
cb646e2b RC |
24 | #include <linux/ethtool.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/mii.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/net_tstamp.h> | |
30 | #include <linux/netdevice.h> | |
408eccce | 31 | #include <linux/if_vlan.h> |
cb646e2b RC |
32 | #include <linux/phy.h> |
33 | #include <linux/ptp_classify.h> | |
34 | #include <linux/ptp_clock_kernel.h> | |
35 | ||
36 | #include "dp83640_reg.h" | |
37 | ||
38 | #define DP83640_PHY_ID 0x20005ce1 | |
39 | #define PAGESEL 0x13 | |
40 | #define LAYER4 0x02 | |
41 | #define LAYER2 0x01 | |
8028837d | 42 | #define MAX_RXTS 64 |
49b3fd4a | 43 | #define N_EXT_TS 6 |
ad01577a | 44 | #define N_PER_OUT 7 |
cb646e2b RC |
45 | #define PSF_PTPVER 2 |
46 | #define PSF_EVNT 0x4000 | |
47 | #define PSF_RX 0x2000 | |
48 | #define PSF_TX 0x1000 | |
49 | #define EXT_EVENT 1 | |
49b3fd4a | 50 | #define CAL_EVENT 7 |
397a253a | 51 | #define CAL_TRIGGER 1 |
86dd3612 | 52 | #define DP83640_N_PINS 12 |
cb646e2b | 53 | |
1642182e SG |
54 | #define MII_DP83640_MICR 0x11 |
55 | #define MII_DP83640_MISR 0x12 | |
56 | ||
57 | #define MII_DP83640_MICR_OE 0x1 | |
58 | #define MII_DP83640_MICR_IE 0x2 | |
59 | ||
60 | #define MII_DP83640_MISR_RHF_INT_EN 0x01 | |
61 | #define MII_DP83640_MISR_FHF_INT_EN 0x02 | |
62 | #define MII_DP83640_MISR_ANC_INT_EN 0x04 | |
63 | #define MII_DP83640_MISR_DUP_INT_EN 0x08 | |
64 | #define MII_DP83640_MISR_SPD_INT_EN 0x10 | |
65 | #define MII_DP83640_MISR_LINK_INT_EN 0x20 | |
66 | #define MII_DP83640_MISR_ED_INT_EN 0x40 | |
67 | #define MII_DP83640_MISR_LQ_INT_EN 0x80 | |
68 | ||
cb646e2b RC |
69 | /* phyter seems to miss the mark by 16 ns */ |
70 | #define ADJTIME_FIX 16 | |
71 | ||
72 | #if defined(__BIG_ENDIAN) | |
73 | #define ENDIAN_FLAG 0 | |
74 | #elif defined(__LITTLE_ENDIAN) | |
75 | #define ENDIAN_FLAG PSF_ENDIAN | |
76 | #endif | |
77 | ||
63502b8d SS |
78 | struct dp83640_skb_info { |
79 | int ptp_type; | |
80 | unsigned long tmo; | |
81 | }; | |
cb646e2b RC |
82 | |
83 | struct phy_rxts { | |
84 | u16 ns_lo; /* ns[15:0] */ | |
85 | u16 ns_hi; /* overflow[1:0], ns[29:16] */ | |
86 | u16 sec_lo; /* sec[15:0] */ | |
87 | u16 sec_hi; /* sec[31:16] */ | |
88 | u16 seqid; /* sequenceId[15:0] */ | |
89 | u16 msgtype; /* messageType[3:0], hash[11:0] */ | |
90 | }; | |
91 | ||
92 | struct phy_txts { | |
93 | u16 ns_lo; /* ns[15:0] */ | |
94 | u16 ns_hi; /* overflow[1:0], ns[29:16] */ | |
95 | u16 sec_lo; /* sec[15:0] */ | |
96 | u16 sec_hi; /* sec[31:16] */ | |
97 | }; | |
98 | ||
99 | struct rxts { | |
100 | struct list_head list; | |
101 | unsigned long tmo; | |
102 | u64 ns; | |
103 | u16 seqid; | |
104 | u8 msgtype; | |
105 | u16 hash; | |
106 | }; | |
107 | ||
108 | struct dp83640_clock; | |
109 | ||
110 | struct dp83640_private { | |
111 | struct list_head list; | |
112 | struct dp83640_clock *clock; | |
113 | struct phy_device *phydev; | |
114 | struct work_struct ts_work; | |
115 | int hwts_tx_en; | |
116 | int hwts_rx_en; | |
117 | int layer; | |
118 | int version; | |
119 | /* remember state of cfg0 during calibration */ | |
120 | int cfg0; | |
121 | /* remember the last event time stamp */ | |
122 | struct phy_txts edata; | |
123 | /* list of rx timestamps */ | |
124 | struct list_head rxts; | |
125 | struct list_head rxpool; | |
126 | struct rxts rx_pool_data[MAX_RXTS]; | |
127 | /* protects above three fields from concurrent access */ | |
128 | spinlock_t rx_lock; | |
129 | /* queues of incoming and outgoing packets */ | |
130 | struct sk_buff_head rx_queue; | |
131 | struct sk_buff_head tx_queue; | |
132 | }; | |
133 | ||
134 | struct dp83640_clock { | |
135 | /* keeps the instance in the 'phyter_clocks' list */ | |
136 | struct list_head list; | |
137 | /* we create one clock instance per MII bus */ | |
138 | struct mii_bus *bus; | |
139 | /* protects extended registers from concurrent access */ | |
140 | struct mutex extreg_lock; | |
141 | /* remembers which page was last selected */ | |
142 | int page; | |
143 | /* our advertised capabilities */ | |
144 | struct ptp_clock_info caps; | |
145 | /* protects the three fields below from concurrent access */ | |
146 | struct mutex clock_lock; | |
147 | /* the one phyter from which we shall read */ | |
148 | struct dp83640_private *chosen; | |
149 | /* list of the other attached phyters, not chosen */ | |
150 | struct list_head phylist; | |
151 | /* reference to our PTP hardware clock */ | |
152 | struct ptp_clock *ptp_clock; | |
153 | }; | |
154 | ||
155 | /* globals */ | |
156 | ||
49b3fd4a RC |
157 | enum { |
158 | CALIBRATE_GPIO, | |
159 | PEROUT_GPIO, | |
160 | EXTTS0_GPIO, | |
161 | EXTTS1_GPIO, | |
162 | EXTTS2_GPIO, | |
163 | EXTTS3_GPIO, | |
164 | EXTTS4_GPIO, | |
165 | EXTTS5_GPIO, | |
166 | GPIO_TABLE_SIZE | |
167 | }; | |
168 | ||
cb646e2b | 169 | static int chosen_phy = -1; |
49b3fd4a RC |
170 | static ushort gpio_tab[GPIO_TABLE_SIZE] = { |
171 | 1, 2, 3, 4, 8, 9, 10, 11 | |
172 | }; | |
cb646e2b RC |
173 | |
174 | module_param(chosen_phy, int, 0444); | |
49b3fd4a | 175 | module_param_array(gpio_tab, ushort, NULL, 0444); |
cb646e2b RC |
176 | |
177 | MODULE_PARM_DESC(chosen_phy, \ | |
178 | "The address of the PHY to use for the ancillary clock features"); | |
49b3fd4a RC |
179 | MODULE_PARM_DESC(gpio_tab, \ |
180 | "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6"); | |
cb646e2b | 181 | |
86dd3612 RC |
182 | static void dp83640_gpio_defaults(struct ptp_pin_desc *pd) |
183 | { | |
184 | int i, index; | |
185 | ||
186 | for (i = 0; i < DP83640_N_PINS; i++) { | |
187 | snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i); | |
188 | pd[i].index = i; | |
189 | } | |
190 | ||
191 | for (i = 0; i < GPIO_TABLE_SIZE; i++) { | |
192 | if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) { | |
193 | pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]); | |
194 | return; | |
195 | } | |
196 | } | |
197 | ||
198 | index = gpio_tab[CALIBRATE_GPIO] - 1; | |
199 | pd[index].func = PTP_PF_PHYSYNC; | |
200 | pd[index].chan = 0; | |
201 | ||
202 | index = gpio_tab[PEROUT_GPIO] - 1; | |
203 | pd[index].func = PTP_PF_PEROUT; | |
204 | pd[index].chan = 0; | |
205 | ||
206 | for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) { | |
207 | index = gpio_tab[i] - 1; | |
208 | pd[index].func = PTP_PF_EXTTS; | |
209 | pd[index].chan = i - EXTTS0_GPIO; | |
210 | } | |
211 | } | |
212 | ||
cb646e2b RC |
213 | /* a list of clocks and a mutex to protect it */ |
214 | static LIST_HEAD(phyter_clocks); | |
215 | static DEFINE_MUTEX(phyter_clocks_lock); | |
216 | ||
217 | static void rx_timestamp_work(struct work_struct *work); | |
218 | ||
219 | /* extended register access functions */ | |
220 | ||
221 | #define BROADCAST_ADDR 31 | |
222 | ||
223 | static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val) | |
224 | { | |
225 | return mdiobus_write(bus, BROADCAST_ADDR, regnum, val); | |
226 | } | |
227 | ||
228 | /* Caller must hold extreg_lock. */ | |
229 | static int ext_read(struct phy_device *phydev, int page, u32 regnum) | |
230 | { | |
231 | struct dp83640_private *dp83640 = phydev->priv; | |
232 | int val; | |
233 | ||
234 | if (dp83640->clock->page != page) { | |
235 | broadcast_write(phydev->bus, PAGESEL, page); | |
236 | dp83640->clock->page = page; | |
237 | } | |
238 | val = phy_read(phydev, regnum); | |
239 | ||
240 | return val; | |
241 | } | |
242 | ||
243 | /* Caller must hold extreg_lock. */ | |
244 | static void ext_write(int broadcast, struct phy_device *phydev, | |
245 | int page, u32 regnum, u16 val) | |
246 | { | |
247 | struct dp83640_private *dp83640 = phydev->priv; | |
248 | ||
249 | if (dp83640->clock->page != page) { | |
250 | broadcast_write(phydev->bus, PAGESEL, page); | |
251 | dp83640->clock->page = page; | |
252 | } | |
253 | if (broadcast) | |
254 | broadcast_write(phydev->bus, regnum, val); | |
255 | else | |
256 | phy_write(phydev, regnum, val); | |
257 | } | |
258 | ||
259 | /* Caller must hold extreg_lock. */ | |
260 | static int tdr_write(int bc, struct phy_device *dev, | |
41c2c18f | 261 | const struct timespec64 *ts, u16 cmd) |
cb646e2b RC |
262 | { |
263 | ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */ | |
264 | ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */ | |
265 | ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */ | |
266 | ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/ | |
267 | ||
268 | ext_write(bc, dev, PAGE4, PTP_CTL, cmd); | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | /* convert phy timestamps into driver timestamps */ | |
274 | ||
275 | static void phy2rxts(struct phy_rxts *p, struct rxts *rxts) | |
276 | { | |
277 | u32 sec; | |
278 | ||
279 | sec = p->sec_lo; | |
280 | sec |= p->sec_hi << 16; | |
281 | ||
282 | rxts->ns = p->ns_lo; | |
283 | rxts->ns |= (p->ns_hi & 0x3fff) << 16; | |
284 | rxts->ns += ((u64)sec) * 1000000000ULL; | |
285 | rxts->seqid = p->seqid; | |
286 | rxts->msgtype = (p->msgtype >> 12) & 0xf; | |
287 | rxts->hash = p->msgtype & 0x0fff; | |
8028837d | 288 | rxts->tmo = jiffies + 2; |
cb646e2b RC |
289 | } |
290 | ||
291 | static u64 phy2txts(struct phy_txts *p) | |
292 | { | |
293 | u64 ns; | |
294 | u32 sec; | |
295 | ||
296 | sec = p->sec_lo; | |
297 | sec |= p->sec_hi << 16; | |
298 | ||
299 | ns = p->ns_lo; | |
300 | ns |= (p->ns_hi & 0x3fff) << 16; | |
301 | ns += ((u64)sec) * 1000000000ULL; | |
302 | ||
303 | return ns; | |
304 | } | |
305 | ||
621bdecc | 306 | static int periodic_output(struct dp83640_clock *clock, |
ad01577a SS |
307 | struct ptp_clock_request *clkreq, bool on, |
308 | int trigger) | |
49b3fd4a RC |
309 | { |
310 | struct dp83640_private *dp83640 = clock->chosen; | |
311 | struct phy_device *phydev = dp83640->phydev; | |
564ca56e | 312 | u32 sec, nsec, pwidth; |
ad01577a | 313 | u16 gpio, ptp_trig, val; |
49b3fd4a | 314 | |
621bdecc | 315 | if (on) { |
ad01577a SS |
316 | gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, |
317 | trigger); | |
621bdecc RC |
318 | if (gpio < 1) |
319 | return -EINVAL; | |
320 | } else { | |
321 | gpio = 0; | |
322 | } | |
323 | ||
49b3fd4a RC |
324 | ptp_trig = TRIG_WR | |
325 | (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | | |
326 | (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | | |
327 | TRIG_PER | | |
328 | TRIG_PULSE; | |
329 | ||
330 | val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; | |
331 | ||
332 | if (!on) { | |
333 | val |= TRIG_DIS; | |
334 | mutex_lock(&clock->extreg_lock); | |
335 | ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); | |
336 | ext_write(0, phydev, PAGE4, PTP_CTL, val); | |
337 | mutex_unlock(&clock->extreg_lock); | |
621bdecc | 338 | return 0; |
49b3fd4a RC |
339 | } |
340 | ||
341 | sec = clkreq->perout.start.sec; | |
342 | nsec = clkreq->perout.start.nsec; | |
564ca56e RC |
343 | pwidth = clkreq->perout.period.sec * 1000000000UL; |
344 | pwidth += clkreq->perout.period.nsec; | |
345 | pwidth /= 2; | |
49b3fd4a RC |
346 | |
347 | mutex_lock(&clock->extreg_lock); | |
348 | ||
349 | ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig); | |
350 | ||
351 | /*load trigger*/ | |
352 | val |= TRIG_LOAD; | |
353 | ext_write(0, phydev, PAGE4, PTP_CTL, val); | |
354 | ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */ | |
355 | ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */ | |
356 | ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */ | |
357 | ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */ | |
564ca56e RC |
358 | ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */ |
359 | ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */ | |
35e872ae SS |
360 | /* Triggers 0 and 1 has programmable pulsewidth2 */ |
361 | if (trigger < 2) { | |
362 | ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); | |
363 | ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); | |
364 | } | |
49b3fd4a RC |
365 | |
366 | /*enable trigger*/ | |
367 | val &= ~TRIG_LOAD; | |
368 | val |= TRIG_EN; | |
369 | ext_write(0, phydev, PAGE4, PTP_CTL, val); | |
370 | ||
371 | mutex_unlock(&clock->extreg_lock); | |
621bdecc | 372 | return 0; |
49b3fd4a RC |
373 | } |
374 | ||
cb646e2b RC |
375 | /* ptp clock methods */ |
376 | ||
377 | static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb) | |
378 | { | |
379 | struct dp83640_clock *clock = | |
380 | container_of(ptp, struct dp83640_clock, caps); | |
381 | struct phy_device *phydev = clock->chosen->phydev; | |
382 | u64 rate; | |
383 | int neg_adj = 0; | |
384 | u16 hi, lo; | |
385 | ||
386 | if (ppb < 0) { | |
387 | neg_adj = 1; | |
388 | ppb = -ppb; | |
389 | } | |
390 | rate = ppb; | |
391 | rate <<= 26; | |
392 | rate = div_u64(rate, 1953125); | |
393 | ||
394 | hi = (rate >> 16) & PTP_RATE_HI_MASK; | |
395 | if (neg_adj) | |
396 | hi |= PTP_RATE_DIR; | |
397 | ||
398 | lo = rate & 0xffff; | |
399 | ||
400 | mutex_lock(&clock->extreg_lock); | |
401 | ||
402 | ext_write(1, phydev, PAGE4, PTP_RATEH, hi); | |
403 | ext_write(1, phydev, PAGE4, PTP_RATEL, lo); | |
404 | ||
405 | mutex_unlock(&clock->extreg_lock); | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
410 | static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta) | |
411 | { | |
412 | struct dp83640_clock *clock = | |
413 | container_of(ptp, struct dp83640_clock, caps); | |
414 | struct phy_device *phydev = clock->chosen->phydev; | |
41c2c18f | 415 | struct timespec64 ts; |
cb646e2b RC |
416 | int err; |
417 | ||
418 | delta += ADJTIME_FIX; | |
419 | ||
41c2c18f | 420 | ts = ns_to_timespec64(delta); |
cb646e2b RC |
421 | |
422 | mutex_lock(&clock->extreg_lock); | |
423 | ||
424 | err = tdr_write(1, phydev, &ts, PTP_STEP_CLK); | |
425 | ||
426 | mutex_unlock(&clock->extreg_lock); | |
427 | ||
428 | return err; | |
429 | } | |
430 | ||
41c2c18f RC |
431 | static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, |
432 | struct timespec64 *ts) | |
cb646e2b RC |
433 | { |
434 | struct dp83640_clock *clock = | |
435 | container_of(ptp, struct dp83640_clock, caps); | |
436 | struct phy_device *phydev = clock->chosen->phydev; | |
437 | unsigned int val[4]; | |
438 | ||
439 | mutex_lock(&clock->extreg_lock); | |
440 | ||
441 | ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK); | |
442 | ||
443 | val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */ | |
444 | val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */ | |
445 | val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */ | |
446 | val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */ | |
447 | ||
448 | mutex_unlock(&clock->extreg_lock); | |
449 | ||
450 | ts->tv_nsec = val[0] | (val[1] << 16); | |
451 | ts->tv_sec = val[2] | (val[3] << 16); | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
456 | static int ptp_dp83640_settime(struct ptp_clock_info *ptp, | |
41c2c18f | 457 | const struct timespec64 *ts) |
cb646e2b RC |
458 | { |
459 | struct dp83640_clock *clock = | |
460 | container_of(ptp, struct dp83640_clock, caps); | |
461 | struct phy_device *phydev = clock->chosen->phydev; | |
462 | int err; | |
463 | ||
464 | mutex_lock(&clock->extreg_lock); | |
465 | ||
466 | err = tdr_write(1, phydev, ts, PTP_LOAD_CLK); | |
467 | ||
468 | mutex_unlock(&clock->extreg_lock); | |
469 | ||
470 | return err; | |
471 | } | |
472 | ||
473 | static int ptp_dp83640_enable(struct ptp_clock_info *ptp, | |
474 | struct ptp_clock_request *rq, int on) | |
475 | { | |
476 | struct dp83640_clock *clock = | |
477 | container_of(ptp, struct dp83640_clock, caps); | |
478 | struct phy_device *phydev = clock->chosen->phydev; | |
fbf4b934 | 479 | unsigned int index; |
49b3fd4a | 480 | u16 evnt, event_num, gpio_num; |
cb646e2b RC |
481 | |
482 | switch (rq->type) { | |
483 | case PTP_CLK_REQ_EXTTS: | |
49b3fd4a | 484 | index = rq->extts.index; |
fbf4b934 | 485 | if (index >= N_EXT_TS) |
cb646e2b | 486 | return -EINVAL; |
49b3fd4a RC |
487 | event_num = EXT_EVENT + index; |
488 | evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; | |
cb646e2b | 489 | if (on) { |
faa89716 RC |
490 | gpio_num = 1 + ptp_find_pin(clock->ptp_clock, |
491 | PTP_PF_EXTTS, index); | |
492 | if (gpio_num < 1) | |
493 | return -EINVAL; | |
49b3fd4a | 494 | evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; |
80671bd2 SS |
495 | if (rq->extts.flags & PTP_FALLING_EDGE) |
496 | evnt |= EVNT_FALL; | |
497 | else | |
498 | evnt |= EVNT_RISE; | |
cb646e2b | 499 | } |
a935865c | 500 | mutex_lock(&clock->extreg_lock); |
cb646e2b | 501 | ext_write(0, phydev, PAGE5, PTP_EVNT, evnt); |
a935865c | 502 | mutex_unlock(&clock->extreg_lock); |
cb646e2b | 503 | return 0; |
49b3fd4a RC |
504 | |
505 | case PTP_CLK_REQ_PEROUT: | |
ad01577a | 506 | if (rq->perout.index >= N_PER_OUT) |
49b3fd4a | 507 | return -EINVAL; |
ad01577a | 508 | return periodic_output(clock, rq, on, rq->perout.index); |
49b3fd4a | 509 | |
cb646e2b RC |
510 | default: |
511 | break; | |
512 | } | |
513 | ||
514 | return -EOPNOTSUPP; | |
515 | } | |
516 | ||
86dd3612 RC |
517 | static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin, |
518 | enum ptp_pin_function func, unsigned int chan) | |
519 | { | |
6f39eb87 SS |
520 | struct dp83640_clock *clock = |
521 | container_of(ptp, struct dp83640_clock, caps); | |
522 | ||
523 | if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && | |
524 | !list_empty(&clock->phylist)) | |
525 | return 1; | |
526 | ||
527 | if (func == PTP_PF_PHYSYNC) | |
528 | return 1; | |
529 | ||
86dd3612 RC |
530 | return 0; |
531 | } | |
532 | ||
cb646e2b RC |
533 | static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 }; |
534 | static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F }; | |
535 | ||
536 | static void enable_status_frames(struct phy_device *phydev, bool on) | |
537 | { | |
a935865c RC |
538 | struct dp83640_private *dp83640 = phydev->priv; |
539 | struct dp83640_clock *clock = dp83640->clock; | |
cb646e2b RC |
540 | u16 cfg0 = 0, ver; |
541 | ||
542 | if (on) | |
543 | cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; | |
544 | ||
545 | ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT; | |
546 | ||
a935865c RC |
547 | mutex_lock(&clock->extreg_lock); |
548 | ||
cb646e2b RC |
549 | ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); |
550 | ext_write(0, phydev, PAGE6, PSF_CFG1, ver); | |
551 | ||
a935865c RC |
552 | mutex_unlock(&clock->extreg_lock); |
553 | ||
cb646e2b | 554 | if (!phydev->attached_dev) { |
8d242488 | 555 | pr_warn("expected to find an attached netdevice\n"); |
cb646e2b RC |
556 | return; |
557 | } | |
558 | ||
559 | if (on) { | |
560 | if (dev_mc_add(phydev->attached_dev, status_frame_dst)) | |
8d242488 | 561 | pr_warn("failed to add mc address\n"); |
cb646e2b RC |
562 | } else { |
563 | if (dev_mc_del(phydev->attached_dev, status_frame_dst)) | |
8d242488 | 564 | pr_warn("failed to delete mc address\n"); |
cb646e2b RC |
565 | } |
566 | } | |
567 | ||
568 | static bool is_status_frame(struct sk_buff *skb, int type) | |
569 | { | |
570 | struct ethhdr *h = eth_hdr(skb); | |
571 | ||
572 | if (PTP_CLASS_V2_L2 == type && | |
573 | !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src))) | |
574 | return true; | |
575 | else | |
576 | return false; | |
577 | } | |
578 | ||
579 | static int expired(struct rxts *rxts) | |
580 | { | |
581 | return time_after(jiffies, rxts->tmo); | |
582 | } | |
583 | ||
584 | /* Caller must hold rx_lock. */ | |
585 | static void prune_rx_ts(struct dp83640_private *dp83640) | |
586 | { | |
587 | struct list_head *this, *next; | |
588 | struct rxts *rxts; | |
589 | ||
590 | list_for_each_safe(this, next, &dp83640->rxts) { | |
591 | rxts = list_entry(this, struct rxts, list); | |
592 | if (expired(rxts)) { | |
593 | list_del_init(&rxts->list); | |
594 | list_add(&rxts->list, &dp83640->rxpool); | |
595 | } | |
596 | } | |
597 | } | |
598 | ||
599 | /* synchronize the phyters so they act as one clock */ | |
600 | ||
601 | static void enable_broadcast(struct phy_device *phydev, int init_page, int on) | |
602 | { | |
603 | int val; | |
604 | phy_write(phydev, PAGESEL, 0); | |
605 | val = phy_read(phydev, PHYCR2); | |
606 | if (on) | |
607 | val |= BC_WRITE; | |
608 | else | |
609 | val &= ~BC_WRITE; | |
610 | phy_write(phydev, PHYCR2, val); | |
611 | phy_write(phydev, PAGESEL, init_page); | |
612 | } | |
613 | ||
614 | static void recalibrate(struct dp83640_clock *clock) | |
615 | { | |
616 | s64 now, diff; | |
617 | struct phy_txts event_ts; | |
41c2c18f | 618 | struct timespec64 ts; |
cb646e2b RC |
619 | struct list_head *this; |
620 | struct dp83640_private *tmp; | |
621 | struct phy_device *master = clock->chosen->phydev; | |
49b3fd4a | 622 | u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; |
cb646e2b RC |
623 | |
624 | trigger = CAL_TRIGGER; | |
e0155950 SS |
625 | cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0); |
626 | if (cal_gpio < 1) { | |
f42cf8d6 | 627 | pr_err("PHY calibration pin not available - PHY is not calibrated."); |
e0155950 SS |
628 | return; |
629 | } | |
cb646e2b RC |
630 | |
631 | mutex_lock(&clock->extreg_lock); | |
632 | ||
633 | /* | |
634 | * enable broadcast, disable status frames, enable ptp clock | |
635 | */ | |
636 | list_for_each(this, &clock->phylist) { | |
637 | tmp = list_entry(this, struct dp83640_private, list); | |
638 | enable_broadcast(tmp->phydev, clock->page, 1); | |
639 | tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); | |
640 | ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0); | |
641 | ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE); | |
642 | } | |
643 | enable_broadcast(master, clock->page, 1); | |
644 | cfg0 = ext_read(master, PAGE5, PSF_CFG0); | |
645 | ext_write(0, master, PAGE5, PSF_CFG0, 0); | |
646 | ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE); | |
647 | ||
648 | /* | |
649 | * enable an event timestamp | |
650 | */ | |
651 | evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE; | |
652 | evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT; | |
653 | evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT; | |
654 | ||
655 | list_for_each(this, &clock->phylist) { | |
656 | tmp = list_entry(this, struct dp83640_private, list); | |
657 | ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt); | |
658 | } | |
659 | ext_write(0, master, PAGE5, PTP_EVNT, evnt); | |
660 | ||
661 | /* | |
662 | * configure a trigger | |
663 | */ | |
664 | ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE; | |
665 | ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT; | |
666 | ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT; | |
667 | ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig); | |
668 | ||
669 | /* load trigger */ | |
670 | val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; | |
671 | val |= TRIG_LOAD; | |
672 | ext_write(0, master, PAGE4, PTP_CTL, val); | |
673 | ||
674 | /* enable trigger */ | |
675 | val &= ~TRIG_LOAD; | |
676 | val |= TRIG_EN; | |
677 | ext_write(0, master, PAGE4, PTP_CTL, val); | |
678 | ||
679 | /* disable trigger */ | |
680 | val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT; | |
681 | val |= TRIG_DIS; | |
682 | ext_write(0, master, PAGE4, PTP_CTL, val); | |
683 | ||
684 | /* | |
685 | * read out and correct offsets | |
686 | */ | |
687 | val = ext_read(master, PAGE4, PTP_STS); | |
8d242488 | 688 | pr_info("master PTP_STS 0x%04hx\n", val); |
cb646e2b | 689 | val = ext_read(master, PAGE4, PTP_ESTS); |
8d242488 | 690 | pr_info("master PTP_ESTS 0x%04hx\n", val); |
cb646e2b RC |
691 | event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA); |
692 | event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA); | |
693 | event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA); | |
694 | event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA); | |
695 | now = phy2txts(&event_ts); | |
696 | ||
697 | list_for_each(this, &clock->phylist) { | |
698 | tmp = list_entry(this, struct dp83640_private, list); | |
699 | val = ext_read(tmp->phydev, PAGE4, PTP_STS); | |
8d242488 | 700 | pr_info("slave PTP_STS 0x%04hx\n", val); |
cb646e2b | 701 | val = ext_read(tmp->phydev, PAGE4, PTP_ESTS); |
8d242488 | 702 | pr_info("slave PTP_ESTS 0x%04hx\n", val); |
cb646e2b RC |
703 | event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); |
704 | event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); | |
705 | event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA); | |
706 | event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA); | |
707 | diff = now - (s64) phy2txts(&event_ts); | |
708 | pr_info("slave offset %lld nanoseconds\n", diff); | |
709 | diff += ADJTIME_FIX; | |
41c2c18f | 710 | ts = ns_to_timespec64(diff); |
cb646e2b RC |
711 | tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK); |
712 | } | |
713 | ||
714 | /* | |
715 | * restore status frames | |
716 | */ | |
717 | list_for_each(this, &clock->phylist) { | |
718 | tmp = list_entry(this, struct dp83640_private, list); | |
719 | ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); | |
720 | } | |
721 | ext_write(0, master, PAGE5, PSF_CFG0, cfg0); | |
722 | ||
723 | mutex_unlock(&clock->extreg_lock); | |
724 | } | |
725 | ||
726 | /* time stamping methods */ | |
727 | ||
49b3fd4a RC |
728 | static inline u16 exts_chan_to_edata(int ch) |
729 | { | |
730 | return 1 << ((ch + EXT_EVENT) * 2); | |
731 | } | |
732 | ||
2331038a | 733 | static int decode_evnt(struct dp83640_private *dp83640, |
13322f2e | 734 | void *data, int len, u16 ests) |
cb646e2b | 735 | { |
2331038a | 736 | struct phy_txts *phy_txts; |
cb646e2b | 737 | struct ptp_clock_event event; |
49b3fd4a | 738 | int i, parsed; |
cb646e2b | 739 | int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK; |
2331038a RC |
740 | u16 ext_status = 0; |
741 | ||
13322f2e CR |
742 | /* calculate length of the event timestamp status message */ |
743 | if (ests & MULT_EVNT) | |
744 | parsed = (words + 2) * sizeof(u16); | |
745 | else | |
746 | parsed = (words + 1) * sizeof(u16); | |
747 | ||
748 | /* check if enough data is available */ | |
749 | if (len < parsed) | |
750 | return len; | |
751 | ||
2331038a RC |
752 | if (ests & MULT_EVNT) { |
753 | ext_status = *(u16 *) data; | |
754 | data += sizeof(ext_status); | |
755 | } | |
756 | ||
757 | phy_txts = data; | |
cb646e2b RC |
758 | |
759 | switch (words) { /* fall through in every case */ | |
760 | case 3: | |
761 | dp83640->edata.sec_hi = phy_txts->sec_hi; | |
762 | case 2: | |
763 | dp83640->edata.sec_lo = phy_txts->sec_lo; | |
764 | case 1: | |
765 | dp83640->edata.ns_hi = phy_txts->ns_hi; | |
766 | case 0: | |
767 | dp83640->edata.ns_lo = phy_txts->ns_lo; | |
768 | } | |
769 | ||
13322f2e | 770 | if (!ext_status) { |
49b3fd4a RC |
771 | i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT; |
772 | ext_status = exts_chan_to_edata(i); | |
773 | } | |
774 | ||
cb646e2b | 775 | event.type = PTP_CLOCK_EXTTS; |
cb646e2b RC |
776 | event.timestamp = phy2txts(&dp83640->edata); |
777 | ||
a0077a9f SS |
778 | /* Compensate for input path and synchronization delays */ |
779 | event.timestamp -= 35; | |
780 | ||
49b3fd4a RC |
781 | for (i = 0; i < N_EXT_TS; i++) { |
782 | if (ext_status & exts_chan_to_edata(i)) { | |
783 | event.index = i; | |
784 | ptp_clock_event(dp83640->clock->ptp_clock, &event); | |
785 | } | |
786 | } | |
2331038a | 787 | |
13322f2e | 788 | return parsed; |
cb646e2b RC |
789 | } |
790 | ||
539e44d2 SS |
791 | #define DP83640_PACKET_HASH_OFFSET 20 |
792 | #define DP83640_PACKET_HASH_LEN 10 | |
793 | ||
63502b8d SS |
794 | static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts) |
795 | { | |
539e44d2 | 796 | u16 *seqid, hash; |
63502b8d SS |
797 | unsigned int offset = 0; |
798 | u8 *msgtype, *data = skb_mac_header(skb); | |
799 | ||
800 | /* check sequenceID, messageType, 12 bit hash of offset 20-29 */ | |
801 | ||
802 | if (type & PTP_CLASS_VLAN) | |
803 | offset += VLAN_HLEN; | |
804 | ||
805 | switch (type & PTP_CLASS_PMASK) { | |
806 | case PTP_CLASS_IPV4: | |
cca04b28 | 807 | offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN; |
63502b8d SS |
808 | break; |
809 | case PTP_CLASS_IPV6: | |
810 | offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; | |
811 | break; | |
812 | case PTP_CLASS_L2: | |
813 | offset += ETH_HLEN; | |
814 | break; | |
815 | default: | |
816 | return 0; | |
817 | } | |
818 | ||
819 | if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid)) | |
820 | return 0; | |
821 | ||
822 | if (unlikely(type & PTP_CLASS_V1)) | |
823 | msgtype = data + offset + OFF_PTP_CONTROL; | |
824 | else | |
825 | msgtype = data + offset; | |
539e44d2 SS |
826 | if (rxts->msgtype != (*msgtype & 0xf)) |
827 | return 0; | |
63502b8d SS |
828 | |
829 | seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); | |
539e44d2 SS |
830 | if (rxts->seqid != ntohs(*seqid)) |
831 | return 0; | |
832 | ||
833 | hash = ether_crc(DP83640_PACKET_HASH_LEN, | |
834 | data + offset + DP83640_PACKET_HASH_OFFSET) >> 20; | |
835 | if (rxts->hash != hash) | |
836 | return 0; | |
63502b8d | 837 | |
539e44d2 | 838 | return 1; |
63502b8d SS |
839 | } |
840 | ||
cb646e2b RC |
841 | static void decode_rxts(struct dp83640_private *dp83640, |
842 | struct phy_rxts *phy_rxts) | |
843 | { | |
844 | struct rxts *rxts; | |
63502b8d SS |
845 | struct skb_shared_hwtstamps *shhwtstamps = NULL; |
846 | struct sk_buff *skb; | |
cb646e2b RC |
847 | unsigned long flags; |
848 | ||
849 | spin_lock_irqsave(&dp83640->rx_lock, flags); | |
850 | ||
851 | prune_rx_ts(dp83640); | |
852 | ||
853 | if (list_empty(&dp83640->rxpool)) { | |
8d242488 | 854 | pr_debug("rx timestamp pool is empty\n"); |
cb646e2b RC |
855 | goto out; |
856 | } | |
857 | rxts = list_first_entry(&dp83640->rxpool, struct rxts, list); | |
858 | list_del_init(&rxts->list); | |
859 | phy2rxts(phy_rxts, rxts); | |
63502b8d | 860 | |
adbe088f | 861 | spin_lock(&dp83640->rx_queue.lock); |
63502b8d SS |
862 | skb_queue_walk(&dp83640->rx_queue, skb) { |
863 | struct dp83640_skb_info *skb_info; | |
864 | ||
865 | skb_info = (struct dp83640_skb_info *)skb->cb; | |
866 | if (match(skb, skb_info->ptp_type, rxts)) { | |
867 | __skb_unlink(skb, &dp83640->rx_queue); | |
868 | shhwtstamps = skb_hwtstamps(skb); | |
869 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
870 | shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); | |
871 | netif_rx_ni(skb); | |
872 | list_add(&rxts->list, &dp83640->rxpool); | |
873 | break; | |
874 | } | |
875 | } | |
adbe088f | 876 | spin_unlock(&dp83640->rx_queue.lock); |
63502b8d SS |
877 | |
878 | if (!shhwtstamps) | |
879 | list_add_tail(&rxts->list, &dp83640->rxts); | |
cb646e2b RC |
880 | out: |
881 | spin_unlock_irqrestore(&dp83640->rx_lock, flags); | |
882 | } | |
883 | ||
884 | static void decode_txts(struct dp83640_private *dp83640, | |
885 | struct phy_txts *phy_txts) | |
886 | { | |
887 | struct skb_shared_hwtstamps shhwtstamps; | |
888 | struct sk_buff *skb; | |
889 | u64 ns; | |
890 | ||
891 | /* We must already have the skb that triggered this. */ | |
892 | ||
893 | skb = skb_dequeue(&dp83640->tx_queue); | |
894 | ||
895 | if (!skb) { | |
8d242488 | 896 | pr_debug("have timestamp but tx_queue empty\n"); |
cb646e2b RC |
897 | return; |
898 | } | |
899 | ns = phy2txts(phy_txts); | |
900 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
901 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | |
902 | skb_complete_tx_timestamp(skb, &shhwtstamps); | |
903 | } | |
904 | ||
905 | static void decode_status_frame(struct dp83640_private *dp83640, | |
906 | struct sk_buff *skb) | |
907 | { | |
908 | struct phy_rxts *phy_rxts; | |
909 | struct phy_txts *phy_txts; | |
910 | u8 *ptr; | |
911 | int len, size; | |
912 | u16 ests, type; | |
913 | ||
914 | ptr = skb->data + 2; | |
915 | ||
916 | for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) { | |
917 | ||
918 | type = *(u16 *)ptr; | |
919 | ests = type & 0x0fff; | |
920 | type = type & 0xf000; | |
921 | len -= sizeof(type); | |
922 | ptr += sizeof(type); | |
923 | ||
924 | if (PSF_RX == type && len >= sizeof(*phy_rxts)) { | |
925 | ||
926 | phy_rxts = (struct phy_rxts *) ptr; | |
927 | decode_rxts(dp83640, phy_rxts); | |
928 | size = sizeof(*phy_rxts); | |
929 | ||
930 | } else if (PSF_TX == type && len >= sizeof(*phy_txts)) { | |
931 | ||
932 | phy_txts = (struct phy_txts *) ptr; | |
933 | decode_txts(dp83640, phy_txts); | |
934 | size = sizeof(*phy_txts); | |
935 | ||
13322f2e | 936 | } else if (PSF_EVNT == type) { |
cb646e2b | 937 | |
13322f2e | 938 | size = decode_evnt(dp83640, ptr, len, ests); |
cb646e2b RC |
939 | |
940 | } else { | |
941 | size = 0; | |
942 | break; | |
943 | } | |
944 | ptr += size; | |
945 | } | |
946 | } | |
947 | ||
dccaa9e0 RC |
948 | static int is_sync(struct sk_buff *skb, int type) |
949 | { | |
950 | u8 *data = skb->data, *msgtype; | |
951 | unsigned int offset = 0; | |
952 | ||
ae5c6c6d SS |
953 | if (type & PTP_CLASS_VLAN) |
954 | offset += VLAN_HLEN; | |
955 | ||
956 | switch (type & PTP_CLASS_PMASK) { | |
957 | case PTP_CLASS_IPV4: | |
cca04b28 | 958 | offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN; |
dccaa9e0 | 959 | break; |
ae5c6c6d SS |
960 | case PTP_CLASS_IPV6: |
961 | offset += ETH_HLEN + IP6_HLEN + UDP_HLEN; | |
dccaa9e0 | 962 | break; |
ae5c6c6d SS |
963 | case PTP_CLASS_L2: |
964 | offset += ETH_HLEN; | |
dccaa9e0 RC |
965 | break; |
966 | default: | |
967 | return 0; | |
968 | } | |
969 | ||
970 | if (type & PTP_CLASS_V1) | |
971 | offset += OFF_PTP_CONTROL; | |
972 | ||
973 | if (skb->len < offset + 1) | |
974 | return 0; | |
975 | ||
976 | msgtype = data + offset; | |
977 | ||
978 | return (*msgtype & 0xf) == 0; | |
979 | } | |
980 | ||
cb646e2b RC |
981 | static void dp83640_free_clocks(void) |
982 | { | |
983 | struct dp83640_clock *clock; | |
984 | struct list_head *this, *next; | |
985 | ||
986 | mutex_lock(&phyter_clocks_lock); | |
987 | ||
988 | list_for_each_safe(this, next, &phyter_clocks) { | |
989 | clock = list_entry(this, struct dp83640_clock, list); | |
990 | if (!list_empty(&clock->phylist)) { | |
8d242488 | 991 | pr_warn("phy list non-empty while unloading\n"); |
cb646e2b RC |
992 | BUG(); |
993 | } | |
994 | list_del(&clock->list); | |
995 | mutex_destroy(&clock->extreg_lock); | |
996 | mutex_destroy(&clock->clock_lock); | |
997 | put_device(&clock->bus->dev); | |
86dd3612 | 998 | kfree(clock->caps.pin_config); |
cb646e2b RC |
999 | kfree(clock); |
1000 | } | |
1001 | ||
1002 | mutex_unlock(&phyter_clocks_lock); | |
1003 | } | |
1004 | ||
1005 | static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus) | |
1006 | { | |
1007 | INIT_LIST_HEAD(&clock->list); | |
1008 | clock->bus = bus; | |
1009 | mutex_init(&clock->extreg_lock); | |
1010 | mutex_init(&clock->clock_lock); | |
1011 | INIT_LIST_HEAD(&clock->phylist); | |
1012 | clock->caps.owner = THIS_MODULE; | |
1013 | sprintf(clock->caps.name, "dp83640 timer"); | |
1014 | clock->caps.max_adj = 1953124; | |
1015 | clock->caps.n_alarm = 0; | |
1016 | clock->caps.n_ext_ts = N_EXT_TS; | |
ad01577a | 1017 | clock->caps.n_per_out = N_PER_OUT; |
86dd3612 | 1018 | clock->caps.n_pins = DP83640_N_PINS; |
cb646e2b RC |
1019 | clock->caps.pps = 0; |
1020 | clock->caps.adjfreq = ptp_dp83640_adjfreq; | |
1021 | clock->caps.adjtime = ptp_dp83640_adjtime; | |
41c2c18f RC |
1022 | clock->caps.gettime64 = ptp_dp83640_gettime; |
1023 | clock->caps.settime64 = ptp_dp83640_settime; | |
cb646e2b | 1024 | clock->caps.enable = ptp_dp83640_enable; |
86dd3612 RC |
1025 | clock->caps.verify = ptp_dp83640_verify; |
1026 | /* | |
1027 | * Convert the module param defaults into a dynamic pin configuration. | |
1028 | */ | |
1029 | dp83640_gpio_defaults(clock->caps.pin_config); | |
cb646e2b RC |
1030 | /* |
1031 | * Get a reference to this bus instance. | |
1032 | */ | |
1033 | get_device(&bus->dev); | |
1034 | } | |
1035 | ||
1036 | static int choose_this_phy(struct dp83640_clock *clock, | |
1037 | struct phy_device *phydev) | |
1038 | { | |
1039 | if (chosen_phy == -1 && !clock->chosen) | |
1040 | return 1; | |
1041 | ||
1042 | if (chosen_phy == phydev->addr) | |
1043 | return 1; | |
1044 | ||
1045 | return 0; | |
1046 | } | |
1047 | ||
1048 | static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock) | |
1049 | { | |
1050 | if (clock) | |
1051 | mutex_lock(&clock->clock_lock); | |
1052 | return clock; | |
1053 | } | |
1054 | ||
1055 | /* | |
1056 | * Look up and lock a clock by bus instance. | |
1057 | * If there is no clock for this bus, then create it first. | |
1058 | */ | |
1059 | static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus) | |
1060 | { | |
1061 | struct dp83640_clock *clock = NULL, *tmp; | |
1062 | struct list_head *this; | |
1063 | ||
1064 | mutex_lock(&phyter_clocks_lock); | |
1065 | ||
1066 | list_for_each(this, &phyter_clocks) { | |
1067 | tmp = list_entry(this, struct dp83640_clock, list); | |
1068 | if (tmp->bus == bus) { | |
1069 | clock = tmp; | |
1070 | break; | |
1071 | } | |
1072 | } | |
1073 | if (clock) | |
1074 | goto out; | |
1075 | ||
1076 | clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL); | |
1077 | if (!clock) | |
1078 | goto out; | |
1079 | ||
86dd3612 RC |
1080 | clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) * |
1081 | DP83640_N_PINS, GFP_KERNEL); | |
1082 | if (!clock->caps.pin_config) { | |
1083 | kfree(clock); | |
1084 | clock = NULL; | |
1085 | goto out; | |
1086 | } | |
cb646e2b RC |
1087 | dp83640_clock_init(clock, bus); |
1088 | list_add_tail(&phyter_clocks, &clock->list); | |
1089 | out: | |
1090 | mutex_unlock(&phyter_clocks_lock); | |
1091 | ||
1092 | return dp83640_clock_get(clock); | |
1093 | } | |
1094 | ||
1095 | static void dp83640_clock_put(struct dp83640_clock *clock) | |
1096 | { | |
1097 | mutex_unlock(&clock->clock_lock); | |
1098 | } | |
1099 | ||
1100 | static int dp83640_probe(struct phy_device *phydev) | |
1101 | { | |
1102 | struct dp83640_clock *clock; | |
1103 | struct dp83640_private *dp83640; | |
1104 | int err = -ENOMEM, i; | |
1105 | ||
1106 | if (phydev->addr == BROADCAST_ADDR) | |
1107 | return 0; | |
1108 | ||
1109 | clock = dp83640_clock_get_bus(phydev->bus); | |
1110 | if (!clock) | |
1111 | goto no_clock; | |
1112 | ||
1113 | dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL); | |
1114 | if (!dp83640) | |
1115 | goto no_memory; | |
1116 | ||
1117 | dp83640->phydev = phydev; | |
1118 | INIT_WORK(&dp83640->ts_work, rx_timestamp_work); | |
1119 | ||
1120 | INIT_LIST_HEAD(&dp83640->rxts); | |
1121 | INIT_LIST_HEAD(&dp83640->rxpool); | |
1122 | for (i = 0; i < MAX_RXTS; i++) | |
1123 | list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool); | |
1124 | ||
1125 | phydev->priv = dp83640; | |
1126 | ||
1127 | spin_lock_init(&dp83640->rx_lock); | |
1128 | skb_queue_head_init(&dp83640->rx_queue); | |
1129 | skb_queue_head_init(&dp83640->tx_queue); | |
1130 | ||
1131 | dp83640->clock = clock; | |
1132 | ||
1133 | if (choose_this_phy(clock, phydev)) { | |
1134 | clock->chosen = dp83640; | |
1ef76158 | 1135 | clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev); |
cb646e2b RC |
1136 | if (IS_ERR(clock->ptp_clock)) { |
1137 | err = PTR_ERR(clock->ptp_clock); | |
1138 | goto no_register; | |
1139 | } | |
1140 | } else | |
1141 | list_add_tail(&dp83640->list, &clock->phylist); | |
1142 | ||
cb646e2b RC |
1143 | dp83640_clock_put(clock); |
1144 | return 0; | |
1145 | ||
1146 | no_register: | |
1147 | clock->chosen = NULL; | |
1148 | kfree(dp83640); | |
1149 | no_memory: | |
1150 | dp83640_clock_put(clock); | |
1151 | no_clock: | |
1152 | return err; | |
1153 | } | |
1154 | ||
1155 | static void dp83640_remove(struct phy_device *phydev) | |
1156 | { | |
1157 | struct dp83640_clock *clock; | |
1158 | struct list_head *this, *next; | |
1159 | struct dp83640_private *tmp, *dp83640 = phydev->priv; | |
1160 | ||
1161 | if (phydev->addr == BROADCAST_ADDR) | |
1162 | return; | |
1163 | ||
1164 | enable_status_frames(phydev, false); | |
1165 | cancel_work_sync(&dp83640->ts_work); | |
1166 | ||
db91b724 AD |
1167 | skb_queue_purge(&dp83640->rx_queue); |
1168 | skb_queue_purge(&dp83640->tx_queue); | |
8b3408f8 | 1169 | |
cb646e2b RC |
1170 | clock = dp83640_clock_get(dp83640->clock); |
1171 | ||
1172 | if (dp83640 == clock->chosen) { | |
1173 | ptp_clock_unregister(clock->ptp_clock); | |
1174 | clock->chosen = NULL; | |
1175 | } else { | |
1176 | list_for_each_safe(this, next, &clock->phylist) { | |
1177 | tmp = list_entry(this, struct dp83640_private, list); | |
1178 | if (tmp == dp83640) { | |
1179 | list_del_init(&tmp->list); | |
1180 | break; | |
1181 | } | |
1182 | } | |
1183 | } | |
1184 | ||
1185 | dp83640_clock_put(clock); | |
1186 | kfree(dp83640); | |
1187 | } | |
1188 | ||
62ad9684 SS |
1189 | static int dp83640_config_init(struct phy_device *phydev) |
1190 | { | |
602b1099 SS |
1191 | struct dp83640_private *dp83640 = phydev->priv; |
1192 | struct dp83640_clock *clock = dp83640->clock; | |
1193 | ||
1194 | if (clock->chosen && !list_empty(&clock->phylist)) | |
1195 | recalibrate(clock); | |
a935865c RC |
1196 | else { |
1197 | mutex_lock(&clock->extreg_lock); | |
602b1099 | 1198 | enable_broadcast(phydev, clock->page, 1); |
a935865c RC |
1199 | mutex_unlock(&clock->extreg_lock); |
1200 | } | |
602b1099 | 1201 | |
62ad9684 | 1202 | enable_status_frames(phydev, true); |
a935865c RC |
1203 | |
1204 | mutex_lock(&clock->extreg_lock); | |
62ad9684 | 1205 | ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE); |
a935865c RC |
1206 | mutex_unlock(&clock->extreg_lock); |
1207 | ||
62ad9684 SS |
1208 | return 0; |
1209 | } | |
1210 | ||
1642182e SG |
1211 | static int dp83640_ack_interrupt(struct phy_device *phydev) |
1212 | { | |
1213 | int err = phy_read(phydev, MII_DP83640_MISR); | |
1214 | ||
1215 | if (err < 0) | |
1216 | return err; | |
1217 | ||
1218 | return 0; | |
1219 | } | |
1220 | ||
1221 | static int dp83640_config_intr(struct phy_device *phydev) | |
1222 | { | |
1223 | int micr; | |
1224 | int misr; | |
1225 | int err; | |
1226 | ||
1227 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { | |
1228 | misr = phy_read(phydev, MII_DP83640_MISR); | |
1229 | if (misr < 0) | |
1230 | return misr; | |
1231 | misr |= | |
1232 | (MII_DP83640_MISR_ANC_INT_EN | | |
1233 | MII_DP83640_MISR_DUP_INT_EN | | |
1234 | MII_DP83640_MISR_SPD_INT_EN | | |
1235 | MII_DP83640_MISR_LINK_INT_EN); | |
1236 | err = phy_write(phydev, MII_DP83640_MISR, misr); | |
1237 | if (err < 0) | |
1238 | return err; | |
1239 | ||
1240 | micr = phy_read(phydev, MII_DP83640_MICR); | |
1241 | if (micr < 0) | |
1242 | return micr; | |
1243 | micr |= | |
1244 | (MII_DP83640_MICR_OE | | |
1245 | MII_DP83640_MICR_IE); | |
1246 | return phy_write(phydev, MII_DP83640_MICR, micr); | |
1247 | } else { | |
1248 | micr = phy_read(phydev, MII_DP83640_MICR); | |
1249 | if (micr < 0) | |
1250 | return micr; | |
1251 | micr &= | |
1252 | ~(MII_DP83640_MICR_OE | | |
1253 | MII_DP83640_MICR_IE); | |
1254 | err = phy_write(phydev, MII_DP83640_MICR, micr); | |
1255 | if (err < 0) | |
1256 | return err; | |
1257 | ||
1258 | misr = phy_read(phydev, MII_DP83640_MISR); | |
1259 | if (misr < 0) | |
1260 | return misr; | |
1261 | misr &= | |
1262 | ~(MII_DP83640_MISR_ANC_INT_EN | | |
1263 | MII_DP83640_MISR_DUP_INT_EN | | |
1264 | MII_DP83640_MISR_SPD_INT_EN | | |
1265 | MII_DP83640_MISR_LINK_INT_EN); | |
1266 | return phy_write(phydev, MII_DP83640_MISR, misr); | |
1267 | } | |
1268 | } | |
1269 | ||
cb646e2b RC |
1270 | static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr) |
1271 | { | |
1272 | struct dp83640_private *dp83640 = phydev->priv; | |
1273 | struct hwtstamp_config cfg; | |
1274 | u16 txcfg0, rxcfg0; | |
1275 | ||
1276 | if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) | |
1277 | return -EFAULT; | |
1278 | ||
1279 | if (cfg.flags) /* reserved for future extensions */ | |
1280 | return -EINVAL; | |
1281 | ||
dccaa9e0 | 1282 | if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC) |
cb646e2b | 1283 | return -ERANGE; |
dccaa9e0 RC |
1284 | |
1285 | dp83640->hwts_tx_en = cfg.tx_type; | |
cb646e2b RC |
1286 | |
1287 | switch (cfg.rx_filter) { | |
1288 | case HWTSTAMP_FILTER_NONE: | |
1289 | dp83640->hwts_rx_en = 0; | |
1290 | dp83640->layer = 0; | |
1291 | dp83640->version = 0; | |
1292 | break; | |
1293 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
1294 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
1295 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
1296 | dp83640->hwts_rx_en = 1; | |
1297 | dp83640->layer = LAYER4; | |
1298 | dp83640->version = 1; | |
1299 | break; | |
1300 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
1301 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
1302 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
1303 | dp83640->hwts_rx_en = 1; | |
1304 | dp83640->layer = LAYER4; | |
1305 | dp83640->version = 2; | |
1306 | break; | |
1307 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1308 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
1309 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
1310 | dp83640->hwts_rx_en = 1; | |
1311 | dp83640->layer = LAYER2; | |
1312 | dp83640->version = 2; | |
1313 | break; | |
1314 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
1315 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
1316 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
1317 | dp83640->hwts_rx_en = 1; | |
1318 | dp83640->layer = LAYER4|LAYER2; | |
1319 | dp83640->version = 2; | |
1320 | break; | |
1321 | default: | |
1322 | return -ERANGE; | |
1323 | } | |
1324 | ||
1325 | txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; | |
1326 | rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT; | |
1327 | ||
1328 | if (dp83640->layer & LAYER2) { | |
1329 | txcfg0 |= TX_L2_EN; | |
1330 | rxcfg0 |= RX_L2_EN; | |
1331 | } | |
1332 | if (dp83640->layer & LAYER4) { | |
1333 | txcfg0 |= TX_IPV6_EN | TX_IPV4_EN; | |
1334 | rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN; | |
1335 | } | |
1336 | ||
1337 | if (dp83640->hwts_tx_en) | |
1338 | txcfg0 |= TX_TS_EN; | |
1339 | ||
dccaa9e0 RC |
1340 | if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC) |
1341 | txcfg0 |= SYNC_1STEP | CHK_1STEP; | |
1342 | ||
cb646e2b RC |
1343 | if (dp83640->hwts_rx_en) |
1344 | rxcfg0 |= RX_TS_EN; | |
1345 | ||
1346 | mutex_lock(&dp83640->clock->extreg_lock); | |
1347 | ||
cb646e2b RC |
1348 | ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0); |
1349 | ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0); | |
1350 | ||
1351 | mutex_unlock(&dp83640->clock->extreg_lock); | |
1352 | ||
1353 | return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; | |
1354 | } | |
1355 | ||
1356 | static void rx_timestamp_work(struct work_struct *work) | |
1357 | { | |
1358 | struct dp83640_private *dp83640 = | |
1359 | container_of(work, struct dp83640_private, ts_work); | |
cb646e2b | 1360 | struct sk_buff *skb; |
cb646e2b | 1361 | |
63502b8d SS |
1362 | /* Deliver expired packets. */ |
1363 | while ((skb = skb_dequeue(&dp83640->rx_queue))) { | |
1364 | struct dp83640_skb_info *skb_info; | |
1365 | ||
1366 | skb_info = (struct dp83640_skb_info *)skb->cb; | |
1367 | if (!time_after(jiffies, skb_info->tmo)) { | |
1368 | skb_queue_head(&dp83640->rx_queue, skb); | |
1369 | break; | |
cb646e2b | 1370 | } |
63502b8d | 1371 | |
72092cc4 | 1372 | netif_rx_ni(skb); |
cb646e2b RC |
1373 | } |
1374 | ||
63502b8d SS |
1375 | if (!skb_queue_empty(&dp83640->rx_queue)) |
1376 | schedule_work(&dp83640->ts_work); | |
cb646e2b RC |
1377 | } |
1378 | ||
1379 | static bool dp83640_rxtstamp(struct phy_device *phydev, | |
1380 | struct sk_buff *skb, int type) | |
1381 | { | |
1382 | struct dp83640_private *dp83640 = phydev->priv; | |
63502b8d SS |
1383 | struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb; |
1384 | struct list_head *this, *next; | |
1385 | struct rxts *rxts; | |
1386 | struct skb_shared_hwtstamps *shhwtstamps = NULL; | |
1387 | unsigned long flags; | |
cb646e2b | 1388 | |
cb646e2b RC |
1389 | if (is_status_frame(skb, type)) { |
1390 | decode_status_frame(dp83640, skb); | |
ae6e86b7 RC |
1391 | kfree_skb(skb); |
1392 | return true; | |
cb646e2b RC |
1393 | } |
1394 | ||
a12f78c5 SS |
1395 | if (!dp83640->hwts_rx_en) |
1396 | return false; | |
1397 | ||
63502b8d SS |
1398 | spin_lock_irqsave(&dp83640->rx_lock, flags); |
1399 | list_for_each_safe(this, next, &dp83640->rxts) { | |
1400 | rxts = list_entry(this, struct rxts, list); | |
1401 | if (match(skb, type, rxts)) { | |
1402 | shhwtstamps = skb_hwtstamps(skb); | |
1403 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
1404 | shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns); | |
1405 | netif_rx_ni(skb); | |
1406 | list_del_init(&rxts->list); | |
1407 | list_add(&rxts->list, &dp83640->rxpool); | |
1408 | break; | |
1409 | } | |
1410 | } | |
1411 | spin_unlock_irqrestore(&dp83640->rx_lock, flags); | |
1412 | ||
1413 | if (!shhwtstamps) { | |
1414 | skb_info->ptp_type = type; | |
1415 | skb_info->tmo = jiffies + 2; | |
1416 | skb_queue_tail(&dp83640->rx_queue, skb); | |
1417 | schedule_work(&dp83640->ts_work); | |
1418 | } | |
cb646e2b RC |
1419 | |
1420 | return true; | |
1421 | } | |
1422 | ||
1423 | static void dp83640_txtstamp(struct phy_device *phydev, | |
1424 | struct sk_buff *skb, int type) | |
1425 | { | |
1426 | struct dp83640_private *dp83640 = phydev->priv; | |
1427 | ||
dccaa9e0 RC |
1428 | switch (dp83640->hwts_tx_en) { |
1429 | ||
1430 | case HWTSTAMP_TX_ONESTEP_SYNC: | |
1431 | if (is_sync(skb, type)) { | |
62bccb8c | 1432 | kfree_skb(skb); |
dccaa9e0 RC |
1433 | return; |
1434 | } | |
1435 | /* fall through */ | |
1436 | case HWTSTAMP_TX_ON: | |
e2e2f51d | 1437 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
dccaa9e0 | 1438 | skb_queue_tail(&dp83640->tx_queue, skb); |
dccaa9e0 RC |
1439 | break; |
1440 | ||
1441 | case HWTSTAMP_TX_OFF: | |
1442 | default: | |
62bccb8c | 1443 | kfree_skb(skb); |
dccaa9e0 | 1444 | break; |
cb646e2b | 1445 | } |
cb646e2b RC |
1446 | } |
1447 | ||
7dff3499 RC |
1448 | static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info) |
1449 | { | |
1450 | struct dp83640_private *dp83640 = dev->priv; | |
1451 | ||
1452 | info->so_timestamping = | |
1453 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1454 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1455 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1456 | info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock); | |
1457 | info->tx_types = | |
1458 | (1 << HWTSTAMP_TX_OFF) | | |
1459 | (1 << HWTSTAMP_TX_ON) | | |
1460 | (1 << HWTSTAMP_TX_ONESTEP_SYNC); | |
1461 | info->rx_filters = | |
1462 | (1 << HWTSTAMP_FILTER_NONE) | | |
1463 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | | |
7dff3499 | 1464 | (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | |
7dff3499 | 1465 | (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | |
11b1544b | 1466 | (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); |
7dff3499 RC |
1467 | return 0; |
1468 | } | |
1469 | ||
cb646e2b RC |
1470 | static struct phy_driver dp83640_driver = { |
1471 | .phy_id = DP83640_PHY_ID, | |
1472 | .phy_id_mask = 0xfffffff0, | |
1473 | .name = "NatSemi DP83640", | |
1474 | .features = PHY_BASIC_FEATURES, | |
1642182e | 1475 | .flags = PHY_HAS_INTERRUPT, |
cb646e2b RC |
1476 | .probe = dp83640_probe, |
1477 | .remove = dp83640_remove, | |
62ad9684 | 1478 | .config_init = dp83640_config_init, |
cb646e2b RC |
1479 | .config_aneg = genphy_config_aneg, |
1480 | .read_status = genphy_read_status, | |
1642182e SG |
1481 | .ack_interrupt = dp83640_ack_interrupt, |
1482 | .config_intr = dp83640_config_intr, | |
7dff3499 | 1483 | .ts_info = dp83640_ts_info, |
cb646e2b RC |
1484 | .hwtstamp = dp83640_hwtstamp, |
1485 | .rxtstamp = dp83640_rxtstamp, | |
1486 | .txtstamp = dp83640_txtstamp, | |
1487 | .driver = {.owner = THIS_MODULE,} | |
1488 | }; | |
1489 | ||
1490 | static int __init dp83640_init(void) | |
1491 | { | |
1492 | return phy_driver_register(&dp83640_driver); | |
1493 | } | |
1494 | ||
1495 | static void __exit dp83640_exit(void) | |
1496 | { | |
1497 | dp83640_free_clocks(); | |
1498 | phy_driver_unregister(&dp83640_driver); | |
1499 | } | |
1500 | ||
1501 | MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver"); | |
fbf4b934 | 1502 | MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>"); |
cb646e2b RC |
1503 | MODULE_LICENSE("GPL"); |
1504 | ||
1505 | module_init(dp83640_init); | |
1506 | module_exit(dp83640_exit); | |
1507 | ||
86ff9baa | 1508 | static struct mdio_device_id __maybe_unused dp83640_tbl[] = { |
cb646e2b RC |
1509 | { DP83640_PHY_ID, 0xfffffff0 }, |
1510 | { } | |
1511 | }; | |
1512 | ||
1513 | MODULE_DEVICE_TABLE(mdio, dp83640_tbl); |