[mirror_ubuntu-jammy-kernel.git] / drivers / net / phy / dp83867.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for the Texas Instruments DP83867 PHY
 *
 * Copyright (C) 2015 Texas Instruments Inc.
 */

#include <linux/ethtool.h>
#include <linux/kernel.h>
#include <linux/mii.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>
#include <linux/delay.h>

#include <dt-bindings/net/ti-dp83867.h>

#define DP83867_PHY_ID		0x2000a231
#define DP83867_DEVADDR		0x1f

#define MII_DP83867_PHYCTRL	0x10
#define MII_DP83867_MICR	0x12
#define MII_DP83867_ISR		0x13
#define DP83867_CTRL		0x1f
#define DP83867_CFG3		0x1e

/* Extended Registers */
#define DP83867_CFG4            0x0031
#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)

#define DP83867_RGMIICTL	0x0032
#define DP83867_STRAP_STS1	0x006E
#define DP83867_RGMIIDCTL	0x0086
#define DP83867_IO_MUX_CFG	0x0170
#define DP83867_10M_SGMII_CFG   0x016F
#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)

#define DP83867_SW_RESET	BIT(15)
#define DP83867_SW_RESTART	BIT(14)

/* MICR Interrupt bits */
#define MII_DP83867_MICR_AN_ERR_INT_EN		BIT(15)
#define MII_DP83867_MICR_SPEED_CHNG_INT_EN	BIT(14)
#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN	BIT(13)
#define MII_DP83867_MICR_PAGE_RXD_INT_EN	BIT(12)
#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN	BIT(11)
#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN	BIT(10)
#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN	BIT(8)
#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN	BIT(4)
#define MII_DP83867_MICR_WOL_INT_EN		BIT(3)
#define MII_DP83867_MICR_XGMII_ERR_INT_EN	BIT(2)
#define MII_DP83867_MICR_POL_CHNG_INT_EN	BIT(1)
#define MII_DP83867_MICR_JABBER_INT_EN		BIT(0)

/* RGMIICTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_EN		BIT(1)
#define DP83867_RGMII_RX_CLK_DELAY_EN		BIT(0)

/* STRAP_STS1 bits */
#define DP83867_STRAP_STS1_RESERVED		BIT(11)

/* PHY CTRL bits */
#define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
#define DP83867_PHYCR_FIFO_DEPTH_MASK		(3 << 14)
#define DP83867_PHYCR_RESERVED_MASK		BIT(11)

/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_SHIFT	4

/* IO_MUX_CFG bits */
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL	0x1f

#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX	0x0
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN	0x1f
#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK	(0x1f << 8)
#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT	8

/* CFG4 bits */
#define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)

enum {
	DP83867_PORT_MIRROING_KEEP,
	DP83867_PORT_MIRROING_EN,
	DP83867_PORT_MIRROING_DIS,
};

struct dp83867_private {
	int rx_id_delay;
	int tx_id_delay;
	int fifo_depth;
	int io_impedance;
	int port_mirroring;
	bool rxctrl_strap_quirk;
	int clk_output_sel;
};

static int dp83867_ack_interrupt(struct phy_device *phydev)
{
	int err = phy_read(phydev, MII_DP83867_ISR);

	if (err < 0)
		return err;

	return 0;
}

static int dp83867_config_intr(struct phy_device *phydev)
{
	int micr_status;

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
		micr_status = phy_read(phydev, MII_DP83867_MICR);
		if (micr_status < 0)
			return micr_status;

		micr_status |=
			(MII_DP83867_MICR_AN_ERR_INT_EN |
			MII_DP83867_MICR_SPEED_CHNG_INT_EN |
			MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
			MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
			MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
			MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);

		return phy_write(phydev, MII_DP83867_MICR, micr_status);
	}

	micr_status = 0x0;
	return phy_write(phydev, MII_DP83867_MICR, micr_status);
}

static int dp83867_config_port_mirroring(struct phy_device *phydev)
{
	struct dp83867_private *dp83867 =
		(struct dp83867_private *)phydev->priv;

	if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
		phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
				 DP83867_CFG4_PORT_MIRROR_EN);
	else
		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
				   DP83867_CFG4_PORT_MIRROR_EN);
	return 0;
}

#ifdef CONFIG_OF_MDIO
static int dp83867_of_init(struct phy_device *phydev)
{
	struct dp83867_private *dp83867 = phydev->priv;
	struct device *dev = &phydev->mdio.dev;
	struct device_node *of_node = dev->of_node;
	int ret;

	if (!of_node)
		return -ENODEV;

	dp83867->io_impedance = -EINVAL;

	/* Optional configuration */
	ret = of_property_read_u32(of_node, "ti,clk-output-sel",
				   &dp83867->clk_output_sel);
	if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)
		/* Keep the default value if ti,clk-output-sel is not set
		 * or too high
		 */
		dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;

	if (of_property_read_bool(of_node, "ti,max-output-impedance"))
		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
	else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;

	dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
					"ti,dp83867-rxctrl-strap-quirk");

	ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
				   &dp83867->rx_id_delay);
	if (ret &&
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
	     phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
		return ret;

	ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
				   &dp83867->tx_id_delay);
	if (ret &&
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
	     phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
		return ret;

	if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
		dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;

	if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
		dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;

	return of_property_read_u32(of_node, "ti,fifo-depth",
				   &dp83867->fifo_depth);
}
#else
static int dp83867_of_init(struct phy_device *phydev)
{
	return 0;
}
#endif /* CONFIG_OF_MDIO */

static int dp83867_config_init(struct phy_device *phydev)
{
	struct dp83867_private *dp83867;
	int ret, val, bs;
	u16 delay;

	if (!phydev->priv) {
		dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
				       GFP_KERNEL);
		if (!dp83867)
			return -ENOMEM;

		phydev->priv = dp83867;
		ret = dp83867_of_init(phydev);
		if (ret)
			return ret;
	} else {
		dp83867 = (struct dp83867_private *)phydev->priv;
	}

	/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
	if (dp83867->rxctrl_strap_quirk)
		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
				   BIT(7));

	if (phy_interface_is_rgmii(phydev)) {
		val = phy_read(phydev, MII_DP83867_PHYCTRL);
		if (val < 0)
			return val;
		val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
		val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);

		/* The code below checks if "port mirroring" N/A MODE4 has been
		 * enabled during power on bootstrap.
		 *
		 * Such N/A mode enabled by mistake can put PHY IC in some
		 * internal testing mode and disable RGMII transmission.
		 *
		 * In this particular case one needs to check STRAP_STS1
		 * register's bit 11 (marked as RESERVED).
		 */

		bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
		if (bs & DP83867_STRAP_STS1_RESERVED)
			val &= ~DP83867_PHYCR_RESERVED_MASK;

		ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
		if (ret)
			return ret;

		/* Set up RGMII delays */
		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
			val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
			val |= DP83867_RGMII_TX_CLK_DELAY_EN;

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
			val |= DP83867_RGMII_RX_CLK_DELAY_EN;

		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);

		delay = (dp83867->rx_id_delay |
			(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));

		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
			      delay);

		if (dp83867->io_impedance >= 0)
			phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
				       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
				       dp83867->io_impedance &
				       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
	}

	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
		/* For support SPEED_10 in SGMII mode
		 * DP83867_10M_SGMII_RATE_ADAPT bit
		 * has to be cleared by software. That
		 * does not affect SPEED_100 and
		 * SPEED_1000.
		 */
		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
				     DP83867_10M_SGMII_CFG,
				     DP83867_10M_SGMII_RATE_ADAPT_MASK,
				     0);
		if (ret)
			return ret;

		/* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
		 * are 01). That is not enough to finalize autoneg on some
		 * devices. Increase this timer duration to maximum 16ms.
		 */
		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
				     DP83867_CFG4,
				     DP83867_CFG4_SGMII_ANEG_MASK,
				     DP83867_CFG4_SGMII_ANEG_TIMER_16MS);

		if (ret)
			return ret;
	}

	/* Enable Interrupt output INT_OE in CFG3 register */
	if (phy_interrupt_is_valid(phydev)) {
		val = phy_read(phydev, DP83867_CFG3);
		val |= BIT(7);
		phy_write(phydev, DP83867_CFG3, val);
	}

	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
		dp83867_config_port_mirroring(phydev);

	/* Clock output selection if muxing property is set */
	if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK)
		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
			       DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,
			       dp83867->clk_output_sel <<
			       DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);

	return 0;
}

static int dp83867_phy_reset(struct phy_device *phydev)
{
	int err;

	err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
	if (err < 0)
		return err;

	usleep_range(10, 20);

	return 0;
}

static struct phy_driver dp83867_driver[] = {
	{
		.phy_id		= DP83867_PHY_ID,
		.phy_id_mask	= 0xfffffff0,
		.name		= "TI DP83867",
		/* PHY_GBIT_FEATURES */

		.config_init	= dp83867_config_init,
		.soft_reset	= dp83867_phy_reset,

		/* IRQ related */
		.ack_interrupt	= dp83867_ack_interrupt,
		.config_intr	= dp83867_config_intr,

		.suspend	= genphy_suspend,
		.resume		= genphy_resume,
	},
};
module_phy_driver(dp83867_driver);

static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
	{ DP83867_PHY_ID, 0xfffffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, dp83867_tbl);

MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
5f857575	1	// SPDX-License-Identifier: GPL-2.0
2a10154a DM	2	/*
	3	* Driver for the Texas Instruments DP83867 PHY
	4	*
	5	* Copyright (C) 2015 Texas Instruments Inc.
2a10154a DM	6	*/
	7
	8	#include <linux/ethtool.h>
	9	#include <linux/kernel.h>
	10	#include <linux/mii.h>
	11	#include <linux/module.h>
	12	#include <linux/of.h>
	13	#include <linux/phy.h>
72a7d452	14	#include <linux/delay.h>
2a10154a DM	15
	16	#include <dt-bindings/net/ti-dp83867.h>
	17
	18	#define DP83867_PHY_ID 0x2000a231
	19	#define DP83867_DEVADDR 0x1f
	20
	21	#define MII_DP83867_PHYCTRL 0x10
	22	#define MII_DP83867_MICR 0x12
	23	#define MII_DP83867_ISR 0x13
	24	#define DP83867_CTRL 0x1f
5ca7d1ca	25	#define DP83867_CFG3 0x1e
2a10154a DM	26
2a10154a DM	27	/* Extended Registers */
fc6d39c3	28	#define DP83867_CFG4 0x0031
1a97a477 MU	29	#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) \| BIT(6))
	30	#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
	31	#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
	32	#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
	33	#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
	34
2a10154a	35	#define DP83867_RGMIICTL 0x0032
ac6e058b	36	#define DP83867_STRAP_STS1 0x006E
2a10154a	37	#define DP83867_RGMIIDCTL 0x0086
ed838fe9	38	#define DP83867_IO_MUX_CFG 0x0170
333061b9 MU	39	#define DP83867_10M_SGMII_CFG 0x016F
333061b9 MU	40	#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
2a10154a DM	41
	42	#define DP83867_SW_RESET BIT(15)
	43	#define DP83867_SW_RESTART BIT(14)
	44
	45	/* MICR Interrupt bits */
	46	#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
	47	#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
	48	#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
	49	#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
	50	#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
	51	#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
	52	#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
	53	#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
	54	#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
	55	#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
	56	#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
	57	#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
	58
	59	/* RGMIICTL bits */
	60	#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
	61	#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
	62
ac6e058b LM	63	/* STRAP_STS1 bits */
	64	#define DP83867_STRAP_STS1_RESERVED BIT(11)
	65
2a10154a DM	66	/* PHY CTRL bits */
2a10154a DM	67	#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
b291c418	68	#define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
ac6e058b	69	#define DP83867_PHYCR_RESERVED_MASK BIT(11)
2a10154a DM	70
	71	/* RGMIIDCTL bits */
	72	#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
	73
ed838fe9 M	74	/* IO_MUX_CFG bits */
	75	#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
	76
	77	#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
	78	#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
9708fb63 WE	79	#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
9708fb63 WE	80	#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
ed838fe9	81
fc6d39c3 LM	82	/* CFG4 bits */
	83	#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
	84
	85	enum {
	86	DP83867_PORT_MIRROING_KEEP,
	87	DP83867_PORT_MIRROING_EN,
	88	DP83867_PORT_MIRROING_DIS,
	89	};
	90
2a10154a DM	91	struct dp83867_private {
	92	int rx_id_delay;
	93	int tx_id_delay;
	94	int fifo_depth;
ed838fe9	95	int io_impedance;
fc6d39c3	96	int port_mirroring;
37144476	97	bool rxctrl_strap_quirk;
9708fb63	98	int clk_output_sel;
2a10154a DM	99	};
	100
	101	static int dp83867_ack_interrupt(struct phy_device *phydev)
	102	{
	103	int err = phy_read(phydev, MII_DP83867_ISR);
	104
	105	if (err < 0)
	106	return err;
	107
	108	return 0;
	109	}
	110
	111	static int dp83867_config_intr(struct phy_device *phydev)
	112	{
	113	int micr_status;
	114
	115	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
	116	micr_status = phy_read(phydev, MII_DP83867_MICR);
	117	if (micr_status < 0)
	118	return micr_status;
	119
	120	micr_status \|=
	121	(MII_DP83867_MICR_AN_ERR_INT_EN \|
	122	MII_DP83867_MICR_SPEED_CHNG_INT_EN \|
5ca7d1ca GS	123	MII_DP83867_MICR_AUTONEG_COMP_INT_EN \|
5ca7d1ca GS	124	MII_DP83867_MICR_LINK_STS_CHNG_INT_EN \|
2a10154a DM	125	MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN \|
	126	MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
	127
	128	return phy_write(phydev, MII_DP83867_MICR, micr_status);
	129	}
	130
	131	micr_status = 0x0;
	132	return phy_write(phydev, MII_DP83867_MICR, micr_status);
	133	}
	134
fc6d39c3 LM	135	static int dp83867_config_port_mirroring(struct phy_device *phydev)
	136	{
	137	struct dp83867_private *dp83867 =
	138	(struct dp83867_private *)phydev->priv;
fc6d39c3 LM	139
fc6d39c3 LM	140	if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
b52c018d HK	141	phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
b52c018d HK	142	DP83867_CFG4_PORT_MIRROR_EN);
fc6d39c3	143	else
b52c018d HK	144	phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
b52c018d HK	145	DP83867_CFG4_PORT_MIRROR_EN);
fc6d39c3 LM	146	return 0;
	147	}
	148
2a10154a DM	149	#ifdef CONFIG_OF_MDIO
	150	static int dp83867_of_init(struct phy_device *phydev)
	151	{
	152	struct dp83867_private *dp83867 = phydev->priv;
e5a03bfd	153	struct device *dev = &phydev->mdio.dev;
2a10154a DM	154	struct device_node *of_node = dev->of_node;
	155	int ret;
	156
7bf9ae01	157	if (!of_node)
2a10154a DM	158	return -ENODEV;
2a10154a DM	159
ed838fe9 M	160	dp83867->io_impedance = -EINVAL;
	161
	162	/* Optional configuration */
9708fb63 WE	163	ret = of_property_read_u32(of_node, "ti,clk-output-sel",
	164	&dp83867->clk_output_sel);
	165	if (ret \|\| dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)
	166	/* Keep the default value if ti,clk-output-sel is not set
	167	* or too high
	168	*/
	169	dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
	170
ed838fe9 M	171	if (of_property_read_bool(of_node, "ti,max-output-impedance"))
	172	dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
	173	else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
	174	dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
	175
37144476 MK	176	dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
	177	"ti,dp83867-rxctrl-strap-quirk");
	178
ac7ba51c	179	ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
2a10154a	180	&dp83867->rx_id_delay);
34c55cf2 KM	181	if (ret &&
	182	(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID \|\|
	183	phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
2a10154a DM	184	return ret;
2a10154a DM	185
ac7ba51c	186	ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
2a10154a	187	&dp83867->tx_id_delay);
34c55cf2 KM	188	if (ret &&
	189	(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID \|\|
	190	phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
2a10154a DM	191	return ret;
2a10154a DM	192
fc6d39c3 LM	193	if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
	194	dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
	195
	196	if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
	197	dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
	198
9267135c	199	return of_property_read_u32(of_node, "ti,fifo-depth",
2a10154a	200	&dp83867->fifo_depth);
2a10154a DM	201	}
	202	#else
	203	static int dp83867_of_init(struct phy_device *phydev)
	204	{
	205	return 0;
	206	}
	207	#endif /* CONFIG_OF_MDIO */
	208
	209	static int dp83867_config_init(struct phy_device *phydev)
	210	{
	211	struct dp83867_private *dp83867;
ac6e058b	212	int ret, val, bs;
b291c418	213	u16 delay;
2a10154a DM	214
2a10154a DM	215	if (!phydev->priv) {
e5a03bfd	216	dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
2a10154a DM	217	GFP_KERNEL);
	218	if (!dp83867)
	219	return -ENOMEM;
	220
	221	phydev->priv = dp83867;
	222	ret = dp83867_of_init(phydev);
	223	if (ret)
	224	return ret;
	225	} else {
	226	dp83867 = (struct dp83867_private *)phydev->priv;
	227	}
	228
37144476	229	/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
b52c018d HK	230	if (dp83867->rxctrl_strap_quirk)
	231	phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
	232	BIT(7));
37144476	233
2a10154a	234	if (phy_interface_is_rgmii(phydev)) {
b291c418 SH	235	val = phy_read(phydev, MII_DP83867_PHYCTRL);
	236	if (val < 0)
	237	return val;
	238	val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
	239	val \|= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
ac6e058b LM	240
	241	/* The code below checks if "port mirroring" N/A MODE4 has been
	242	* enabled during power on bootstrap.
	243	*
	244	* Such N/A mode enabled by mistake can put PHY IC in some
	245	* internal testing mode and disable RGMII transmission.
	246	*
	247	* In this particular case one needs to check STRAP_STS1
	248	* register's bit 11 (marked as RESERVED).
	249	*/
	250
a6d99fcd	251	bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
ac6e058b LM	252	if (bs & DP83867_STRAP_STS1_RESERVED)
	253	val &= ~DP83867_PHYCR_RESERVED_MASK;
	254
b291c418	255	ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
2a10154a DM	256	if (ret)
2a10154a DM	257	return ret;
2a10154a	258
2b892649	259	/* Set up RGMII delays */
a6d99fcd	260	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
2a10154a DM	261
	262	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
	263	val \|= (DP83867_RGMII_TX_CLK_DELAY_EN \| DP83867_RGMII_RX_CLK_DELAY_EN);
	264
	265	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
	266	val \|= DP83867_RGMII_TX_CLK_DELAY_EN;
	267
	268	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
	269	val \|= DP83867_RGMII_RX_CLK_DELAY_EN;
	270
a6d99fcd	271	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
2a10154a DM	272
	273	delay = (dp83867->rx_id_delay \|
	274	(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
	275
a6d99fcd RK	276	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
a6d99fcd RK	277	delay);
ed838fe9	278
b52c018d HK	279	if (dp83867->io_impedance >= 0)
	280	phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
	281	DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
	282	dp83867->io_impedance &
	283	DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
2a10154a DM	284	}
2a10154a DM	285
333061b9 MU	286	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
	287	/* For support SPEED_10 in SGMII mode
	288	* DP83867_10M_SGMII_RATE_ADAPT bit
	289	* has to be cleared by software. That
	290	* does not affect SPEED_100 and
	291	* SPEED_1000.
	292	*/
	293	ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
	294	DP83867_10M_SGMII_CFG,
	295	DP83867_10M_SGMII_RATE_ADAPT_MASK,
	296	0);
	297	if (ret)
	298	return ret;
1a97a477 MU	299
	300	/* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
	301	* are 01). That is not enough to finalize autoneg on some
	302	* devices. Increase this timer duration to maximum 16ms.
	303	*/
	304	ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
	305	DP83867_CFG4,
	306	DP83867_CFG4_SGMII_ANEG_MASK,
	307	DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
	308
	309	if (ret)
	310	return ret;
333061b9 MU	311	}
333061b9 MU	312
5ca7d1ca GS	313	/* Enable Interrupt output INT_OE in CFG3 register */
	314	if (phy_interrupt_is_valid(phydev)) {
	315	val = phy_read(phydev, DP83867_CFG3);
	316	val \|= BIT(7);
	317	phy_write(phydev, DP83867_CFG3, val);
	318	}
	319
fc6d39c3 LM	320	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
	321	dp83867_config_port_mirroring(phydev);
	322
9708fb63	323	/* Clock output selection if muxing property is set */
b52c018d HK	324	if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK)
	325	phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
	326	DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,
	327	dp83867->clk_output_sel <<
	328	DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
9708fb63	329
2a10154a DM	330	return 0;
	331	}
	332
	333	static int dp83867_phy_reset(struct phy_device *phydev)
	334	{
	335	int err;
	336
	337	err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
	338	if (err < 0)
	339	return err;
	340
72a7d452 MU	341	usleep_range(10, 20);
72a7d452 MU	342
c8081fc3	343	return 0;
2a10154a DM	344	}
	345
	346	static struct phy_driver dp83867_driver[] = {
	347	{
	348	.phy_id = DP83867_PHY_ID,
	349	.phy_id_mask = 0xfffffff0,
	350	.name = "TI DP83867",
dcdecdcf	351	/* PHY_GBIT_FEATURES */
2a10154a DM	352
	353	.config_init = dp83867_config_init,
	354	.soft_reset = dp83867_phy_reset,
	355
	356	/* IRQ related */
	357	.ack_interrupt = dp83867_ack_interrupt,
	358	.config_intr = dp83867_config_intr,
	359
2a10154a DM	360	.suspend = genphy_suspend,
2a10154a DM	361	.resume = genphy_resume,
2a10154a DM	362	},
	363	};
	364	module_phy_driver(dp83867_driver);
	365
	366	static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
	367	{ DP83867_PHY_ID, 0xfffffff0 },
	368	{ }
	369	};
	370
	371	MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
	372
	373	MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
	374	MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
5f857575	375	MODULE_LICENSE("GPL v2");