[mirror_ubuntu-bionic-kernel.git] / drivers / net / phy / dp83867.c

/*
 * Driver for the Texas Instruments DP83867 PHY
 *
 * Copyright (C) 2015 Texas Instruments Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/ethtool.h>
#include <linux/kernel.h>
#include <linux/mii.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>

#include <dt-bindings/net/ti-dp83867.h>

#define DP83867_PHY_ID		0x2000a231
#define DP83867_DEVADDR		0x1f

#define MII_DP83867_PHYCTRL	0x10
#define MII_DP83867_MICR	0x12
#define MII_DP83867_ISR		0x13
#define DP83867_CTRL		0x1f
#define DP83867_CFG3		0x1e

/* Extended Registers */
#define DP83867_CFG4            0x0031
#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)

#define DP83867_RGMIICTL	0x0032
#define DP83867_STRAP_STS1	0x006E
#define DP83867_RGMIIDCTL	0x0086
#define DP83867_IO_MUX_CFG	0x0170
#define DP83867_10M_SGMII_CFG   0x016F
#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)

#define DP83867_SW_RESET	BIT(15)
#define DP83867_SW_RESTART	BIT(14)

/* MICR Interrupt bits */
#define MII_DP83867_MICR_AN_ERR_INT_EN		BIT(15)
#define MII_DP83867_MICR_SPEED_CHNG_INT_EN	BIT(14)
#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN	BIT(13)
#define MII_DP83867_MICR_PAGE_RXD_INT_EN	BIT(12)
#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN	BIT(11)
#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN	BIT(10)
#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN	BIT(8)
#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN	BIT(4)
#define MII_DP83867_MICR_WOL_INT_EN		BIT(3)
#define MII_DP83867_MICR_XGMII_ERR_INT_EN	BIT(2)
#define MII_DP83867_MICR_POL_CHNG_INT_EN	BIT(1)
#define MII_DP83867_MICR_JABBER_INT_EN		BIT(0)

/* RGMIICTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_EN		BIT(1)
#define DP83867_RGMII_RX_CLK_DELAY_EN		BIT(0)

/* STRAP_STS1 bits */
#define DP83867_STRAP_STS1_RESERVED		BIT(11)

/* PHY CTRL bits */
#define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
#define DP83867_PHYCR_FIFO_DEPTH_MASK		(3 << 14)
#define DP83867_PHYCR_RESERVED_MASK		BIT(11)

/* RGMIIDCTL bits */
#define DP83867_RGMII_TX_CLK_DELAY_SHIFT	4

/* IO_MUX_CFG bits */
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL	0x1f

#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX	0x0
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN	0x1f

/* CFG3 bits */
#define DP83867_CFG3_INT_OE			BIT(7)
#define DP83867_CFG3_ROBUST_AUTO_MDIX		BIT(9)

/* CFG4 bits */
#define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)

enum {
	DP83867_PORT_MIRROING_KEEP,
	DP83867_PORT_MIRROING_EN,
	DP83867_PORT_MIRROING_DIS,
};

struct dp83867_private {
	int rx_id_delay;
	int tx_id_delay;
	int fifo_depth;
	int io_impedance;
	int port_mirroring;
	bool rxctrl_strap_quirk;
};

static int dp83867_ack_interrupt(struct phy_device *phydev)
{
	int err = phy_read(phydev, MII_DP83867_ISR);

	if (err < 0)
		return err;

	return 0;
}

static int dp83867_config_intr(struct phy_device *phydev)
{
	int micr_status;

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
		micr_status = phy_read(phydev, MII_DP83867_MICR);
		if (micr_status < 0)
			return micr_status;

		micr_status |=
			(MII_DP83867_MICR_AN_ERR_INT_EN |
			MII_DP83867_MICR_SPEED_CHNG_INT_EN |
			MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
			MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
			MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
			MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);

		return phy_write(phydev, MII_DP83867_MICR, micr_status);
	}

	micr_status = 0x0;
	return phy_write(phydev, MII_DP83867_MICR, micr_status);
}

static int dp83867_config_port_mirroring(struct phy_device *phydev)
{
	struct dp83867_private *dp83867 =
		(struct dp83867_private *)phydev->priv;
	u16 val;

	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);

	if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
		val |= DP83867_CFG4_PORT_MIRROR_EN;
	else
		val &= ~DP83867_CFG4_PORT_MIRROR_EN;

	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);

	return 0;
}

#ifdef CONFIG_OF_MDIO
static int dp83867_of_init(struct phy_device *phydev)
{
	struct dp83867_private *dp83867 = phydev->priv;
	struct device *dev = &phydev->mdio.dev;
	struct device_node *of_node = dev->of_node;
	int ret;

	if (!of_node)
		return -ENODEV;

	dp83867->io_impedance = -EINVAL;

	/* Optional configuration */
	if (of_property_read_bool(of_node, "ti,max-output-impedance"))
		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
	else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;

	dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
					"ti,dp83867-rxctrl-strap-quirk");

	ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
				   &dp83867->rx_id_delay);
	if (ret &&
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
	     phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
		return ret;

	ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
				   &dp83867->tx_id_delay);
	if (ret &&
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
	     phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
		return ret;

	if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
		dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;

	if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
		dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;

	return of_property_read_u32(of_node, "ti,fifo-depth",
				   &dp83867->fifo_depth);
}
#else
static int dp83867_of_init(struct phy_device *phydev)
{
	return 0;
}
#endif /* CONFIG_OF_MDIO */

static int dp83867_config_init(struct phy_device *phydev)
{
	struct dp83867_private *dp83867;
	int ret, val, bs;
	u16 delay;

	if (!phydev->priv) {
		dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
				       GFP_KERNEL);
		if (!dp83867)
			return -ENOMEM;

		phydev->priv = dp83867;
		ret = dp83867_of_init(phydev);
		if (ret)
			return ret;
	} else {
		dp83867 = (struct dp83867_private *)phydev->priv;
	}

	/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
	if (dp83867->rxctrl_strap_quirk) {
		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
		val &= ~BIT(7);
		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
	}

	if (phy_interface_is_rgmii(phydev)) {
		val = phy_read(phydev, MII_DP83867_PHYCTRL);
		if (val < 0)
			return val;
		val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
		val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);

		/* The code below checks if "port mirroring" N/A MODE4 has been
		 * enabled during power on bootstrap.
		 *
		 * Such N/A mode enabled by mistake can put PHY IC in some
		 * internal testing mode and disable RGMII transmission.
		 *
		 * In this particular case one needs to check STRAP_STS1
		 * register's bit 11 (marked as RESERVED).
		 */

		bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
		if (bs & DP83867_STRAP_STS1_RESERVED)
			val &= ~DP83867_PHYCR_RESERVED_MASK;

		ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
		if (ret)
			return ret;

		/* Set up RGMII delays */
		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
			val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
			val |= DP83867_RGMII_TX_CLK_DELAY_EN;

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
			val |= DP83867_RGMII_RX_CLK_DELAY_EN;

		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);

		delay = (dp83867->rx_id_delay |
			(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));

		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
			      delay);

		if (dp83867->io_impedance >= 0) {
			val = phy_read_mmd(phydev, DP83867_DEVADDR,
					   DP83867_IO_MUX_CFG);

			val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
			val |= dp83867->io_impedance &
			       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;

			phy_write_mmd(phydev, DP83867_DEVADDR,
				      DP83867_IO_MUX_CFG, val);
		}
	}

	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
		/* For support SPEED_10 in SGMII mode
		 * DP83867_10M_SGMII_RATE_ADAPT bit
		 * has to be cleared by software. That
		 * does not affect SPEED_100 and
		 * SPEED_1000.
		 */
		val = phy_read_mmd(phydev, DP83867_DEVADDR,
				   DP83867_10M_SGMII_CFG);
		val &= ~DP83867_10M_SGMII_RATE_ADAPT_MASK;
		ret = phy_write_mmd(phydev, DP83867_DEVADDR,
				    DP83867_10M_SGMII_CFG, val);

		if (ret)
			return ret;

		/* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
		 * are 01). That is not enough to finalize autoneg on some
		 * devices. Increase this timer duration to maximum 16ms.
		 */
		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
		val &= ~DP83867_CFG4_SGMII_ANEG_MASK;
		val |= DP83867_CFG4_SGMII_ANEG_TIMER_16MS;
		ret = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);

		if (ret)
			return ret;
	}

	val = phy_read(phydev, DP83867_CFG3);
	/* Enable Interrupt output INT_OE in CFG3 register */
	if (phy_interrupt_is_valid(phydev))
		val |= DP83867_CFG3_INT_OE;

	val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
	phy_write(phydev, DP83867_CFG3, val);

	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
		dp83867_config_port_mirroring(phydev);

	return 0;
}

static int dp83867_phy_reset(struct phy_device *phydev)
{
	int err;

	err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
	if (err < 0)
		return err;

	return dp83867_config_init(phydev);
}

static struct phy_driver dp83867_driver[] = {
	{
		.phy_id		= DP83867_PHY_ID,
		.phy_id_mask	= 0xfffffff0,
		.name		= "TI DP83867",
		.features	= PHY_GBIT_FEATURES,
		.flags		= PHY_HAS_INTERRUPT,

		.config_init	= dp83867_config_init,
		.soft_reset	= dp83867_phy_reset,

		/* IRQ related */
		.ack_interrupt	= dp83867_ack_interrupt,
		.config_intr	= dp83867_config_intr,

		.config_aneg	= genphy_config_aneg,
		.read_status	= genphy_read_status,
		.suspend	= genphy_suspend,
		.resume		= genphy_resume,
	},
};
module_phy_driver(dp83867_driver);

static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
	{ DP83867_PHY_ID, 0xfffffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, dp83867_tbl);

MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
MODULE_LICENSE("GPL");
Commit	Line	Data
2a10154a DM	1	/*
	2	* Driver for the Texas Instruments DP83867 PHY
	3	*
	4	* Copyright (C) 2015 Texas Instruments Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/ethtool.h>
	17	#include <linux/kernel.h>
	18	#include <linux/mii.h>
	19	#include <linux/module.h>
	20	#include <linux/of.h>
	21	#include <linux/phy.h>
	22
	23	#include <dt-bindings/net/ti-dp83867.h>
	24
	25	#define DP83867_PHY_ID 0x2000a231
	26	#define DP83867_DEVADDR 0x1f
	27
	28	#define MII_DP83867_PHYCTRL 0x10
	29	#define MII_DP83867_MICR 0x12
	30	#define MII_DP83867_ISR 0x13
	31	#define DP83867_CTRL 0x1f
5ca7d1ca	32	#define DP83867_CFG3 0x1e
2a10154a DM	33
2a10154a DM	34	/* Extended Registers */
fc6d39c3	35	#define DP83867_CFG4 0x0031
99ea7dda MU	36	#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) \| BIT(6))
	37	#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
	38	#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
	39	#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
	40	#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
	41
2a10154a	42	#define DP83867_RGMIICTL 0x0032
ac6e058b	43	#define DP83867_STRAP_STS1 0x006E
2a10154a	44	#define DP83867_RGMIIDCTL 0x0086
ed838fe9	45	#define DP83867_IO_MUX_CFG 0x0170
0d4eb036 MU	46	#define DP83867_10M_SGMII_CFG 0x016F
0d4eb036 MU	47	#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
2a10154a DM	48
	49	#define DP83867_SW_RESET BIT(15)
	50	#define DP83867_SW_RESTART BIT(14)
	51
	52	/* MICR Interrupt bits */
	53	#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
	54	#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
	55	#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
	56	#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
	57	#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
	58	#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
	59	#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
	60	#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
	61	#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
	62	#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
	63	#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
	64	#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
	65
	66	/* RGMIICTL bits */
	67	#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
	68	#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
	69
ac6e058b LM	70	/* STRAP_STS1 bits */
	71	#define DP83867_STRAP_STS1_RESERVED BIT(11)
	72
2a10154a DM	73	/* PHY CTRL bits */
2a10154a DM	74	#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
b291c418	75	#define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
ac6e058b	76	#define DP83867_PHYCR_RESERVED_MASK BIT(11)
2a10154a DM	77
	78	/* RGMIIDCTL bits */
	79	#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
	80
ed838fe9 M	81	/* IO_MUX_CFG bits */
	82	#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
	83
	84	#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
	85	#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
	86
edb3b17d GS	87	/* CFG3 bits */
	88	#define DP83867_CFG3_INT_OE BIT(7)
	89	#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
	90
fc6d39c3 LM	91	/* CFG4 bits */
	92	#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
	93
	94	enum {
	95	DP83867_PORT_MIRROING_KEEP,
	96	DP83867_PORT_MIRROING_EN,
	97	DP83867_PORT_MIRROING_DIS,
	98	};
	99
2a10154a DM	100	struct dp83867_private {
	101	int rx_id_delay;
	102	int tx_id_delay;
	103	int fifo_depth;
ed838fe9	104	int io_impedance;
fc6d39c3	105	int port_mirroring;
37144476	106	bool rxctrl_strap_quirk;
2a10154a DM	107	};
	108
	109	static int dp83867_ack_interrupt(struct phy_device *phydev)
	110	{
	111	int err = phy_read(phydev, MII_DP83867_ISR);
	112
	113	if (err < 0)
	114	return err;
	115
	116	return 0;
	117	}
	118
	119	static int dp83867_config_intr(struct phy_device *phydev)
	120	{
	121	int micr_status;
	122
	123	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
	124	micr_status = phy_read(phydev, MII_DP83867_MICR);
	125	if (micr_status < 0)
	126	return micr_status;
	127
	128	micr_status \|=
	129	(MII_DP83867_MICR_AN_ERR_INT_EN \|
	130	MII_DP83867_MICR_SPEED_CHNG_INT_EN \|
5ca7d1ca GS	131	MII_DP83867_MICR_AUTONEG_COMP_INT_EN \|
5ca7d1ca GS	132	MII_DP83867_MICR_LINK_STS_CHNG_INT_EN \|
2a10154a DM	133	MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN \|
	134	MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
	135
	136	return phy_write(phydev, MII_DP83867_MICR, micr_status);
	137	}
	138
	139	micr_status = 0x0;
	140	return phy_write(phydev, MII_DP83867_MICR, micr_status);
	141	}
	142
fc6d39c3 LM	143	static int dp83867_config_port_mirroring(struct phy_device *phydev)
	144	{
	145	struct dp83867_private *dp83867 =
	146	(struct dp83867_private *)phydev->priv;
	147	u16 val;
	148
a6d99fcd	149	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
fc6d39c3 LM	150
	151	if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
	152	val \|= DP83867_CFG4_PORT_MIRROR_EN;
	153	else
	154	val &= ~DP83867_CFG4_PORT_MIRROR_EN;
	155
a6d99fcd	156	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
fc6d39c3 LM	157
	158	return 0;
	159	}
	160
2a10154a DM	161	#ifdef CONFIG_OF_MDIO
	162	static int dp83867_of_init(struct phy_device *phydev)
	163	{
	164	struct dp83867_private *dp83867 = phydev->priv;
e5a03bfd	165	struct device *dev = &phydev->mdio.dev;
2a10154a DM	166	struct device_node *of_node = dev->of_node;
	167	int ret;
	168
7bf9ae01	169	if (!of_node)
2a10154a DM	170	return -ENODEV;
2a10154a DM	171
ed838fe9 M	172	dp83867->io_impedance = -EINVAL;
	173
	174	/* Optional configuration */
	175	if (of_property_read_bool(of_node, "ti,max-output-impedance"))
	176	dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
	177	else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
	178	dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
	179
37144476 MK	180	dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
	181	"ti,dp83867-rxctrl-strap-quirk");
	182
ac7ba51c	183	ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
2a10154a	184	&dp83867->rx_id_delay);
34c55cf2 KM	185	if (ret &&
	186	(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID \|\|
	187	phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
2a10154a DM	188	return ret;
2a10154a DM	189
ac7ba51c	190	ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
2a10154a	191	&dp83867->tx_id_delay);
34c55cf2 KM	192	if (ret &&
	193	(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID \|\|
	194	phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
2a10154a DM	195	return ret;
2a10154a DM	196
fc6d39c3 LM	197	if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
	198	dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
	199
	200	if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
	201	dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
	202
9267135c	203	return of_property_read_u32(of_node, "ti,fifo-depth",
2a10154a	204	&dp83867->fifo_depth);
2a10154a DM	205	}
	206	#else
	207	static int dp83867_of_init(struct phy_device *phydev)
	208	{
	209	return 0;
	210	}
	211	#endif /* CONFIG_OF_MDIO */
	212
	213	static int dp83867_config_init(struct phy_device *phydev)
	214	{
	215	struct dp83867_private *dp83867;
ac6e058b	216	int ret, val, bs;
b291c418	217	u16 delay;
2a10154a DM	218
2a10154a DM	219	if (!phydev->priv) {
e5a03bfd	220	dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
2a10154a DM	221	GFP_KERNEL);
	222	if (!dp83867)
	223	return -ENOMEM;
	224
	225	phydev->priv = dp83867;
	226	ret = dp83867_of_init(phydev);
	227	if (ret)
	228	return ret;
	229	} else {
	230	dp83867 = (struct dp83867_private *)phydev->priv;
	231	}
	232
37144476 MK	233	/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
	234	if (dp83867->rxctrl_strap_quirk) {
	235	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
	236	val &= ~BIT(7);
	237	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
	238	}
	239
2a10154a	240	if (phy_interface_is_rgmii(phydev)) {
b291c418 SH	241	val = phy_read(phydev, MII_DP83867_PHYCTRL);
	242	if (val < 0)
	243	return val;
	244	val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
	245	val \|= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
ac6e058b LM	246
	247	/* The code below checks if "port mirroring" N/A MODE4 has been
	248	* enabled during power on bootstrap.
	249	*
	250	* Such N/A mode enabled by mistake can put PHY IC in some
	251	* internal testing mode and disable RGMII transmission.
	252	*
	253	* In this particular case one needs to check STRAP_STS1
	254	* register's bit 11 (marked as RESERVED).
	255	*/
	256
a6d99fcd	257	bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
ac6e058b LM	258	if (bs & DP83867_STRAP_STS1_RESERVED)
	259	val &= ~DP83867_PHYCR_RESERVED_MASK;
	260
b291c418	261	ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
2a10154a DM	262	if (ret)
2a10154a DM	263	return ret;
2a10154a	264
0c745010	265	/* Set up RGMII delays */
a6d99fcd	266	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
2a10154a DM	267
	268	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
	269	val \|= (DP83867_RGMII_TX_CLK_DELAY_EN \| DP83867_RGMII_RX_CLK_DELAY_EN);
	270
	271	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
	272	val \|= DP83867_RGMII_TX_CLK_DELAY_EN;
	273
	274	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
	275	val \|= DP83867_RGMII_RX_CLK_DELAY_EN;
	276
a6d99fcd	277	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
2a10154a DM	278
	279	delay = (dp83867->rx_id_delay \|
	280	(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
	281
a6d99fcd RK	282	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
a6d99fcd RK	283	delay);
ed838fe9 M	284
ed838fe9 M	285	if (dp83867->io_impedance >= 0) {
a6d99fcd RK	286	val = phy_read_mmd(phydev, DP83867_DEVADDR,
a6d99fcd RK	287	DP83867_IO_MUX_CFG);
ed838fe9 M	288
	289	val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
	290	val \|= dp83867->io_impedance &
	291	DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
	292
a6d99fcd RK	293	phy_write_mmd(phydev, DP83867_DEVADDR,
a6d99fcd RK	294	DP83867_IO_MUX_CFG, val);
ed838fe9	295	}
2a10154a DM	296	}
2a10154a DM	297
0d4eb036 MU	298	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
	299	/* For support SPEED_10 in SGMII mode
	300	* DP83867_10M_SGMII_RATE_ADAPT bit
	301	* has to be cleared by software. That
	302	* does not affect SPEED_100 and
	303	* SPEED_1000.
	304	*/
	305	val = phy_read_mmd(phydev, DP83867_DEVADDR,
	306	DP83867_10M_SGMII_CFG);
	307	val &= ~DP83867_10M_SGMII_RATE_ADAPT_MASK;
	308	ret = phy_write_mmd(phydev, DP83867_DEVADDR,
	309	DP83867_10M_SGMII_CFG, val);
	310
	311	if (ret)
	312	return ret;
99ea7dda MU	313
	314	/* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
	315	* are 01). That is not enough to finalize autoneg on some
	316	* devices. Increase this timer duration to maximum 16ms.
	317	*/
	318	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
	319	val &= ~DP83867_CFG4_SGMII_ANEG_MASK;
	320	val \|= DP83867_CFG4_SGMII_ANEG_TIMER_16MS;
	321	ret = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
	322
	323	if (ret)
	324	return ret;
0d4eb036 MU	325	}
0d4eb036 MU	326
edb3b17d	327	val = phy_read(phydev, DP83867_CFG3);
5ca7d1ca	328	/* Enable Interrupt output INT_OE in CFG3 register */
edb3b17d GS	329	if (phy_interrupt_is_valid(phydev))
	330	val \|= DP83867_CFG3_INT_OE;
	331
	332	val \|= DP83867_CFG3_ROBUST_AUTO_MDIX;
	333	phy_write(phydev, DP83867_CFG3, val);
5ca7d1ca	334
fc6d39c3 LM	335	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
	336	dp83867_config_port_mirroring(phydev);
	337
2a10154a DM	338	return 0;
	339	}
	340
	341	static int dp83867_phy_reset(struct phy_device *phydev)
	342	{
	343	int err;
	344
	345	err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
	346	if (err < 0)
	347	return err;
	348
	349	return dp83867_config_init(phydev);
	350	}
	351
	352	static struct phy_driver dp83867_driver[] = {
	353	{
	354	.phy_id = DP83867_PHY_ID,
	355	.phy_id_mask = 0xfffffff0,
	356	.name = "TI DP83867",
	357	.features = PHY_GBIT_FEATURES,
	358	.flags = PHY_HAS_INTERRUPT,
	359
	360	.config_init = dp83867_config_init,
	361	.soft_reset = dp83867_phy_reset,
	362
	363	/* IRQ related */
	364	.ack_interrupt = dp83867_ack_interrupt,
	365	.config_intr = dp83867_config_intr,
	366
	367	.config_aneg = genphy_config_aneg,
	368	.read_status = genphy_read_status,
	369	.suspend = genphy_suspend,
	370	.resume = genphy_resume,
2a10154a DM	371	},
	372	};
	373	module_phy_driver(dp83867_driver);
	374
	375	static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
	376	{ DP83867_PHY_ID, 0xfffffff0 },
	377	{ }
	378	};
	379
	380	MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
	381
	382	MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
	383	MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
	384	MODULE_LICENSE("GPL");